From rminnich at lanl.gov  Tue Aug  1 00:39:46 2006
From: rminnich at lanl.gov (Ronald G. Minnich)
Date: Mon, 31 Jul 2006 16:39:46 -0600 (MDT)
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
Message-ID: <9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>

>> 5. ./buildtarget bitworks/ims
>> 6. cd bitworks/ims/ims
>> 7. make
>
> IMS uses a NSC pc87351 for the super IO.
>
> Make sure you change the SuperIO to match your board.  Or you won't
> get any output.
>
> Remember that if it "works" all you are going to get is a dump of the
> SPD, some messages on copying and jumping to RAM and then it will
> crash.  Everthing else is  on the ToDo list. :)
>
>> 9. sudo ../../../util/flashrom/flashrom -w linuxbios.rom
>>
>> Calibrating delay loop... ok
>> No LinuxBIOS table found.
>> No EEPROM/flash device found.


I'm guessing the write enable did not happen.

you can'd ID flash without write cycles working.

ron



From stepan at coresystems.de  Tue Aug  1 00:53:11 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 1 Aug 2006 00:53:11 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
Message-ID: <20060731225311.GA22634@coresystems.de>

* Richard Smith <smithbone at gmail.com> [060731 20:46]:
> I'm spoiled.  We have EEPROM/flash programmers.  So I've actually
> never used flashrom.  But 29f04b have been suported for a while.
> 
> Try it with the -v option so we can see what the return values are
> from the device check.

It's -V ... -v is verify.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Tue Aug  1 01:36:23 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Aug 2006 01:36:23 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
Message-ID: <20060731233623.GA7869@aragorn>

Hi,

On Mon, Jul 31, 2006 at 04:39:46PM -0600, Ronald G. Minnich wrote:
> I'm guessing the write enable did not happen.
> 
> you can'd ID flash without write cycles working.

How do I find out whether it happened and how can I fix it if it didn't?

Attached is the output of ./flashrom -V. It's the same for both the
AM2* and W49* chips. I had no luck with flash_rom from V1, either.
The output of that is attached, too.


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Calibrating delay loop... Setting up microsecond timing loop
128M loops per second
ok
No LinuxBIOS table found.
Trying Am29F040B, 512 KB
probe_29f040b: id1 0xff, id2 0xff
Trying Am29F016D, 2048 KB
probe_29f040b: id1 0xff, id2 0xff
Trying At29C040A, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying Mx29f002, 256 KB
probe_29f002: id1 0xff, id2 0xff
Trying SST29EE020A, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST28SF040A, 512 KB
probe_28sf040: id1 0xff, id2 0xff
Trying SST39SF020A, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST39VF020, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF040B, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF040, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF080A, 1024 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF002A/B, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF003A/B, 384 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF004A/B, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF008A, 1024 KB
probe_jedec: id1 0xff, id2 0xff
Trying Pm49FL002, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying Pm49FL004, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying W29C011, 128 KB
probe_jedec: id1 0xff, id2 0xff
Trying W29C020C, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W49F002U, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W49V002A, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W49V002FA, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W39V040A, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying M29F040B, 512 KB
probe_29f040b: id1 0xff, id2 0xff
Trying M29F400BT, 512 KB
probe_m29f400bt: id1 0xff, id2 0xff
Trying 82802ab, 512 KB
probe_82802ab: id1 0xff, id2 0xff
Trying 82802ac, 1024 KB
probe_82802ab: id1 0xff, id2 0xff
Trying F49B002UA, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying LHF00L04, 1024 KB
probe_lhf00l04: id1 0xff, id2 0xff
No EEPROM/flash device found.
-------------- next part --------------
Calibrating timer since microsleep sucks ... takes a second
Setting up microsecond timing loop
OK, calibrated, now do the deed
Trying Am29F040B, 512 KB
probe_29f040b: id1 0xff, id2 0xff
Trying At29C040A, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying Mx29f002, 256 KB
probe_29f002: id1 255, id2 255
Trying SST29EE020A, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST28SF040A, 512 KB
probe_28sf040: id1 0xff, id2 0xff
Trying SST39SF020A, 256 KB
probe_39sf020: id1 0xff, id2 0xff
Trying SST39VF020, 256 KB
probe_39sf020: id1 0xff, id2 0xff
Trying W29C011, 128 KB
probe_jedec: id1 0xff, id2 0xff
Trying W29C020C, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W49F002U, 256 KB
probe_49f002: id1 0xff, id2 0xff
Trying M29F400BT, 512 KB
probe_m29f400bt: id1 0xff, id2 0xff
Trying 82802ab, 512 KB
probe_82802ab: id1 0xff, id2 0xff
Trying 82802ac, 1024 KB
probe_82802ab: id1 0xff, id2 0xff
Trying MD-2802 (M-Systems DiskOnChip Millennium Module), 8 KB
probe_md2802:
probe_md2802: *******************************
probe_md2802: * THIS IS A PRE ALPHA VERSION *
probe_md2802: * IN THE DEVELOPEMENT *********
probe_md2802: * PROCESS RIGHT NOW. **********
probe_md2802: *******************************
probe_md2802: * IF YOU ARE NOT A DEVELOPER **
probe_md2802: * THEN DO NOT TRY TO READ OR **
probe_md2802: * WRITE TO THIS DEVICE ********
probe_md2802: *******************************
probe_md2802:
probe_md2802: switching off reset mode ...
probe_md2802: switching off reset mode ... done
probe_md2802:
probe_md2802: switching off write protection ...
probe_md2802: switching off write protection ... done
probe_md2802:
probe_md2802: IPL_0x0000: 0xff
probe_md2802: IPL_0x0001: 0xff
probe_md2802: IPL_0x0002: 0xff
probe_md2802: IPL_0x0003: 0xff
probe_md2802:
probe_md2802: ChipID: 0xff
probe_md2802: DOCStatus: 0xff
probe_md2802: FloorSelect: 0xff
probe_md2802: CDSNControl: 0xff
probe_md2802: CDSNDeviceSelect: 0xff
probe_md2802: ECCConfiguration: 0xff
probe_md2802: CDSNSlowIO: 0xff
probe_md2802: ECCSyndrome0: 0xff
probe_md2802: ECCSyndrome1: 0xff
probe_md2802: ECCSyndrome2: 0xff
probe_md2802: ECCSyndrome3: 0xff
probe_md2802: ECCSyndrome4: 0xff
probe_md2802: ECCSyndrome5: 0xff
probe_md2802: AliasResolution: 0xff
probe_md2802: ConfigurationInput: 0xff
probe_md2802: ReadPipelineInitialization: 0xff
probe_md2802: LastDataRead: 0xff
probe_md2802:
probe_md2802: checking ECCConfiguration toggle bit
probe_md2802: 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01
probe_md2802: toggle result: 5/5
EEPROM not found
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060801/6a684d24/attachment.sig>

From bari at onelabs.com  Tue Aug  1 01:43:35 2006
From: bari at onelabs.com (Bari Ari)
Date: Mon, 31 Jul 2006 18:43:35 -0500
Subject: [LinuxBIOS] Intel Asks for Opinions on EFI,
	BIOS/Firmware in a Survey
Message-ID: <44CE95A7.20904@onelabs.com>

Intel has a BIOS survey at:  http://developer.intel.com/sites/developer/

Take the BIOS/Firmware Survey. Give us your opinions on BIOS/Firmware 
<http://poll.onsurvey.net/istu/61030C1/dnc.asp>

Here's a way to send a message to Intel about what BIOS developers think 
of EFI.







From stepan at coresystems.de  Tue Aug  1 01:41:51 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 1 Aug 2006 01:41:51 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060731233623.GA7869@aragorn>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
Message-ID: <20060731234151.GA25670@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060801 01:36]:
> > you can'd ID flash without write cycles working.
> 
> How do I find out whether it happened and how can I fix it if it didn't?
 
They don't work. You read back ff all the time.

> Attached is the output of ./flashrom -V. It's the same for both the
> AM2* and W49* chips. I had no luck with flash_rom from V1, either.
> The output of that is attached, too.
 
I assume it doesnt even try to enable write cycles. This should be
warned in flashrom with an appropriate message to fix it.

ie on Epia it would say:
Enabling flash write on VT8235...OK


Can you send around an lspci -n ?


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Tue Aug  1 01:43:03 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 1 Aug 2006 01:43:03 +0200
Subject: [LinuxBIOS] Winbond W39V040BPZ support in flash_rom?
In-Reply-To: <20060731144511.25800@gmx.net>
References: <20060729191320.292640@gmx.net>
	<20060729201454.GA30947@coresystems.de>
	<20060731144511.25800@gmx.net>
Message-ID: <20060731234303.GA27948@coresystems.de>

Applied.

* Carl-Daniel U. Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060731 16:45]:
> With the following (whitespace-damaged) patch
> 
> Index: flash.h
> ===================================================================
> --- flash.h     (Revision 2350)
> +++ flash.h     (Arbeitskopie)
> @@ -59,6 +59,7 @@
>  #define W_29C011          0xC1 /* Winbond w29c011 device code */
>  #define W_29C020C         0x45 /* Winbond w29c020c device code */
>  #define W_39V040A         0x3D /* Winbond w39v040a device code */
> +#define W_39V040B         0x54 /* Winbond w39v040b device code */
>  #define W_49F002U         0x0B /* Winbond w49F002u device code */
>  #define W_49V002A         0xB0  /* Winbond W49V002A device code */
>  #define W_49V002FA        0x32  /* Winbond W49V002FA device code */
> Index: flash_enable.c
> ===================================================================
> --- flash_enable.c      (Revision 2350)
> +++ flash_enable.c      (Arbeitskopie)
> @@ -396,6 +396,7 @@
>         {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
>         // this fallthrough looks broken.
>          {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, // LPC
> +        {0x10de, 0x0261, "NVIDIA C51", enable_flash_ck804},
>          {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, // Pro
>          {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, // Slave, should not be here, to fix known bug for A01.
>         {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, // ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80)
> Index: flashchips.c
> ===================================================================
> --- flashchips.c        (Revision 2350)
> +++ flashchips.c        (Arbeitskopie)
> @@ -88,6 +88,8 @@
>          probe_jedec,   erase_chip_jedec, write_49f002, NULL},
>         {"W39V040A",    WINBOND_ID,     W_39V040A,      NULL, 512, 64*1024,
>          probe_jedec,   erase_chip_jedec, write_39sf020, NULL},
> +       {"W39V040B",    WINBOND_ID,     W_39V040B,      NULL, 512, 64*1024,
> +        probe_jedec,   erase_chip_jedec, write_39sf020, NULL},
>         {"M29F040B",    ST_ID,          ST_M29F040B,    NULL, 512, 64 * 1024,
>          probe_29f040b, erase_29f040b,  write_29f040b,  NULL},
>         {"M29F400BT",   ST_ID,          ST_M29F400BT,   NULL, 512, 64 * 1024,
> 
> 
> I get this result:
> # LinuxBIOSv2/util/flashrom/flashrom 
> Calibrating delay loop... ok
> No LinuxBIOS table found.
> Enabling flash write on NVIDIA C51...OK
> W39V040B found at physical address: 0xfff80000
> Flash part is W39V040B
> OK, only ENABLING flash write, but NOT FLASHING.
> 
> There is one small problem: I depend on this board very much since my laptop is in repair. So I can't test whether writing would work. The only difference between W39V040B (new) and W39V040A (supported) ist that W39V040B is a LPC chip instead of FWH. I don't know whether that matters for flashing.
> 
> Regards,
> Carl-Daniel
> -- 
> 
> 
> Echte DSL-Flatrate dauerhaft f?r 0,- Euro*. Nur noch kurze Zeit!
> "Feel free" mit GMX DSL: http://www.gmx.net/de/go/dsl
> 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Tue Aug  1 01:49:49 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Aug 2006 01:49:49 +0200
Subject: [LinuxBIOS] PATCH: flashrom documentation fixes.
Message-ID: <20060731234949.GB7869@aragorn>

Hi,

here's a small patch which fixes minor issues in the flashrom docs:

 * Made the README, manpage, and ./flashrom -h output the same things
 * Added some missing options to the "usage:" one-liner
 * Aligned spaces in ./flashrom -h output
 * Added explicit license to the manpage (GPL).


HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: flash_rom.c
===================================================================
--- flash_rom.c	(revision 2349)
+++ flash_rom.c	(working copy)
@@ -145,22 +145,24 @@
 
 void usage(const char *name)
 {
-	printf("usage: %s [-rwvE] [-V] [-c chipname] [-s exclude_start] [-e exclude_end] [file]\n", name);
-	printf("   -r | --read:   read flash and save into file\n"
-	       "   -w | --write:  write file into flash (default when file is specified)\n"
-	       "   -v | --verify: verify flash against file\n"
-	       "   -E | --erase: Erase flash device\n"
-	       "   -V | --verbose: more verbose output\n\n"
-	       "   -c | --chip <chipname>: probe only for specified flash chip\n"
-	       "   -s | --estart <addr>: exclude start position\n"
-	       "   -e | --eend <addr>: exclude end postion\n"
+	printf("usage: %s [-rwvEVfh] [-c chipname] [-s exclude_start]\n", name);
+	printf("       [-e exclude_end] [-m vendor:part] [-l file.layout] [-i imagename] [file]\n");
+	printf("   -r | --read:                    read flash and save into file\n"
+	       "   -w | --write:                   write file into flash (default when\n"
+	       "                                   file is specified)\n"
+	       "   -v | --verify:                  verify flash against file\n"
+	       "   -E | --erase:                   erase flash device\n"
+	       "   -V | --verbose:                 more verbose output\n"
+	       "   -c | --chip <chipname>:         probe only for specified flash chip\n"
+	       "   -s | --estart <addr>:           exclude start position\n"
+	       "   -e | --eend <addr>:             exclude end postion\n"
 	       "   -m | --mainboard <vendor:part>: override mainboard settings\n"
-	       "   -f | --force: force write without checking image\n"
-	       "   -l | --layout <file.layout>: read rom layout from file\n"
-	       "   -i | --image <name>: only flash image name from flash layout\n"
+	       "   -f | --force:                   force write without checking image\n"
+	       "   -l | --layout <file.layout>:    read rom layout from file\n"
+	       "   -i | --image <name>:            only flash image name from flash layout\n"
 	       "\n"
 	       " If no file is specified, then all that happens\n"
-	       " is that flash info is dumped\n\n");
+	       " is that flash info is dumped.\n\n");
 	exit(1);
 }
 
Index: README
===================================================================
--- README	(revision 2349)
+++ README	(working copy)
@@ -13,21 +13,21 @@
 usage
 -----
 
-usage: ./flashrom [-rwvE] [-V] [-c chipname] 
-                           [-s exclude_start] [-e exclude_end] [file]
-
-   -r | --read:   read flash and save into file
-   -w | --write:  write file into flash (default when file is specified)
-   -v | --verify: verify flash against file
-   -E | --erase: Erase flash device
-   -V | --verbose: more verbose output
-
-   -c | --chip <chipname>: probe only for specified flash chip
-   -s | --estart <addr>: exclude start position
-   -e | --eend <addr>: exclude end postion
+usage: ./flashrom [-rwvEVfh] [-c chipname] [-s exclude_start]
+       [-e exclude_end] [-m vendor:part] [-l file.layout] [-i imagename] [file]
+   -r | --read:                    read flash and save into file
+   -w | --write:                   write file into flash (default when
+                                   file is specified)
+   -v | --verify:                  verify flash against file
+   -E | --erase:                   erase flash device
+   -V | --verbose:                 more verbose output
+   -c | --chip <chipname>:         probe only for specified flash chip
+   -s | --estart <addr>:           exclude start position
+   -e | --eend <addr>:             exclude end postion
    -m | --mainboard <vendor:part>: override mainboard settings
-   -l | --layout <file.layout>: read rom layout from file
-   -i | --image <name>: only flash image name from flash layout
+   -f | --force:                   force write without checking image
+   -l | --layout <file.layout>:    read rom layout from file
+   -i | --image <name>:            only flash image name from flash layout
 
  If no file is specified, then all that happens
  is that flash info is dumped and the flash chip is set to writable.
Index: flashrom.1
===================================================================
--- flashrom.1	(revision 2349)
+++ flashrom.1	(working copy)
@@ -1,3 +1,5 @@
+.\" Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>.
+.\" This manpage is licensed under the terms of the GNU GPL.
 .TH FLASHROM 1 "July 26, 2006"
 .SH NAME
 flashrom \- the universal LinuxBIOS flash utility
@@ -2,5 +4,4 @@
 .SH SYNOPSIS
-.B flashrom \fR[\fB\-rwvEVflih\fR] [\fB\-c\fR chipname]
-         [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
-         [\fB-m\fR vendor:part] [file]
+.B flashrom \fR[\fB\-rwvEVfh\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
+         [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
 .SH DESCRIPTION
@@ -42,7 +43,7 @@
 .B "\-f, \-\-force"
 Force write without checking image.
 .PP
-.B "\-l, \-\-layout"
+.B "\-l, \-\-layout" <layout.file>
 Read ROM layout from file.
 .PP
 .B "\-i, \-\-image" <name>
@@ -54,7 +55,7 @@
 .\".B "\-\-version"
 .\"Show version information and exit.
 .SH BUGS
-Please report any bugs at http://bugzilla.openbios.org/
+Please report any bugs at http://bugzilla.openbios.org/.
 .SH LICENCE
 .B flashrom
 is covered by the GNU General Public License (GPL).
@@ -63,11 +64,11 @@
 .SH COPYRIGHT
 2000 Silicon Integrated System Corporation
 .br
+2003 Niki W. Waibel
+.br
 2004 Tyan Corp
 .br
 2005-2006 coresystems GmbH
-.br
-2003 Niki W. Waibel
 .SH AUTHORS
 Yhlu <yinghai.lu at amd.com>
 .br
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060801/57098fab/attachment.sig>

From uwe at hermann-uwe.de  Tue Aug  1 01:57:18 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Aug 2006 01:57:18 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060731234151.GA25670@coresystems.de>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
Message-ID: <20060731235718.GC7869@aragorn>

Hi,

On Tue, Aug 01, 2006 at 01:41:51AM +0200, Stefan Reinauer wrote:
> They don't work. You read back ff all the time.

Yes, that's what I was guessing. It should return the vendor
and device ID (0xDA, 0x0B), correct?

Do the access times matter here? I have a W49F002U-12B, i.e. 120ns, according
to the datasheet.

 
> > Attached is the output of ./flashrom -V. It's the same for both the
> > AM2* and W49* chips. I had no luck with flash_rom from V1, either.
> > The output of that is attached, too.
>  
> I assume it doesnt even try to enable write cycles. This should be
> warned in flashrom with an appropriate message to fix it.
> 
> ie on Epia it would say:
> Enabling flash write on VT8235...OK

I haven't seen such a message here.

 
> Can you send around an lspci -n ?

Sure.

00:00.0 0600: 8086:7190 (rev 03)
00:01.0 0604: 8086:7191 (rev 03)
00:07.0 0601: 8086:7110 (rev 02)
00:07.1 0101: 8086:7111 (rev 01)
00:07.2 0c03: 8086:7112 (rev 01)
00:07.3 0680: 8086:7113 (rev 02)
01:00.0 0300: 1039:6326 (rev 0b)


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060801/6f677796/attachment.sig>

From info at coresystems.de  Tue Aug  1 02:15:30 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Tue, 01 Aug 2006 02:15:30 +0200
Subject: [LinuxBIOS] LinuxBIOS r2354 build changes
Message-ID: <E1G7hv0-0007yI-B8@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2354 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Add support for SST39SF040 and SST39SF010Aapply C.-D. Hailfinger's patch for Winbond part (untested)

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From rminnich at lanl.gov  Tue Aug  1 04:46:36 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 31 Jul 2006 20:46:36 -0600
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060731233623.GA7869@aragorn>
References: <20060731180409.GA13592@aragorn>	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
Message-ID: <44CEC08C.70001@lanl.gov>

Uwe Hermann wrote:

> How do I find out whether it happened and how can I fix it if it didn't?

you know it did not, but the fact that every single id1 and id2 is 0xff 
is a sign that something is really wrong.

You're going to have to do some more digging :-(

ron



From rminnich at lanl.gov  Tue Aug  1 05:21:30 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 31 Jul 2006 21:21:30 -0600
Subject: [LinuxBIOS] Intel Asks for Opinions on EFI,
 BIOS/Firmware in a Survey
In-Reply-To: <44CE95A7.20904@onelabs.com>
References: <44CE95A7.20904@onelabs.com>
Message-ID: <44CEC8BA.1040702@lanl.gov>

Bari Ari wrote:
> Intel has a BIOS survey at:  http://developer.intel.com/sites/developer/
> 
> Take the BIOS/Firmware Survey. Give us your opinions on BIOS/Firmware 
> <http://poll.onsurvey.net/istu/61030C1/dnc.asp>
> 
> Here's a way to send a message to Intel about what BIOS developers think 
> of EFI.
> 
> 
> 
> 
> 

I love advertisements concealed as polls:

Are you aware the industry is in the midst of moving from legacy BIOS to 
EFI/UEFI?

and there's no selections for linuxbios. What a joke.

It gets better:
"
EFI/UEFI:The EFI specification defines a new model for the interface 
between operating systems and platform firmware. The interface consists 
of data tables that contain platform-related information, plus boot and 
runtime service calls that are available to the operating system and its 
loader. Together, these provide a standard environment for booting an 
operating system and running pre-boot applications."


No mention of DRM hooks. hmm.

oh yeah, it's so great that we have to conceal an ad as a poll. What a 
winner.

and...
"Which company is leading the industry in terms of EFI/UEFI?"

There's no "I really don't care" button.

Betcha they want to pick intel.

This is great. These are "questions"
EFI/UEFI creates efficiency						
EFI/UEFI is flexible						
EFI/UEFI is scalable						
EFI/UEFI saves money						
EFI/UEFI saves time


Here's a dead giveaway:
Which CPU are you currently using?
	AMD
	Intel? Celeron
	Intel? Celeron D
	Intel? Celeron M
	Intel? Core? Duo Processors
	Intel? Itanium? 2
	Intel? Pentium D
	Intel? Pentium M
	Intel? Xeon?
	VIA


Since there's only one type of AMD cpu, right? And you only get *one* 
choice.

And, still better:
"
Would you like to be contacted to participate in further Intel related 
research activities?
	Yes - I would like to be contacted to participate in further Intel 
related research activities.
"

Wow, these guys are smooth, eh? I would never have guessed that this was 
a fake poll.

To be honest, I doubt very much what Intel cares about what people think 
of efi, but go ahead and take the poll -- you never know.

ron






From stepan at coresystems.de  Tue Aug  1 14:02:21 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 1 Aug 2006 14:02:21 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060731235718.GC7869@aragorn>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
Message-ID: <20060801120221.GA17269@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060801 01:57]:
> Yes, that's what I was guessing. It should return the vendor
> and device ID (0xDA, 0x0B), correct?
 
Yes, exactly.

> Do the access times matter here? I have a W49F002U-12B, i.e. 120ns, according
> to the datasheet.
 
If you replace a part, it should not be slower than the original one,
but I never saw problems due to access times, realy.
  
> > ie on Epia it would say:
> > Enabling flash write on VT8235...OK
> 
> I haven't seen such a message here.
> 
>  
> > Can you send around an lspci -n ?
> 
> Sure.
> 
> 00:00.0 0600: 8086:7190 (rev 03)
> 00:01.0 0604: 8086:7191 (rev 03)
> 00:07.0 0601: 8086:7110 (rev 02)
> 00:07.1 0101: 8086:7111 (rev 01)
> 00:07.2 0c03: 8086:7112 (rev 01)
> 00:07.3 0680: 8086:7113 (rev 02)
> 01:00.0 0300: 1039:6326 (rev 0b)
 



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stuge-linuxbios at cdy.org  Tue Aug  1 16:08:17 2006
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Tue, 1 Aug 2006 16:08:17 +0200
Subject: [LinuxBIOS] Intel Asks for Opinions on EFI,
	BIOS/Firmware in a Survey
In-Reply-To: <44CEC8BA.1040702@lanl.gov>
References: <44CE95A7.20904@onelabs.com> <44CEC8BA.1040702@lanl.gov>
Message-ID: <20060801140817.16769.qmail@cdy.org>

On Mon, Jul 31, 2006 at 09:21:30PM -0600, Ronald G Minnich wrote:
> Are you aware the industry is in the midst of moving from legacy
> BIOS to EFI/UEFI?
> 
> and there's no selections for linuxbios. What a joke.

I guess they don't consider people using LinuxBIOS to be in the
industry. (read: market)


> To be honest, I doubt very much what Intel cares about what people
> think of efi, but go ahead and take the poll -- you never know.

I think all they will get from the "poll" is how they can improve EFI
as a product. I wouldn't have bothered if I hadn't gotten to play
with a friend's iPod nano the other day. :)


//Peter



From indrek.kruusa at artecdesign.ee  Tue Aug  1 19:22:21 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Tue, 01 Aug 2006 20:22:21 +0300
Subject: [LinuxBIOS] [PATCH] Geode LX MSRs added/fixed
Message-ID: <44CF8DCD.8010000@artecdesign.ee>

Geode LX: this patch adds configuration/status/self-test MSR definitions 
for L2 cache and fixes wrong  P2D defines.

Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>



-------------- next part --------------
A non-text attachment was scrubbed...
Name: geode_lx_def_fix.patch
Type: text/x-patch
Size: 1937 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060801/30ea82e0/attachment.patch>

From indrek.kruusa at artecdesign.ee  Tue Aug  1 19:34:59 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Tue, 01 Aug 2006 20:34:59 +0300
Subject: [LinuxBIOS] [PATCH] Geode LX L2 cache initialization
Message-ID: <44CF90C3.5050401@artecdesign.ee>

This patch adds L2 cache initialization for Geode LX CPU.

Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>

-------------- next part --------------
A non-text attachment was scrubbed...
Name: geode_lx_init_cache.patch
Type: text/x-patch
Size: 1280 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060801/d7f2f1fd/attachment.patch>

From vincentetsou at nexcom.com.tw  Wed Aug  2 06:09:48 2006
From: vincentetsou at nexcom.com.tw (Vincente Tsou)
Date: Wed, 2 Aug 2006 12:09:48 +0800
Subject: [LinuxBIOS] New guy in LinuxBios
In-Reply-To: <41fde3420606261816k4bc80e7aw71bed26f2cc954f7@mail.gmail.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004004@ssvlexmb2.amd.com>
	<41fde3420606261816k4bc80e7aw71bed26f2cc954f7@mail.gmail.com>
Message-ID: <41fde3420608012109o51f02f2bs4bb882ab856fad09@mail.gmail.com>

Hi,

My target board is similar to Tyan s2882, I base on s2882's code to fit my
target board.

My target board also got an onboard Intel 10/100 NIC, and I assign the irq
like s2882 done.
        printk_debug("setting Onboard Intel NIC\n");
        static const unsigned char slotIrqs_8111_1_8[4] = { 9, 0, 0, 0 };
        pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_8);
        write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0, 0,
0, 0, 0, 0, 0, 0);
        pirq_info++; slot_num++;

It can works fine on unique processor platform, but when I boot into smp
kernel it's interrupts is not going.

[root at iSCSI h412]# cat /proc/interrupts
           CPU0       CPU1
  0:    1235644    1223971    IO-APIC-edge  timer
  1:          0          8    IO-APIC-edge  i8042
  2:          0          0          XT-PIC  cascade
  3:          5          3    IO-APIC-edge  serial
  4:       1209       1984    IO-APIC-edge  serial
  8:          0          1    IO-APIC-edge  rtc
 12:          0         66    IO-APIC-edge  i8042
 14:       3144        759    IO-APIC-edge  ide0
137:          0          0   IO-APIC-level  eth0     <-- It not works.
145:          0          0   IO-APIC-level  ohci_hcd, ohci_hcd
193:      10622          1   IO-APIC-level  eth2
NMI:          0          0
LOC:    2459674    2459668
ERR:          0
MIS:          0

Is it possible cause by IO-APIC ??



The other question, my VGA still has snow screen when linuxbios booting,
 even I moved the CPU init before other pci device init call.
But after I login the system, it will become clear.
following is part of my log....

--- part of linuxbios boot message --

Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device f5a
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

microcode: equivalent processor rev id  = 0x004a, patch id = 0x00000000
microcode: patch id that want to apply= 0x00000047
microcode: updated to patch id = 0x00000047  success

Setting up local apic... apic_id: 0 done.
Clearing memory 2048K - 262144K: --- done
CPU #0 Initialized
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device f5a
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

microcode: equivalent processor rev id  = 0x004a, patch id = 0x00000000
microcode: patch id that want to apply= 0x00000047
microcode: updated to patch id = 0x00000047  success

Setting up local apic... apic_id: 1 done.
Clearing memory 262144K - 524288K: ---- done
CPU #1 Initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 01:02.0 init
PCI: 03:04.0 init
PCI: 03:04.1 init
PCI: 01:03.0 init
PCI: 04:04.0 init
PCI: 04:02.0 init
rom address for PCI: 04:02.0 = fff80000
copying VGA ROM Image from 0xfff80000 to 0xc0000, 0x9000 bytes
entering emulator
halt_sys: file /home/vincente/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c,
line 4387

--- end of linuxbios boot message ---
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060802/d951c88a/attachment.html>

From yinghailu at gmail.com  Wed Aug  2 08:20:56 2006
From: yinghailu at gmail.com (yhlu)
Date: Tue, 1 Aug 2006 23:20:56 -0700
Subject: [LinuxBIOS] New guy in LinuxBios
In-Reply-To: <41fde3420608012109o51f02f2bs4bb882ab856fad09@mail.gmail.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004004@ssvlexmb2.amd.com>
	<41fde3420606261816k4bc80e7aw71bed26f2cc954f7@mail.gmail.com>
	<41fde3420608012109o51f02f2bs4bb882ab856fad09@mail.gmail.com>
Message-ID: <2ea3fae10608012320v7c20ac34ic903ca1f6afd4751@mail.gmail.com>

you need to update the entry in mptable.c for your eth0. try to read
the schematic to figure out how the io apic is conntected.

YH

On 8/1/06, Vincente Tsou <vincentetsou at nexcom.com.tw> wrote:
>
> Hi,
>
> My target board is similar to Tyan s2882, I base on s2882's code to fit my
> target board.
>
> My target board also got an onboard Intel 10/100 NIC, and I assign the irq
> like s2882 done.
>         printk_debug("setting Onboard Intel NIC\n");
>         static const unsigned char slotIrqs_8111_1_8[4] = { 9, 0, 0, 0 };
>         pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_8);
>         write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0, 0,
> 0, 0, 0, 0, 0, 0);
>         pirq_info++; slot_num++;
>
> It can works fine on unique processor platform, but when I boot into smp
> kernel it's interrupts is not going.
>
> [root at iSCSI h412]# cat /proc/interrupts
>            CPU0       CPU1
>   0:    1235644    1223971    IO-APIC-edge  timer
>   1:          0          8    IO-APIC-edge  i8042
>   2:          0          0          XT-PIC  cascade
>   3:          5          3    IO-APIC-edge  serial
>   4:       1209       1984    IO-APIC-edge  serial
>   8:          0          1    IO-APIC-edge  rtc
>  12:          0         66    IO-APIC-edge  i8042
>  14:       3144        759    IO-APIC-edge  ide0
> 137:          0          0   IO-APIC-level  eth0     <-- It not works.
> 145:          0          0   IO-APIC-level  ohci_hcd, ohci_hcd
> 193:      10622          1   IO-APIC-level  eth2
> NMI:          0          0
> LOC:    2459674    2459668
> ERR:          0
> MIS:          0
>
> Is it possible cause by IO-APIC ??
>
>
>
> The other question, my VGA still has snow screen when linuxbios booting,
>
> even I moved the CPU init before other pci device init call.
> But after I login the system, it will become clear.
> following is part of my log....
>
> --- part of linuxbios boot message --
>
>
> Initializing devices...
> Root Device init
> APIC_CLUSTER: 0 init
> Initializing CPU #0
> CPU: vendor AMD device f5a
> Enabling cache
>
> Setting fixed MTRRs(0-88) type: UC
> Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
> Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
> DONE fixed MTRRs
> Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
> DONE variable MTRRs
> Clear out the extra MTRR's
>
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
>
> microcode: equivalent processor rev id  = 0x004a, patch id = 0x00000000
> microcode: patch id that want to apply= 0x00000047
> microcode: updated to patch id = 0x00000047  success
>
> Setting up local apic... apic_id: 0 done.
> Clearing memory 2048K - 262144K: --- done
> CPU #0 Initialized
> Initializing CPU #1
> Waiting for 1 CPUS to stop
> CPU: vendor AMD device f5a
> Enabling cache
>
> Setting fixed MTRRs(0-88) type: UC
> Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
> Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
> DONE fixed MTRRs
> Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
> DONE variable MTRRs
> Clear out the extra MTRR's
>
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
>
> microcode: equivalent processor rev id  = 0x004a, patch id = 0x00000000
> microcode: patch id that want to apply= 0x00000047
> microcode: updated to patch id = 0x00000047  success
>
> Setting up local apic... apic_id: 1 done.
> Clearing memory 262144K - 524288K: ---- done
> CPU #1 Initialized
> All AP CPUs stopped
> PCI: 00:18.0 init
> PCI: 01:02.0 init
> PCI: 03:04.0 init
> PCI: 03:04.1 init
> PCI: 01:03.0 init
> PCI: 04:04.0 init
>
> PCI: 04:02.0 init
> rom address for PCI: 04:02.0 = fff80000
> copying VGA ROM Image from 0xfff80000 to 0xc0000, 0x9000 bytes
> entering emulator
> halt_sys: file
> /home/vincente/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c,
> line 4387
>
>
>
> --- end of linuxbios boot message ---



From vincentetsou at nexcom.com.tw  Wed Aug  2 09:53:29 2006
From: vincentetsou at nexcom.com.tw (Vincente Tsou)
Date: Wed, 2 Aug 2006 15:53:29 +0800
Subject: [LinuxBIOS] New guy in LinuxBios
In-Reply-To: <2ea3fae10608012320v7c20ac34ic903ca1f6afd4751@mail.gmail.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004004@ssvlexmb2.amd.com>
	<41fde3420606261816k4bc80e7aw71bed26f2cc954f7@mail.gmail.com>
	<41fde3420608012109o51f02f2bs4bb882ab856fad09@mail.gmail.com>
	<2ea3fae10608012320v7c20ac34ic903ca1f6afd4751@mail.gmail.com>
Message-ID: <41fde3420608020053laf420eoe9508cbc636bef55@mail.gmail.com>

Yeah, it works now.

Thanks a lot.

How about the snow screen issue?
Do you have any idea?

2006/8/2, yhlu <yinghailu at gmail.com>:
>
> you need to update the entry in mptable.c for your eth0. try to read
> the schematic to figure out how the io apic is conntected.
>
> YH
>
> On 8/1/06, Vincente Tsou <vincentetsou at nexcom.com.tw> wrote:
> >
> > Hi,
> >
> > My target board is similar to Tyan s2882, I base on s2882's code to fit
> my
> > target board.
> >
> > My target board also got an onboard Intel 10/100 NIC, and I assign the
> irq
> > like s2882 done.
> >         printk_debug("setting Onboard Intel NIC\n");
> >         static const unsigned char slotIrqs_8111_1_8[4] = { 9, 0, 0, 0
> };
> >         pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_8);
> >         write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0,
> 0,
> > 0, 0, 0, 0, 0, 0);
> >         pirq_info++; slot_num++;
> >
> > It can works fine on unique processor platform, but when I boot into smp
> > kernel it's interrupts is not going.
> >
> > [root at iSCSI h412]# cat /proc/interrupts
> >            CPU0       CPU1
> >   0:    1235644    1223971    IO-APIC-edge  timer
> >   1:          0          8    IO-APIC-edge  i8042
> >   2:          0          0          XT-PIC  cascade
> >   3:          5          3    IO-APIC-edge  serial
> >   4:       1209       1984    IO-APIC-edge  serial
> >   8:          0          1    IO-APIC-edge  rtc
> >  12:          0         66    IO-APIC-edge  i8042
> >  14:       3144        759    IO-APIC-edge  ide0
> > 137:          0          0   IO-APIC-level  eth0     <-- It not works.
> > 145:          0          0   IO-APIC-level  ohci_hcd, ohci_hcd
> > 193:      10622          1   IO-APIC-level  eth2
> > NMI:          0          0
> > LOC:    2459674    2459668
> > ERR:          0
> > MIS:          0
> >
> > Is it possible cause by IO-APIC ??
> >
> >
> >
> > The other question, my VGA still has snow screen when linuxbios booting,
> >
> > even I moved the CPU init before other pci device init call.
> > But after I login the system, it will become clear.
> > following is part of my log....
> >
> > --- part of linuxbios boot message --
> >
> >
> > Initializing devices...
> > Root Device init
> > APIC_CLUSTER: 0 init
> > Initializing CPU #0
> > CPU: vendor AMD device f5a
> > Enabling cache
> >
> > Setting fixed MTRRs(0-88) type: UC
> > Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
> > Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
> > DONE fixed MTRRs
> > Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
> > DONE variable MTRRs
> > Clear out the extra MTRR's
> >
> > MTRR check
> > Fixed MTRRs   : Enabled
> > Variable MTRRs: Enabled
> >
> > microcode: equivalent processor rev id  = 0x004a, patch id = 0x00000000
> > microcode: patch id that want to apply= 0x00000047
> > microcode: updated to patch id = 0x00000047  success
> >
> > Setting up local apic... apic_id: 0 done.
> > Clearing memory 2048K - 262144K: --- done
> > CPU #0 Initialized
> > Initializing CPU #1
> > Waiting for 1 CPUS to stop
> > CPU: vendor AMD device f5a
> > Enabling cache
> >
> > Setting fixed MTRRs(0-88) type: UC
> > Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
> > Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
> > DONE fixed MTRRs
> > Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
> > DONE variable MTRRs
> > Clear out the extra MTRR's
> >
> > MTRR check
> > Fixed MTRRs   : Enabled
> > Variable MTRRs: Enabled
> >
> > microcode: equivalent processor rev id  = 0x004a, patch id = 0x00000000
> > microcode: patch id that want to apply= 0x00000047
> > microcode: updated to patch id = 0x00000047  success
> >
> > Setting up local apic... apic_id: 1 done.
> > Clearing memory 262144K - 524288K: ---- done
> > CPU #1 Initialized
> > All AP CPUs stopped
> > PCI: 00:18.0 init
> > PCI: 01:02.0 init
> > PCI: 03:04.0 init
> > PCI: 03:04.1 init
> > PCI: 01:03.0 init
> > PCI: 04:04.0 init
> >
> > PCI: 04:02.0 init
> > rom address for PCI: 04:02.0 = fff80000
> > copying VGA ROM Image from 0xfff80000 to 0xc0000, 0x9000 bytes
> > entering emulator
> > halt_sys: file
> > /home/vincente/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c,
> > line 4387
> >
> >
> >
> > --- end of linuxbios boot message ---
>
>


-- 
Best Regards,
Vincente Tsou

Engineer
R/D, S/W Dept.
NEXCOM International Co.
Tel: 886-2-82280606 Ext. 3205
Fax: 886-2-82280506
E-mail: vincentetsou at nexcom.com.tw
Web: http://www.nexcom.com.tw/
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060802/2c8dc816/attachment.html>

From info at coresystems.de  Wed Aug  2 14:08:47 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Wed, 02 Aug 2006 14:08:47 +0200
Subject: [LinuxBIOS] LinuxBIOS r2355 build changes
Message-ID: <E1G8FWp-0004dF-GJ@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2355 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Geode LX: this patch adds configuration/status/self-test MSR definitionsfor L2 cache and fixes wrong  P2D defines.This also patch adds L2 cache initialization for Geode LX CPU.Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From info at coresystems.de  Wed Aug  2 15:04:20 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Wed, 02 Aug 2006 15:04:20 +0200
Subject: [LinuxBIOS] LinuxBIOS r2356 build changes
Message-ID: <E1G8GOa-0006BK-N9@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "noodles" checked in revision 2356 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Add newer Via Nehemiah stepping levels.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in noodles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From info at coresystems.de  Wed Aug  2 15:43:45 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Wed, 02 Aug 2006 15:43:45 +0200
Subject: [LinuxBIOS] LinuxBIOS r2357 build changes
Message-ID: <E1G8H0j-0007JG-9B@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "noodles" checked in revision 2357 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Allow setting of serial port speed in EPIA-M config file.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in noodles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From indrek.kruusa at artecdesign.ee  Wed Aug  2 18:38:13 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Wed, 02 Aug 2006 19:38:13 +0300
Subject: [LinuxBIOS] [PATCH] Geode LX L2 cache initialization
In-Reply-To: <44CF90C3.5050401@artecdesign.ee>
References: <44CF90C3.5050401@artecdesign.ee>
Message-ID: <44D0D4F5.5060704@artecdesign.ee>

Indrek Kruusa wrote:
> This patch adds L2 cache initialization for Geode LX CPU.
>
> Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>


Please don't commit this one!

Cache sould be initialized right after shadowing linuxBIOS  and before 
northbridge/CPU bugs/chipset/VSA etc.

I will prepare the new patch.

thanks,
Indrek




From stepan at coresystems.de  Wed Aug  2 18:42:43 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 2 Aug 2006 18:42:43 +0200
Subject: [LinuxBIOS] [PATCH] Geode LX L2 cache initialization
In-Reply-To: <44D0D4F5.5060704@artecdesign.ee>
References: <44CF90C3.5050401@artecdesign.ee> <44D0D4F5.5060704@artecdesign.ee>
Message-ID: <20060802164243.GB12881@coresystems.de>

* Indrek Kruusa <indrek.kruusa at artecdesign.ee> [060802 18:38]:
> Indrek Kruusa wrote:
> > This patch adds L2 cache initialization for Geode LX CPU.
> >
> > Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>
> 
> 
> Please don't commit this one!
> 
> Cache sould be initialized right after shadowing linuxBIOS  and before 
> northbridge/CPU bugs/chipset/VSA etc.
> 
> I will prepare the new patch.
>

can you look into why the target does not build? (see build logs on
snapshots.linuxbios.org)

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From indrek.kruusa at artecdesign.ee  Wed Aug  2 19:09:42 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Wed, 02 Aug 2006 20:09:42 +0300
Subject: [LinuxBIOS] [PATCH] Geode LX L2 cache initialization
In-Reply-To: <20060802164243.GB12881@coresystems.de>
References: <44CF90C3.5050401@artecdesign.ee> <44D0D4F5.5060704@artecdesign.ee>
	<20060802164243.GB12881@coresystems.de>
Message-ID: <44D0DC56.5090204@artecdesign.ee>

Stefan Reinauer wrote:
> * Indrek Kruusa <indrek.kruusa at artecdesign.ee> [060802 18:38]:
>   
>> Indrek Kruusa wrote:
>>     
>>> This patch adds L2 cache initialization for Geode LX CPU.
>>>
>>> Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>
>>>       
>> Please don't commit this one!
>>
>> Cache sould be initialized right after shadowing linuxBIOS  and before 
>> northbridge/CPU bugs/chipset/VSA etc.
>>
>> I will prepare the new patch.
>>
>>     
>
> can you look into why the target does not build? (see build logs on
> snapshots.linuxbios.org)
>   

I'v sent some patches directly to Ronald but he is lost somewere.

I will prepare new patches as there are more changes. This will not fix 
the build though - we need to separate GX2 and CS5536 (latter includes 
defs from CPU). Then we can connect CS5536 to Geode LX too.

My local copy builds of course ;)

thanks,
Indrek




From dpw at email.cs.arizona.edu  Wed Aug  2 19:45:26 2006
From: dpw at email.cs.arizona.edu (Don Waugaman)
Date: Wed, 02 Aug 2006 10:45:26 -0700
Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L
In-Reply-To: <8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
References: <1154140868.9333.47.camel@cslewis>
	<8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com>
	<8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
Message-ID: <1154540726.4537.17.camel@cslewis>


On Sat, 2006-07-29 at 12:53 -0500, Richard Smith wrote:
> > You are in luck.  I've actually got booting code for my ASUS P2b. Both
> >
> > > My main question is:  The W83977TF has support under v1, but not v2 -
> > > any tips on porting from one to the other?
> >
> > I've done this already.  I'll push the code up in a few hours or so.
> > Its on a machine I don't have local access to right now.
> 
> I just committed my framework for the Asus P2B.  Hopefully it works
> for you.  It should come up and try to dump the contents of the SPD on
> the RAM. But like I said its broken even without the Asus magic.  I'm
> going to try and work on that today and see if I can discover
> something.
> 
> So step one for P2B is to work with the board booted under factory
> BIOS and see if we can figure out what GPIO is used to enable the
> memory SMbus.
> 
> 2.6 kernels know how to dump the SPD for a i440bx so see if you can do
> that.  If that works then we just need to start comparing a
> northbridge dump of the Asus vs a non-asus 440bx and see if any of the
> GPIO are different.

Thanks for your help on this, Richard!

This took a little longer than I expected due to my son's fourth
birthday and having to change the p2b configuration to output via the
second serial port (my board's first serial port has been flaky in the
past), but I'm getting some results.

Here's what I get from i2cdump 0 0x5{0-3} under Linux running with the
factory BIOS:

[root at matthias ~]# i2cdump 0 0x50
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and
worse!
I will probe file /dev/i2c-0, address 0x50, mode byte
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 80 08 04 0c 0a 02 48 00 01 a0 60 02 80 08 08 01    ??????H.??`?????
10: 07 04 04 01 01 1f 0e 00 00 00 00 14 14 14 32 20    ???????....???2
20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00     ? ?............
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 be    ..............??
40: 7f 98 00 00 00 00 00 00 46 4b 47 4d 31 30 30 78    ??......FKGM100x
50: 37 32 52 43 33 2f 32 35 36 00 00 00 00 01 26 18    72RC3/256....?&?
60: 1a f2 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ??..............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 84    ..............d?
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
f0: 39 39 36 32 32 32 38 2d 30 30 31 2e 41 30 30 ff    9962228-001.A00.

[root at matthias ~]# i2cdump 0 0x51
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and
worse!
I will probe file /dev/i2c-0, address 0x51, mode byte
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 80 08 04 0c 0a 02 48 00 01 a0 60 02 80 08 08 01    ??????H.??`?????
10: 07 04 04 01 01 1f 0e 00 00 00 00 14 14 14 32 20    ???????....???2
20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00     ? ?............
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 be    ..............??
40: 7f 98 00 00 00 00 00 00 46 4b 47 4d 31 30 30 78    ??......FKGM100x
50: 37 32 52 43 33 2f 32 35 36 00 00 00 00 01 23 18    72RC3/256....?#?
60: 04 25 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?%..............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 84    ..............d?
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

[root at matthias ~]# i2cdump 0 0x52
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and
worse!
I will probe file /dev/i2c-0, address 0x52, mode byte
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 80 08 04 0c 0a 02 48 00 01 a0 60 02 80 08 08 01    ??????H.??`?????
10: 07 04 04 01 01 1f 0e 00 00 00 00 14 14 14 32 20    ???????....???2
20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00     ? ?............
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 be    ..............??
40: 7f 98 00 00 00 00 00 00 46 4b 47 4d 31 30 30 78    ??......FKGM100x
50: 37 32 52 43 33 2f 32 35 36 00 00 00 00 01 23 1c    72RC3/256....?#?
60: 04 b8 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ??..............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 84    ..............d?
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

[root at matthias ~]# i2cdump 0 0x53
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and
worse!
I will probe file /dev/i2c-0, address 0x53, mode byte
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 80 08 04 0c 0a 02 48 00 01 a0 60 02 80 08 08 01    ??????H.??`?????
10: 07 04 04 01 01 1f 0e 00 00 00 00 14 14 14 32 20    ???????....???2
20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00     ? ?............
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 be    ..............??
40: 7f 98 00 00 00 00 00 00 46 4b 47 4d 31 30 30 78    ??......FKGM100x
50: 37 32 52 43 33 2f 32 35 36 00 00 00 00 02 21 01    72RC3/256....?!?
60: 26 7c 26 00 00 00 00 00 00 00 00 00 00 00 00 00    &|&.............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 84    ..............d?
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
f0: 39 39 36 32 32 32 38 2d 30 30 31 2e 41 30 30 00    9962228-001.A00.


These probes are byte-for-byte identical with what the p2b target
LinuxBIOSv2 outputs when I flash it and start up my system.

When I ran the program to setup lm_sensors, I got this:


Driver `lm78' (may not be inserted):
  Misdetects:
  * Bus `SMBus PIIX4 adapter at e800' (Algorithm unavailable)
    Busdriver `i2c-piix4', I2C address 0x2d
    ISA bus address 0x0290 (Busdriver `i2c-isa')
    Chip `National Semiconductor LM78' (confidence: 6)

Driver `w83781d' (should be inserted):
  Detects correctly:
  * Bus `SMBus PIIX4 adapter at e800' (Algorithm unavailable)
    Busdriver `i2c-piix4', I2C address 0x2d (and 0x48 0x49)
    ISA bus address 0x0290 (Busdriver `i2c-isa')
    Chip `Winbond W83781D' (confidence: 8)

Driver `eeprom' (should be inserted):
  Detects correctly:
  * Bus `SMBus PIIX4 adapter at e800' (Algorithm unavailable)
    Busdriver `i2c-piix4', I2C address 0x50
    Chip `SPD EEPROM' (confidence: 8)
  * Bus `SMBus PIIX4 adapter at e800' (Algorithm unavailable)
    Busdriver `i2c-piix4', I2C address 0x51
    Chip `SPD EEPROM' (confidence: 8)
  * Bus `SMBus PIIX4 adapter at e800' (Algorithm unavailable)
    Busdriver `i2c-piix4', I2C address 0x52
    Chip `SPD EEPROM' (confidence: 8)
  * Bus `SMBus PIIX4 adapter at e800' (Algorithm unavailable)
    Busdriver `i2c-piix4', I2C address 0x53
    Chip `SPD EEPROM' (confidence: 8)


So - does this mean that the w83781d is controlling the memory SMBUS,
since it's detected correctly?

Also, you mentioned a couple of changes to the 440bx code that you'd
like to do.  Would it be OK for me to take a shot at these changes -
probably tonight or tomorrow - as a way to get my feet wet with the
codebase and hopefully make a small contribution?  I'd guess that the
southbridge name change would be pretty trivial, but the other change
might need a little more smarts - but I'd like to take a shot at 'em.

Take care,

Don





From indrek.kruusa at artecdesign.ee  Wed Aug  2 20:12:15 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Wed, 02 Aug 2006 21:12:15 +0300
Subject: [LinuxBIOS] [PATCH] Geode LX changes
Message-ID: <44D0EAFF.1050905@artecdesign.ee>

Changelog:

* src/cpu/amd/model_lx/model_lx_init.c
    L2 cache initialization removed (moved to northbridge.c)

* src/include/cpu/amd/lxdef.h
    more checked values

* src/northbridge/amd/lx/northbridge.c
    L2 cache initialization added
    cpubug() commented out

* src/northbridge/amd/lx/raminit.c
    empty function sdram_set_registers() is in use, don't remove


Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov at artecdesign.ee>

-------------- next part --------------
A non-text attachment was scrubbed...
Name: geode_lx_fixes.patch
Type: text/x-patch
Size: 4915 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060802/fca61176/attachment.patch>

From indrek.kruusa at artecdesign.ee  Wed Aug  2 20:23:52 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Wed, 02 Aug 2006 21:23:52 +0300
Subject: [LinuxBIOS] [PATCH] Changes for artecgroup/dbe61
Message-ID: <44D0EDB8.2050402@artecdesign.ee>

Changelog:

* src/mainboard/artecgroup/dbe61/Config.lb
    irqmap changes

* src/mainboard/artecgroup/dbe61/irq_tables.c
    tentative changes to irq table (currently not in use)

* src/mainboard/artecgroup/dbe61/mainboard.c
    irq assigned manually to NIC

* src/mainboard/artecgroup/dbe61/Options.lb
    gcc 4.0 is OK

* targets/artecgroup/dbe61/Config.lb
    64K for VSA is OK at moment


Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov at artecdesign.ee>

-------------- next part --------------
A non-text attachment was scrubbed...
Name: artecgroup_dbe61_fixes.patch
Type: text/x-patch
Size: 8395 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060802/21e3e55c/attachment.patch>

From indrek.kruusa at artecdesign.ee  Wed Aug  2 20:37:03 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Wed, 02 Aug 2006 21:37:03 +0300
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
Message-ID: <44D0F0CF.2050308@artecdesign.ee>

Hi!

Currently I need to change cs5536 code (below) to make Geode LX target 
build.

To conclude the situation:
- different CPU-s with integrated northbridge using the same southbridge
- southbridge needs to know about CPU

Which should be the preferred way to fix it?

thanks,
Indrek


/*****************/


diff -u -r -b -B LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 
LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536.c
--- LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c     2006-07-22 
02:21:01.000000000 +0300
+++ LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536.c 2006-07-31 
17:53:04.000000000 +0300
@@ -5,7 +5,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include <cpu/amd/gx2def.h>
+#include <cpu/amd/lxdef.h>
 #include <cpu/x86/msr.h>
 #include "chip.h"

diff -u -r -b -B 
LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 
LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536_early_setup.c
--- LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 
2006-07-27 07:05:43.000000000 +0300
+++ LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536_early_setup.c     
2006-07-31 17:52:52.000000000 +0300
@@ -1,4 +1,4 @@
-#include <cpu/amd/gx2def.h>
+#include <cpu/amd/lxdef.h>

 /*
  *






From rminnich at gmail.com  Wed Aug  2 21:53:23 2006
From: rminnich at gmail.com (ron minnich)
Date: Wed, 2 Aug 2006 13:53:23 -0600
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <44D0F0CF.2050308@artecdesign.ee>
References: <44D0F0CF.2050308@artecdesign.ee>
Message-ID: <13426df10608021253g2030de50p6757d1017b5fb203@mail.gmail.com>

I'm on vacation, but have a plan for this, can we wait one week?

thanks

ron



From rminnich at lanl.gov  Wed Aug  2 22:25:14 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Wed, 02 Aug 2006 14:25:14 -0600
Subject: [LinuxBIOS] [PATCH] Geode LX L2 cache initialization
In-Reply-To: <44D0DC56.5090204@artecdesign.ee>
References: <44CF90C3.5050401@artecdesign.ee>
	<44D0D4F5.5060704@artecdesign.ee>	<20060802164243.GB12881@coresystems.de>
	<44D0DC56.5090204@artecdesign.ee>
Message-ID: <44D10A2A.7060808@lanl.gov>

Indrek Kruusa wrote:

> I'v sent some patches directly to Ronald but he is lost somewere.
> 
> I will prepare new patches as there are more changes. This will not fix 
> the build though - we need to separate GX2 and CS5536 (latter includes 
> defs from CPU). Then we can connect CS5536 to Geode LX too.


I am on travel. I'd also like your patches to be totally stable before I 
commit them.

ron



From smithbone at gmail.com  Thu Aug  3 01:30:51 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 2 Aug 2006 18:30:51 -0500
Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L
In-Reply-To: <1154540726.4537.17.camel@cslewis>
References: <1154140868.9333.47.camel@cslewis>
	<8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com>
	<8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
	<1154540726.4537.17.camel@cslewis>
Message-ID: <8a0c36780608021630n6bcdb593wd9a6ca192a4ae6a7@mail.gmail.com>

>
> This took a little longer than I expected due to my son's fourth

No rush we got lots of time.

> These probes are byte-for-byte identical with what the p2b target
> LinuxBIOSv2 outputs when I flash it and start up my system.

Well thats a positive sign.  I don't know for a _fact_ that the asus
p2b has the smbus hidden.  Back when I was messing with that under V1
(several years ago) there were reports on the list that asus
motherboards did funky things with the smbus.  I took working V1
bitworks/IMS code and brought it up on a p2b (rev 1.04) with the exact
same memory and memory didn't fly.  Hardcoding the memory settings
made it work fine.  That + reports of asus smbus funkyness led me to
believe that the smbus was as fault.  At the time hardcoding the
memory was fine for what I needed to test so I didn't persue it any
further.

You are reporting that the spd reads work you under linuxbios.  Correct?
If thats the case then perhaps my V1 issues were code problems and not
hardware smbus problems.  Which is good.
I've still got that p2b so I'll test and see if I get the same results as you.

> So - does this mean that the w83781d is controlling the memory SMBUS,
> since it's detected correctly?

I don't think so.  The W83781D is a hardware monitor chip and looking
at the datasheet I don't see the ability to be an I2C master.  What I
think that is telling you is that the W83781D ISA's interface (it has
I2C and ISA) is also available at IO 0x0290.

The spd read code only talks to the PIIX4 and you got data back from
that so the W83781D really doesn't matter.

> Also, you mentioned a couple of changes to the 440bx code that you'd
> like to do.  Would it be OK for me to take a shot at these changes -
> probably tonight or tomorrow - as a way to get my feet wet with the
> codebase and hopefully make a small contribution?  I'd guess that the
> southbridge name change would be pretty trivial, but the other change
> might need a little more smarts - but I'd like to take a shot at 'em.

Sure. Any and all help is very welcome.

Lets go with Stefan's suggestion and name the southbridge chip after
its actual ID.  i82371eb.  Thats a pretty easy change.

The RAM init re-base is pertty much the same.  Copy the raminit.c and
raminit.h from the intel/e7501 on top of the raminit.[ch] thats there
and then go though and fixup any specific e7501 names.

Then the hard part starts.  We have to go though and start walking the
ram init chain and make each one of those steps match the 440bx using
the V1 assembly as a guide.  The e7501 appears to be a DDR controller
with 2 channels but its very well documented and I like the structure.
 It looks much nicer than the via example I used previously.

-- 
Richard A. Smith



From c-d.hailfinger.devel.2006 at gmx.net  Thu Aug  3 08:24:37 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel U. Hailfinger)
Date: Thu, 03 Aug 2006 08:24:37 +0200
Subject: [LinuxBIOS] [OLPC-devel] Re: Not so good news (Was: good news)
In-Reply-To: <20060802162632.GA11524@coresystems.de>
References: <20060731163016.GH20126@cosmic.amd.com>
	<20060731180048.25800@gmx.net> <20060731211450.183750@gmx.net>
	<20060731221138.GB23596@cosmic.amd.com> <44CEBFAF.6060402@lanl.gov>
	<20060801131955.181340@gmx.net> <20060801143545.181320@gmx.net>
	<20060801173319.GD13756@cosmic.amd.com> <44D01006.4020809@lanl.gov>
	<20060802161101.216680@gmx.net> <20060802162632.GA11524@coresystems.de>
Message-ID: <20060803062437.59500@gmx.net>

Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger wrote:
>
> > What we need from you is a way to use nrv2b compressed ELF images as
> > payload. Please don't say that is impossible.
>  
> CONFIG_COMPRESSED_ROM_STREAM does exactly that. 
> 
> You need to give it an uncompressed payload since it does compression on
> its own.

ARGH! Now that indeed explains things very well.

Attached is a patch to make LinuxBIOS support precompressed payloads. While the LinuxBIOS build system can compress payloads on its own, the OLPC build system benefits from delivering a precompressed (and size-checked) payload.

Although the patch modifies targets/olpc/rev_a/Config.1M.lb this has no effect on current OLPC buildrom because it checks out an earlier revision of LinuxBIOS. So it should be a safe to apply.

As a reply to this message, I'll post the necessary OLPC buildrom changes to make use of the new infrastructure.

Regards,
Carl-Daniel
-- 


Echte DSL-Flatrate dauerhaft f?r 0,- Euro*. Nur noch kurze Zeit!
"Feel free" mit GMX DSL: http://www.gmx.net/de/go/dsl
-------------- next part --------------
A non-text attachment was scrubbed...
Name: linuxbios-precompressed-rom-stream02.diff
Type: text/x-patch
Size: 1769 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060803/c24dd498/attachment.diff>

From c-d.hailfinger.devel.2006 at gmx.net  Thu Aug  3 08:34:15 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel U. Hailfinger)
Date: Thu, 03 Aug 2006 08:34:15 +0200
Subject: [LinuxBIOS] [OLPC-devel] Re: Not so good news (Was: good news)
In-Reply-To: <20060803062437.59500@gmx.net>
References: <20060731163016.GH20126@cosmic.amd.com>
	<20060731180048.25800@gmx.net> <20060731211450.183750@gmx.net>
	<20060731221138.GB23596@cosmic.amd.com> <44CEBFAF.6060402@lanl.gov>
	<20060801131955.181340@gmx.net> <20060801143545.181320@gmx.net>
	<20060801173319.GD13756@cosmic.amd.com> <44D01006.4020809@lanl.gov>
	<20060802161101.216680@gmx.net> <20060802162632.GA11524@coresystems.de>
	<20060803062437.59500@gmx.net>
Message-ID: <20060803063415.59500@gmx.net>

Carl-Daniel Hailfinger wrote:
> Stefan Reinauer wrote:
> > * Carl-Daniel Hailfinger wrote:
> >
> > > What we need from you is a way to use nrv2b compressed ELF images as
> > > payload. Please don't say that is impossible.
> >  
> > CONFIG_COMPRESSED_ROM_STREAM does exactly that. 
> > 
> > You need to give it an uncompressed payload since it does compression
> > on its own.
> 
> ARGH! Now that indeed explains things very well.
> 
> Attached is a patch to make LinuxBIOS support precompressed payloads.
> 
> Although the patch modifies targets/olpc/rev_a/Config.1M.lb this has no
> effect on current OLPC buildrom because it checks out an earlier revision
> of LinuxBIOS. So it should be a safe to apply.

And here is the patch to buildrom to make use of the new infrastructure. Please note that it should only be applied AFTER the LinuxBIOS patch in my last mail has been merged upstream.
You may have to change the checked out revision in packages/linuxbios/linuxbios.mk.

Regards,
Carl-Daniel
-- 


Echte DSL-Flatrate dauerhaft f?r 0,- Euro*. Nur noch kurze Zeit!
"Feel free" mit GMX DSL: http://www.gmx.net/de/go/dsl
-------------- next part --------------
A non-text attachment was scrubbed...
Name: olpc-nrv2b-support-01.diff
Type: text/x-patch
Size: 1128 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060803/acde27d4/attachment.diff>

From indrek.kruusa at artecdesign.ee  Thu Aug  3 09:14:34 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Thu, 03 Aug 2006 10:14:34 +0300
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <13426df10608021253g2030de50p6757d1017b5fb203@mail.gmail.com>
References: <44D0F0CF.2050308@artecdesign.ee>
	<13426df10608021253g2030de50p6757d1017b5fb203@mail.gmail.com>
Message-ID: <44D1A25A.8020401@artecdesign.ee>

ron minnich wrote:
> I'm on vacation, but have a plan for this, can we wait one week?

yes we can.

thanks,
Indrek




From info at coresystems.de  Thu Aug  3 13:29:28 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 03 Aug 2006 13:29:28 +0200
Subject: [LinuxBIOS] LinuxBIOS r2358 build changes
Message-ID: <E1G8bOK-0008DD-6q@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2358 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
some documentation updates by Uwe and some smaller ones by me.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From smithbone at gmail.com  Thu Aug  3 17:13:18 2006
From: smithbone at gmail.com (Richard Smith)
Date: Thu, 3 Aug 2006 10:13:18 -0500
Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L
In-Reply-To: <8a0c36780608021630n6bcdb593wd9a6ca192a4ae6a7@mail.gmail.com>
References: <1154140868.9333.47.camel@cslewis>
	<8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com>
	<8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
	<1154540726.4537.17.camel@cslewis>
	<8a0c36780608021630n6bcdb593wd9a6ca192a4ae6a7@mail.gmail.com>
Message-ID: <8a0c36780608030813u7ffcabchb63fc921a02456ff@mail.gmail.com>

> hardware smbus problems.  Which is good.
> I've still got that p2b so I'll test and see if I get the same results as you.
>

I pulled out my old p2b board and manged to find all the stuff to make
it boot.  Then ran the current V2 p2b target build.

Indeed it dumps the SPD out just fine.  So yah!  Thats good news.  My
V1 stuff must have had some other issue that kept the RAM from getting
detected properly.

-- 
Richard A. Smith



From rminnich at lanl.gov  Thu Aug  3 17:27:16 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 03 Aug 2006 09:27:16 -0600
Subject: [LinuxBIOS] [OLPC-devel] Re: Not so good news (Was: good news)
In-Reply-To: <20060803062437.59500@gmx.net>
References: <20060731163016.GH20126@cosmic.amd.com>
	<20060731180048.25800@gmx.net> <20060731211450.183750@gmx.net>
	<20060731221138.GB23596@cosmic.amd.com>
	<44CEBFAF.6060402@lanl.gov> <20060801131955.181340@gmx.net>
	<20060801143545.181320@gmx.net>
	<20060801173319.GD13756@cosmic.amd.com>
	<44D01006.4020809@lanl.gov> <20060802161101.216680@gmx.net>
	<20060802162632.GA11524@coresystems.de>
	<20060803062437.59500@gmx.net>
Message-ID: <44D215D4.6000809@lanl.gov>

stefan, if this patch is ok with you, it's ok with me too.

thanks

ron



From rminnich at lanl.gov  Thu Aug  3 17:28:29 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 03 Aug 2006 09:28:29 -0600
Subject: [LinuxBIOS] [OLPC-devel] Re: Not so good news (Was: good news)
In-Reply-To: <20060803063415.59500@gmx.net>
References: <20060731163016.GH20126@cosmic.amd.com>	<20060731180048.25800@gmx.net>
	<20060731211450.183750@gmx.net>	<20060731221138.GB23596@cosmic.amd.com>
	<44CEBFAF.6060402@lanl.gov>	<20060801131955.181340@gmx.net>
	<20060801143545.181320@gmx.net>	<20060801173319.GD13756@cosmic.amd.com>
	<44D01006.4020809@lanl.gov>	<20060802161101.216680@gmx.net>
	<20060802162632.GA11524@coresystems.de>	<20060803062437.59500@gmx.net>
	<20060803063415.59500@gmx.net>
Message-ID: <44D2161D.5000908@lanl.gov>

Carl-Daniel U. Hailfinger wrote:

> And here is the patch to buildrom to make use of the new infrastructure. Please note that it should only be applied AFTER the LinuxBIOS patch in my last mail has been merged upstream.
> You may have to change the checked out revision in packages/linuxbios/linuxbios.mk.


as soon as someone tests that new version of linuxbios and it works, we 
can do that change.

Thanks, this is excellent work.

ron



From stepan at coresystems.de  Thu Aug  3 18:09:16 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 3 Aug 2006 18:09:16 +0200
Subject: [LinuxBIOS] [OLPC-devel] Re: Not so good news (Was: good news)
In-Reply-To: <44D215D4.6000809@lanl.gov>
References: <20060731221138.GB23596@cosmic.amd.com>
	<44CEBFAF.6060402@lanl.gov> <20060801131955.181340@gmx.net>
	<20060801143545.181320@gmx.net>
	<20060801173319.GD13756@cosmic.amd.com>
	<44D01006.4020809@lanl.gov> <20060802161101.216680@gmx.net>
	<20060802162632.GA11524@coresystems.de>
	<20060803062437.59500@gmx.net> <44D215D4.6000809@lanl.gov>
Message-ID: <20060803160916.GA19626@coresystems.de>

* Ronald G Minnich <rminnich at lanl.gov> [060803 17:27]:
> stefan, if this patch is ok with you, it's ok with me too.
 
The CONFIG_PRECOMPRESSED_ROM_STREAM patch is fine. No curlicues but ok
to commit. A cleaner version would be to autodetect if the nrv2b stream
is already compressed. But:
 - nrv2b would need to be extended
 - we have lzma in mind anyways
 - the patch is simple

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From jordan.crouse at amd.com  Thu Aug  3 18:04:13 2006
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 3 Aug 2006 10:04:13 -0600
Subject: [LinuxBIOS] Not so good news (Was: good news)
In-Reply-To: <20060803062437.59500@gmx.net>
References: <20060731211450.183750@gmx.net>
	<20060731221138.GB23596@cosmic.amd.com> <44CEBFAF.6060402@lanl.gov>
	<20060801131955.181340@gmx.net> <20060801143545.181320@gmx.net>
	<20060801173319.GD13756@cosmic.amd.com> <44D01006.4020809@lanl.gov>
	<20060802161101.216680@gmx.net> <20060802162632.GA11524@coresystems.de>
	<20060803062437.59500@gmx.net>
Message-ID: <20060803160413.GE30215@cosmic.amd.com>

On 03/08/06 08:24 +0200, Carl-Daniel U. Hailfinger wrote:
> Stefan Reinauer wrote:
> > * Carl-Daniel Hailfinger wrote:
> >
> > > What we need from you is a way to use nrv2b compressed ELF images as
> > > payload. Please don't say that is impossible.
> >  
> > CONFIG_COMPRESSED_ROM_STREAM does exactly that. 
> > 
> > You need to give it an uncompressed payload since it does compression on
> > its own.
> 
> ARGH! Now that indeed explains things very well.
> 
> Attached is a patch to make LinuxBIOS support precompressed payloads. While the LinuxBIOS build system can compress payloads on its own, the OLPC build system benefits from delivering a precompressed (and size-checked) payload.
> 
> Although the patch modifies targets/olpc/rev_a/Config.1M.lb this has no effect on current OLPC buildrom because it checks out an earlier revision of LinuxBIOS. So it should be a safe to apply.

Ron - you'll have to decide if you want to apply this to LinuxBIO or not -
and then we'll just use the new revision.

This scares me - I don't like that we can't easily control the behavior here
without patches (that would have to be updated every time we change 
revisions).

Jordan





From stepan at coresystems.de  Thu Aug  3 18:22:06 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 3 Aug 2006 18:22:06 +0200
Subject: [LinuxBIOS] [OLPC-devel] Re: Not so good news (Was: good news)
In-Reply-To: <20060803160916.GA19626@coresystems.de>
References: <44CEBFAF.6060402@lanl.gov> <20060801131955.181340@gmx.net>
	<20060801143545.181320@gmx.net>
	<20060801173319.GD13756@cosmic.amd.com>
	<44D01006.4020809@lanl.gov> <20060802161101.216680@gmx.net>
	<20060802162632.GA11524@coresystems.de>
	<20060803062437.59500@gmx.net> <44D215D4.6000809@lanl.gov>
	<20060803160916.GA19626@coresystems.de>
Message-ID: <20060803162206.GA21860@coresystems.de>

* Stefan Reinauer <stepan at coresystems.de> [060803 18:09]:
> * Ronald G Minnich <rminnich at lanl.gov> [060803 17:27]:
> > stefan, if this patch is ok with you, it's ok with me too.
>  
> The CONFIG_PRECOMPRESSED_ROM_STREAM patch is fine. No curlicues but ok
> to commit. A cleaner version would be to autodetect if the nrv2b stream
> is already compressed. But:
>  - nrv2b would need to be extended
>  - we have lzma in mind anyways
>  - the patch is simple

Applied.



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Aug  3 18:48:46 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 3 Aug 2006 18:48:46 +0200
Subject: [LinuxBIOS] [PATCH] Geode LX changes
In-Reply-To: <44D0EAFF.1050905@artecdesign.ee>
References: <44D0EAFF.1050905@artecdesign.ee>
Message-ID: <20060803164846.GA6842@coresystems.de>

commited.

* Indrek Kruusa <indrek.kruusa at artecdesign.ee> [060802 20:12]:
> Changelog:
> 
> * src/cpu/amd/model_lx/model_lx_init.c
>    L2 cache initialization removed (moved to northbridge.c)
> 
> * src/include/cpu/amd/lxdef.h
>    more checked values
> 
> * src/northbridge/amd/lx/northbridge.c
>    L2 cache initialization added
>    cpubug() commented out
> 
> * src/northbridge/amd/lx/raminit.c
>    empty function sdram_set_registers() is in use, don't remove
> 
> 
> Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>
> Signed-off-by: Andrei Birjukov <andrei.birjukov at artecdesign.ee>
 


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Aug  3 18:50:07 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 3 Aug 2006 18:50:07 +0200
Subject: [LinuxBIOS] [PATCH] Changes for artecgroup/dbe61
In-Reply-To: <44D0EDB8.2050402@artecdesign.ee>
References: <44D0EDB8.2050402@artecdesign.ee>
Message-ID: <20060803165007.GB6842@coresystems.de>

committed.

* Indrek Kruusa <indrek.kruusa at artecdesign.ee> [060802 20:23]:
> Changelog:
> 
> * src/mainboard/artecgroup/dbe61/Config.lb
>    irqmap changes
> 
> * src/mainboard/artecgroup/dbe61/irq_tables.c
>    tentative changes to irq table (currently not in use)
> 
> * src/mainboard/artecgroup/dbe61/mainboard.c
>    irq assigned manually to NIC
> 
> * src/mainboard/artecgroup/dbe61/Options.lb
>    gcc 4.0 is OK
> 
> * targets/artecgroup/dbe61/Config.lb
>    64K for VSA is OK at moment
> 
> 
> Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>
> Signed-off-by: Andrei Birjukov <andrei.birjukov at artecdesign.ee>


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From info at coresystems.de  Thu Aug  3 18:57:42 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 03 Aug 2006 18:57:42 +0200
Subject: [LinuxBIOS] LinuxBIOS r2359 build changes
Message-ID: <E1G8gVy-0006jO-Q5@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2359 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
slightly changed C.D. Hailfinger's precompressed rom stream patch

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From stepan at coresystems.de  Thu Aug  3 18:57:58 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 3 Aug 2006 18:57:58 +0200
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <44D0F0CF.2050308@artecdesign.ee>
References: <44D0F0CF.2050308@artecdesign.ee>
Message-ID: <20060803165758.GC6842@coresystems.de>


Why is this one needed? Which of the defines actually break the tree?
Can't you #define GX2_FOO and LX_FOO instead of FOO and use it based on
some compile time or runtime test?

> diff -u -r -b -B LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 
> LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536.c
> --- LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c     2006-07-22 
> 02:21:01.000000000 +0300
> +++ LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536.c 2006-07-31 
> 17:53:04.000000000 +0300
> @@ -5,7 +5,7 @@
>  #include <device/pci_ops.h>
>  #include <device/pci_ids.h>
>  #include <console/console.h>
> -#include <cpu/amd/gx2def.h>
> +#include <cpu/amd/lxdef.h>
>  #include <cpu/x86/msr.h>
>  #include "chip.h"
 

the next one is simple. it is included from here:
 src/mainboard/amd/rumba/auto.c
 src/mainboard/olpc/rev_a/auto.c
 src/mainboard/artecgroup/dbe61/auto.c

so these 3 should be patched to include gx2def.h or lxdef.h accordingly
before including cs5536_early_setup.c

> LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 
> LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536_early_setup.c
> --- LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 
> 2006-07-27 07:05:43.000000000 +0300
> +++ LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536_early_setup.c     
> 2006-07-31 17:52:52.000000000 +0300
> @@ -1,4 +1,4 @@
> -#include <cpu/amd/gx2def.h>
> +#include <cpu/amd/lxdef.h>
 
-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From info at coresystems.de  Thu Aug  3 19:36:53 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 03 Aug 2006 19:36:53 +0200
Subject: [LinuxBIOS] LinuxBIOS r2360 build changes
Message-ID: <E1G8h7t-0001LO-Ow@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2360 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Changelog:* src/cpu/amd/model_lx/model_lx_init.c  L2 cache initialization removed (moved to northbridge.c)* src/include/cpu/amd/lxdef.h  more checked values* src/northbridge/amd/lx/northbridge.c  L2 cache initialization added  cpubug() commented out* src/northbridge/amd/lx/raminit.c  empty function sdram_set_registers() is in use, don't remove* src/mainboard/artecgroup/dbe61/Config.lb  irqmap changes* src/mainboard/artecgroup/dbe61/irq_tables.c  tentative changes to irq table (currently not in use)* src/mainboard/artecgroup/dbe61/mainboard.c  irq assigned manually to NIC* src/mainboard/artecgroup/dbe61/Options.lb  gcc 4.0 is OK* targets/artecgroup/dbe61/Config.lb  64K for VSA is OK at momentSigned-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>Signed-off-by: Andrei Birjukov <andrei.birjukov at artecdesign.ee>

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From rminnich at lanl.gov  Thu Aug  3 21:46:03 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 03 Aug 2006 13:46:03 -0600
Subject: [LinuxBIOS] [PATCH] Geode LX changes
In-Reply-To: <20060803164846.GA6842@coresystems.de>
References: <44D0EAFF.1050905@artecdesign.ee>
	<20060803164846.GA6842@coresystems.de>
Message-ID: <44D2527B.9080400@lanl.gov>

Stefan Reinauer wrote:
> commited.
> 
> * Indrek Kruusa <indrek.kruusa at artecdesign.ee> [060802 20:12]:
> 
>>Changelog:
>>
>>* src/cpu/amd/model_lx/model_lx_init.c
>>   L2 cache initialization removed (moved to northbridge.c)
>>
>>* src/include/cpu/amd/lxdef.h
>>   more checked values
>>
>>* src/northbridge/amd/lx/northbridge.c
>>   L2 cache initialization added
>>   cpubug() commented out
>>
>>* src/northbridge/amd/lx/raminit.c
>>   empty function sdram_set_registers() is in use, don't remove
>>
>>
>>Signed-off-by: Indrek Kruusa <indrek.kruusa at artecdesign.ee>
>>Signed-off-by: Andrei Birjukov <andrei.birjukov at artecdesign.ee>
> 
>  
> 
> 

Thank you!

ron



From rminnich at lanl.gov  Thu Aug  3 21:55:36 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 03 Aug 2006 13:55:36 -0600
Subject: [LinuxBIOS] Not so good news (Was: good news)
In-Reply-To: <20060803160413.GE30215@cosmic.amd.com>
References: <20060731211450.183750@gmx.net>
	<20060731221138.GB23596@cosmic.amd.com>
	<44CEBFAF.6060402@lanl.gov> <20060801131955.181340@gmx.net>
	<20060801143545.181320@gmx.net>
	<20060801173319.GD13756@cosmic.amd.com>
	<44D01006.4020809@lanl.gov> <20060802161101.216680@gmx.net>
	<20060802162632.GA11524@coresystems.de>
	<20060803062437.59500@gmx.net>
	<20060803160413.GE30215@cosmic.amd.com>
Message-ID: <44D254B8.2070704@lanl.gov>

Jordan Crouse wrote:

> Ron - you'll have to decide if you want to apply this to LinuxBIO or not -
> and then we'll just use the new revision.

There's no problem applying these patches.

I go with a fixed rev of linuxbios for OLPC because I want to avoid the 
'broken tip of tree' experience. Every once in a while somebody busts a 
linuxbios build for a given platform due to things you can't always 
foresee. So, by using a fixed version of linuxbios, we can ensure that 
anyone who uses buildrom is guaranteed to get a working flash image.


> 
> This scares me - I don't like that we can't easily control the behavior here
> without patches (that would have to be updated every time we change 
> revisions).
>

I think I'm not sure what you mean. Our goal should be to have a 
known-good, patch-free svn rev of linuxbios to use for buildrom.

I don't like local patches.

ron



From samghost at mpx.net  Thu Aug  3 22:36:04 2006
From: samghost at mpx.net (Sam Brightman)
Date: Thu, 03 Aug 2006 22:36:04 +0200
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
Message-ID: <20060803203604.32272.qmail@customer.mpex.net>

Hello, 

I was wondering if someone could tell me whether LinuxBIOS will work with my 
setup (details below). At the moment I'm only hoping that flashrom works, as 
I have an updated BIOS from Asus but I'd also like to play with LinuxBIOS 
later. I've compiled and run flashrom -V from the "latest snapshot" link 
with nothing being detected. Details: 

Asus P2B - Intel i440BX (Pentium II 400MHz)
Award BIOS
Winbond W83977TF-AW (SuperIO/Flash Chip?? Nearest to BIOS) 

Below is the lcpci output. 

0000:00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host 
bridge (rev 03)
0000:00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP 
bridge (rev 03)
0000:00:04.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02)
0000:00:04.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 
01)
0000:00:04.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 
01)
0000:00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02)
0000:00:0b.0 Ethernet controller: 3Com Corporation 3c900 10Mbps Combo 
[Boomerang]
0000:01:00.0 VGA compatible controller: ATI Technologies Inc Radeon RV100 QY 
[Radeon 7000/VE] 

Any help appreciated, 


-- 
sam brightman



From uwe at hermann-uwe.de  Fri Aug  4 00:05:02 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Aug 2006 00:05:02 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060801120221.GA17269@coresystems.de>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
Message-ID: <20060803220502.GA18987@aragorn>

Hi,

On Tue, Aug 01, 2006 at 02:02:21PM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [060801 01:57]:
> > Yes, that's what I was guessing. It should return the vendor
> > and device ID (0xDA, 0x0B), correct?
>  
> Yes, exactly.

I still had no luck with flashrom. I tried both chips on another computer
now, same results. I also tried a PLCC chip (AM29F040B-120JC) on a third
computer, same result too (0xFF for all queries).

This seems really strange - could it be that the chips are not only
"empty" but also do not have an ID hardcoded in them? I.e. is it
possible that the 0xFF is actually correct? If so, I could skip the
vendor ID check and just try/force writing, maybe...


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060804/d3a1ef01/attachment.sig>

From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  4 00:05:32 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel U. Hailfinger)
Date: Fri, 04 Aug 2006 00:05:32 +0200
Subject: [LinuxBIOS] [OLPC-devel] Re: Not so good news (Was: good news)
In-Reply-To: <20060803162206.GA21860@coresystems.de>
References: <44CEBFAF.6060402@lanl.gov> <20060801131955.181340@gmx.net>
	<20060801143545.181320@gmx.net>	<20060801173319.GD13756@cosmic.amd.com>
	<44D01006.4020809@lanl.gov> <20060802161101.216680@gmx.net>
	<20060802162632.GA11524@coresystems.de>	<20060803062437.59500@gmx.net>
	<44D215D4.6000809@lanl.gov>	<20060803160916.GA19626@coresystems.de>
	<20060803162206.GA21860@coresystems.de>
Message-ID: <20060803220532.81150@gmx.net>

Stefan Reinauer wrote:
> * Stefan Reinauer <stepan at coresystems.de> [060803 18:09]:
> > * Ronald G Minnich <rminnich at lanl.gov> [060803 17:27]:
> > > stefan, if this patch is ok with you, it's ok with me too.
> >  
> > The CONFIG_PRECOMPRESSED_ROM_STREAM patch is fine. No curlicues but ok
> > to commit. A cleaner version would be to autodetect if the nrv2b stream
> > is already compressed. But:
> >  - nrv2b would need to be extended
> >  - we have lzma in mind anyways
> >  - the patch is simple
> 
> Applied.

Thanks!

Regards,
Carl-Daniel
-- 


Echte DSL-Flatrate dauerhaft f?r 0,- Euro*. Nur noch kurze Zeit!
"Feel free" mit GMX DSL: http://www.gmx.net/de/go/dsl



From stepan at coresystems.de  Fri Aug  4 00:43:45 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 4 Aug 2006 00:43:45 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060803220502.GA18987@aragorn>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
Message-ID: <20060803224345.GC5055@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060804 00:05]:
> This seems really strange - could it be that the chips are not only
> "empty" but also do not have an ID hardcoded in them? I.e. is it
> possible that the 0xFF is actually correct? If so, I could skip the
> vendor ID check and just try/force writing, maybe...

I don't believe so. ("But I would not bet my leg for it either")

Basically if you can't ID a chip, you can't write to it either.

Some board vendors, Asus is known to be one of them, secure their boards
from "flash viruses" (did they mean linuxbios?) with additional GPIO linux
This kind of stuff requires reverse engineering (which was legal in
Germany last time I had to do this) or a loooot of patience talking to
sales reps.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From rminnich at lanl.gov  Fri Aug  4 00:41:33 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 03 Aug 2006 16:41:33 -0600
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060803220502.GA18987@aragorn>
References: <20060731180409.GA13592@aragorn>	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>	<20060731233623.GA7869@aragorn>	<20060731234151.GA25670@coresystems.de>	<20060731235718.GC7869@aragorn>	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
Message-ID: <44D27B9D.3070509@lanl.gov>

Uwe Hermann wrote:

> 
> This seems really strange - could it be that the chips are not only
> "empty" but also do not have an ID hardcoded in them? 

no, that is definitely not in the cards.

There is something really bad going on .

ron




From smithbone at gmail.com  Fri Aug  4 01:11:47 2006
From: smithbone at gmail.com (Richard Smith)
Date: Thu, 3 Aug 2006 18:11:47 -0500
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060803224345.GC5055@coresystems.de>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
Message-ID: <8a0c36780608031611p7b7def9bu476cbd13502fb854@mail.gmail.com>

On 8/3/06, Stefan Reinauer <stepan at coresystems.de> wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [060804 00:05]:
> > This seems really strange - could it be that the chips are not only

Uwe.  What kind of hardware tools to you have available?  Do you have
access to an Oscope?

-- 
Richard A. Smith



From uwe at hermann-uwe.de  Fri Aug  4 03:45:48 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Aug 2006 03:45:48 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060803224345.GC5055@coresystems.de>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
Message-ID: <20060804014548.GA30639@aragorn>

Hi,

On Fri, Aug 04, 2006 at 12:43:45AM +0200, Stefan Reinauer wrote:
> Basically if you can't ID a chip, you can't write to it either.

I'll try some more computers I have access to. If I find one which
_does_ get the ID correctly I know it's a problem with the board
and not with the chips themselves.


> Some board vendors, Asus is known to be one of them, secure their boards
> from "flash viruses" (did they mean linuxbios?) with additional GPIO linux
> This kind of stuff requires reverse engineering (which was legal in
> Germany last time I had to do this) or a loooot of patience talking to
> sales reps.

Can some of the programs in util/ be used to find out whether or not such
GPIOs could be in place?


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060804/15e06e2a/attachment.sig>

From uwe at hermann-uwe.de  Fri Aug  4 03:56:38 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Aug 2006 03:56:38 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <8a0c36780608031611p7b7def9bu476cbd13502fb854@mail.gmail.com>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<8a0c36780608031611p7b7def9bu476cbd13502fb854@mail.gmail.com>
Message-ID: <20060804015638.GB30639@aragorn>

Hi,

On Thu, Aug 03, 2006 at 06:11:47PM -0500, Richard Smith wrote:
> Uwe.  What kind of hardware tools to you have available?  Do you have
> access to an Oscope?

Not usually, but I might be able to get access to one from time to time.
What can I do/check if I have one?

I do not currently have a POST card, but intend to get one. I should
be able to setup a serial connection.

Say I manage to flash targets/bitworks/ims/ims/fallback/linuxbios.rom
(that's the only ims image <= 256K, so I'll have to use it as my chips are
256K, is that correct?), connect a serial cable on ttyS0 (ttyS1?),
115200 Baud, 8N1. Should I be able to get some debug output with the
current code in svn?


P.S. no need to CC me, I'm subscribed.

Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060804/97089cce/attachment.sig>

From smithbone at gmail.com  Fri Aug  4 04:11:25 2006
From: smithbone at gmail.com (Richard Smith)
Date: Thu, 3 Aug 2006 21:11:25 -0500
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060804015638.GB30639@aragorn>
References: <20060731180409.GA13592@aragorn>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<8a0c36780608031611p7b7def9bu476cbd13502fb854@mail.gmail.com>
	<20060804015638.GB30639@aragorn>
Message-ID: <8a0c36780608031911o2d706355w19a60fb92e4e00a9@mail.gmail.com>

> > Uwe.  What kind of hardware tools to you have available?  Do you have
> > access to an Oscope?
>
> Not usually, but I might be able to get access to one from time to time.
> What can I do/check if I have one?

You can watch the write line on the chip and see if its getting
asserted.  Then you know for sure if its flash chip or chipset.

> Say I manage to flash targets/bitworks/ims/ims/fallback/linuxbios.rom
> (that's the only ims image <= 256K, so I'll have to use it as my chips are
> 256K, is that correct?), connect a serial cable on ttyS0 (ttyS1?),

The IMS config is setup for a 29f040b which is a 512k part. Did you
change the rom size in the config file?   But yes your rom size needs
to match your chips.

> 115200 Baud, 8N1. Should I be able to get some debug output with the
> current code in svn?

Yes you will get some boot messages and it will try to dump the spd contents.

-- 
Richard A. Smith



From dpw at email.cs.arizona.edu  Fri Aug  4 07:23:02 2006
From: dpw at email.cs.arizona.edu (Don Waugaman)
Date: Thu, 03 Aug 2006 22:23:02 -0700
Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L
In-Reply-To: <8a0c36780608030813u7ffcabchb63fc921a02456ff@mail.gmail.com>
References: <1154140868.9333.47.camel@cslewis>
	<8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com>
	<8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
	<1154540726.4537.17.camel@cslewis>
	<8a0c36780608021630n6bcdb593wd9a6ca192a4ae6a7@mail.gmail.com>
	<8a0c36780608030813u7ffcabchb63fc921a02456ff@mail.gmail.com>
Message-ID: <1154668982.6058.11.camel@cslewis>

On Thu, 2006-08-03 at 10:13 -0500, Richard Smith wrote:
> > hardware smbus problems.  Which is good.
> > I've still got that p2b so I'll test and see if I get the same results as you.
> >
> 
> I pulled out my old p2b board and manged to find all the stuff to make
> it boot.  Then ran the current V2 p2b target build.
> 
> Indeed it dumps the SPD out just fine.  So yah!  Thats good news.  My
> V1 stuff must have had some other issue that kept the RAM from getting
> detected properly.

Good to hear you're getting the same results!

Since you straightened me on what to expect, I went ahead and changed
the southbridge/i440bx to i82371eb, and recompiled all the 440bx targets
I could find (successfully, except that the eaglelion/5bcm tried to look
for a payload under /home/hamish, which for some reason didn't exist on
my system :-).  I've attached a patch for this - could you review and
commit for me?  I think it may require some svn magic to copy/remove the
old 440bx directory and files - I'm not sure how well just applying the
diffs here will work (I'm an svn newbie).

I'll tackle rebasing the RAM init on the e7501 next.

Thanks,

Don


-------------- next part --------------
A non-text attachment was scrubbed...
Name: i82371eb.patch
Type: text/x-patch
Size: 13862 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060803/b7d609bb/attachment.patch>

From ilpadrino at dodo.com.au  Fri Aug  4 06:06:27 2006
From: ilpadrino at dodo.com.au (ilpadrino)
Date: Fri, 4 Aug 2006 12:06:27 +0800
Subject: [LinuxBIOS] isa-486s
Message-ID: <000801c6b77b$5d170d10$0100a8c0@mine>

4865dx; isa-486s; accepts pci cards; 200w psu; 6 memory slots; no heatsink or fan; 2 cpu sockets; adjustable cache size 64k, 128k, 256k; maybe accepts one 8 bit card; combine disk drive serial io controller on seperate card;
tbase10 network card; seperate vga card;

not yet acquired linux boot disk; disk drive status dubious; 

1437F0055; SL82C461; 9133NAS batch no?;

U131050M; u131050m; D27C12; m,c,1988; 1501v0; 486 bios hi; 1990; "award software inc" original author; A4060337 batch no.; 28 pin large style dual inline package;

don't know manafacture could be written under stuff 3/4 of the motherboard is covered in drives and cards assorted and psu;

spare memory chips available; able to flash eproms;

ok 
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060804/65f0b869/attachment.html>

From smithbone at gmail.com  Fri Aug  4 08:41:42 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 4 Aug 2006 01:41:42 -0500
Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L
In-Reply-To: <1154668982.6058.11.camel@cslewis>
References: <1154140868.9333.47.camel@cslewis>
	<8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com>
	<8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
	<1154540726.4537.17.camel@cslewis>
	<8a0c36780608021630n6bcdb593wd9a6ca192a4ae6a7@mail.gmail.com>
	<8a0c36780608030813u7ffcabchb63fc921a02456ff@mail.gmail.com>
	<1154668982.6058.11.camel@cslewis>
Message-ID: <8a0c36780608032341p721be1c6kba531cd931154b23@mail.gmail.com>

> my system :-).  I've attached a patch for this - could you review and
> commit for me?

The diffs look good.  You got the idea.  However......

> I think it may require some svn magic to copy/remove the
> old 440bx directory and files - I'm not sure how well just applying the
> diffs here will work (I'm an svn newbie).

They won't apply. :(  The i8371eb/* files don't exist in the tree so
the patch that modifies them fails.

The reason doesn't appear to be your fault.   Did you use svn move or svn copy?
Reading the svn docs indicates that svn diff does _not_ understand
moves and copys.  That's listed as a post 1.0 feature.
So your diffs remove all the i440bx stuff but don't create the i82371eb files.

The rest of your diffs that modify existing config files are ok.

Looks like I'll have to do the remove of the old files.

I played around with a copy of the tree and here's how I think you
need to create the diffs for this instance.  Stefan? Ron? Do you have
any  suggestions?

1) Copy (filesystem cp not svn copy) your current i82371eb dir to i82371eb.orig
1.1) Look in i82371eb.orig and remove the .svn directory if there is one.
2) svn remove your i82371eb directory.  You may have to use the
--force option if it wines about uncommitted changes.
3) rm -rf your i440bx dir if it exists.
4) svn update.   Now you should be back to what you had before your
changes with an extra i82371eb.orig directory in there
5) mkdir i82371eb
6) cp i82371eb.orig/* i82371eb
7) svn add i82371eb
8) svn diff and send in the patch.

That should generate a diff that adds all the new files and keeps the
mods you made to the other config files.

I will then apply the patch to my local copy and if it all looks good
then I'll do a svn remove on the i440bx dir and commit.

-- 
Richard A. Smith



From smithbone at gmail.com  Fri Aug  4 08:47:23 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 4 Aug 2006 01:47:23 -0500
Subject: [LinuxBIOS] isa-486s
In-Reply-To: <000801c6b77b$5d170d10$0100a8c0@mine>
References: <000801c6b77b$5d170d10$0100a8c0@mine>
Message-ID: <8a0c36780608032347v7c0d9179x7077f2ed8c9a6012@mail.gmail.com>

> U131050M; u131050m; D27C12; m,c,1988; 1501v0; 486 bios hi; 1990; "award
> software inc" original author; A4060337 batch no.; 28 pin large style dual
> inline package;
>
> don't know manafacture could be written under stuff 3/4 of the motherboard
> is covered in drives and cards assorted and psu;

If you are asking about LinuxBios support then you need to get Linux
up on it and do an lspci -v  But considering the age its very doubtful
you can get the docs for the chipsets.

-- 
Richard A. Smith



From a.borisov at tesv.tmb.ru  Fri Aug  4 08:53:21 2006
From: a.borisov at tesv.tmb.ru (Anton Borisov)
Date: Fri, 4 Aug 2006 10:53:21 +0400
Subject: [LinuxBIOS] isa-486s
In-Reply-To: <8a0c36780608032347v7c0d9179x7077f2ed8c9a6012@mail.gmail.com>
References: <000801c6b77b$5d170d10$0100a8c0@mine>
	<8a0c36780608032347v7c0d9179x7077f2ed8c9a6012@mail.gmail.com>
Message-ID: <20060804105321.639cf917.a.borisov@tesv.tmb.ru>

On Fri, 4 Aug 2006 01:47:23 -0500
"Richard Smith" <smithbone at gmail.com> wrote:

> > U131050M; u131050m; D27C12; m,c,1988; 1501v0; 486 bios hi; 1990; "award
> > software inc" original author; A4060337 batch no.; 28 pin large style dual
> > inline package;
> >
> > don't know manafacture could be written under stuff 3/4 of the motherboard
> > is covered in drives and cards assorted and psu;
> 
> If you are asking about LinuxBios support then you need to get Linux
> up on it and do an lspci -v  But considering the age its very doubtful
> you can get the docs for the chipsets.

	Richard, this looks like a spam.


-Anton



From smithbone at gmail.com  Fri Aug  4 09:29:28 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 4 Aug 2006 02:29:28 -0500
Subject: [LinuxBIOS] isa-486s
In-Reply-To: <20060804105321.639cf917.a.borisov@tesv.tmb.ru>
References: <000801c6b77b$5d170d10$0100a8c0@mine>
	<8a0c36780608032347v7c0d9179x7077f2ed8c9a6012@mail.gmail.com>
	<20060804105321.639cf917.a.borisov@tesv.tmb.ru>
Message-ID: <8a0c36780608040029r2b50d2d0l4771555d2df0162d@mail.gmail.com>

> > up on it and do an lspci -v  But considering the age its very doubtful
> > you can get the docs for the chipsets.
>
>         Richard, this looks like a spam.

Yeah.  I think you are right..    I tried hard to accept that it was
just really broken english.  Oh well thats why I use gmail, hopefully
it will hold up to a spammer picking up my e-mail.

-- 
Richard A. Smith



From stepan at coresystems.de  Fri Aug  4 09:53:54 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 4 Aug 2006 09:53:54 +0200
Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L
In-Reply-To: <8a0c36780608032341p721be1c6kba531cd931154b23@mail.gmail.com>
References: <1154140868.9333.47.camel@cslewis>
	<8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com>
	<8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
	<1154540726.4537.17.camel@cslewis>
	<8a0c36780608021630n6bcdb593wd9a6ca192a4ae6a7@mail.gmail.com>
	<8a0c36780608030813u7ffcabchb63fc921a02456ff@mail.gmail.com>
	<1154668982.6058.11.camel@cslewis>
	<8a0c36780608032341p721be1c6kba531cd931154b23@mail.gmail.com>
Message-ID: <20060804075354.GA32715@coresystems.de>

* Richard Smith <smithbone at gmail.com> [060804 08:41]:
> > I think it may require some svn magic to copy/remove the
> > old 440bx directory and files - I'm not sure how well just applying the
> > diffs here will work (I'm an svn newbie).
> 
> They won't apply. :(  The i8371eb/* files don't exist in the tree so
> the patch that modifies them fails.
 
Grr ;-) Never cut and paste from emails.. it's the 82371eb ;-))

> So your diffs remove all the i440bx stuff but don't create the i82371eb files.

I renamed the files in the tree, to enable clean diffs here. It's
untested and may fail, but it should make things easier. 

Can you please send a diff against r2363?

Hope this helps ..

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Fri Aug  4 09:59:16 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 4 Aug 2006 09:59:16 +0200
Subject: [LinuxBIOS] isa-486s
In-Reply-To: <8a0c36780608040029r2b50d2d0l4771555d2df0162d@mail.gmail.com>
References: <000801c6b77b$5d170d10$0100a8c0@mine>
	<8a0c36780608032347v7c0d9179x7077f2ed8c9a6012@mail.gmail.com>
	<20060804105321.639cf917.a.borisov@tesv.tmb.ru>
	<8a0c36780608040029r2b50d2d0l4771555d2df0162d@mail.gmail.com>
Message-ID: <20060804075916.GA7460@coresystems.de>

* Richard Smith <smithbone at gmail.com> [060804 09:29]:
> > > up on it and do an lspci -v  But considering the age its very doubtful
> > > you can get the docs for the chipsets.
> >
> >         Richard, this looks like a spam.
> 
> Yeah.  I think you are right..    I tried hard to accept that it was
> just really broken english.  Oh well thats why I use gmail, hopefully
> it will hold up to a spammer picking up my e-mail.

sorry for letting this through. I was really uncertain. Seems these
spammers are improving on random text generation algorithms by now. 
I just wonder what for.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From smithbone at gmail.com  Fri Aug  4 10:04:11 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 4 Aug 2006 03:04:11 -0500
Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L
In-Reply-To: <20060804075354.GA32715@coresystems.de>
References: <1154140868.9333.47.camel@cslewis>
	<8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com>
	<8a0c36780607291053r2f431e0yfeac04575bf87089@mail.gmail.com>
	<1154540726.4537.17.camel@cslewis>
	<8a0c36780608021630n6bcdb593wd9a6ca192a4ae6a7@mail.gmail.com>
	<8a0c36780608030813u7ffcabchb63fc921a02456ff@mail.gmail.com>
	<1154668982.6058.11.camel@cslewis>
	<8a0c36780608032341p721be1c6kba531cd931154b23@mail.gmail.com>
	<20060804075354.GA32715@coresystems.de>
Message-ID: <8a0c36780608040104n3f007d5es643db753ccf9a120@mail.gmail.com>

 > I renamed the files in the tree, to enable clean diffs here. It's
> untested and may fail, but it should make things easier.
>
> Can you please send a diff against r2363?
>
> Hope this helps ..

Thanks.  Looks like it will work to me and should clean up the diffs.
Don had indicated that he wanted to do the diffs to start comming up
to speed on things.  So thats why I just didn't do the renames myself.
 I was going to let him go back through the process as an exercise to
the reader. :)

But theres plenty more to do so on to the next.

-- 
Richard A. Smith



From smithbone at gmail.com  Fri Aug  4 10:08:05 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 4 Aug 2006 03:08:05 -0500
Subject: [LinuxBIOS] isa-486s
In-Reply-To: <20060804075916.GA7460@coresystems.de>
References: <000801c6b77b$5d170d10$0100a8c0@mine>
	<8a0c36780608032347v7c0d9179x7077f2ed8c9a6012@mail.gmail.com>
	<20060804105321.639cf917.a.borisov@tesv.tmb.ru>
	<8a0c36780608040029r2b50d2d0l4771555d2df0162d@mail.gmail.com>
	<20060804075916.GA7460@coresystems.de>
Message-ID: <8a0c36780608040108w6117edc3i53fd1919e15bc9ea@mail.gmail.com>

> sorry for letting this through. I was really uncertain. Seems these
> spammers are improving on random text generation algorithms by now.
> I just wonder what for.
>

I read somewhere that a lot of that is to try and get addresses.  Get
back and actual response to the mail and chances are it was looked at
by a human.  Bump the address up to the verified level.

I'll let you know if my spam goes up :)  Gmail is pretty darn good though.

-- 
Richard A. Smith



From info at coresystems.de  Fri Aug  4 10:24:15 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 04 Aug 2006 10:24:15 +0200
Subject: [LinuxBIOS] LinuxBIOS r2361 build changes
Message-ID: <E1G8uyd-0003vw-1m@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2361 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
rename southbridge i440bx to its actual name i8371eb

Build Log:
 Compilation of artecgroup:dbe61 is still broken. Compilation of asus:p2b has been broken

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From info at coresystems.de  Fri Aug  4 11:04:51 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 04 Aug 2006 11:04:51 +0200
Subject: [LinuxBIOS] LinuxBIOS r2362 build changes
Message-ID: <E1G8vbv-0004Y9-F2@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2362 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
ouch. it's 8_2_371. I'll fix it. This commit breaks compilation

Build Log:
 Compilation of artecgroup:dbe61 is still broken. Compilation of asus:p2b is still broken. Compilation of bitworks:ims has been broken

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From stepan at coresystems.de  Fri Aug  4 11:16:35 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 4 Aug 2006 11:16:35 +0200
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
In-Reply-To: <20060803203604.32272.qmail@customer.mpex.net>
References: <20060803203604.32272.qmail@customer.mpex.net>
Message-ID: <20060804091635.GA20192@coresystems.de>

* Sam Brightman <samghost at mpx.net> [060803 22:36]:
> Hello, 
> 
> I was wondering if someone could tell me whether LinuxBIOS will work with my 
> setup (details below). At the moment I'm only hoping that flashrom works, as 
> I have an updated BIOS from Asus but I'd also like to play with LinuxBIOS 
> later. I've compiled and run flashrom -V from the "latest snapshot" link 
> with nothing being detected.

Can you post the output?

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From info at coresystems.de  Fri Aug  4 12:28:27 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 04 Aug 2006 12:28:27 +0200
Subject: [LinuxBIOS] LinuxBIOS r2363 build changes
Message-ID: <E1G8wup-00077y-I7@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2363 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
final rename orgy. sorry for the inconvenience. This should fix it again

Build Log:
 Compilation of artecgroup:dbe61 is still broken. Compilation of asus:p2b is still broken. Compilation of bitworks:ims has been fixed.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From samghost at mpx.net  Fri Aug  4 12:34:21 2006
From: samghost at mpx.net (Sam Brightman)
Date: Fri, 04 Aug 2006 11:34:21 +0100
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
In-Reply-To: <20060804091635.GA20192@coresystems.de>
References: <20060803203604.32272.qmail@customer.mpex.net>
	<20060804091635.GA20192@coresystems.de>
Message-ID: <44D322AD.8070107@mpx.net>

Stefan Reinauer wrote:

> * Sam Brightman <samghost at mpx.net> [060803 22:36]:
>> Hello, 
>>
>> I was wondering if someone could tell me whether LinuxBIOS will work with my 
>> setup (details below). At the moment I'm only hoping that flashrom works, as 
>> I have an updated BIOS from Asus but I'd also like to play with LinuxBIOS 
>> later. I've compiled and run flashrom -V from the "latest snapshot" link 
>> with nothing being detected.
> 
> Can you post the output?

I can indeed, but my home PC has changed its darn IP address so I'll 
have to send it this evening (UK time) when I can access it.

-- 
sam brightman



From indrek.kruusa at artecdesign.ee  Fri Aug  4 17:18:35 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Fri, 04 Aug 2006 18:18:35 +0300
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <20060803165758.GC6842@coresystems.de>
References: <44D0F0CF.2050308@artecdesign.ee>
	<20060803165758.GC6842@coresystems.de>
Message-ID: <44D3654B.2050800@artecdesign.ee>

Stefan Reinauer wrote:
> Why is this one needed? Which of the defines actually break the tree?
> Can't you #define GX2_FOO and LX_FOO instead of FOO and use it based on
> some compile time or runtime test?
>
>   
>> diff -u -r -b -B LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 
>> LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536.c
>> --- LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c     2006-07-22 
>> 02:21:01.000000000 +0300
>> +++ LinuxBIOSv2_cp1/src/southbridge/amd/cs5536/cs5536.c 2006-07-31 
>> 17:53:04.000000000 +0300
>> @@ -5,7 +5,7 @@
>>  #include <device/pci_ops.h>
>>  #include <device/pci_ids.h>
>>  #include <console/console.h>
>> -#include <cpu/amd/gx2def.h>
>> +#include <cpu/amd/lxdef.h>
>>  #include <cpu/x86/msr.h>
>>  #include "chip.h"
>>     
>  
>   

Yes - and the question was what should be that compile time test.

> the next one is simple. it is included from here:
>  src/mainboard/amd/rumba/auto.c
>  src/mainboard/olpc/rev_a/auto.c
>  src/mainboard/artecgroup/dbe61/auto.c
>
> so these 3 should be patched to include gx2def.h or lxdef.h accordingly
> before including cs5536_early_setup.c
>   

This is OK for me.

Question about OLPC: if memtest is set as payload then is it works? We 
have got dbe61 up and running after some ram_resource() hacking. With 
ehterbooted Linux the thing is still totally quiet.

thanks,
Indrek




From smithbone at gmail.com  Fri Aug  4 18:37:09 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 4 Aug 2006 11:37:09 -0500
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <44D3654B.2050800@artecdesign.ee>
References: <44D0F0CF.2050308@artecdesign.ee>
	<20060803165758.GC6842@coresystems.de>
	<44D3654B.2050800@artecdesign.ee>
Message-ID: <8a0c36780608040937m4519663bs87fe9b3974741167@mail.gmail.com>

>
> Question about OLPC: if memtest is set as payload then is it works? We
> have got dbe61 up and running after some ram_resource() hacking. With
> ehterbooted Linux the thing is still totally quiet.

I've not tried memtest on OLPC.  Ron may have.  I can test later on
tonight if you wish. I'm CDT. So it will be in 6 or so hours.

-- 
Richard A. Smith



From samghost at mpx.net  Fri Aug  4 19:02:30 2006
From: samghost at mpx.net (Sam Brightman)
Date: Fri, 04 Aug 2006 19:02:30 +0200
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
In-Reply-To: <44D322AD.8070107@mpx.net>
References: <20060803203604.32272.qmail@customer.mpex.net>
	<20060804091635.GA20192@coresystems.de> <44D322AD.8070107@mpx.net>
Message-ID: <20060804170230.11139.qmail@customer.mpex.net>

Hmm... not change of IP. Must remember to feed electricity meter! 

Anyway, here is the output: 

sam at wildthing:~/dev/LinuxBIOSv2/util/flashrom$ sudo ./flashrom -V
Password:
Calibrating delay loop... Setting up microsecond timing loop
188M loops per second
ok
No LinuxBIOS table found.
Trying Am29F040B, 512 KB
probe_29f040b: id1 0xff, id2 0xff
Trying Am29F016D, 2048 KB
probe_29f040b: id1 0xff, id2 0xff
Trying At29C040A, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying Mx29f002, 256 KB
probe_29f002: id1 0xff, id2 0xff
Trying SST29EE020A, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST28SF040A, 512 KB
probe_28sf040: id1 0xff, id2 0xff
Trying SST39SF010A, 128 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST39SF020A, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST39SF040, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST39VF020, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF040B, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF040, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF080A, 1024 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF002A/B, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF003A/B, 384 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF004A/B, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying SST49LF008A, 1024 KB
probe_jedec: id1 0xff, id2 0xff
Trying Pm49FL002, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying Pm49FL004, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying W29C011, 128 KB
probe_jedec: id1 0xff, id2 0xff
Trying W29C020C, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W49F002U, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W49V002A, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W49V002FA, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying W39V040A, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying W39V040B, 512 KB
probe_jedec: id1 0xff, id2 0xff
Trying M29F040B, 512 KB
probe_29f040b: id1 0xff, id2 0xff
Trying M29F400BT, 512 KB
probe_m29f400bt: id1 0xff, id2 0xff
Trying 82802ab, 512 KB
probe_82802ab: id1 0xff, id2 0xff
Trying 82802ac, 1024 KB
probe_82802ab: id1 0xff, id2 0xff
Trying F49B002UA, 256 KB
probe_jedec: id1 0xff, id2 0xff
Trying LHF00L04, 1024 KB
probe_lhf00l04: id1 0xff, id2 0xff
No EEPROM/flash device found. 


-- 
sam brightman 




From uwe at hermann-uwe.de  Fri Aug  4 22:44:10 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Aug 2006 22:44:10 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060804014548.GA30639@aragorn>
References: <20060731180409.GA13592@aragorn>
	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn>
Message-ID: <20060804204410.GB17104@aragorn>

Hi,

more tests, still no luck. I had access to a hardware flash/EEPROM programmer
today and flashed bitworks/ims/linuxbios.rom (256K this time, last time
it was 512K which obviously cannot work). The Windows-Software for the
programmer supported the chip (W49F002U) and reported that flashing
worked fine (verify succeeded, too).

Now, I tried to boot from that chip but cannot get serial output, it
seems (115200 Baud, 8N1, ttyS0).

I also tried to set the "reset BIOS" jumper on the board before running
"./flashrom -V", but it seems that doesn't help either. I'm slowly
running out of ideas.

Hm, say I accidentally killed the chips (ESD) somehow - would the result
be 0xFF's returned as vendor/device ID?


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060804/3c2e2442/attachment.sig>

From smithbone at gmail.com  Fri Aug  4 23:43:00 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 4 Aug 2006 16:43:00 -0500
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060804204410.GB17104@aragorn>
References: <20060731180409.GA13592@aragorn>
	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
Message-ID: <8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>

> today and flashed bitworks/ims/linuxbios.rom (256K this time, last time
> it was 512K which obviously cannot work). The Windows-Software for the
> programmer supported the chip (W49F002U) and reported that flashing
> worked fine (verify succeeded, too).

Your problem I think is the superIO.  The GA-6BXC uses an ITE it8671f
as the SuperIO and its not supported in V2.    IMS uses a nsc pc87351.

You have to fix up the superIO first or you won't ever get any output.

Did you port the superIO?

-- 
Richard A. Smith



From uwe at hermann-uwe.de  Sun Aug  6 21:52:15 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 6 Aug 2006 21:52:15 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
References: <9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
Message-ID: <20060806195215.GB27511@aragorn>

Hi,

On Fri, Aug 04, 2006 at 04:43:00PM -0500, Richard Smith wrote:
> Your problem I think is the superIO.  The GA-6BXC uses an ITE it8671f
> as the SuperIO and its not supported in V2.    IMS uses a nsc pc87351.

Indeed, that was the only remaining problem. I created a patch to add
support for the ITE it8671f in LinuxBIOSv2.

The setup_serial.inc is copied from v1, for the rest of the stuff I tried
to guess what's needed from other superios in v2. I haven't grasped
LinuxBIOS well enough to _really_ know what I'm doing ;)

Anyways, I managed to build an image (based on bitworks/ims) which
outputs something on the serial line:

LinuxBIOS-1.1.0-* starting...
BIST failed: 00000002

Please look over the preliminary patch (attached) and tell me about
obvious stupid errors I made.

Btw, is the following snippet needed in chip.h?

#ifndef SIO_COM1
#define SIO_COM1_BASE   0x3F8
#endif
#ifndef SIO_COM2
#define SIO_COM2_BASE   0x2F8
#endif

It's in many chip.h files in src/superio, but an 'rgrep SIO_COM *' shows
that it's only defined in these chip.h files but never used. Is this
some remainder from v1?

Also, who was the original author of the other files from which
I cut'n'pasted (superio.c, chip.h, it8671f_early_serial.c, ...)?
He/she needs to be added to the copyright header of the files.


My next steps are to prepare a patch for the motherboard, and to find
out if I can add support for more hardware devices (other than serial
port)...


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
diff -Naur src/superio/foo/it8671f/chip.h src/superio/ITE/it8671f/chip.h
--- src/superio/foo/it8671f/chip.h	1970-01-01 01:00:00.000000000 +0100
+++ src/superio/ITE/it8671f/chip.h	2006-08-06 21:18:48.000000000 +0200
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) xxxx ????
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8671F
+#define _SUPERIO_ITE_IT8671F
+
+// TODO: Unused?
+// #ifndef SIO_COM1
+// #define SIO_COM1_BASE   0x3F8
+// #endif
+// #ifndef SIO_COM2
+// #define SIO_COM2_BASE   0x2F8
+// #endif
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8671f_ops;
+
+struct superio_ITE_it8671f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif /* _SUPERIO_ITE_IT8671F */
+
diff -Naur src/superio/foo/it8671f/Config.lb src/superio/ITE/it8671f/Config.lb
--- src/superio/foo/it8671f/Config.lb	1970-01-01 01:00:00.000000000 +0100
+++ src/superio/ITE/it8671f/Config.lb	2006-08-06 21:18:48.000000000 +0200
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
diff -Naur src/superio/foo/it8671f/it8671f_early_serial.c src/superio/ITE/it8671f/it8671f_early_serial.c
--- src/superio/foo/it8671f/it8671f_early_serial.c	1970-01-01 01:00:00.000000000 +0100
+++ src/superio/ITE/it8671f/it8671f_early_serial.c	2006-08-06 21:18:48.000000000 +0200
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) xxxx ????
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8671f.h"
+
+static void it8671f_enable_serial(device_t dev, unsigned iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 1);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}
+
diff -Naur src/superio/foo/it8671f/it8671f.h src/superio/ITE/it8671f/it8671f.h
--- src/superio/foo/it8671f/it8671f.h	1970-01-01 01:00:00.000000000 +0100
+++ src/superio/ITE/it8671f/it8671f.h	2006-08-06 21:18:48.000000000 +0200
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) xxxx ????
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+// TODO: Untested, cut'n'pasted from some other file so it's probably wrong.
+// #define IT8671F_FDC  0x00 /* Floppy */
+// #define IT8671F_PP   0x01 /* Parallel port */
+#define IT8671F_SP2  0x02 /* Com2 */
+#define IT8671F_SP1  0x03 /* Com1 */
+// #define IT8671F_SWC  0x04
+// #define IT8671F_KBCM 0x05 /* Mouse */
+#define IT8671F_KBCK 0x06 /* Keyboard */
+// #define IT8671F_GPIO 0x07
+// #define IT8671F_ACB  0x08
+// #define IT8671F_FSCM 0x09
+// #define IT8671F_WDT  0x0A
+// #define IT8671F_GMP  0x0B
+// #define IT8671F_MIDI 0x0C
+// #define IT8671F_VLM  0x0D
+// #define IT8671F_TMS  0x0E
+
diff -Naur src/superio/foo/it8671f/setup_serial.inc src/superio/ITE/it8671f/setup_serial.inc
--- src/superio/foo/it8671f/setup_serial.inc	1970-01-01 01:00:00.000000000 +0100
+++ src/superio/ITE/it8671f/setup_serial.inc	2006-08-06 21:18:48.000000000 +0200
@@ -0,0 +1,154 @@
+/*
+ * Enable the peripheral devices on the IT8671F Super IO chip
+ */
+
+/* The base address is 0x3F0, 0x3bd or 0x370, depending on config bytes */
+
+#define SIO_BASE $0x3f0
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA  SIO_BASE+1
+
+#define SIO_READ(ldn, index) \
+	mov SIO_BASE, %dx	; \
+	mov $0x07, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	mov ldn, %al		; \
+	outb %al, %dx		; \
+	dec %dx			; \
+	mov index, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	inb %dx, %al		;
+
+#define SIO_WRITE(ldn, index, data) \
+	mov SIO_BASE, %dx	; \
+	mov $0x07, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	mov ldn, %al		; \
+	outb %al, %dx		; \
+	dec %dx			; \
+	mov index, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	mov data, %al		; \
+	outb %al, %dx		;
+
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0 */
+
+	/* Base address 0x3f0 :	 0x86 0x80 0x55 0x55 */
+	/* Base address 0x3bd :	 0x86 0x80 0x55 0xaa */
+	/* Base address 0x370 :	 0x86 0x80 0xaa 0x55 */
+		
+	mov $0x279, %dx
+	mov $0x86, %al
+	outb %al, %dx
+	mov $0x80, %al
+	outb %al, %dx
+	mov $0x55, %al
+	outb %al, %dx
+	mov $0x55, %al
+	outb %al, %dx
+
+	/* Enter the configuration state */
+
+	mov SIO_BASE, %dx
+
+	/* 6a, b5, da, ed : f6, fb, 7d, be */
+
+	mov $0x6a, %al
+	outb %al, %dx
+	mov $0xb5, %al
+	outb %al, %dx
+	mov $0xda, %al
+	outb %al, %dx
+	mov $0xed, %al
+	outb %al, %dx
+
+	mov $0xf6, %al
+	outb %al, %dx
+	mov $0xfb, %al
+	outb %al, %dx
+	mov $0x7d, %al
+	outb %al, %dx
+	mov $0xbe, %al
+	outb %al, %dx
+			
+	/* df, 6f, 37, 1b : 0d, 86, c3, 61 */
+
+	mov $0xdf, %al
+	outb %al, %dx
+	mov $0x6f, %al
+	outb %al, %dx
+	mov $0x37, %al
+	outb %al, %dx
+	mov $0x1b, %al
+	outb %al, %dx
+
+	mov $0x0d, %al
+	outb %al, %dx
+	mov $0x86, %al
+	outb %al, %dx
+	mov $0xc3, %al
+	outb %al, %dx
+	mov $0x61, %al
+	outb %al, %dx
+			
+	/* b0, 58, 2c, 16 : 8b, 45, a2, d1 */
+
+	mov $0xb0, %al
+	outb %al, %dx
+	mov $0x58, %al
+	outb %al, %dx
+	mov $0x2c, %al
+	outb %al, %dx
+	mov $0x16, %al
+	outb %al, %dx
+
+	mov $0x8b, %al
+	outb %al, %dx
+	mov $0x45, %al
+	outb %al, %dx
+	mov $0xa2, %al
+	outb %al, %dx
+	mov $0xd1, %al
+	outb %al, %dx
+
+	/* e8, 74, 3a, 9d : ce, e7, 73, 39 */
+
+	mov $0xe8, %al
+	outb %al, %dx
+	mov $0x74, %al
+	outb %al, %dx
+	mov $0x3a, %al
+	outb %al, %dx
+	mov $0x9d, %al
+	outb %al, %dx
+
+	mov $0xce, %al
+	outb %al, %dx
+	mov $0xe7, %al
+	outb %al, %dx
+	mov $0x73, %al
+	outb %al, %dx
+	mov $0x39, %al
+	outb %al, %dx
+
+	/* Enable parallel port, serial 1, serial port 2, Floppy */
+	
+	SIO_WRITE($0x00, $0x23, $0x0f)
+
+	/* Activate serial port 1 and 2 */
+
+	SIO_WRITE($0x01, $0x30, $0x1)
+	SIO_WRITE($0x02, $0x30, $0x1)
+
+	/* Select 24MHz CLKIN and clear software suspend mode */
+	
+	SIO_WRITE($0x00, $0x24, $0x00)
+
+	/* Exit the configuration state */
+
+	SIO_WRITE($0x00, $0x02, $0x02); 
diff -Naur src/superio/foo/it8671f/superio.c src/superio/ITE/it8671f/superio.c
--- src/superio/foo/it8671f/superio.c	1970-01-01 01:00:00.000000000 +0100
+++ src/superio/ITE/it8671f/superio.c	2006-08-06 21:21:22.000000000 +0200
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) xxxx ????
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+// #include <arch/io.h>
+// #include <device/device.h>
+// #include <device/pnp.h>
+// #include <console/console.h>
+// #include <string.h>
+// #include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "it8671f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8671f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch(dev->path.u.pnp.device) {
+	case IT8671F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8671F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8671F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+// TODO.
+static struct pnp_info pnp_dev_info[] = {
+// { &ops, IT8671F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
+// { &ops, IT8671F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, },
+ { &ops, IT8671F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, IT8671F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+// { &ops, IT8671F_SWC,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
+// { &ops, IT8671F_KBCM, PNP_IRQ0 },
+{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+// { &ops, IT8671F_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
+// { &ops, IT8671F_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
+// { &ops, IT8671F_RTC,  PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8671f_ops = {
+	CHIP_NAME("ITE it8671f")
+	.enable_dev = enable_dev,
+};
+
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060806/1f6b39d4/attachment.sig>

From uwe at hermann-uwe.de  Sun Aug  6 21:58:47 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 6 Aug 2006 21:58:47 +0200
Subject: [LinuxBIOS] Uniflash.
Message-ID: <20060806195847.GC27511@aragorn>

Hi,

I've stumbled over Uniflash recently (http://uniflash.org/) which is a
flashing program similar to flashrom.

I was lucky to find that I can use that to flash my W49F002U with that,
so I can now finally flash LinuxBIOS (and other) images.

The program is quite old, but supports lots of flash chips and
motherboards (http://uniflash.org/hardware.htm). As it has recently been GPL'd
I figure it might be interesting for LinuxBIOS in order to add support
for more chips (even though it's written in Pascal and is compiled to a
DOS *.exe file ;)

I'll try to figure out what it does that flashrom does not, in order to
be able to use flashrom; I'll post a patch for flashrom when I'm done.


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060806/4da30045/attachment.sig>

From indrek.kruusa at artecdesign.ee  Mon Aug  7 10:17:49 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Mon, 07 Aug 2006 11:17:49 +0300
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <8a0c36780608040937m4519663bs87fe9b3974741167@mail.gmail.com>
References: <44D0F0CF.2050308@artecdesign.ee>	
	<20060803165758.GC6842@coresystems.de>	
	<44D3654B.2050800@artecdesign.ee>
	<8a0c36780608040937m4519663bs87fe9b3974741167@mail.gmail.com>
Message-ID: <44D6F72D.8040707@artecdesign.ee>

Richard Smith wrote:
>>
>> Question about OLPC: if memtest is set as payload then is it works? We
>> have got dbe61 up and running after some ram_resource() hacking. With
>> ehterbooted Linux the thing is still totally quiet.
>
> I've not tried memtest on OLPC.  Ron may have.  I can test later on
> tonight if you wish. I'm CDT. So it will be in 6 or so hours.
>

Yes, I am very interested in your results. If you still have the 
possbility to test of course.

thanks,
Indrek




From juergen127 at kreuzholzen.de  Mon Aug  7 11:19:17 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Mon, 7 Aug 2006 11:19:17 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
Message-ID: <200608071119.17303.juergen127@kreuzholzen.de>

Hi all,

I try to write a native sound driver for the Geode GX1/5530a Companion chip. 
Problem here: The sound chip only generates SMI. Does anyone knows a trick or 
a chipset switch that let me forward this SMI to a regular IRQ?
Its too ugly to use a polling loop.... ;-)

Regards,
Juergen




From rminnich at lanl.gov  Mon Aug  7 16:36:50 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 07 Aug 2006 08:36:50 -0600
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060804204410.GB17104@aragorn>
References: <20060731180409.GA13592@aragorn>	<8a0c36780607311146g28ed8afyc0b04737ce0c0565@mail.gmail.com>	<9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>	<20060731233623.GA7869@aragorn>	<20060731234151.GA25670@coresystems.de>	<20060731235718.GC7869@aragorn>	<20060801120221.GA17269@coresystems.de>	<20060803220502.GA18987@aragorn>	<20060803224345.GC5055@coresystems.de>	<20060804014548.GA30639@aragorn>
	<20060804204410.GB17104@aragorn>
Message-ID: <44D75002.1070500@lanl.gov>

Uwe Hermann wrote:
> Hi,
> 
> more tests, still no luck. I had access to a hardware flash/EEPROM programmer
> today and flashed bitworks/ims/linuxbios.rom (256K this time, last time
> it was 512K which obviously cannot work). The Windows-Software for the
> programmer supported the chip (W49F002U) and reported that flashing
> worked fine (verify succeeded, too).
> 
> Now, I tried to boot from that chip but cannot get serial output, it
> seems (115200 Baud, 8N1, ttyS0).
> 
> I also tried to set the "reset BIOS" jumper on the board before running
> "./flashrom -V", but it seems that doesn't help either. I'm slowly
> running out of ideas.
> 
> Hm, say I accidentally killed the chips (ESD) somehow - would the result
> be 0xFF's returned as vendor/device ID?


yes but I don't think that is it. There's something "special" on this board.

ron



From rminnich at lanl.gov  Mon Aug  7 16:38:35 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 07 Aug 2006 08:38:35 -0600
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060806195215.GB27511@aragorn>
References: <9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>	<20060731233623.GA7869@aragorn>	<20060731234151.GA25670@coresystems.de>	<20060731235718.GC7869@aragorn>	<20060801120221.GA17269@coresystems.de>	<20060803220502.GA18987@aragorn>	<20060803224345.GC5055@coresystems.de>	<20060804014548.GA30639@aragorn>
	<20060804204410.GB17104@aragorn>	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
Message-ID: <44D7506B.6020702@lanl.gov>

stefan, what do you think? committable?

Uwe, nice job.

ron



From smithbone at gmail.com  Mon Aug  7 17:09:10 2006
From: smithbone at gmail.com (Richard Smith)
Date: Mon, 7 Aug 2006 10:09:10 -0500
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060806195215.GB27511@aragorn>
References: <9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
Message-ID: <8a0c36780608070809g3ec76c6dnbd74c9f47d035984@mail.gmail.com>

On 8/6/06, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> The setup_serial.inc is copied from v1, for the rest of the stuff I tried
> to guess what's needed from other superios in v2. I haven't grasped
> LinuxBIOS well enough to _really_ know what I'm doing ;)

setup_serial.inc is a holdover from V1 and not used in V2.  Just say
not to assembly.

Are you #includeing this in your auto.c?  If so then remove it an only
use the .c stuff to init the device.

> Anyways, I managed to build an image (based on bitworks/ims) which
> outputs something on the serial line:
>
> LinuxBIOS-1.1.0-* starting...

1.1.0?   What rev are you working with?

Hmmm... Perhpas we need to add some .svn build info in here.

> Please look over the preliminary patch (attached) and tell me about
> obvious stupid errors I made.

I've only had time to briefly look at it.  I'll study it more later.

-- 
Richard A. Smith



From uwe at hermann-uwe.de  Mon Aug  7 17:20:14 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 7 Aug 2006 17:20:14 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <44D75002.1070500@lanl.gov>
References: <9048.128.165.0.81.1154385586.squirrel@webmail.lanl.gov>
	<20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn>
	<20060804204410.GB17104@aragorn> <44D75002.1070500@lanl.gov>
Message-ID: <20060807152014.GA16605@aragorn>

Hi,

On Mon, Aug 07, 2006 at 08:36:50AM -0600, Ronald G Minnich wrote:
> yes but I don't think that is it. There's something "special" on this board.

Yes, definately. I don't yet know _what_ it is, but I managed to use
Uniflash (see my other post) to flash a chip on that board, so it's a
software issue which can be fixed.


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060807/d7621fbe/attachment.sig>

From uwe at hermann-uwe.de  Mon Aug  7 17:26:42 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 7 Aug 2006 17:26:42 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <8a0c36780608070809g3ec76c6dnbd74c9f47d035984@mail.gmail.com>
References: <20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
	<8a0c36780608070809g3ec76c6dnbd74c9f47d035984@mail.gmail.com>
Message-ID: <20060807152642.GB16605@aragorn>

Hi,

On Mon, Aug 07, 2006 at 10:09:10AM -0500, Richard Smith wrote:
> Are you #includeing this in your auto.c?  If so then remove it an only
> use the .c stuff to init the device.

Yes, I included it from auto.c. I'll try if the init works without the
asm stuff, but I fear it won't. Where should a C replacement of that
code be added? Should it be made part of it8671f_enable_serial()?


> > Anyways, I managed to build an image (based on bitworks/ims) which
> > outputs something on the serial line:
> >
> > LinuxBIOS-1.1.0-* starting...
> 
> 1.1.0?   What rev are you working with?

Latest svn, v2. There was more info in that line (I replaced it with "*"),
but I was too lazy to type all of it.


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060807/f1350c87/attachment.sig>

From uwe at hermann-uwe.de  Mon Aug  7 17:52:07 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 7 Aug 2006 17:52:07 +0200
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
In-Reply-To: <20060804170230.11139.qmail@customer.mpex.net>
References: <20060803203604.32272.qmail@customer.mpex.net>
	<20060804091635.GA20192@coresystems.de> <44D322AD.8070107@mpx.net>
	<20060804170230.11139.qmail@customer.mpex.net>
Message-ID: <20060807155206.GF16605@aragorn>

Hi,

On Fri, Aug 04, 2006 at 07:02:30PM +0200, Sam Brightman wrote:
> Anyway, here is the output: 

I have a similar problem (same output) with flashrom. Can you try
Uniflash (uniflash.org) and report whether it works?


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060807/7902c3a5/attachment.sig>

From rminnich at lanl.gov  Mon Aug  7 18:28:40 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 07 Aug 2006 10:28:40 -0600
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <8a0c36780608040937m4519663bs87fe9b3974741167@mail.gmail.com>
References: <44D0F0CF.2050308@artecdesign.ee>	<20060803165758.GC6842@coresystems.de>	<44D3654B.2050800@artecdesign.ee>
	<8a0c36780608040937m4519663bs87fe9b3974741167@mail.gmail.com>
Message-ID: <44D76A38.30904@lanl.gov>

Richard Smith wrote:
>>Question about OLPC: if memtest is set as payload then is it works? We
>>have got dbe61 up and running after some ram_resource() hacking. With
>>ehterbooted Linux the thing is still totally quiet.
> 
> 
> I've not tried memtest on OLPC.  Ron may have.  I can test later on
> tonight if you wish. I'm CDT. So it will be in 6 or so hours.
> 

we have used memtest as a payload. It works fine.

ron



From smithbone at gmail.com  Mon Aug  7 18:34:03 2006
From: smithbone at gmail.com (Richard Smith)
Date: Mon, 7 Aug 2006 11:34:03 -0500
Subject: [LinuxBIOS] How to separate CS5536 and CPU?
In-Reply-To: <44D76A38.30904@lanl.gov>
References: <44D0F0CF.2050308@artecdesign.ee>
	<20060803165758.GC6842@coresystems.de>
	<44D3654B.2050800@artecdesign.ee>
	<8a0c36780608040937m4519663bs87fe9b3974741167@mail.gmail.com>
	<44D76A38.30904@lanl.gov>
Message-ID: <8a0c36780608070934l6fbfc5banf62af008f02c421c@mail.gmail.com>

> >
> > I've not tried memtest on OLPC.  Ron may have.  I can test later on
> > tonight if you wish. I'm CDT. So it will be in 6 or so hours.
> >

Oops.  Sorry.  I forgot i was going to try this for you.

-- 
Richard A. Smith



From samghost at mpx.net  Mon Aug  7 18:43:29 2006
From: samghost at mpx.net (Sam Brightman)
Date: Mon, 07 Aug 2006 17:43:29 +0100
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
In-Reply-To: <20060807155206.GF16605@aragorn>
References: <20060803203604.32272.qmail@customer.mpex.net>	<20060804091635.GA20192@coresystems.de>
	<44D322AD.8070107@mpx.net>	<20060804170230.11139.qmail@customer.mpex.net>
	<20060807155206.GF16605@aragorn>
Message-ID: <44D76DB1.3050401@mpx.net>

Uwe Hermann wrote:

> On Fri, Aug 04, 2006 at 07:02:30PM +0200, Sam Brightman wrote:
>> Anyway, here is the output: 
> 
> I have a similar problem (same output) with flashrom. Can you try
> Uniflash (uniflash.org) and report whether it works?

I was trying to avoid Uniflash because it seemed dated and DOS-ish. 
Granted I could probably get FreeDOS, but I've also gradually broken all 
my floppy drives over the years...

 From what I can tell Uniflash, OpenBIOS and LinuxBIOSv1 have all been 
abandoned to a greater or lesser extent, yet the knowledge from them 
hasn't been used anywhere else? Is LinuxBIOSv2 a from-scratch effort? I 
think the chip used in this board was supported by /dev/bios, but I'm a 
bit unsure as to the state/stability of that given the non-activity on 
OpenBIOS.

Is this board fundamentally different from P2B-L? I should probably also 
mention that we have some pretty groovy-looking equipment at work that I 
could possibly use if basic reverse engineering is required. Only 
problem being my lack of hardware knowledge - there's something that 
looks like an oscilloscope but it says "impedance analyser" and I need 
to be told what to do with such equipment.

-- 
sam brightman



From samghost at mpx.net  Mon Aug  7 17:29:01 2006
From: samghost at mpx.net (Sam Brightman)
Date: Mon, 07 Aug 2006 16:29:01 +0100
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
In-Reply-To: <20060804170230.11139.qmail@customer.mpex.net>
References: <20060803203604.32272.qmail@customer.mpex.net>	<20060804091635.GA20192@coresystems.de>
	<44D322AD.8070107@mpx.net>
	<20060804170230.11139.qmail@customer.mpex.net>
Message-ID: <44D75C3D.90907@mpx.net>

For some reason I had ignored the other P2B-L thread, but it seems to 
suggest that one can indeed flash the (similar) chip. If anyone could 
tell me why this is not being detected at all, I'd be most appreciative. 
I should add that I have a spare board/chip, so I'd be quite happy to do 
some investigative work on this without worrying about losing the thing.

-- 
sam brightman



From stepan at coresystems.de  Mon Aug  7 18:50:50 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 7 Aug 2006 18:50:50 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <44D7506B.6020702@lanl.gov>
References: <20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn> <44D7506B.6020702@lanl.gov>
Message-ID: <20060807165050.GA30568@coresystems.de>

* Ronald G Minnich <rminnich at lanl.gov> [060807 16:38]:
> stefan, what do you think? committable?
 
i checked it in.

- dropped the assembler part
- renamed the directory from "foo" to "ite" ;-)

no mainboard in the tree uses it though.. Anything to check in here?

updates and patches against 2365 or later please.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From info at coresystems.de  Mon Aug  7 19:26:52 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Mon, 07 Aug 2006 19:26:52 +0200
Subject: [LinuxBIOS] LinuxBIOS r2365 build changes
Message-ID: <E1GA8sO-0000iM-US@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2365 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
add support for ite/it8671f superio from Uwe Hermann.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From stepan at coresystems.de  Mon Aug  7 19:35:34 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 7 Aug 2006 19:35:34 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060807152642.GB16605@aragorn>
References: <20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
	<8a0c36780608070809g3ec76c6dnbd74c9f47d035984@mail.gmail.com>
	<20060807152642.GB16605@aragorn>
Message-ID: <20060807173534.GB30568@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060807 17:26]:
> Hi,
> 
> On Mon, Aug 07, 2006 at 10:09:10AM -0500, Richard Smith wrote:
> > Are you #includeing this in your auto.c?  If so then remove it an only
> > use the .c stuff to init the device.
> 
> Yes, I included it from auto.c. I'll try if the init works without the
> asm stuff, but I fear it won't. Where should a C replacement of that
> code be added? Should it be made part of it8671f_enable_serial()?

That's what 
src/superio/ite/it8671f/it8671f_early_serial.c is good for.
It should be included in your auto.c file and it8671f_enable_serial()
from there should be called.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Mon Aug  7 19:55:21 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 7 Aug 2006 19:55:21 +0200
Subject: [LinuxBIOS] LinuxBIOS/flashrom on Asus P2B
In-Reply-To: <44D76DB1.3050401@mpx.net>
References: <20060803203604.32272.qmail@customer.mpex.net>
	<20060804091635.GA20192@coresystems.de> <44D322AD.8070107@mpx.net>
	<20060804170230.11139.qmail@customer.mpex.net>
	<20060807155206.GF16605@aragorn> <44D76DB1.3050401@mpx.net>
Message-ID: <20060807175521.GA4650@coresystems.de>

* Sam Brightman <samghost at mpx.net> [060807 18:43]:
> I was trying to avoid Uniflash because it seemed dated and DOS-ish. 
> Granted I could probably get FreeDOS, but I've also gradually broken all 
> my floppy drives over the years...
> 
>  From what I can tell Uniflash, OpenBIOS and LinuxBIOSv1 have all been 
> abandoned to a greater or lesser extent, yet the knowledge from them 
> hasn't been used anywhere else? Is LinuxBIOSv2 a from-scratch effort?

Uniflash works with everything because it does 16bit calls into the bios
image to enable flash writes. We can't really do that (or: heavily try
to avoid that) in Linux(BIOS)

> think the chip used in this board was supported by /dev/bios, but I'm a 
> bit unsure as to the state/stability of that given the non-activity on 
> OpenBIOS.
 
I am putting my efforts in the flashrom utility of LinuxBIOS instead and
I want to drop devbios once flashrom handles everything it needs to
handle.

Can you try to get devbios work (whether it finds the chip. no flashing
needed)

> Is this board fundamentally different from P2B-L? I should probably also 
> mention that we have some pretty groovy-looking equipment at work that I 
> could possibly use if basic reverse engineering is required. 

You may want to look at the asus bios flashing hooks to find out what
they do. Be sure it is legal in your country to analyze foreign code
though.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Mon Aug  7 20:02:42 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 7 Aug 2006 20:02:42 +0200
Subject: [LinuxBIOS] GA-6BXC - first try.
In-Reply-To: <20060807152014.GA16605@aragorn>
References: <20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn>
	<20060804204410.GB17104@aragorn> <44D75002.1070500@lanl.gov>
	<20060807152014.GA16605@aragorn>
Message-ID: <20060807180242.GA4995@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060807 17:20]:
> Hi,
> 
> On Mon, Aug 07, 2006 at 08:36:50AM -0600, Ronald G Minnich wrote:
> > yes but I don't think that is it. There's something "special" on this board.
> 
> Yes, definately. I don't yet know _what_ it is, but I managed to use
> Uniflash (see my other post) to flash a chip on that board, so it's a
> software issue which can be fixed.

You might want to have a look at the patch described here:

http://www.mail-archive.com/linuxbios%40linuxbios.org/msg00372.html



Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Mon Aug  7 20:07:25 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 7 Aug 2006 20:07:25 +0200
Subject: [LinuxBIOS] Uniflash.
In-Reply-To: <20060806195847.GC27511@aragorn>
References: <20060806195847.GC27511@aragorn>
Message-ID: <20060807180725.GB4995@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060806 21:58]:
> I'll try to figure out what it does that flashrom does not, in order to
> be able to use flashrom; I'll post a patch for flashrom when I'm done.
 
It calls 16bit bios code. Tricky. You might want to link in x86emu to
get it working cleanly, or do some vm86 tricks that fail on amd64 boxes.
Check ASUSBIOS.PAS in UniFlash. Same thing in different exists for
AMIBIOS as well.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From juergen127 at kreuzholzen.de  Mon Aug  7 22:15:57 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Mon, 7 Aug 2006 22:15:57 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <200608071119.17303.juergen127@kreuzholzen.de>
References: <200608071119.17303.juergen127@kreuzholzen.de>
Message-ID: <200608072215.57520.juergen127@kreuzholzen.de>

Hi all,

On Monday 07 August 2006 11:19, myself wrote:
> I try to write a native sound driver for the Geode GX1/5530a Companion
> chip. Problem here: The sound chip only generates SMI. Does anyone knows a
> trick or a chipset switch that let me forward this SMI to a regular IRQ?
> Its too ugly to use a polling loop.... ;-)

Sorry. I think I must explain: I'm using linuxbios on this Geode system, so 
there is no SMM emulation of the sound hardware. Thats why I'm searching for 
a solution to forward the SMI to a regular IRQ. Has someone experience in 
programming this SMM code? Maybe a short routine that only triggers a regular 
interrupt when an SMI occures would help.

Regards,
Juergen




From info at coresystems.de  Mon Aug  7 22:40:11 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Mon, 07 Aug 2006 22:40:11 +0200
Subject: [LinuxBIOS] LinuxBIOS r2366 build changes
Message-ID: <E1GABtT-0004DF-5R@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2366 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
initial work on sunw ultra40. It's wrong :-)

Build Log:
 Compilation of artecgroup:dbe61 is still broken. Configuration of sunw:ultra40 has been fixed. Compilation of sunw:ultra40 has been fixed.

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From rminnich at lanl.gov  Mon Aug  7 22:48:54 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 07 Aug 2006 14:48:54 -0600
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <200608072215.57520.juergen127@kreuzholzen.de>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608072215.57520.juergen127@kreuzholzen.de>
Message-ID: <44D7A736.5050401@lanl.gov>

Juergen Beisert wrote:
> Hi all,
> 
> On Monday 07 August 2006 11:19, myself wrote:
> 
>>I try to write a native sound driver for the Geode GX1/5530a Companion
>>chip. Problem here: The sound chip only generates SMI. Does anyone knows a
>>trick or a chipset switch that let me forward this SMI to a regular IRQ?
>>Its too ugly to use a polling loop.... ;-)
> 
> 
> Sorry. I think I must explain: I'm using linuxbios on this Geode system, so 
> there is no SMM emulation of the sound hardware. Thats why I'm searching for 
> a solution to forward the SMI to a regular IRQ. Has someone experience in 
> programming this SMM code? Maybe a short routine that only triggers a regular 
> interrupt when an SMI occures would help.

Is there some reason to continue to use SMI? why not just drive the 
hardware directly w/o smi?

ron



From tcrawford at lnxi.com  Mon Aug  7 23:09:09 2006
From: tcrawford at lnxi.com (Tim Crawford)
Date: Mon, 07 Aug 2006 15:09:09 -0600
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a	regular IRQ
In-Reply-To: <44D7A736.5050401@lanl.gov>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608072215.57520.juergen127@kreuzholzen.de>
	<44D7A736.5050401@lanl.gov>
Message-ID: <44D75762.9BB4.00CE.0@lnxi.com>

If I understand the question correctly Juergen want to tell the
chipset to issue a IRQ not a SMI.  There is no SMM code in LB.

Tim
 
 
>>> Ronald G Minnich <rminnich at lanl.gov> 08/07/06 2:48 PM >>> 
Juergen Beisert wrote:
> Hi all,
> 
> On Monday 07 August 2006 11:19, myself wrote:
> 
>>I try to write a native sound driver for the Geode GX1/5530a Companion
>>chip. Problem here: The sound chip only generates SMI. Does anyone knows a
>>trick or a chipset switch that let me forward this SMI to a regular IRQ?
>>Its too ugly to use a polling loop.... ;- )
> 
> 
> Sorry. I think I must explain: I'm using linuxbios on this Geode system, so 
> there is no SMM emulation of the sound hardware. Thats why I'm searching for 
> a solution to forward the SMI to a regular IRQ. Has someone experience in 
> programming this SMM code? Maybe a short routine that only triggers a regular 
> interrupt when an SMI occures would help.

Is there some reason to continue to use SMI? why not just drive the 
hardware directly w/o smi?

ron

--  
linuxbios mailing list
linuxbios at linuxbios.org
http://www.openbios.org/mailman/listinfo/linuxbios





From rminnich at lanl.gov  Mon Aug  7 23:27:32 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 07 Aug 2006 15:27:32 -0600
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a	regular IRQ
In-Reply-To: <44D75762.9BB4.00CE.0@lnxi.com>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608072215.57520.juergen127@kreuzholzen.de>
	<44D7A736.5050401@lanl.gov> <44D75762.9BB4.00CE.0@lnxi.com>
Message-ID: <44D7B044.9020203@lanl.gov>

Tim Crawford wrote:
> If I understand the question correctly Juergen want to tell the
> chipset to issue a IRQ not a SMI.  There is no SMM code in LB.
> 
> Tim
>  
>  
> 
>>>>Ronald G Minnich <rminnich at lanl.gov> 08/07/06 2:48 PM >>> 
> 
> Juergen Beisert wrote:
> 
>>Hi all,
>>
>>On Monday 07 August 2006 11:19, myself wrote:
>>
>>
>>>I try to write a native sound driver for the Geode GX1/5530a Companion
>>>chip. Problem here: The sound chip only generates SMI. Does anyone knows a
>>>trick or a chipset switch that let me forward this SMI to a regular IRQ?
>>>Its too ugly to use a polling loop.... ;- )
>>
>>
>>Sorry. I think I must explain: I'm using linuxbios on this Geode system, so 
>>there is no SMM emulation of the sound hardware. Thats why I'm searching for 
>>a solution to forward the SMI to a regular IRQ. Has someone experience in 
>>programming this SMM code? Maybe a short routine that only triggers a regular 
>>interrupt when an SMI occures would help.
> 
> 
> Is there some reason to continue to use SMI? why not just drive the 
> hardware directly w/o smi?

apologies, I am really in 'slow mode' today.

we may need to write a stupid trampoline to get from smi to linux.

ron



From rminnich at lanl.gov  Tue Aug  8 01:08:41 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 07 Aug 2006 17:08:41 -0600
Subject: [LinuxBIOS] something new ... buildrom
Message-ID: <44D7C7F9.2000009@lanl.gov>


we're all sick of having to do all the steps to build a flash image, 
right? Well, thanks to OLPC, there is a new tool: buildrom.

This tool is designed to build a 1M flash image including linuxbios, 
kernel, and an initrd with busybox tools.

Right now, it only works for OLPC, but that should not hold you back.

To get it, just svn co svn://linuxbios.org/buildrom/buildrom-devel

cd buildrom-devel/buildrom

look at:
packages/linuxbios/linuxbios.mk

and see how you can set vendor, board, and config file in the top-level 
Config.mk.

This is a work in progress. What I want to do over time is have a config 
directory such that you can pull down buildrom, set a few variables for 
mainboard etc., and in short time have a rom image automagically.

take a look

ron



From smithbone at gmail.com  Tue Aug  8 08:23:52 2006
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 8 Aug 2006 01:23:52 -0500
Subject: [LinuxBIOS] Tyan s2865
Message-ID: <8a0c36780608072323g65bc59afpa8017d1455e6b9be@mail.gmail.com>

I've got someone asking about the Tyan s2865 which is an nVidia based
board.  Whats the status on these parts?  The board is not listed in
the Tyan dir.

0000:00:00.0 Memory controller: nVidia Corporation CK804 Memory
Controller (rev a3)
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0
       Capabilities: [44] #08 [01e0]
       Capabilities: [e0] #08 [a801]

0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 0050 (rev a3)
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0

0000:00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2)
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: 66Mhz, fast devsel, IRQ 12
       I/O ports at fc00 [size=32]
       I/O ports at 1c00 [size=64]
       I/O ports at 1c40 [size=64]
       Capabilities: [44] Power Management version 2

0000:00:02.0 USB Controller: nVidia Corporation CK804 USB Controller
(rev a2) (prog-if 10 [OHCI])
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 10
       Memory at febff000 (32-bit, non-prefetchable) [size=4K]
       Capabilities: [44] Power Management version 2

0000:00:02.1 USB Controller: nVidia Corporation CK804 USB Controller
(rev a3) (prog-if 20 [EHCI])
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 11
       Memory at febfe000 (32-bit, non-prefetchable) [size=256]
       Capabilities: [44] #0a [2098]
       Capabilities: [80] Power Management version 2

0000:00:04.0 Multimedia audio controller: nVidia Corporation CK804
AC'97 Audio Controller (rev a2)
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 12
       I/O ports at f000 [size=256]
       I/O ports at ec00 [size=256]
       Memory at febfd000 (32-bit, non-prefetchable) [size=4K]
       Capabilities: [44] Power Management version 2

0000:00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev a2)
(prog-if 8a [Master SecP PriP])
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0
       I/O ports at e000 [size=16]
       Capabilities: [44] Power Management version 2

0000:00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA
Controller (rev a3) (prog-if 85 [Master SecO PriO])
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 11
       I/O ports at 09f0 [size=8]
       I/O ports at 0bf0 [size=4]
       I/O ports at 0970 [size=8]
       I/O ports at 0b70 [size=4]
       I/O ports at cc00 [size=16]
       Memory at febfb000 (32-bit, non-prefetchable) [size=4K]
       Capabilities: [44] Power Management version 2

0000:00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA
Controller (rev a3) (prog-if 85 [Master SecO PriO])
       Subsystem: nVidia Corporation: Unknown device cb84
       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 10
       I/O ports at 09e0 [size=8]
       I/O ports at 0be0 [size=4]
       I/O ports at 0960 [size=8]
       I/O ports at 0b60 [size=4]
       I/O ports at b800 [size=16]
       Memory at febfa000 (32-bit, non-prefetchable) [size=4K]
       Capabilities: [44] Power Management version 2

0000:00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2)
(prog-if 01 [Subtractive decode])
       Flags: bus master, 66Mhz, fast devsel, latency 0
       Bus: primary=00, secondary=01, subordinate=02, sec-latency=32
       I/O behind bridge: 00009000-0000afff
       Memory behind bridge: f8000000-fdffffff
       Prefetchable memory behind bridge: fea00000-feafffff

0000:00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3)
       Subsystem: Tyan Computer: Unknown device 2865
       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 5
       Memory at febf9000 (32-bit, non-prefetchable) [size=4K]
       I/O ports at b400 [size=8]
       Capabilities: [44] Power Management version 2

0000:00:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
(prog-if 00 [Normal decode])
       Flags: bus master, fast devsel, latency 0
       Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
       I/O behind bridge: 00008000-00008fff
       Memory behind bridge: fe900000-fe9fffff
       Prefetchable memory behind bridge: 00000000fe800000-00000000fe800000
       Capabilities: [40] Power Management version 2
       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
       Capabilities: [58] #08 [a800]
       Capabilities: [80] #10 [0141]

0000:00:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
(prog-if 00 [Normal decode])
       Flags: bus master, fast devsel, latency 0
       Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
       I/O behind bridge: 00007000-00007fff
       Memory behind bridge: fe700000-fe7fffff
       Prefetchable memory behind bridge: 00000000fe600000-00000000fe600000
       Capabilities: [40] Power Management version 2
       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
       Capabilities: [58] #08 [a800]
       Capabilities: [80] #10 [0141]

0000:00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
(prog-if 00 [Normal decode])
       Flags: bus master, fast devsel, latency 0
       Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
       I/O behind bridge: 00006000-00006fff
       Memory behind bridge: fe500000-fe5fffff
       Prefetchable memory behind bridge: 00000000fe400000-00000000fe400000
       Capabilities: [40] Power Management version 2
       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
       Capabilities: [58] #08 [a800]
       Capabilities: [80] #10 [0141]

0000:00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
(prog-if 00 [Normal decode])
       Flags: bus master, fast devsel, latency 0
       Bus: primary=00, secondary=06, subordinate=06, sec-latency=0
       I/O behind bridge: 00005000-00005fff
       Memory behind bridge: fe300000-fe3fffff
       Prefetchable memory behind bridge: 00000000fe200000-00000000fe200000
       Capabilities: [40] Power Management version 2
       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
       Capabilities: [58] #08 [a800]
       Capabilities: [80] #10 [0141]

0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8
[Athlon64/Opteron] HyperTransport Technology Configuration
       Flags: fast devsel
       Capabilities: [80] #08 [2101]

0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8
[Athlon64/Opteron] Address Map
       Flags: fast devsel

0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8
[Athlon64/Opteron] DRAM Controller
       Flags: fast devsel

0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8
[Athlon64/Opteron] Miscellaneous Control
       Flags: fast devsel

0000:01:05.0 VGA compatible controller: ATI Technologies Inc Rage XL
(rev 27) (prog-if 00 [VGA])
       Subsystem: ATI Technologies Inc Rage XL
       Flags: bus master, stepping, medium devsel, latency 32, IRQ 12
       Memory at f8000000 (32-bit, non-prefetchable) [size=16M]
       I/O ports at ac00 [size=256]
       Memory at fdfff000 (32-bit, non-prefetchable) [size=4K]
       Expansion ROM at fd000000 [disabled] [size=128K]
       Capabilities: [5c] Power Management version 2

0000:01:06.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394
Host Controller (rev 80) (prog-if 10 [OHCI])
       Subsystem: VIA Technologies, Inc. IEEE 1394 Host Controller
       Flags: bus master, stepping, medium devsel, latency 32, IRQ 10
       Memory at fdffe000 (32-bit, non-prefetchable) [size=2K]
       I/O ports at a800 [size=128]
       Capabilities: [50] Power Management version 2

0000:05:00.0 Ethernet controller: Broadcom Corporation NetXtreme
BCM5721 Gigabit Ethernet PCI Express (rev 11)
       Subsystem: Broadcom Corporation NetXtreme BCM5721 Gigabit
Ethernet PCI Express
       Flags: bus master, fast devsel, latency 0, IRQ 12
       Memory at fe500000 (64-bit, non-prefetchable) [size=64K]
       Capabilities: [48] Power Management version 2
       Capabilities: [50] Vital Product Data
       Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable-
       Capabilities: [d0] #10 [0001]


-- 
Richard A. Smith



From juergen127 at kreuzholzen.de  Tue Aug  8 08:47:46 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Tue, 8 Aug 2006 08:47:46 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <44D7A736.5050401@lanl.gov>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608072215.57520.juergen127@kreuzholzen.de>
	<44D7A736.5050401@lanl.gov>
Message-ID: <200608080847.47079.juergen127@kreuzholzen.de>

Hi Ronald,

On Monday 07 August 2006 22:48, Ronald G Minnich wrote:
> > On Monday 07 August 2006 11:19, myself wrote:
> >>I try to write a native sound driver for the Geode GX1/5530a Companion
> >>chip. Problem here: The sound chip only generates SMI. Does anyone knows
> >> a trick or a chipset switch that let me forward this SMI to a regular
> >> IRQ? Its too ugly to use a polling loop.... ;-)
> >
> > Sorry. I think I must explain: I'm using linuxbios on this Geode system,
> > so there is no SMM emulation of the sound hardware. Thats why I'm
> > searching for a solution to forward the SMI to a regular IRQ. Has someone
> > experience in programming this SMM code? Maybe a short routine that only
> > triggers a regular interrupt when an SMI occures would help.
>
> Is there some reason to continue to use SMI? why not just drive the
> hardware directly w/o smi?

Yes, there is: The audio hardware part of the chip can only generate SMI. I 
didn't find any chipset settings to let it generate a regular IRQ instead. 
There is only one register to let the SMM software trigger a regular IRQ.

On Monday 07 August 2006 23:27, Ronald G Minnich wrote:
> we may need to write a stupid trampoline to get from smi to linux.

What does it mean? A small SMM rotuine? That would be great. Can I help to 
write it?

Juergen




From yinghailu at gmail.com  Tue Aug  8 08:51:56 2006
From: yinghailu at gmail.com (yhlu)
Date: Mon, 7 Aug 2006 23:51:56 -0700
Subject: [LinuxBIOS] Tyan s2865
In-Reply-To: <8a0c36780608072323g65bc59afpa8017d1455e6b9be@mail.gmail.com>
References: <8a0c36780608072323g65bc59afpa8017d1455e6b9be@mail.gmail.com>
Message-ID: <2ea3fae10608072351l6896dbbfhe85728032a788265@mail.gmail.com>

I did something porting about it one year ago at tyan.

status
all works except only can use one DIMM.

but according to my experience about AM2 socket. I guess after some
fine tuning it could work with 4 dimms.

YH



On 8/7/06, Richard Smith <smithbone at gmail.com> wrote:
> I've got someone asking about the Tyan s2865 which is an nVidia based
> board.  Whats the status on these parts?  The board is not listed in
> the Tyan dir.
>
> 0000:00:00.0 Memory controller: nVidia Corporation CK804 Memory
> Controller (rev a3)
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0
>       Capabilities: [44] #08 [01e0]
>       Capabilities: [e0] #08 [a801]
>
> 0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 0050 (rev a3)
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0
>
> 0000:00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2)
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: 66Mhz, fast devsel, IRQ 12
>       I/O ports at fc00 [size=32]
>       I/O ports at 1c00 [size=64]
>       I/O ports at 1c40 [size=64]
>       Capabilities: [44] Power Management version 2
>
> 0000:00:02.0 USB Controller: nVidia Corporation CK804 USB Controller
> (rev a2) (prog-if 10 [OHCI])
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 10
>       Memory at febff000 (32-bit, non-prefetchable) [size=4K]
>       Capabilities: [44] Power Management version 2
>
> 0000:00:02.1 USB Controller: nVidia Corporation CK804 USB Controller
> (rev a3) (prog-if 20 [EHCI])
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 11
>       Memory at febfe000 (32-bit, non-prefetchable) [size=256]
>       Capabilities: [44] #0a [2098]
>       Capabilities: [80] Power Management version 2
>
> 0000:00:04.0 Multimedia audio controller: nVidia Corporation CK804
> AC'97 Audio Controller (rev a2)
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 12
>       I/O ports at f000 [size=256]
>       I/O ports at ec00 [size=256]
>       Memory at febfd000 (32-bit, non-prefetchable) [size=4K]
>       Capabilities: [44] Power Management version 2
>
> 0000:00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev a2)
> (prog-if 8a [Master SecP PriP])
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0
>       I/O ports at e000 [size=16]
>       Capabilities: [44] Power Management version 2
>
> 0000:00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA
> Controller (rev a3) (prog-if 85 [Master SecO PriO])
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 11
>       I/O ports at 09f0 [size=8]
>       I/O ports at 0bf0 [size=4]
>       I/O ports at 0970 [size=8]
>       I/O ports at 0b70 [size=4]
>       I/O ports at cc00 [size=16]
>       Memory at febfb000 (32-bit, non-prefetchable) [size=4K]
>       Capabilities: [44] Power Management version 2
>
> 0000:00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA
> Controller (rev a3) (prog-if 85 [Master SecO PriO])
>       Subsystem: nVidia Corporation: Unknown device cb84
>       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 10
>       I/O ports at 09e0 [size=8]
>       I/O ports at 0be0 [size=4]
>       I/O ports at 0960 [size=8]
>       I/O ports at 0b60 [size=4]
>       I/O ports at b800 [size=16]
>       Memory at febfa000 (32-bit, non-prefetchable) [size=4K]
>       Capabilities: [44] Power Management version 2
>
> 0000:00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2)
> (prog-if 01 [Subtractive decode])
>       Flags: bus master, 66Mhz, fast devsel, latency 0
>       Bus: primary=00, secondary=01, subordinate=02, sec-latency=32
>       I/O behind bridge: 00009000-0000afff
>       Memory behind bridge: f8000000-fdffffff
>       Prefetchable memory behind bridge: fea00000-feafffff
>
> 0000:00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3)
>       Subsystem: Tyan Computer: Unknown device 2865
>       Flags: bus master, 66Mhz, fast devsel, latency 0, IRQ 5
>       Memory at febf9000 (32-bit, non-prefetchable) [size=4K]
>       I/O ports at b400 [size=8]
>       Capabilities: [44] Power Management version 2
>
> 0000:00:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
> (prog-if 00 [Normal decode])
>       Flags: bus master, fast devsel, latency 0
>       Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
>       I/O behind bridge: 00008000-00008fff
>       Memory behind bridge: fe900000-fe9fffff
>       Prefetchable memory behind bridge: 00000000fe800000-00000000fe800000
>       Capabilities: [40] Power Management version 2
>       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
>       Capabilities: [58] #08 [a800]
>       Capabilities: [80] #10 [0141]
>
> 0000:00:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
> (prog-if 00 [Normal decode])
>       Flags: bus master, fast devsel, latency 0
>       Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
>       I/O behind bridge: 00007000-00007fff
>       Memory behind bridge: fe700000-fe7fffff
>       Prefetchable memory behind bridge: 00000000fe600000-00000000fe600000
>       Capabilities: [40] Power Management version 2
>       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
>       Capabilities: [58] #08 [a800]
>       Capabilities: [80] #10 [0141]
>
> 0000:00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
> (prog-if 00 [Normal decode])
>       Flags: bus master, fast devsel, latency 0
>       Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
>       I/O behind bridge: 00006000-00006fff
>       Memory behind bridge: fe500000-fe5fffff
>       Prefetchable memory behind bridge: 00000000fe400000-00000000fe400000
>       Capabilities: [40] Power Management version 2
>       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
>       Capabilities: [58] #08 [a800]
>       Capabilities: [80] #10 [0141]
>
> 0000:00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
> (prog-if 00 [Normal decode])
>       Flags: bus master, fast devsel, latency 0
>       Bus: primary=00, secondary=06, subordinate=06, sec-latency=0
>       I/O behind bridge: 00005000-00005fff
>       Memory behind bridge: fe300000-fe3fffff
>       Prefetchable memory behind bridge: 00000000fe200000-00000000fe200000
>       Capabilities: [40] Power Management version 2
>       Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+
>       Capabilities: [58] #08 [a800]
>       Capabilities: [80] #10 [0141]
>
> 0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8
> [Athlon64/Opteron] HyperTransport Technology Configuration
>       Flags: fast devsel
>       Capabilities: [80] #08 [2101]
>
> 0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8
> [Athlon64/Opteron] Address Map
>       Flags: fast devsel
>
> 0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8
> [Athlon64/Opteron] DRAM Controller
>       Flags: fast devsel
>
> 0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8
> [Athlon64/Opteron] Miscellaneous Control
>       Flags: fast devsel
>
> 0000:01:05.0 VGA compatible controller: ATI Technologies Inc Rage XL
> (rev 27) (prog-if 00 [VGA])
>       Subsystem: ATI Technologies Inc Rage XL
>       Flags: bus master, stepping, medium devsel, latency 32, IRQ 12
>       Memory at f8000000 (32-bit, non-prefetchable) [size=16M]
>       I/O ports at ac00 [size=256]
>       Memory at fdfff000 (32-bit, non-prefetchable) [size=4K]
>       Expansion ROM at fd000000 [disabled] [size=128K]
>       Capabilities: [5c] Power Management version 2
>
> 0000:01:06.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394
> Host Controller (rev 80) (prog-if 10 [OHCI])
>       Subsystem: VIA Technologies, Inc. IEEE 1394 Host Controller
>       Flags: bus master, stepping, medium devsel, latency 32, IRQ 10
>       Memory at fdffe000 (32-bit, non-prefetchable) [size=2K]
>       I/O ports at a800 [size=128]
>       Capabilities: [50] Power Management version 2
>
> 0000:05:00.0 Ethernet controller: Broadcom Corporation NetXtreme
> BCM5721 Gigabit Ethernet PCI Express (rev 11)
>       Subsystem: Broadcom Corporation NetXtreme BCM5721 Gigabit
> Ethernet PCI Express
>       Flags: bus master, fast devsel, latency 0, IRQ 12
>       Memory at fe500000 (64-bit, non-prefetchable) [size=64K]
>       Capabilities: [48] Power Management version 2
>       Capabilities: [50] Vital Product Data
>       Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable-
>       Capabilities: [d0] #10 [0001]
>
>
> --
> Richard A. Smith
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From rminnich at gmail.com  Tue Aug  8 15:54:25 2006
From: rminnich at gmail.com (ron minnich)
Date: Tue, 8 Aug 2006 07:54:25 -0600
Subject: [LinuxBIOS] Tyan s2865
In-Reply-To: <2ea3fae10608072351l6896dbbfhe85728032a788265@mail.gmail.com>
References: <8a0c36780608072323g65bc59afpa8017d1455e6b9be@mail.gmail.com>
	<2ea3fae10608072351l6896dbbfhe85728032a788265@mail.gmail.com>
Message-ID: <13426df10608080654ye4d6f8coc640147189422721@mail.gmail.com>

I'm working on the sun ultra40 which is very similar. Why would only one
dimm socket work?

ron
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060808/005e47ff/attachment.html>

From rminnich at lanl.gov  Tue Aug  8 18:58:52 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Tue, 08 Aug 2006 10:58:52 -0600
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <200608080847.47079.juergen127@kreuzholzen.de>
References: <200608071119.17303.juergen127@kreuzholzen.de>	<200608072215.57520.juergen127@kreuzholzen.de>	<44D7A736.5050401@lanl.gov>
	<200608080847.47079.juergen127@kreuzholzen.de>
Message-ID: <44D8C2CC.9060100@lanl.gov>

Juergen Beisert wrote:

> What does it mean? A small SMM rotuine? That would be great. Can I help to 
> write it?

I talked to some amd guys about this. We think it is doable. You need an 
SMI handler that does nothing more than fix up the stack with a pointer 
to a kernel assembly thing that does a soft interrupt. Then you do a ret 
from SMI mode and you end up back in the kernel where you want.

If you study SMI mode a bit, we can do this.

ron



From ollie at lanl.gov  Tue Aug  8 19:03:31 2006
From: ollie at lanl.gov (ollie)
Date: Tue, 08 Aug 2006 11:03:31 -0600
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <200608080847.47079.juergen127@kreuzholzen.de>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608072215.57520.juergen127@kreuzholzen.de>
	<44D7A736.5050401@lanl.gov>
	<200608080847.47079.juergen127@kreuzholzen.de>
Message-ID: <1155056611.22405.11.camel@logarithm.lanl.gov>

On Tue, 2006-08-08 at 08:47 +0200, Juergen Beisert wrote:
> Hi Ronald,
> 
> On Monday 07 August 2006 22:48, Ronald G Minnich wrote:
> > > On Monday 07 August 2006 11:19, myself wrote:
> > >>I try to write a native sound driver for the Geode GX1/5530a Companion
> > >>chip. Problem here: The sound chip only generates SMI. Does anyone knows
> > >> a trick or a chipset switch that let me forward this SMI to a regular
> > >> IRQ? Its too ugly to use a polling loop.... ;-)
> > >
> > > Sorry. I think I must explain: I'm using linuxbios on this Geode system,
> > > so there is no SMM emulation of the sound hardware. Thats why I'm
> > > searching for a solution to forward the SMI to a regular IRQ. Has someone
> > > experience in programming this SMM code? Maybe a short routine that only
> > > triggers a regular interrupt when an SMI occures would help.
> >
> > Is there some reason to continue to use SMI? why not just drive the
> > hardware directly w/o smi?
> 
> Yes, there is: The audio hardware part of the chip can only generate SMI. I 
> didn't find any chipset settings to let it generate a regular IRQ instead. 
> There is only one register to let the SMM software trigger a regular IRQ.
> 

Under what circumstances do you want the audio device generate SMI?  If
you just want to translate SMI to IRQ for DMA completion like other
sound devices do, it should not be difficult to write a small SMM code
to do that. 

Ollie





From juergen127 at kreuzholzen.de  Tue Aug  8 20:05:42 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Tue, 8 Aug 2006 20:05:42 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <1155056611.22405.11.camel@logarithm.lanl.gov>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608080847.47079.juergen127@kreuzholzen.de>
	<1155056611.22405.11.camel@logarithm.lanl.gov>
Message-ID: <200608082005.42686.juergen127@kreuzholzen.de>

On Tuesday 08 August 2006 19:03, ollie wrote:
> On Tue, 2006-08-08 at 08:47 +0200, Juergen Beisert wrote:
> > Hi Ronald,
> >
> > On Monday 07 August 2006 22:48, Ronald G Minnich wrote:
> > > > On Monday 07 August 2006 11:19, myself wrote:
> > > >>I try to write a native sound driver for the Geode GX1/5530a
> > > >> Companion chip. Problem here: The sound chip only generates SMI.
> > > >> Does anyone knows a trick or a chipset switch that let me forward
> > > >> this SMI to a regular IRQ? Its too ugly to use a polling loop....
> > > >> ;-)
> > > >
> > > > Sorry. I think I must explain: I'm using linuxbios on this Geode
> > > > system, so there is no SMM emulation of the sound hardware. Thats why
> > > > I'm searching for a solution to forward the SMI to a regular IRQ. Has
> > > > someone experience in programming this SMM code? Maybe a short
> > > > routine that only triggers a regular interrupt when an SMI occures
> > > > would help.
> > >
> > > Is there some reason to continue to use SMI? why not just drive the
> > > hardware directly w/o smi?
> >
> > Yes, there is: The audio hardware part of the chip can only generate SMI.
> > I didn't find any chipset settings to let it generate a regular IRQ
> > instead. There is only one register to let the SMM software trigger a
> > regular IRQ.
>
> Under what circumstances do you want the audio device generate SMI?  If
> you just want to translate SMI to IRQ for DMA completion like other
> sound devices do, it should not be difficult to write a small SMM code
> to do that.

ALSA wants to be informed when a buffer is transmitted to the sound device 
(and the next begins). Thats on reason. CS5530's master DMA generates an SMI 
whenever it jumps to the next buffer to transmitt.
The other reason is, if I do not read back the SMI status registers until a 
second jump to another block happens the sound hardware stops with a bus 
error.
So my answer to your question is: Yes, only to translate the SMI to a DMA 
completion IRQ.
There are some registers in this audio hardware to trigger a regular interrupt 
in software from inside an SMI routine. Maybe this could be a starting point.

Regards
Juergen




From svn at openbios.org  Tue Aug  8 20:02:12 2006
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 08 Aug 2006 20:02:12 +0200
Subject: [LinuxBIOS] r2367 - trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40
Message-ID: <E1GAVu8-0004lX-8q@khepri.openbios.org>

Author: rminnich
Date: 2006-08-08 20:02:12 +0200 (Tue, 08 Aug 2006)
New Revision: 2367

Modified:
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c
Log:
fix up config space.


Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c	2006-08-07 20:02:02 UTC (rev 2366)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/resourcemap.c	2006-08-08 18:02:12 UTC (rev 2367)
@@ -3,7 +3,7 @@
  *
  */
 
-static void setup_s2895_resource_map(void)
+static void setup_ultra40_resource_map(void)
 {
 	static const unsigned int register_values[] = {
 		/* Careful set limit registers before base registers which contain the enables */
@@ -253,11 +253,10 @@
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, 
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, 
-		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, 
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
-
+		PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103,
+		PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113,
+		PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000,
 	};
 
 	int max;




From ollie at lanl.gov  Tue Aug  8 20:30:39 2006
From: ollie at lanl.gov (ollie)
Date: Tue, 08 Aug 2006 12:30:39 -0600
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <200608082005.42686.juergen127@kreuzholzen.de>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608080847.47079.juergen127@kreuzholzen.de>
	<1155056611.22405.11.camel@logarithm.lanl.gov>
	<200608082005.42686.juergen127@kreuzholzen.de>
Message-ID: <1155061839.22405.29.camel@logarithm.lanl.gov>

On Tue, 2006-08-08 at 20:05 +0200, Juergen Beisert wrote:
> ALSA wants to be informed when a buffer is transmitted to the sound device 
> (and the next begins). Thats on reason. CS5530's master DMA generates an SMI 
> whenever it jumps to the next buffer to transmitt.
> The other reason is, if I do not read back the SMI status registers until a 
> second jump to another block happens the sound hardware stops with a bus 
> error.
> So my answer to your question is: Yes, only to translate the SMI to a DMA 
> completion IRQ.
> There are some registers in this audio hardware to trigger a regular interrupt 
> in software from inside an SMI routine. Maybe this could be a starting point.
> 

Now the problem is you have to write a bunch of code to load and 
initialize your 2 line SMI->IRQ translator. Is VSA source code for
GX2 freely from AMD or not?

BTW, how "native" is your driver? Do you rd/wrmsr all the operations?

Ollie




From info at coresystems.de  Tue Aug  8 20:41:36 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Tue, 08 Aug 2006 20:41:36 +0200
Subject: [LinuxBIOS] LinuxBIOS r2367 build changes
Message-ID: <E1GAWWG-0006Vs-Op@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2367 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
fix up config space.

Build Log:
 Compilation of artecgroup:dbe61 is still broken. Compilation of sunw:ultra40 has been broken

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From juergen127 at kreuzholzen.de  Tue Aug  8 20:53:42 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Tue, 8 Aug 2006 20:53:42 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <1155061839.22405.29.camel@logarithm.lanl.gov>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608082005.42686.juergen127@kreuzholzen.de>
	<1155061839.22405.29.camel@logarithm.lanl.gov>
Message-ID: <200608082053.42949.juergen127@kreuzholzen.de>

Hi Ollie,

On Tuesday 08 August 2006 20:30, you wrote:
> On Tue, 2006-08-08 at 20:05 +0200, Juergen Beisert wrote:
> > ALSA wants to be informed when a buffer is transmitted to the sound
> > device (and the next begins). Thats on reason. CS5530's master DMA
> > generates an SMI whenever it jumps to the next buffer to transmitt.
> > The other reason is, if I do not read back the SMI status registers until
> > a second jump to another block happens the sound hardware stops with a
> > bus error.
> > So my answer to your question is: Yes, only to translate the SMI to a DMA
> > completion IRQ.
> > There are some registers in this audio hardware to trigger a regular
> > interrupt in software from inside an SMI routine. Maybe this could be a
> > starting point.
>
> Now the problem is you have to write a bunch of code to load and
> initialize your 2 line SMI->IRQ translator. Is VSA source code for
> GX2 freely from AMD or not?
>
> BTW, how "native" is your driver? Do you rd/wrmsr all the operations?

rd/wrmsr? What does it mean?

I am using the native PCI hardware and its registers only. AC97 works, I can 
configure the AC97 codec. Only sending/capturing audio data is missing...

Juergen




From bchafy at ccs.neu.edu  Tue Aug  8 21:33:18 2006
From: bchafy at ccs.neu.edu (Bryan E. Chafy)
Date: Tue, 8 Aug 2006 15:33:18 -0400 (EDT)
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <200608082053.42949.juergen127@kreuzholzen.de> from "Juergen
	Beisert" at Aug 08, 2006 08:53:42 PM
Message-ID: <E1GAXKI-0004gb-MK@denali.ccs.neu.edu>


Are you porting the FreeBSD geode gx1 native audio driver to linux? ie:
http://alumni.cse.ucsc.edu/%7Ebrucem/gx_audio/

> 
> rd/wrmsr? What does it mean?
> 
> I am using the native PCI hardware and its registers only. AC97 works, I can 
> configure the AC97 codec. Only sending/capturing audio data is missing...
> 
> Juergen



From svn at openbios.org  Tue Aug  8 23:42:18 2006
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 08 Aug 2006 23:42:18 +0200
Subject: [LinuxBIOS] r2368 - trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40
Message-ID: <E1GAZL8-0000o1-OK@khepri.openbios.org>

Author: rminnich
Date: 2006-08-08 23:42:18 +0200 (Tue, 08 Aug 2006)
New Revision: 2368

Modified:
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb
Log:
fix up the links for the ultra 40 -- i/o on ht 1 on each cpu


Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb	2006-08-08 18:02:12 UTC (rev 2367)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb	2006-08-08 21:42:18 UTC (rev 2368)
@@ -201,7 +201,8 @@
         end
 	device pci_domain 0 on
 		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on 
+			device pci 18.0 on end # link 0
+			device pci 18.0 on # link1 
 				#  devices on link 0, link 0 == LDT 0 
 			        chip southbridge/nvidia/ck804 
 					device pci 0.0 on end   # HT
@@ -318,30 +319,16 @@
 					register "mac_eeprom_addr" = "0x51"
 				end
 			end #  device pci 18.0 
-			device pci 18.0 on end # Link 1
-			device pci 18.0 on
-                        #  devices on link 2, link 2 == LDT 2
-	                        chip southbridge/amd/amd8131
-        	                        # the on/off keyword is mandatory
-                	                device pci 0.0 on end
-                        	        device pci 0.1 on end
-					device pci 1.0 on 
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end # lsi scsi
-                                                        device pci 6.1 on end
-                                                end
-					end
-					device pci 1.1 on end
-                	        end
-			end # device pci 18.0
+			device pci 18.0 on end # link 2
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
 		
 		chip northbridge/amd/amdk8
-                	device pci 19.0 on #  northbridge 
-                        	#  devices on link 0, link 0 == LDT 0 
+                	device pci 19.0 on end # link 0
+		device pci 19.0 on   
+                        	#  devices on link 1, link 1 == LDT 1
                         	chip southbridge/nvidia/ck804 
                                 	device pci 0.0 on end   # HT
                                 	device pci 1.0 on end   # LPC
@@ -366,21 +353,10 @@
                 	end #  device pci 19.0 
 			
 			device pci 19.0 on end
-			device pci 19.0 on end
 			device pci 19.1 on end
 			device pci 19.2 on end
 			device pci 19.3 on end
 		end
 	end # PCI domain
 	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 off end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end  
 end #root_complex




From info at coresystems.de  Wed Aug  9 00:20:09 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Wed, 09 Aug 2006 00:20:09 +0200
Subject: [LinuxBIOS] LinuxBIOS r2368 build changes
Message-ID: <E1GAZvl-0002dX-AL@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2368 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
fix up the links for the ultra 40 -- i/o on ht 1 on each cpu

Build Log:
 Compilation of artecgroup:dbe61 is still broken. Compilation of sunw:ultra40 is still broken.

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From svn at openbios.org  Wed Aug  9 04:21:49 2006
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 09 Aug 2006 04:21:49 +0200
Subject: [LinuxBIOS] r2369 - in trunk/LinuxBIOSv2:
	src/mainboard/sunw/ultra40 src/northbridge/amd/gx2
	targets/olpc/rev_a targets/sunw/ultra40
Message-ID: <E1GAdhd-0005au-PK@khepri.openbios.org>

Author: rminnich
Date: 2006-08-09 04:21:49 +0200 (Wed, 09 Aug 2006)
New Revision: 2369

Modified:
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c
   trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c
   trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb
   trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb
Log:
mods for the ultra40 bringup. This now builds.

amd gx2 north -- don't set anything in the north, it conflicts with vsa
settings. So we have our own pci_set_resources that is essentially a
no-op -- just calls the kids. 

olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOT
have been set -- it is untested and caused real trouble. 


Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb	2006-08-09 02:21:49 UTC (rev 2369)
@@ -176,11 +176,12 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="s2895"
-default MAINBOARD_VENDOR="Tyan"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
+default MAINBOARD_PART_NUMBER="ultra40"
+default MAINBOARD_VENDOR="sunw"
 
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40
+
 ###
 ### LinuxBIOS layout values
 ###

Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c	2006-08-09 02:21:49 UTC (rev 2369)
@@ -174,7 +174,7 @@
 
 	sio_gpio_setup();
 
-        setup_s2895_resource_map();
+        setup_ultra40_resource_map();
 
 	needs_reset = setup_coherent_ht_domain();
 

Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c	2006-08-09 02:21:49 UTC (rev 2369)
@@ -236,7 +236,7 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        setup_s2895_resource_map();
+        setup_ultra40_resource_map();
 
 	needs_reset = setup_coherent_ht_domain();
 

Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/chip.h	2006-08-09 02:21:49 UTC (rev 2369)
@@ -1,6 +1,6 @@
-extern struct chip_operations mainboard_tyan_s2895_ops;
+extern struct chip_operations mainboard_sunw_ultra40_ops;
 
-struct mainboard_tyan_s2895_config {
+struct mainboard_sunw_ultra40_config {
 //	int fixup_scsi;
 //	int fixup_vga;
 };

Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/mptable.c	2006-08-09 02:21:49 UTC (rev 2369)
@@ -35,8 +35,8 @@
 void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "TYAN    ";
-        static const char productid[12] = "S2895       ";
+        static const char oem[8] = "SUNW    ";
+        static const char productid[12] = "ultra40     ";
         struct mp_config_table *mc;
 
         unsigned char bus_num;

Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c	2006-08-09 02:21:49 UTC (rev 2369)
@@ -283,9 +283,56 @@
 	irq_init_steering(dev, nb->irqmap);
 }
 
+/* due to vsa interactions, we need not not touch the nb settings ... */
+/* this is a test -- we are not sure it will work -- but it ought to */
+static void set_resources(struct device *dev)
+{
+        struct resource *resource, *last;
+        unsigned link;
+        uint8_t line;
+
+#if 0
+        last = &dev->resource[dev->resources];
+
+        for(resource = &dev->resource[0]; resource < last; resource++) {
+                pci_set_resource(dev, resource);
+        }
+#endif
+        for(link = 0; link < dev->links; link++) {
+                struct bus *bus;
+                bus = &dev->link[link];
+                if (bus->children) {
+                        assign_resources(bus);
+                }
+        }
+
+#if 0
+        /* set a default latency timer */
+        pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+        /* set a default secondary latency timer */
+        if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+                pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
+        }
+
+        /* zero the irq settings */
+        line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+        if (line) {
+                pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
+        }
+        /* set the cache line size, so far 64 bytes is good for everyone */
+        pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
+#endif
+}
+
+
+
 static struct device_operations northbridge_operations = {
 	.read_resources   = pci_dev_read_resources,
+#if 0
 	.set_resources    = pci_dev_set_resources,
+#endif
+	.set_resources    = set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = northbridge_init,
 	.enable           = 0,

Modified: trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb	2006-08-09 02:21:49 UTC (rev 2369)
@@ -5,7 +5,7 @@
 
 # Don't let LinuxBIOS compress the payload
 # option CONFIG_COMPRESSED_ROM_STREAM=0
-option CONFIG_PRECOMPRESSED_ROM_STREAM=1
+#option CONFIG_PRECOMPRESSED_ROM_STREAM=1
 
 # leave 64k for vsa
 option ROM_SIZE=1024*1024-64*1024

Modified: trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb	2006-08-08 21:42:18 UTC (rev 2368)
+++ trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb	2006-08-09 02:21:49 UTC (rev 2369)
@@ -29,7 +29,7 @@
 #       payload ../../../payloads/filo.zelf
 #	payload ../../../payloads/tg3.zelf
 #	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+	payload /etc/hosts
 #	payload ../../../payloads/forcedeth_vga.zelf
 #	payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf
 #	payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf
@@ -58,7 +58,7 @@
 #       payload ../../../payloads/filo.zelf
 #	payload ../../../payloads/tg3.zelf
 #	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+	payload /etc/hosts
 #	payload ../../../payloads/forcedeth_vga.zelf
 #	payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
 #	payload ../../../payloads/tg3_vga.zelf




From info at coresystems.de  Wed Aug  9 04:59:31 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Wed, 09 Aug 2006 04:59:31 +0200
Subject: [LinuxBIOS] LinuxBIOS r2369 build changes
Message-ID: <E1GAeI7-0006Y9-DD@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2369 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
mods for the ultra40 bringup. This now builds.amd gx2 north -- don't set anything in the north, it conflicts with vsasettings. So we have our own pci_set_resources that is essentially ano-op -- just calls the kids.olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOThave been set -- it is untested and caused real trouble.

Build Log:
 Compilation of artecgroup:dbe61 is still broken. Compilation of sunw:ultra40 has been fixed.

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From juergen127 at kreuzholzen.de  Wed Aug  9 10:15:59 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Wed, 9 Aug 2006 10:15:59 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <E1GAXKI-0004gb-MK@denali.ccs.neu.edu>
References: <E1GAXKI-0004gb-MK@denali.ccs.neu.edu>
Message-ID: <200608091015.59235.juergen127@kreuzholzen.de>

Hi Bryan,

On Tuesday 08 August 2006 21:33, Bryan E. Chafy wrote:
> Are you porting the FreeBSD geode gx1 native audio driver to linux? ie:
> http://alumni.cse.ucsc.edu/%7Ebrucem/gx_audio/

I read this BDS driver also. But then I cloned the cs5535 driver. Most of it 
can be used with the cs5530. That was much easier than porting the BSD 
driver.

Regards
J?rgen




From juergen127 at kreuzholzen.de  Wed Aug  9 10:51:19 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Wed, 9 Aug 2006 10:51:19 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <E1GAXKI-0004gb-MK@denali.ccs.neu.edu>
References: <E1GAXKI-0004gb-MK@denali.ccs.neu.edu>
Message-ID: <200608091051.19479.juergen127@kreuzholzen.de>

Hi Bryan,

On Tuesday 08 August 2006 21:33, Bryan E. Chafy wrote:
> Are you porting the FreeBSD geode gx1 native audio driver to linux? ie:
> http://alumni.cse.ucsc.edu/%7Ebrucem/gx_audio/

Here is the current driver. Does not work correctly yet. I have two Geode GX1 
systems here: One with regular BIOS (and SMM software) that is currently 
working and a second one (different manufacturer) with a not complete 
LinuxBIOS (not working yet). My tests are running on the BIOS based system 
yet. So maybe some of my problems are founded in interference with the SMM. 
-> Someone clears my Bus Master Control bit soon or later, but not my driver 
:-(

There are some open questions the datasheet not answers:

  - How does the Audio Bus Master 0 (and 1) handle the data in memory?
    I think left and right audio sample (16 bit each) in one 32 bit word.
    Correct? What sample in the upper, what in the lower bits?
 - Reading back any PRD pointer from hardware register always has
   bit 0 set. Datasheet says to set the lower two bits to 0. Maybe this bit
   has a meaning? Status?

I did not understand completly how the PCM framework works yet. So I don't 
know what happens if the master DMA unit reaches the last PRD in the chain (I 
did not reach this point yet, someone clears the Bus Master Control bit...). 
This PRD points back to the first PRD. But this would play the same samples 
ever and ever...

Any comments and ideas are appreciated.

Regards,
Juergen
-------------- next part --------------
A non-text attachment was scrubbed...
Name: kahlua.c
Type: text/x-csrc
Size: 31339 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060809/1d2766b1/attachment.c>

From indrek.kruusa at artecdesign.ee  Wed Aug  9 12:32:44 2006
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Wed, 09 Aug 2006 13:32:44 +0300
Subject: [LinuxBIOS] Linux & memory regions
Message-ID: <44D9B9CC.409@artecdesign.ee>

Hi!

I am looking for clarification about what and how  (Linux)BIOS should 
provide to kernel about memory size/memory regions.

I'm wondering about linuxbios table: there are lot of different 
variation with new_resource/ram_resource, where those calls are placed, 
what regions they are setting up, are those regions 0-TopOfSysRAM, or 
0-640/768-TopOfSysRAM etc. And reportedly it all works with linux kernel.
I'm not sure how to properly control linuxbios table content - and is 
this table mandatory for linux kernel?

thanks,
Indrek




From lists at actweb.info  Wed Aug  9 01:49:36 2006
From: lists at actweb.info (lists at actweb.info)
Date: Wed,  9 Aug 2006 00:49:36 +0100 (BST)
Subject: [LinuxBIOS] RD1-PL on EPIA-M10000 problem
In-Reply-To: <mailman.1525.1155075610.6425.linuxbios@linuxbios.org>
Message-ID: <1155080976.27120@actweb.info>

hi can someone confirm that i have the following correct?

 i have an EPIA-M m/board with an SST39SF020A bios chip, along with an RD1-PL 2Mbit bios savour, are these both 2Mb chips? i have tried writing the RD1 with a image file, but it always fails :( anyone any pointers?

have so far tried to write image aprox 8 times, still with no luck :(
this is the output from flashrom :-
Original BIOS
# ./flashrom
Calibrating delay loop... ok
No LinuxBIOS table found.
Enabling flash write on VT8235...tried to set 0x45 to 0x55 on VT8235 failed (WARNING ONLY)
SST39SF020A found at physical address: 0xfffc0000
Flash part is SST39SF020A
OK, only ENABLING flash write, but NOT FLASHING.

RD1-PL BIOS
# ./flashrom
Calibrating delay loop... ok
No LinuxBIOS table found.
Enabling flash write on VT8235...OK
W49F002U found at physical address: 0xfffc0000
Flash part is W49F002U
OK, only ENABLING flash write, but NOT FLASHING.


as far as i can tell both are 2M bios, is htere something that prevent writing to the differant chip number properly?

PS. this bios savour worked fine on my EPIA-PD board, always writing corectly first time :(


Many thanks in advance

Matt

From smithbone at gmail.com  Wed Aug  9 15:39:39 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 9 Aug 2006 08:39:39 -0500
Subject: [LinuxBIOS] RD1-PL on EPIA-M10000 problem
In-Reply-To: <1155080976.27120@actweb.info>
References: <mailman.1525.1155075610.6425.linuxbios@linuxbios.org>
	<1155080976.27120@actweb.info>
Message-ID: <8a0c36780608090639x1d90d0ew1a8eb1b9b02a042e@mail.gmail.com>

On 8/8/06, lists at actweb.info <lists at actweb.info> wrote:
> hi can someone confirm that i have the following correct?
>
>  i have an EPIA-M m/board with an SST39SF020A bios chip, along with an RD1-PL 2Mbit bios savour, are these both 2Mb chips?

Looking at the datasheets they are both 2Mbit parts and both are 5V
program.  So they should be equivilent.

 i have tried writing the RD1 with a image file, but it always fails
:( anyone any pointers?

> have so far tried to write image aprox 8 times, still with no luck :(
> Original BIOS
> Enabling flash write on VT8235...tried to set 0x45 to 0x55 on VT8235 failed (WARNING ONLY)

What's up here?  Has the factory bios set some lock so you can't
enable bit 4?  What does that bit do?

>
> as far as i can tell both are 2M bios, is htere something that prevent writing to the differant chip > number properly?

You IDed both parts correctly which means that writes to flash seem to
be happening.  Can you read the parts ok?
If so then you might try flashing in your LinuxBIOS image and then
read the image back from the part to see if it wrote anything close to
what you expected where you expected.


-- 
Richard A. Smith



From smithbone at gmail.com  Wed Aug  9 15:42:25 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 9 Aug 2006 08:42:25 -0500
Subject: [LinuxBIOS] RD1-PL on EPIA-M10000 problem
In-Reply-To: <1155080976.27120@actweb.info>
References: <mailman.1525.1155075610.6425.linuxbios@linuxbios.org>
	<1155080976.27120@actweb.info>
Message-ID: <8a0c36780608090642l5a0fa0f1i82f51b670db5faa4@mail.gmail.com>

On 8/8/06, lists at actweb.info <lists at actweb.info> wrote:
> hi can someone confirm that i have the following correct?

Please adjust your MTA so that we don't get a failure everytime someone does a
"reply to all"  lists at actweb.info isn't valid.


-- 
Richard A. Smith



From stepan at coresystems.de  Wed Aug  9 15:52:22 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 9 Aug 2006 15:52:22 +0200
Subject: [LinuxBIOS] RD1-PL on EPIA-M10000 problem
In-Reply-To: <1155080976.27120@actweb.info>
References: <mailman.1525.1155075610.6425.linuxbios@linuxbios.org>
	<1155080976.27120@actweb.info>
Message-ID: <20060809135222.GA21676@coresystems.de>

* lists at actweb.info <lists at actweb.info> [060809 01:49]:
>  i have an EPIA-M m/board with an SST39SF020A bios chip, along with an
>  RD1-PL 2Mbit bios savour, are these both 2Mb chips? i have tried
>  writing the RD1 with a image file, but it always fails :( anyone any
>  pointers?
> 
> have so far tried to write image aprox 8 times, still with no luck :(
> this is the output from flashrom :-

Have you tried to write it and read it back?
I get the same error
> Enabling flash write on VT8235...tried to set 0x45 to 0x55 on VT8235 failed (WARNING ONLY)
ocassionally, but writing works fine. 

  Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From ollie at lanl.gov  Wed Aug  9 17:26:30 2006
From: ollie at lanl.gov (ollie)
Date: Wed, 09 Aug 2006 09:26:30 -0600
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <200608082053.42949.juergen127@kreuzholzen.de>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608082005.42686.juergen127@kreuzholzen.de>
	<1155061839.22405.29.camel@logarithm.lanl.gov>
	<200608082053.42949.juergen127@kreuzholzen.de>
Message-ID: <1155137190.24601.14.camel@logarithm.lanl.gov>

On Tue, 2006-08-08 at 20:53 +0200, Juergen Beisert wrote:
> >
> > BTW, how "native" is your driver? Do you rd/wrmsr all the operations?
> 
> rd/wrmsr? What does it mean?
> 
> I am using the native PCI hardware and its registers only. AC97 works, I can 
> configure the AC97 codec. Only sending/capturing audio data is missing...
> 

I am sorry that I didn't RTFM but is that there is no physical PCI 
stuff in the GX1 too? Every PCI CS registers are emulated by the
VSA software. Is the 5530 a real and physical PCI device? 

Ollie





From stuge-linuxbios at cdy.org  Wed Aug  9 17:54:04 2006
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Wed, 9 Aug 2006 17:54:04 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <1155137190.24601.14.camel@logarithm.lanl.gov>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608082005.42686.juergen127@kreuzholzen.de>
	<1155061839.22405.29.camel@logarithm.lanl.gov>
	<200608082053.42949.juergen127@kreuzholzen.de>
	<1155137190.24601.14.camel@logarithm.lanl.gov>
Message-ID: <20060809155404.17137.qmail@cdy.org>

On Wed, Aug 09, 2006 at 09:26:30AM -0600, ollie wrote:
> I am sorry that I didn't RTFM but is that there is no physical PCI
> stuff in the GX1 too? Every PCI CS registers are emulated by the
> VSA software. Is the 5530 a real and physical PCI device? 

Yes. From CS5530A.pdf p.117:

"The CS5530A audio hardware includes six PCI bus masters (three for
input and three for output) for transferring digitized audio between
memory and the external codec."


//Peter



From juergen127 at kreuzholzen.de  Wed Aug  9 18:02:00 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Wed, 9 Aug 2006 18:02:00 +0200
Subject: [LinuxBIOS] Geode GX1/5530: How to forward SMI to a regular IRQ
In-Reply-To: <1155137190.24601.14.camel@logarithm.lanl.gov>
References: <200608071119.17303.juergen127@kreuzholzen.de>
	<200608082053.42949.juergen127@kreuzholzen.de>
	<1155137190.24601.14.camel@logarithm.lanl.gov>
Message-ID: <200608091802.00104.juergen127@kreuzholzen.de>

Hi Ollie,

On Wednesday 09 August 2006 17:26, ollie wrote:
> On Tue, 2006-08-08 at 20:53 +0200, Juergen Beisert wrote:
> > > BTW, how "native" is your driver? Do you rd/wrmsr all the operations?
> >
> > rd/wrmsr? What does it mean?
> >
> > I am using the native PCI hardware and its registers only. AC97 works, I
> > can configure the AC97 codec. Only sending/capturing audio data is
> > missing...
>
> I am sorry that I didn't RTFM but is that there is no physical PCI
> stuff in the GX1 too? Every PCI CS registers are emulated by the
> VSA software. Is the 5530 a real and physical PCI device?

The VSA only emulates a soundblaster. So all accesses to legacy io-space will 
trap if enabled.
I'm working with the PCI registers. There are *physical* registers to 
communicate with the external AC97 codec and to setup the master DMA engines 
(PCI function #3 of the kahlua chip is the audio function). FBAR3 points to 
128 bytes memory mapped register space that I'm using.

$ lspci -v
[...]
00:12.3 Multimedia audio controller: Cyrix Corporation 5530 Audio [Kahlua]
        Flags: bus master, medium devsel, latency 0
        Memory at 40011000 (32-bit, non-prefetchable) [size=128]
[...]

Offset           Function
------------------------------------------------------
00..03 Codec GPOIO Status Register
04..07 Codec GPIO Control Register
08..0B Codec Status Register
0C..0F Codec Command Register
10..11 SMI Status Mirror Register
12..13 SMI Status Register
14..17 SMI Trap Status Register
18..19 SMI Trap-Enable Register
1A..1B IRQ Emulation Enable
1C..1D IRQ Emulation Control
1E..1F IRQ Emulation Mask
20..27 DMA Master 0 engine (Playback)
28..2F DMA Master 1 engine (Capture)
30..3F DMA Master 2 engine (Modem out)
38..3F DMA Master 3 engine (Modem in)
40..47 DMA Master 4 engine (Mono out/Modem handset)
48..4F DMA Master 5 engine (Micro in/Modem handset)
50..7F reserved? (no docu available)

Regards,
Juergen




From ben at hewson-venieri.com  Wed Aug  9 19:38:39 2006
From: ben at hewson-venieri.com (Ben Hewson)
Date: Wed, 09 Aug 2006 18:38:39 +0100
Subject: [LinuxBIOS] RD1-PL on EPIA-M10000 problem
In-Reply-To: <20060809135222.GA21676@coresystems.de>
References: <mailman.1525.1155075610.6425.linuxbios@linuxbios.org>	<1155080976.27120@actweb.info>
	<20060809135222.GA21676@coresystems.de>
Message-ID: <44DA1D9F.5010609@hewson-venieri.com>

I had alot of problems with the RD1 bios savior on my EPIA5000 board. I
lost track of the times I tried to flash it, it certainly seemed alot
more than 10 times. In the end I wrote a small script to just sit there
and try and flash the RD1 bios until it verified. It actually worked on
the 5th attempt. I now have the original bios in the RD1 flash and am
using the on-board flash for linuxbios (although it does not boot yet).
The on-board flash, programs first time. There is a note on the
Linuxbios web site about the RD1 bios savior and the fact that it
doesn't program very well. Of course the EPIA-M has a different chipset
so there may be other problems, but I suspect it is just down to the
flash on the RD1.

Ben

> * lists at actweb.info <lists at actweb.info> [060809 01:49]:
>   
>>  i have an EPIA-M m/board with an SST39SF020A bios chip, along with an
>>  RD1-PL 2Mbit bios savour, are these both 2Mb chips? i have tried
>>  writing the RD1 with a image file, but it always fails :( anyone any
>>  pointers?
>>
>> have so far tried to write image aprox 8 times, still with no luck :(
>> this is the output from flashrom :-
>>     
>
> Have you tried to write it and read it back?
> I get the same error
>   
>> Enabling flash write on VT8235...tried to set 0x45 to 0x55 on VT8235 failed (WARNING ONLY)
>>     
> ocassionally, but writing works fine. 
>
>   Stefan
>
>
>   

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060809/ce6dceed/attachment.html>

From uwe at hermann-uwe.de  Thu Aug 10 02:43:02 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 10 Aug 2006 02:43:02 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060807173534.GB30568@coresystems.de>
References: <20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
	<8a0c36780608070809g3ec76c6dnbd74c9f47d035984@mail.gmail.com>
	<20060807152642.GB16605@aragorn>
	<20060807173534.GB30568@coresystems.de>
Message-ID: <20060810004302.GA11237@aragorn>

Hi,

On Mon, Aug 07, 2006 at 07:35:34PM +0200, Stefan Reinauer wrote:
> That's what 
> src/superio/ite/it8671f/it8671f_early_serial.c is good for.
> It should be included in your auto.c file and it8671f_enable_serial()
> from there should be called.

Done, patch attached.

I wasn't able to find a datasheet for the it8671f on the net, so I used
the one from the it8673f, which seems to be reasonably similar.
The patch works for me (I tested serial port 1), but may need some more
polishing and support for floppy and parallel port...


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: it8671f_early_serial.c
===================================================================
--- it8671f_early_serial.c	(Revision 2369)
+++ it8671f_early_serial.c	(Arbeitskopie)
@@ -19,11 +19,73 @@
 #include <arch/romcc_io.h>
 #include "it8671f.h"
 
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE  0x3f0
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA  SIO_BASE+1
+
+/* TODO: These values are actually from the IT8673F datasheet; check if
+   they're also valid for the IT8671F. */
+#define IT8671F_CONFIG_REG_CC       0x02 /* Configure Control. */
+#define IT8671F_CONFIG_REG_LDN      0x07 /* Logical Device Number. */
+#define IT8671F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8671F_CONFIG_REG_SWSUSP   0x24 /* Software Suspend. */
+
+#define IT8671F_ADDRESS_PORT        0x279
+
+/* Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data. */
+static const uint8_t init_values[] = {
+	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+/* The content of IT8671F_CONFIG_REG_LDN (index 07h) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8671F Super IO chip. */
 static void it8671f_enable_serial(device_t dev, unsigned iobase)
 {
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 1);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
+	uint8_t i;
+
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+	outb(0x86, IT8671F_ADDRESS_PORT);
+	outb(0x80, IT8671F_ADDRESS_PORT);
+	outb(0x55, IT8671F_ADDRESS_PORT);
+	outb(0x55, IT8671F_ADDRESS_PORT);
+
+	/* Sequentially write the 32 special values. */
+	for (i = 0; i < 32; i++) {
+		outb(init_values[i], SIO_BASE);
+	}
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Enable parallel port, serial port 1, serial port 2, floppy. */
+	it8671f_sio_write(0x00, 0x23, 0x0f);
+
+	/* Activate serial port 1 and 2. */
+	it8671f_sio_write(0x01, 0x30, 0x1);
+	it8671f_sio_write(0x02, 0x30, 0x1);
+
+	/* Select 24MHz CLKIN and clear software suspend mode. */
+	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); 
 }
 
Index: superio.c
===================================================================
--- superio.c	(Revision 2369)
+++ superio.c	(Arbeitskopie)
@@ -16,12 +16,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-// #include <arch/io.h>
-// #include <device/device.h>
-// #include <device/pnp.h>
-// #include <console/console.h>
-// #include <string.h>
-// #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
 #include "chip.h"
@@ -38,7 +32,10 @@
 
 	conf = dev->chip_info;
 
-	switch(dev->path.u.pnp.device) {
+	switch (dev->path.u.pnp.device) {
+	case IT8671F_FDC:
+		/* TODO. */
+		break;
 	case IT8671F_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com1);
@@ -63,18 +60,13 @@
 	.init             = init,
 };
 
-// TODO.
+/* TODO: Find and check datasheet. */
 static struct pnp_info pnp_dev_info[] = {
-// { &ops, IT8671F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
-// { &ops, IT8671F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, },
+ { &ops, IT8671F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
+ /* { &ops, IT8671F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, */
  { &ops, IT8671F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
  { &ops, IT8671F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-// { &ops, IT8671F_SWC,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
-// { &ops, IT8671F_KBCM, PNP_IRQ0 },
-{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
-// { &ops, IT8671F_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
-// { &ops, IT8671F_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
-// { &ops, IT8671F_RTC,  PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} },
+ { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
 };
 
 static void enable_dev(struct device *dev)
Index: chip.h
===================================================================
--- chip.h	(Revision 2369)
+++ chip.h	(Arbeitskopie)
@@ -19,14 +19,6 @@
 #ifndef _SUPERIO_ITE_IT8671F
 #define _SUPERIO_ITE_IT8671F
 
-// TODO: Unused?
-// #ifndef SIO_COM1
-// #define SIO_COM1_BASE   0x3F8
-// #endif
-// #ifndef SIO_COM2
-// #define SIO_COM2_BASE   0x2F8
-// #endif
-
 #include <pc80/keyboard.h>
 #include <uart8250.h>
 
Index: it8671f.h
===================================================================
--- it8671f.h	(Revision 2369)
+++ it8671f.h	(Arbeitskopie)
@@ -16,20 +16,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-// TODO: Untested, cut'n'pasted from some other file so it's probably wrong.
-// #define IT8671F_FDC  0x00 /* Floppy */
-// #define IT8671F_PP   0x01 /* Parallel port */
+/* TODO: Find datasheet and check for correct values. */
+#define IT8671F_FDC  0x00 /* Floppy */
+/* #define IT8671F_PP   0x01 */ /* Parallel port */
 #define IT8671F_SP2  0x02 /* Com2 */
 #define IT8671F_SP1  0x03 /* Com1 */
-// #define IT8671F_SWC  0x04
-// #define IT8671F_KBCM 0x05 /* Mouse */
 #define IT8671F_KBCK 0x06 /* Keyboard */
-// #define IT8671F_GPIO 0x07
-// #define IT8671F_ACB  0x08
-// #define IT8671F_FSCM 0x09
-// #define IT8671F_WDT  0x0A
-// #define IT8671F_GMP  0x0B
-// #define IT8671F_MIDI 0x0C
-// #define IT8671F_VLM  0x0D
-// #define IT8671F_TMS  0x0E
+/* #define IT8671F_FAN  0x09 */
 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060810/e9543c54/attachment.sig>

From svn at openbios.org  Thu Aug 10 05:23:48 2006
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 10 Aug 2006 05:23:48 +0200
Subject: [LinuxBIOS] r2370 - in trunk/LinuxBIOSv2/src: mainboard/olpc/rev_a
	northbridge/amd/gx2
Message-ID: <E1GB19A-0002AW-EK@khepri.openbios.org>

Author: rminnich
Date: 2006-08-10 05:23:48 +0200 (Thu, 10 Aug 2006)
New Revision: 2370

Modified:
   trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c
   trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c
Log:
change from AMD for the IRQ10 problem.


Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c	2006-08-09 02:21:49 UTC (rev 2369)
+++ trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/auto.c	2006-08-10 03:23:48 UTC (rev 2370)
@@ -149,7 +149,18 @@
         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
 }
 
-	
+static void gpio_init(void)
+{
+	unsigned long m;
+
+	/* Make sure events enable for gpio 12 is off */
+
+	m = inl(GPIOL_EVENTS_ENABLE);
+	m &= ~GPIOL_12_SET;
+	m |= GPIOL_12_CLEAR;
+	outl(m, GPIOL_EVENTS_ENABLE);
+}
+
 static void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
@@ -166,6 +177,7 @@
 	 * for cs5536
 	 */
 	cs5536_setup_onchipuart();
+	gpio_init();
 	uart_init();
 	console_init();
 

Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c	2006-08-09 02:21:49 UTC (rev 2369)
+++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c	2006-08-10 03:23:48 UTC (rev 2370)
@@ -276,11 +276,20 @@
 
 static void northbridge_init(device_t dev) 
 {
+	unsigned long m;
+
 	struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
 	printk_debug("northbridge: %s()\n", __FUNCTION__);
 	
 	enable_shadow(dev);
 	irq_init_steering(dev, nb->irqmap);
+
+	/* HACK HACK HACK HACK */
+	/* 0x1000 is where GPIO is being assigned */
+	m = inl(0x1038);
+	m &= ~GPIOL_12_SET;
+	m |= GPIOL_12_CLEAR;
+	outl(m, 0x1038);
 }
 
 /* due to vsa interactions, we need not not touch the nb settings ... */




From info at coresystems.de  Thu Aug 10 06:02:39 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 10 Aug 2006 06:02:39 +0200
Subject: [LinuxBIOS] LinuxBIOS r2370 build changes
Message-ID: <E1GB1kl-0004qh-Uf@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2370 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
change from AMD for the IRQ10 problem.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From svn at openbios.org  Thu Aug 10 11:38:39 2006
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 10 Aug 2006 11:38:39 +0200
Subject: [LinuxBIOS] r2371 - trunk/LinuxBIOSv2/src/superio/ite/it8671f
Message-ID: <E1GB6zv-0000WO-Ns@khepri.openbios.org>

Author: stepan
Date: 2006-08-10 11:38:39 +0200 (Thu, 10 Aug 2006)
New Revision: 2371

Modified:
   trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h
   trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h
   trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c
   trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c
Log:
fix serial initialization (from Uwe Hermann)


Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h	2006-08-10 03:23:48 UTC (rev 2370)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/chip.h	2006-08-10 09:38:39 UTC (rev 2371)
@@ -19,14 +19,6 @@
 #ifndef _SUPERIO_ITE_IT8671F
 #define _SUPERIO_ITE_IT8671F
 
-// TODO: Unused?
-// #ifndef SIO_COM1
-// #define SIO_COM1_BASE   0x3F8
-// #endif
-// #ifndef SIO_COM2
-// #define SIO_COM2_BASE   0x2F8
-// #endif
-
 #include <pc80/keyboard.h>
 #include <uart8250.h>
 

Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h	2006-08-10 03:23:48 UTC (rev 2370)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h	2006-08-10 09:38:39 UTC (rev 2371)
@@ -16,20 +16,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-// TODO: Untested, cut'n'pasted from some other file so it's probably wrong.
-// #define IT8671F_FDC  0x00 /* Floppy */
-// #define IT8671F_PP   0x01 /* Parallel port */
+/* TODO: Find datasheet and check for correct values. */
+#define IT8671F_FDC  0x00 /* Floppy */
+/* #define IT8671F_PP   0x01 */ /* Parallel port */
 #define IT8671F_SP2  0x02 /* Com2 */
 #define IT8671F_SP1  0x03 /* Com1 */
-// #define IT8671F_SWC  0x04
-// #define IT8671F_KBCM 0x05 /* Mouse */
 #define IT8671F_KBCK 0x06 /* Keyboard */
-// #define IT8671F_GPIO 0x07
-// #define IT8671F_ACB  0x08
-// #define IT8671F_FSCM 0x09
-// #define IT8671F_WDT  0x0A
-// #define IT8671F_GMP  0x0B
-// #define IT8671F_MIDI 0x0C
-// #define IT8671F_VLM  0x0D
-// #define IT8671F_TMS  0x0E
+/* #define IT8671F_FAN  0x09 */
 

Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c	2006-08-10 03:23:48 UTC (rev 2370)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c	2006-08-10 09:38:39 UTC (rev 2371)
@@ -19,11 +19,73 @@
 #include <arch/romcc_io.h>
 #include "it8671f.h"
 
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE  0x3f0
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA  SIO_BASE+1
+
+/* TODO: These values are actually from the IT8673F datasheet; check if
+   they're also valid for the IT8671F. */
+#define IT8671F_CONFIG_REG_CC       0x02 /* Configure Control. */
+#define IT8671F_CONFIG_REG_LDN      0x07 /* Logical Device Number. */
+#define IT8671F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8671F_CONFIG_REG_SWSUSP   0x24 /* Software Suspend. */
+
+#define IT8671F_ADDRESS_PORT        0x279
+
+/* Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data. */
+static const uint8_t init_values[] = {
+	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+/* The content of IT8671F_CONFIG_REG_LDN (index 07h) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8671F Super IO chip. */
 static void it8671f_enable_serial(device_t dev, unsigned iobase)
 {
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 1);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
+	uint8_t i;
+
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+	outb(0x86, IT8671F_ADDRESS_PORT);
+	outb(0x80, IT8671F_ADDRESS_PORT);
+	outb(0x55, IT8671F_ADDRESS_PORT);
+	outb(0x55, IT8671F_ADDRESS_PORT);
+
+	/* Sequentially write the 32 special values. */
+	for (i = 0; i < 32; i++) {
+		outb(init_values[i], SIO_BASE);
+	}
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Enable parallel port, serial port 1, serial port 2, floppy. */
+	it8671f_sio_write(0x00, 0x23, 0x0f);
+
+	/* Activate serial port 1 and 2. */
+	it8671f_sio_write(0x01, 0x30, 0x1);
+	it8671f_sio_write(0x02, 0x30, 0x1);
+
+	/* Select 24MHz CLKIN and clear software suspend mode. */
+	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); 
 }
 

Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c	2006-08-10 03:23:48 UTC (rev 2370)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c	2006-08-10 09:38:39 UTC (rev 2371)
@@ -16,12 +16,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-// #include <arch/io.h>
-// #include <device/device.h>
-// #include <device/pnp.h>
-// #include <console/console.h>
-// #include <string.h>
-// #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
 #include "chip.h"
@@ -38,7 +32,10 @@
 
 	conf = dev->chip_info;
 
-	switch(dev->path.u.pnp.device) {
+	switch (dev->path.u.pnp.device) {
+	case IT8671F_FDC:
+		/* TODO. */
+		break;
 	case IT8671F_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com1);
@@ -63,18 +60,13 @@
 	.init             = init,
 };
 
-// TODO.
+/* TODO: Find and check datasheet. */
 static struct pnp_info pnp_dev_info[] = {
-// { &ops, IT8671F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
-// { &ops, IT8671F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, },
+ { &ops, IT8671F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
+ /* { &ops, IT8671F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, */
  { &ops, IT8671F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
  { &ops, IT8671F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-// { &ops, IT8671F_SWC,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
-// { &ops, IT8671F_KBCM, PNP_IRQ0 },
-{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
-// { &ops, IT8671F_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
-// { &ops, IT8671F_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
-// { &ops, IT8671F_RTC,  PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} },
+ { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
 };
 
 static void enable_dev(struct device *dev)




From stepan at coresystems.de  Thu Aug 10 11:38:47 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 10 Aug 2006 11:38:47 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060810004302.GA11237@aragorn>
References: <20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
	<8a0c36780608070809g3ec76c6dnbd74c9f47d035984@mail.gmail.com>
	<20060807152642.GB16605@aragorn>
	<20060807173534.GB30568@coresystems.de>
	<20060810004302.GA11237@aragorn>
Message-ID: <20060810093847.GA1743@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060810 02:43]:
> Hi,
> 
> On Mon, Aug 07, 2006 at 07:35:34PM +0200, Stefan Reinauer wrote:
> > That's what 
> > src/superio/ite/it8671f/it8671f_early_serial.c is good for.
> > It should be included in your auto.c file and it8671f_enable_serial()
> > from there should be called.
> 
> Done, patch attached.

Thank you! 

Patch committed.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From info at coresystems.de  Thu Aug 10 12:17:55 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 10 Aug 2006 12:17:55 +0200
Subject: [LinuxBIOS] LinuxBIOS r2371 build changes
Message-ID: <E1GB7bv-0002Gd-6y@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2371 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
fix serial initialization (from Uwe Hermann)

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From rminnich at lanl.gov  Thu Aug 10 16:06:23 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 10 Aug 2006 08:06:23 -0600
Subject: [LinuxBIOS] smsc dme1737 data book -- anybody got it?
Message-ID: <44DB3D5F.4010009@lanl.gov>


smsc appears not to have the data sheets for dme1737. All I can find is 
a 6-page useless document. Anyone seen a data sheet for this part?

ron



From jfaslist at yahoo.fr  Thu Aug 10 16:43:27 2006
From: jfaslist at yahoo.fr (jf simon)
Date: Thu, 10 Aug 2006 16:43:27 +0200
Subject: [LinuxBIOS] AMD Turion - AGESA
Message-ID: <44DB460F.5060706@yahoo.fr>

Hi,
The company i worked for has designed a card that uses the AMD 
Turion. It uses the PHOENIX Bios.
I am trying to port linuxbios to it. But among other issues, one 
hardware engineer told me to make sure that linuxbios was using 
the latest AGESA code from AMD (from what i understand that code 
changes the CPU processor state, frequency,...)as it seems we had 
trouble in the past getting the right BIOS with the latest AGESA 
code.

How does linuxbios  manage to do the same thing as the agesa code 
(and at what agesa version)? If so what is the file location that 
handles it?

Thanks a lot,
-jf simon




	

	
		
___________________________________________________________________________ 
D?couvrez un nouveau moyen de poser toutes vos questions quelque soit le sujet ! 
Yahoo! Questions/R?ponses pour partager vos connaissances, vos opinions et vos exp?riences. 
http://fr.answers.yahoo.com 





From rminnich at lanl.gov  Thu Aug 10 16:55:26 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 10 Aug 2006 08:55:26 -0600
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <44DB460F.5060706@yahoo.fr>
References: <44DB460F.5060706@yahoo.fr>
Message-ID: <44DB48DE.9040102@lanl.gov>

jf simon wrote:
> Hi,
> The company i worked for has designed a card that uses the AMD Turion. 
> It uses the PHOENIX Bios.
> I am trying to port linuxbios to it. But among other issues, one 
> hardware engineer told me to make sure that linuxbios was using the 
> latest AGESA code from AMD (from what i understand that code changes the 
> CPU processor state, frequency,...)as it seems we had trouble in the 
> past getting the right BIOS with the latest AGESA code.
> 
> How does linuxbios  manage to do the same thing as the agesa code (and 
> at what agesa version)? If so what is the file location that handles it?

another acronum I don't understand. What is AGESA?

ron



From jfaslist at yahoo.fr  Thu Aug 10 17:33:42 2006
From: jfaslist at yahoo.fr (jf simon)
Date: Thu, 10 Aug 2006 17:33:42 +0200
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <44DB48DE.9040102@lanl.gov>
References: <44DB460F.5060706@yahoo.fr> <44DB48DE.9040102@lanl.gov>
Message-ID: <44DB51D6.5040203@yahoo.fr>

Hi,

Ronald G Minnich wrote:

>
>another acronum I don't understand. What is AGESA?
>
>ron
>
>  
>
Sorry about that. It stands for AMD Generic & Encapsulated Software 
Architecture. From :
http://www.ami.com/news/pressshow.cfm?PrID=187

"...The AMD Generic Encapsulated Software Architecture (AGESA) is a 
library of validated processor procedures designed to aid customers with 
quick adoption of AMD technology into their products. AMI?s drop-in 
support of AGESA allows minimal time-to-market for APTIO? customers to 
integrate AMD Processor Solutions into their products. AMI?s integration 
in APTIO? indicates that AGESA? code is versatile enough that it can be 
dropped in totally new architecture (UEFI) with minimal build changes...."

I was told that this agesa code was responsible at power-up, for 
changing the CPU "P-state" from Min P-state, (minimum frequency, reduced 
power consumption) to the maximum performance max P-state. Could you 
plse point me in the linuxbios code, where this achieved?

Thanks a lot
-jf simon


	

	
		
___________________________________________________________________________ 
D?couvrez un nouveau moyen de poser toutes vos questions quelque soit le sujet ! 
Yahoo! Questions/R?ponses pour partager vos connaissances, vos opinions et vos exp?riences. 
http://fr.answers.yahoo.com 





From rminnich at lanl.gov  Thu Aug 10 18:01:20 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 10 Aug 2006 10:01:20 -0600
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <44DB51D6.5040203@yahoo.fr>
References: <44DB460F.5060706@yahoo.fr> <44DB48DE.9040102@lanl.gov>
	<44DB51D6.5040203@yahoo.fr>
Message-ID: <44DB5850.3070809@lanl.gov>

jf simon wrote:

> I was told that this agesa code was responsible at power-up, for 
> changing the CPU "P-state" from Min P-state, (minimum frequency, reduced 
> power consumption) to the maximum performance max P-state. Could you 
> plse point me in the linuxbios code, where this achieved?


looks like another nice piece of software to support binary BIOSes? Is 
the source available?

ron



From jfaslist at yahoo.fr  Thu Aug 10 18:17:17 2006
From: jfaslist at yahoo.fr (jf simon)
Date: Thu, 10 Aug 2006 18:17:17 +0200
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <44DB5850.3070809@lanl.gov>
References: <44DB460F.5060706@yahoo.fr> <44DB48DE.9040102@lanl.gov>
	<44DB51D6.5040203@yahoo.fr> <44DB5850.3070809@lanl.gov>
Message-ID: <44DB5C0D.1060903@yahoo.fr>

Ronald G Minnich wrote:

> looks like another nice piece of software to support binary BIOSes? Is 
> the source available?
> ron
>
No. AMD told us they give it to bios vendors only.
-jf simon


	

	
		
___________________________________________________________________________ 
D?couvrez un nouveau moyen de poser toutes vos questions quelque soit le sujet ! 
Yahoo! Questions/R?ponses pour partager vos connaissances, vos opinions et vos exp?riences. 
http://fr.answers.yahoo.com 





From rminnich at lanl.gov  Thu Aug 10 18:17:13 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 10 Aug 2006 10:17:13 -0600
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <44DB5C0D.1060903@yahoo.fr>
References: <44DB460F.5060706@yahoo.fr> <44DB48DE.9040102@lanl.gov>
	<44DB51D6.5040203@yahoo.fr> <44DB5850.3070809@lanl.gov>
	<44DB5C0D.1060903@yahoo.fr>
Message-ID: <44DB5C09.9070603@lanl.gov>

jf simon wrote:
> Ronald G Minnich wrote:
> 
>> looks like another nice piece of software to support binary BIOSes? Is 
>> the source available?
>> ron
>>
> No. AMD told us they give it to bios vendors only.
> -jf simon

my suspicion is we don't need it.

YH? Any word on what this is?

ron



From yinghai.lu at amd.com  Thu Aug 10 18:34:32 2006
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Thu, 10 Aug 2006 09:34:32 -0700
Subject: [LinuxBIOS] AMD Turion - AGESA
Message-ID: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>

AGESA is in assembly code now, and it is only can be released to IBV
under NDA. IBV use the source code in their framework.

Current LinuxBIOS support code for rev F are LinuxBIOS native code. 

YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Ronald G Minnich
Sent: Thursday, August 10, 2006 9:17 AM
To: jf simon
Cc: linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] AMD Turion - AGESA

jf simon wrote:
> Ronald G Minnich wrote:
> 
>> looks like another nice piece of software to support binary BIOSes?
Is 
>> the source available?
>> ron
>>
> No. AMD told us they give it to bios vendors only.
> -jf simon

my suspicion is we don't need it.

YH? Any word on what this is?

ron

-- 
linuxbios mailing list
linuxbios at linuxbios.org
http://www.openbios.org/mailman/listinfo/linuxbios







From rminnich at lanl.gov  Thu Aug 10 18:33:20 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Thu, 10 Aug 2006 10:33:20 -0600
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
Message-ID: <44DB5FD0.7030307@lanl.gov>

Lu, Yinghai wrote:
> AGESA is in assembly code now, and it is only can be released to IBV
> under NDA. IBV use the source code in their framework.
> 
> Current LinuxBIOS support code for rev F are LinuxBIOS native code. 

so we don't need agesa.

ron



From jfaslist at yahoo.fr  Thu Aug 10 18:43:45 2006
From: jfaslist at yahoo.fr (jf simon)
Date: Thu, 10 Aug 2006 18:43:45 +0200
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
Message-ID: <44DB6241.7050406@yahoo.fr>

Lu, Yinghai wrote:

>AGESA is in assembly code now, and it is only can be released to IBV
>under NDA. IBV use the source code in their framework.
>
>Current LinuxBIOS support code for rev F are LinuxBIOS native code. 
>
>YH
>
>  
>

I am new to linuxbios and I would appreciate if you could point me to 
the place where linuxbios is doing what AGESA does (that is when  the 
CPU is set from its min P-state to max P-State)?
Thanks a lot
-jf simon

	
 p4.vert.ukl.yahoo.com uncompressed Thu Aug 10 16:27:00 GMT 2006 
	
		
___________________________________________________________________________ 
D?couvrez un nouveau moyen de poser toutes vos questions quelque soit le sujet ! 
Yahoo! Questions/R?ponses pour partager vos connaissances, vos opinions et vos exp?riences. 
http://fr.answers.yahoo.com 





From yinghai.lu at amd.com  Thu Aug 10 19:09:49 2006
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Thu, 10 Aug 2006 10:09:49 -0700
Subject: [LinuxBIOS] boot windows, BSD and solaris on x86
Message-ID: <6F7DA19D05F3CF40B890C7CA2DB13A4207004129@ssvlexmb2.amd.com>

Eric,

Anyone try to use kexec to boot windows, BSD and solaris on x86?

YH





From svn at openbios.org  Fri Aug 11 02:08:38 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 11 Aug 2006 02:08:38 +0200
Subject: [LinuxBIOS] r2372 - trunk/LinuxBIOSv2/targets/olpc/rev_a
Message-ID: <E1GBKZq-0004C5-0c@khepri.openbios.org>

Author: rminnich
Date: 2006-08-11 02:08:37 +0200 (Fri, 11 Aug 2006)
New Revision: 2372

Modified:
   trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb
Log:
build 1024-128k binary as per requests.


Modified: trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb	2006-08-10 09:38:39 UTC (rev 2371)
+++ trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb	2006-08-11 00:08:37 UTC (rev 2372)
@@ -8,7 +8,7 @@
 #option CONFIG_PRECOMPRESSED_ROM_STREAM=1
 
 # leave 64k for vsa
-option ROM_SIZE=1024*1024-64*1024
+option ROM_SIZE=1024*1024-64*1024-64*1024
 option FALLBACK_SIZE=ROM_SIZE
 
 option DEFAULT_CONSOLE_LOGLEVEL = 11




From info at coresystems.de  Fri Aug 11 02:46:07 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 11 Aug 2006 02:46:07 +0200
Subject: [LinuxBIOS] LinuxBIOS r2372 build changes
Message-ID: <E1GBLA7-00056M-K3@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2372 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
build 1024-128k binary as per requests.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From svn at openbios.org  Fri Aug 11 08:49:40 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 11 Aug 2006 08:49:40 +0200
Subject: [LinuxBIOS] r2373 - trunk/LinuxBIOSv2/util/newconfig
Message-ID: <E1GBQpw-000474-6N@khepri.openbios.org>

Author: rsmith
Date: 2006-08-11 08:49:39 +0200 (Fri, 11 Aug 2006)
New Revision: 2373

Modified:
   trunk/LinuxBIOSv2/util/newconfig/config.g
Log:
- fix dependency rule for Makefile and Makefile.settings

The make dependency rule for Makefile and Makefile.settings was completely broken.  No way it ever worked.
OLPC buildrom flushed out this issue.

If you updated the Config.lb file in your target/<mfg>/<mainboard> directory and then switched to 
target/<mfg>/<mainboard>/<target> and ran 'make' you would get a permission denied error due to the 
make file trying to run 'config.py' directly rather than 'python config.py'
We never saw this because we always run target/buildtarget <target> and that sets up everything
correctly.



Modified: trunk/LinuxBIOSv2/util/newconfig/config.g
===================================================================
--- trunk/LinuxBIOSv2/util/newconfig/config.g	2006-08-11 00:08:37 UTC (rev 2372)
+++ trunk/LinuxBIOSv2/util/newconfig/config.g	2006-08-11 06:49:39 UTC (rev 2373)
@@ -1933,8 +1933,8 @@
 def writemakefilefooter(file, fname):
 	file.write("\n\n%s: %s %s\n"
 		% (os.path.basename(fname), os.path.abspath(sys.argv[0]), top_config_file))
-	file.write("\t(cd %s ; %s %s %s)\n\n"
-		% (os.getcwd(), sys.argv[0], sys.argv[1], sys.argv[2]))
+	file.write("\t(cd %s ; export PYTHONPATH=%s/util/newconfig ; python %s %s %s)\n\n"
+		% (os.getcwd(), treetop, sys.argv[0], sys.argv[1], sys.argv[2]))
 
 def writemakefilesettings(path):
 	""" Write Makefile.settings to seperate the settings




From info at coresystems.de  Fri Aug 11 09:27:38 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 11 Aug 2006 09:27:38 +0200
Subject: [LinuxBIOS] LinuxBIOS r2373 build changes
Message-ID: <E1GBRQg-0005Dp-2D@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rsmith" checked in revision 2373 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
- fix dependency rule for Makefile and Makefile.settingsThe make dependency rule for Makefile and Makefile.settings was completely broken.  No way it ever worked.OLPC buildrom flushed out this issue.If you updated the Config.lb file in your target/<mfg>/<mainboard> directory and then switched totarget/<mfg>/<mainboard>/<target> and ran 'make' you would get a permission denied error due to themake file trying to run 'config.py' directly rather than 'python config.py'We never saw this because we always run target/buildtarget <target> and that sets up everythingcorrectly.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in rsmith's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From svn at openbios.org  Fri Aug 11 10:15:19 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 11 Aug 2006 10:15:19 +0200
Subject: [LinuxBIOS] r2374 - trunk/LinuxBIOSv2/targets/olpc/rev_a
Message-ID: <E1GBSAp-0005jU-Ja@khepri.openbios.org>

Author: rsmith
Date: 2006-08-11 10:15:19 +0200 (Fri, 11 Aug 2006)
New Revision: 2374

Added:
   trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.SPI.lb
Modified:
   trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb
Log:
- revert Config.1M.lb back to PLCC size and add new SPI config file

SPI config file is 1M-128k to allow for EC code


Modified: trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb	2006-08-11 06:49:39 UTC (rev 2373)
+++ trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.1M.lb	2006-08-11 08:15:19 UTC (rev 2374)
@@ -8,7 +8,7 @@
 #option CONFIG_PRECOMPRESSED_ROM_STREAM=1
 
 # leave 64k for vsa
-option ROM_SIZE=1024*1024-64*1024-64*1024
+option ROM_SIZE=(1024*1024)-(64*1024)
 option FALLBACK_SIZE=ROM_SIZE
 
 option DEFAULT_CONSOLE_LOGLEVEL = 11

Added: trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.SPI.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.SPI.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/olpc/rev_a/Config.SPI.lb	2006-08-11 08:15:19 UTC (rev 2374)
@@ -0,0 +1,23 @@
+# Config file for the olpc rev_a
+
+target rev_a_1M
+mainboard olpc/rev_a
+
+# Don't let LinuxBIOS compress the payload
+# option CONFIG_COMPRESSED_ROM_STREAM=0
+#option CONFIG_PRECOMPRESSED_ROM_STREAM=1
+
+# leave 64k for vsa and 64k for EC code
+option ROM_SIZE=(1024*1024)-(64*1024)-(64*1024)
+option FALLBACK_SIZE=ROM_SIZE
+
+option DEFAULT_CONSOLE_LOGLEVEL = 11
+option MAXIMUM_CONSOLE_LOGLEVEL = 11
+romimage "fallback" 
+	option USE_FALLBACK_IMAGE=1
+	option ROM_IMAGE_SIZE=32*1024
+	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+	payload /tmp/olpcpayload.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE  "fallback"




From info at coresystems.de  Fri Aug 11 10:53:08 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 11 Aug 2006 10:53:08 +0200
Subject: [LinuxBIOS] LinuxBIOS r2374 build changes
Message-ID: <E1GBSlQ-00072D-L5@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rsmith" checked in revision 2374 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
- revert Config.1M.lb back to PLCC size and add new SPI config fileSPI config file is 1M-128k to allow for EC code

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in rsmith's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From jfaslist at yahoo.fr  Fri Aug 11 14:32:33 2006
From: jfaslist at yahoo.fr (jf simon)
Date: Fri, 11 Aug 2006 14:32:33 +0200
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <44DB5FD0.7030307@lanl.gov>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
	<44DB5FD0.7030307@lanl.gov>
Message-ID: <44DC78E1.9000001@yahoo.fr>

Hi Ron,

Ronald G Minnich wrote:

>Lu, Yinghai wrote:
>  
>
>>AGESA is in assembly code now, and it is only can be released to IBV
>>under NDA. IBV use the source code in their framework.
>>
>>Current LinuxBIOS support code for rev F are LinuxBIOS native code. 
>>    
>>
>
>so we don't need agesa.
>
>ron
>
>  
>
I have read on the mailing list that Intel didn't want to see linuxbios 
running on their CPUs (certainly a shame). But it was my understanding 
that AMD was willing to share information so that linubios runs on AMD 
CPUs. Is this true? The agesa  thing seems to contradict this since AMD 
doesn't provide the code of it.
Thanks
-jf simon

	
 p5.vert.ukl.yahoo.com uncompressed Fri Aug 11 12:27:00 GMT 2006 
	
		
___________________________________________________________________________ 
D?couvrez un nouveau moyen de poser toutes vos questions quelque soit le sujet ! 
Yahoo! Questions/R?ponses pour partager vos connaissances, vos opinions et vos exp?riences. 
http://fr.answers.yahoo.com 





From ebiederman at lnxi.com  Fri Aug 11 14:44:55 2006
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Fri, 11 Aug 2006 06:44:55 -0600
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <44DC78E1.9000001@yahoo.fr> (jf simon's message of "Fri, 11 Aug
	2006 14:32:33 +0200")
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
	<44DB5FD0.7030307@lanl.gov> <44DC78E1.9000001@yahoo.fr>
Message-ID: <m3k65figqg.fsf@maxwell.lnxi.com>

jf simon <jfaslist at yahoo.fr> writes:

> I have read on the mailing list that Intel didn't want to see linuxbios 
> running on their CPUs (certainly a shame). But it was my understanding 
> that AMD was willing to share information so that linubios runs on AMD 
> CPUs. Is this true? The agesa  thing seems to contradict this since AMD 
> doesn't provide the code of it.

Neither is true.
As this thread clarified even the latest AMD work does not require AGESA.

In addition while it sucks to work with Intel you can work with them,
if you have an appropriate business case.  We coming close to getting
having a port to the latest Intel chipset completed.

There are camps within Intel that are strongly opposed to the idea of LinuxBIOS
in general.  But those camps are not the ones making the decision.

AMD has a general policy of being friendly and enabling inovators
(or something like that), making AMD much easier to deal with.

Eric



From uwe at hermann-uwe.de  Fri Aug 11 14:57:53 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 11 Aug 2006 14:57:53 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060810093847.GA1743@coresystems.de>
References: <20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
	<8a0c36780608070809g3ec76c6dnbd74c9f47d035984@mail.gmail.com>
	<20060807152642.GB16605@aragorn>
	<20060807173534.GB30568@coresystems.de>
	<20060810004302.GA11237@aragorn>
	<20060810093847.GA1743@coresystems.de>
Message-ID: <20060811125753.GB695@aragorn>

Hi,

On Thu, Aug 10, 2006 at 11:38:47AM +0200, Stefan Reinauer wrote:
> Patch committed.

Thanks! For consistency reasons, shouldn't the ite/ directory be
named ITE/? Either that, or NSC/ should be called nsc/?

Also, what about the variable names? Should they be called *_ITE_*
or *_ite_*?


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060811/eeaef20d/attachment.sig>

From stuge-linuxbios at cdy.org  Fri Aug 11 15:27:19 2006
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Fri, 11 Aug 2006 15:27:19 +0200
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <m3k65figqg.fsf@maxwell.lnxi.com> <44DC78E1.9000001@yahoo.fr>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
	<44DB5FD0.7030307@lanl.gov> <44DC78E1.9000001@yahoo.fr>
	<m3k65figqg.fsf@maxwell.lnxi.com>
	<6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
	<44DB5FD0.7030307@lanl.gov> <44DC78E1.9000001@yahoo.fr>
Message-ID: <20060811132719.22061.qmail@cdy.org>

On Fri, Aug 11, 2006 at 02:32:33PM +0200, jf simon wrote:
> But it was my understanding that AMD was willing to share
> information so that linubios runs on AMD CPUs. Is this true?

It is certainly true. There is at least one person active on this
mailing list working for AMD who contributes a lot of information
and code.


> The agesa  thing seems to contradict this since AMD doesn't provide
> the code of it.

On Fri, Aug 11, 2006 at 06:44:55AM -0600, Eric W. Biederman wrote:
> As this thread clarified even the latest AMD work does not require
> AGESA.

To re-iterate, AGESA is not useful in LinuxBIOS - from what I
understand it's a bunch of assembly that "plugs in" to traditional
BIOS codebases in order to quickly assemble a new BIOS for a
particular AMD CPU.

Traditional BIOS codebases are generally all assembly and not very
well-designed. I would argue that LinuxBIOS is the opposite.

LinuxBIOS has excellent support for several AMD CPUs, lately a lot
of work is going into the GX2 platform since that's what OLPC is
using. Earlier lots of effort was put into making Opteron based
servers work perfectly.

Look around in the source tree. It has a little bit of a learning
curve (which I haven't climbed to the top) but you should be able
find your way around pretty quickly.

I'd suggest looking around in the src/cpu/amd/model_fxx and
src/northbridge/amd/amdk8 directories for interesting code.

E.g. src/cpu/amd/model_fxx/model_fxx_init.c at 14kb might be what
you're asking for.


//Peter



From uwe at hermann-uwe.de  Fri Aug 11 15:28:56 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 11 Aug 2006 15:28:56 +0200
Subject: [LinuxBIOS] smsc dme1737 data book -- anybody got it?
In-Reply-To: <44DB3D5F.4010009@lanl.gov>
References: <44DB3D5F.4010009@lanl.gov>
Message-ID: <20060811132856.GC695@aragorn>

Hi,

On Thu, Aug 10, 2006 at 08:06:23AM -0600, Ronald G Minnich wrote:
> smsc appears not to have the data sheets for dme1737. All I can find is 
> a 6-page useless document. Anyone seen a data sheet for this part?

I didn't find anything more detailed than the 6 page PDF either.

Maybe some of these people can help:

 * http://lists.lm-sensors.org/pipermail/lm-sensors/2006-May/016175.html

 * http://www.almico.com/sfhistory.php
   (says "added full support for SMSC DME1737" on that page)


What experience did you guys have with asking vendors for datasheets -
does that usually work? Should you mention you need it for adding LinuxBIOS
support, or does that reduce your chances to get the datasheet?

Obviously, there's no use in getting a datasheet under NDA, we wouldn't
be able to distribute code derived from that under the GPL, right?

Specifically, I'm looking for the IT8671F datasheet, which I cannot find
on the net, either. Should I contact ITE?


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060811/d4d39d3b/attachment.sig>

From smithbone at gmail.com  Fri Aug 11 15:32:41 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 11 Aug 2006 08:32:41 -0500
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <20060811132719.22061.qmail@cdy.org>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
	<44DB5FD0.7030307@lanl.gov> <m3k65figqg.fsf@maxwell.lnxi.com>
	<44DC78E1.9000001@yahoo.fr> <20060811132719.22061.qmail@cdy.org>
Message-ID: <8a0c36780608110632ja0acfev8710e0e60c428bac@mail.gmail.com>

> LinuxBIOS has excellent support for several AMD CPUs, lately a lot
> of work is going into the GX2 platform since that's what OLPC is
> using. Earlier lots of effort was put into making Opteron based

Indeed and its just about ready to come alive and kicking.  Just a few
more kinks to work out.  Most of which aren't really even LinuxBIOS
kinks.  Look for to show up on a in a test board RSN.

-- 
Richard A. Smith



From smithbone at gmail.com  Fri Aug 11 15:41:38 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 11 Aug 2006 08:41:38 -0500
Subject: [LinuxBIOS] smsc dme1737 data book -- anybody got it?
In-Reply-To: <20060811132856.GC695@aragorn>
References: <44DB3D5F.4010009@lanl.gov> <20060811132856.GC695@aragorn>
Message-ID: <8a0c36780608110641q51e84892r42c12789ad01ef86@mail.gmail.com>

> What experience did you guys have with asking vendors for datasheets -
> does that usually work? Should you mention you need it for adding LinuxBIOS
> support, or does that reduce your chances to get the datasheet?

Depends on the company.  Pretty much have to make that call on a case
by case basis.

> Obviously, there's no use in getting a datasheet under NDA, we wouldn't
> be able to distribute code derived from that under the GPL, right?

Again Depends.  Some companies will allow you to release code based on
docs under NDA but you need to make sure you know this _before_ you
look at the docs or your code could be considered violating the NDA.

> Specifically, I'm looking for the IT8671F datasheet, which I cannot find
> on the net, either. Should I contact ITE?

What vendor carries ITE in its linecard?  Perhaps can get a copy
somewhere through our vendors.

-- 
Richard A. Smith



From smithbone at gmail.com  Fri Aug 11 15:47:23 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 11 Aug 2006 08:47:23 -0500
Subject: [LinuxBIOS] smsc dme1737 data book -- anybody got it?
In-Reply-To: <8a0c36780608110641q51e84892r42c12789ad01ef86@mail.gmail.com>
References: <44DB3D5F.4010009@lanl.gov> <20060811132856.GC695@aragorn>
	<8a0c36780608110641q51e84892r42c12789ad01ef86@mail.gmail.com>
Message-ID: <8a0c36780608110647m1e730311h92c66c49c4b08b12@mail.gmail.com>

 > What vendor carries ITE in its linecard?  Perhaps can get a copy
> somewhere through our vendors.

Answering myself.  Webpage has mostly overseas distributors.  E-Proxy,
Inc is the only US vendor listed.  Not any that we do buisness with.

You might contact E-Proxy and see what they say.

-- 
Richard A. Smith



From uwe at hermann-uwe.de  Fri Aug 11 19:32:54 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 11 Aug 2006 19:32:54 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060806195215.GB27511@aragorn>
References: <20060731233623.GA7869@aragorn>
	<20060731234151.GA25670@coresystems.de>
	<20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
Message-ID: <20060811173253.GA24894@aragorn>

Hi,

On Sun, Aug 06, 2006 at 09:52:15PM +0200, Uwe Hermann wrote:
> Btw, is the following snippet needed in chip.h?
> 
> #ifndef SIO_COM1
> #define SIO_COM1_BASE   0x3F8
> #endif
> #ifndef SIO_COM2
> #define SIO_COM2_BASE   0x2F8
> #endif

Responding to myself, here's a bold patch to remove all of them.
I don't see them used anywhere, but I might be wrong.


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: winbond/w83627thf/chip.h
===================================================================
--- winbond/w83627thf/chip.h	(Revision 2374)
+++ winbond/w83627thf/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_winbond_w83627thf_ops;
 
 #include <pc80/keyboard.h>
Index: winbond/w83977tf/chip.h
===================================================================
--- winbond/w83977tf/chip.h	(Revision 2374)
+++ winbond/w83977tf/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_winbond_w83977tf_ops;
 
 #include <pc80/keyboard.h>
Index: winbond/w83627hf/chip.h
===================================================================
--- winbond/w83627hf/chip.h	(Revision 2374)
+++ winbond/w83627hf/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_winbond_w83627hf_ops;
 
 #include <pc80/keyboard.h>
Index: NSC/pc87366/chip.h
===================================================================
--- NSC/pc87366/chip.h	(Revision 2374)
+++ NSC/pc87366/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_NSC_pc87366_ops;
 
 #include <pc80/keyboard.h>
Index: NSC/pc8374/chip.h
===================================================================
--- NSC/pc8374/chip.h	(Revision 2374)
+++ NSC/pc8374/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_NSC_pc8374_ops;
 
Index: NSC/pc87360/chip.h
===================================================================
--- NSC/pc87360/chip.h	(Revision 2374)
+++ NSC/pc87360/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_NSC_pc87360_ops;
 
Index: NSC/pc87351/chip.h
===================================================================
--- NSC/pc87351/chip.h	(Revision 2374)
+++ NSC/pc87351/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_NSC_pc87351_ops;
 
Index: NSC/pc97307/chip.h
===================================================================
--- NSC/pc97307/chip.h	(Revision 2374)
+++ NSC/pc97307/chip.h	(Arbeitskopie)
@@ -7,12 +7,6 @@
 #ifndef PNP_DATA_REG
 #define PNP_DATA_REG    0x15D
 #endif
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
 
 extern struct chip_operations superio_NSC_pc97307_ops;
 
Index: NSC/pc87417/chip.h
===================================================================
--- NSC/pc87417/chip.h	(Revision 2374)
+++ NSC/pc87417/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_NSC_pc87417_ops;
 
 #include <pc80/keyboard.h>
Index: NSC/pc97317/chip.h
===================================================================
--- NSC/pc97317/chip.h	(Revision 2374)
+++ NSC/pc97317/chip.h	(Arbeitskopie)
@@ -7,12 +7,6 @@
 #ifndef PNP_DATA_REG
 #define PNP_DATA_REG    0x15D
 #endif
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
 
 extern struct chip_operations superio_NSC_pc97317_ops;
 
Index: NSC/pc87427/chip.h
===================================================================
--- NSC/pc87427/chip.h	(Revision 2374)
+++ NSC/pc87427/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_NSC_pc87427_ops;
 
 #include <pc80/keyboard.h>
Index: smsc/lpc47n217/chip.h
===================================================================
--- smsc/lpc47n217/chip.h	(Revision 2374)
+++ smsc/lpc47n217/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_smsc_lpc47n217_ops;
 
Index: smsc/lpc47b272/chip.h
===================================================================
--- smsc/lpc47b272/chip.h	(Revision 2374)
+++ smsc/lpc47b272/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_smsc_lpc47b272_ops;
 
Index: smsc/lpc47b397/chip.h
===================================================================
--- smsc/lpc47b397/chip.h	(Revision 2374)
+++ smsc/lpc47b397/chip.h	(Arbeitskopie)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_smsc_lpc47b397_ops;
 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060811/01b900c0/attachment.sig>

From rminnich at lanl.gov  Fri Aug 11 19:37:42 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Fri, 11 Aug 2006 11:37:42 -0600
Subject: [LinuxBIOS] Success.
In-Reply-To: <20060811173253.GA24894@aragorn>
References: <20060731233623.GA7869@aragorn>	<20060731234151.GA25670@coresystems.de>	<20060731235718.GC7869@aragorn>	<20060801120221.GA17269@coresystems.de>	<20060803220502.GA18987@aragorn>	<20060803224345.GC5055@coresystems.de>	<20060804014548.GA30639@aragorn>
	<20060804204410.GB17104@aragorn>	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>	<20060806195215.GB27511@aragorn>
	<20060811173253.GA24894@aragorn>
Message-ID: <44DCC066.5030601@lanl.gov>

did you test your patch with abuild?

ron



From uwe at hermann-uwe.de  Fri Aug 11 20:09:31 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 11 Aug 2006 20:09:31 +0200
Subject: [LinuxBIOS] GA-6BXC - cont'd
Message-ID: <20060811180931.GA27444@aragorn>

Hi,

here's the output I get when running LinuxBIOS ony my GA-6BXC board,
using the fixed IT8671F code from svn, and an almost unmodified bitworks/ims
code.

I have 3 RAM slots (all used); does the output look good? Where should I
continue now? One thing I'll have to figure out is to build a payload
which prints some stuff to the serial port, so I know that the payload
is reached.

The monitor stays black, which code do I need to touch to get VGA
output?


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: minicom.cap
Type: application/cap
Size: 2763 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060811/221c1f1e/attachment.bin>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060811/221c1f1e/attachment.sig>

From smithbone at gmail.com  Fri Aug 11 20:32:45 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 11 Aug 2006 13:32:45 -0500
Subject: [LinuxBIOS] GA-6BXC - cont'd
In-Reply-To: <20060811180931.GA27444@aragorn>
References: <20060811180931.GA27444@aragorn>
Message-ID: <8a0c36780608111132u53f868een8beea6604aa35ee7@mail.gmail.com>

> I have 3 RAM slots (all used); does the output look good?

Yes thats looks ok.

> Where should I
> continue now? One thing I'll have to figure out is to build a payload
> which prints some stuff to the serial port, so I know that the payload
> is reached.

Um.... You need to go re-read all the thread postings on the i44bx and
V2.  Its not even close to running a payload.

Thats it.  Thats all the code base does right now is dump out the RAM
spd.  Thats the tip  of the iceberg.

Next we have to actually make the RAM work.
Then we load and jump to linux bios.
Then we discover and config all the necessary devices on the pci bus
Then we can try to load a payload.

The next step is to copy the RAM init code from the Intel e7501
nortbridge (raminit.c) over whats in the i440bx directory.  Then start
comparing that code to what V1 does in 440bx/raminit.inc and fix it up
so it works.

The e7501 is a DDR controller but a lot of the terminology is the same
as the SDRAM controller in the 440bx and the structure of the file is
sane and very well commented.
 It also has some stuff in there about ECC ram which we would
eventually like to support.

-- 
Richard A. Smith



From stepan at coresystems.de  Fri Aug 11 22:56:14 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 11 Aug 2006 22:56:14 +0200
Subject: [LinuxBIOS] LinuxBIOS Symposium '06 Europe
Message-ID: <20060811205614.GA3316@coresystems.de>

Dear LinuxBIOS community,

join the firmware revolution! This year's LinuxBIOS symposium will 
take place on October 1-3 in Hamburg, Germany. We cordially invite 
you to participate.

Expect to meet interesting people from all over the world, 
thrilling topics and exciting talks and discussion about 
LinuxBIOS. 

Among the topics you will find:

 * Breaking news since the LinuxBIOS summit 2005

 * The future: LinuxBIOS v3

 * Development Guidelines and Quality Assurance

 * LinuxBIOS feat. MIT's One Laptop Per Child

If you are interested in additional topics or want to talk on the
symposium, please send us an email to symposium at coresystems.de.

Registration is possible until September 10th using the registration
form at http://linuxbios.eu/. The website also provides details on the 
event. We are looking forward to meeting all of you.

Our venue is Hamburg, an intriguing green metropolis in Germany's North
where history and modernity, nature and culture meet back-to-back.
The famous Hamburg harbor, numerous parks, nifty arcades, manifold
restaurants and a great nightlife --  Take a chance to explore this 
very nice city alongside the symposium!

Hamburg has an international airport and is also easily accessible via
train. 

Find more information about the city at http://www.hamburg.de/ and 
http://en.wikipedia.org/wiki/Hamburg

The symposium will (presumably) take place in the Speicherstadt, an
ancient brick-built warehouse complex. The Speicherstadt is the
historical center of the port of Hamburg. Still today the smell of
roasted coffee and exotic spices lies in the air, experience
unforgettable events in an authentic hanseatic setting.
 
You can see pictures of the Speicherstadt 
here: 

 * http://linuxbios.eu/speicherstadt.jpg 
 * http://commons.wikimedia.org/wiki/Category:Speicherstadt 

Vendors on this list, if you have something you'd like to talk about,
please get back to me.
 
Go register today!

 Thanks,

 Stefan Reinauer
 coresystems GmbH

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Fri Aug 11 23:31:15 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 11 Aug 2006 23:31:15 +0200
Subject: [LinuxBIOS] Success.
In-Reply-To: <44DCC066.5030601@lanl.gov>
References: <20060731235718.GC7869@aragorn>
	<20060801120221.GA17269@coresystems.de>
	<20060803220502.GA18987@aragorn>
	<20060803224345.GC5055@coresystems.de>
	<20060804014548.GA30639@aragorn> <20060804204410.GB17104@aragorn>
	<8a0c36780608041443u364172aaq3244e53126863c2d@mail.gmail.com>
	<20060806195215.GB27511@aragorn>
	<20060811173253.GA24894@aragorn> <44DCC066.5030601@lanl.gov>
Message-ID: <20060811213114.GA1526@aragorn>

Hi,

On Fri, Aug 11, 2006 at 11:37:42AM -0600, Ronald G Minnich wrote:
> did you test your patch with abuild?

Yes, it works (mostly). And it really should, grep reports that
the defines are only #defined, but never used.

I get a few

  Processing mainboard/embeddedplanet/ep405pc (ppc: skipped, we're i386)

and similar lines, but that's normal, I guess.

Also, artecgroup/dbe61 fails (see below), but that's
always the case, judging from the recent svn commit messages
("Compilation of artecgroup:dbe61 is still broken.").

-----------------
Processing mainboard/artecgroup/dbe61 (i386: ok)
  Creating config file... ok
  Creating builddir...ok
  Compiling image ..FAILED after 0s! Log excerpt:
macro MSR_CPU already defined

make[1]: *** [auto.inc] Error 1
make[1]: Leaving directory `/home/uh1763/data/code/linuxbios/linuxbios-0.0+svn20060724/util/abuild/linuxbios-builds/artecgroup_dbe61/normal'
make: *** [normal/linuxbios.rom] Error 1
-----------------
Processing mainboard/tyan/s2885 (i386: ok)
  Creating config file... ok
  Creating builddir...ok
  Compiling image ..FAILED after 0s! Log excerpt:
make: *** No targets specified and no makefile found.  Stop.
-----------------

The second (tyan/s2885) I'm not sure about. Manually building it does not
work, but only because of payload path issues:

make[1]: *** No rule to make target `../../../../payloads/tg3--filo_hda2_vga.zelf', needed by `payload'.  Stop.

Other than that it works fine.

I had to 'ln -s /usr/bin/iasl /usr/sbin/iasl', as that's in /usr/bin on Debian.
Maybe there should be a small wrapper script which checks where iasl resides
and then calls it?


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060811/a9d2d1dd/attachment.sig>

From svn at openbios.org  Sat Aug 12 01:48:14 2006
From: svn at openbios.org (svn at openbios.org)
Date: Sat, 12 Aug 2006 01:48:14 +0200
Subject: [LinuxBIOS] r2375 - in trunk/LinuxBIOSv2/src/superio: NSC/pc8374
	NSC/pc87351 NSC/pc87360 NSC/pc87366 NSC/pc87417 NSC/pc87427
	NSC/pc97307 NSC/pc97317 smsc/lpc47b272 smsc/lpc47b397
	smsc/lpc47n217 winbond/w83627hf winbond/w83627thf winbond/w83977tf
Message-ID: <E1GBgje-0003PE-W0@khepri.openbios.org>

Author: stepan
Date: 2006-08-12 01:48:14 +0200 (Sat, 12 Aug 2006)
New Revision: 2375

Modified:
   trunk/LinuxBIOSv2/src/superio/NSC/pc8374/chip.h
   trunk/LinuxBIOSv2/src/superio/NSC/pc87351/chip.h
   trunk/LinuxBIOSv2/src/superio/NSC/pc87360/chip.h
   trunk/LinuxBIOSv2/src/superio/NSC/pc87366/chip.h
   trunk/LinuxBIOSv2/src/superio/NSC/pc87417/chip.h
   trunk/LinuxBIOSv2/src/superio/NSC/pc87427/chip.h
   trunk/LinuxBIOSv2/src/superio/NSC/pc97307/chip.h
   trunk/LinuxBIOSv2/src/superio/NSC/pc97317/chip.h
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/chip.h
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47b397/chip.h
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/chip.h
   trunk/LinuxBIOSv2/src/superio/winbond/w83627hf/chip.h
   trunk/LinuxBIOSv2/src/superio/winbond/w83627thf/chip.h
   trunk/LinuxBIOSv2/src/superio/winbond/w83977tf/chip.h
Log:
cleanup patch from Uwe Hermann.


Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc8374/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc8374/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc8374/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_NSC_pc8374_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc87351/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc87351/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc87351/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_NSC_pc87351_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc87360/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc87360/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc87360/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_NSC_pc87360_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc87366/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc87366/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc87366/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_NSC_pc87366_ops;
 
 #include <pc80/keyboard.h>

Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc87417/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc87417/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc87417/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_NSC_pc87417_ops;
 
 #include <pc80/keyboard.h>

Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc87427/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc87427/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc87427/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_NSC_pc87427_ops;
 
 #include <pc80/keyboard.h>

Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc97307/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc97307/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc97307/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -7,12 +7,6 @@
 #ifndef PNP_DATA_REG
 #define PNP_DATA_REG    0x15D
 #endif
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
 
 extern struct chip_operations superio_NSC_pc97307_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/NSC/pc97317/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/NSC/pc97317/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/NSC/pc97317/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -7,12 +7,6 @@
 #ifndef PNP_DATA_REG
 #define PNP_DATA_REG    0x15D
 #endif
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
 
 extern struct chip_operations superio_NSC_pc97317_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_smsc_lpc47b272_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47b397/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47b397/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47b397/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_smsc_lpc47b397_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 struct chip_operations;
 extern struct chip_operations superio_smsc_lpc47n217_ops;
 

Modified: trunk/LinuxBIOSv2/src/superio/winbond/w83627hf/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627hf/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627hf/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_winbond_w83627hf_ops;
 
 #include <pc80/keyboard.h>

Modified: trunk/LinuxBIOSv2/src/superio/winbond/w83627thf/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627thf/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627thf/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_winbond_w83627thf_ops;
 
 #include <pc80/keyboard.h>

Modified: trunk/LinuxBIOSv2/src/superio/winbond/w83977tf/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83977tf/chip.h	2006-08-11 08:15:19 UTC (rev 2374)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83977tf/chip.h	2006-08-11 23:48:14 UTC (rev 2375)
@@ -1,10 +1,3 @@
-#ifndef SIO_COM1
-#define SIO_COM1_BASE   0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE   0x2F8
-#endif
-
 extern struct chip_operations superio_winbond_w83977tf_ops;
 
 #include <pc80/keyboard.h>




From info at coresystems.de  Sat Aug 12 02:25:50 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Sat, 12 Aug 2006 02:25:50 +0200
Subject: [LinuxBIOS] LinuxBIOS r2375 build changes
Message-ID: <E1GBhK2-0004PA-ER@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2375 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
cleanup patch from Uwe Hermann.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From uwe at hermann-uwe.de  Sat Aug 12 23:08:47 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 12 Aug 2006 23:08:47 +0200
Subject: [LinuxBIOS] LinuxBIOS Symposium '06 Europe
In-Reply-To: <20060811205614.GA3316@coresystems.de>
References: <20060811205614.GA3316@coresystems.de>
Message-ID: <20060812210847.GA14884@aragorn>

Hi,

On Fri, Aug 11, 2006 at 10:56:14PM +0200, Stefan Reinauer wrote:
> join the firmware revolution! This year's LinuxBIOS symposium will 
> take place on October 1-3 in Hamburg, Germany. We cordially invite 
> you to participate.

As I probably won't be able to attend - are there plans to make
available video or audio recordings of the talks and/or PDF slides,
papers, and other materials?

That would be great...


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060812/b5ce135a/attachment.sig>

From uwe at hermann-uwe.de  Sat Aug 12 23:10:32 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 12 Aug 2006 23:10:32 +0200
Subject: [LinuxBIOS] PATCH: minor GPL fixes.
Message-ID: <20060812211032.GB14884@aragorn>

Hi,

the attached patch brings the COPYING file up-to-date with the
gpl.txt file distributed from http://www.gnu.org/licenses/gpl.txt.


HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: COPYING
===================================================================
--- COPYING	(Revision 2375)
+++ COPYING	(Arbeitskopie)
@@ -1,9 +1,8 @@
-
 		    GNU GENERAL PUBLIC LICENSE
 		       Version 2, June 1991
 
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-     51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
@@ -16,7 +15,7 @@
 General Public License applies to most of the Free Software
 Foundation's software and to any other program whose authors commit to
 using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
+the GNU Lesser General Public License instead.)  You can apply it to
 your programs, too.
 
   When we speak of free software, we are referring to freedom, not
@@ -56,7 +55,7 @@
 
   The precise terms and conditions for copying, distribution and
 modification follow.
-
+
 		    GNU GENERAL PUBLIC LICENSE
    TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
 
@@ -111,7 +110,7 @@
     License.  (Exception: if the Program itself is interactive but
     does not normally print such an announcement, your work based on
     the Program is not required to print an announcement.)
-
+
 These requirements apply to the modified work as a whole.  If
 identifiable sections of that work are not derived from the Program,
 and can be reasonably considered independent and separate works in
@@ -169,7 +168,7 @@
 access to copy the source code from the same place counts as
 distribution of the source code, even though third parties are not
 compelled to copy the source along with the object code.
-
+
   4. You may not copy, modify, sublicense, or distribute the Program
 except as expressly provided under this License.  Any attempt
 otherwise to copy, modify, sublicense or distribute the Program is
@@ -226,7 +225,7 @@
 
 This section is intended to make thoroughly clear what is believed to
 be a consequence of the rest of this License.
-
+
   8. If the distribution and/or use of the Program is restricted in
 certain countries either by patents or by copyrighted interfaces, the
 original copyright holder who places the Program under this License
@@ -279,9 +278,9 @@
 POSSIBILITY OF SUCH DAMAGES.
 
 		     END OF TERMS AND CONDITIONS
-
-	Appendix: How to Apply These Terms to Your New Programs
 
+	    How to Apply These Terms to Your New Programs
+
   If you develop a new program, and you want it to be of the greatest
 possible use to the public, the best way to achieve this is to make it
 free software which everyone can redistribute and change under these terms.
@@ -292,7 +291,7 @@
 the "copyright" line and a pointer to where the full notice is found.
 
     <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) 19yy  <name of author>
+    Copyright (C) <year>  <name of author>
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -304,16 +303,16 @@
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU General Public License for more details.
 
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 Also add information on how to contact you by electronic and paper mail.
 
 If the program is interactive, make it output a short notice like this
 when it starts in an interactive mode:
 
-    Gnomovision version 69, Copyright (C) 19yy name of author
+    Gnomovision version 69, Copyright (C) year name of author
     Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
     This is free software, and you are welcome to redistribute it
     under certain conditions; type `show c' for details.
@@ -336,5 +335,5 @@
 This General Public License does not permit incorporating your program into
 proprietary programs.  If your program is a subroutine library, you may
 consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Library General
+library.  If this is what you want to do, use the GNU Lesser General
 Public License instead of this License.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060812/dd73a824/attachment.sig>

From uwe at hermann-uwe.de  Sat Aug 12 23:26:06 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 12 Aug 2006 23:26:06 +0200
Subject: [LinuxBIOS] GA-6BXC - cont'd
In-Reply-To: <8a0c36780608111132u53f868een8beea6604aa35ee7@mail.gmail.com>
References: <20060811180931.GA27444@aragorn>
	<8a0c36780608111132u53f868een8beea6604aa35ee7@mail.gmail.com>
Message-ID: <20060812212605.GC14884@aragorn>

Hi,

On Fri, Aug 11, 2006 at 01:32:45PM -0500, Richard Smith wrote:
> Um.... You need to go re-read all the thread postings on the i44bx and
> V2.  Its not even close to running a payload.
> 
> Thats it.  Thats all the code base does right now is dump out the RAM
> spd.  Thats the tip  of the iceberg.
> 
> Next we have to actually make the RAM work.
> Then we load and jump to linux bios.
> Then we discover and config all the necessary devices on the pci bus
> Then we can try to load a payload.
> 
> The next step is to copy the RAM init code from the Intel e7501
> nortbridge (raminit.c) over whats in the i440bx directory.  Then start
> comparing that code to what V1 does in 440bx/raminit.inc and fix it up
> so it works.
> 
> The e7501 is a DDR controller but a lot of the terminology is the same
> as the SDRAM controller in the 440bx and the structure of the file is
> sane and very well commented.
>  It also has some stuff in there about ECC ram which we would
> eventually like to support.

OK, sounds like a lot of work... As I'm not an expert with all this
low-level stuff it'll take a while until I read and understand all the
code and datasheets...

In the mean time, here's a patch which forks the bitworks/ims code and
adds a gigabyte/ga-6bxc target with some minor changes...


Cheers, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/mainboard/gigabyte/ga-6bxc/Config.lb
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/Config.lb	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/Config.lb	(Revision 0)
@@ -0,0 +1,136 @@
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E 
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc 
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files 
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i440bx
+   device pci_domain 0 on 
+   end
+
+   chip cpu/intel/socket_PGA370
+   end
+
+end
+
Index: src/mainboard/gigabyte/ga-6bxc/reset.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/reset.c	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/reset.c	(Revision 0)
@@ -0,0 +1,43 @@
+#if 0
+//#include "arch/romcc_io.h"
+#include <arch/io.h>
+
+typedef unsigned device_t;
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN)  & 0x7) << 8))
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+        unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+}
+#endif
Index: src/mainboard/gigabyte/ga-6bxc/irq_tables.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/irq_tables.c	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/irq_tables.c	(Revision 0)
@@ -0,0 +1,32 @@
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE, /* u32 signature */
+	PIRQ_VERSION,   /* u16 version   */
+	32+16*5,        /* there can be total 5 devices on the bus */
+	0,              /* Where the interrupt router lies (bus) */
+	0x88,           /* Where the interrupt router lies (dev) */
+	0x1c20,         /* IRQs devoted exclusively to PCI usage */
+	0x1106,         /* Vendor */
+	0x8231,         /* Device */
+	0,              /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x5e,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* 8231 ethernet */
+		{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
+		/* 8231 internal */
+		{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
+		/* PCI slot */
+		{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
+		{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
+		{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
+	}
+};
Index: src/mainboard/gigabyte/ga-6bxc/Options.lb
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/Options.lb	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/Options.lb	(Revision 0)
@@ -0,0 +1,156 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_STREAM
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE  = 512*1024
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## no MP table
+##
+default HAVE_MP_TABLE=0
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=0
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=0
+default IRQ_SLOT_COUNT=4
+#object irq_tables.o
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=0
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+default FALLBACK_SIZE = 131072
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_STREAM     = 1
+
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=9
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=9
+
+default CONFIG_UDELAY_TSC=1
+
+end
+
Index: src/mainboard/gigabyte/ga-6bxc/debug.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/debug.c	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/debug.c	(Revision 0)
@@ -0,0 +1,66 @@
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
+	}
+}
+
+static void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
+	
+	for(i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
+	}
+}
Index: src/mainboard/gigabyte/ga-6bxc/failover.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/failover.c	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/failover.c	(Revision 0)
@@ -0,0 +1,32 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+
+static unsigned long main(unsigned long bist)
+{
+	/* This is the primary cpu how should I boot? */
+	if (do_normal_boot()) {
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
+	}
+ normal_image:
+	asm volatile ("jmp __normal_image" 
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm volatile ("jmp __cpu_reset"
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+	return bist;
+}
Index: src/mainboard/gigabyte/ga-6bxc/auto.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/auto.c	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/auto.c	(Revision 0)
@@ -0,0 +1,162 @@
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8671F_SP1)
+
+/*
+ */
+void udelay(int usecs) 
+{
+	int i;
+	for(i = 0; i < usecs; i++)
+		outb(i&0xff, 0x80);
+}
+
+#include "debug.c"
+#include "lib/delay.c"
+
+
+static void memreset_setup(void)
+{
+}
+
+/*
+  static void memreset(int controllers, const struct mem_controller *ctrl)
+  {
+  }
+*/
+
+
+static void enable_mainboard_devices(void) 
+{
+	device_t dev;
+	/* dev 0 for southbridge */
+  
+	dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
+  
+	if (dev == PCI_DEV_INVALID) {
+		die("Southbridge not found!!!\n");
+	}
+	pci_write_config8(dev, 0x50, 7);
+	pci_write_config8(dev, 0x51, 0xff);
+#if 0
+	// This early setup switches IDE into compatibility mode before PCI gets 
+	// // a chance to assign I/Os
+	//         movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
+	//         //      movb    $0x09, %dl
+	//                 movb    $0x00, %dl
+	//                         PCI_WRITE_CONFIG_BYTE
+	//
+#endif
+	/* we do this here as in V2, we can not yet do raw operations 
+	 * to pci!
+	 */
+        dev += 0x100; /* ICKY */
+
+	pci_write_config8(dev, 0x42, 0);
+}
+
+static void enable_shadow_ram(void) 
+{
+	device_t dev = 0; /* no need to look up 0:0.0 */
+	unsigned char shadowreg;
+	/* dev 0 for southbridge */
+	shadowreg = pci_read_config8(dev, 0x63);
+	/* 0xf0000-0xfffff */
+	shadowreg |= 0x30;
+	pci_write_config8(dev, 0x63, shadowreg);
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	int c;
+	c = smbus_read_byte(device, address);
+	return c;
+}
+
+
+#include "northbridge/intel/i440bx/raminit.c"
+#include "northbridge/intel/i440bx/debug.c"
+#include "sdram/generic_sdram.c"
+
+static void main(unsigned long bist)
+{
+	static const struct mem_controller cpu[] = {
+		{
+		 .channel0 = {
+			 (0xa << 3) | 0,
+			 (0xa << 3) | 1,
+			 (0xa << 3) | 2, 
+			 (0xa << 3) | 3,
+		 	},
+		 }
+	};
+	unsigned long x;
+	int result;
+	
+	if (bist == 0) {
+		early_mtrr_init();
+	}
+	it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+	
+	enable_smbus();
+/*
+	result = spd_read_byte(cpu[0].channel0[0],0x03);
+	print_debug("Result: ");
+	print_debug_hex16(result);
+	print_debug("\r\n");
+*/
+	dump_spd_registers(&cpu[0]);
+
+#if 0
+	enable_shadow_ram();
+	/*
+	  memreset_setup();
+	  this is way more generic than we need.
+	  sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+	*/
+	sdram_set_registers((const struct mem_controller *) 0);
+	sdram_set_spd_registers((const struct mem_controller *) 0);
+	sdram_enable(0, (const struct mem_controller *) 0);
+#endif
+	
+	/* Check all of memory */
+#if 0
+	ram_check(0x00000000, msr.lo);
+#endif
+#if 0
+	static const struct {
+		unsigned long lo, hi;
+	} check_addrs[] = {
+		/* Check 16MB of memory @ 0*/
+		{ 0x00000000, 0x01000000 },
+#if TOTAL_CPUS > 1
+		/* Check 16MB of memory @ 2GB */
+		{ 0x80000000, 0x81000000 },
+#endif
+	};
+	int i;
+	for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+		ram_check(check_addrs[i].lo, check_addrs[i].hi);
+	}
+#endif
+}
Index: src/mainboard/gigabyte/ga-6bxc/chip.h
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/chip.h	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/chip.h	(Revision 0)
@@ -0,0 +1,5 @@
+extern struct chip_operations mainboard_gigabyte_ga_6bxc_ops;
+
+struct mainboard_gigabyte_ga_6bxc_config {
+	int nothing;
+};
Index: src/mainboard/gigabyte/ga-6bxc/cmos.layout
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/cmos.layout	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/cmos.layout	(Revision 0)
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
Index: src/mainboard/gigabyte/ga-6bxc/mainboard.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/mainboard.c	(Revision 0)
+++ src/mainboard/gigabyte/ga-6bxc/mainboard.c	(Revision 0)
@@ -0,0 +1,12 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "chip.h"
+
+struct chip_operations mainboard_gigabyte_ga_6bxc_ops = {
+	CHIP_NAME("Gigabyte GA-6BXC mainboard ")
+};
+
Index: targets/gigabyte/ga-6bxc/Config.lb
===================================================================
--- targets/gigabyte/ga-6bxc/Config.lb	(Revision 0)
+++ targets/gigabyte/ga-6bxc/Config.lb	(Revision 0)
@@ -0,0 +1,29 @@
+# Config file for the Gigabyte GA-6BXC board
+# This will make a target directory of ./ga-6bxc
+
+target ga-6bxc
+mainboard gigabyte/ga-6bxc
+
+option ROM_SIZE=262144
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE=0
+	option ROM_IMAGE_SIZE=0x10000
+	option LINUXBIOS_EXTRA_VERSION=".0Normal"
+#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+#	payload ../../../../tg3--ide_disk.zelf	
+#	payload ../../../../../lnxieepro100.ebi
+	payload /etc/hosts
+end
+
+romimage "fallback" 
+	option USE_FALLBACK_IMAGE=1
+	option ROM_IMAGE_SIZE=0x10000
+	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+#	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+#	payload ../../../../tg3--ide_disk.zelf	
+#	payload ../../../../../lnxieepro100.ebia
+	payload /etc/hosts
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060812/1343319e/attachment.sig>

From svn at openbios.org  Sun Aug 13 00:03:36 2006
From: svn at openbios.org (svn at openbios.org)
Date: Sun, 13 Aug 2006 00:03:36 +0200
Subject: [LinuxBIOS] r2376 - trunk/LinuxBIOSv2
Message-ID: <E1GC1Zw-00005q-Rn@khepri.openbios.org>

Author: stepan
Date: 2006-08-13 00:03:36 +0200 (Sun, 13 Aug 2006)
New Revision: 2376

Modified:
   trunk/LinuxBIOSv2/COPYING
Log:
update license template.


Modified: trunk/LinuxBIOSv2/COPYING
===================================================================
--- trunk/LinuxBIOSv2/COPYING	2006-08-11 23:48:14 UTC (rev 2375)
+++ trunk/LinuxBIOSv2/COPYING	2006-08-12 22:03:36 UTC (rev 2376)
@@ -1,9 +1,8 @@
-
 		    GNU GENERAL PUBLIC LICENSE
 		       Version 2, June 1991
 
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-     51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
@@ -16,7 +15,7 @@
 General Public License applies to most of the Free Software
 Foundation's software and to any other program whose authors commit to
 using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
+the GNU Lesser General Public License instead.)  You can apply it to
 your programs, too.
 
   When we speak of free software, we are referring to freedom, not
@@ -56,7 +55,7 @@
 
   The precise terms and conditions for copying, distribution and
 modification follow.
-

+
 		    GNU GENERAL PUBLIC LICENSE
    TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
 
@@ -111,7 +110,7 @@
     License.  (Exception: if the Program itself is interactive but
     does not normally print such an announcement, your work based on
     the Program is not required to print an announcement.)
-

+
 These requirements apply to the modified work as a whole.  If
 identifiable sections of that work are not derived from the Program,
 and can be reasonably considered independent and separate works in
@@ -169,7 +168,7 @@
 access to copy the source code from the same place counts as
 distribution of the source code, even though third parties are not
 compelled to copy the source along with the object code.
-

+
   4. You may not copy, modify, sublicense, or distribute the Program
 except as expressly provided under this License.  Any attempt
 otherwise to copy, modify, sublicense or distribute the Program is
@@ -226,7 +225,7 @@
 
 This section is intended to make thoroughly clear what is believed to
 be a consequence of the rest of this License.
-

+
   8. If the distribution and/or use of the Program is restricted in
 certain countries either by patents or by copyrighted interfaces, the
 original copyright holder who places the Program under this License
@@ -279,9 +278,9 @@
 POSSIBILITY OF SUCH DAMAGES.
 
 		     END OF TERMS AND CONDITIONS
-

-	Appendix: How to Apply These Terms to Your New Programs
 
+	    How to Apply These Terms to Your New Programs
+
   If you develop a new program, and you want it to be of the greatest
 possible use to the public, the best way to achieve this is to make it
 free software which everyone can redistribute and change under these terms.
@@ -292,7 +291,7 @@
 the "copyright" line and a pointer to where the full notice is found.
 
     <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) 19yy  <name of author>
+    Copyright (C) <year>  <name of author>
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -304,16 +303,16 @@
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU General Public License for more details.
 
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 Also add information on how to contact you by electronic and paper mail.
 
 If the program is interactive, make it output a short notice like this
 when it starts in an interactive mode:
 
-    Gnomovision version 69, Copyright (C) 19yy name of author
+    Gnomovision version 69, Copyright (C) year name of author
     Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
     This is free software, and you are welcome to redistribute it
     under certain conditions; type `show c' for details.
@@ -336,5 +335,5 @@
 This General Public License does not permit incorporating your program into
 proprietary programs.  If your program is a subroutine library, you may
 consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Library General
+library.  If this is what you want to do, use the GNU Lesser General
 Public License instead of this License.




From info at coresystems.de  Sun Aug 13 00:41:46 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 13 Aug 2006 00:41:46 +0200
Subject: [LinuxBIOS] LinuxBIOS r2376 build changes
Message-ID: <E1GC2As-0001iC-CS@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2376 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
update license template.

Build Log:
 Compilation of artecgroup:dbe61 is still broken.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From uwe at hermann-uwe.de  Mon Aug 14 18:14:45 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 14 Aug 2006 18:14:45 +0200
Subject: [LinuxBIOS] smsc dme1737 data book -- anybody got it?
In-Reply-To: <8a0c36780608110647m1e730311h92c66c49c4b08b12@mail.gmail.com>
References: <44DB3D5F.4010009@lanl.gov> <20060811132856.GC695@aragorn>
	<8a0c36780608110641q51e84892r42c12789ad01ef86@mail.gmail.com>
	<8a0c36780608110647m1e730311h92c66c49c4b08b12@mail.gmail.com>
Message-ID: <20060814161445.GB24425@aragorn>

Hi,

ah, nice, I received the datasheet from ITE directly today...


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060814/b7103b2d/attachment.sig>

From svn at openbios.org  Tue Aug 15 15:52:51 2006
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 15 Aug 2006 15:52:51 +0200
Subject: [LinuxBIOS] r2377 - trunk/LinuxBIOSv2/src/southbridge/amd/cs5536
Message-ID: <E1GCzLf-0000iB-K5@khepri.openbios.org>

Author: stepan
Date: 2006-08-15 15:52:51 +0200 (Tue, 15 Aug 2006)
New Revision: 2377

Modified:
   trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c
Log:
this file is already included by auto.c on all targets.


Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c	2006-08-12 22:03:36 UTC (rev 2376)
+++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c	2006-08-15 13:52:51 UTC (rev 2377)
@@ -1,4 +1,3 @@
-#include <cpu/amd/gx2def.h>
 
 /*
  *




From info at coresystems.de  Tue Aug 15 16:29:58 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Tue, 15 Aug 2006 16:29:58 +0200
Subject: [LinuxBIOS] LinuxBIOS r2377 build changes
Message-ID: <E1GCzva-0001yd-KU@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2377 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
this file is already included by auto.c on all targets.

Build Log:
 Compilation of artecgroup:dbe61 has been fixed.

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From jsturges at speakeasy.net  Tue Aug 15 22:25:20 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Tue, 15 Aug 2006 16:25:20 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
Message-ID: <44E22DB0.2040905@speakeasy.net>

So I'm back to working on getting LB on my Geode-based MaxTerm 230 thin 
client again.  I've built a test image from the Eaglelion 5bcm target 
that boots this machine.  However, IRQ mapping is not working.  I have 
no doubt that is because the MaxTerm differs from the 5bcm.  :-)

I'm not entirely sure how to proceed.  I know I can create PIRQ tables, 
but in some posts, I've seen mention that this is outdated and ACPI 
should be used.  Even if I were to build a PIRQ table, the usual method 
of booting with the system's default BIOS is out of the question.  The 
MaxTerm only ran WinCE 3.0, and has a WinCE BIOS instead of a full PC 
BIOS.  Unless someone knows of a WinCE system inspection tool that might 
reveal the IRQ assignments.

Advice appreciated....

thanks,
Jonathan




From rminnich at lanl.gov  Tue Aug 15 22:27:27 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Tue, 15 Aug 2006 14:27:27 -0600
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E22DB0.2040905@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net>
Message-ID: <44E22E2F.6070709@lanl.gov>

put the bios flash psrt in another machine that takes the same part, and 
run the getpir program. This should work.

ron



From smithbone at gmail.com  Tue Aug 15 22:49:41 2006
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 15 Aug 2006 15:49:41 -0500
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E22E2F.6070709@lanl.gov>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>
Message-ID: <8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>

On 8/15/06, Ronald G Minnich <rminnich at lanl.gov> wrote:
> put the bios flash psrt in another machine that takes the same part, and
> run the getpir program. This should work.

Unless its compressed.

-- 
Richard A. Smith



From rminnich at lanl.gov  Tue Aug 15 22:51:26 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Tue, 15 Aug 2006 14:51:26 -0600
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>
Message-ID: <44E233CE.1010802@lanl.gov>

Richard Smith wrote:
> On 8/15/06, Ronald G Minnich <rminnich at lanl.gov> wrote:
> 
>> put the bios flash psrt in another machine that takes the same part, and
>> run the getpir program. This should work.
> 
> 
> Unless its compressed.
> 

yeah, but, it's worth the chance :-)

ron



From jsturges at speakeasy.net  Tue Aug 15 22:56:07 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Tue, 15 Aug 2006 16:56:07 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>
Message-ID: <44E234E7.4040404@speakeasy.net>

Richard Smith wrote:

> On 8/15/06, Ronald G Minnich <rminnich at lanl.gov> wrote:
>
>> put the bios flash psrt in another machine that takes the same part, and
>> run the getpir program. This should work.
>
>
> Unless its compressed.
>
You mean, run getpir against the WinCE BIOS image?  Please clarify what 
you're saying.
I still can't use the WinCE BIOS to boot other OSes, so unless I'm 
misunderstanding you, I don't think that'll work.

thanks,
Jonathan



From smithbone at gmail.com  Tue Aug 15 23:03:47 2006
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 15 Aug 2006 16:03:47 -0500
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E234E7.4040404@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>
	<44E234E7.4040404@speakeasy.net>
Message-ID: <8a0c36780608151403o48b3d6f1o4e7f23b264f16976@mail.gmail.com>

> >
> > Unless its compressed.
> >
> You mean, run getpir against the WinCE BIOS image?  Please clarify what
> you're saying.
> I still can't use the WinCE BIOS to boot other OSes, so unless I'm
> misunderstanding you, I don't think that'll work.

Exactly.  The $PIR was just a table.  Ron's guessing that if they used
PIR then its probably just the table hanging out in the ROM in which
getpir will find it.

you can also hd (or other hexeditor) the image file and look for
occurances of $PIR.  There may be more than one so you have to go
further to verify its a PIR table.

-- 
Richard A. Smith



From jsturges at speakeasy.net  Tue Aug 15 23:07:24 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Tue, 15 Aug 2006 17:07:24 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <8a0c36780608151403o48b3d6f1o4e7f23b264f16976@mail.gmail.com>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>	
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>	
	<44E234E7.4040404@speakeasy.net>
	<8a0c36780608151403o48b3d6f1o4e7f23b264f16976@mail.gmail.com>
Message-ID: <44E2378C.5020904@speakeasy.net>

Richard Smith wrote:

>> >
>> > Unless its compressed.
>> >
>> You mean, run getpir against the WinCE BIOS image?  Please clarify what
>> you're saying.
>> I still can't use the WinCE BIOS to boot other OSes, so unless I'm
>> misunderstanding you, I don't think that'll work.
>
>
> Exactly.  The $PIR was just a table.  Ron's guessing that if they used
> PIR then its probably just the table hanging out in the ROM in which
> getpir will find it.
>
> you can also hd (or other hexeditor) the image file and look for
> occurances of $PIR.  There may be more than one so you have to go
> further to verify its a PIR table.
>

Oh, sweet!  I hope that is indeed the case.  I'll peek at the ROM image 
shortly.
Can getpir read from a file, such as a binary image of the WinCE BIOS?

thanks again,
Jonathan



From jsturges at speakeasy.net  Tue Aug 15 23:54:43 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Tue, 15 Aug 2006 17:54:43 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <8a0c36780608151403o48b3d6f1o4e7f23b264f16976@mail.gmail.com>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>	
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>	
	<44E234E7.4040404@speakeasy.net>
	<8a0c36780608151403o48b3d6f1o4e7f23b264f16976@mail.gmail.com>
Message-ID: <44E242A3.5050005@speakeasy.net>

Richard Smith wrote:

>> >
>> > Unless its compressed.
>> >
>> You mean, run getpir against the WinCE BIOS image?  Please clarify what
>> you're saying.
>> I still can't use the WinCE BIOS to boot other OSes, so unless I'm
>> misunderstanding you, I don't think that'll work.
>
>
> Exactly.  The $PIR was just a table.  Ron's guessing that if they used
> PIR then its probably just the table hanging out in the ROM in which
> getpir will find it.
>
> you can also hd (or other hexeditor) the image file and look for
> occurances of $PIR.  There may be more than one so you have to go
> further to verify its a PIR table.
>

No $PIR in the image.  What's my best "Plan B"?  Options that I'm aware 
of include:
1)  Find a way to enumerate IRQ assignments while booted into WinCE 3.0.
2)  Guess.  :-)  Right now, the only devices I need that are lacking IRQ 
assignments are the USB controller and the NIC.

Question:  how is the kernel getting IRQ assignments for ide0 and the 2 
serial ports?  Without an IRQ table, I have to assume it's assuming 
standard IRQs for those devices.

thanks,
Jonathan



From smithbone at gmail.com  Wed Aug 16 00:11:15 2006
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 15 Aug 2006 17:11:15 -0500
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E242A3.5050005@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>
	<44E234E7.4040404@speakeasy.net>
	<8a0c36780608151403o48b3d6f1o4e7f23b264f16976@mail.gmail.com>
	<44E242A3.5050005@speakeasy.net>
Message-ID: <8a0c36780608151511kd970904vef2d512ee4a4fb4@mail.gmail.com>

>
> No $PIR in the image.  What's my best "Plan B"?  Options that I'm aware
> of include:
> 1)  Find a way to enumerate IRQ assignments while booted into WinCE 3.0.

Can you run one of the pci enum tools that work under windows?  That
will give you _some_ info.

> 2)  Guess.  :-)  Right now, the only devices I need that are lacking IRQ
> assignments are the USB controller and the NIC.

This might not be that bad of an option.  What you really need to know
is what PCI Int is hooked up to the device.  There are only 4.

This might work:

For INT in INTA, INTB, INTC, INTD:
   Configure the NIC and set it to use IRQ 9.
   Then route INT to IRQ 9.
   Hook up a ethernet cable and see if you get Rx packets.

> Question:  how is the kernel getting IRQ assignments for ide0 and the 2
> serial ports?  Without an IRQ table, I have to assume it's assuming
> standard IRQs for those devices.

Yeah. Those have long time accepted defaults.

-- 
Richard A. Smith



From rminnich at lanl.gov  Wed Aug 16 00:25:56 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Tue, 15 Aug 2006 16:25:56 -0600
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E234E7.4040404@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>
	<44E234E7.4040404@speakeasy.net>
Message-ID: <44E249F4.5030808@lanl.gov>

Jonathan Sturges wrote:
> Richard Smith wrote:
> 
>> On 8/15/06, Ronald G Minnich <rminnich at lanl.gov> wrote:
>>
>>> put the bios flash psrt in another machine that takes the same part, and
>>> run the getpir program. This should work.
>>
>>
>>
>> Unless its compressed.
>>
> You mean, run getpir against the WinCE BIOS image?  Please clarify what 
> you're saying.
> I still can't use the WinCE BIOS to boot other OSes, so unless I'm 
> misunderstanding you, I don't think that'll work.
> 
> thanks,
> Jonathan

what kind of bios chip is it? Or, failing that, do you have a place to 
get a bios image?

ron



From rminnich at lanl.gov  Wed Aug 16 00:26:53 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Tue, 15 Aug 2006 16:26:53 -0600
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E242A3.5050005@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net> <44E22E2F.6070709@lanl.gov>	
	<8a0c36780608151349x30933259s6ef4eaa942fa5d81@mail.gmail.com>	
	<44E234E7.4040404@speakeasy.net>
	<8a0c36780608151403o48b3d6f1o4e7f23b264f16976@mail.gmail.com>
	<44E242A3.5050005@speakeasy.net>
Message-ID: <44E24A2D.3060007@lanl.gov>

Jonathan Sturges wrote:
> Richard Smith wrote:
> 
>>> >
>>> > Unless its compressed.
>>> >
>>> You mean, run getpir against the WinCE BIOS image?  Please clarify what
>>> you're saying.
>>> I still can't use the WinCE BIOS to boot other OSes, so unless I'm
>>> misunderstanding you, I don't think that'll work.
>>
>>
>>
>> Exactly.  The $PIR was just a table.  Ron's guessing that if they used
>> PIR then its probably just the table hanging out in the ROM in which
>> getpir will find it.
>>
>> you can also hd (or other hexeditor) the image file and look for
>> occurances of $PIR.  There may be more than one so you have to go
>> further to verify its a PIR table.
>>
> 
> No $PIR in the image.  What's my best "Plan B"?  Options that I'm aware 
> of include:
> 1)  Find a way to enumerate IRQ assignments while booted into WinCE 3.0.
> 2)  Guess.  :-)  Right now, the only devices I need that are lacking IRQ 
> assignments are the USB controller and the NIC.
> 

you should be able to look at irq assignments in wince.

ron



From juergen127 at kreuzholzen.de  Wed Aug 16 09:39:59 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Wed, 16 Aug 2006 09:39:59 +0200
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E22DB0.2040905@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net>
Message-ID: <200608160939.59196.juergen127@kreuzholzen.de>

Jonathan,

On Tuesday 15 August 2006 22:25, Jonathan Sturges wrote:
> So I'm back to working on getting LB on my Geode-based MaxTerm 230 thin
> client again.  I've built a test image from the Eaglelion 5bcm target
> that boots this machine.  However, IRQ mapping is not working.  I have
> no doubt that is because the MaxTerm differs from the 5bcm.  :-)

What exactly does not work (error messages and so on)? I also started with the 
Eaglelion 5bcm for my AXUS-TC320 (with WinCE-Loader, no BIOS). On my first 
tries with LinuxBIOS Linux complained about a broken IRQ map, but I played 
around with the settings and now it works.

Juergen




From jsturges at speakeasy.net  Wed Aug 16 13:58:10 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Wed, 16 Aug 2006 07:58:10 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <200608160939.59196.juergen127@kreuzholzen.de>
References: <44E22DB0.2040905@speakeasy.net>
	<200608160939.59196.juergen127@kreuzholzen.de>
Message-ID: <44E30852.4040402@speakeasy.net>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060816/1a1d75d0/attachment.html>

From juergen127 at kreuzholzen.de  Wed Aug 16 14:50:01 2006
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Wed, 16 Aug 2006 14:50:01 +0200
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E30852.4040402@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net>
	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net>
Message-ID: <200608161450.01712.juergen127@kreuzholzen.de>

Hi Jonathan,

please use plain text, no HTML....

On Wednesday 16 August 2006 13:58, Jonathan Sturges wrote:
> PCI: No IRQ known for interrupt pin A of device 00:13.0. Please try
> using pci=biosirq.
> usb-ohci.c: found OHCI device with no IRQ assigned. check BIOS
> settings!
> ...which basically means the entries for these devices in the IRQ map
> are either wrong, or missing.&nbsp; What's needed now is a way to determine
> those interrupts, and put them in the map.&nbsp; Did you have to go through
> a similar process on your board, and if so, can you detail what you
> did?

Yes, similar to my experience. I tried (no chance to read back any values due 
to WinCE-Bootloader instead of BIOS) with this irq map and it works.
Source attached.

Juergen
-------------- next part --------------
A non-text attachment was scrubbed...
Name: irq_tables.c
Type: text/x-csrc
Size: 3071 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060816/4681f413/attachment.c>

From jsturges at speakeasy.net  Wed Aug 16 14:59:26 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Wed, 16 Aug 2006 08:59:26 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <200608161450.01712.juergen127@kreuzholzen.de>
References: <44E22DB0.2040905@speakeasy.net>
	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net>
	<200608161450.01712.juergen127@kreuzholzen.de>
Message-ID: <44E316AE.1040806@speakeasy.net>


Juergen Beisert wrote:

>Hi Jonathan,
>
>please use plain text, no HTML....
>
>On Wednesday 16 August 2006 13:58, Jonathan Sturges wrote:
>  
>
>>PCI: No IRQ known for interrupt pin A of device 00:13.0. Please try
>>using pci=biosirq.
>>usb-ohci.c: found OHCI device with no IRQ assigned. check BIOS
>>settings!
>>...which basically means the entries for these devices in the IRQ map
>>are either wrong, or missing.&nbsp; What's needed now is a way to determine
>>those interrupts, and put them in the map.&nbsp; Did you have to go through
>>a similar process on your board, and if so, can you detail what you
>>did?
>>    
>>
>
>Yes, similar to my experience. I tried (no chance to read back any values due 
>to WinCE-Bootloader instead of BIOS) with this irq map and it works.
>Source attached.
>
>Juergen
>

Thanks for the irq_tables.c file; I'll compare it to what I've got and 
merge in the changes.

Sorry if that last mail came out HTML; I don't intentionally compose it 
that way, and apparently Thunderbird's autodetect got confused.

thanks,
Jonathan


>------------------------------------------------------------------------
>



From stepan at coresystems.de  Wed Aug 16 16:18:04 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 16 Aug 2006 16:18:04 +0200
Subject: [LinuxBIOS] LinuxBIOS Symposium '06 Europe
In-Reply-To: <20060812210847.GA14884@aragorn>
References: <20060811205614.GA3316@coresystems.de>
	<20060812210847.GA14884@aragorn>
Message-ID: <20060816141804.GB28102@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060812 23:08]:
> On Fri, Aug 11, 2006 at 10:56:14PM +0200, Stefan Reinauer wrote:
> > join the firmware revolution! This year's LinuxBIOS symposium will 
> > take place on October 1-3 in Hamburg, Germany. We cordially invite 
> > you to participate.
> 
> As I probably won't be able to attend - are there plans to make
> available video or audio recordings of the talks and/or PDF slides,
> papers, and other materials?

We will put all slides and papers online as PDFs. 

But do consider coming, it will be a worthwhile event!

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From rminnich at lanl.gov  Wed Aug 16 16:16:01 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Wed, 16 Aug 2006 08:16:01 -0600
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E30852.4040402@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net>	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net>
Message-ID: <44E328A1.8010208@lanl.gov>

Jonathan Sturges wrote:

> I was aware of the issues with LB failing to copy the IRQ map, due to 
> the GX1's cache not being enabled.  However, I applied the two 
> northbridge.c patches for enabling the cache, so now that much works.  
> (By the way, can someone on the development team commit those cache 
> patches?  As of revision 2360, they're not included.  I'll send links to 
> the posts if needed.)  But what I get now is that there is no IRQ 
> defined for my on-board USB and Ethernet adapters.  So 'insmod'-ing a 
> driver for either results in this message:

sorry, please resend.

ron



From svn at openbios.org  Wed Aug 16 16:22:10 2006
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 16 Aug 2006 16:22:10 +0200
Subject: [LinuxBIOS] r2378 - in trunk/LinuxBIOSv2/src/cpu/amd: model_gx2
	model_lx
Message-ID: <E1GDMHa-0007qG-Fg@khepri.openbios.org>

Author: stepan
Date: 2006-08-16 16:22:10 +0200 (Wed, 16 Aug 2006)
New Revision: 2378

Modified:
   trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c
   trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c
Log:
share decompression code.


Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c
===================================================================
--- trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c	2006-08-15 13:52:51 UTC (rev 2377)
+++ trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c	2006-08-16 14:22:10 UTC (rev 2378)
@@ -11,92 +11,8 @@
  * was done, but can't fix it yet. RGM
  */
 #warning "Fix the uncompress once linuxbios knows how to do it"
-// This GETBIT is supposed to work on little endian 
-// 32bit systems. The algorithm will definitely need
-// some fixing on other systems, but it might not be
-// a problem since the nrv2b binary behaves the same..
+#include "../lib/nrv2b.c"
 
-#ifndef ENDIAN
-#define ENDIAN   0
-#endif
-#ifndef BITSIZE
-#define BITSIZE 32
-#endif
-
-#define GETBIT_8(bb, src, ilen) \
-    (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
-
-#define GETBIT_LE16(bb, src, ilen) \
-    (bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
-#define GETBIT_LE32(bb, src, ilen) \
-    (bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
-    bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1))
-
-#if ENDIAN == 0 && BITSIZE == 8
-#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
-#endif
-#if ENDIAN == 0 && BITSIZE == 16
-#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
-#endif
-#if ENDIAN == 0 && BITSIZE == 32
-#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
-#endif
-
-static unsigned long unrv2b(uint8_t * src, uint8_t * dst)
-{
-	unsigned long ilen = 0, olen = 0, last_m_off = 1;
-	uint32_t bb = 0;
-	unsigned bc = 0;
-	const uint8_t *m_pos;
-	unsigned long file_len = *(unsigned long *) src;
-
-	printk_debug("compressed file len is supposed to be %d bytes\n", file_len);
-	// skip length
-	src += 4;
-	/* FIXME: check olen with the length stored in first 4 bytes */	
-
-	for (;;) {
-		unsigned int m_off, m_len;
-		while (GETBIT(bb, src, ilen)) {
-			dst[olen++] = src[ilen++];
-		}
-
-		m_off = 1;
-		do {
-			m_off = m_off * 2 + GETBIT(bb, src, ilen);
-		} while (!GETBIT(bb, src, ilen));
-		if (m_off == 2) {
-			m_off = last_m_off;
-		} else {
-			m_off = (m_off - 3) * 256 + src[ilen++];
-			if (m_off == 0xffffffffU)
-				break;
-			last_m_off = ++m_off;
-		}
-
-		m_len = GETBIT(bb, src, ilen);
-		m_len = m_len * 2 + GETBIT(bb, src, ilen);
-		if (m_len == 0) {
-			m_len++;
-			do {
-				m_len = m_len * 2 + GETBIT(bb, src, ilen);
-			} while (!GETBIT(bb, src, ilen));
-			m_len += 2;
-		}
-		m_len += (m_off > 0xd00);
-
-		m_pos = dst + olen - m_off;
-		dst[olen++] = *m_pos++;
-		do {
-			dst[olen++] = *m_pos++;
-		} while (--m_len > 0);
-	}
-
-	printk_debug("computed len is %d, file len is %d\n", olen, file_len);
-	return olen;
-
-}
-
 /* vsmsetup.c derived from vgabios.c. Derived from: */
 
 /*------------------------------------------------------------ -*- C -*-

Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c
===================================================================
--- trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c	2006-08-15 13:52:51 UTC (rev 2377)
+++ trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c	2006-08-16 14:22:10 UTC (rev 2378)
@@ -11,92 +11,8 @@
  * was done, but can't fix it yet. RGM
  */
 #warning "Fix the uncompress once linuxbios knows how to do it"
-// This GETBIT is supposed to work on little endian 
-// 32bit systems. The algorithm will definitely need
-// some fixing on other systems, but it might not be
-// a problem since the nrv2b binary behaves the same..
+#include "../lib/nrv2b.c"
 
-#ifndef ENDIAN
-#define ENDIAN   0
-#endif
-#ifndef BITSIZE
-#define BITSIZE 32
-#endif
-
-#define GETBIT_8(bb, src, ilen) \
-    (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
-
-#define GETBIT_LE16(bb, src, ilen) \
-    (bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
-#define GETBIT_LE32(bb, src, ilen) \
-    (bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
-    bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1))
-
-#if ENDIAN == 0 && BITSIZE == 8
-#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
-#endif
-#if ENDIAN == 0 && BITSIZE == 16
-#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
-#endif
-#if ENDIAN == 0 && BITSIZE == 32
-#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
-#endif
-
-static unsigned long unrv2b(uint8_t * src, uint8_t * dst)
-{
-	unsigned long ilen = 0, olen = 0, last_m_off = 1;
-	uint32_t bb = 0;
-	unsigned bc = 0;
-	const uint8_t *m_pos;
-	unsigned long file_len = *(unsigned long *) src;
-
-	printk_debug("compressed file len is supposed to be %d bytes\n", file_len);
-	// skip length
-	src += 4;
-	/* FIXME: check olen with the length stored in first 4 bytes */	
-
-	for (;;) {
-		unsigned int m_off, m_len;
-		while (GETBIT(bb, src, ilen)) {
-			dst[olen++] = src[ilen++];
-		}
-
-		m_off = 1;
-		do {
-			m_off = m_off * 2 + GETBIT(bb, src, ilen);
-		} while (!GETBIT(bb, src, ilen));
-		if (m_off == 2) {
-			m_off = last_m_off;
-		} else {
-			m_off = (m_off - 3) * 256 + src[ilen++];
-			if (m_off == 0xffffffffU)
-				break;
-			last_m_off = ++m_off;
-		}
-
-		m_len = GETBIT(bb, src, ilen);
-		m_len = m_len * 2 + GETBIT(bb, src, ilen);
-		if (m_len == 0) {
-			m_len++;
-			do {
-				m_len = m_len * 2 + GETBIT(bb, src, ilen);
-			} while (!GETBIT(bb, src, ilen));
-			m_len += 2;
-		}
-		m_len += (m_off > 0xd00);
-
-		m_pos = dst + olen - m_off;
-		dst[olen++] = *m_pos++;
-		do {
-			dst[olen++] = *m_pos++;
-		} while (--m_len > 0);
-	}
-
-	printk_debug("computed len is %d, file len is %d\n", olen, file_len);
-	return olen;
-
-}
-
 /* vsmsetup.c derived from vgabios.c. Derived from: */
 
 /*------------------------------------------------------------ -*- C -*-




From jsturges at speakeasy.net  Wed Aug 16 16:30:46 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Wed, 16 Aug 2006 10:30:46 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E328A1.8010208@lanl.gov>
References: <44E22DB0.2040905@speakeasy.net>	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net> <44E328A1.8010208@lanl.gov>
Message-ID: <44E32C16.8050708@speakeasy.net>



Ronald G Minnich wrote:

> Jonathan Sturges wrote:
>
>> I was aware of the issues with LB failing to copy the IRQ map, due to 
>> the GX1's cache not being enabled.  However, I applied the two 
>> northbridge.c patches for enabling the cache, so now that much 
>> works.  (By the way, can someone on the development team commit those 
>> cache patches?  As of revision 2360, they're not included.  I'll send 
>> links to the posts if needed.)  But what I get now is that there is 
>> no IRQ defined for my on-board USB and Ethernet adapters.  So 
>> 'insmod'-ing a driver for either results in this message:
>
>
> sorry, please resend.
>
> ron


The 2 patches I applied are from these posts:
http://www.linuxbios.org/pipermail/linuxbios/2006-May/014546.html
http://www.linuxbios.org/pipermail/linuxbios/2006-May/014777.html

Granted, both of these patches were offered up as "hacks," but they 
work, allowing the GX1 cache to be enabled and for the IRQ map to be 
successfully copied, so I endorse them.  :-)

thanks,
Jonathan




From svn at openbios.org  Wed Aug 16 16:38:01 2006
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 16 Aug 2006 16:38:01 +0200
Subject: [LinuxBIOS] r2379 - trunk/LinuxBIOSv2/src/northbridge/amd/gx1
Message-ID: <E1GDMWv-0002a5-4J@khepri.openbios.org>

Author: rminnich
Date: 2006-08-16 16:38:00 +0200 (Wed, 16 Aug 2006)
New Revision: 2379

Modified:
   trunk/LinuxBIOSv2/src/northbridge/amd/gx1/northbridge.c
Log:
updates to make gx1 IRQ map work. not tested;
signed-off-by: Ronald G. Minnich


Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx1/northbridge.c
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/amd/gx1/northbridge.c	2006-08-16 14:22:10 UTC (rev 2378)
+++ trunk/LinuxBIOSv2/src/northbridge/amd/gx1/northbridge.c	2006-08-16 14:38:00 UTC (rev 2379)
@@ -10,6 +10,7 @@
 #include "chip.h"
 #include "northbridge.h"
 #include <cpu/amd/gx1def.h>
+#include <cpu/x86/cache.h>
 
 #define NORTHBRIDGE_FILE "northbridge.c"
 /*
@@ -24,9 +25,18 @@
 	pci_write_config8(dev, 0x44, 0x00);
 }
 
+/**
+ * Enables memory from 0xC0000 up to 0xFFFFF.
+ * So this region is read/write and cache able
+ *
+ * FIXME: What about PCI master access into
+ *        this region?
+ **/
+
 static void enable_shadow(device_t dev)
 {
-	
+       writel(0x77777777,GX_BASE+BC_XMAP_2);
+       writel(0x77777777,GX_BASE+BC_XMAP_3);
 }
 
 static void northbridge_init(device_t dev) 
@@ -35,6 +45,8 @@
 	
 	optimize_xbus(dev);
 	enable_shadow(dev);
+	printk_spew("Calling enable_cache()\n");
+	enable_cache();
 }
 
 
@@ -180,7 +192,8 @@
 
 static void cpu_bus_init(device_t dev)
 {
-        initialize_cpus(&dev->link[0]);
+	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
+	initialize_cpus(&dev->link[0]);
 }
 
 static void cpu_bus_noop(device_t dev)
@@ -197,14 +210,19 @@
 
 static void enable_dev(struct device *dev)
 {
+        printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+        	printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
                 dev->ops = &pci_domain_ops;
 		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+        	printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
-        }
+        } else {
+        	printk_spew("device path type %d\n",dev->path.type);
+	}
 }
 
 struct chip_operations northbridge_amd_gx1_ops = {




From rminnich at lanl.gov  Wed Aug 16 16:35:33 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Wed, 16 Aug 2006 08:35:33 -0600
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E32C16.8050708@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net>	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net> <44E328A1.8010208@lanl.gov>
	<44E32C16.8050708@speakeasy.net>
Message-ID: <44E32D35.5040909@lanl.gov>

Jonathan Sturges wrote:

> Granted, both of these patches were offered up as "hacks," but they 
> work, allowing the GX1 cache to be enabled and for the IRQ map to be 
> successfully copied, so I endorse them.  :-)
> 
> thanks,
> Jonathan
> 

Committed as rev 2379, builds fine, not tested; let me know.

thanks

ron



From smithbone at gmail.com  Wed Aug 16 17:24:49 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 16 Aug 2006 10:24:49 -0500
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E32D35.5040909@lanl.gov>
References: <44E22DB0.2040905@speakeasy.net>
	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net> <44E328A1.8010208@lanl.gov>
	<44E32C16.8050708@speakeasy.net> <44E32D35.5040909@lanl.gov>
Message-ID: <8a0c36780608160824w2de56a36tf6b76cd93f4fc72f@mail.gmail.com>

> > Granted, both of these patches were offered up as "hacks," but they
> > work, allowing the GX1 cache to be enabled and for the IRQ map to be
> > successfully copied, so I endorse them.  :-)
> >
>
> Committed as rev 2379, builds fine, not tested; let me know.
>

Woah.. Slow down there Tex. And give the authors of the patch(s) a bit
of time to respond.  :)

My patch was for tyring to figure out if thats really what the problem
was.  The framework was failing to do it properly.

I never applied that patch since it just covers up a problem rather
than fixing it.

I don't have the hardware so it was difficult for me to rework and fix
it the Right Way.

IIRC the problem was that the device chain was looking for a APIC
cluster and not finding that it took a different route that did not
call the cache init function.

We need to find and fix the real problem rather than bandaid over the issue.

Jonathan thanks for being the squeaky wheel and not letting this drop.
 Have you come up to speed yet on the device chain init code?

I think this may just be a static dev tree issue.   If nobody gets to
it before me I'll try to look at it tonight.

-- 
Richard A. Smith



From rminnich at lanl.gov  Wed Aug 16 17:29:22 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Wed, 16 Aug 2006 09:29:22 -0600
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <8a0c36780608160824w2de56a36tf6b76cd93f4fc72f@mail.gmail.com>
References: <44E22DB0.2040905@speakeasy.net>	
	<200608160939.59196.juergen127@kreuzholzen.de>	
	<44E30852.4040402@speakeasy.net> <44E328A1.8010208@lanl.gov>	
	<44E32C16.8050708@speakeasy.net> <44E32D35.5040909@lanl.gov>
	<8a0c36780608160824w2de56a36tf6b76cd93f4fc72f@mail.gmail.com>
Message-ID: <44E339D2.8090709@lanl.gov>

Richard Smith wrote:
>> > Granted, both of these patches were offered up as "hacks," but they
>> > work, allowing the GX1 cache to be enabled and for the IRQ map to be
>> > successfully copied, so I endorse them.  :-)
>> >
>>
>> Committed as rev 2379, builds fine, not tested; let me know.
>>
> 
> Woah.. Slow down there Tex. And give the authors of the patch(s) a bit
> of time to respond.  :)

sorry. It just seemd this had been lingering for a while.

I dont' see an issue with the enable shadow patch, however.


thanks

ron



From smithbone at gmail.com  Wed Aug 16 17:40:46 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 16 Aug 2006 10:40:46 -0500
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E339D2.8090709@lanl.gov>
References: <44E22DB0.2040905@speakeasy.net>
	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net> <44E328A1.8010208@lanl.gov>
	<44E32C16.8050708@speakeasy.net> <44E32D35.5040909@lanl.gov>
	<8a0c36780608160824w2de56a36tf6b76cd93f4fc72f@mail.gmail.com>
	<44E339D2.8090709@lanl.gov>
Message-ID: <8a0c36780608160840w76d52a39s1c987549bdc4e9cd@mail.gmail.com>

>
> sorry. It just seemd this had been lingering for a while.
>
> I dont' see an issue with the enable shadow patch, however.

Maybe there isn't.  But I just didn't want to blindly go around the
established way until we thought about it.

So if your board dosen't have an APIC cluster whats the right way to
describe that?

-- 
Richard A. Smith



From jsturges at speakeasy.net  Wed Aug 16 21:08:27 2006
From: jsturges at speakeasy.net (Jonathan Sturges)
Date: Wed, 16 Aug 2006 15:08:27 -0400
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <8a0c36780608160824w2de56a36tf6b76cd93f4fc72f@mail.gmail.com>
References: <44E22DB0.2040905@speakeasy.net>	
	<200608160939.59196.juergen127@kreuzholzen.de>	
	<44E30852.4040402@speakeasy.net> <44E328A1.8010208@lanl.gov>	
	<44E32C16.8050708@speakeasy.net> <44E32D35.5040909@lanl.gov>
	<8a0c36780608160824w2de56a36tf6b76cd93f4fc72f@mail.gmail.com>
Message-ID: <44E36D2B.5060502@speakeasy.net>

Richard Smith wrote:

>> > Granted, both of these patches were offered up as "hacks," but they
>> > work, allowing the GX1 cache to be enabled and for the IRQ map to be
>> > successfully copied, so I endorse them.  :-)
>> >
>>
>> Committed as rev 2379, builds fine, not tested; let me know.
>>
>
> Woah.. Slow down there Tex. And give the authors of the patch(s) a bit
> of time to respond.  :)
>
> My patch was for tyring to figure out if thats really what the problem
> was.  The framework was failing to do it properly.
>
> I never applied that patch since it just covers up a problem rather
> than fixing it.
>
> I don't have the hardware so it was difficult for me to rework and fix
> it the Right Way.
>
> IIRC the problem was that the device chain was looking for a APIC
> cluster and not finding that it took a different route that did not
> call the cache init function.
>
> We need to find and fix the real problem rather than bandaid over the 
> issue.
>
> Jonathan thanks for being the squeaky wheel and not letting this drop.
> Have you come up to speed yet on the device chain init code?
>
> I think this may just be a static dev tree issue.   If nobody gets to
> it before me I'll try to look at it tonight.
>

Heh... I'm glad to be the squeaky wheel, but thus far I've taken an 
implementer's stance with LB and haven't learned the code.
I will try to take a look but it may be the weekend before I have any 
appreciable time for it.

I can provide you hardware, if it will help.  The thin clients I'm using 
can be had for US$10 on eBay.  If you're in the states, I'll ship you one.

thanks,
Jonathan



From smithbone at gmail.com  Wed Aug 16 21:22:53 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 16 Aug 2006 14:22:53 -0500
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E36D2B.5060502@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net>
	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net> <44E328A1.8010208@lanl.gov>
	<44E32C16.8050708@speakeasy.net> <44E32D35.5040909@lanl.gov>
	<8a0c36780608160824w2de56a36tf6b76cd93f4fc72f@mail.gmail.com>
	<44E36D2B.5060502@speakeasy.net>
Message-ID: <8a0c36780608161222r730bbf2bof0950445772884dc@mail.gmail.com>

>
> Heh... I'm glad to be the squeaky wheel, but thus far I've taken an
> implementer's stance with LB and haven't learned the code.
> I will try to take a look but it may be the weekend before I have any
> appreciable time for it.

Well if you haven't been hacking on it the device code can be pretty
difficult to follow but if you grok that then you pretty much grok all
of LinuxBIOS structure.

> I can provide you hardware, if it will help.  The thin clients I'm using
> can be had for US$10 on eBay.  If you're in the states, I'll ship you one.

I am.  $10?  How many extra do you have?  Let me go look at whats on
that puppy  maybe I'll just buy one from you.  I need something for
some remote temp monitoring in my house.

OLPC has a lot of my spare hacking cycles consumed so I may not be
able to spend any more time on it than you.  But physical hardware and
having a project to use it on tends to up the priority level.

-- 
Richard A. Smith



From smithbone at gmail.com  Wed Aug 16 22:01:44 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 16 Aug 2006 15:01:44 -0500
Subject: [LinuxBIOS] Geode GX1 system IRQ handling
In-Reply-To: <44E30852.4040402@speakeasy.net>
References: <44E22DB0.2040905@speakeasy.net>
	<200608160939.59196.juergen127@kreuzholzen.de>
	<44E30852.4040402@speakeasy.net>
Message-ID: <8a0c36780608161301kf10db3eleb5650f9ee2d216d@mail.gmail.com>

On 8/16/06, Jonathan Sturges <jsturges at speakeasy.net> wrote:

>  PCI: No IRQ known for interrupt pin A of device 00:13.0. Please try using
> pci=biosirq.
>  usb-ohci.c: found OHCI device with no IRQ assigned. check BIOS settings!
>
>  ...which basically means the entries for these devices in the IRQ map are
> either wrong, or missing.

This means that PCI interrupt A was aserted but was not routed to any
particular IRQ.

So then its very likely then that IntA is wired to the USB bridge.
Theres your first bit of routing info to try.  This and lspci gives
you most of the info you need.

Take the existing $PIR table and change it such that IntA is routed to
the IRQ of your choice ( an unused one is a good choice) and tell the
dirver to use that irq.

Now just because you have a irq table dosen't mean that the irq router
gets magically setup.  Depends on what the LinuxBIOS code does and
what Linux does. Linux in the past has not done a lot of the IRQ
routeing setup but its getting better all the time.

You will need to look at the datasheet for the IRQ router to see what
registers need to be dumped to see what PCI Int pins are routed to
wthat IRQ.

-- 
Richard A. Smith



From svn at openbios.org  Thu Aug 17 22:31:10 2006
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 17 Aug 2006 22:31:10 +0200
Subject: [LinuxBIOS] r2380 - in trunk/LinuxBIOSv2/src:
	mainboard/sunw/ultra40 superio/smsc superio/smsc/lpc47m10x
Message-ID: <E1GDoWE-0000Gn-B8@khepri.openbios.org>

Author: rminnich
Date: 2006-08-17 22:31:09 +0200 (Thu, 17 Aug 2006)
New Revision: 2380

Added:
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/Config.lb
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/chip.h
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x.h
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c
Modified:
   trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb
Log:
add smsc part. Mod sun board to use smsc part for now


Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb	2006-08-16 14:38:00 UTC (rev 2379)
+++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Config.lb	2006-08-17 20:31:09 UTC (rev 2380)
@@ -207,8 +207,8 @@
 			        chip southbridge/nvidia/ck804 
 					device pci 0.0 on end   # HT
                 			device pci 1.0 on # LPC
-                	                        chip superio/smsc/lpc47b397
-                        	                        device pnp 2e.0 on #  Floppy
+                	                        chip superio/smsc/lpc47m10x
+                        	                        device pnp 2e.0 off #  Floppy
                                 	                         io 0x60 = 0x3f0
                                         	                irq 0x70 = 6
                                                 	        drq 0x74 = 2
@@ -225,24 +225,12 @@
                         	                                io 0x60 = 0x2f8
                                 	                        irq 0x70 = 3
                                         	        end
-	                                                device pnp 2e.7 on #  Keyboard
+	                                                device pnp 2e.7 off #  Keyboard
         	                                                io 0x60 = 0x60
                 	                                        io 0x62 = 0x64
                         	                                irq 0x70 = 1
                                 	                        irq 0x72 = 12
                                         	        end
-	                                                device pnp 2e.8 on # HW Monitor
-        	                                                io 0x60 = 0x290
-                                                                chip drivers/generic/generic # LM95221 CPU temp
-                                                                        device i2c 2b on end
-                                                                end
-                                                                chip drivers/generic/generic # EMCT03
-                                                                        device i2c 54 on end
-                                                                end
-							end
-	                                                device	pnp 2e.a on #  RT
-        	                                                io 0x60 = 0x400
-							end
                         	                end
 					end
 			                device pci 1.1 on # SM 0

Added: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/Config.lb	2006-08-17 20:31:09 UTC (rev 2380)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o

Added: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/chip.h	2006-08-17 20:31:09 UTC (rev 2380)
@@ -0,0 +1,10 @@
+struct chip_operations;
+extern struct chip_operations superio_smsc_lpc47m10x_ops;
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct superio_smsc_lpc47m10x_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};

Added: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x.h	2006-08-17 20:31:09 UTC (rev 2380)
@@ -0,0 +1,10 @@
+#define LPC47M10X2_FDC              0   /* Floppy */
+#define LPC47M10X2_PP               3   /* Parallel Port */
+#define LPC47M10X2_SP1              4   /* Com1 */
+#define LPC47M10X2_SP2              5   /* Com2 */
+#define LPC47M10X2_KBC              7   /* Keyboard & Mouse */
+#define LPC47M10X2_GAME             9  /* GAME */
+#define LPC47M10X2_PME             10   /* PME  reg*/
+#define LPC47M10X2_MPU           10   /* MPE -- who knows --   reg*/
+
+#define LPC47M10X2_MAX_CONFIG_REGISTER	0x5F

Added: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c	2006-08-17 20:31:09 UTC (rev 2380)
@@ -0,0 +1,69 @@
+/*
+ * $Header$
+ *
+ * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
+ * derived from lpc47n217
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * $Log$
+ *
+ */
+
+#include <arch/romcc_io.h>
+#include "lpc47m10x.h"
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47M10X2's configuration registers.
+//
+static inline void pnp_enter_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0x55, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47M10X2's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0xaa, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47b272.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
+static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}

Added: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c	2006-08-17 20:31:09 UTC (rev 2380)
@@ -0,0 +1,228 @@
+/*
+ * $Header$
+ *
+ * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
+ *
+ * Copyright 2000  AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan 
+ * Copyright (C) 2005 Digital Design Corporation
+ * Copyright (C) Ron Minnich, LANL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * $Log$
+ *
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "lpc47m10x.h"
+
+// Forward declarations
+static void enable_dev(device_t dev);
+void lpc47m10x_pnp_set_resources(device_t dev);
+void lpc47m10x_pnp_set_resources(device_t dev);
+void lpc47m10x_pnp_enable_resources(device_t dev);
+void lpc47m10x_pnp_enable(device_t dev);
+static void lpc47m10x_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+static void dump_pnp_device(device_t dev);
+
+
+struct chip_operations superio_smsc_lpc47m10x_ops = {
+	CHIP_NAME("smsc lpc47m10x")
+	.enable_dev = enable_dev
+};
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = lpc47m10x_pnp_set_resources,
+	.enable_resources = lpc47m10x_pnp_enable_resources,
+	.enable           = lpc47m10x_pnp_enable,
+	.init             = lpc47m10x_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+        { &ops, LPC47M10X2_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+        { &ops, LPC47M10X2_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+        { &ops, LPC47M10X2_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+        { &ops, LPC47M10X2_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+        { &ops, LPC47M10X2_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+        { &ops, LPC47M10X2_RT,   PNP_IO0, { 0x780, 0 }, },
+};
+
+/**********************************************************************************/
+/*								PUBLIC INTERFACE								  */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	enable_dev
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Create device structures and allocate resources to devices 
+//					specified in the pnp_dev_info array (above).
+//
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, 
+					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47m10x_pnp_set_resources
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Configure the specified Super I/O device with the resources
+//					(I/O space, etc.) that have been allocated for it.
+//
+void lpc47m10x_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);  
+	pnp_set_resources(dev);
+    pnp_exit_conf_state(dev);  
+}       
+
+void lpc47m10x_pnp_enable_resources(device_t dev)
+{       
+	pnp_enter_conf_state(dev);
+    pnp_enable_resources(dev);
+    pnp_exit_conf_state(dev);
+}
+
+void lpc47m10x_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);   
+	pnp_set_logical_device(dev);
+
+	if(dev->enabled) {
+		pnp_set_enable(dev, 1);
+	}
+	else {
+		pnp_set_enable(dev, 0);
+	}
+	pnp_exit_conf_state(dev);  
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47m10x_init
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Initialize the specified Super I/O device.
+//					Devices other than COM ports and the keyboard controller are 
+//					ignored. For COM ports, we configure the baud rate. 
+//
+static void lpc47m10x_init(device_t dev)
+{
+	struct superio_smsc_lpc47m10x_config *conf = dev->chip_info;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled)
+		return;
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47M10X2_SP1: 
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+		
+	case LPC47M10X2_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+		
+	case LPC47M10X2_KBC:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	}
+}
+
+/**********************************************************************************/
+/*								PRIVATE FUNCTIONS							      */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Enable access to the LPC47M10X2's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev) 
+{
+	outb(0x55, dev->path.u.pnp.port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Disable access to the LPC47M10X2's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) 
+{
+    outb(0xaa, dev->path.u.pnp.port);
+}
+
+#if 0
+//----------------------------------------------------------------------------------
+// Function:    	dump_pnp_device
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Print the values of all of the LPC47M10X2's configuration registers.
+//					NOTE: The LPC47M10X2 must be in configuration mode when this
+//						  function is called.
+//
+static void dump_pnp_device(device_t dev)
+{
+    int register_index;
+    print_debug("\r\n");
+
+    for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) {
+        uint8_t register_value;
+
+        if ((register_index & 0x0f) == 0) {
+                print_debug_hex8(register_index);
+                print_debug_char(':');
+        }
+
+		// Skip over 'register' that would cause exit from configuration mode
+	    if (register_index == 0xaa)
+			register_value = 0xaa;
+		else
+        	register_value = pnp_read_config(dev, register_index);
+
+        print_debug_char(' ');
+        print_debug_hex8(register_value);
+        if ((register_index & 0x0f) == 0x0f) {
+        	print_debug("\r\n");
+        }
+    }
+
+   	print_debug("\r\n");
+}
+#endif




From info at coresystems.de  Thu Aug 17 23:07:54 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 17 Aug 2006 23:07:54 +0200
Subject: [LinuxBIOS] LinuxBIOS r2380 build changes
Message-ID: <E1GDp5m-0001Fi-4h@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2380 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
add smsc part. Mod sun board to use smsc part for now

Build Log:
 Compilation of sunw:ultra40 has been broken

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From bari at onelabs.com  Fri Aug 18 08:28:42 2006
From: bari at onelabs.com (Bari Ari)
Date: Fri, 18 Aug 2006 01:28:42 -0500
Subject: [LinuxBIOS] AMD Turion - AGESA
In-Reply-To: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A4207004124@ssvlexmb2.amd.com>
Message-ID: <44E55E1A.5000808@onelabs.com>

Lu, Yinghai wrote:
> AGESA is in assembly code now, and it is only can be released to IBV
> under NDA. IBV use the source code in their framework.
>
> Current LinuxBIOS support code for rev F are LinuxBIOS native code. 
>   

Is all the source to support the NPT Family 10h DDR2 processors now in 
the current tree?

-Bari



From yinghai.lu at amd.com  Fri Aug 18 19:00:47 2006
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 18 Aug 2006 10:00:47 -0700
Subject: [LinuxBIOS] AMD Turion - AGESA
Message-ID: <6F7DA19D05F3CF40B890C7CA2DB13A4207004157@ssvlexmb2.amd.com>

It is under processing.

YH

-----Original Message-----
From: Bari Ari [mailto:bari at onelabs.com] 
Sent: Thursday, August 17, 2006 11:29 PM
To: Lu, Yinghai
Cc: Ronald G Minnich; jf simon; linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] AMD Turion - AGESA

Lu, Yinghai wrote:
> AGESA is in assembly code now, and it is only can be released to IBV
> under NDA. IBV use the source code in their framework.
>
> Current LinuxBIOS support code for rev F are LinuxBIOS native code. 
>   

Is all the source to support the NPT Family 10h DDR2 processors now in 
the current tree?

-Bari







From svn at openbios.org  Fri Aug 18 21:25:25 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 18 Aug 2006 21:25:25 +0200
Subject: [LinuxBIOS] r2381 - in trunk/LinuxBIOSv2:
	src/superio/smsc/lpc47m10x targets/sunw/ultra40
Message-ID: <E1GE9y9-0006lW-GS@khepri.openbios.org>

Author: rminnich
Date: 2006-08-18 21:25:25 +0200 (Fri, 18 Aug 2006)
New Revision: 2381

Modified:
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c
   trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb
Log:
delete unused device. 
set rom to 512k


Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c	2006-08-17 20:31:09 UTC (rev 2380)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c	2006-08-18 19:25:25 UTC (rev 2381)
@@ -71,7 +71,6 @@
         { &ops, LPC47M10X2_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
         { &ops, LPC47M10X2_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
         { &ops, LPC47M10X2_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
-        { &ops, LPC47M10X2_RT,   PNP_IO0, { 0x780, 0 }, },
 };
 
 /**********************************************************************************/

Modified: trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb	2006-08-17 20:31:09 UTC (rev 2380)
+++ trunk/LinuxBIOSv2/targets/sunw/ultra40/Config.lb	2006-08-18 19:25:25 UTC (rev 2381)
@@ -5,6 +5,7 @@
 target ultra40
 mainboard sunw/ultra40
 
+option ROM_SIZE=512*1024
 # sunw ultra40
 romimage "normal"
 #       48K for SCSI FW




From info at coresystems.de  Fri Aug 18 22:02:18 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 18 Aug 2006 22:02:18 +0200
Subject: [LinuxBIOS] LinuxBIOS r2381 build changes
Message-ID: <E1GEAXq-000815-ER@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2381 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
delete unused device.set rom to 512k

Build Log:
 Compilation of sunw:ultra40 has been fixed.

If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From uwe at hermann-uwe.de  Sat Aug 19 21:29:50 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 19 Aug 2006 21:29:50 +0200
Subject: [LinuxBIOS] PATCH: IT8671F fixes.
Message-ID: <20060819192949.GA18374@aragorn>

Hi,

here's a bunch of fixes for the IT8671F Super IO. 


HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/superio/ite/it8671f/it8671f_early_serial.c
===================================================================
--- src/superio/ite/it8671f/it8671f_early_serial.c	(Revision 2381)
+++ src/superio/ite/it8671f/it8671f_early_serial.c	(Arbeitskopie)
@@ -20,18 +20,18 @@
 #include "it8671f.h"
 
 /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE  0x3f0
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA  SIO_BASE+1
+#define SIO_BASE                    0x3f0
+#define SIO_INDEX                   SIO_BASE
+#define SIO_DATA                    SIO_BASE+1
 
-/* TODO: These values are actually from the IT8673F datasheet; check if
-   they're also valid for the IT8671F. */
-#define IT8671F_CONFIG_REG_CC       0x02 /* Configure Control. */
-#define IT8671F_CONFIG_REG_LDN      0x07 /* Logical Device Number. */
-#define IT8671F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8671F_CONFIG_REG_SWSUSP   0x24 /* Software Suspend. */
+/* Global Configuration Registers. */
+#define IT8671F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
+#define IT8671F_CONFIG_REG_LDN     0x07   /* Logical Device Number. */
+#define IT8671F_CONFIG_REG_LDE     0x23   /* PnP Logical Device Enable. */
+#define IT8671F_CONFIG_REG_SWSUSP  0x24   /* Software Suspend. */
 
-#define IT8671F_ADDRESS_PORT        0x279
+#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
+#define IT8671F_WRITE_DATA_PORT    0x0A79 /* Write-only. */
 
 /* Special values used for entering MB PnP mode. The first four bytes of
  * each line determine the address port, the last four are data. */
@@ -42,7 +42,7 @@
 	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
 };
 
-/* The content of IT8671F_CONFIG_REG_LDN (index 07h) must be set to the
+/* The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the
  * LDN the register belongs to, before you can access the register. */
 static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
@@ -63,10 +63,10 @@
 	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
 	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
 	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
-	outb(0x86, IT8671F_ADDRESS_PORT);
-	outb(0x80, IT8671F_ADDRESS_PORT);
-	outb(0x55, IT8671F_ADDRESS_PORT);
-	outb(0x55, IT8671F_ADDRESS_PORT);
+	outb(0x86, IT8671F_CONFIGURATION_PORT);
+	outb(0x80, IT8671F_CONFIGURATION_PORT);
+	outb(0x55, IT8671F_CONFIGURATION_PORT);
+	outb(0x55, IT8671F_CONFIGURATION_PORT);
 
 	/* Sequentially write the 32 special values. */
 	for (i = 0; i < 32; i++) {
@@ -75,14 +75,20 @@
 
 	/* (2) Modify the data of configuration registers. */
 
-	/* Enable parallel port, serial port 1, serial port 2, floppy. */
-	it8671f_sio_write(0x00, 0x23, 0x0f);
+	/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
+           PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
+	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
 
-	/* Activate serial port 1 and 2. */
-	it8671f_sio_write(0x01, 0x30, 0x1);
-	it8671f_sio_write(0x02, 0x30, 0x1);
+	/* Activate all devices. */  
+	it8671f_sio_write(IT8671F_FDC,  0x30, 0x01); /* Floppy */
+	it8671f_sio_write(IT8671F_SP1,  0x30, 0x01); /* Serial port 1 */
+	it8671f_sio_write(IT8671F_SP2,  0x30, 0x01); /* Serial port 2 */
+	it8671f_sio_write(IT8671F_PP,   0x30, 0x01); /* Parallel port */
+	it8671f_sio_write(IT8671F_KBCK, 0x30, 0x01); /* Keyboard */
+	it8671f_sio_write(IT8671F_KBCM, 0x30, 0x01); /* Mouse */
 
-	/* Select 24MHz CLKIN and clear software suspend mode. */
+	/* Select 24MHz CLKIN (clear bit 6) and clear software suspend
+	   mode (clear bit 0). */
 	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
 
 	/* (3) Exit the configuration state (MB PnP mode). */
Index: src/superio/ite/it8671f/superio.c
===================================================================
--- src/superio/ite/it8671f/superio.c	(Revision 2381)
+++ src/superio/ite/it8671f/superio.c	(Arbeitskopie)
@@ -33,8 +33,7 @@
 	conf = dev->chip_info;
 
 	switch (dev->path.u.pnp.device) {
-	case IT8671F_FDC:
-		/* TODO. */
+	case IT8671F_FDC: /* TODO. */
 		break;
 	case IT8671F_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
@@ -44,11 +43,15 @@
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com2);
 		break;
+	case IT8671F_PP: /* TODO. */
+		break;
 	case IT8671F_KBCK:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		res1 = find_resource(dev, PNP_IDX_IO1);
 		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
 		break;
+	case IT8671F_KBCM: /* TODO. */
+		break;
 	}
 }
 
@@ -60,12 +63,10 @@
 	.init             = init,
 };
 
-/* TODO: Find and check datasheet. */
+/* TODO: FDC, PP, KBCM. */
 static struct pnp_info pnp_dev_info[] = {
- { &ops, IT8671F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
- /* { &ops, IT8671F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, */
+ { &ops, IT8671F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
  { &ops, IT8671F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
- { &ops, IT8671F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
  { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
 };
 
Index: src/superio/ite/it8671f/it8671f.h
===================================================================
--- src/superio/ite/it8671f/it8671f.h	(Revision 2381)
+++ src/superio/ite/it8671f/it8671f.h	(Arbeitskopie)
@@ -16,11 +16,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* TODO: Find datasheet and check for correct values. */
 #define IT8671F_FDC  0x00 /* Floppy */
-/* #define IT8671F_PP   0x01 */ /* Parallel port */
+#define IT8671F_SP1  0x01 /* Com1 */
 #define IT8671F_SP2  0x02 /* Com2 */
-#define IT8671F_SP1  0x03 /* Com1 */
-#define IT8671F_KBCK 0x06 /* Keyboard */
-/* #define IT8671F_FAN  0x09 */
+#define IT8671F_PP   0x03 /* Parallel port */
+#define IT8671F_KBCK 0x05 /* Keyboard */
+#define IT8671F_KBCM 0x06 /* Mouse */
 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060819/1248b6a8/attachment.sig>

From uwe at hermann-uwe.de  Mon Aug 21 14:18:15 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 21 Aug 2006 14:18:15 +0200
Subject: [LinuxBIOS] PATCH: Various cleanups.
Message-ID: <20060821121815.GA12544@aragorn>

Hi,

here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.

HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/southbridge/intel/i82801ca/i82801ca.c
===================================================================
--- src/southbridge/intel/i82801ca/i82801ca.c	(Revision 2381)
+++ src/southbridge/intel/i82801ca/i82801ca.c	(Arbeitskopie)
@@ -7,8 +7,8 @@
 
 void i82801ca_enable(device_t dev)
 {
-	unsigned int index = 0;
-	uint8_t bHasDisableBit = 0;
+	unsigned int index = 0;
+	uint8_t bHasDisableBit = 0;
 	uint16_t cur_disable_mask, new_disable_mask;
 
 //	all 82801ca devices are in bus 0
@@ -19,22 +19,22 @@
 
 	// Calculate disable bit position for specified device:function
 	// NOTE: For ICH-3, only the following devices can be disabled:
-	//		 D31:F1, D31:F3, D31:F5, D31:F6, 
-	//		 D29:F0, D29:F1, D29:F2
+	//		 D31:F1, D31:F3, D31:F5, D31:F6, 
+	//		 D29:F0, D29:F1, D29:F2
 
     if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
-    	index = PCI_FUNC(dev->path.u.pci.devfn);
-
-		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
-			bHasDisableBit = 1;
+    	index = PCI_FUNC(dev->path.u.pci.devfn);
 
+		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
+			bHasDisableBit = 1;
+
     } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
-    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
-
-		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
+    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
+
+		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
 			bHasDisableBit = 1;
     }
-
+
 	if (bHasDisableBit) {
 		cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
 		new_disable_mask = cur_disable_mask & ~(1<<index); 		// enable it
@@ -43,7 +43,7 @@
 		}
 		if (new_disable_mask != cur_disable_mask) {
 			pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
-		}
+		}
 	}
 }
 
Index: src/southbridge/intel/i82801ca/i82801ca_ide.c
===================================================================
--- src/southbridge/intel/i82801ca/i82801ca_ide.c	(Revision 2381)
+++ src/southbridge/intel/i82801ca/i82801ca_ide.c	(Arbeitskopie)
@@ -10,7 +10,7 @@
 {
 	/* Enable ide devices so the linux ide driver will work */
 	uint16_t ideTimingConfig;
-	int enable_primary = 1;
+	int enable_primary = 1;
 	int enable_secondary = 1;
 
 	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
Index: src/southbridge/intel/i82801ca/i82801ca.h
===================================================================
--- src/southbridge/intel/i82801ca/i82801ca.h	(Revision 2381)
+++ src/southbridge/intel/i82801ca/i82801ca.h	(Arbeitskopie)
@@ -1,10 +1,10 @@
 #ifndef I82801CA_H
 #define I82801CA_H
-
-#ifndef __ROMCC__
+
+#ifndef __ROMCC__
 #include "chip.h"
-extern void i82801ca_enable(device_t dev);
-#endif
+extern void i82801ca_enable(device_t dev);
+#endif
 
 
 #define PCI_DMA_CFG     0x90
@@ -26,37 +26,37 @@
 #define FUNC_DIS        0xF2
 
 // GEN_PMCON_3 bits
-#define RTC_BATTERY_DEAD		(1<<2)
-#define RTC_POWER_FAILED		(1<<1)
+#define RTC_BATTERY_DEAD		(1<<2)
+#define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
-
-/********************************************************************/
-/*							IDE Controller                          */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F1)
-#define IDE_TIM_PRI		0x40		// IDE timings, primary
-#define IDE_TIM_SEC		0x42		// IDE timings, secondary
-
-
-// IDE_TIM bits
-#define IDE_DECODE_ENABLE	(1<<15)
-
-/********************************************************************/
-/*								SMBus                               */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F3)
+
+/********************************************************************/
+/*							IDE Controller                          */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F1)
+#define IDE_TIM_PRI		0x40		// IDE timings, primary
+#define IDE_TIM_SEC		0x42		// IDE timings, secondary
+
+
+// IDE_TIM bits
+#define IDE_DECODE_ENABLE	(1<<15)
+
+/********************************************************************/
+/*								SMBus                               */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20
-#define HOSTC		0x40
-
-// HOSTC bits
-#define I2C_EN		(1<<2)
-#define SMB_SMI_EN	(1<<1)
-#define HST_EN		(1<<0)
+#define HOSTC		0x40
 
+// HOSTC bits
+#define I2C_EN		(1<<2)
+#define SMB_SMI_EN	(1<<1)
+#define HST_EN		(1<<0)
+
 #define SMBUS_IO_BASE 0x1000
-
+
 // I/O registers (relative to SMBUS_IO_BASE)
 #define SMBHSTSTAT		0
 #define SMBHSTCTL		2
@@ -69,7 +69,7 @@
 #define SMBSLVDATA		10
 #define SMLINK_PIN_CTL	14
 #define SMBUS_PIN_CTL	15 
-
+
 /* Between 1-10 seconds, We should never timeout normally 
  * Longer than this is just painful when a timeout condition occurs.
  */
Index: src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
===================================================================
--- src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	(Revision 2381)
+++ src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	(Arbeitskopie)
@@ -1,5 +1,5 @@
 #include <device/pci_ids.h>
-#include "i82801ca.h"
+#include "i82801ca.h"
 
 static void enable_smbus(void)
 {
Index: src/southbridge/intel/i82801ca/cmos_failover.c
===================================================================
--- src/southbridge/intel/i82801ca/cmos_failover.c	(Revision 2381)
+++ src/southbridge/intel/i82801ca/cmos_failover.c	(Arbeitskopie)
@@ -1,19 +1,19 @@
-//kind of cmos_err for ich3
-
-#include "i82801ca.h"
+//kind of cmos_err for ich3
 
+#include "i82801ca.h"
+
 static void check_cmos_failed(void) 
-{
+{
 #if HAVE_OPTION_TABLE
-	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
+	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
 
 	if( byte & RTC_BATTERY_DEAD) {
-		// Set boot_option and last_boot to 'Fallback',
+		// Set boot_option and last_boot to 'Fallback',
 		// clear reboot_bits
         byte = cmos_read(RTC_BOOT_BYTE);
         byte &= 0x0c;
         byte |= MAX_REBOOT_CNT << 4;
         cmos_write(byte, RTC_BOOT_BYTE);
-    }
+    }
 #endif
 }
Index: src/southbridge/intel/i82801ca/i82801ca_smbus.c
===================================================================
--- src/southbridge/intel/i82801ca/i82801ca_smbus.c	(Revision 2381)
+++ src/southbridge/intel/i82801ca/i82801ca_smbus.c	(Arbeitskopie)
@@ -1,7 +1,7 @@
 #include <smbus.h>
 #include <pci.h>
 #include <arch/io.h>
-#include "i82801ca.h"
+#include "i82801ca.h"
 
 #define PM_BUS 0
 #define PM_DEVFN PCI_DEVFN(0x1f,3)
@@ -9,7 +9,7 @@
 void smbus_enable(void)
 {
 	/* iobase addr */
-	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 
+	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 
 							   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
 	/* smbus enable */
 	pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);
Index: src/southbridge/intel/i82801ca/i82801ca_lpc.c
===================================================================
--- src/southbridge/intel/i82801ca/i82801ca_lpc.c	(Revision 2381)
+++ src/southbridge/intel/i82801ca/i82801ca_lpc.c	(Arbeitskopie)
@@ -1,7 +1,7 @@
 /*
  * (C) 2003 Linux Networx, SuSE Linux AG
  * (C) 2004 Tyan Computer
- * (c) 2005 Digital Design Corporation
+ * (c) 2005 Digital Design Corporation
  */
 #include <console/console.h>
 #include <device/device.h>
@@ -14,15 +14,15 @@
 #include "i82801ca.h"
 
 #define NMI_OFF 0
-
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON  1
-
 
+#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+
 void i82801ca_enable_ioapic( struct device *dev) 
 {
 	uint32_t dword;
@@ -60,20 +60,20 @@
     pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	i82801ca_lpc_route_dma
+//----------------------------------------------------------------------------------
+// Function:    	i82801ca_lpc_route_dma
 // Parameters:  	dev
 //					mask - identifies whether each channel should be used for PCI DMA
 //						   (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-//						   Channel 4 is not used (reserved). 
-// Return Value:	None
-// Description: 	Route all DMA channels to either PCI or LPC.
-//
+//						   Channel 4 is not used (reserved). 
+// Return Value:	None
+// Description: 	Route all DMA channels to either PCI or LPC.
+//
 void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) 
 {
     uint16_t dmaConfig;
     int channelIndex;
-
+
     dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
     dmaConfig &= 0x300;				// Preserve reserved bits
     for(channelIndex = 0; channelIndex < 8; channelIndex++) {
@@ -87,27 +87,27 @@
 void i82801ca_rtc_init(struct device *dev)
 {
     uint32_t dword;
-    int rtc_failed;
-	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
-    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
+    int rtc_failed;
+	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
 
     rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
     if (rtc_failed) {
     	// Clear the RTC_BATTERY_DEAD bit, but preserve
-        // the RTC_POWER_FAILED, G3 state, and reserved bits
+        // the RTC_POWER_FAILED, G3 state, and reserved bits
 		// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
         pmcon3 &= ~RTC_POWER_FAILED;
-    }
-
-    get_option(&pwr_on, "power_on_after_fail");
-	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
-	if (!pwr_on) {
-		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
-	}
-	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
-	printk_info("set power %s after power fail\n", 
-				 pwr_on ? "on" : "off");
+    }
 
+    get_option(&pwr_on, "power_on_after_fail");
+	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
+	if (!pwr_on) {
+		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
+	}
+	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
+	printk_info("set power %s after power fail\n", 
+				 pwr_on ? "on" : "off");
+
     // See if the Safe Mode jumper is set
     dword = pci_read_config32(dev, GEN_STS);
     rtc_failed |= dword & (1 << 2);
@@ -142,14 +142,14 @@
     // Enable access to the upper 128 byte bank of CMOS RAM
     pci_write_config8(dev, RTC_CONF, 0x04);
         
-    // Decode 0x3F8-0x3FF (COM1) for COMA port,
+    // Decode 0x3F8-0x3FF (COM1) for COMA port,
 	//		  0x2F8-0x2FF (COM2) for COMB
     pci_write_config8(dev, COM_DEC, 0x10);
-
-	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
-	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
 
-    // Enable COMA, COMB, LPT, floppy; 
+	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
+	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
+
+    // Enable COMA, COMB, LPT, floppy; 
 	// disable microcontroller, Super I/O, sound, gameport
     pci_write_config16(dev, LPC_EN, 0x000F);
 }
@@ -179,18 +179,18 @@
     pci_write_config8(dev, GEN_PMCON_3, byte);
     printk_info("set power %s after power fail\n", pwr_on?"on":"off");
 
-    /* Set up NMI on errors */
-    byte = inb(0x61);
-    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
-    byte &= ~(1 << 2); /* PCI SERR# Enable */
-    outb(byte, 0x61);
-    byte = inb(0x70);
-    nmi_option = NMI_OFF;
-    get_option(&nmi_option, "nmi");
-    if (nmi_option) {			
-        byte &= ~(1 << 7); /* set NMI */
-        outb(byte, 0x70);
-    }
+    /* Set up NMI on errors */
+    byte = inb(0x61);
+    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+    byte &= ~(1 << 2); /* PCI SERR# Enable */
+    outb(byte, 0x61);
+    byte = inb(0x70);
+    nmi_option = NMI_OFF;
+    get_option(&nmi_option, "nmi");
+    if (nmi_option) {			
+        byte &= ~(1 << 7); /* set NMI */
+        outb(byte, 0x70);
+    }
 	
 	/* Initialize the real time clock */
 	i82801ca_rtc_init(dev);
Index: src/include/assert.h
===================================================================
--- src/include/assert.h	(Revision 2381)
+++ src/include/assert.h	(Arbeitskopie)
@@ -1,59 +1,51 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/assert.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * assert.h: Debugging macros
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: assert.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __ASSERT_H_DEFINED
-#define __ASSERT_H_DEFINED
-
-// ROMCC doesn't support __FILE__ or __LINE__  :^{
-
-#if DEBUG
-#ifdef __ROMCC__
-#define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
-#else
-#define ASSERT(x)	{ 				\
-						if (!(x)) 	\
-						{			\
-							printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
-							die(""); \
-						}			\
-					}
-#endif		// __ROMCC__
-#else		// !DEBUG
-#define ASSERT(x)	{ }
-#endif
-
-#ifdef __ROMCC__
-#define BUG()		{ 	die("BUG encountered: system halted\r\n");  }
-#else
-#define BUG()		{ 				\
-						printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
-						die(""); \
-					}
-#endif
-					
-#endif 	// __ASSERT_H_DEFINED
+/*
+ * assert.h: Debugging macros
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASSERT_H_DEFINED
+#define __ASSERT_H_DEFINED
+
+// ROMCC doesn't support __FILE__ or __LINE__  :^{
+
+#if DEBUG
+#ifdef __ROMCC__
+#define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
+#else
+#define ASSERT(x)	{ 				\
+						if (!(x)) 	\
+						{			\
+							printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
+							die(""); \
+						}			\
+					}
+#endif		// __ROMCC__
+#else		// !DEBUG
+#define ASSERT(x)	{ }
+#endif
+
+#ifdef __ROMCC__
+#define BUG()		{ 	die("BUG encountered: system halted\r\n");  }
+#else
+#define BUG()		{ 				\
+						printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
+						die(""); \
+					}
+#endif
+					
+#endif 	// __ASSERT_H_DEFINED
Index: src/include/sdram_mode.h
===================================================================
--- src/include/sdram_mode.h	(Revision 2381)
+++ src/include/sdram_mode.h	(Arbeitskopie)
@@ -1,62 +1,53 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/sdram_mode.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
- *				 
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: sdram_mode.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __SDRAMMODE_H_DEFINED
-#define __SDRAMMODE_H_DEFINED
-
-// SDRAM Mode Register definitions, per JESD79D
-// These are transmitted via A0-A13
-
-// Burst length
-#define SDRAM_BURST_2     (1<<0)
-#define SDRAM_BURST_4     (2<<0)
-#define SDRAM_BURST_8     (3<<0)
-
-#define SDRAM_BURST_SEQUENTIAL  (0<<3)
-#define SDRAM_BURST_INTERLEAVED	(1<<3)
-
-#define SDRAM_CAS_2_0	  (2<<4)
-#define SDRAM_CAS_3_0     (3<<4)	/* Optional for DDR 200-333 */
-#define SDRAM_CAS_1_5     (5<<4)	/* Optional */
-#define SDRAM_CAS_2_5     (6<<4)
-#define SDRAM_CAS_MASK    (7<<4)
-
-#define SDRAM_MODE_NORMAL		(0 << 7)
-#define SDRAM_MODE_TEST         (1 << 7)
-#define SDRAM_MODE_DLL_RESET    (2 << 7)
-
-// Extended Mode Register
-
-#define SDRAM_EXTMODE_DLL_ENABLE	(0 << 0)
-#define SDRAM_EXTMODE_DLL_DISABLE	(1 << 0)
-
-#define SDRAM_EXTMODE_DRIVE_NORMAL	(0 << 1)
-#define SDRAM_EXTMODE_DRIVE_WEAK	(1 << 1)	/* Optional */
-
-#endif 	// __SDRAMMODE_H_DEFINED
+/*
+ * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SDRAMMODE_H_DEFINED
+#define __SDRAMMODE_H_DEFINED
+
+// SDRAM Mode Register definitions, per JESD79D
+// These are transmitted via A0-A13
+
+// Burst length
+#define SDRAM_BURST_2     (1<<0)
+#define SDRAM_BURST_4     (2<<0)
+#define SDRAM_BURST_8     (3<<0)
+
+#define SDRAM_BURST_SEQUENTIAL  (0<<3)
+#define SDRAM_BURST_INTERLEAVED	(1<<3)
+
+#define SDRAM_CAS_2_0	  (2<<4)
+#define SDRAM_CAS_3_0     (3<<4)	/* Optional for DDR 200-333 */
+#define SDRAM_CAS_1_5     (5<<4)	/* Optional */
+#define SDRAM_CAS_2_5     (6<<4)
+#define SDRAM_CAS_MASK    (7<<4)
+
+#define SDRAM_MODE_NORMAL		(0 << 7)
+#define SDRAM_MODE_TEST         (1 << 7)
+#define SDRAM_MODE_DLL_RESET    (2 << 7)
+
+// Extended Mode Register
+
+#define SDRAM_EXTMODE_DLL_ENABLE	(0 << 0)
+#define SDRAM_EXTMODE_DLL_DISABLE	(1 << 0)
+
+#define SDRAM_EXTMODE_DRIVE_NORMAL	(0 << 1)
+#define SDRAM_EXTMODE_DRIVE_WEAK	(1 << 1)	/* Optional */
+
+#endif 	// __SDRAMMODE_H_DEFINED
Index: src/include/spd.h
===================================================================
--- src/include/spd.h	(Revision 2381)
+++ src/include/spd.h	(Arbeitskopie)
@@ -1,89 +1,81 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/spd.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * spd.h: Definitions for Serial Presence Detect (SPD) data
- *		  stored on SDRAM modules
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: spd.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __SPD_H_DEFINED
-#define __SPD_H_DEFINED
-
-// Byte numbers
-#define SPD_MEMORY_TYPE							 2
-#define SPD_NUM_ROWS							 3
-#define SPD_NUM_COLUMNS							 4
-#define SPD_NUM_DIMM_BANKS						 5
-#define SPD_MODULE_DATA_WIDTH_LSB				 6
-#define SPD_MODULE_DATA_WIDTH_MSB				 7
-#define SPD_MODULE_VOLTAGE						 8
-#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX			 9
-#define SPD_DIMM_CONFIG_TYPE					11
-#define	SPD_REFRESH								12
-#define SPD_PRIMARY_DRAM_WIDTH					13
-#define SPD_SUPPORTED_BURST_LENGTHS				16
-#define SPD_NUM_BANKS_PER_DRAM					17
-#define SPD_ACCEPTABLE_CAS_LATENCIES			18
-#define SPD_MODULE_ATTRIBUTES					21
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05	23
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10	25
-#define SPD_MIN_ROW_PRECHARGE_TIME				27
-#define SPD_MIN_RAS_TO_CAS_DELAY				29
-#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY		30
-#define SPD_ADDRESS_CMD_HOLD					33
-
-
-// SPD_MEMORY_TYPE values
-#define MEMORY_TYPE_SDRAM_DDR	7
-
-// SPD_MODULE_VOLTAGE values
-#define SPD_VOLTAGE_SSTL2		4
-
-// SPD_DIMM_CONFIG_TYPE values
-#define ERROR_SCHEME_NONE		0
-#define ERROR_SCHEME_PARITY		1
-#define ERROR_SCHEME_ECC		2
-
-// SPD_ACCEPTABLE_CAS_LATENCIES values
-#define SPD_CAS_LATENCY_1_0		0x01
-#define SPD_CAS_LATENCY_1_5		0x02
-#define SPD_CAS_LATENCY_2_0		0x04
-#define SPD_CAS_LATENCY_2_5		0x08
-#define SPD_CAS_LATENCY_3_0		0x10
-#define SPD_CAS_LATENCY_3_5		0x20
-#define SPD_CAS_LATENCY_4_0		0x40
-
-// SPD_SUPPORTED_BURST_LENGTHS values
-#define SPD_BURST_LENGTH_1		1
-#define SPD_BURST_LENGTH_2		2
-#define SPD_BURST_LENGTH_4		4
-#define SPD_BURST_LENGTH_8		8
-#define SPD_BURST_LENGTH_PAGE	(1<<7)
-
-
-// SPD_MODULE_ATTRIBUTES values
-#define MODULE_BUFFERED			1
-#define MODULE_REGISTERED		2
-
-#endif 	// __SPD_H_DEFINED
+/*
+ * spd.h: Definitions for Serial Presence Detect (SPD) data
+ *		  stored on SDRAM modules
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SPD_H_DEFINED
+#define __SPD_H_DEFINED
+
+// Byte numbers
+#define SPD_MEMORY_TYPE							 2
+#define SPD_NUM_ROWS							 3
+#define SPD_NUM_COLUMNS							 4
+#define SPD_NUM_DIMM_BANKS						 5
+#define SPD_MODULE_DATA_WIDTH_LSB				 6
+#define SPD_MODULE_DATA_WIDTH_MSB				 7
+#define SPD_MODULE_VOLTAGE						 8
+#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX			 9
+#define SPD_DIMM_CONFIG_TYPE					11
+#define	SPD_REFRESH								12
+#define SPD_PRIMARY_DRAM_WIDTH					13
+#define SPD_SUPPORTED_BURST_LENGTHS				16
+#define SPD_NUM_BANKS_PER_DRAM					17
+#define SPD_ACCEPTABLE_CAS_LATENCIES			18
+#define SPD_MODULE_ATTRIBUTES					21
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05	23
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10	25
+#define SPD_MIN_ROW_PRECHARGE_TIME				27
+#define SPD_MIN_RAS_TO_CAS_DELAY				29
+#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY		30
+#define SPD_ADDRESS_CMD_HOLD					33
+
+
+// SPD_MEMORY_TYPE values
+#define MEMORY_TYPE_SDRAM_DDR	7
+
+// SPD_MODULE_VOLTAGE values
+#define SPD_VOLTAGE_SSTL2		4
+
+// SPD_DIMM_CONFIG_TYPE values
+#define ERROR_SCHEME_NONE		0
+#define ERROR_SCHEME_PARITY		1
+#define ERROR_SCHEME_ECC		2
+
+// SPD_ACCEPTABLE_CAS_LATENCIES values
+#define SPD_CAS_LATENCY_1_0		0x01
+#define SPD_CAS_LATENCY_1_5		0x02
+#define SPD_CAS_LATENCY_2_0		0x04
+#define SPD_CAS_LATENCY_2_5		0x08
+#define SPD_CAS_LATENCY_3_0		0x10
+#define SPD_CAS_LATENCY_3_5		0x20
+#define SPD_CAS_LATENCY_4_0		0x40
+
+// SPD_SUPPORTED_BURST_LENGTHS values
+#define SPD_BURST_LENGTH_1		1
+#define SPD_BURST_LENGTH_2		2
+#define SPD_BURST_LENGTH_4		4
+#define SPD_BURST_LENGTH_8		8
+#define SPD_BURST_LENGTH_PAGE	(1<<7)
+
+
+// SPD_MODULE_ATTRIBUTES values
+#define MODULE_BUFFERED			1
+#define MODULE_REGISTERED		2
+
+#endif 	// __SPD_H_DEFINED
Index: src/superio/smsc/lpc47m10x/superio.c
===================================================================
--- src/superio/smsc/lpc47m10x/superio.c	(Revision 2381)
+++ src/superio/smsc/lpc47m10x/superio.c	(Arbeitskopie)
@@ -1,6 +1,4 @@
 /*
- * $Header$
- *
  * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
  *
  * Copyright 2000  AG Electronics Ltd.
@@ -22,9 +20,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
  */
 
 #include <arch/io.h>
Index: src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
===================================================================
--- src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c	(Revision 2381)
+++ src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c	(Arbeitskopie)
@@ -1,63 +1,58 @@
-/*
- * $Header$
- *
- * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
+/*
+ * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
  * derived from lpc47n217
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/romcc_io.h>
 #include "lpc47m10x.h"
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47M10X2's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47M10X2's configuration registers.
+//
 static inline void pnp_enter_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0x55, port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47M10X2's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47M10X2's configuration registers.
+//
 static void pnp_exit_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0xaa, port);
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47b272.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47b272.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
 static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_conf_state(dev);
Index: src/superio/smsc/lpc47n217/superio.c
===================================================================
--- src/superio/smsc/lpc47n217/superio.c	(Revision 2381)
+++ src/superio/smsc/lpc47n217/superio.c	(Arbeitskopie)
@@ -1,394 +1,386 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/superio.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $
- *
- * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
- *
- * Based on LinuxBIOS code for SMSC 47B397:
- * Copyright 2000  AG Electronics Ltd.
- * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan 
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: superio.c,v $
- * Revision 1.1.1.1  2005/07/11 15:28:51  smagnani
- * Initial revision.
- *
- *
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pnp.h>
-#include <console/console.h>
-#include <device/smbus.h>
-#include <string.h>
-#include <bitops.h>
-#include <uart8250.h>
-#include <assert.h>
-#include "chip.h"
-#include "lpc47n217.h"
-
-// Forward declarations
-static void enable_dev(device_t dev);
-void lpc47n217_pnp_set_resources(device_t dev);
-void lpc47n217_pnp_enable_resources(device_t dev);
-void lpc47n217_pnp_enable(device_t dev);
-static void lpc47n217_init(device_t dev);
-
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
-void lpc47n217_pnp_set_enable(device_t dev, int enable);
-
-static void pnp_enter_conf_state(device_t dev);
-static void pnp_exit_conf_state(device_t dev);
-
-
-struct chip_operations superio_smsc_lpc47n217_ops = {
-	CHIP_NAME("smsc lpc47n217")
-	.enable_dev = enable_dev,
-};
-
-static struct device_operations ops = {
-	.read_resources   = pnp_read_resources,
-	.set_resources    = lpc47n217_pnp_set_resources,
-	.enable_resources = lpc47n217_pnp_enable_resources,
-	.enable           = lpc47n217_pnp_enable,
-	.init             = lpc47n217_init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
-        { &ops, LPC47N217_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &ops, LPC47N217_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, LPC47N217_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
-};
-
-/**********************************************************************************/
-/*								PUBLIC INTERFACE								  */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function:    	enable_dev
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Create device structures and allocate resources to devices 
-//					specified in the pnp_dev_info array (above).
-//
-static void enable_dev(device_t dev)
-{
-	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
-					   pnp_dev_info);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_resources
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Configure the specified Super I/O device with the resources
-//					(I/O space, etc.) that have been allocate for it.
-//
-void lpc47n217_pnp_set_resources(device_t dev)
-{
-	int i;
-	
-	pnp_enter_conf_state(dev);  
-
-	// NOTE: Cannot use pnp_set_resources() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-	for(i = 0; i < dev->resources; i++)
-		lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
-
-//	dump_pnp_device(dev);
-                
-   	pnp_exit_conf_state(dev);  
-}       
-
-void lpc47n217_pnp_enable_resources(device_t dev)
-{       
-    pnp_enter_conf_state(dev);
-
-	// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-    lpc47n217_pnp_set_enable(dev, 1);
-
-    pnp_exit_conf_state(dev);
-}
-
-void lpc47n217_pnp_enable(device_t dev)
-{
-	pnp_enter_conf_state(dev);   
-
-	// NOTE: Cannot use pnp_set_enable() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-
-	if(dev->enabled) {
-		lpc47n217_pnp_set_enable(dev, 1);
-	}
-	else {
-		lpc47n217_pnp_set_enable(dev, 0);
-	}
-
-	pnp_exit_conf_state(dev);  
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_init
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Initialize the specified Super I/O device.
-//					Devices other than COM ports are ignored.
-//					For COM ports, we configure the baud rate. 
-//
-static void lpc47n217_init(device_t dev)
-{
-	struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
-	struct resource *res0;
-
-	if (!dev->enabled)
-		return;
-
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_SP1: 
-		res0 = find_resource(dev, PNP_IDX_IO0);
-		init_uart8250(res0->base, &conf->com1);
-		break;
-
-	case LPC47N217_SP2:
-		res0 = find_resource(dev, PNP_IDX_IO0);
-		init_uart8250(res0->base, &conf->com2);
-		break;
-	}
-}
-
-
-/**********************************************************************************/
-/*								PRIVATE FUNCTIONS							      */
-/**********************************************************************************/
-
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
-{
-	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02x not allocated\n",
-			dev_path(dev), resource->index);
-		return;
-	}
-
-	/* Now store the resource */
-	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-
-	if (resource->flags & IORESOURCE_IO) {
-		lpc47n217_pnp_set_iobase(dev, resource->base);
-	}
-	else if (resource->flags & IORESOURCE_DRQ) {
-		lpc47n217_pnp_set_drq(dev, resource->base);
-	}
-	else if (resource->flags  & IORESOURCE_IRQ) {
-		lpc47n217_pnp_set_irq(dev, resource->base);
-	}
-	else {
-		printk_err("ERROR: %s %02x unknown resource type\n",
-			dev_path(dev), resource->index);
-		return;
-	}
-	resource->flags |= IORESOURCE_STORED;
-
-	report_resource_stored(dev, resource, "");
-}
-
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
-{
-	ASSERT(!(iobase & 0x3));
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP1: 
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-		
-	default:
-		BUG();
-		break;
-	}
-}
-
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
-{
-	if (dev->path.u.pnp.device == LPC47N217_PP) {
-		const uint8_t PP_DMA_MASK = 0x0F;
-		const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
-		uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
-		uint8_t new_config;
-
-		ASSERT(!(drq & ~PP_DMA_MASK));		// DRQ out of range??		
-		new_config = (current_config & ~PP_DMA_MASK) | drq;
-		pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
-	} else {
-		BUG();
-	}
-}
-
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
-{
-	uint8_t irq_config_register = 0;
-	uint8_t irq_config_mask = 0;
-	uint8_t current_config;
-	uint8_t new_config;
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		irq_config_register = 0x27;
-		irq_config_mask = 0x0F;
-		break;
-		
-	case LPC47N217_SP1: 
-		irq_config_register = 0x28;
-		irq_config_mask = 0xF0;
-		irq <<= 4;
-		break;
-		
-	case LPC47N217_SP2:
-		irq_config_register = 0x28;
-		irq_config_mask = 0x0F;
-		break;
-		
-	default:
-		BUG();
-		return;
-	}
-
-	ASSERT(!(irq & ~irq_config_mask));		// IRQ out of range??
-	
-	current_config = pnp_read_config(dev, irq_config_register);
-	new_config = (current_config & ~irq_config_mask) | irq;
-	pnp_write_config(dev, irq_config_register, new_config);
-}
-
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
-	uint8_t power_register = 0;
-	uint8_t power_mask = 0;
-	uint8_t current_power;
-	uint8_t new_power;
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-		
-	case LPC47N217_SP1: 
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-		
-	case LPC47N217_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-		
-	default:
-		BUG();
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask;		// disable by default
-
-	if (enable) {
-		struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
-		lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
-		
-		new_power |= power_mask;		// Enable
-		
-    } else {
-		lpc47n217_pnp_set_iobase(dev, 0);
-	}
-	pnp_write_config(dev, power_register, new_power);
-}
-
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Enable access to the LPC47N217's configuration registers.
-//
-static void pnp_enter_conf_state(device_t dev) 
-{
-	outb(0x55, dev->path.u.pnp.port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Disable access to the LPC47N217's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) 
-{
-    outb(0xaa, dev->path.u.pnp.port);
-}
-
-#if 0
-//----------------------------------------------------------------------------------
-// Function:    	dump_pnp_device
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Print the values of all of the LPC47N217's configuration registers.
-//					NOTE: The LPC47N217 must be in configuration mode when this
-//						  function is called.
-//
-static void dump_pnp_device(device_t dev)
-{
-    int register_index;
-    print_debug("\r\n");
-
-    for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
-        uint8_t register_value;
-
-        if ((register_index & 0x0f) == 0) {
-                print_debug_hex8(register_index);
-                print_debug_char(':');
-        }
-
-		// Skip over 'register' that would cause exit from configuration mode
-	    if (register_index == 0xaa)
-			register_value = 0xaa;
-		else
-        	register_value = pnp_read_config(dev, register_index);
-
-        print_debug_char(' ');
-        print_debug_hex8(register_value);
-        if ((register_index & 0x0f) == 0x0f) {
-        	print_debug("\r\n");
-        }
-    }
-
-   	print_debug("\r\n");
-}
-#endif
+/*
+ * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Based on LinuxBIOS code for SMSC 47B397:
+ * Copyright 2000  AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan 
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <assert.h>
+#include "chip.h"
+#include "lpc47n217.h"
+
+// Forward declarations
+static void enable_dev(device_t dev);
+void lpc47n217_pnp_set_resources(device_t dev);
+void lpc47n217_pnp_enable_resources(device_t dev);
+void lpc47n217_pnp_enable(device_t dev);
+static void lpc47n217_init(device_t dev);
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
+void lpc47n217_pnp_set_enable(device_t dev, int enable);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+
+struct chip_operations superio_smsc_lpc47n217_ops = {
+	CHIP_NAME("smsc lpc47n217")
+	.enable_dev = enable_dev,
+};
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = lpc47n217_pnp_set_resources,
+	.enable_resources = lpc47n217_pnp_enable_resources,
+	.enable           = lpc47n217_pnp_enable,
+	.init             = lpc47n217_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+        { &ops, LPC47N217_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+        { &ops, LPC47N217_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+        { &ops, LPC47N217_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
+};
+
+/**********************************************************************************/
+/*								PUBLIC INTERFACE								  */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	enable_dev
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Create device structures and allocate resources to devices 
+//					specified in the pnp_dev_info array (above).
+//
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, 
+					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_resources
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Configure the specified Super I/O device with the resources
+//					(I/O space, etc.) that have been allocate for it.
+//
+void lpc47n217_pnp_set_resources(device_t dev)
+{
+	int i;
+	
+	pnp_enter_conf_state(dev);  
+
+	// NOTE: Cannot use pnp_set_resources() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+	for(i = 0; i < dev->resources; i++)
+		lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
+
+//	dump_pnp_device(dev);
+                
+   	pnp_exit_conf_state(dev);  
+}       
+
+void lpc47n217_pnp_enable_resources(device_t dev)
+{       
+    pnp_enter_conf_state(dev);
+
+	// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+    lpc47n217_pnp_set_enable(dev, 1);
+
+    pnp_exit_conf_state(dev);
+}
+
+void lpc47n217_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);   
+
+	// NOTE: Cannot use pnp_set_enable() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+
+	if(dev->enabled) {
+		lpc47n217_pnp_set_enable(dev, 1);
+	}
+	else {
+		lpc47n217_pnp_set_enable(dev, 0);
+	}
+
+	pnp_exit_conf_state(dev);  
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_init
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Initialize the specified Super I/O device.
+//					Devices other than COM ports are ignored.
+//					For COM ports, we configure the baud rate. 
+//
+static void lpc47n217_init(device_t dev)
+{
+	struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_SP1: 
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+
+	case LPC47N217_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	}
+}
+
+
+/**********************************************************************************/
+/*								PRIVATE FUNCTIONS							      */
+/**********************************************************************************/
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
+{
+	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		printk_err("ERROR: %s %02x not allocated\n",
+			dev_path(dev), resource->index);
+		return;
+	}
+
+	/* Now store the resource */
+	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+
+	if (resource->flags & IORESOURCE_IO) {
+		lpc47n217_pnp_set_iobase(dev, resource->base);
+	}
+	else if (resource->flags & IORESOURCE_DRQ) {
+		lpc47n217_pnp_set_drq(dev, resource->base);
+	}
+	else if (resource->flags  & IORESOURCE_IRQ) {
+		lpc47n217_pnp_set_irq(dev, resource->base);
+	}
+	else {
+		printk_err("ERROR: %s %02x unknown resource type\n",
+			dev_path(dev), resource->index);
+		return;
+	}
+	resource->flags |= IORESOURCE_STORED;
+
+	report_resource_stored(dev, resource, "");
+}
+
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+	ASSERT(!(iobase & 0x3));
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP1: 
+		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP2:
+		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+		break;
+		
+	default:
+		BUG();
+		break;
+	}
+}
+
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
+{
+	if (dev->path.u.pnp.device == LPC47N217_PP) {
+		const uint8_t PP_DMA_MASK = 0x0F;
+		const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
+		uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
+		uint8_t new_config;
+
+		ASSERT(!(drq & ~PP_DMA_MASK));		// DRQ out of range??		
+		new_config = (current_config & ~PP_DMA_MASK) | drq;
+		pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
+	} else {
+		BUG();
+	}
+}
+
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
+{
+	uint8_t irq_config_register = 0;
+	uint8_t irq_config_mask = 0;
+	uint8_t current_config;
+	uint8_t new_config;
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		irq_config_register = 0x27;
+		irq_config_mask = 0x0F;
+		break;
+		
+	case LPC47N217_SP1: 
+		irq_config_register = 0x28;
+		irq_config_mask = 0xF0;
+		irq <<= 4;
+		break;
+		
+	case LPC47N217_SP2:
+		irq_config_register = 0x28;
+		irq_config_mask = 0x0F;
+		break;
+		
+	default:
+		BUG();
+		return;
+	}
+
+	ASSERT(!(irq & ~irq_config_mask));		// IRQ out of range??
+	
+	current_config = pnp_read_config(dev, irq_config_register);
+	new_config = (current_config & ~irq_config_mask) | irq;
+	pnp_write_config(dev, irq_config_register, new_config);
+}
+
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+	uint8_t power_register = 0;
+	uint8_t power_mask = 0;
+	uint8_t current_power;
+	uint8_t new_power;
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		power_register = 0x01;
+		power_mask = 0x04;
+		break;
+		
+	case LPC47N217_SP1: 
+		power_register = 0x02;
+		power_mask = 0x08;
+		break;
+		
+	case LPC47N217_SP2:
+		power_register = 0x02;
+		power_mask = 0x80;
+		break;
+		
+	default:
+		BUG();
+		return;
+	}
+
+	current_power = pnp_read_config(dev, power_register);
+	new_power = current_power & ~power_mask;		// disable by default
+
+	if (enable) {
+		struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
+		lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
+		
+		new_power |= power_mask;		// Enable
+		
+    } else {
+		lpc47n217_pnp_set_iobase(dev, 0);
+	}
+	pnp_write_config(dev, power_register, new_power);
+}
+
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Enable access to the LPC47N217's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev) 
+{
+	outb(0x55, dev->path.u.pnp.port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) 
+{
+    outb(0xaa, dev->path.u.pnp.port);
+}
+
+#if 0
+//----------------------------------------------------------------------------------
+// Function:    	dump_pnp_device
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Print the values of all of the LPC47N217's configuration registers.
+//					NOTE: The LPC47N217 must be in configuration mode when this
+//						  function is called.
+//
+static void dump_pnp_device(device_t dev)
+{
+    int register_index;
+    print_debug("\r\n");
+
+    for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
+        uint8_t register_value;
+
+        if ((register_index & 0x0f) == 0) {
+                print_debug_hex8(register_index);
+                print_debug_char(':');
+        }
+
+		// Skip over 'register' that would cause exit from configuration mode
+	    if (register_index == 0xaa)
+			register_value = 0xaa;
+		else
+        	register_value = pnp_read_config(dev, register_index);
+
+        print_debug_char(' ');
+        print_debug_hex8(register_value);
+        if ((register_index & 0x0f) == 0x0f) {
+        	print_debug("\r\n");
+        }
+    }
+
+   	print_debug("\r\n");
+}
+#endif
Index: src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
===================================================================
--- src/superio/smsc/lpc47n217/lpc47n217_early_serial.c	(Revision 2381)
+++ src/superio/smsc/lpc47n217/lpc47n217_early_serial.c	(Arbeitskopie)
@@ -1,155 +1,147 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $
- *
- * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: lpc47n217_early_serial.c,v $
- * Revision 1.1.1.1  2005/07/11 15:28:51  smagnani
- * Initial revision.
- *
- *
- */
-
-#include <arch/romcc_io.h>
-#include <assert.h>
-#include "lpc47n217.h"
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47N217's configuration registers.
-//
-static inline void pnp_enter_conf_state(device_t dev) {
-	unsigned port = dev>>8;
-    outb(0x55, port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47N217's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) {
-	unsigned port = dev>>8;
-    outb(0xaa, port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_iobase
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					iobase - base I/O port for the logical device
-// Return Value:	None
-// Description: 	Program the base I/O port for the specified logical device.
-//
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
-{
-	// LPC47N217 requires base ports to be a multiple of 4
-	ASSERT(!(iobase & 0x3));
-
-	switch(dev & 0xFF) {
-	case LPC47N217_PP: 
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP1: 
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-		
-	default:
-		break;
-	}
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_enable
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					enable - 0 to disable, anythig else to enable
-// Return Value:	None
-// Description: 	Enable or disable the specified logical device.
-//					Technically, a full disable requires setting the device's base
-//					I/O port below 0x100. We don't do that here, because we don't
-//					have access to a data structure that specifies what the 'real'
-//					base port is (when asked to enable the device). Also the function
-//					is used only to disable the device while its true base port is
-//					programmed (see lpc47n217_enable_serial() below).
-//
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
-	uint8_t power_register = 0;
-	uint8_t power_mask = 0;
-	uint8_t current_power;
-	uint8_t new_power;
-	
-	switch(dev & 0xFF) {
-	case LPC47N217_PP: 
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-		
-	case LPC47N217_SP1: 
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-		
-	case LPC47N217_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-		
-	default:
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask;		// disable by default
-
-	if (enable)
-		new_power |= power_mask;		// Enable
-
-	pnp_write_config(dev, power_register, new_power);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
-static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
-{
-	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-	
-	pnp_enter_conf_state(dev);
-	lpc47n217_pnp_set_enable(dev, 0);
-	lpc47n217_pnp_set_iobase(dev, iobase);
-	lpc47n217_pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
+/*
+ * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <arch/romcc_io.h>
+#include <assert.h>
+#include "lpc47n217.h"
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47N217's configuration registers.
+//
+static inline void pnp_enter_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0x55, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0xaa, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_iobase
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					iobase - base I/O port for the logical device
+// Return Value:	None
+// Description: 	Program the base I/O port for the specified logical device.
+//
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+	// LPC47N217 requires base ports to be a multiple of 4
+	ASSERT(!(iobase & 0x3));
+
+	switch(dev & 0xFF) {
+	case LPC47N217_PP: 
+		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP1: 
+		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP2:
+		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+		break;
+		
+	default:
+		break;
+	}
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_enable
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					enable - 0 to disable, anythig else to enable
+// Return Value:	None
+// Description: 	Enable or disable the specified logical device.
+//					Technically, a full disable requires setting the device's base
+//					I/O port below 0x100. We don't do that here, because we don't
+//					have access to a data structure that specifies what the 'real'
+//					base port is (when asked to enable the device). Also the function
+//					is used only to disable the device while its true base port is
+//					programmed (see lpc47n217_enable_serial() below).
+//
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+	uint8_t power_register = 0;
+	uint8_t power_mask = 0;
+	uint8_t current_power;
+	uint8_t new_power;
+	
+	switch(dev & 0xFF) {
+	case LPC47N217_PP: 
+		power_register = 0x01;
+		power_mask = 0x04;
+		break;
+		
+	case LPC47N217_SP1: 
+		power_register = 0x02;
+		power_mask = 0x08;
+		break;
+		
+	case LPC47N217_SP2:
+		power_register = 0x02;
+		power_mask = 0x80;
+		break;
+		
+	default:
+		return;
+	}
+
+	current_power = pnp_read_config(dev, power_register);
+	new_power = current_power & ~power_mask;		// disable by default
+
+	if (enable)
+		new_power |= power_mask;		// Enable
+
+	pnp_write_config(dev, power_register, new_power);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
+static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
+{
+	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+	
+	pnp_enter_conf_state(dev);
+	lpc47n217_pnp_set_enable(dev, 0);
+	lpc47n217_pnp_set_iobase(dev, iobase);
+	lpc47n217_pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}
Index: src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
===================================================================
--- src/superio/smsc/lpc47b272/lpc47b272_early_serial.c	(Revision 2381)
+++ src/superio/smsc/lpc47b272/lpc47b272_early_serial.c	(Arbeitskopie)
@@ -1,62 +1,57 @@
-/*
- * $Header$
- *
- * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+/*
+ * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/romcc_io.h>
 #include "lpc47b272.h"
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47B272's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47B272's configuration registers.
+//
 static inline void pnp_enter_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0x55, port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47B272's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47B272's configuration registers.
+//
 static void pnp_exit_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0xaa, port);
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47b272.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47b272.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
 static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_conf_state(dev);
Index: src/superio/smsc/lpc47b272/superio.c
===================================================================
--- src/superio/smsc/lpc47b272/superio.c	(Revision 2381)
+++ src/superio/smsc/lpc47b272/superio.c	(Arbeitskopie)
@@ -1,30 +1,25 @@
-/*
- * $Header$
- *
- * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
- *
+/*
+ * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
+ *
  * Copyright 2000  AG Electronics Ltd.
  * Copyright 2003-2004 Linux Networx
  * Copyright 2004 Tyan 
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/io.h>
 #include <device/device.h>
@@ -38,16 +33,16 @@
 #include "chip.h"
 #include "lpc47b272.h"
 
-// Forward declarations
-static void enable_dev(device_t dev);
+// Forward declarations
+static void enable_dev(device_t dev);
 void lpc47b272_pnp_set_resources(device_t dev);
 void lpc47b272_pnp_set_resources(device_t dev);
 void lpc47b272_pnp_enable_resources(device_t dev);
 void lpc47b272_pnp_enable(device_t dev);
 static void lpc47b272_init(device_t dev);
 
-static void pnp_enter_conf_state(device_t dev);
-static void pnp_exit_conf_state(device_t dev);
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
 static void dump_pnp_device(device_t dev);
 
 
@@ -73,31 +68,31 @@
         { &ops, LPC47B272_RT,   PNP_IO0, { 0x780, 0 }, },
 };
 
-/**********************************************************************************/
-/*								PUBLIC INTERFACE								  */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function:    	enable_dev
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Create device structures and allocate resources to devices 
-//					specified in the pnp_dev_info array (above).
-//
-static void enable_dev(device_t dev)
-{
-	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
-					   pnp_dev_info);
-}
+/**********************************************************************************/
+/*								PUBLIC INTERFACE								  */
+/**********************************************************************************/
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_pnp_set_resources
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Configure the specified Super I/O device with the resources
-//					(I/O space, etc.) that have been allocated for it.
+//----------------------------------------------------------------------------------
+// Function:    	enable_dev
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Create device structures and allocate resources to devices 
+//					specified in the pnp_dev_info array (above).
 //
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, 
+					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_pnp_set_resources
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Configure the specified Super I/O device with the resources
+//					(I/O space, etc.) that have been allocated for it.
+//
 void lpc47b272_pnp_set_resources(device_t dev)
 {
 	pnp_enter_conf_state(dev);  
@@ -126,14 +121,14 @@
 	pnp_exit_conf_state(dev);  
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_init
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Initialize the specified Super I/O device.
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_init
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Initialize the specified Super I/O device.
 //					Devices other than COM ports and the keyboard controller are 
-//					ignored. For COM ports, we configure the baud rate. 
-//
+//					ignored. For COM ports, we configure the baud rate. 
+//
 static void lpc47b272_init(device_t dev)
 {
 	struct superio_smsc_lpc47b272_config *conf = dev->chip_info;
@@ -160,68 +155,68 @@
 		break;
 	}
 }
-
-/**********************************************************************************/
-/*								PRIVATE FUNCTIONS							      */
-/**********************************************************************************/
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Enable access to the LPC47B272's configuration registers.
-//
-static void pnp_enter_conf_state(device_t dev) 
+/**********************************************************************************/
+/*								PRIVATE FUNCTIONS							      */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Enable access to the LPC47B272's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev) 
 {
 	outb(0x55, dev->path.u.pnp.port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Disable access to the LPC47B272's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) 
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Disable access to the LPC47B272's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) 
 {
     outb(0xaa, dev->path.u.pnp.port);
 }
 
 #if 0
-//----------------------------------------------------------------------------------
-// Function:    	dump_pnp_device
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Print the values of all of the LPC47B272's configuration registers.
-//					NOTE: The LPC47B272 must be in configuration mode when this
-//						  function is called.
-//
+//----------------------------------------------------------------------------------
+// Function:    	dump_pnp_device
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Print the values of all of the LPC47B272's configuration registers.
+//					NOTE: The LPC47B272 must be in configuration mode when this
+//						  function is called.
+//
 static void dump_pnp_device(device_t dev)
 {
     int register_index;
     print_debug("\r\n");
 
     for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
-        uint8_t register_value;
+        uint8_t register_value;
 
         if ((register_index & 0x0f) == 0) {
                 print_debug_hex8(register_index);
                 print_debug_char(':');
-        }
-
+        }
+
 		// Skip over 'register' that would cause exit from configuration mode
 	    if (register_index == 0xaa)
-			register_value = 0xaa;
+			register_value = 0xaa;
 		else
-        	register_value = pnp_read_config(dev, register_index);
-
+        	register_value = pnp_read_config(dev, register_index);
+
         print_debug_char(' ');
         print_debug_hex8(register_value);
         if ((register_index & 0x0f) == 0x0f) {
         	print_debug("\r\n");
         }
-    }
-
-   	print_debug("\r\n");
+    }
+
+   	print_debug("\r\n");
 }
 #endif
Index: src/northbridge/intel/e7501/e7501.h
===================================================================
--- src/northbridge/intel/e7501/e7501.h	(Revision 2381)
+++ src/northbridge/intel/e7501/e7501.h	(Arbeitskopie)
@@ -1,6 +1,4 @@
 /*
- * $Header$
- *
  * e7501.h: PCI configuration space for the Intel E7501 memory controller
  *
  * Copyright (C) 2005 Digital Design Corporation
@@ -18,9 +16,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
  */
 
 
Index: targets/intel/xe7501devkit/Config.lb
===================================================================
--- targets/intel/xe7501devkit/Config.lb	(Revision 2381)
+++ targets/intel/xe7501devkit/Config.lb	(Arbeitskopie)
@@ -1,37 +1,38 @@
-target xe7501devkit
-mainboard intel/xe7501devkit
-
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
-## (normal AND fallback images and payloads).
-option ROM_SIZE = 0x30000
-
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
-## not including any payload.
-option ROM_IMAGE_SIZE = 0x1B000
-
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image 
-## (including payload) will use
-option FALLBACK_SIZE = 0
-
-
-
-romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-#	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../../../../../memtest86/memtest
-#       payload ../../../../../../../etherboot/src/bin/e1000.zelf
-        payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
-#       payload ../../../../../../../QNX/BSP/images/qnxbasesmp.elf
-end
-
-#NOTE: CMOS currently not supported due to conflicts with factory BIOS
-#      Thus no support for fallback boot.
-#romimage "fallback" 
-#	option USE_FALLBACK_IMAGE=1
-#	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../../../../../memtest86/memtest
-#       payload ../../../../../../../etherboot/src/bin/e1000.zelf
-#       payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
-#end
-
-buildrom ./linuxbios.rom ROM_SIZE "normal"
+target xe7501devkit
+mainboard intel/xe7501devkit
+
+## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
+## (normal AND fallback images and payloads).
+option ROM_SIZE = 0x30000
+
+## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
+## not including any payload.
+option ROM_IMAGE_SIZE = 0x1B000
+
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image 
+## (including payload) will use
+option FALLBACK_SIZE = 0
+
+
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE=0
+#	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+#       payload ../../../../../../../memtest86/memtest
+#       payload ../../../../../../../etherboot/src/bin/e1000.zelf
+        payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
+#       payload ../../../../../../../QNX/BSP/images/qnxbasesmp.elf
+end
+
+#NOTE: CMOS currently not supported due to conflicts with factory BIOS
+#      Thus no support for fallback boot.
+#romimage "fallback" 
+#	option USE_FALLBACK_IMAGE=1
+#	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+#       payload ../../../../../../../memtest86/memtest
+#       payload ../../../../../../../etherboot/src/bin/e1000.zelf
+#       payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
+#end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal"
+
Index: util/flashrom/sst39sf020.c
===================================================================
--- util/flashrom/sst39sf020.c	(Revision 2381)
+++ util/flashrom/sst39sf020.c	(Arbeitskopie)
@@ -23,8 +23,6 @@
  *	4 MEgabit (512K x 8) SuperFlash EEPROM, SST28SF040 data sheet
  *
  * ToDo: Consilidated to standard JEDEC code.
- *
- * $Id$
  */
 
 #include <stdio.h>
Index: util/flashrom/jedec.c
===================================================================
--- util/flashrom/jedec.c	(Revision 2381)
+++ util/flashrom/jedec.c	(Arbeitskopie)
@@ -17,11 +17,6 @@
  *	You should have received a copy of the GNU General Public License
  *	along with this program; if not, write to the Free Software
  *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- * Reference:
- *
- * $Id$
  */
 
 #include <stdio.h>
Index: util/flashrom/sharplhf00l04.c
===================================================================
--- util/flashrom/sharplhf00l04.c	(Revision 2381)
+++ util/flashrom/sharplhf00l04.c	(Arbeitskopie)
@@ -20,8 +20,6 @@
  *
  *
  * Reference: http://www.intel.com/design/chipsets/datashts/290658.htm
- *
- * $Id: lhf00l04.c 2111 2005-11-26 21:55:36Z ollie $
  */
 
 #include <errno.h>
Index: util/flashrom/w49f002u.c
===================================================================
--- util/flashrom/w49f002u.c	(Revision 2381)
+++ util/flashrom/w49f002u.c	(Arbeitskopie)
@@ -23,8 +23,6 @@
  *	W49F002U data sheet
  *
  * ToDo: Consilidated to standard JEDEC code.
- *
- * $Id$
  */
 
 #include <stdio.h>
Index: util/flashrom/82802ab.c
===================================================================
--- util/flashrom/82802ab.c	(Revision 2381)
+++ util/flashrom/82802ab.c	(Arbeitskopie)
@@ -20,8 +20,6 @@
  *
  *
  * Reference: http://www.intel.com/design/chipsets/datashts/290658.htm
- *
- * $Id$
  */
 
 #include <errno.h>
Index: util/flashrom/mx29f002.c
===================================================================
--- util/flashrom/mx29f002.c	(Revision 2381)
+++ util/flashrom/mx29f002.c	(Arbeitskopie)
@@ -21,8 +21,6 @@
  *
  * Reference:
  *	MX29F002/002N data sheet
- *
- * $Id$
  */
 
 #include <stdio.h>
Index: util/flashrom/m29f400bt.c
===================================================================
--- util/flashrom/m29f400bt.c	(Revision 2381)
+++ util/flashrom/m29f400bt.c	(Arbeitskopie)
@@ -17,11 +17,6 @@
  *	You should have received a copy of the GNU General Public License
  *	along with this program; if not, write to the Free Software
  *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- * Reference:
- *
- * $Id$
  */
 
 #include "flash.h"
Index: util/flashrom/sst49lf040.c
===================================================================
--- util/flashrom/sst49lf040.c	(Revision 2381)
+++ util/flashrom/sst49lf040.c	(Arbeitskopie)
@@ -22,8 +22,6 @@
  *      4 MEgabit (512K x 8) SuperFlash EEPROM, SST49lF040 data sheet
  *
  * ToDo: Consilidated to standard JEDEC code.
- *
- * $Id$
  */
 #include <stdio.h>
 #include "flash.h"
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060821/f436e4c5/attachment.sig>

From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug 21 19:16:14 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel U. Hailfinger)
Date: Mon, 21 Aug 2006 19:16:14 +0200
Subject: [LinuxBIOS] OLPC buildsystem cleanups
In-Reply-To: <8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>
References: <20060803231225.81150@gmx.net>	
	<8a0c36780608031915j5c61bbcehe9384281dc362683@mail.gmail.com>	
	<20060804231125.310580@gmx.net>	
	<m13bcbob14.fsf@ebiederm.dsl.xmission.com>	
	<20060820021356.76290@gmx.net>
	<8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>
Message-ID: <20060821171614.230770@gmx.net>

Hi,

the attached patches change the OLPC build system to use relative payload paths instead of using a hardcoded file in /tmp which will sooner or later cause security problems. Additionally, a check for config file correctness has been added so you can't accidentially generate the wrong payload for a given LinuxBIOS config.
I forgot how to invert command return codes in makefiles, so it would be cool if somebody could replace the FIXME in the olpc patch with the inverted grep command of some lines later.

Please note: The buildrom patch can only be applied upstream after teh LinuxBIOS patch has been applied upstream (and the needed svn revision obviously also has to be updated).

Regards,
Carl-Daniel

-- 


"Feel free" ? 10 GB Mailbox, 100 FreeSMS/Monat ...
Jetzt GMX TopMail testen: http://www.gmx.net/de/go/topmail
-------------- next part --------------
A non-text attachment was scrubbed...
Name: linuxbios-relative-payload-02.diff
Type: text/x-patch
Size: 1025 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060821/14399c35/attachment.diff>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: olpc-relative-payload-03.diff
Type: text/x-patch
Size: 2173 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060821/14399c35/attachment-0001.diff>

From stepan at coresystems.de  Mon Aug 21 19:22:26 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 21 Aug 2006 19:22:26 +0200
Subject: [LinuxBIOS] [OLPC-devel] OLPC buildsystem cleanups
In-Reply-To: <20060821171614.230770@gmx.net>
References: <20060803231225.81150@gmx.net>
	<8a0c36780608031915j5c61bbcehe9384281dc362683@mail.gmail.com>
	<20060804231125.310580@gmx.net>
	<m13bcbob14.fsf@ebiederm.dsl.xmission.com>
	<20060820021356.76290@gmx.net>
	<8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>
	<20060821171614.230770@gmx.net>
Message-ID: <20060821172226.GA4066@coresystems.de>

* Carl-Daniel U. Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060821 19:16]:
> -	payload /tmp/olpcpayload.elf
> +	payload ../../../../../../../../deploy/olpc-payload
>  end

Hm. I dont know. The above path is pretty unreadable.
Or at least really ugly.

Can we have it parse environment variables instead? 
$(TOPDIR) / $(PAYLOADDIR) ?


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From jordan.crouse at amd.com  Mon Aug 21 19:41:09 2006
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 21 Aug 2006 11:41:09 -0600
Subject: [LinuxBIOS] OLPC buildsystem cleanups
In-Reply-To: <20060821171614.230770@gmx.net>
References: <20060803231225.81150@gmx.net>
	<8a0c36780608031915j5c61bbcehe9384281dc362683@mail.gmail.com>
	<20060804231125.310580@gmx.net>
	<m13bcbob14.fsf@ebiederm.dsl.xmission.com>
	<20060820021356.76290@gmx.net>
	<8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>
	<20060821171614.230770@gmx.net>
Message-ID: <20060821174109.GZ3643@cosmic.amd.com>

On 21/08/06 19:16 +0200, Carl-Daniel U. Hailfinger wrote:
> Hi,
> 
> the attached patches change the OLPC build system to use relative payload paths instead of using a hardcoded file in /tmp which will sooner or later cause security problems. Additionally, a check for config file correctness has been added so you can't accidentially generate the wrong payload for a given LinuxBIOS config.

> -	payload /tmp/olpcpayload.elf
> +	payload ../../../../../../../../deploy/olpc-payload

I agree that using /tmp is a problem, but this is definitely not the way to
fix it.  First of all, it breaks LinuxBIOS only builds, and secondly, it 
is dependent on how buildrom works, which may or may not change on a 
moment's notice.  it would be smarter to use sed to modify the configuration
on the fly, as the attached patch indicates.

Jordan

-------------- next part --------------
LINUXBIOS:  Update the payload string to be more secure

From: Jordan Crouse <jordan.crouse at amd.com>


---

 packages/linuxbios/linuxbios.mk |    8 +++-----
 1 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/packages/linuxbios/linuxbios.mk b/packages/linuxbios/linuxbios.mk
index 8b2ffc2..2e35c30 100644
--- a/packages/linuxbios/linuxbios.mk
+++ b/packages/linuxbios/linuxbios.mk
@@ -47,16 +47,14 @@ endif
 	$(LINUXBIOS_VER) > $(LINUXBIOS_FETCH_LOG) 2>&1
 	@ touch $@
 
-# fix me sooner or later!
-/tmp/olpcpayload.elf: $(PAYLOAD_TARGET)
-	@ cp $< $@
-
 $(LINUXBIOS_STAMP_DIR)/.configured: $(LINUXBIOS_STAMP_DIR)/.unpacked_$(LINUXBIOS_VER)
+	@ cp -f $(LINUXBIOS_TARGET_DIR)/$(LINUXBIOS_CONFIG_NAME) $(LINUXBIOS_TARGET_DIR)/$(LINUXBIOS_CONFIG_NAME).orig
+	cat $(LINUXBIOS_TARGET_DIR)/$(LINUXBIOS_CONFIG_NAME).orig | sed -e 's:payload .*$$:payload $(PAYLOAD_TARGET):' > $(LINUXBIOS_TARGET_DIR)/$(LINUXBIOS_CONFIG_NAME)
 	@( cd $(LINUXBIOS_TARGET_DIR); \
 	./buildtarget $(LINUXBIOS_CONFIG_NAME) > $(LINUXBIOS_CONFIG_LOG) 2>&1)
 	@ touch $@
 
-$(LINUXBIOS_BUILD_DIR)/linuxbios.rom:  $(LINUXBIOS_STAMP_DIR)/.configured /tmp/olpcpayload.elf
+$(LINUXBIOS_BUILD_DIR)/linuxbios.rom:  $(LINUXBIOS_STAMP_DIR)/.configured $(PAYLOAD_TARGET) 
 	@ echo "Building linuxbios..."
 	@ make -C $(LINUXBIOS_BUILD_DIR) > $(LINUXBIOS_BUILD_LOG) 2>&1
 

From smithbone at gmail.com  Mon Aug 21 21:41:25 2006
From: smithbone at gmail.com (Richard Smith)
Date: Mon, 21 Aug 2006 14:41:25 -0500
Subject: [LinuxBIOS] [OLPC-devel] Re: OLPC buildsystem cleanups
In-Reply-To: <20060821174109.GZ3643@cosmic.amd.com>
References: <20060803231225.81150@gmx.net>
	<8a0c36780608031915j5c61bbcehe9384281dc362683@mail.gmail.com>
	<20060804231125.310580@gmx.net>
	<m13bcbob14.fsf@ebiederm.dsl.xmission.com>
	<20060820021356.76290@gmx.net>
	<8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>
	<20060821171614.230770@gmx.net> <20060821174109.GZ3643@cosmic.amd.com>
Message-ID: <8a0c36780608211241m78ecd2a5of230dfa6db006c69@mail.gmail.com>

> I agree that using /tmp is a problem, but this is definitely not the way to
> fix it.  First of all, it breaks LinuxBIOS only builds, and secondly, it
> is dependent on how buildrom works, which may or may not change on a
> moment's notice.  it would be smarter to use sed to modify the configuration
> on the fly, as the attached patch indicates.

While very elegant, I think changing the config file on the fly makes
it harder to see whats going on.  Rather than copy the payload into
temp can we not just copy the payload into $(LINUXBIOS_TARGET_NAME)

Then the config file just has PAYLOAD ../olpcpayload.elf which should
work for both buildrom and non-buildrom builds.

Perhaps we can build and export a $(LINUXBIOS_PAYLOAD_PATH)? So the
higher level make code knows where to stick it.

That to me would seem to be a much more discoverable behavior than
changing the config file automagically.

-- 
Richard A. Smith



From jordan.crouse at amd.com  Mon Aug 21 21:55:32 2006
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 21 Aug 2006 13:55:32 -0600
Subject: [LinuxBIOS] OLPC buildsystem cleanups
In-Reply-To: <8a0c36780608211241m78ecd2a5of230dfa6db006c69@mail.gmail.com>
References: <20060803231225.81150@gmx.net>
	<8a0c36780608031915j5c61bbcehe9384281dc362683@mail.gmail.com>
	<20060804231125.310580@gmx.net>
	<m13bcbob14.fsf@ebiederm.dsl.xmission.com>
	<20060820021356.76290@gmx.net>
	<8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>
	<20060821171614.230770@gmx.net> <20060821174109.GZ3643@cosmic.amd.com>
	<8a0c36780608211241m78ecd2a5of230dfa6db006c69@mail.gmail.com>
Message-ID: <20060821195532.GA3643@cosmic.amd.com>

On 21/08/06 14:41 -0500, Richard Smith wrote:
> >I agree that using /tmp is a problem, but this is definitely not the way to
> >fix it.  First of all, it breaks LinuxBIOS only builds, and secondly, it
> >is dependent on how buildrom works, which may or may not change on a
> >moment's notice.  it would be smarter to use sed to modify the 
> >configuration
> >on the fly, as the attached patch indicates.
> 
> While very elegant, I think changing the config file on the fly makes
> it harder to see whats going on.  Rather than copy the payload into
> temp can we not just copy the payload into $(LINUXBIOS_TARGET_NAME)
> 
> Then the config file just has PAYLOAD ../olpcpayload.elf which should
> work for both buildrom and non-buildrom builds.
> 
> Perhaps we can build and export a $(LINUXBIOS_PAYLOAD_PATH)? So the
> higher level make code knows where to stick it.
> 
> That to me would seem to be a much more discoverable behavior than
> changing the config file automagically.

True - I have less of a problem with this since I percieve payload to be
an variable that the LinuxBIOS build system expects the user to set.
Regardless, changing the config file on the fly is very much a Bad Thing. 
I wouldn't have any problem redirecting the payload somewhere within the
LinuxBIOS build, assuming the LinuxBIOS owners are cool with that paradigm.

Jordan

-- 
Jordan Crouse
Senior Linux Engineer
Advanced Micro Devices, Inc.
<www.amd.com/embeddedprocessors>





From smithbone at gmail.com  Tue Aug 22 05:54:00 2006
From: smithbone at gmail.com (Richard Smith)
Date: Mon, 21 Aug 2006 22:54:00 -0500
Subject: [LinuxBIOS] OLPC buildsystem cleanups
In-Reply-To: <20060821195532.GA3643@cosmic.amd.com>
References: <20060803231225.81150@gmx.net>
	<8a0c36780608031915j5c61bbcehe9384281dc362683@mail.gmail.com>
	<20060804231125.310580@gmx.net>
	<m13bcbob14.fsf@ebiederm.dsl.xmission.com>
	<20060820021356.76290@gmx.net>
	<8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>
	<20060821171614.230770@gmx.net> <20060821174109.GZ3643@cosmic.amd.com>
	<8a0c36780608211241m78ecd2a5of230dfa6db006c69@mail.gmail.com>
	<20060821195532.GA3643@cosmic.amd.com>
Message-ID: <8a0c36780608212054k24562dcfsaf4a4b26e010fd7a@mail.gmail.com>

> I wouldn't have any problem redirecting the payload somewhere within the
> LinuxBIOS build, assuming the LinuxBIOS owners are cool with that paradigm.
>

Speaking as one  I don't have an issue.

In fact thats normally how I setup my config files anyway.  Most
LinuxBIOS payloads are build outside of LB.  I usually copy them into
my target directory with my config files so that if I need to blow
away my build dir and start over clean I can without nuking my
payload(s).

-- 
Richard A. Smith



From rminnich at lanl.gov  Tue Aug 22 07:03:33 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Mon, 21 Aug 2006 23:03:33 -0600
Subject: [LinuxBIOS] [OLPC-devel] OLPC buildsystem cleanups
In-Reply-To: <20060821172226.GA4066@coresystems.de>
References: <20060803231225.81150@gmx.net>	<8a0c36780608031915j5c61bbcehe9384281dc362683@mail.gmail.com>	<20060804231125.310580@gmx.net>	<m13bcbob14.fsf@ebiederm.dsl.xmission.com>	<20060820021356.76290@gmx.net>	<8a0c36780608191946g34c37b69o2326caf5d26e5d52@mail.gmail.com>	<20060821171614.230770@gmx.net>
	<20060821172226.GA4066@coresystems.de>
Message-ID: <44EA9025.9020304@lanl.gov>

Stefan Reinauer wrote:
> * Carl-Daniel U. Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060821 19:16]:
> 
>>-	payload /tmp/olpcpayload.elf
>>+	payload ../../../../../../../../deploy/olpc-payload
>> end
> 
> 
> Hm. I dont know. The above path is pretty unreadable.
> Or at least really ugly.
> 
> Can we have it parse environment variables instead? 
> $(TOPDIR) / $(PAYLOADDIR) ?
> 
> 

using an environment variable instead of a hardcoded path has been on my 
list for a long time. Rather than all this path finagling, we might want 
to consider doing that.

thanks

ron



From rogelio.serrano at gmail.com  Tue Aug 22 09:21:31 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Tue, 22 Aug 2006 15:21:31 +0800
Subject: [LinuxBIOS] standard hardware interface
Message-ID: <a9951d2a0608220021m39776fc0j5e6ca70ed6bf8b18@mail.gmail.com>

Is there a de facto standard for ram controllers?

If none which chipset is close to being a de facto standard?

Same question for pci

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From rogelio.serrano at gmail.com  Tue Aug 22 09:28:53 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Tue, 22 Aug 2006 15:28:53 +0800
Subject: [LinuxBIOS] linux pci initialization
Message-ID: <a9951d2a0608220028gbefcdfaoecd92b970cb1325a@mail.gmail.com>

can linux handle complete pci initialization by itself now?

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From stepan at coresystems.de  Tue Aug 22 12:48:49 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 22 Aug 2006 12:48:49 +0200
Subject: [LinuxBIOS] standard hardware interface
In-Reply-To: <a9951d2a0608220021m39776fc0j5e6ca70ed6bf8b18@mail.gmail.com>
References: <a9951d2a0608220021m39776fc0j5e6ca70ed6bf8b18@mail.gmail.com>
Message-ID: <20060822104849.GB28554@coresystems.de>

* Rogelio Serrano <rogelio.serrano at gmail.com> [060822 09:21]:
> Is there a de facto standard for ram controllers?
> 
> If none which chipset is close to being a de facto standard?

No, each chipset/dram controller needs to be supported individually
on the bios level. All AMD K8 boards are somewhat similar to each other,
as the memory controller is in the CPU. Intel controllers might be
similar across the product lines as well from the software side.

> Same question for pci

PCI is pretty much standardized: http://www.pcisig.com/


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Tue Aug 22 12:49:18 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 22 Aug 2006 12:49:18 +0200
Subject: [LinuxBIOS] linux pci initialization
In-Reply-To: <a9951d2a0608220028gbefcdfaoecd92b970cb1325a@mail.gmail.com>
References: <a9951d2a0608220028gbefcdfaoecd92b970cb1325a@mail.gmail.com>
Message-ID: <20060822104918.GC28554@coresystems.de>

* Rogelio Serrano <rogelio.serrano at gmail.com> [060822 09:28]:
> can linux handle complete pci initialization by itself now?

No, but LinuxBIOS does a pretty good job doing so.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From rogelio.serrano at gmail.com  Tue Aug 22 12:56:56 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Tue, 22 Aug 2006 18:56:56 +0800
Subject: [LinuxBIOS] linux pci initialization
In-Reply-To: <20060822104918.GC28554@coresystems.de>
References: <a9951d2a0608220028gbefcdfaoecd92b970cb1325a@mail.gmail.com>
	<20060822104918.GC28554@coresystems.de>
Message-ID: <a9951d2a0608220356i31b36ed4ya6ca74c33d4de60@mail.gmail.com>

On 8/22/06, Stefan Reinauer <stepan at coresystems.de> wrote:
> * Rogelio Serrano <rogelio.serrano at gmail.com> [060822 09:28]:
> > can linux handle complete pci initialization by itself now?
>
> No, but LinuxBIOS does a pretty good job doing so.
>

I gathered from the wiki that linux cant handle a totally
uninitialized pci bus and that linux is close to doing that. Im trying
to read the pci sources in hopes of being able to make linuxbios work
with my kt600 motherboard. So if linux 2.6.17 can already initialize a
totally uninitialized kt600 pci bus then i might start playing with
linuxbios. all thats left is figuring out how to initialize  the dram
controller.

> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
>


-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself

From rogelio.serrano at gmail.com  Tue Aug 22 12:59:59 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Tue, 22 Aug 2006 18:59:59 +0800
Subject: [LinuxBIOS] standard hardware interface
In-Reply-To: <20060822104849.GB28554@coresystems.de>
References: <a9951d2a0608220021m39776fc0j5e6ca70ed6bf8b18@mail.gmail.com>
	<20060822104849.GB28554@coresystems.de>
Message-ID: <a9951d2a0608220359u48059319p58171392fc1ae4df@mail.gmail.com>

On 8/22/06, Stefan Reinauer <stepan at coresystems.de> wrote:
> * Rogelio Serrano <rogelio.serrano at gmail.com> [060822 09:21]:
> > Is there a de facto standard for ram controllers?
> >
> > If none which chipset is close to being a de facto standard?
>
> No, each chipset/dram controller needs to be supported individually
> on the bios level. All AMD K8 boards are somewhat similar to each other,
> as the memory controller is in the CPU. Intel controllers might be
> similar across the product lines as well from the software side.
>

i was looking for some hope of being able to force a hardware standard
of some kind. looks like there is none.

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From stepan at coresystems.de  Tue Aug 22 13:01:03 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 22 Aug 2006 13:01:03 +0200
Subject: [LinuxBIOS] linux pci initialization
In-Reply-To: <a9951d2a0608220356i31b36ed4ya6ca74c33d4de60@mail.gmail.com>
References: <a9951d2a0608220028gbefcdfaoecd92b970cb1325a@mail.gmail.com>
	<20060822104918.GC28554@coresystems.de>
	<a9951d2a0608220356i31b36ed4ya6ca74c33d4de60@mail.gmail.com>
Message-ID: <20060822110103.GA399@coresystems.de>

* Rogelio Serrano <rogelio.serrano at gmail.com> [060822 12:56]:
> I gathered from the wiki that linux cant handle a totally
> uninitialized pci bus and that linux is close to doing that. Im trying
> to read the pci sources in hopes of being able to make linuxbios work
> with my kt600 motherboard. So if linux 2.6.17 can already initialize a
> totally uninitialized kt600 pci bus then i might start playing with
> linuxbios. all thats left is figuring out how to initialize  the dram
> controller.
 
LinuxBIOS will set up your PCI devices correctly. The big question is
how to get dram working indeed. Can you provide an lspci output to the
list?

> >--
> >coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
> >      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> >Email: info at coresystems.de  ? http://www.coresystems.de/
> >
> 
> 
> -- 
> things i hate about my linux pc:
> 
> 1. it takes more than a second to boot up
> 2. keeps asking about filenames and directories
> 3. does not remember what i was working on yesterday
> 4. does not remember all the changes i have ever made
> 5.cannot figure out necessary settings by itself

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From rogelio.serrano at gmail.com  Tue Aug 22 13:07:10 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Tue, 22 Aug 2006 19:07:10 +0800
Subject: [LinuxBIOS] linux pci initialization
In-Reply-To: <20060822110103.GA399@coresystems.de>
References: <a9951d2a0608220028gbefcdfaoecd92b970cb1325a@mail.gmail.com>
	<20060822104918.GC28554@coresystems.de>
	<a9951d2a0608220356i31b36ed4ya6ca74c33d4de60@mail.gmail.com>
	<20060822110103.GA399@coresystems.de>
Message-ID: <a9951d2a0608220407s780fed9dp83f01a53d9f20168@mail.gmail.com>

On 8/22/06, Stefan Reinauer <stepan at coresystems.de> wrote:
> * Rogelio Serrano <rogelio.serrano at gmail.com> [060822 12:56]:
> > I gathered from the wiki that linux cant handle a totally
> > uninitialized pci bus and that linux is close to doing that. Im trying
> > to read the pci sources in hopes of being able to make linuxbios work
> > with my kt600 motherboard. So if linux 2.6.17 can already initialize a
> > totally uninitialized kt600 pci bus then i might start playing with
> > linuxbios. all thats left is figuring out how to initialize  the dram
> > controller.
>
> LinuxBIOS will set up your PCI devices correctly. The big question is
> how to get dram working indeed.

Well thats great.

> Can you provide an lspci output to the
> list?
>

Yes when i get home.

Is there some hope that the kt600 is somehow similar to other
supported via chipsets?

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From svn at openbios.org  Tue Aug 22 15:21:39 2006
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 22 Aug 2006 15:21:39 +0200
Subject: [LinuxBIOS] r2382 - trunk/LinuxBIOSv2/util
Message-ID: <E1GFWCJ-0003BH-FV@khepri.openbios.org>

Author: stepan
Date: 2006-08-22 15:21:39 +0200 (Tue, 22 Aug 2006)
New Revision: 2382

Removed:
   trunk/LinuxBIOSv2/util/extensions/
Log:
drop extensions directory. it has never been used.





From info at coresystems.de  Tue Aug 22 15:24:49 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Tue, 22 Aug 2006 15:24:49 +0200
Subject: [LinuxBIOS] LinuxBIOS r2382 build changes
Message-ID: <E1GFWFN-0004K7-1c@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2382 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
drop extensions directory. it has never been used.

Build Log:
 Compilation of Iwill:DK8HTX has been broken Compilation of Iwill:DK8S2 has been broken Compilation of Iwill:DK8X has been broken Compilation of advantech:som_gx533c has been broken Compilation of agami:aruma has been broken Compilation of amd:quartet has been broken Compilation of amd:rumba has been broken Compilation of amd:serenade has been broken Compilation of amd:serengeti_leopard has been broken Compilation of amd:solo has been broken Compilation of arima:hdama has been broken Compilation of artecgroup:dbe61 has been broken Compilation of asus:p2b has been broken Compilation of bitworks:ims has been broken Compilation of broadcom:blast has been broken Compilation of dell:s1850 has been broken Compilation of densitron:dpx114 has been broken Compilation of digitallogic:adl855pc has been broken Compilation of digitallogic:msm586seg has been broken Compilation of eaglelion:5bcm has been broken Compilation of emulation:qemu-i386 has been broken Compilation of ibm:e325 has been broken Compilation of ibm:e326 has been broken Compilation of intel:jarrell has been broken Compilation of intel:xe7501devkit has been broken Compilation of lippert:frontrunner has been broken Compilation of newisys:khepri has been broken Compilation of olpc:rev_a has been broken Compilation of sunw:ultra40 has been broken Compilation of supermicro:x6dai_g has been broken Compilation of supermicro:x6dhe_g has been broken Compilation of supermicro:x6dhe_g2 has been broken Compilation of supermicro:x6dhr_ig has been broken Compilation of supermicro:x6dhr_ig2 has been broken Compilation of technologic:ts5300 has been broken Compilation of tyan:s2735 has been broken Compilation of tyan:s2850 has been broken Compilation of tyan:s2875 has been broken Compilation of tyan:s2880 has been broken Compilation of tyan:s2881 has been broken Compilation of tyan:s2882 has been broken Compilation of tyan:s2885 has been broken Compilation of tyan:s2891 has been broken Compilation of tyan:s2892 has been broken Compilation of tyan:s2895 has been broken Compilation of tyan:s4880 has been broken Compilation of tyan:s4882 has been broken Compilation of via:epia has been broken Compilation of via:epia-m has been broken

If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From rogelio.serrano at gmail.com  Tue Aug 22 17:55:21 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Tue, 22 Aug 2006 23:55:21 +0800
Subject: [LinuxBIOS] linux pci initialization
In-Reply-To: <a9951d2a0608220407s780fed9dp83f01a53d9f20168@mail.gmail.com>
References: <a9951d2a0608220028gbefcdfaoecd92b970cb1325a@mail.gmail.com>
	<20060822104918.GC28554@coresystems.de>
	<a9951d2a0608220356i31b36ed4ya6ca74c33d4de60@mail.gmail.com>
	<20060822110103.GA399@coresystems.de>
	<a9951d2a0608220407s780fed9dp83f01a53d9f20168@mail.gmail.com>
Message-ID: <a9951d2a0608220855t6bd856ffv86dd71a02696e149@mail.gmail.com>

On 8/22/06, Rogelio Serrano <rogelio.serrano at gmail.com> wrote:
> On 8/22/06, Stefan Reinauer <stepan at coresystems.de> wrote:
> > * Rogelio Serrano <rogelio.serrano at gmail.com> [060822 12:56]:
> > > I gathered from the wiki that linux cant handle a totally
> > > uninitialized pci bus and that linux is close to doing that. Im trying
> > > to read the pci sources in hopes of being able to make linuxbios work
> > > with my kt600 motherboard. So if linux 2.6.17 can already initialize a
> > > totally uninitialized kt600 pci bus then i might start playing with
> > > linuxbios. all thats left is figuring out how to initialize  the dram
> > > controller.
> >
> > LinuxBIOS will set up your PCI devices correctly. The big question is
> > how to get dram working indeed.
>
> Well thats great.
>
> > Can you provide an lspci output to the
> > list?
> >
>
> Yes when i get home.

00:00.0 Host bridge: VIA Technologies, Inc. VT8377 [KT400/KT600 AGP]
Host Bridge (rev 80)
00:01.0 PCI bridge: VIA Technologies, Inc. VT8237 PCI Bridge
00:0a.0 SCSI storage controller: Adaptec AIC-7861 (rev 03)
00:0c.0 Ethernet controller: 3Com Corporation 3c905C-TX/TX-M [Tornado] (rev 74)
00:0f.0 RAID bus controller: VIA Technologies, Inc. VIA VT6420 SATA
RAID Controller (rev 80)
00:0f.1 IDE interface: VIA Technologies, Inc.
VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06)
00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81)
00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81)
00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81)
00:10.3 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81)
00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86)
00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge
[KT600/K8T800/K8T890 South]
00:11.5 Multimedia audio controller: VIA Technologies, Inc.
VT8233/A/8235/8237 AC97 Audio Controller (rev 60)
01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G400/G450 (rev 82)

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From svn at openbios.org  Wed Aug 23 12:52:12 2006
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 23 Aug 2006 12:52:12 +0200
Subject: [LinuxBIOS] r2383 - trunk/LinuxBIOSv2/documentation
Message-ID: <E1GFqLE-0002VU-Uk@khepri.openbios.org>

Author: stepan
Date: 2006-08-23 12:52:12 +0200 (Wed, 23 Aug 2006)
New Revision: 2383

Modified:
   trunk/LinuxBIOSv2/documentation/LinuxBIOS-AMD64.tex
Log:
fix special chars in document.


Modified: trunk/LinuxBIOSv2/documentation/LinuxBIOS-AMD64.tex
===================================================================
--- trunk/LinuxBIOSv2/documentation/LinuxBIOS-AMD64.tex	2006-08-22 13:21:39 UTC (rev 2382)
+++ trunk/LinuxBIOSv2/documentation/LinuxBIOS-AMD64.tex	2006-08-23 10:52:12 UTC (rev 2383)
@@ -148,7 +148,7 @@
 
 { \small
 \begin{verbatim}
-% cvs update ?Pd
+% cvs update -Pd
 \end{verbatim}
 }
 
@@ -330,7 +330,7 @@
 quotation marks: 
 
 \begin{verbatim}
-        default CC="gcc ?m32"
+        default CC="gcc -m32"
 \end{verbatim}
 
 \item \begin{verbatim}option\end{verbatim}
@@ -407,7 +407,7 @@
 \item \begin{verbatim}CC\end{verbatim}
 
 Target C Compiler. Default is \texttt{\$(CROSS\_COMPILE)gcc}. Set to
-\texttt{gcc ?m32} for compiling AMD64 LinuxBIOS images on an AMD64 
+\texttt{gcc -m32} for compiling AMD64 LinuxBIOS images on an AMD64 
 machine.
 
 \item \begin{verbatim}CONFIG_CHIP_CONFIGURE \end{verbatim}
@@ -552,12 +552,12 @@
 \begin{verbatim}
 makerule ./auto.E
         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action "./romcc -E -mcpu=k8 -O2 ?I$(TOP)/src -I. $(CPPFLAGS) \
+        action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
 		$(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action "./romcc    -mcpu=k8 -O2 ?I$(TOP)/src -I. $(CPPFLAGS) \
+        action "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
                 $(MAINBOARD)/auto.c -o $@"
 end
 \end{verbatim}




From info at coresystems.de  Wed Aug 23 13:31:13 2006
From: info at coresystems.de (LinuxBIOS information)
Date: Wed, 23 Aug 2006 13:31:13 +0200
Subject: [LinuxBIOS] r2383 build service
Message-ID: <E1GFqwz-0004Mt-W4@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2383 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
fix special chars in document.


Build Log:
Compilation of Iwill:DK8HTX has been fixed
Compilation of Iwill:DK8S2 has been fixed
Compilation of Iwill:DK8X has been fixed
Compilation of advantech:som_gx533c has been fixed
Compilation of agami:aruma has been fixed
Compilation of amd:quartet has been fixed
Compilation of amd:rumba has been fixed
Compilation of amd:serenade has been fixed
Compilation of amd:serengeti_leopard has been fixed
Compilation of amd:solo has been fixed
Compilation of arima:hdama has been fixed
Compilation of artecgroup:dbe61 has been fixed
Compilation of asus:p2b has been fixed
Compilation of bitworks:ims has been fixed
Compilation of broadcom:blast has been fixed
Compilation of dell:s1850 has been fixed
Compilation of densitron:dpx114 has been fixed
Compilation of digitallogic:adl855pc has been fixed
Compilation of digitallogic:msm586seg has been fixed
Compilation of eaglelion:5bcm has been fixed
Compilation of emulation:qemu-i386 has been fixed
Compilation of ibm:e325 has been fixed
Compilation of ibm:e326 has been fixed
Compilation of intel:jarrell has been fixed
Compilation of intel:xe7501devkit has been fixed
Compilation of lippert:frontrunner has been fixed
Compilation of newisys:khepri has been fixed
Compilation of olpc:rev_a has been fixed
Compilation of sunw:ultra40 has been fixed
Compilation of supermicro:x6dai_g has been fixed
Compilation of supermicro:x6dhe_g has been fixed
Compilation of supermicro:x6dhe_g2 has been fixed
Compilation of supermicro:x6dhr_ig has been fixed
Compilation of supermicro:x6dhr_ig2 has been fixed
Compilation of technologic:ts5300 has been fixed
Compilation of tyan:s2735 has been fixed
Compilation of tyan:s2850 has been fixed
Compilation of tyan:s2875 has been fixed
Compilation of tyan:s2880 has been fixed
Compilation of tyan:s2881 has been fixed
Compilation of tyan:s2882 has been fixed
Compilation of tyan:s2885 has been fixed
Compilation of tyan:s2891 has been fixed
Compilation of tyan:s2892 has been fixed
Compilation of tyan:s2895 has been fixed
Compilation of tyan:s4880 has been fixed
Compilation of tyan:s4882 has been fixed
Compilation of via:epia has been fixed
Compilation of via:epia-m has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From svn at openbios.org  Wed Aug 23 13:47:59 2006
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 23 Aug 2006 13:47:59 +0200
Subject: [LinuxBIOS] r2384 - trunk/LinuxBIOSv2/src/config
Message-ID: <E1GFrDD-0004rm-1s@khepri.openbios.org>

Author: stepan
Date: 2006-08-23 13:47:58 +0200 (Wed, 23 Aug 2006)
New Revision: 2384

Modified:
   trunk/LinuxBIOSv2/src/config/LinuxBIOSDoc.config
Log:
enable graphs created by dot.


Modified: trunk/LinuxBIOSv2/src/config/LinuxBIOSDoc.config
===================================================================
--- trunk/LinuxBIOSv2/src/config/LinuxBIOSDoc.config	2006-08-23 10:52:12 UTC (rev 2383)
+++ trunk/LinuxBIOSv2/src/config/LinuxBIOSDoc.config	2006-08-23 11:47:58 UTC (rev 2384)
@@ -243,15 +243,15 @@
 #---------------------------------------------------------------------------
 CLASS_DIAGRAMS         = YES
 HIDE_UNDOC_RELATIONS   = YES
-HAVE_DOT               = NO
+HAVE_DOT               = YES
 CLASS_GRAPH            = YES
 COLLABORATION_GRAPH    = YES
 GROUP_GRAPHS           = YES
-UML_LOOK               = NO
+UML_LOOK               = YES
 TEMPLATE_RELATIONS     = NO
 INCLUDE_GRAPH          = YES
 INCLUDED_BY_GRAPH      = YES
-CALL_GRAPH             = NO
+CALL_GRAPH             = YES
 GRAPHICAL_HIERARCHY    = YES
 DIRECTORY_GRAPH        = YES
 DOT_IMAGE_FORMAT       = png




From svn at openbios.org  Wed Aug 23 16:28:37 2006
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 23 Aug 2006 16:28:37 +0200
Subject: [LinuxBIOS] r2385 - in trunk/LinuxBIOSv2/src: include
	northbridge/intel/e7501 southbridge/intel/i82801ca
	superio/smsc/lpc47b272 superio/smsc/lpc47m10x superio/smsc/lpc47n217
Message-ID: <E1GFtif-0004Hn-NK@khepri.openbios.org>

Author: stepan
Date: 2006-08-23 16:28:37 +0200 (Wed, 23 Aug 2006)
New Revision: 2385

Modified:
   trunk/LinuxBIOSv2/src/include/assert.h
   trunk/LinuxBIOSv2/src/include/sdram_mode.h
   trunk/LinuxBIOSv2/src/include/spd.h
   trunk/LinuxBIOSv2/src/northbridge/intel/e7501/e7501.h
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/cmos_failover.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.h
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_ide.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_smbus.c
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/superio.c
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
   trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/superio.c
Log:
Uwe Hermann:
here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.
(part 1)



Modified: trunk/LinuxBIOSv2/src/include/assert.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/assert.h	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/include/assert.h	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,59 +1,51 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/assert.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * assert.h: Debugging macros
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: assert.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __ASSERT_H_DEFINED
-#define __ASSERT_H_DEFINED
-
-// ROMCC doesn't support __FILE__ or __LINE__  :^{
-
-#if DEBUG
-#ifdef __ROMCC__
-#define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
-#else
-#define ASSERT(x)	{ 				\
-						if (!(x)) 	\
-						{			\
-							printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
-							die(""); \
-						}			\
-					}
-#endif		// __ROMCC__
-#else		// !DEBUG
-#define ASSERT(x)	{ }
-#endif
-
-#ifdef __ROMCC__
-#define BUG()		{ 	die("BUG encountered: system halted\r\n");  }
-#else
-#define BUG()		{ 				\
-						printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
-						die(""); \
-					}
-#endif
-					
-#endif 	// __ASSERT_H_DEFINED
+/*
+ * assert.h: Debugging macros
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASSERT_H_DEFINED
+#define __ASSERT_H_DEFINED
+
+// ROMCC doesn't support __FILE__ or __LINE__  :^{
+
+#if DEBUG
+#ifdef __ROMCC__
+#define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
+#else
+#define ASSERT(x)	{ 				\
+						if (!(x)) 	\
+						{			\
+							printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
+							die(""); \
+						}			\
+					}
+#endif		// __ROMCC__
+#else		// !DEBUG
+#define ASSERT(x)	{ }
+#endif
+
+#ifdef __ROMCC__
+#define BUG()		{ 	die("BUG encountered: system halted\r\n");  }
+#else
+#define BUG()		{ 				\
+						printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
+						die(""); \
+					}
+#endif
+					
+#endif 	// __ASSERT_H_DEFINED

Modified: trunk/LinuxBIOSv2/src/include/sdram_mode.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/sdram_mode.h	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/include/sdram_mode.h	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,62 +1,53 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/sdram_mode.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
- *				 
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: sdram_mode.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __SDRAMMODE_H_DEFINED
-#define __SDRAMMODE_H_DEFINED
-
-// SDRAM Mode Register definitions, per JESD79D
-// These are transmitted via A0-A13
-
-// Burst length
-#define SDRAM_BURST_2     (1<<0)
-#define SDRAM_BURST_4     (2<<0)
-#define SDRAM_BURST_8     (3<<0)
-
-#define SDRAM_BURST_SEQUENTIAL  (0<<3)
-#define SDRAM_BURST_INTERLEAVED	(1<<3)
-
-#define SDRAM_CAS_2_0	  (2<<4)
-#define SDRAM_CAS_3_0     (3<<4)	/* Optional for DDR 200-333 */
-#define SDRAM_CAS_1_5     (5<<4)	/* Optional */
-#define SDRAM_CAS_2_5     (6<<4)
-#define SDRAM_CAS_MASK    (7<<4)
-
-#define SDRAM_MODE_NORMAL		(0 << 7)
-#define SDRAM_MODE_TEST         (1 << 7)
-#define SDRAM_MODE_DLL_RESET    (2 << 7)
-
-// Extended Mode Register
-
-#define SDRAM_EXTMODE_DLL_ENABLE	(0 << 0)
-#define SDRAM_EXTMODE_DLL_DISABLE	(1 << 0)
-
-#define SDRAM_EXTMODE_DRIVE_NORMAL	(0 << 1)
-#define SDRAM_EXTMODE_DRIVE_WEAK	(1 << 1)	/* Optional */
-
-#endif 	// __SDRAMMODE_H_DEFINED
+/*
+ * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SDRAMMODE_H_DEFINED
+#define __SDRAMMODE_H_DEFINED
+
+// SDRAM Mode Register definitions, per JESD79D
+// These are transmitted via A0-A13
+
+// Burst length
+#define SDRAM_BURST_2     (1<<0)
+#define SDRAM_BURST_4     (2<<0)
+#define SDRAM_BURST_8     (3<<0)
+
+#define SDRAM_BURST_SEQUENTIAL  (0<<3)
+#define SDRAM_BURST_INTERLEAVED	(1<<3)
+
+#define SDRAM_CAS_2_0	  (2<<4)
+#define SDRAM_CAS_3_0     (3<<4)	/* Optional for DDR 200-333 */
+#define SDRAM_CAS_1_5     (5<<4)	/* Optional */
+#define SDRAM_CAS_2_5     (6<<4)
+#define SDRAM_CAS_MASK    (7<<4)
+
+#define SDRAM_MODE_NORMAL		(0 << 7)
+#define SDRAM_MODE_TEST         (1 << 7)
+#define SDRAM_MODE_DLL_RESET    (2 << 7)
+
+// Extended Mode Register
+
+#define SDRAM_EXTMODE_DLL_ENABLE	(0 << 0)
+#define SDRAM_EXTMODE_DLL_DISABLE	(1 << 0)
+
+#define SDRAM_EXTMODE_DRIVE_NORMAL	(0 << 1)
+#define SDRAM_EXTMODE_DRIVE_WEAK	(1 << 1)	/* Optional */
+
+#endif 	// __SDRAMMODE_H_DEFINED

Modified: trunk/LinuxBIOSv2/src/include/spd.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/spd.h	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/include/spd.h	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,89 +1,81 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/spd.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * spd.h: Definitions for Serial Presence Detect (SPD) data
- *		  stored on SDRAM modules
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: spd.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __SPD_H_DEFINED
-#define __SPD_H_DEFINED
-
-// Byte numbers
-#define SPD_MEMORY_TYPE							 2
-#define SPD_NUM_ROWS							 3
-#define SPD_NUM_COLUMNS							 4
-#define SPD_NUM_DIMM_BANKS						 5
-#define SPD_MODULE_DATA_WIDTH_LSB				 6
-#define SPD_MODULE_DATA_WIDTH_MSB				 7
-#define SPD_MODULE_VOLTAGE						 8
-#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX			 9
-#define SPD_DIMM_CONFIG_TYPE					11
-#define	SPD_REFRESH								12
-#define SPD_PRIMARY_DRAM_WIDTH					13
-#define SPD_SUPPORTED_BURST_LENGTHS				16
-#define SPD_NUM_BANKS_PER_DRAM					17
-#define SPD_ACCEPTABLE_CAS_LATENCIES			18
-#define SPD_MODULE_ATTRIBUTES					21
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05	23
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10	25
-#define SPD_MIN_ROW_PRECHARGE_TIME				27
-#define SPD_MIN_RAS_TO_CAS_DELAY				29
-#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY		30
-#define SPD_ADDRESS_CMD_HOLD					33
-
-
-// SPD_MEMORY_TYPE values
-#define MEMORY_TYPE_SDRAM_DDR	7
-
-// SPD_MODULE_VOLTAGE values
-#define SPD_VOLTAGE_SSTL2		4
-
-// SPD_DIMM_CONFIG_TYPE values
-#define ERROR_SCHEME_NONE		0
-#define ERROR_SCHEME_PARITY		1
-#define ERROR_SCHEME_ECC		2
-
-// SPD_ACCEPTABLE_CAS_LATENCIES values
-#define SPD_CAS_LATENCY_1_0		0x01
-#define SPD_CAS_LATENCY_1_5		0x02
-#define SPD_CAS_LATENCY_2_0		0x04
-#define SPD_CAS_LATENCY_2_5		0x08
-#define SPD_CAS_LATENCY_3_0		0x10
-#define SPD_CAS_LATENCY_3_5		0x20
-#define SPD_CAS_LATENCY_4_0		0x40
-
-// SPD_SUPPORTED_BURST_LENGTHS values
-#define SPD_BURST_LENGTH_1		1
-#define SPD_BURST_LENGTH_2		2
-#define SPD_BURST_LENGTH_4		4
-#define SPD_BURST_LENGTH_8		8
-#define SPD_BURST_LENGTH_PAGE	(1<<7)
-
-
-// SPD_MODULE_ATTRIBUTES values
-#define MODULE_BUFFERED			1
-#define MODULE_REGISTERED		2
-
-#endif 	// __SPD_H_DEFINED
+/*
+ * spd.h: Definitions for Serial Presence Detect (SPD) data
+ *		  stored on SDRAM modules
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SPD_H_DEFINED
+#define __SPD_H_DEFINED
+
+// Byte numbers
+#define SPD_MEMORY_TYPE							 2
+#define SPD_NUM_ROWS							 3
+#define SPD_NUM_COLUMNS							 4
+#define SPD_NUM_DIMM_BANKS						 5
+#define SPD_MODULE_DATA_WIDTH_LSB				 6
+#define SPD_MODULE_DATA_WIDTH_MSB				 7
+#define SPD_MODULE_VOLTAGE						 8
+#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX			 9
+#define SPD_DIMM_CONFIG_TYPE					11
+#define	SPD_REFRESH								12
+#define SPD_PRIMARY_DRAM_WIDTH					13
+#define SPD_SUPPORTED_BURST_LENGTHS				16
+#define SPD_NUM_BANKS_PER_DRAM					17
+#define SPD_ACCEPTABLE_CAS_LATENCIES			18
+#define SPD_MODULE_ATTRIBUTES					21
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05	23
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10	25
+#define SPD_MIN_ROW_PRECHARGE_TIME				27
+#define SPD_MIN_RAS_TO_CAS_DELAY				29
+#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY		30
+#define SPD_ADDRESS_CMD_HOLD					33
+
+
+// SPD_MEMORY_TYPE values
+#define MEMORY_TYPE_SDRAM_DDR	7
+
+// SPD_MODULE_VOLTAGE values
+#define SPD_VOLTAGE_SSTL2		4
+
+// SPD_DIMM_CONFIG_TYPE values
+#define ERROR_SCHEME_NONE		0
+#define ERROR_SCHEME_PARITY		1
+#define ERROR_SCHEME_ECC		2
+
+// SPD_ACCEPTABLE_CAS_LATENCIES values
+#define SPD_CAS_LATENCY_1_0		0x01
+#define SPD_CAS_LATENCY_1_5		0x02
+#define SPD_CAS_LATENCY_2_0		0x04
+#define SPD_CAS_LATENCY_2_5		0x08
+#define SPD_CAS_LATENCY_3_0		0x10
+#define SPD_CAS_LATENCY_3_5		0x20
+#define SPD_CAS_LATENCY_4_0		0x40
+
+// SPD_SUPPORTED_BURST_LENGTHS values
+#define SPD_BURST_LENGTH_1		1
+#define SPD_BURST_LENGTH_2		2
+#define SPD_BURST_LENGTH_4		4
+#define SPD_BURST_LENGTH_8		8
+#define SPD_BURST_LENGTH_PAGE	(1<<7)
+
+
+// SPD_MODULE_ATTRIBUTES values
+#define MODULE_BUFFERED			1
+#define MODULE_REGISTERED		2
+
+#endif 	// __SPD_H_DEFINED

Modified: trunk/LinuxBIOSv2/src/northbridge/intel/e7501/e7501.h
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/intel/e7501/e7501.h	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/northbridge/intel/e7501/e7501.h	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,6 +1,4 @@
 /*
- * $Header$
- *
  * e7501.h: PCI configuration space for the Intel E7501 memory controller
  *
  * Copyright (C) 2005 Digital Design Corporation
@@ -18,9 +16,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
  */
 
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/cmos_failover.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/cmos_failover.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/cmos_failover.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,19 +1,19 @@
-//kind of cmos_err for ich3
-
-#include "i82801ca.h"
+//kind of cmos_err for ich3
 
+#include "i82801ca.h"
+
 static void check_cmos_failed(void) 
-{
+{
 #if HAVE_OPTION_TABLE
-	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
+	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
 
 	if( byte & RTC_BATTERY_DEAD) {
-		// Set boot_option and last_boot to 'Fallback',
+		// Set boot_option and last_boot to 'Fallback',
 		// clear reboot_bits
         byte = cmos_read(RTC_BOOT_BYTE);
         byte &= 0x0c;
         byte |= MAX_REBOOT_CNT << 4;
         cmos_write(byte, RTC_BOOT_BYTE);
-    }
+    }
 #endif
 }

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -7,8 +7,8 @@
 
 void i82801ca_enable(device_t dev)
 {
-	unsigned int index = 0;
-	uint8_t bHasDisableBit = 0;
+	unsigned int index = 0;
+	uint8_t bHasDisableBit = 0;
 	uint16_t cur_disable_mask, new_disable_mask;
 
 //	all 82801ca devices are in bus 0
@@ -19,22 +19,22 @@
 
 	// Calculate disable bit position for specified device:function
 	// NOTE: For ICH-3, only the following devices can be disabled:
-	//		 D31:F1, D31:F3, D31:F5, D31:F6, 
-	//		 D29:F0, D29:F1, D29:F2
+	//		 D31:F1, D31:F3, D31:F5, D31:F6, 
+	//		 D29:F0, D29:F1, D29:F2
 
     if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
-    	index = PCI_FUNC(dev->path.u.pci.devfn);
-
-		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
-			bHasDisableBit = 1;
+    	index = PCI_FUNC(dev->path.u.pci.devfn);
 
+		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
+			bHasDisableBit = 1;
+
     } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
-    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
-
-		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
+    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
+
+		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
 			bHasDisableBit = 1;
     }
-
+
 	if (bHasDisableBit) {
 		cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
 		new_disable_mask = cur_disable_mask & ~(1<<index); 		// enable it
@@ -43,7 +43,7 @@
 		}
 		if (new_disable_mask != cur_disable_mask) {
 			pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
-		}
+		}
 	}
 }
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.h	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca.h	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,10 +1,10 @@
 #ifndef I82801CA_H
 #define I82801CA_H
-
-#ifndef __ROMCC__
+
+#ifndef __ROMCC__
 #include "chip.h"
-extern void i82801ca_enable(device_t dev);
-#endif
+extern void i82801ca_enable(device_t dev);
+#endif
 
 
 #define PCI_DMA_CFG     0x90
@@ -26,37 +26,37 @@
 #define FUNC_DIS        0xF2
 
 // GEN_PMCON_3 bits
-#define RTC_BATTERY_DEAD		(1<<2)
-#define RTC_POWER_FAILED		(1<<1)
+#define RTC_BATTERY_DEAD		(1<<2)
+#define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
-
-/********************************************************************/
-/*							IDE Controller                          */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F1)
-#define IDE_TIM_PRI		0x40		// IDE timings, primary
-#define IDE_TIM_SEC		0x42		// IDE timings, secondary
-
-
-// IDE_TIM bits
-#define IDE_DECODE_ENABLE	(1<<15)
-
-/********************************************************************/
-/*								SMBus                               */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F3)
+
+/********************************************************************/
+/*							IDE Controller                          */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F1)
+#define IDE_TIM_PRI		0x40		// IDE timings, primary
+#define IDE_TIM_SEC		0x42		// IDE timings, secondary
+
+
+// IDE_TIM bits
+#define IDE_DECODE_ENABLE	(1<<15)
+
+/********************************************************************/
+/*								SMBus                               */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20
-#define HOSTC		0x40
-
-// HOSTC bits
-#define I2C_EN		(1<<2)
-#define SMB_SMI_EN	(1<<1)
-#define HST_EN		(1<<0)
+#define HOSTC		0x40
 
+// HOSTC bits
+#define I2C_EN		(1<<2)
+#define SMB_SMI_EN	(1<<1)
+#define HST_EN		(1<<0)
+
 #define SMBUS_IO_BASE 0x1000
-
+
 // I/O registers (relative to SMBUS_IO_BASE)
 #define SMBHSTSTAT		0
 #define SMBHSTCTL		2
@@ -69,7 +69,7 @@
 #define SMBSLVDATA		10
 #define SMLINK_PIN_CTL	14
 #define SMBUS_PIN_CTL	15 
-
+
 /* Between 1-10 seconds, We should never timeout normally 
  * Longer than this is just painful when a timeout condition occurs.
  */

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,5 +1,5 @@
 #include <device/pci_ids.h>
-#include "i82801ca.h"
+#include "i82801ca.h"
 
 static void enable_smbus(void)
 {

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_ide.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_ide.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_ide.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -10,7 +10,7 @@
 {
 	/* Enable ide devices so the linux ide driver will work */
 	uint16_t ideTimingConfig;
-	int enable_primary = 1;
+	int enable_primary = 1;
 	int enable_secondary = 1;
 
 	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,7 +1,7 @@
 /*
  * (C) 2003 Linux Networx, SuSE Linux AG
  * (C) 2004 Tyan Computer
- * (c) 2005 Digital Design Corporation
+ * (c) 2005 Digital Design Corporation
  */
 #include <console/console.h>
 #include <device/device.h>
@@ -14,15 +14,15 @@
 #include "i82801ca.h"
 
 #define NMI_OFF 0
-
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON  1
-
 
+#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+
 void i82801ca_enable_ioapic( struct device *dev) 
 {
 	uint32_t dword;
@@ -60,20 +60,20 @@
     pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	i82801ca_lpc_route_dma
+//----------------------------------------------------------------------------------
+// Function:    	i82801ca_lpc_route_dma
 // Parameters:  	dev
 //					mask - identifies whether each channel should be used for PCI DMA
 //						   (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-//						   Channel 4 is not used (reserved). 
-// Return Value:	None
-// Description: 	Route all DMA channels to either PCI or LPC.
-//
+//						   Channel 4 is not used (reserved). 
+// Return Value:	None
+// Description: 	Route all DMA channels to either PCI or LPC.
+//
 void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) 
 {
     uint16_t dmaConfig;
     int channelIndex;
-
+
     dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
     dmaConfig &= 0x300;				// Preserve reserved bits
     for(channelIndex = 0; channelIndex < 8; channelIndex++) {
@@ -87,27 +87,27 @@
 void i82801ca_rtc_init(struct device *dev)
 {
     uint32_t dword;
-    int rtc_failed;
-	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
-    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
+    int rtc_failed;
+	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
 
     rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
     if (rtc_failed) {
     	// Clear the RTC_BATTERY_DEAD bit, but preserve
-        // the RTC_POWER_FAILED, G3 state, and reserved bits
+        // the RTC_POWER_FAILED, G3 state, and reserved bits
 		// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
         pmcon3 &= ~RTC_POWER_FAILED;
-    }
-
-    get_option(&pwr_on, "power_on_after_fail");
-	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
-	if (!pwr_on) {
-		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
-	}
-	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
-	printk_info("set power %s after power fail\n", 
-				 pwr_on ? "on" : "off");
+    }
 
+    get_option(&pwr_on, "power_on_after_fail");
+	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
+	if (!pwr_on) {
+		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
+	}
+	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
+	printk_info("set power %s after power fail\n", 
+				 pwr_on ? "on" : "off");
+
     // See if the Safe Mode jumper is set
     dword = pci_read_config32(dev, GEN_STS);
     rtc_failed |= dword & (1 << 2);
@@ -142,14 +142,14 @@
     // Enable access to the upper 128 byte bank of CMOS RAM
     pci_write_config8(dev, RTC_CONF, 0x04);
         
-    // Decode 0x3F8-0x3FF (COM1) for COMA port,
+    // Decode 0x3F8-0x3FF (COM1) for COMA port,
 	//		  0x2F8-0x2FF (COM2) for COMB
     pci_write_config8(dev, COM_DEC, 0x10);
-
-	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
-	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
 
-    // Enable COMA, COMB, LPT, floppy; 
+	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
+	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
+
+    // Enable COMA, COMB, LPT, floppy; 
 	// disable microcontroller, Super I/O, sound, gameport
     pci_write_config16(dev, LPC_EN, 0x000F);
 }
@@ -179,18 +179,18 @@
     pci_write_config8(dev, GEN_PMCON_3, byte);
     printk_info("set power %s after power fail\n", pwr_on?"on":"off");
 
-    /* Set up NMI on errors */
-    byte = inb(0x61);
-    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
-    byte &= ~(1 << 2); /* PCI SERR# Enable */
-    outb(byte, 0x61);
-    byte = inb(0x70);
-    nmi_option = NMI_OFF;
-    get_option(&nmi_option, "nmi");
-    if (nmi_option) {			
-        byte &= ~(1 << 7); /* set NMI */
-        outb(byte, 0x70);
-    }
+    /* Set up NMI on errors */
+    byte = inb(0x61);
+    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+    byte &= ~(1 << 2); /* PCI SERR# Enable */
+    outb(byte, 0x61);
+    byte = inb(0x70);
+    nmi_option = NMI_OFF;
+    get_option(&nmi_option, "nmi");
+    if (nmi_option) {			
+        byte &= ~(1 << 7); /* set NMI */
+        outb(byte, 0x70);
+    }
 	
 	/* Initialize the real time clock */
 	i82801ca_rtc_init(dev);

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_smbus.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_smbus.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,7 +1,7 @@
 #include <smbus.h>
 #include <pci.h>
 #include <arch/io.h>
-#include "i82801ca.h"
+#include "i82801ca.h"
 
 #define PM_BUS 0
 #define PM_DEVFN PCI_DEVFN(0x1f,3)
@@ -9,7 +9,7 @@
 void smbus_enable(void)
 {
 	/* iobase addr */
-	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 
+	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 
 							   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
 	/* smbus enable */
 	pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,62 +1,57 @@
-/*
- * $Header$
- *
- * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+/*
+ * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/romcc_io.h>
 #include "lpc47b272.h"
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47B272's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47B272's configuration registers.
+//
 static inline void pnp_enter_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0x55, port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47B272's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47B272's configuration registers.
+//
 static void pnp_exit_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0xaa, port);
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47b272.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47b272.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
 static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_conf_state(dev);

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/superio.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47b272/superio.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,30 +1,25 @@
-/*
- * $Header$
- *
- * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
- *
+/*
+ * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
+ *
  * Copyright 2000  AG Electronics Ltd.
  * Copyright 2003-2004 Linux Networx
  * Copyright 2004 Tyan 
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/io.h>
 #include <device/device.h>
@@ -38,16 +33,16 @@
 #include "chip.h"
 #include "lpc47b272.h"
 
-// Forward declarations
-static void enable_dev(device_t dev);
+// Forward declarations
+static void enable_dev(device_t dev);
 void lpc47b272_pnp_set_resources(device_t dev);
 void lpc47b272_pnp_set_resources(device_t dev);
 void lpc47b272_pnp_enable_resources(device_t dev);
 void lpc47b272_pnp_enable(device_t dev);
 static void lpc47b272_init(device_t dev);
 
-static void pnp_enter_conf_state(device_t dev);
-static void pnp_exit_conf_state(device_t dev);
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
 static void dump_pnp_device(device_t dev);
 
 
@@ -73,31 +68,31 @@
         { &ops, LPC47B272_RT,   PNP_IO0, { 0x780, 0 }, },
 };
 
-/**********************************************************************************/
-/*								PUBLIC INTERFACE								  */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function:    	enable_dev
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Create device structures and allocate resources to devices 
-//					specified in the pnp_dev_info array (above).
-//
-static void enable_dev(device_t dev)
-{
-	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
-					   pnp_dev_info);
-}
+/**********************************************************************************/
+/*								PUBLIC INTERFACE								  */
+/**********************************************************************************/
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_pnp_set_resources
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Configure the specified Super I/O device with the resources
-//					(I/O space, etc.) that have been allocated for it.
+//----------------------------------------------------------------------------------
+// Function:    	enable_dev
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Create device structures and allocate resources to devices 
+//					specified in the pnp_dev_info array (above).
 //
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, 
+					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_pnp_set_resources
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Configure the specified Super I/O device with the resources
+//					(I/O space, etc.) that have been allocated for it.
+//
 void lpc47b272_pnp_set_resources(device_t dev)
 {
 	pnp_enter_conf_state(dev);  
@@ -126,14 +121,14 @@
 	pnp_exit_conf_state(dev);  
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_init
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Initialize the specified Super I/O device.
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_init
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Initialize the specified Super I/O device.
 //					Devices other than COM ports and the keyboard controller are 
-//					ignored. For COM ports, we configure the baud rate. 
-//
+//					ignored. For COM ports, we configure the baud rate. 
+//
 static void lpc47b272_init(device_t dev)
 {
 	struct superio_smsc_lpc47b272_config *conf = dev->chip_info;
@@ -160,68 +155,68 @@
 		break;
 	}
 }
-
-/**********************************************************************************/
-/*								PRIVATE FUNCTIONS							      */
-/**********************************************************************************/
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Enable access to the LPC47B272's configuration registers.
-//
-static void pnp_enter_conf_state(device_t dev) 
+/**********************************************************************************/
+/*								PRIVATE FUNCTIONS							      */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Enable access to the LPC47B272's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev) 
 {
 	outb(0x55, dev->path.u.pnp.port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Disable access to the LPC47B272's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) 
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Disable access to the LPC47B272's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) 
 {
     outb(0xaa, dev->path.u.pnp.port);
 }
 
 #if 0
-//----------------------------------------------------------------------------------
-// Function:    	dump_pnp_device
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Print the values of all of the LPC47B272's configuration registers.
-//					NOTE: The LPC47B272 must be in configuration mode when this
-//						  function is called.
-//
+//----------------------------------------------------------------------------------
+// Function:    	dump_pnp_device
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Print the values of all of the LPC47B272's configuration registers.
+//					NOTE: The LPC47B272 must be in configuration mode when this
+//						  function is called.
+//
 static void dump_pnp_device(device_t dev)
 {
     int register_index;
     print_debug("\r\n");
 
     for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
-        uint8_t register_value;
+        uint8_t register_value;
 
         if ((register_index & 0x0f) == 0) {
                 print_debug_hex8(register_index);
                 print_debug_char(':');
-        }
-
+        }
+
 		// Skip over 'register' that would cause exit from configuration mode
 	    if (register_index == 0xaa)
-			register_value = 0xaa;
+			register_value = 0xaa;
 		else
-        	register_value = pnp_read_config(dev, register_index);
-
+        	register_value = pnp_read_config(dev, register_index);
+
         print_debug_char(' ');
         print_debug_hex8(register_value);
         if ((register_index & 0x0f) == 0x0f) {
         	print_debug("\r\n");
         }
-    }
-
-   	print_debug("\r\n");
+    }
+
+   	print_debug("\r\n");
 }
 #endif

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,63 +1,58 @@
-/*
- * $Header$
- *
- * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
+/*
+ * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
  * derived from lpc47n217
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/romcc_io.h>
 #include "lpc47m10x.h"
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47M10X2's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47M10X2's configuration registers.
+//
 static inline void pnp_enter_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0x55, port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47M10X2's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47M10X2's configuration registers.
+//
 static void pnp_exit_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0xaa, port);
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47b272.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47b272.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
 static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_conf_state(dev);

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47m10x/superio.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,6 +1,4 @@
 /*
- * $Header$
- *
  * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
  *
  * Copyright 2000  AG Electronics Ltd.
@@ -22,9 +20,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
  */
 
 #include <arch/io.h>

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,155 +1,147 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $
- *
- * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: lpc47n217_early_serial.c,v $
- * Revision 1.1.1.1  2005/07/11 15:28:51  smagnani
- * Initial revision.
- *
- *
- */
-
-#include <arch/romcc_io.h>
-#include <assert.h>
-#include "lpc47n217.h"
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47N217's configuration registers.
-//
-static inline void pnp_enter_conf_state(device_t dev) {
-	unsigned port = dev>>8;
-    outb(0x55, port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47N217's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) {
-	unsigned port = dev>>8;
-    outb(0xaa, port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_iobase
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					iobase - base I/O port for the logical device
-// Return Value:	None
-// Description: 	Program the base I/O port for the specified logical device.
-//
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
-{
-	// LPC47N217 requires base ports to be a multiple of 4
-	ASSERT(!(iobase & 0x3));
-
-	switch(dev & 0xFF) {
-	case LPC47N217_PP: 
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP1: 
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-		
-	default:
-		break;
-	}
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_enable
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					enable - 0 to disable, anythig else to enable
-// Return Value:	None
-// Description: 	Enable or disable the specified logical device.
-//					Technically, a full disable requires setting the device's base
-//					I/O port below 0x100. We don't do that here, because we don't
-//					have access to a data structure that specifies what the 'real'
-//					base port is (when asked to enable the device). Also the function
-//					is used only to disable the device while its true base port is
-//					programmed (see lpc47n217_enable_serial() below).
-//
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
-	uint8_t power_register = 0;
-	uint8_t power_mask = 0;
-	uint8_t current_power;
-	uint8_t new_power;
-	
-	switch(dev & 0xFF) {
-	case LPC47N217_PP: 
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-		
-	case LPC47N217_SP1: 
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-		
-	case LPC47N217_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-		
-	default:
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask;		// disable by default
-
-	if (enable)
-		new_power |= power_mask;		// Enable
-
-	pnp_write_config(dev, power_register, new_power);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
-static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
-{
-	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-	
-	pnp_enter_conf_state(dev);
-	lpc47n217_pnp_set_enable(dev, 0);
-	lpc47n217_pnp_set_iobase(dev, iobase);
-	lpc47n217_pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
+/*
+ * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <arch/romcc_io.h>
+#include <assert.h>
+#include "lpc47n217.h"
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47N217's configuration registers.
+//
+static inline void pnp_enter_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0x55, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0xaa, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_iobase
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					iobase - base I/O port for the logical device
+// Return Value:	None
+// Description: 	Program the base I/O port for the specified logical device.
+//
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+	// LPC47N217 requires base ports to be a multiple of 4
+	ASSERT(!(iobase & 0x3));
+
+	switch(dev & 0xFF) {
+	case LPC47N217_PP: 
+		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP1: 
+		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP2:
+		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+		break;
+		
+	default:
+		break;
+	}
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_enable
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					enable - 0 to disable, anythig else to enable
+// Return Value:	None
+// Description: 	Enable or disable the specified logical device.
+//					Technically, a full disable requires setting the device's base
+//					I/O port below 0x100. We don't do that here, because we don't
+//					have access to a data structure that specifies what the 'real'
+//					base port is (when asked to enable the device). Also the function
+//					is used only to disable the device while its true base port is
+//					programmed (see lpc47n217_enable_serial() below).
+//
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+	uint8_t power_register = 0;
+	uint8_t power_mask = 0;
+	uint8_t current_power;
+	uint8_t new_power;
+	
+	switch(dev & 0xFF) {
+	case LPC47N217_PP: 
+		power_register = 0x01;
+		power_mask = 0x04;
+		break;
+		
+	case LPC47N217_SP1: 
+		power_register = 0x02;
+		power_mask = 0x08;
+		break;
+		
+	case LPC47N217_SP2:
+		power_register = 0x02;
+		power_mask = 0x80;
+		break;
+		
+	default:
+		return;
+	}
+
+	current_power = pnp_read_config(dev, power_register);
+	new_power = current_power & ~power_mask;		// disable by default
+
+	if (enable)
+		new_power |= power_mask;		// Enable
+
+	pnp_write_config(dev, power_register, new_power);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
+static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
+{
+	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+	
+	pnp_enter_conf_state(dev);
+	lpc47n217_pnp_set_enable(dev, 0);
+	lpc47n217_pnp_set_iobase(dev, iobase);
+	lpc47n217_pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}

Modified: trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/superio.c	2006-08-23 11:47:58 UTC (rev 2384)
+++ trunk/LinuxBIOSv2/src/superio/smsc/lpc47n217/superio.c	2006-08-23 14:28:37 UTC (rev 2385)
@@ -1,394 +1,386 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/superio.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $
- *
- * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
- *
- * Based on LinuxBIOS code for SMSC 47B397:
- * Copyright 2000  AG Electronics Ltd.
- * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan 
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: superio.c,v $
- * Revision 1.1.1.1  2005/07/11 15:28:51  smagnani
- * Initial revision.
- *
- *
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pnp.h>
-#include <console/console.h>
-#include <device/smbus.h>
-#include <string.h>
-#include <bitops.h>
-#include <uart8250.h>
-#include <assert.h>
-#include "chip.h"
-#include "lpc47n217.h"
-
-// Forward declarations
-static void enable_dev(device_t dev);
-void lpc47n217_pnp_set_resources(device_t dev);
-void lpc47n217_pnp_enable_resources(device_t dev);
-void lpc47n217_pnp_enable(device_t dev);
-static void lpc47n217_init(device_t dev);
-
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
-void lpc47n217_pnp_set_enable(device_t dev, int enable);
-
-static void pnp_enter_conf_state(device_t dev);
-static void pnp_exit_conf_state(device_t dev);
-
-
-struct chip_operations superio_smsc_lpc47n217_ops = {
-	CHIP_NAME("smsc lpc47n217")
-	.enable_dev = enable_dev,
-};
-
-static struct device_operations ops = {
-	.read_resources   = pnp_read_resources,
-	.set_resources    = lpc47n217_pnp_set_resources,
-	.enable_resources = lpc47n217_pnp_enable_resources,
-	.enable           = lpc47n217_pnp_enable,
-	.init             = lpc47n217_init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
-        { &ops, LPC47N217_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &ops, LPC47N217_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, LPC47N217_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
-};
-
-/**********************************************************************************/
-/*								PUBLIC INTERFACE								  */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function:    	enable_dev
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Create device structures and allocate resources to devices 
-//					specified in the pnp_dev_info array (above).
-//
-static void enable_dev(device_t dev)
-{
-	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
-					   pnp_dev_info);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_resources
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Configure the specified Super I/O device with the resources
-//					(I/O space, etc.) that have been allocate for it.
-//
-void lpc47n217_pnp_set_resources(device_t dev)
-{
-	int i;
-	
-	pnp_enter_conf_state(dev);  
-
-	// NOTE: Cannot use pnp_set_resources() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-	for(i = 0; i < dev->resources; i++)
-		lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
-
-//	dump_pnp_device(dev);
-                
-   	pnp_exit_conf_state(dev);  
-}       
-
-void lpc47n217_pnp_enable_resources(device_t dev)
-{       
-    pnp_enter_conf_state(dev);
-
-	// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-    lpc47n217_pnp_set_enable(dev, 1);
-
-    pnp_exit_conf_state(dev);
-}
-
-void lpc47n217_pnp_enable(device_t dev)
-{
-	pnp_enter_conf_state(dev);   
-
-	// NOTE: Cannot use pnp_set_enable() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-
-	if(dev->enabled) {
-		lpc47n217_pnp_set_enable(dev, 1);
-	}
-	else {
-		lpc47n217_pnp_set_enable(dev, 0);
-	}
-
-	pnp_exit_conf_state(dev);  
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_init
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Initialize the specified Super I/O device.
-//					Devices other than COM ports are ignored.
-//					For COM ports, we configure the baud rate. 
-//
-static void lpc47n217_init(device_t dev)
-{
-	struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
-	struct resource *res0;
-
-	if (!dev->enabled)
-		return;
-
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_SP1: 
-		res0 = find_resource(dev, PNP_IDX_IO0);
-		init_uart8250(res0->base, &conf->com1);
-		break;
-
-	case LPC47N217_SP2:
-		res0 = find_resource(dev, PNP_IDX_IO0);
-		init_uart8250(res0->base, &conf->com2);
-		break;
-	}
-}
-
-
-/**********************************************************************************/
-/*								PRIVATE FUNCTIONS							      */
-/**********************************************************************************/
-
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
-{
-	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02x not allocated\n",
-			dev_path(dev), resource->index);
-		return;
-	}
-
-	/* Now store the resource */
-	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-
-	if (resource->flags & IORESOURCE_IO) {
-		lpc47n217_pnp_set_iobase(dev, resource->base);
-	}
-	else if (resource->flags & IORESOURCE_DRQ) {
-		lpc47n217_pnp_set_drq(dev, resource->base);
-	}
-	else if (resource->flags  & IORESOURCE_IRQ) {
-		lpc47n217_pnp_set_irq(dev, resource->base);
-	}
-	else {
-		printk_err("ERROR: %s %02x unknown resource type\n",
-			dev_path(dev), resource->index);
-		return;
-	}
-	resource->flags |= IORESOURCE_STORED;
-
-	report_resource_stored(dev, resource, "");
-}
-
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
-{
-	ASSERT(!(iobase & 0x3));
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP1: 
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-		
-	default:
-		BUG();
-		break;
-	}
-}
-
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
-{
-	if (dev->path.u.pnp.device == LPC47N217_PP) {
-		const uint8_t PP_DMA_MASK = 0x0F;
-		const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
-		uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
-		uint8_t new_config;
-
-		ASSERT(!(drq & ~PP_DMA_MASK));		// DRQ out of range??		
-		new_config = (current_config & ~PP_DMA_MASK) | drq;
-		pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
-	} else {
-		BUG();
-	}
-}
-
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
-{
-	uint8_t irq_config_register = 0;
-	uint8_t irq_config_mask = 0;
-	uint8_t current_config;
-	uint8_t new_config;
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		irq_config_register = 0x27;
-		irq_config_mask = 0x0F;
-		break;
-		
-	case LPC47N217_SP1: 
-		irq_config_register = 0x28;
-		irq_config_mask = 0xF0;
-		irq <<= 4;
-		break;
-		
-	case LPC47N217_SP2:
-		irq_config_register = 0x28;
-		irq_config_mask = 0x0F;
-		break;
-		
-	default:
-		BUG();
-		return;
-	}
-
-	ASSERT(!(irq & ~irq_config_mask));		// IRQ out of range??
-	
-	current_config = pnp_read_config(dev, irq_config_register);
-	new_config = (current_config & ~irq_config_mask) | irq;
-	pnp_write_config(dev, irq_config_register, new_config);
-}
-
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
-	uint8_t power_register = 0;
-	uint8_t power_mask = 0;
-	uint8_t current_power;
-	uint8_t new_power;
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-		
-	case LPC47N217_SP1: 
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-		
-	case LPC47N217_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-		
-	default:
-		BUG();
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask;		// disable by default
-
-	if (enable) {
-		struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
-		lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
-		
-		new_power |= power_mask;		// Enable
-		
-    } else {
-		lpc47n217_pnp_set_iobase(dev, 0);
-	}
-	pnp_write_config(dev, power_register, new_power);
-}
-
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Enable access to the LPC47N217's configuration registers.
-//
-static void pnp_enter_conf_state(device_t dev) 
-{
-	outb(0x55, dev->path.u.pnp.port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Disable access to the LPC47N217's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) 
-{
-    outb(0xaa, dev->path.u.pnp.port);
-}
-
-#if 0
-//----------------------------------------------------------------------------------
-// Function:    	dump_pnp_device
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Print the values of all of the LPC47N217's configuration registers.
-//					NOTE: The LPC47N217 must be in configuration mode when this
-//						  function is called.
-//
-static void dump_pnp_device(device_t dev)
-{
-    int register_index;
-    print_debug("\r\n");
-
-    for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
-        uint8_t register_value;
-
-        if ((register_index & 0x0f) == 0) {
-                print_debug_hex8(register_index);
-                print_debug_char(':');
-        }
-
-		// Skip over 'register' that would cause exit from configuration mode
-	    if (register_index == 0xaa)
-			register_value = 0xaa;
-		else
-        	register_value = pnp_read_config(dev, register_index);
-
-        print_debug_char(' ');
-        print_debug_hex8(register_value);
-        if ((register_index & 0x0f) == 0x0f) {
-        	print_debug("\r\n");
-        }
-    }
-
-   	print_debug("\r\n");
-}
-#endif
+/*
+ * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Based on LinuxBIOS code for SMSC 47B397:
+ * Copyright 2000  AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan 
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <assert.h>
+#include "chip.h"
+#include "lpc47n217.h"
+
+// Forward declarations
+static void enable_dev(device_t dev);
+void lpc47n217_pnp_set_resources(device_t dev);
+void lpc47n217_pnp_enable_resources(device_t dev);
+void lpc47n217_pnp_enable(device_t dev);
+static void lpc47n217_init(device_t dev);
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
+void lpc47n217_pnp_set_enable(device_t dev, int enable);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+
+struct chip_operations superio_smsc_lpc47n217_ops = {
+	CHIP_NAME("smsc lpc47n217")
+	.enable_dev = enable_dev,
+};
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = lpc47n217_pnp_set_resources,
+	.enable_resources = lpc47n217_pnp_enable_resources,
+	.enable           = lpc47n217_pnp_enable,
+	.init             = lpc47n217_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+        { &ops, LPC47N217_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+        { &ops, LPC47N217_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+        { &ops, LPC47N217_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
+};
+
+/**********************************************************************************/
+/*								PUBLIC INTERFACE								  */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	enable_dev
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Create device structures and allocate resources to devices 
+//					specified in the pnp_dev_info array (above).
+//
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, 
+					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_resources
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Configure the specified Super I/O device with the resources
+//					(I/O space, etc.) that have been allocate for it.
+//
+void lpc47n217_pnp_set_resources(device_t dev)
+{
+	int i;
+	
+	pnp_enter_conf_state(dev);  
+
+	// NOTE: Cannot use pnp_set_resources() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+	for(i = 0; i < dev->resources; i++)
+		lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
+
+//	dump_pnp_device(dev);
+                
+   	pnp_exit_conf_state(dev);  
+}       
+
+void lpc47n217_pnp_enable_resources(device_t dev)
+{       
+    pnp_enter_conf_state(dev);
+
+	// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+    lpc47n217_pnp_set_enable(dev, 1);
+
+    pnp_exit_conf_state(dev);
+}
+
+void lpc47n217_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);   
+
+	// NOTE: Cannot use pnp_set_enable() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+
+	if(dev->enabled) {
+		lpc47n217_pnp_set_enable(dev, 1);
+	}
+	else {
+		lpc47n217_pnp_set_enable(dev, 0);
+	}
+
+	pnp_exit_conf_state(dev);  
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_init
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Initialize the specified Super I/O device.
+//					Devices other than COM ports are ignored.
+//					For COM ports, we configure the baud rate. 
+//
+static void lpc47n217_init(device_t dev)
+{
+	struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_SP1: 
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+
+	case LPC47N217_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	}
+}
+
+
+/**********************************************************************************/
+/*								PRIVATE FUNCTIONS							      */
+/**********************************************************************************/
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
+{
+	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		printk_err("ERROR: %s %02x not allocated\n",
+			dev_path(dev), resource->index);
+		return;
+	}
+
+	/* Now store the resource */
+	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+
+	if (resource->flags & IORESOURCE_IO) {
+		lpc47n217_pnp_set_iobase(dev, resource->base);
+	}
+	else if (resource->flags & IORESOURCE_DRQ) {
+		lpc47n217_pnp_set_drq(dev, resource->base);
+	}
+	else if (resource->flags  & IORESOURCE_IRQ) {
+		lpc47n217_pnp_set_irq(dev, resource->base);
+	}
+	else {
+		printk_err("ERROR: %s %02x unknown resource type\n",
+			dev_path(dev), resource->index);
+		return;
+	}
+	resource->flags |= IORESOURCE_STORED;
+
+	report_resource_stored(dev, resource, "");
+}
+
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+	ASSERT(!(iobase & 0x3));
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP1: 
+		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP2:
+		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+		break;
+		
+	default:
+		BUG();
+		break;
+	}
+}
+
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
+{
+	if (dev->path.u.pnp.device == LPC47N217_PP) {
+		const uint8_t PP_DMA_MASK = 0x0F;
+		const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
+		uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
+		uint8_t new_config;
+
+		ASSERT(!(drq & ~PP_DMA_MASK));		// DRQ out of range??		
+		new_config = (current_config & ~PP_DMA_MASK) | drq;
+		pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
+	} else {
+		BUG();
+	}
+}
+
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
+{
+	uint8_t irq_config_register = 0;
+	uint8_t irq_config_mask = 0;
+	uint8_t current_config;
+	uint8_t new_config;
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		irq_config_register = 0x27;
+		irq_config_mask = 0x0F;
+		break;
+		
+	case LPC47N217_SP1: 
+		irq_config_register = 0x28;
+		irq_config_mask = 0xF0;
+		irq <<= 4;
+		break;
+		
+	case LPC47N217_SP2:
+		irq_config_register = 0x28;
+		irq_config_mask = 0x0F;
+		break;
+		
+	default:
+		BUG();
+		return;
+	}
+
+	ASSERT(!(irq & ~irq_config_mask));		// IRQ out of range??
+	
+	current_config = pnp_read_config(dev, irq_config_register);
+	new_config = (current_config & ~irq_config_mask) | irq;
+	pnp_write_config(dev, irq_config_register, new_config);
+}
+
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+	uint8_t power_register = 0;
+	uint8_t power_mask = 0;
+	uint8_t current_power;
+	uint8_t new_power;
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		power_register = 0x01;
+		power_mask = 0x04;
+		break;
+		
+	case LPC47N217_SP1: 
+		power_register = 0x02;
+		power_mask = 0x08;
+		break;
+		
+	case LPC47N217_SP2:
+		power_register = 0x02;
+		power_mask = 0x80;
+		break;
+		
+	default:
+		BUG();
+		return;
+	}
+
+	current_power = pnp_read_config(dev, power_register);
+	new_power = current_power & ~power_mask;		// disable by default
+
+	if (enable) {
+		struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
+		lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
+		
+		new_power |= power_mask;		// Enable
+		
+    } else {
+		lpc47n217_pnp_set_iobase(dev, 0);
+	}
+	pnp_write_config(dev, power_register, new_power);
+}
+
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Enable access to the LPC47N217's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev) 
+{
+	outb(0x55, dev->path.u.pnp.port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) 
+{
+    outb(0xaa, dev->path.u.pnp.port);
+}
+
+#if 0
+//----------------------------------------------------------------------------------
+// Function:    	dump_pnp_device
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Print the values of all of the LPC47N217's configuration registers.
+//					NOTE: The LPC47N217 must be in configuration mode when this
+//						  function is called.
+//
+static void dump_pnp_device(device_t dev)
+{
+    int register_index;
+    print_debug("\r\n");
+
+    for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
+        uint8_t register_value;
+
+        if ((register_index & 0x0f) == 0) {
+                print_debug_hex8(register_index);
+                print_debug_char(':');
+        }
+
+		// Skip over 'register' that would cause exit from configuration mode
+	    if (register_index == 0xaa)
+			register_value = 0xaa;
+		else
+        	register_value = pnp_read_config(dev, register_index);
+
+        print_debug_char(' ');
+        print_debug_hex8(register_value);
+        if ((register_index & 0x0f) == 0x0f) {
+        	print_debug("\r\n");
+        }
+    }
+
+   	print_debug("\r\n");
+}
+#endif




From svn at openbios.org  Wed Aug 23 16:33:54 2006
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 23 Aug 2006 16:33:54 +0200
Subject: [LinuxBIOS] r2386 - trunk/LinuxBIOSv2/util/flashrom
Message-ID: <E1GFtnm-0004uc-UA@khepri.openbios.org>

Author: stepan
Date: 2006-08-23 16:33:54 +0200 (Wed, 23 Aug 2006)
New Revision: 2386

Modified:
   trunk/LinuxBIOSv2/util/flashrom/82802ab.c
   trunk/LinuxBIOSv2/util/flashrom/jedec.c
   trunk/LinuxBIOSv2/util/flashrom/m29f400bt.c
   trunk/LinuxBIOSv2/util/flashrom/mx29f002.c
   trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c
   trunk/LinuxBIOSv2/util/flashrom/sst39sf020.c
   trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c
   trunk/LinuxBIOSv2/util/flashrom/w49f002u.c
Log:
Removing $Id$ tags as they have no meaning in SVN


Modified: trunk/LinuxBIOSv2/util/flashrom/82802ab.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/82802ab.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/82802ab.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -21,7 +21,6 @@
  *
  * Reference: http://www.intel.com/design/chipsets/datashts/290658.htm
  *
- * $Id$
  */
 
 #include <errno.h>

Modified: trunk/LinuxBIOSv2/util/flashrom/jedec.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/jedec.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/jedec.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -21,7 +21,6 @@
  *
  * Reference:
  *
- * $Id$
  */
 
 #include <stdio.h>

Modified: trunk/LinuxBIOSv2/util/flashrom/m29f400bt.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/m29f400bt.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/m29f400bt.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -21,7 +21,6 @@
  *
  * Reference:
  *
- * $Id$
  */
 
 #include "flash.h"

Modified: trunk/LinuxBIOSv2/util/flashrom/mx29f002.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/mx29f002.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/mx29f002.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -22,7 +22,6 @@
  * Reference:
  *	MX29F002/002N data sheet
  *
- * $Id$
  */
 
 #include <stdio.h>

Modified: trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -20,8 +20,6 @@
  *
  *
  * Reference: http://www.intel.com/design/chipsets/datashts/290658.htm
- *
- * $Id: lhf00l04.c 2111 2005-11-26 21:55:36Z ollie $
  */
 
 #include <errno.h>

Modified: trunk/LinuxBIOSv2/util/flashrom/sst39sf020.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/sst39sf020.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/sst39sf020.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -24,7 +24,6 @@
  *
  * ToDo: Consilidated to standard JEDEC code.
  *
- * $Id$
  */
 
 #include <stdio.h>

Modified: trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -23,7 +23,6 @@
  *
  * ToDo: Consilidated to standard JEDEC code.
  *
- * $Id$
  */
 #include <stdio.h>
 #include "flash.h"

Modified: trunk/LinuxBIOSv2/util/flashrom/w49f002u.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/w49f002u.c	2006-08-23 14:28:37 UTC (rev 2385)
+++ trunk/LinuxBIOSv2/util/flashrom/w49f002u.c	2006-08-23 14:33:54 UTC (rev 2386)
@@ -24,7 +24,6 @@
  *
  * ToDo: Consilidated to standard JEDEC code.
  *
- * $Id$
  */
 
 #include <stdio.h>




From rogelio.serrano at gmail.com  Wed Aug 23 17:54:53 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Wed, 23 Aug 2006 23:54:53 +0800
Subject: [LinuxBIOS] pci base registers
Message-ID: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>

does linuxbios use the acpi tables to figure out where to find the pci
base registers?

and how are the dram config registers accessed in epia-m? is it
directly or via pci host bridge configuration registers?

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From smithbone at gmail.com  Wed Aug 23 18:05:10 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 23 Aug 2006 11:05:10 -0500
Subject: [LinuxBIOS] pci base registers
In-Reply-To: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>
References: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>
Message-ID: <8a0c36780608230905t38f86151yc89bbfc4f8f988f7@mail.gmail.com>

On 8/23/06, Rogelio Serrano <rogelio.serrano at gmail.com> wrote:

> does linuxbios use the acpi tables to figure out where to find the pci
> base registers?

No.  acpi tables are subject to copyright from the mfg and might be
restricted on distribution.

> and how are the dram config registers accessed in epia-m? is it
> directly or via pci host bridge configuration registers?

I'm not sure I understand what you are asking.  Can you point me to
the code that you are asking about?

-- 
Richard A. Smith



From rogelio.serrano at gmail.com  Wed Aug 23 18:26:47 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Thu, 24 Aug 2006 00:26:47 +0800
Subject: [LinuxBIOS] pci base registers
In-Reply-To: <8a0c36780608230905t38f86151yc89bbfc4f8f988f7@mail.gmail.com>
References: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>
	<8a0c36780608230905t38f86151yc89bbfc4f8f988f7@mail.gmail.com>
Message-ID: <a9951d2a0608230926u59bd37bahccbb34171dec7d12@mail.gmail.com>

On 8/24/06, Richard Smith <smithbone at gmail.com> wrote:
> On 8/23/06, Rogelio Serrano <rogelio.serrano at gmail.com> wrote:
>
> > does linuxbios use the acpi tables to figure out where to find the pci
> > base registers?
>
> No.  acpi tables are subject to copyright from the mfg and might be
> restricted on distribution.
>
> > and how are the dram config registers accessed in epia-m? is it
> > directly or via pci host bridge configuration registers?
>
> I'm not sure I understand what you are asking.  Can you point me to
> the code that you are asking about?
>
> --
> Richard A. Smith
>

im really confused where dram configuration is being done in the
epia-m. is it in raminit.c? I thought we cannot use c code until dram
is set up.

i resorted to reading the acpi and amd bios manuals and got even more confused.

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From smithbone at gmail.com  Wed Aug 23 18:45:01 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 23 Aug 2006 11:45:01 -0500
Subject: [LinuxBIOS] pci base registers
In-Reply-To: <a9951d2a0608230926u59bd37bahccbb34171dec7d12@mail.gmail.com>
References: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>
	<8a0c36780608230905t38f86151yc89bbfc4f8f988f7@mail.gmail.com>
	<a9951d2a0608230926u59bd37bahccbb34171dec7d12@mail.gmail.com>
Message-ID: <8a0c36780608230945v2c9ec407p67650d7d3851b288@mail.gmail.com>

>
> im really confused where dram configuration is being done in the
> epia-m. is it in raminit.c? I thought we cannot use c code until dram
> is set up.

Welcom to the most difficult part of linuxbios. :)

We can't run _normal_ C code.  But we have romcc.  romcc is a C
compiler that is designed to run without RAM.  Its uses CPU registers
only.

The raminit.c and .h code is the code you want to look at.

> i resorted to reading the acpi and amd bios manuals and got even more confused.

Yeah.  Avoid acpi if you can .

-- 
Richard A. Smith



From rogelio.serrano at gmail.com  Wed Aug 23 18:49:38 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Thu, 24 Aug 2006 00:49:38 +0800
Subject: [LinuxBIOS] pci base registers
In-Reply-To: <8a0c36780608230945v2c9ec407p67650d7d3851b288@mail.gmail.com>
References: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>
	<8a0c36780608230905t38f86151yc89bbfc4f8f988f7@mail.gmail.com>
	<a9951d2a0608230926u59bd37bahccbb34171dec7d12@mail.gmail.com>
	<8a0c36780608230945v2c9ec407p67650d7d3851b288@mail.gmail.com>
Message-ID: <a9951d2a0608230949y2d88ace2i9d15c3402d8d5fdc@mail.gmail.com>

On 8/24/06, Richard Smith <smithbone at gmail.com> wrote:
> >
> > im really confused where dram configuration is being done in the
> > epia-m. is it in raminit.c? I thought we cannot use c code until dram
> > is set up.
>
> Welcom to the most difficult part of linuxbios. :)
>
> We can't run _normal_ C code.  But we have romcc.  romcc is a C
> compiler that is designed to run without RAM.  Its uses CPU registers
> only.
>
> The raminit.c and .h code is the code you want to look at.

I see! Thanks!

Thats really smart!

>
> > i resorted to reading the acpi and amd bios manuals and got even more confused.
>
> Yeah.  Avoid acpi if you can .
>
> --
> Richard A. Smith
>



-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From stepan at coresystems.de  Wed Aug 23 21:21:59 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 23 Aug 2006 21:21:59 +0200
Subject: [LinuxBIOS] pci base registers
In-Reply-To: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>
References: <a9951d2a0608230854y76b19970m88c7dec1a7f14b69@mail.gmail.com>
Message-ID: <20060823192159.GA9998@coresystems.de>

* Rogelio Serrano <rogelio.serrano at gmail.com> [060823 17:54]:
> does linuxbios use the acpi tables to figure out where to find the pci
> base registers?

no. they are cfc/cf8 on all PC architectures. No need for ACPI bloat.

   Stefan



From stepan at coresystems.de  Thu Aug 24 01:25:54 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 24 Aug 2006 01:25:54 +0200
Subject: [LinuxBIOS] Register now for LinuxBIOS symposium '06!
In-Reply-To: <20060810154443.GA5827@coresystems.de>
References: <20060810154443.GA5827@coresystems.de>
Message-ID: <20060823232554.GA16985@coresystems.de>

Dear LinuxBIOS community,

This is a reminder to join the LinuxBIOS symposium 2006 in Hamburg,
Germany in October!

On October 1-3, 2006 we invite you to join the firmware revolution 
and participate in the LinuxBIOS Symposium 2006. 

Find more information on the web site 

        http://linuxbios.eu/

We hope to have vendor talks, and discussions on where we as a community
are going with linuxbios. 

So if you have something interesting to say, LinuxBIOS use cases,
applications, plans for the future, do register now!

Enjoy a couple of interesting and nice days in Hamburg. The free and
hanseatic city of Hamburg boasts 31 theatres, 6 music halls, 10 cabarets
and 50 state and private museums. Of the 4,000 restaurants, 2,400 offer
foreign cuisine.

Do consider coming! We'd like to see all of you folks out here. 

The Symposium will take place in the the Speicherstadt, an ancient
brick-built warehouse complex. The Speicherstadt is the historical
center of the port of Hamburg. Still today the smell of roasted coffee
and exotic spices lies in the air, experience unforgettable events in an
authentic hanseatic setting.

Vendors on this list, if you have something you'd like to talk about, 
please get back to me.

Thanks,

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From fredrik at dolda2000.com  Thu Aug 24 01:35:53 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Thu, 24 Aug 2006 01:35:53 +0200
Subject: [LinuxBIOS] [PATCH] ST M29F040B flash_and_burn driver
Message-ID: <1156376153.28040.56.camel@pc7.dolda2000.com>

I bought a M29F040B 4 Mib flash chip for my EPIA-V motherboard today in
order to get LinuxBIOS on it, and found that flash_and_burn didn't
support it. So, I got the datasheet and modified a copy of the M29F400BT
driver to work with it.

I make no guarantees, of course, but it seems to Work For Me (TM), so I
thought you might want to include it. I haven't managed to get LinuxBIOS
working yet, though, but burning the original BIOS to it works and
boots.

I'm attaching the patch as MIME.

Fredrik Tolf

-------------- next part --------------
A non-text attachment was scrubbed...
Name: lb-m29f040b.patch
Type: text/x-patch
Size: 7544 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060824/045e44cb/attachment.patch>

From smithbone at gmail.com  Thu Aug 24 01:52:00 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 23 Aug 2006 18:52:00 -0500
Subject: [LinuxBIOS] [PATCH] ST M29F040B flash_and_burn driver
In-Reply-To: <1156376153.28040.56.camel@pc7.dolda2000.com>
References: <1156376153.28040.56.camel@pc7.dolda2000.com>
Message-ID: <8a0c36780608231652s2f068d64tfc7f2b9ea2d278be@mail.gmail.com>

On 8/23/06, Fredrik Tolf <fredrik at dolda2000.com> wrote:
> I bought a M29F040B 4 Mib flash chip for my EPIA-V motherboard today in
> order to get LinuxBIOS on it, and found that flash_and_burn didn't
> support it. So, I got the datasheet and modified a copy of the M29F400BT
> driver to work with it.

How is this part different from the am29f040b?  The programming
sequences look mostly the same.

-- 
Richard A. Smith



From fredrik at dolda2000.com  Thu Aug 24 01:52:01 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Thu, 24 Aug 2006 01:52:01 +0200
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
Message-ID: <1156377121.16966.6.camel@pc7.dolda2000.com>

Hi list!

I've been trying to get LinuxBIOS to boot on my EPIA-V motherboard (VIA
8601A NB, VT8231 SB), and at first I followed the bundled HOWTO for the
EPIA-M, before I discovered that EPIA-V was an entirely different
creatures (it uses SDRAM, whereas I believe that the EPIA-M uses DDRAM),
and the EPIA-M BIOS didn't boot, of course.

However, I've tried a number of different variations of the via/epia
configuration now, and it doesn't seem to want to boot whatever I do.
The new flash chip I used is a 512 KiB chip, as opposed to the original
256 KiB chip (which isn't a problem, though, because if I burn the
original BIOS to it with a 256 KiB block from /dev/zero prepended to it,
it boots just fine), so I tried the 512kbflash config file as well, but
to no avail.

I'm using FILO as the payload.

I'm beginning to run out of options, and I don't know how to diagnose
LinuxBIOS. The monitor doesn't turn on, so I'm guessing it might be
something to do with the VGA BIOS. In the EPIA-M HOWTO it said to
prepend the LinuxBIOS image with the original 64 KiB VGA BIOS image --
is that the same for the EPIA-V (and in that case, how would I do to
generate a LinuxBIOS image that is suitable for prepending with the VGA
BIOS)?

Thank you for your time!

Fredrik Tolf





From stepan at coresystems.de  Thu Aug 24 01:56:53 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 24 Aug 2006 01:56:53 +0200
Subject: [LinuxBIOS] [PATCH] ST M29F040B flash_and_burn driver
In-Reply-To: <1156376153.28040.56.camel@pc7.dolda2000.com>
References: <1156376153.28040.56.camel@pc7.dolda2000.com>
Message-ID: <20060823235653.GB31736@coresystems.de>

* Fredrik Tolf <fredrik at dolda2000.com> [060824 01:35]:
> I bought a M29F040B 4 Mib flash chip for my EPIA-V motherboard today in
> order to get LinuxBIOS on it, and found that flash_and_burn didn't
> support it. So, I got the datasheet and modified a copy of the M29F400BT
> driver to work with it.
> 
> I make no guarantees, of course, but it seems to Work For Me (TM), so I
> thought you might want to include it. I haven't managed to get LinuxBIOS
> working yet, though, but burning the original BIOS to it works and
> boots.
> 
> I'm attaching the patch as MIME.

Can you remake the patch for the flashrom utility from LinuxBIOSv2
please?


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From smithbone at gmail.com  Thu Aug 24 02:02:29 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 23 Aug 2006 19:02:29 -0500
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <1156377121.16966.6.camel@pc7.dolda2000.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
Message-ID: <8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>

> I've been trying to get LinuxBIOS to boot on my EPIA-V motherboard (VIA
> 8601A NB, VT8231 SB), and at first I followed the bundled HOWTO for the

The 8601A is broken and we don't know why.  It won't setup the RAM
correctly anymore.

Sorry.. We really need to put this on the wiki.  Use a serial console
and enable the RAM test.  you will see the failures.

If you feel up to the task of debugging it we will try to help though.

-- 
Richard A. Smith



From fredrik at dolda2000.com  Thu Aug 24 02:09:05 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Thu, 24 Aug 2006 02:09:05 +0200
Subject: [LinuxBIOS] [PATCH] ST M29F040B flash_and_burn driver
In-Reply-To: <8a0c36780608231652s2f068d64tfc7f2b9ea2d278be@mail.gmail.com>
References: <1156376153.28040.56.camel@pc7.dolda2000.com>
	<8a0c36780608231652s2f068d64tfc7f2b9ea2d278be@mail.gmail.com>
Message-ID: <1156378145.16966.9.camel@pc7.dolda2000.com>

On Wed, 2006-08-23 at 18:52 -0500, Richard Smith wrote:
> On 8/23/06, Fredrik Tolf <fredrik at dolda2000.com> wrote:
> > I bought a M29F040B 4 Mib flash chip for my EPIA-V motherboard today in
> > order to get LinuxBIOS on it, and found that flash_and_burn didn't
> > support it. So, I got the datasheet and modified a copy of the M29F400BT
> > driver to work with it.
> 
> How is this part different from the am29f040b?  The programming
> sequences look mostly the same.

Mostly, indeed. There are a couple of differences, though, the most
important being that the address sequence as 555, 2AA, 555 instead of
AAA, 555, AAA. Then there are a couple of other differences as well,
such as when reading the product code, and the fact that the block
layout is uniform. There may have been some other things as well, but I
don't quite remember.

Fredrik Tolf





From smithbone at gmail.com  Thu Aug 24 02:16:06 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 23 Aug 2006 19:16:06 -0500
Subject: [LinuxBIOS] [PATCH] ST M29F040B flash_and_burn driver
In-Reply-To: <1156378145.16966.9.camel@pc7.dolda2000.com>
References: <1156376153.28040.56.camel@pc7.dolda2000.com>
	<8a0c36780608231652s2f068d64tfc7f2b9ea2d278be@mail.gmail.com>
	<1156378145.16966.9.camel@pc7.dolda2000.com>
Message-ID: <8a0c36780608231716u55d1f084gea7368e364ed562@mail.gmail.com>

> Mostly, indeed. There are a couple of differences, though, the most
> important being that the address sequence as 555, 2AA, 555 instead of
> AAA, 555, AAA. Then there are a couple of other differences as well,
> such as when reading the product code, and the fact that the block
> layout is uniform. There may have been some other things as well, but I
> don't quite remember.

Ok.. Just checking.  Great. Thanks for the patch.

-- 
Richard A. Smith



From fredrik at dolda2000.com  Thu Aug 24 02:31:23 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Thu, 24 Aug 2006 02:31:23 +0200
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
Message-ID: <1156379483.16966.20.camel@pc7.dolda2000.com>

On Wed, 2006-08-23 at 19:02 -0500, Richard Smith wrote:
> > I've been trying to get LinuxBIOS to boot on my EPIA-V motherboard (VIA
> > 8601A NB, VT8231 SB), and at first I followed the bundled HOWTO for the
> 
> The 8601A is broken and we don't know why.  It won't setup the RAM
> correctly anymore.

Does "anymore" mean that it was working at some point?

> Sorry.. We really need to put this on the wiki.  Use a serial console
> and enable the RAM test.  you will see the failures.
> 
> If you feel up to the task of debugging it we will try to help though.

That would be great. I'd just like to ask if anyone has any docs on it
or something?

Another question, if it's OK -- I don't really know how all this VGA
stuff works. When is the monitor supposed to be turned on, and what code
is it that takes care of that stuff?

Fredrik Tolf





From fredrik at dolda2000.com  Thu Aug 24 02:24:02 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Thu, 24 Aug 2006 02:24:02 +0200
Subject: [LinuxBIOS] [PATCH] ST M29F040B flash_and_burn driver
In-Reply-To: <8a0c36780608231716u55d1f084gea7368e364ed562@mail.gmail.com>
References: <1156376153.28040.56.camel@pc7.dolda2000.com>
	<8a0c36780608231652s2f068d64tfc7f2b9ea2d278be@mail.gmail.com>
	<1156378145.16966.9.camel@pc7.dolda2000.com>
	<8a0c36780608231716u55d1f084gea7368e364ed562@mail.gmail.com>
Message-ID: <1156379043.16966.14.camel@pc7.dolda2000.com>

On Wed, 2006-08-23 at 19:16 -0500, Richard Smith wrote:
> > [Snipped my senseless rambling]
> > 
> Ok.. Just checking.  Great. Thanks for the patch.

Sorry, I misread you as asking how it was different from the M29F400BT.
Actually, I hadn't checked the flashrom utility in the trunk, and it
appears someone got there before me. The existing driver worked
perfectly for my chip.

Fredrik Tolf





From smithbone at gmail.com  Thu Aug 24 03:04:36 2006
From: smithbone at gmail.com (Richard Smith)
Date: Wed, 23 Aug 2006 20:04:36 -0500
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <1156379483.16966.20.camel@pc7.dolda2000.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
Message-ID: <8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>

> Does "anymore" mean that it was working at some point?

Yes. But some commit somewhere broke it.  But nobody has yet to find
the breaking point.

> That would be great. I'd just like to ask if anyone has any docs on it
> or something?

Yeah... I've got some somewhere... Let me look. Somebody send me a
copy a while ago.

> Another question, if it's OK

Perfectly fine.

>-- I don't really know how all this VGA
> stuff works. When is the monitor supposed to be turned on, and what code
> is it that takes care of that stuff?

Well most of the time it dosen't. :)  VGA is always the last thing
because it tricky to get going.  RAM has to happen first.   Use the
serial link.  Are you getting any serial output?

-- 
Richard A. Smith



From fredrik at dolda2000.com  Thu Aug 24 03:12:02 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Thu, 24 Aug 2006 03:12:02 +0200
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
Message-ID: <1156381922.16966.27.camel@pc7.dolda2000.com>

On Wed, 2006-08-23 at 20:04 -0500, Richard Smith wrote:
> > Does "anymore" mean that it was working at some point?
> 
> Yes. But some commit somewhere broke it.  But nobody has yet to find
> the breaking point.

That's good news, I guess. :) Would you have any idea whatsoever of any
time it did work? If so, I could much more easily look for when it
broke.

> > That would be great. I'd just like to ask if anyone has any docs on it
> > or something?
> 
> Yeah... I've got some somewhere... Let me look. Somebody send me a
> copy a while ago.

It would be great if I could get a copy!

> >-- I don't really know how all this VGA
> > stuff works. When is the monitor supposed to be turned on, and what code
> > is it that takes care of that stuff?
> 
> Well most of the time it dosen't. :)  VGA is always the last thing
> because it tricky to get going.  RAM has to happen first.

I was actually under the impression that the video card might turn
itself on without CPU intervention. :)

> Use the
> serial link.  Are you getting any serial output?

No, not yet. I've only been trying for a couple of hours yet and have
been overly optimistic. Therefore I haven't yet built myself a null
modem cable. I'll get my hands on a couple of D-Subs first thing I do
tomorrow. It's getting late right over here now.

Thank you very much for all your help so far!

Fredrik Tolf





From rogelio.serrano at gmail.com  Fri Aug 25 02:50:06 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Fri, 25 Aug 2006 08:50:06 +0800
Subject: [LinuxBIOS] testing with system emulator
Message-ID: <a9951d2a0608241750h61965815l8a45d284dcbafbb6@mail.gmail.com>

Is there an emulator that we can use for development and testing?
Something that i can customise with registers to look like my
motherboard?

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From yinghai.lu at amd.com  Fri Aug 25 02:56:45 2006
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Thu, 24 Aug 2006 17:56:45 -0700
Subject: [LinuxBIOS] testing with system emulator
Message-ID: <6F7DA19D05F3CF40B890C7CA2DB13A420700418D@ssvlexmb2.amd.com>

You can get AMD SimNow. There is one public version that you can
download for AMD web.

YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Rogelio Serrano
Sent: Thursday, August 24, 2006 5:50 PM
To: linuxbios at linuxbios.org
Subject: [LinuxBIOS] testing with system emulator

Is there an emulator that we can use for development and testing?
Something that i can customise with registers to look like my
motherboard?

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself

-- 
linuxbios mailing list
linuxbios at linuxbios.org
http://www.openbios.org/mailman/listinfo/linuxbios







From smithbone at gmail.com  Fri Aug 25 03:19:44 2006
From: smithbone at gmail.com (Richard Smith)
Date: Thu, 24 Aug 2006 20:19:44 -0500
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <1156468594.16966.32.camel@pc7.dolda2000.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
	<1156468594.16966.32.camel@pc7.dolda2000.com>
Message-ID: <8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>

> 0000360  \0  \0  \0 340  \0 340  \0 340 340 340  \0 340  \0  \0 340  \0
> 0000400 340 340 340  \0 340 340  \0 340 340 340  \0 340  \0 340  \0  \0
> 0000420 340  \0  \0 340  \0 340 340  \0  \0 340  \0  \0 340 340  \0 340
> 0000440 340  \0  \0  \0 340  \0  \0  \0 340  \0  \0  \0  \0 340  \0 340
> 0000460 340  \0 340 340 340  \0 340 340  \0 340 340  \0  \0 340  \0 340
> 0000500  \0 340 340 340  \0 340  \0  \0 340  \0 340 340 340  \0 340 340
> 0000520  \0 340 340 340  \0 340 340 340  \0  \0 340  \0
>
> Is this somehow wrong, or am I supposed to use some program to decode
> it?

Nope its all ASCII.  I think you have a baud rate problem 115200,N,8,1
-- 
Richard A. Smith



From fredrik at dolda2000.com  Fri Aug 25 03:16:34 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Fri, 25 Aug 2006 03:16:34 +0200
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
Message-ID: <1156468594.16966.32.camel@pc7.dolda2000.com>

On Wed, 2006-08-23 at 20:04 -0500, Richard Smith wrote:
> Are you getting any serial output?

OK, I actually got myself a null modem cable now, but I don't really
understand the output from LinuxBIOS, or if it's even supposed to be
what it is... here is how it looks if I pipe it through od -t c:

0000000 340  \0 340  \0  \0 340 340 340 340 340 340 340 340 340 340 340
0000020 340  \0 340 340  \0  \0  \0 340 340 340 340 340 340 340 340 340
0000040 340  \0 340  \0  \0 340 340 340 340 340 340 340 340 340 340 340
0000060 340  \0 340 340  \0  \0  \0 340 340 340 340 340 340 340 340 340
0000100 340 340  \0  \0 340  \0 340 340  \0  \0 340  \0  \0  \0 340 340
0000120  \0 340 340  \0 340 340 340 340 340 340  \0 340  \0  \0 340 340
0000140  \0  \0 340 340  \0 340 340  \0 340 340 340 340 340  \0 340  \0
0000160  \0  \0 340  \0 340  \0  \0  \0 340  \0  \0  \0  \0 340  \0  \0
0000200  \0  \0  \0 340 340  \0 340  \0 340 340  \0 340 340  \0  \0 340
0000220 340  \0 340 340  \0 340 340 340 340 340  \0  \0  \0 340 340 340
0000240  \0 340 340 340 340 340 340  \0  \0 340  \0 340 340 340 340 340
0000260 340  \0 340  \0  \0  \0  \0  \0  \0 340  \0  \0  \0  \0  \0 340
0000300  \0  \0  \0 340  \0 340  \0  \0 340  \0  \0  \0 340  \0 340  \0
0000320  \0  \0 340  \0  \0  \0 340  \0 340 340 340  \0 340 340  \0 340
0000340 340  \0 340 340 340  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0 340
0000360  \0  \0  \0 340  \0 340  \0 340 340 340  \0 340  \0  \0 340  \0
0000400 340 340 340  \0 340 340  \0 340 340 340  \0 340  \0 340  \0  \0
0000420 340  \0  \0 340  \0 340 340  \0  \0 340  \0  \0 340 340  \0 340
0000440 340  \0  \0  \0 340  \0  \0  \0 340  \0  \0  \0  \0 340  \0 340
0000460 340  \0 340 340 340  \0 340 340  \0 340 340  \0  \0 340  \0 340
0000500  \0 340 340 340  \0 340  \0  \0 340  \0 340 340 340  \0 340 340
0000520  \0 340 340 340  \0 340 340 340  \0  \0 340  \0

Is this somehow wrong, or am I supposed to use some program to decode
it?

Fredrik Tolf





From uwe at hermann-uwe.de  Fri Aug 25 03:59:26 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 25 Aug 2006 03:59:26 +0200
Subject: [LinuxBIOS] PATCH: IT8673F Super IO support.
Message-ID: <20060825015926.GA28007@aragorn>

Hi,

here's a patch which adds support for the IT8673F Super IO. I cannot
test it at the moment (other than that it builds), but it's reasonably
similar to the IT8671F, so I think it should work (given that I didn't
miss anything important in the datasheet).


HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/superio/ite/it8673f/it8673f.h
===================================================================
--- src/superio/ite/it8673f/it8673f.h	(Revision 0)
+++ src/superio/ite/it8673f/it8673f.h	(Revision 0)
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define IT8673F_FDC  0x00 /* Floppy */
+#define IT8673F_SP1  0x01 /* Com1 */
+#define IT8673F_SP2  0x02 /* Com2 */
+#define IT8673F_PP   0x03 /* Parallel port */
+#define IT8673F_FAN  0x04 /* Fan controller */
+#define IT8673F_KBCK 0x05 /* Keyboard */
+#define IT8673F_KBCM 0x06 /* Mouse */
+
Index: src/superio/ite/it8673f/Config.lb
===================================================================
--- src/superio/ite/it8673f/Config.lb	(Revision 0)
+++ src/superio/ite/it8673f/Config.lb	(Revision 0)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
Index: src/superio/ite/it8673f/it8673f_early_serial.c
===================================================================
--- src/superio/ite/it8673f/it8673f_early_serial.c	(Revision 0)
+++ src/superio/ite/it8673f/it8673f_early_serial.c	(Revision 0)
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8673f.h"
+
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE                    0x3f0
+#define SIO_INDEX                   SIO_BASE
+#define SIO_DATA                    SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8673F_CONFIG_REG_CC       0x02   /* Configure Control (write-only). */
+#define IT8673F_CONFIG_REG_LDN      0x07   /* Logical Device Number. */
+#define IT8673F_CONFIG_REG_CLOCKSEL 0x23   /* Clock Selection. */
+#define IT8673F_CONFIG_REG_SWSUSP   0x24   /* Software Suspend. */
+
+#define IT8673F_CONFIGURATION_PORT  0x0279 /* Write-only. */
+
+/* Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data. */
+static const uint8_t init_values[] = {
+	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+/* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8673F Super IO chip. */
+static void it8673f_enable_serial(device_t dev, unsigned iobase)
+{
+	uint8_t i;
+
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+	outb(0x86, IT8673F_CONFIGURATION_PORT);
+	outb(0x80, IT8673F_CONFIGURATION_PORT);
+	outb(0x55, IT8673F_CONFIGURATION_PORT);
+	outb(0x55, IT8673F_CONFIGURATION_PORT);
+
+	/* Sequentially write the 32 special values. */
+	for (i = 0; i < 32; i++) {
+		outb(init_values[i], SIO_BASE);
+	}
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Enable all devices. */
+	it8673f_sio_write(IT8673F_FDC,  0x30, 0x1); /* Floppy */
+	it8673f_sio_write(IT8673F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8673f_sio_write(IT8673F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8673f_sio_write(IT8673F_PP,   0x30, 0x1); /* Parallel port */
+	it8673f_sio_write(IT8673F_FAN,  0x30, 0x1); /* Fan controller */
+	it8673f_sio_write(IT8673F_KBCK, 0x30, 0x1); /* Keyboard */
+	it8673f_sio_write(IT8673F_KBCM, 0x30, 0x1); /* Mouse */
+
+	/* Select 24MHz CLKIN (clear bit 0). TODO: is this really needed? */
+	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00);
+
+	/* Clear software suspend mode (clear bit 0). */
+	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00);
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02); 
+}
+
Index: src/superio/ite/it8673f/superio.c
===================================================================
--- src/superio/ite/it8673f/superio.c	(Revision 0)
+++ src/superio/ite/it8673f/superio.c	(Revision 0)
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "it8673f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8673f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8673F_FDC: /* TODO. */
+		break;
+	case IT8673F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8673F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8673F_PP: /* TODO. */
+		break;
+	case IT8673F_FAN: /* TODO. */
+		break;
+	case IT8673F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	case IT8673F_KBCM: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, FAN, KBCM. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8673F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8673F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, IT8673F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8673f_ops = {
+	CHIP_NAME("ITE it8673f")
+	.enable_dev = enable_dev,
+};
+
Index: src/superio/ite/it8673f/chip.h
===================================================================
--- src/superio/ite/it8673f/chip.h	(Revision 0)
+++ src/superio/ite/it8673f/chip.h	(Revision 0)
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8673F
+#define _SUPERIO_ITE_IT8673F
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8673f_ops;
+
+struct superio_ITE_it8673f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif /* _SUPERIO_ITE_IT8673F */
+
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060825/71b56083/attachment.sig>

From smithbone at gmail.com  Fri Aug 25 04:50:06 2006
From: smithbone at gmail.com (Richard Smith)
Date: Thu, 24 Aug 2006 21:50:06 -0500
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <1156471054.16966.42.camel@pc7.dolda2000.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
	<1156468594.16966.32.camel@pc7.dolda2000.com>
	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>
	<1156471054.16966.42.camel@pc7.dolda2000.com>
Message-ID: <8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>

On 8/24/06, Fredrik Tolf <fredrik at dolda2000.com> wrote:
>
> It was indeed set to 115200 N81, but I just experimented a bit and found
> that it worked on 19200 baud (with some garbage at the top, though). :)

Oh thats right.. There is some freaky divider issue with the EPIA...
Need to document that somewhere.

> Slot 00 is SDRAM 08000000 bytes ^M$
> 0100 is the chip size^M$
> 000e is the MA type^M$
> Slot 01 is empty^M$
> Slot 02 is empty^M$
> Slot 03 is empty^M$
> vt8601 done^M$
> Copying LinuxBIOS to ram.^M$
> Jumping to LinuxBIOS.^M$
>
> I guess that's a pretty good indication that RAM isn't working, right?
>

Yeah.  Look in the code and you will find a simple RAM test.  It will
show lots of bit errors and then total failure.

> So to get back to debugging this, do you have any idea of a time when
> the 8601 code was working?

Sorry no.. You will just have to go through the entire log and pull
revs all revs that deal with the 8601.  Sorry I don't have any more
info.  Most of the people who worked on that don't seem to be on the
list anymore.

 Was it while LinuxBIOS existed in Subversion
> (there was a CVS repo some years ago, wasn't there)?

Right but Stefan back ported all the stuff to svn.

-- 
Richard A. Smith



From fredrik at dolda2000.com  Fri Aug 25 03:57:34 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Fri, 25 Aug 2006 03:57:34 +0200
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
	<1156468594.16966.32.camel@pc7.dolda2000.com>
	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>
Message-ID: <1156471054.16966.42.camel@pc7.dolda2000.com>

On Thu, 2006-08-24 at 20:19 -0500, Richard Smith wrote:
> > 0000360  \0  \0  \0 340  \0 340  \0 340 340 340  \0 340  \0  \0 340  \0
> > 0000400 340 340 340  \0 340 340  \0 340 340 340  \0 340  \0 340  \0  \0
> > 0000420 340  \0  \0 340  \0 340 340  \0  \0 340  \0  \0 340 340  \0 340
> > 0000440 340  \0  \0  \0 340  \0  \0  \0 340  \0  \0  \0  \0 340  \0 340
> > 0000460 340  \0 340 340 340  \0 340 340  \0 340 340  \0  \0 340  \0 340
> > 0000500  \0 340 340 340  \0 340  \0  \0 340  \0 340 340 340  \0 340 340
> > 0000520  \0 340 340 340  \0 340 340 340  \0  \0 340  \0
> >
> > Is this somehow wrong, or am I supposed to use some program to decode
> > it?
> 
> Nope its all ASCII.  I think you have a baud rate problem 115200,N,8,1

It was indeed set to 115200 N81, but I just experimented a bit and found
that it worked on 19200 baud (with some garbage at the top, though). :)

So I just recompiled and reburned LinuxBIOS with maximum logging, and I
got this:

M-^_M-OM-&M-oM-mM-yM-?M-^?M-^M-}>M-v}M-^?M-?^?M-^_M-OM-&M-oM-mM-yM-?M-^?M-^M-}>M-v}M-^?M-?^?^M$
^M$
LinuxBIOS-1.1.8.0Fallback Fri Aug 25 03:51:14 CEST 2006 starting...^M$
87 is the comm register^M$
SMBus controller enabled^M$
vt8601 init starting^M$
00000000 is the north$
1106 0601^M$
0120d4 is the computed timing$
NOP^M$
PRECHARGE^M$
DUMMY READS^M$
CBR^M$
MRS^M$
NORMAL^M$
set ref. rate^M$
enable multi-page open^M$
Slot 00 is SDRAM 08000000 bytes ^M$
0100 is the chip size^M$
000e is the MA type^M$
Slot 01 is empty^M$
Slot 02 is empty^M$
Slot 03 is empty^M$
vt8601 done^M$
Copying LinuxBIOS to ram.^M$
Jumping to LinuxBIOS.^M$

I guess that's a pretty good indication that RAM isn't working, right?

So to get back to debugging this, do you have any idea of a time when
the 8601 code was working? Was it while LinuxBIOS existed in Subversion
(there was a CVS repo some years ago, wasn't there)?

Fredrik Tolf





From svn at openbios.org  Fri Aug 25 07:01:30 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 25 Aug 2006 07:01:30 +0200
Subject: [LinuxBIOS] r2387 - in trunk/LinuxBIOSv2/src: include/cpu/amd
	mainboard/olpc/rev_a southbridge/amd/cs5536
Message-ID: <E1GGTow-0000zi-HY@khepri.openbios.org>

Author: rsmith
Date: 2006-08-25 07:01:30 +0200 (Fri, 25 Aug 2006)
New Revision: 2387

Modified:
   trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h
   trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb
   trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h
   trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
Log:
- Added suport for enabling USB P4 on the olpc

USB P4 is disabled by default and we need to setup the mux bits proper
to make it work.  This is the frame work for that.  All thats needed
is the right address values



Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h	2006-08-23 14:33:54 UTC (rev 2386)
+++ trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h	2006-08-25 05:01:30 UTC (rev 2387)
@@ -731,10 +731,14 @@
 /* */
 /*  USB2*/
 /* */
-#define USB2_SB_GLD_MSR_CAP		 (	MSR_SB_USB2 + 0x00)
-#define USB2_SB_GLD_MSR_CONF	 (	MSR_SB_USB2 + 0x01)
-#define USB2_SB_GLD_MSR_PM		 (	MSR_SB_USB2 + 0x04)
 
+#define USB2_SB_GLD_MSR_CAP		 	(	MSR_SB_USB2 + 0x00)
+#define USB2_SB_GLD_MSR_CONF	 	(	MSR_SB_USB2 + 0x01)
+#define USB2_SB_GLD_MSR_PM		 	(	MSR_SB_USB2 + 0x04)
+#define USB2_SB_GLD_MSR_OHCI_BASE	(	MSR_SB_USB2 + 0x08)
+#define USB2_SB_GLD_MSR_EHCI_BASE	(	MSR_SB_USB2 + 0x09)
+#define USB2_SB_GLD_MSR_DEVCTL_BASE	(	MSR_SB_USB2 + 0x0A)
+#define USB2_SB_GLD_MSR_UOC_BASE	(	MSR_SB_USB2 + 0x0B) /* Option controller base */
 
 /* */
 /*  ATA*/

Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb	2006-08-23 14:33:54 UTC (rev 2386)
+++ trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb	2006-08-25 05:01:30 UTC (rev 2387)
@@ -138,6 +138,7 @@
                         register "enable_gpio0_inta" = "1"
 			register "enable_ide_nand_flash" = "1"
 			register "enable_uarta" = "1"
+			register "enable_USBP4_host" = "1"
 			register "audio_irq" = "5"
 			register "usbf4_irq" = "10"
 			register "usbf5_irq" = "10"

Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h	2006-08-23 14:33:54 UTC (rev 2386)
+++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h	2006-08-25 05:01:30 UTC (rev 2387)
@@ -12,6 +12,7 @@
  	int enable_gpio0_inta; 	/* almost always will be true */
 	int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */
 	int enable_uarta; 		/* internal uarta interrupt enable */
+	int enable_USBP4_host;	/* Enable USB Port 4 as a host */
 	/* following are IRQ numbers for various southbridge resources. */
 	/* I have guessed at some things, as I still don't have an lspci from anyone */
 	int ide_irq;		/* f.2 */

Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-23 14:33:54 UTC (rev 2386)
+++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-25 05:01:30 UTC (rev 2387)
@@ -152,6 +152,48 @@
 		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
 		outl(0xDEADBEEF,                  0xCFC);
 	}
+
+	if (sb->enable_USBP4_host) {
+		volatile unsigned long* uocmux;
+		unsigned long val;
+
+		printk_err("Base 0x%08x\n",USB2_SB_GLD_MSR_CAP);
+		
+		msr = rdmsr(USB2_SB_GLD_MSR_CAP);
+		printk_err("CAP 0x%08x%08x\n", msr.hi,msr.lo);
+
+		msr = rdmsr(USB2_SB_GLD_MSR_OHCI_BASE);
+		printk_err("OHCI base 0x%08x%08x\n", msr.hi,msr.lo);
+
+		msr = rdmsr(USB2_SB_GLD_MSR_EHCI_BASE);
+		printk_err("EHCI base 0x%08x%08x\n", msr.hi,msr.lo);
+
+		msr = rdmsr(USB2_SB_GLD_MSR_DEVCTL_BASE);
+		printk_err("DevCtl base 0x%08x%08x\n", msr.hi,msr.lo);
+
+		msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE);
+		printk_err("Old UOC Base 0x%08x%08x\n", msr.hi,msr.lo);
+		msr.hi |= 0xa;
+		msr.lo |= 0xfe010000;
+	
+#if 0	
+		wrmsr(USB2_SB_GLD_MSR_UOC_BASE, msr);
+
+		msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE);
+		printk_err("New UOC Base 0x%08x%08x\n", msr.hi,msr.lo);
+
+		uocmux = (unsigned long *)msr.lo+4;
+		val = *uocmux;
+
+		printk_err("UOCMUX is 0x%lx\n",*val);
+		val &= ~(0xc0);
+		val |= 0x2;
+
+		*uocmux = val;
+#endif
+
+	}
+
 }
 
 




From rogelio.serrano at gmail.com  Fri Aug 25 08:18:22 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Fri, 25 Aug 2006 14:18:22 +0800
Subject: [LinuxBIOS] booting without vga
Message-ID: <a9951d2a0608242318y9dedfdam365e4134688a0b4f@mail.gmail.com>

Is there a way for linuxbios to initialize the graphics hardware
directly? besides making linux use the framebuffer directly on bootup.
and maybe making filo use the framebuffer too.

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From smithbone at gmail.com  Fri Aug 25 08:52:19 2006
From: smithbone at gmail.com (Richard Smith)
Date: Fri, 25 Aug 2006 01:52:19 -0500
Subject: [LinuxBIOS] booting without vga
In-Reply-To: <a9951d2a0608242318y9dedfdam365e4134688a0b4f@mail.gmail.com>
References: <a9951d2a0608242318y9dedfdam365e4134688a0b4f@mail.gmail.com>
Message-ID: <8a0c36780608242352y3c6a8030h5bb10e6da04b5dfc@mail.gmail.com>

On 8/25/06, Rogelio Serrano <rogelio.serrano at gmail.com> wrote:

> Is there a way for linuxbios to initialize the graphics hardware
> directly? besides making linux use the framebuffer directly on bootup.
> and maybe making filo use the framebuffer too.

If the hardware was standard then yes but each graphics mfg does it
differently and its hidden by the VGA bios.  Think of each graphics
card as a graphics northbridge.  You have to eanble all the right
bits, turn on the video ram, etc.  On 99% of graphics cards the info
on how to do this is not known.  So you have to run the vga bios to do
it.


-- 
Richard A. Smith



From rogelio.serrano at gmail.com  Fri Aug 25 09:23:41 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Fri, 25 Aug 2006 15:23:41 +0800
Subject: [LinuxBIOS] booting without vga
In-Reply-To: <8a0c36780608242352y3c6a8030h5bb10e6da04b5dfc@mail.gmail.com>
References: <a9951d2a0608242318y9dedfdam365e4134688a0b4f@mail.gmail.com>
	<8a0c36780608242352y3c6a8030h5bb10e6da04b5dfc@mail.gmail.com>
Message-ID: <a9951d2a0608250023u631e95f2t8d891f82e573543@mail.gmail.com>

On 8/25/06, Richard Smith <smithbone at gmail.com> wrote:
> On 8/25/06, Rogelio Serrano <rogelio.serrano at gmail.com> wrote:
>
> > Is there a way for linuxbios to initialize the graphics hardware
> > directly? besides making linux use the framebuffer directly on bootup.
> > and maybe making filo use the framebuffer too.
>
> If the hardware was standard then yes but each graphics mfg does it
> differently and its hidden by the VGA bios.  Think of each graphics
> card as a graphics northbridge.  You have to eanble all the right
> bits, turn on the video ram, etc.  On 99% of graphics cards the info
> on how to do this is not known.  So you have to run the vga bios to do
> it.
>
>
> --
> Richard A. Smith
>

ugh!!!

and the vga bios is running at 16 bit mode? and its slow with all its
timing loops and other stuff.

which graphic cards are in the other 1%?

hah! this is another argument for ogp. i have to start studying fpgas
now. i need an open graphics card that boots at a fraction of the
speed of current cards and boots straight into framebuffer mode.

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug 25 11:32:58 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel U. Hailfinger)
Date: Fri, 25 Aug 2006 11:32:58 +0200
Subject: [LinuxBIOS] PATCH: IT8673F Super IO support.
In-Reply-To: <20060825015926.GA28007@aragorn>
References: <20060825015926.GA28007@aragorn>
Message-ID: <20060825093258.270860@gmx.net>

Hi Uwe,

while you're at it, could you possibly also add support for the IT8712F? It's used in quite a lot of Asus boards. If you have trouble locating the datasheets, I can send them to you via mail.

Regards,
Carl-Daniel
-- 


"Feel free" ? 10 GB Mailbox, 100 FreeSMS/Monat ...
Jetzt GMX TopMail testen: http://www.gmx.net/de/go/topmail



From svn at openbios.org  Fri Aug 25 16:06:49 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 25 Aug 2006 16:06:49 +0200
Subject: [LinuxBIOS] r2388 - trunk/LinuxBIOSv2/src/southbridge/amd/cs5536
Message-ID: <E1GGcKf-0006UQ-06@khepri.openbios.org>

Author: rsmith
Date: 2006-08-25 16:06:48 +0200 (Fri, 25 Aug 2006)
New Revision: 2388

Modified:
   trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
Log:
- fix a silly pointer dereference thinko in my previous commit



Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-25 05:01:30 UTC (rev 2387)
+++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-25 14:06:48 UTC (rev 2388)
@@ -176,16 +176,16 @@
 		msr.hi |= 0xa;
 		msr.lo |= 0xfe010000;
 	
-#if 0	
 		wrmsr(USB2_SB_GLD_MSR_UOC_BASE, msr);
 
 		msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE);
 		printk_err("New UOC Base 0x%08x%08x\n", msr.hi,msr.lo);
 
-		uocmux = (unsigned long *)msr.lo+4;
+		uocmux = (unsigned long *)(msr.lo+4);
 		val = *uocmux;
 
-		printk_err("UOCMUX is 0x%lx\n",*val);
+		printk_err("UOCMUX is 0x%lx\n",val);
+#if 0	
 		val &= ~(0xc0);
 		val |= 0x2;
 




From rminnich at lanl.gov  Fri Aug 25 16:46:03 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Fri, 25 Aug 2006 08:46:03 -0600
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>	<1156379483.16966.20.camel@pc7.dolda2000.com>	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>	<1156468594.16966.32.camel@pc7.dolda2000.com>	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>	<1156471054.16966.42.camel@pc7.dolda2000.com>
	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>
Message-ID: <44EF0D2B.6070703@lanl.gov>

Go back to V1 and see what that did.

Here is the sad story. I had to hard-code bits of 8601 setup since if 
you followed the manual, and did things right, the chip would lock up. 
the hard codes made certain dram types not work. Somebody got clever and 
fixed the hardcodes to be dynamic a la spd. From that point on, 8601 has 
been broken. When did this happen? don't know.

But it did work in v1.

ron



From rminnich at lanl.gov  Fri Aug 25 16:50:31 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Fri, 25 Aug 2006 08:50:31 -0600
Subject: [LinuxBIOS] PATCH: IT8673F Super IO support.
In-Reply-To: <20060825015926.GA28007@aragorn>
References: <20060825015926.GA28007@aragorn>
Message-ID: <44EF0E37.9070102@lanl.gov>

I have applied this to my tree. Commits are not working right now, 
trying to find out why.

ron



From rminnich at lanl.gov  Fri Aug 25 16:54:39 2006
From: rminnich at lanl.gov (Ronald G Minnich)
Date: Fri, 25 Aug 2006 08:54:39 -0600
Subject: [LinuxBIOS] booting without vga
In-Reply-To: <a9951d2a0608250023u631e95f2t8d891f82e573543@mail.gmail.com>
References: <a9951d2a0608242318y9dedfdam365e4134688a0b4f@mail.gmail.com>	<8a0c36780608242352y3c6a8030h5bb10e6da04b5dfc@mail.gmail.com>
	<a9951d2a0608250023u631e95f2t8d891f82e573543@mail.gmail.com>
Message-ID: <44EF0F2F.9030202@lanl.gov>

Rogelio Serrano wrote:

> hah! this is another argument for ogp. i have to start studying fpgas
> now. i need an open graphics card that boots at a fraction of the
> speed of current cards and boots straight into framebuffer mode.
> 

this is part of a bigger issue. I am thinking of starting a project 
called System Libre (a take on software libre) which would be open from 
the ground up. This is a response to many bad trends in our business, 
where the systems are gradually getting locked up (xbox, EFI, etc.) and 
we can't do much with them. So I like your idea.

ron



From uwe at hermann-uwe.de  Fri Aug 25 17:43:42 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 25 Aug 2006 17:43:42 +0200
Subject: [LinuxBIOS] booting without vga
In-Reply-To: <44EF0F2F.9030202@lanl.gov>
References: <a9951d2a0608242318y9dedfdam365e4134688a0b4f@mail.gmail.com>
	<8a0c36780608242352y3c6a8030h5bb10e6da04b5dfc@mail.gmail.com>
	<a9951d2a0608250023u631e95f2t8d891f82e573543@mail.gmail.com>
	<44EF0F2F.9030202@lanl.gov>
Message-ID: <20060825154342.GA14288@aragorn>

Hi,

On Fri, Aug 25, 2006 at 08:54:39AM -0600, Ronald G Minnich wrote:
> this is part of a bigger issue. I am thinking of starting a project 
> called System Libre (a take on software libre) which would be open from 
> the ground up.

Count me in, I'll help where I can. This is one of the main reasons why
I got interested in LinuxBIOS - to have a 100% Free Software system,
from the ground up.


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060825/3373f971/attachment.sig>

From bchafy at ccs.neu.edu  Fri Aug 25 17:53:37 2006
From: bchafy at ccs.neu.edu (Bryan E. Chafy)
Date: Fri, 25 Aug 2006 11:53:37 -0400 (EDT)
Subject: [LinuxBIOS] booting without vga
In-Reply-To: <44EF0F2F.9030202@lanl.gov> from "Ronald G Minnich" at Aug 25,
	2006 08:54:39 AM
Message-ID: <E1GGe01-0002qP-DZ@denali.ccs.neu.edu>

For video, check out:
http://wiki.duskglow.com/tiki-index.php?page=Open-Graphics
I think It's been going on for a couple of years now.

As for FPGA's, a high end Virtex+ builtin Dual PPC cores gets you there pretty
fast.  Only problem is the price (for the chips and the software).
Not sure how well a spartan-level fpga would work out as SOC or chipset.
But the price is right (free software, relatively cheap chip).

Check out:
http://www.fpga4fun.com


> 
> this is part of a bigger issue. I am thinking of starting a project 
> called System Libre (a take on software libre) which would be open from 
> the ground up. This is a response to many bad trends in our business, 
> where the systems are gradually getting locked up (xbox, EFI, etc.) and 
> we can't do much with them. So I like your idea.
> 
> ron
> 
> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
> 




From rogelio.serrano at gmail.com  Fri Aug 25 18:12:21 2006
From: rogelio.serrano at gmail.com (Rogelio Serrano)
Date: Sat, 26 Aug 2006 00:12:21 +0800
Subject: [LinuxBIOS] booting without vga
In-Reply-To: <44EF0F2F.9030202@lanl.gov>
References: <a9951d2a0608242318y9dedfdam365e4134688a0b4f@mail.gmail.com>
	<8a0c36780608242352y3c6a8030h5bb10e6da04b5dfc@mail.gmail.com>
	<a9951d2a0608250023u631e95f2t8d891f82e573543@mail.gmail.com>
	<44EF0F2F.9030202@lanl.gov>
Message-ID: <a9951d2a0608250912v7b8a8f6cwec44081e0b5bb9ab@mail.gmail.com>

On 8/25/06, Ronald G Minnich <rminnich at lanl.gov> wrote:
> Rogelio Serrano wrote:
>
> > hah! this is another argument for ogp. i have to start studying fpgas
> > now. i need an open graphics card that boots at a fraction of the
> > speed of current cards and boots straight into framebuffer mode.
> >
>
> this is part of a bigger issue. I am thinking of starting a project
> called System Libre (a take on software libre) which would be open from
> the ground up. This is a response to many bad trends in our business,
> where the systems are gradually getting locked up (xbox, EFI, etc.) and
> we can't do much with them. So I like your idea.
>
> ron
>

I would like to help with that too.

The open graphics project is doing the same thing for graphics cards.

-- 
things i hate about my linux pc:

1. it takes more than a second to boot up
2. keeps asking about filenames and directories
3. does not remember what i was working on yesterday
4. does not remember all the changes i have ever made
5.cannot figure out necessary settings by itself



From svn at openbios.org  Fri Aug 25 18:14:31 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 25 Aug 2006 18:14:31 +0200
Subject: [LinuxBIOS] r2389 - in trunk/LinuxBIOSv2/src: include/cpu/amd
	southbridge/amd/cs5536
Message-ID: <E1GGeKF-00043M-Vb@khepri.openbios.org>

Author: rsmith
Date: 2006-08-25 18:14:31 +0200 (Fri, 25 Aug 2006)
New Revision: 2389

Modified:
   trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h
   trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
Log:
- USB P4 as host fix

This should make the USB P4 work as a USB host



Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h	2006-08-25 14:06:48 UTC (rev 2388)
+++ trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h	2006-08-25 16:14:31 UTC (rev 2389)
@@ -706,6 +706,8 @@
 
 /*  SouthBridge Equates*/
 /*  MSR_SB and SB_SHIFT are located in CPU.inc*/
+#define MSR_SB_USB2_MEM_DES ((1<<16) + MSR_SB + 0x25) /* Hack to make USB P4 work */  
+
 #define MSR_SB_GLIU	 ((9 << 14) + MSR_SB)		/* 51024xxx or 510*xxxx	- fake out just like GL0 on CPU. */
 #define MSR_SB_GLPCI	 (MSR_SB)			/* 5100xxxx - don't go to the GLIU */
 #define MSR_SB_USB2	 ((2 << SB_SHIFT) + MSR_SB)	/* 5120xxxx */

Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-25 14:06:48 UTC (rev 2388)
+++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-25 16:14:31 UTC (rev 2389)
@@ -157,19 +157,19 @@
 		volatile unsigned long* uocmux;
 		unsigned long val;
 
-		printk_err("Base 0x%08x\n",USB2_SB_GLD_MSR_CAP);
+
+		printk_err("DES 0x%08x\n",MSR_SB_USB2_MEM_DES);
 		
-		msr = rdmsr(USB2_SB_GLD_MSR_CAP);
-		printk_err("CAP 0x%08x%08x\n", msr.hi,msr.lo);
+		msr = rdmsr(MSR_SB_USB2_MEM_DES);
+		printk_err("DES 0x%08x%08x\n", msr.hi,msr.lo);
 
-		msr = rdmsr(USB2_SB_GLD_MSR_OHCI_BASE);
-		printk_err("OHCI base 0x%08x%08x\n", msr.hi,msr.lo);
+		msr.hi = 0x400000fe;
+		msr.lo = 0x010fffff;
 
-		msr = rdmsr(USB2_SB_GLD_MSR_EHCI_BASE);
-		printk_err("EHCI base 0x%08x%08x\n", msr.hi,msr.lo);
+		wrmsr(MSR_SB_USB2_MEM_DES, msr);
 
-		msr = rdmsr(USB2_SB_GLD_MSR_DEVCTL_BASE);
-		printk_err("DevCtl base 0x%08x%08x\n", msr.hi,msr.lo);
+		msr = rdmsr(MSR_SB_USB2_MEM_DES);
+		printk_err("New DES 0x%08x%08x\n", msr.hi,msr.lo);
 
 		msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE);
 		printk_err("Old UOC Base 0x%08x%08x\n", msr.hi,msr.lo);
@@ -185,13 +185,15 @@
 		val = *uocmux;
 
 		printk_err("UOCMUX is 0x%lx\n",val);
-#if 0	
-		val &= ~(0xc0);
+
+		val &= ~(0x3);
 		val |= 0x2;
 
 		*uocmux = val;
-#endif
 
+		val = *uocmux;
+		printk_err("New UOCMUX is 0x%lx\n",val);
+
 	}
 
 }




From ben at hewson-venieri.com  Fri Aug 25 19:48:37 2006
From: ben at hewson-venieri.com (Ben Hewson)
Date: Fri, 25 Aug 2006 18:48:37 +0100
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>	<1156379483.16966.20.camel@pc7.dolda2000.com>	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>	<1156468594.16966.32.camel@pc7.dolda2000.com>	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>	<1156471054.16966.42.camel@pc7.dolda2000.com>
	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>
Message-ID: <44EF37F5.4010107@hewson-venieri.com>

I assume the EPIA-V board is the oldest version ? VIA on their website
only mention

EPIA EK , CN, EN, SP, ML, MII, M, but no V

Anyway I have tried to get linuxbios to boot on my EPIA 5000 (vt8601
northbridge)
I do not even get any comms from the serial port. Have checked the cable
is ok, by
booting normally.

I only have 100Mhz memory installed, as it was going spare. Could this
be a reason why
it does not work ? Anyway have just downloaded the vt8601 datasheet so
will have a read
through it and the code when I get some time and go through the code.
Perhaps I will try
and get some 133Mhz ram and try with that also.


> On 8/24/06, Fredrik Tolf <fredrik at dolda2000.com> wrote:
>   
>> It was indeed set to 115200 N81, but I just experimented a bit and found
>> that it worked on 19200 baud (with some garbage at the top, though). :)
>>     
>
> Oh thats right.. There is some freaky divider issue with the EPIA...
> Need to document that somewhere.
>
>   
>> Slot 00 is SDRAM 08000000 bytes ^M$
>> 0100 is the chip size^M$
>> 000e is the MA type^M$
>> Slot 01 is empty^M$
>> Slot 02 is empty^M$
>> Slot 03 is empty^M$
>> vt8601 done^M$
>> Copying LinuxBIOS to ram.^M$
>> Jumping to LinuxBIOS.^M$
>>
>> I guess that's a pretty good indication that RAM isn't working, right?
>>
>>     
>
> Yeah.  Look in the code and you will find a simple RAM test.  It will
> show lots of bit errors and then total failure.
>
>   
>> So to get back to debugging this, do you have any idea of a time when
>> the 8601 code was working?
>>     
>
> Sorry no.. You will just have to go through the entire log and pull
> revs all revs that deal with the 8601.  Sorry I don't have any more
> info.  Most of the people who worked on that don't seem to be on the
> list anymore.
>
>  Was it while LinuxBIOS existed in Subversion
>   
>> (there was a CVS repo some years ago, wasn't there)?
>>     
>
> Right but Stefan back ported all the stuff to svn.
>
>   

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060825/a87e20d1/attachment.html>

From uwe at hermann-uwe.de  Fri Aug 25 20:28:40 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 25 Aug 2006 20:28:40 +0200
Subject: [LinuxBIOS] PATCH: IT8712F Super IO support.
In-Reply-To: <20060825093258.270860@gmx.net>
References: <20060825015926.GA28007@aragorn> <20060825093258.270860@gmx.net>
Message-ID: <20060825182840.GA21858@aragorn>

Hi,

On Fri, Aug 25, 2006 at 11:32:58AM +0200, Carl-Daniel U. Hailfinger wrote:
> while you're at it, could you possibly also add support for the IT8712F?

Sure, here it is. Do you have hardware you can use to test this? I can
only verify that it compiles at the moment...


HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/superio/ite/it8712f/it8712f_early_serial.c
===================================================================
--- src/superio/ite/it8712f/it8712f_early_serial.c	(Revision 0)
+++ src/superio/ite/it8712f/it8712f_early_serial.c	(Revision 0)
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8712f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE                     0x2e
+#define SIO_INDEX                    SIO_BASE
+#define SIO_DATA                     SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8712F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8712F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8712F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8712F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+
+#define IT8712F_CONFIGURATION_PORT   0x2E /* Write-only. */
+
+/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8712F Super IO chip. */
+static void it8712f_enable_serial(device_t dev, unsigned iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x2e. */
+	/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+	/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+	outb(0x87, IT8712F_CONFIGURATION_PORT);
+	outb(0x01, IT8712F_CONFIGURATION_PORT);
+	outb(0x55, IT8712F_CONFIGURATION_PORT);
+	outb(0x55, IT8712F_CONFIGURATION_PORT);
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Select the chip to configure (if there's more than one).
+         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+         * If this register is not written, both chips are configured. */
+	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+	/* Enable all devices. */
+	it8712f_sio_write(IT8712F_FDC,  0x30, 0x1); /* Floppy */
+	it8712f_sio_write(IT8712F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8712f_sio_write(IT8712F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8712f_sio_write(IT8712F_PP,   0x30, 0x1); /* Parallel port */
+	it8712f_sio_write(IT8712F_EC,   0x30, 0x1); /* Environment controller */
+	it8712f_sio_write(IT8712F_KBCK, 0x30, 0x1); /* Keyboard */
+	it8712f_sio_write(IT8712F_KBCM, 0x30, 0x1); /* Mouse */
+	it8712f_sio_write(IT8712F_MIDI, 0x30, 0x1); /* MIDI port */
+	it8712f_sio_write(IT8712F_GAME, 0x30, 0x1); /* GAME port */
+	it8712f_sio_write(IT8712F_IR,   0x30, 0x1); /* Consumer IR */
+
+	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
+	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x00); */
+
+	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
+	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); 
+}
+
Index: src/superio/ite/it8712f/Config.lb
===================================================================
--- src/superio/ite/it8712f/Config.lb	(Revision 0)
+++ src/superio/ite/it8712f/Config.lb	(Revision 0)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
Index: src/superio/ite/it8712f/superio.c
===================================================================
--- src/superio/ite/it8712f/superio.c	(Revision 0)
+++ src/superio/ite/it8712f/superio.c	(Revision 0)
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "it8712f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8712f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8712F_FDC: /* TODO. */
+		break;
+	case IT8712F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8712F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8712F_PP: /* TODO. */
+		break;
+	case IT8712F_EC: /* TODO. */
+		break;
+	case IT8712F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	case IT8712F_KBCM: /* TODO. */
+		break;
+	case IT8712F_MIDI: /* TODO. */
+		break;
+	case IT8712F_GAME: /* TODO. */
+		break;
+	case IT8712F_IR: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, EC, KBCM, MIDI, GAME, IR. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8712F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8712F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8712f_ops = {
+	CHIP_NAME("ITE it8712f")
+	.enable_dev = enable_dev,
+};
+
Index: src/superio/ite/it8712f/chip.h
===================================================================
--- src/superio/ite/it8712f/chip.h	(Revision 0)
+++ src/superio/ite/it8712f/chip.h	(Revision 0)
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8712F
+#define _SUPERIO_ITE_IT8712F
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8712f_ops;
+
+struct superio_ITE_it8712f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif /* _SUPERIO_ITE_IT8712F */
+
Index: src/superio/ite/it8712f/it8712f.h
===================================================================
--- src/superio/ite/it8712f/it8712f.h	(Revision 0)
+++ src/superio/ite/it8712f/it8712f.h	(Revision 0)
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define IT8712F_FDC  0x00 /* Floppy */
+#define IT8712F_SP1  0x01 /* Com1 */
+#define IT8712F_SP2  0x02 /* Com2 */
+#define IT8712F_PP   0x03 /* Parallel port */
+#define IT8712F_EC   0x04 /* Environment controller */
+#define IT8712F_KBCK 0x05 /* Keyboard */
+#define IT8712F_KBCM 0x06 /* Mouse */
+#define IT8712F_MIDI 0x08 /* MIDI port */
+#define IT8712F_GAME 0x09 /* GAME port */
+#define IT8712F_IR   0x0a /* Consumer IR */
+
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060825/344eac84/attachment.sig>

From svn at openbios.org  Fri Aug 25 21:21:42 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 25 Aug 2006 21:21:42 +0200
Subject: [LinuxBIOS] r2390 - trunk/LinuxBIOSv2/util/flashrom
Message-ID: <E1GGhFO-0005xF-AO@khepri.openbios.org>

Author: stepan
Date: 2006-08-25 21:21:42 +0200 (Fri, 25 Aug 2006)
New Revision: 2390

Modified:
   trunk/LinuxBIOSv2/util/flashrom/README
   trunk/LinuxBIOSv2/util/flashrom/flash_enable.c
Log:
Print a warning if southbridge is not known to flashrom.


Modified: trunk/LinuxBIOSv2/util/flashrom/README
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/README	2006-08-25 16:14:31 UTC (rev 2389)
+++ trunk/LinuxBIOSv2/util/flashrom/README	2006-08-25 19:21:42 UTC (rev 2390)
@@ -77,6 +77,6 @@
 -----------
 
 DISK on Chip support is currently disabled since it is considered unstable. 
-Change CFLAGS in the Makefile to enable it.
+Change CFLAGS in the Makefile to enable it: Remove -DDISABLE_DOC from CFLAGS.
 
 

Modified: trunk/LinuxBIOSv2/util/flashrom/flash_enable.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/flash_enable.c	2006-08-25 16:14:31 UTC (rev 2389)
+++ trunk/LinuxBIOSv2/util/flashrom/flash_enable.c	2006-08-25 19:21:42 UTC (rev 2390)
@@ -506,11 +506,15 @@
 			}
 	}
 
+	if (!enable) {
+		printf("Warning: Unknown system. Flash detection "
+			"will most likely fail.\n");
+		return 1;
+	}
+	
 	/* now do the deed. */
-	if (enable) {
-		printf("Enabling flash write on %s...", enable->name);
-		if (enable->doit(dev, enable->name) == 0)
-			printf("OK\n");
-	}
+	printf("Enabling flash write on %s...", enable->name);
+	if (enable->doit(dev, enable->name) == 0)
+		printf("OK\n");
 	return 0;
 }




From svn at openbios.org  Fri Aug 25 21:29:58 2006
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 25 Aug 2006 21:29:58 +0200
Subject: [LinuxBIOS] r2391 - in trunk/LinuxBIOSv2/src/superio/ite: . it8673f
	it8712f
Message-ID: <E1GGhNO-0006wd-9z@khepri.openbios.org>

Author: stepan
Date: 2006-08-25 21:29:57 +0200 (Fri, 25 Aug 2006)
New Revision: 2391

Added:
   trunk/LinuxBIOSv2/src/superio/ite/it8673f/
   trunk/LinuxBIOSv2/src/superio/ite/it8673f/Config.lb
   trunk/LinuxBIOSv2/src/superio/ite/it8673f/chip.h
   trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f.h
   trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c
   trunk/LinuxBIOSv2/src/superio/ite/it8673f/superio.c
   trunk/LinuxBIOSv2/src/superio/ite/it8712f/
   trunk/LinuxBIOSv2/src/superio/ite/it8712f/Config.lb
   trunk/LinuxBIOSv2/src/superio/ite/it8712f/chip.h
   trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f.h
   trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c
   trunk/LinuxBIOSv2/src/superio/ite/it8712f/superio.c
Log:
Support for two new ITE superio parts: it8712f
and it8673f from Uwe Hermann.


Added: trunk/LinuxBIOSv2/src/superio/ite/it8673f/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8673f/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8673f/Config.lb	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o

Added: trunk/LinuxBIOSv2/src/superio/ite/it8673f/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8673f/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8673f/chip.h	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8673F
+#define _SUPERIO_ITE_IT8673F
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8673f_ops;
+
+struct superio_ITE_it8673f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif /* _SUPERIO_ITE_IT8673F */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f.h	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define IT8673F_FDC  0x00 /* Floppy */
+#define IT8673F_SP1  0x01 /* Com1 */
+#define IT8673F_SP2  0x02 /* Com2 */
+#define IT8673F_PP   0x03 /* Parallel port */
+#define IT8673F_FAN  0x04 /* Fan controller */
+#define IT8673F_KBCK 0x05 /* Keyboard */
+#define IT8673F_KBCM 0x06 /* Mouse */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8673f.h"
+
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE                    0x3f0
+#define SIO_INDEX                   SIO_BASE
+#define SIO_DATA                    SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8673F_CONFIG_REG_CC       0x02   /* Configure Control (write-only). */
+#define IT8673F_CONFIG_REG_LDN      0x07   /* Logical Device Number. */
+#define IT8673F_CONFIG_REG_CLOCKSEL 0x23   /* Clock Selection. */
+#define IT8673F_CONFIG_REG_SWSUSP   0x24   /* Software Suspend. */
+
+#define IT8673F_CONFIGURATION_PORT  0x0279 /* Write-only. */
+
+/* Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data. */
+static const uint8_t init_values[] = {
+	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+/* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8673F Super IO chip. */
+static void it8673f_enable_serial(device_t dev, unsigned iobase)
+{
+	uint8_t i;
+
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+	outb(0x86, IT8673F_CONFIGURATION_PORT);
+	outb(0x80, IT8673F_CONFIGURATION_PORT);
+	outb(0x55, IT8673F_CONFIGURATION_PORT);
+	outb(0x55, IT8673F_CONFIGURATION_PORT);
+
+	/* Sequentially write the 32 special values. */
+	for (i = 0; i < 32; i++) {
+		outb(init_values[i], SIO_BASE);
+	}
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Enable all devices. */
+	it8673f_sio_write(IT8673F_FDC,  0x30, 0x1); /* Floppy */
+	it8673f_sio_write(IT8673F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8673f_sio_write(IT8673F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8673f_sio_write(IT8673F_PP,   0x30, 0x1); /* Parallel port */
+	it8673f_sio_write(IT8673F_FAN,  0x30, 0x1); /* Fan controller */
+	it8673f_sio_write(IT8673F_KBCK, 0x30, 0x1); /* Keyboard */
+	it8673f_sio_write(IT8673F_KBCM, 0x30, 0x1); /* Mouse */
+
+	/* Select 24MHz CLKIN (clear bit 0). TODO: is this really needed? */
+	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00);
+
+	/* Clear software suspend mode (clear bit 0). */
+	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00);
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02); 
+}
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8673f/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8673f/superio.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8673f/superio.c	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "it8673f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8673f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8673F_FDC: /* TODO. */
+		break;
+	case IT8673F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8673F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8673F_PP: /* TODO. */
+		break;
+	case IT8673F_FAN: /* TODO. */
+		break;
+	case IT8673F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	case IT8673F_KBCM: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, FAN, KBCM. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8673F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8673F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, IT8673F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8673f_ops = {
+	CHIP_NAME("ITE it8673f")
+	.enable_dev = enable_dev,
+};
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8712f/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8712f/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8712f/Config.lb	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o

Added: trunk/LinuxBIOSv2/src/superio/ite/it8712f/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8712f/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8712f/chip.h	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8712F
+#define _SUPERIO_ITE_IT8712F
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8712f_ops;
+
+struct superio_ITE_it8712f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif /* _SUPERIO_ITE_IT8712F */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f.h	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define IT8712F_FDC  0x00 /* Floppy */
+#define IT8712F_SP1  0x01 /* Com1 */
+#define IT8712F_SP2  0x02 /* Com2 */
+#define IT8712F_PP   0x03 /* Parallel port */
+#define IT8712F_EC   0x04 /* Environment controller */
+#define IT8712F_KBCK 0x05 /* Keyboard */
+#define IT8712F_KBCM 0x06 /* Mouse */
+#define IT8712F_MIDI 0x08 /* MIDI port */
+#define IT8712F_GAME 0x09 /* GAME port */
+#define IT8712F_IR   0x0a /* Consumer IR */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8712f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE                     0x2e
+#define SIO_INDEX                    SIO_BASE
+#define SIO_DATA                     SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8712F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8712F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8712F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8712F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+
+#define IT8712F_CONFIGURATION_PORT   0x2E /* Write-only. */
+
+/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8712F Super IO chip. */
+static void it8712f_enable_serial(device_t dev, unsigned iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x2e. */
+	/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+	/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+	outb(0x87, IT8712F_CONFIGURATION_PORT);
+	outb(0x01, IT8712F_CONFIGURATION_PORT);
+	outb(0x55, IT8712F_CONFIGURATION_PORT);
+	outb(0x55, IT8712F_CONFIGURATION_PORT);
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Select the chip to configure (if there's more than one).
+         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+         * If this register is not written, both chips are configured. */
+	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+	/* Enable all devices. */
+	it8712f_sio_write(IT8712F_FDC,  0x30, 0x1); /* Floppy */
+	it8712f_sio_write(IT8712F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8712f_sio_write(IT8712F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8712f_sio_write(IT8712F_PP,   0x30, 0x1); /* Parallel port */
+	it8712f_sio_write(IT8712F_EC,   0x30, 0x1); /* Environment controller */
+	it8712f_sio_write(IT8712F_KBCK, 0x30, 0x1); /* Keyboard */
+	it8712f_sio_write(IT8712F_KBCM, 0x30, 0x1); /* Mouse */
+	it8712f_sio_write(IT8712F_MIDI, 0x30, 0x1); /* MIDI port */
+	it8712f_sio_write(IT8712F_GAME, 0x30, 0x1); /* GAME port */
+	it8712f_sio_write(IT8712F_IR,   0x30, 0x1); /* Consumer IR */
+
+	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
+	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x00); */
+
+	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
+	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); 
+}
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8712f/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8712f/superio.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8712f/superio.c	2006-08-25 19:29:57 UTC (rev 2391)
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "it8712f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8712f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8712F_FDC: /* TODO. */
+		break;
+	case IT8712F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8712F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8712F_PP: /* TODO. */
+		break;
+	case IT8712F_EC: /* TODO. */
+		break;
+	case IT8712F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	case IT8712F_KBCM: /* TODO. */
+		break;
+	case IT8712F_MIDI: /* TODO. */
+		break;
+	case IT8712F_GAME: /* TODO. */
+		break;
+	case IT8712F_IR: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, EC, KBCM, MIDI, GAME, IR. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8712F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8712F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8712f_ops = {
+	CHIP_NAME("ITE it8712f")
+	.enable_dev = enable_dev,
+};
+




From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug 25 23:20:24 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel U. Hailfinger)
Date: Fri, 25 Aug 2006 23:20:24 +0200
Subject: [LinuxBIOS] PATCH: IT8712F Super IO support.
In-Reply-To: <20060825182840.GA21858@aragorn>
References: <20060825015926.GA28007@aragorn> <20060825093258.270860@gmx.net>
	<20060825182840.GA21858@aragorn>
Message-ID: <20060825212024.292040@gmx.net>

Uwe Hermann wrote:

> On Fri, Aug 25, 2006 at 11:32:58AM +0200, Carl-Daniel Hailfinger wrote:
> > while you're at it, could you possibly also add support for the IT8712F?
> 
> Sure, here it is. Do you have hardware you can use to test this? I can
> only verify that it compiles at the moment...

Great, thanks! I do have an ASUS A8N-SLI with this SuperIO which I'll try to port LinuxBIOS on (but it will take me some time to really start that project).


Regards,
Carl-Daniel
-- 


"Feel free" ? 10 GB Mailbox, 100 FreeSMS/Monat ...
Jetzt GMX TopMail testen: http://www.gmx.net/de/go/topmail



From smithbone at gmail.com  Sat Aug 26 11:48:54 2006
From: smithbone at gmail.com (Richard Smith)
Date: Sat, 26 Aug 2006 04:48:54 -0500
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <44EF37F5.4010107@hewson-venieri.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
	<1156468594.16966.32.camel@pc7.dolda2000.com>
	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>
	<1156471054.16966.42.camel@pc7.dolda2000.com>
	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>
	<44EF37F5.4010107@hewson-venieri.com>
Message-ID: <8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>

>  I do not even get any comms from the serial port. Have checked the cable is
> ok, by
>  booting normally.
>
>  I only have 100Mhz memory installed, as it was going spare. Could this be a
> reason why
>  it does not work ?

Com port messages start  happening pre-ram init.  So No. You should at
least some version info build date, and get to the "Jumping to
LinuxBIOS..."  string.

Something must be different with the Com port on that board.

-- 
Richard A. Smith



From ben at hewson-venieri.com  Sat Aug 26 14:01:06 2006
From: ben at hewson-venieri.com (Ben Hewson)
Date: Sat, 26 Aug 2006 13:01:06 +0100
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>	
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>	
	<1156379483.16966.20.camel@pc7.dolda2000.com>	
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>	
	<1156468594.16966.32.camel@pc7.dolda2000.com>	
	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>	
	<1156471054.16966.42.camel@pc7.dolda2000.com>	
	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>	
	<44EF37F5.4010107@hewson-venieri.com>
	<8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>
Message-ID: <44F03802.3010602@hewson-venieri.com>

Richard Smith wrote:
>>  I do not even get any comms from the serial port. Have checked the
>> cable is
>> ok, by
>>  booting normally.
>>
>>  I only have 100Mhz memory installed, as it was going spare. Could
>> this be a
>> reason why
>>  it does not work ?
>
> Com port messages start  happening pre-ram init.  So No. You should at
> least some version info build date, and get to the "Jumping to
> LinuxBIOS..."  string.
>
> Something must be different with the Com port on that board.
>
sorry didnt hit reply to all.

Ok thanks for the info, I guess I had better recheck the whole build
process and make sure I am building what I think I am.
Also I need to spend some time on seeing just exactly what linuxbios is
doing and the order it does it in. Not really a good thing to just build
code and expect it to work. I am not familiar with the BIOS boot process
having mainly worked on much simpler embedded systems.

The Com port is ok when booting normally from original bios.






From fredrik at dolda2000.com  Sat Aug 26 14:11:00 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Sat, 26 Aug 2006 14:11:00 +0200
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
	<1156468594.16966.32.camel@pc7.dolda2000.com>
	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>
	<1156471054.16966.42.camel@pc7.dolda2000.com>
	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>
	<44EF37F5.4010107@hewson-venieri.com>
	<8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>
Message-ID: <1156594260.16966.47.camel@pc7.dolda2000.com>

On Sat, 2006-08-26 at 04:48 -0500, Richard Smith wrote:
> >  I do not even get any comms from the serial port. Have checked the cable is
> > ok, by
> >  booting normally.
> >
> >  I only have 100Mhz memory installed, as it was going spare. Could this be a
> > reason why
> >  it does not work ?
> 
> Com port messages start  happening pre-ram init.  So No. You should at
> least some version info build date, and get to the "Jumping to
> LinuxBIOS..."  string.
> 
> Something must be different with the Com port on that board.

Alternatively, what flash chip are you using? I don't know about your
EPIA 5000, but my EPIA V came with a 256 KiB flash chip from the
factory, and I bought a 512 KiB one that I'm playing with. That means,
however, that when I'm making a 256 KiB LinuxBIOS flash image, I have to
make sure to prepend it with 256 KiB of padding, to ensure that it hits
the top of the address space.

If that's the problem, you can just do this:
dd if=/dev/zero bs=1k count=256 | cat - linuxbios.rom >512kbios
flashrom -w 512kbios

Fredrik Tolf





From ben at hewson-venieri.com  Sat Aug 26 14:25:04 2006
From: ben at hewson-venieri.com (Ben Hewson)
Date: Sat, 26 Aug 2006 13:25:04 +0100
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <1156594260.16966.47.camel@pc7.dolda2000.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>	
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>	
	<1156379483.16966.20.camel@pc7.dolda2000.com>	
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>	
	<1156468594.16966.32.camel@pc7.dolda2000.com>	
	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>	
	<1156471054.16966.42.camel@pc7.dolda2000.com>	
	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>	
	<44EF37F5.4010107@hewson-venieri.com>	
	<8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>
	<1156594260.16966.47.camel@pc7.dolda2000.com>
Message-ID: <44F03DA0.2020008@hewson-venieri.com>

Fredrik Tolf wrote:
> On Sat, 2006-08-26 at 04:48 -0500, Richard Smith wrote:
>   
>>>  I do not even get any comms from the serial port. Have checked the cable is
>>> ok, by
>>>  booting normally.
>>>
>>>  I only have 100Mhz memory installed, as it was going spare. Could this be a
>>> reason why
>>>  it does not work ?
>>>       
>> Com port messages start  happening pre-ram init.  So No. You should at
>> least some version info build date, and get to the "Jumping to
>> LinuxBIOS..."  string.
>>
>> Something must be different with the Com port on that board.
>>     
>
> Alternatively, what flash chip are you using? I don't know about your
> EPIA 5000, but my EPIA V came with a 256 KiB flash chip from the
> factory, and I bought a 512 KiB one that I'm playing with. That means,
> however, that when I'm making a 256 KiB LinuxBIOS flash image, I have to
> make sure to prepend it with 256 KiB of padding, to ensure that it hits
> the top of the address space.
>
> If that's the problem, you can just do this:
> dd if=/dev/zero bs=1k count=256 | cat - linuxbios.rom >512kbios
> flashrom -w 512kbios
>
> Fredrik Tolf
>
>
>
>   
I have a bios savour installed which has the original bios in it and I
am using the on-board flash for linuxbios. Both are 256k  (39SF020A)
part. I am assuming, maybe wrongly that EPIA V and the EPIA 5000 are the
same board.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060826/a9c3a901/attachment.html>

From fredrik at dolda2000.com  Sat Aug 26 14:30:47 2006
From: fredrik at dolda2000.com (Fredrik Tolf)
Date: Sat, 26 Aug 2006 14:30:47 +0200
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <44F03DA0.2020008@hewson-venieri.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>
	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>
	<1156379483.16966.20.camel@pc7.dolda2000.com>
	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>
	<1156468594.16966.32.camel@pc7.dolda2000.com>
	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>
	<1156471054.16966.42.camel@pc7.dolda2000.com>
	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>
	<44EF37F5.4010107@hewson-venieri.com>
	<8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>
	<1156594260.16966.47.camel@pc7.dolda2000.com>
	<44F03DA0.2020008@hewson-venieri.com>
Message-ID: <1156595447.16966.52.camel@pc7.dolda2000.com>

On Sat, 2006-08-26 at 13:25 +0100, Ben Hewson wrote:
> Fredrik Tolf wrote: 
> > On Sat, 2006-08-26 at 04:48 -0500, Richard Smith wrote:
> > > Something must be different with the Com port on that board.
> > 
> > Alternatively, what flash chip are you using? I don't know about your
> > EPIA 5000, but my EPIA V came with a 256 KiB flash chip from the
> > factory, and I bought a 512 KiB one that I'm playing with. That means,
> > however, that when I'm making a 256 KiB LinuxBIOS flash image, I have to
> > make sure to prepend it with 256 KiB of padding, to ensure that it hits
> > the top of the address space.
>   
> I have a bios savour installed which has the original bios in it and I
> am using the on-board flash for linuxbios. Both are 256k  (39SF020A)
> part.

I see, then that's probably not it. I'm "hotplugging" the BIOS chips by
hand.

> I am assuming, maybe wrongly that EPIA V and the EPIA 5000 are the
> same board.

Since you're using SDRAM, I cannot imagine there being any larger
differences, but just for reference, my board has a VT8601A northbridge
and a VT8231 southbridge. If your board are using the same, then I guess
that they are at least functionally equivalent.

Fredrik Tolf





From ben at hewson-venieri.com  Sat Aug 26 18:35:53 2006
From: ben at hewson-venieri.com (Ben Hewson)
Date: Sat, 26 Aug 2006 17:35:53 +0100
Subject: [LinuxBIOS] Booting LinuxBIOS on an EPIA-V
In-Reply-To: <1156595447.16966.52.camel@pc7.dolda2000.com>
References: <1156377121.16966.6.camel@pc7.dolda2000.com>	<8a0c36780608231702sbea72a2t5caedca6193bf8e9@mail.gmail.com>	<1156379483.16966.20.camel@pc7.dolda2000.com>	<8a0c36780608231804s43db773fyb4aeb0cec3134c50@mail.gmail.com>	<1156468594.16966.32.camel@pc7.dolda2000.com>	<8a0c36780608241819i512567dcuda7dcc4260b15995@mail.gmail.com>	<1156471054.16966.42.camel@pc7.dolda2000.com>	<8a0c36780608241950v28962dedxa0d965555bd96ab4@mail.gmail.com>	<44EF37F5.4010107@hewson-venieri.com>	<8a0c36780608260248j80d02c9l1b440d5f9bd37c84@mail.gmail.com>	<1156594260.16966.47.camel@pc7.dolda2000.com>	<44F03DA0.2020008@hewson-venieri.com>
	<1156595447.16966.52.camel@pc7.dolda2000.com>
Message-ID: <44F07869.4040903@hewson-venieri.com>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060826/88e73341/attachment.html>

From guillaume.fortaine at wanadoo.fr  Sat Aug 26 19:54:44 2006
From: guillaume.fortaine at wanadoo.fr (William DUCK)
Date: Sat, 26 Aug 2006 19:54:44 +0200
Subject: [LinuxBIOS] Microkernel  / Manufacturers
Message-ID: <200608261954.44253.guillaume.fortaine@wanadoo.fr>

Hello,

I am currently involved into the UEFI project.

I would want to build an Open Source UEFI firmware in the style of 
U-Boot/LinuxBIOS but to boot a microkernel.

Which manufacturer could I contact to build a firmware ? ( to have the 
specs/datasheets of the hardware)

If you want to contact me, my mail is guillaume_dot_fortaine_at_wanadoo_dot_fr

I will set up a mailing-list, a web server, a wiki and an IRC

Thank you for your answer,

Best Regards,

                   WIll



From rminnich at gmail.com  Sat Aug 26 21:50:34 2006
From: rminnich at gmail.com (ron minnich)
Date: Sat, 26 Aug 2006 13:50:34 -0600
Subject: [LinuxBIOS] Microkernel / Manufacturers
In-Reply-To: <200608261954.44253.guillaume.fortaine@wanadoo.fr>
References: <200608261954.44253.guillaume.fortaine@wanadoo.fr>
Message-ID: <13426df10608261250s725e37a8w9508db2c2d31c991@mail.gmail.com>

On 8/26/06, William DUCK <guillaume.fortaine at wanadoo.fr> wrote:
>
> Hello,
>
> I am currently involved into the UEFI project.



I am curious, what code base are you using? Has UEFI released any open
source code?


I would want to build an Open Source UEFI firmware in the style of
> U-Boot/LinuxBIOS but to boot a microkernel.



What is the reason for UEFI? It's not a very good design. Why not just use
linux as your bios instead, as we are doing on OLPC? We have successfully
booted all kinds of OSes with Linux and/or LinuxBIOS. There is nothing
special about a microkernel vis a vis a boot loader. What special attribute
does UEFI have that makes it necessary?


Which manufacturer could I contact to build a firmware ? ( to have the
> specs/datasheets of the hardware)



Do you object to GPL? If not, you could just use linuxbios as the foundation
for your UEFI, and save a lot of work on the messy device startup code. I
think we would be happy to help you.

But first, you might want to think hard about the following question: Why
UEFI, when you could use Linux to boot your microkernel instead? The big
advantage to using Linux as a bootloader, is that you can test the whole
boot path under Linux; it's really a wonderful way to go!

thanks

ron
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060826/f3df0b78/attachment.html>

From svn at openbios.org  Mon Aug 28 18:18:32 2006
From: svn at openbios.org (svn at openbios.org)
Date: Mon, 28 Aug 2006 18:18:32 +0200
Subject: [LinuxBIOS] r2392 - trunk/LinuxBIOSv2/src/southbridge/amd/cs5536
Message-ID: <E1GHjom-0000eo-9R@khepri.openbios.org>

Author: rsmith
Date: 2006-08-28 18:18:32 +0200 (Mon, 28 Aug 2006)
New Revision: 2392

Modified:
   trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
Log:
- Much better USB P4 fix. 

This one actualy works.  You cannot just go mucking about with stuff that the VSA
has under its thumb.  Bad Things happen.  This does it the VSA way.



Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-25 19:29:57 UTC (rev 2391)
+++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c	2006-08-28 16:18:32 UTC (rev 2392)
@@ -146,56 +146,27 @@
 	/* Southbridge (80007800 = 00.0F.00) */
 	pci_assign_irqs(0, 0x0F, slots_sb);	/* bus=0, device=0x0F, slots={11,5,10,10} */
 #endif
-	/* disable unwanted virtual PCI devices */
-	for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
-		printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]);
-		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
-		outl(0xDEADBEEF,                  0xCFC);
-	}
 
 	if (sb->enable_USBP4_host) {
-		volatile unsigned long* uocmux;
 		unsigned long val;
+		unsigned long uocmux;
 
+		outl(0x80007F10, 0xCF8);
+		outl(0x0EFC00000, 0xCFC);
 
-		printk_err("DES 0x%08x\n",MSR_SB_USB2_MEM_DES);
-		
-		msr = rdmsr(MSR_SB_USB2_MEM_DES);
-		printk_err("DES 0x%08x%08x\n", msr.hi,msr.lo);
+		uocmux = *((unsigned long *) 0x0EFC00004);
+		uocmux &= ~3;
+		uocmux |= 2;
 
-		msr.hi = 0x400000fe;
-		msr.lo = 0x010fffff;
-
-		wrmsr(MSR_SB_USB2_MEM_DES, msr);
-
-		msr = rdmsr(MSR_SB_USB2_MEM_DES);
-		printk_err("New DES 0x%08x%08x\n", msr.hi,msr.lo);
-
-		msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE);
-		printk_err("Old UOC Base 0x%08x%08x\n", msr.hi,msr.lo);
-		msr.hi |= 0xa;
-		msr.lo |= 0xfe010000;
-	
-		wrmsr(USB2_SB_GLD_MSR_UOC_BASE, msr);
-
-		msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE);
-		printk_err("New UOC Base 0x%08x%08x\n", msr.hi,msr.lo);
-
-		uocmux = (unsigned long *)(msr.lo+4);
-		val = *uocmux;
-
-		printk_err("UOCMUX is 0x%lx\n",val);
-
-		val &= ~(0x3);
-		val |= 0x2;
-
-		*uocmux = val;
-
-		val = *uocmux;
-		printk_err("New UOCMUX is 0x%lx\n",val);
-
+		*((unsigned long *) 0x0EFC00004) = uocmux;
 	}
 
+	/* disable unwanted virtual PCI devices */
+	for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
+		printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]);
+		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
+		outl(0xDEADBEEF,                  0xCFC);
+	}
 }
 
 




From uwe at hermann-uwe.de  Tue Aug 29 01:41:36 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 29 Aug 2006 01:41:36 +0200
Subject: [LinuxBIOS] IT8661F support.
Message-ID: <20060828234136.GA13864@aragorn>

Hi,

here's another ITE Super IO. Untested, but compiles.


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/superio/ite/it8661f/Config.lb
===================================================================
--- src/superio/ite/it8661f/Config.lb	(Revision 0)
+++ src/superio/ite/it8661f/Config.lb	(Revision 0)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
Index: src/superio/ite/it8661f/it8661f_early_serial.c
===================================================================
--- src/superio/ite/it8661f/it8661f_early_serial.c	(Revision 0)
+++ src/superio/ite/it8661f/it8661f_early_serial.c	(Revision 0)
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8661f.h"
+
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE                   0x3f0
+#define SIO_INDEX                  SIO_BASE
+#define SIO_DATA                   SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8661F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
+#define IT8661F_CONFIG_REG_LDN     0x07   /* Logical Device Number. */
+#define IT8661F_CONFIG_REG_LDE     0x23   /* PnP Logical Device Enable. */
+#define IT8661F_CONFIG_REG_SWSUSP  0x24   /* Software Suspend + Clock Select. */
+
+#define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
+
+/* Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data. */
+static const uint8_t init_values[] = {
+	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+/* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8661F Super IO chip. */
+static void it8661f_enable_serial(device_t dev, unsigned iobase)
+{
+	uint8_t i;
+
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+	outb(0x86, IT8661F_CONFIGURATION_PORT);
+	outb(0x80, IT8661F_CONFIGURATION_PORT);
+	outb(0x55, IT8661F_CONFIGURATION_PORT);
+	outb(0x55, IT8661F_CONFIGURATION_PORT);
+
+	/* Sequentially write the 32 special values. */
+	for (i = 0; i < 32; i++) {
+		outb(init_values[i], SIO_BASE);
+	}
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
+	   PP (3), IR (4). Bits 5-7 are reserved. */
+	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f);
+
+	/* Enable all devices. */
+	it8661f_sio_write(IT8661F_FDC,  0x30, 0x1); /* Floppy */
+	it8661f_sio_write(IT8661F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8661f_sio_write(IT8661F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8661f_sio_write(IT8661F_PP,   0x30, 0x1); /* Parallel port */
+	it8661f_sio_write(IT8661F_IR,   0x30, 0x1); /* IR */
+
+	/* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
+           (clear bit 0). */
+	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00);
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02); 
+}
+
Index: src/superio/ite/it8661f/superio.c
===================================================================
--- src/superio/ite/it8661f/superio.c	(Revision 0)
+++ src/superio/ite/it8661f/superio.c	(Revision 0)
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This chip doesn't seem to have keyboard and mouse support. */
+
+#include <uart8250.h>
+/* #include <pc80/keyboard.h> */
+#include "chip.h"
+#include "it8661f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8661f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8661F_FDC: /* TODO. */
+		break;
+	case IT8661F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8661F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8661F_PP: /* TODO. */
+		break;
+	case IT8661F_IR: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, IR, GPIO. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8661F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8661F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8661f_ops = {
+	CHIP_NAME("ITE it8661f")
+	.enable_dev = enable_dev,
+};
+
Index: src/superio/ite/it8661f/chip.h
===================================================================
--- src/superio/ite/it8661f/chip.h	(Revision 0)
+++ src/superio/ite/it8661f/chip.h	(Revision 0)
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8661F
+#define _SUPERIO_ITE_IT8661F
+
+/* This chip doesn't seem to have keyboard and mouse support. */
+
+/* #include <pc80/keyboard.h> */
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8661f_ops;
+
+struct superio_ITE_it8661f_config {
+	struct uart8250 com1, com2;
+	/* struct pc_keyboard keyboard; */
+};
+
+#endif /* _SUPERIO_ITE_IT8661F */
+
Index: src/superio/ite/it8661f/it8661f.h
===================================================================
--- src/superio/ite/it8661f/it8661f.h	(Revision 0)
+++ src/superio/ite/it8661f/it8661f.h	(Revision 0)
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */
+/* Status: untested on real hardware, but it compiles. */
+
+/* This chip doesn't seem to have keyboard and mouse support. */
+
+#define IT8661F_FDC  0x00 /* Floppy */
+#define IT8661F_SP1  0x01 /* Com1 */
+#define IT8661F_SP2  0x02 /* Com2 */
+#define IT8661F_PP   0x03 /* Parallel port */
+#define IT8661F_IR   0x04 /* IR */
+#define IT8661F_GPIO 0x05 /* GPIO & Alternate Function Configuration */
+
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060829/b7b3475e/attachment.sig>

From svn at openbios.org  Tue Aug 29 02:45:42 2006
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 29 Aug 2006 02:45:42 +0200
Subject: [LinuxBIOS] r2393 - in trunk/LinuxBIOSv2/src/superio/ite: . it8661f
Message-ID: <E1GHrja-0004Is-Sf@khepri.openbios.org>

Author: stepan
Date: 2006-08-29 02:45:42 +0200 (Tue, 29 Aug 2006)
New Revision: 2393

Added:
   trunk/LinuxBIOSv2/src/superio/ite/it8661f/
   trunk/LinuxBIOSv2/src/superio/ite/it8661f/Config.lb
   trunk/LinuxBIOSv2/src/superio/ite/it8661f/chip.h
   trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f.h
   trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c
   trunk/LinuxBIOSv2/src/superio/ite/it8661f/superio.c
Log:
it8661f support from Uwe Hermann


Added: trunk/LinuxBIOSv2/src/superio/ite/it8661f/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8661f/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8661f/Config.lb	2006-08-29 00:45:42 UTC (rev 2393)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o

Added: trunk/LinuxBIOSv2/src/superio/ite/it8661f/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8661f/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8661f/chip.h	2006-08-29 00:45:42 UTC (rev 2393)
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8661F
+#define _SUPERIO_ITE_IT8661F
+
+/* This chip doesn't seem to have keyboard and mouse support. */
+
+/* #include <pc80/keyboard.h> */
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8661f_ops;
+
+struct superio_ITE_it8661f_config {
+	struct uart8250 com1, com2;
+	/* struct pc_keyboard keyboard; */
+};
+
+#endif /* _SUPERIO_ITE_IT8661F */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f.h	2006-08-29 00:45:42 UTC (rev 2393)
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */
+/* Status: untested on real hardware, but it compiles. */
+
+/* This chip doesn't seem to have keyboard and mouse support. */
+
+#define IT8661F_FDC  0x00 /* Floppy */
+#define IT8661F_SP1  0x01 /* Com1 */
+#define IT8661F_SP2  0x02 /* Com2 */
+#define IT8661F_PP   0x03 /* Parallel port */
+#define IT8661F_IR   0x04 /* IR */
+#define IT8661F_GPIO 0x05 /* GPIO & Alternate Function Configuration */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c	2006-08-29 00:45:42 UTC (rev 2393)
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8661f.h"
+
+/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
+#define SIO_BASE                   0x3f0
+#define SIO_INDEX                  SIO_BASE
+#define SIO_DATA                   SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8661F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
+#define IT8661F_CONFIG_REG_LDN     0x07   /* Logical Device Number. */
+#define IT8661F_CONFIG_REG_LDE     0x23   /* PnP Logical Device Enable. */
+#define IT8661F_CONFIG_REG_SWSUSP  0x24   /* Software Suspend + Clock Select. */
+
+#define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
+
+/* Special values used for entering MB PnP mode. The first four bytes of
+ * each line determine the address port, the last four are data. */
+static const uint8_t init_values[] = {
+	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
+	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
+	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
+	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
+};
+
+/* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8661F Super IO chip. */
+static void it8661f_enable_serial(device_t dev, unsigned iobase)
+{
+	uint8_t i;
+
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
+	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
+	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
+	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
+	outb(0x86, IT8661F_CONFIGURATION_PORT);
+	outb(0x80, IT8661F_CONFIGURATION_PORT);
+	outb(0x55, IT8661F_CONFIGURATION_PORT);
+	outb(0x55, IT8661F_CONFIGURATION_PORT);
+
+	/* Sequentially write the 32 special values. */
+	for (i = 0; i < 32; i++) {
+		outb(init_values[i], SIO_BASE);
+	}
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
+	   PP (3), IR (4). Bits 5-7 are reserved. */
+	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f);
+
+	/* Enable all devices. */
+	it8661f_sio_write(IT8661F_FDC,  0x30, 0x1); /* Floppy */
+	it8661f_sio_write(IT8661F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8661f_sio_write(IT8661F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8661f_sio_write(IT8661F_PP,   0x30, 0x1); /* Parallel port */
+	it8661f_sio_write(IT8661F_IR,   0x30, 0x1); /* IR */
+
+	/* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
+           (clear bit 0). */
+	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00);
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02); 
+}
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8661f/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8661f/superio.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8661f/superio.c	2006-08-29 00:45:42 UTC (rev 2393)
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This chip doesn't seem to have keyboard and mouse support. */
+
+#include <uart8250.h>
+/* #include <pc80/keyboard.h> */
+#include "chip.h"
+#include "it8661f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8661f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8661F_FDC: /* TODO. */
+		break;
+	case IT8661F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8661F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8661F_PP: /* TODO. */
+		break;
+	case IT8661F_IR: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, IR, GPIO. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8661F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8661F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8661f_ops = {
+	CHIP_NAME("ITE it8661f")
+	.enable_dev = enable_dev,
+};
+




From uwe at hermann-uwe.de  Tue Aug 29 12:16:01 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 29 Aug 2006 12:16:01 +0200
Subject: [LinuxBIOS] License clarification, round 1
Message-ID: <20060829101600.GE6649@aragorn>

Hi all,

this will probably make me very unpopular around here, but oh well... ;)

I've started looking at _all_ files in svn and checking their respective
license to see if it's GPL'd or at least has another Free Software license.
Also, all such licenses must be GPL compatible, too, AFAIK (but I'm no
lawyer).

This is important for a) the Debian package, which must meet the DSFG
(Debian Free Software Guidelines), see
http://www.us.debian.org/social_contract#guidelines
and b) for the legal status of the LinuxBIOS project itself, as
any non-free-software/non-gpl-compatible code in the repository would
probably be illegal to distribute (depending on the exact license
terms), may cause all kinds of other legal hassle and just simply
compromise the whole idea of the project - to have a _free_ implementation.

So here I am, reading through all files, taking notes which of them
are not GPL'd. Please check the list and clarify the exact license
status of the files, e.g. by adding a GPL header similar to this one below:

/*
 * Copyright (C) 200x Author Name <email at example.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

(or at least a tiny note saying "this file is copyright 200x John Doe and
is licensed under the GPL)...

I'm happy to provide patches which add the above license header to all files,
but someone has to tell me who wrote the code, when, and which license applies
(if that's not obvious from the code).

I noticed that many files do not have any license header at all (some don't
even say who the author is); such files have an unclear status and must be
considered non-free usually, so in cases where that's just an oversight,
please add a respective license note. If the file was taken from another
project, please add a note saying so, and mention the license of that project
in the file.

Assumption: All *.lb config files are GPL'd even though they don't have
the lengthy GPL header in them. Correct? I don't think it's necessary for
those files. The same is probably true for ChangeLog, NEWS, and
documentation/ChangeLog.cvsimport, etc.

The biggest problems I notices so far is the code from IBM and AMD, which says
things like "Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved"
or stuff like:
  LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  US Government Users Restricted Rights - Use, duplication or
  disclosure restricted by GSA ADP Schedule Contract with
  IBM Corp. 

That alone (which no additional "this is GPL'd" text would make the code non-free and
GPL-incompatible, I guess. I hope this can be resolved or clarified somehow.

I also found some licenses which I simply don't know and cannot tell
right now if they're fine or not - that has to be checked at some point.

Anyways, here's the list of issues I noticed so far (haven't checked all the code, yet):

--------------------------------------------------------------------------------
HOWTO/EPIA-M-howto: No license note.
documentation/Makefile: No license note.
documentation/RFC/*: No license note.
  * Is that stuff used at all?
documentation/*.eps: No license note.
  * I assume this is GPL'd as LinuxBIOS-AMD64.tex is GPL'd. Correct?
src/arch/i386/boot/acpi.c:
  * Says among other things
    "Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved."
    which is bad as it means it's NOT GPL'd and you cannot use it for anything,
    really. No explicit permissions means you have no rights according to
    international copyright laws, AFAIK (but I'm no lawyer).
src/arch/i386/boot/boot.c: No license note.
src/arch/i386/boot/linuxbios_table.*: No license note.
src/arch/i386/boot/pirq_routing.c: No license note.
src/arch/i386/boot/tables.c:
 * Says: 2006.1 yhlu add mptable cross 0x467 processing
         2003-07 by SONE Takeshi
         Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
   Etherboot is GPL'd (mostly, some parts are BSD), so this is GPL'd, right?
src/arch/i386/include/*.h: No license note.
src/arch/i386/include/arch/acpi.h:
 * Now this is totally confusing.
   * written by Stefan Reinauer <stepan at openbios.org> (GPL'd?)
   * (C) 2004 SUSE LINUX AG (license?)
   * The ACPI table structs are based on the Linux kernel sources. (GPL'd!)
   * ACPI FADT & FACS added by Nick Barker <nick.barker9 at btinternet.com>
     those parts (C) 2004 Nick Barker (license?)
   * ACPI SRAT support added in 2005.9 by yhlu (license?)
   * Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
     ---> Baaad...
src/arch/i386/include/arch/intel.h:
  * Not sure what to make of this... It's not the GPL, it's not the BSD
    license (or the MIT license), either. ((2))
    Is this GPL compatible?
      /* This software and ancillary information (herein called SOFTWARE )
      called LinuxBIOS          is made available under the terms described
      here.  The SOFTWARE has been approved for release with associated
      LA-CC Number 00-34   .  Unless otherwise indicated, this SOFTWARE has
      been authored by an employee or employees of the University of
      California, operator of the Los Alamos National Laboratory under
      Contract No. W-7405-ENG-36 with the U.S. Department of Energy.  The
      U.S. Government has rights to use, reproduce, and distribute this
      SOFTWARE.  The public may copy, distribute, prepare derivative works
      and publicly display this SOFTWARE without charge, provided that this
      Notice and any statement of authorship are reproduced on all copies.
      Neither the Government nor the University makes any warranty, express
      or implied, or assumes any liability or responsibility for the use of
      this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
      such modified SOFTWARE should be clearly marked, so as not to confuse
      it with the version available from LANL.  */
      /* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
       * rminnich at lanl.gov */
src/arch/i386/include/arch/*.h (except for the above ones): No license note.
src/arch/i386/include/arch/boot/boot.h: No license note.
src/arch/i386/include/arch/smp/*.h: No license note.
src/arch/i386/init/ldscript.lb:
 * Says: Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
   Not good...
src/arch/i386/lib/printk_init.c:
 * Copyright (C) 1991, 1992  Linus Torvalds
   No explicit license note, but it's quite surely GPL ((1)).
src/arch/i386/lib/*: No license note.
src/arch/i386/llshell/readme.linuxbios: No license note.
 * Probably GPL'd, as the file it documents (llshell.inc) is GPL'd.
src/arch/i386/smp/*: No license note.
src/arch/ppc/boot/*: No license note.
src/arch/ppc/include/ppc4xx.h:
 * Strange non-standard header, not sure what to make of it.
     This source code has been made available to you by IBM on an AS-IS
     basis.  Anyone receiving this source is licensed under IBM
     copyrights to use it in any way he or she deems fit, including
     copying it, modifying it, compiling it, and redistributing it either
     with or without modifications.  No license under IBM patents or
     patent applications is to be implied by the copyright license.
   
     Any user of this software should understand that IBM cannot provide
     technical support for this software and will not be responsible for
     any consequences resulting from the use of this software.
   
     Any person who transfers this source code or any derivative work
     must include the IBM copyright notice, this paragraph, and the
     preceding two paragraphs in the transferred software.
   
     COPYRIGHT   I B M   CORPORATION 1999
     LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
src/arch/ppc/include/ppc970.h:
  COPYRIGHT   I B M   CORPORATION 2003
  LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  US Government Users Restricted Rights - Use, duplication or
  disclosure restricted by GSA ADP Schedule Contract with
  IBM Corp.
src/arch/ppc/include/*.* (except for the above ones): No license note.
src/arch/ppc/include/arch/*.h: No license note.
src/arch/ppc/include/arch/boot/*.h: No license note.
src/arch/ppc/init/ldscript.lb:
 * No license, but some authors:
     Written by Johan Rydberg, based on work by Daniel Kahlin.
     Rewritten by Eric Biederman
     Re-rewritten by Greg Watson for PPC
src/arch/ppc/init/ppc_main.c:
 * No license, but an author:
     Copyright (C) 2003 by Greg Watson, Los Alamos National Laboratory
     gwatson at lanl.gov
src/arch/ppc/lib/cpu.c: No license note.
src/arch/ppc/lib/pci_dev.c: No license note.
src/arch/ppc/lib/pci_ppc_conf1_ops.c: No license note.
src/boot/hardwaremain.c: Same as ((2)).
src/config/LinuxBIOSDoc.config: No license note (GPL?).
src/config/doxyscript.base: No license note (GPL?).
src/config/linuxbios_ram.ld:
 * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
   --> Bad.
src/console/btext_console.c: No license note, but some authors:
 * Benjamin Herrenschmidt <benh at kernel.crashing.org>
   move to LinuxBIOS by LYH yhlu at tyan.com
src/console/font-8x16.c: Same as ((1)).
src/console/printk.c: Same as ((1)).
src/console/vga_console.c: No license note, but an author:
 * modified from original freebios code
   by Steve M. Gehlbach <steve at kesa.com>
src/console/vsprintf.c: Same as ((1)).
src/console/vtxprintf.c: Same as ((1)).

targets/buildtarget: No license note. The rest of target/ has no license, too,
but should be fine (mostly config files).
--------------------------------------------------------------------------------

HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060829/a45e7213/attachment.sig>

From lionel at mamane.lu  Tue Aug 29 17:03:12 2006
From: lionel at mamane.lu (Lionel Elie Mamane)
Date: Tue, 29 Aug 2006 17:03:12 +0200
Subject: [LinuxBIOS] Tyan s2895 clarification
Message-ID: <20060829150312.GE27931@capsaicin.mamane.lu>

Hi,

I'm confused. My Tyan s2895 has a 8Mbit LPC Flash ROM, so I thought I
could not use a RD1 Bios Savior, as no 8Mbit model was available; this
kept me from trying out LinuxBIOS by fear of turning my computer into
an expensive paper weight. But now I see posts to this ML's archive
(such as
http://www.linuxbios.org/pipermail/linuxbios/2006-January/013420.html)
that talk about using 4Mbit savior with the Tyan s2895.

Quid?

-- 
Lionel



From lionel at mamane.lu  Tue Aug 29 17:10:45 2006
From: lionel at mamane.lu (Lionel Elie Mamane)
Date: Tue, 29 Aug 2006 17:10:45 +0200
Subject: [LinuxBIOS] Bounty for LinuxBIOS on VIA C7 platform
Message-ID: <20060829151045.GF27931@capsaicin.mamane.lu>

Hi,

Anybody interested in a bounty for adding support of a motherboard
that can take a Via C7 CPU to LinuxBIOS? (For example the VIA EPIA CN
or VIA EPIA EN.)

-- 
Lionel



From smithbone at gmail.com  Tue Aug 29 17:42:30 2006
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 29 Aug 2006 10:42:30 -0500
Subject: [LinuxBIOS] License clarification, round 1
In-Reply-To: <20060829101600.GE6649@aragorn>
References: <20060829101600.GE6649@aragorn>
Message-ID: <8a0c36780608290842y556b6b5cwda811992c8d78002@mail.gmail.com>

> I've started looking at _all_ files in svn and checking their respective
> license to see if it's GPL'd or at least has another Free Software license.
> Also, all such licenses must be GPL compatible, too, AFAIK (but I'm no
> lawyer).
>
> This is important for a) the Debian package, which must meet the DSFG
> (Debian Free Software Guidelines), see

Uwe,

Wow thats quite a list.  Thank you for doing this.  This is also going
to be very important for OLPC.  We will be releasing some stuff in the
near future and I'm sure this issue will come up.

-- 
Richard A. Smith



From uwe at hermann-uwe.de  Tue Aug 29 18:27:47 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 29 Aug 2006 18:27:47 +0200
Subject: [LinuxBIOS] IT8718F support.
Message-ID: <20060829162747.GA25404@aragorn>

Hi, here's some code for the IT8718F. Untested, but compiles.

Please also checkin my patch at
http://www.linuxbios.org/pipermail/linuxbios/2006-August/015412.html
I think that got overlooked (or is there a technical problem with it?).

Btw, is the code for the Super IOs supposed to initialize/enable _all_
supported devices or merely COM1/COM2 and the rest gets enabled
later on?


U "I read ITE datasheets when I'm bored" we.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/superio/ite/it8718f/it8718f.h
===================================================================
--- src/superio/ite/it8718f/it8718f.h	(Revision 0)
+++ src/superio/ite/it8718f/it8718f.h	(Revision 0)
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
+/* Status: untested on real hardware, but it compiles. */
+
+#define IT8718F_FDC  0x00 /* Floppy */
+#define IT8718F_SP1  0x01 /* Com1 */
+#define IT8718F_SP2  0x02 /* Com2 */
+#define IT8718F_PP   0x03 /* Parallel port */
+#define IT8718F_EC   0x04 /* Environment controller */
+#define IT8718F_KBCK 0x05 /* Keyboard */
+#define IT8718F_KBCM 0x06 /* Mouse */
+#define IT8718F_IR   0x0a /* Consumer IR */
+
Index: src/superio/ite/it8718f/Config.lb
===================================================================
--- src/superio/ite/it8718f/Config.lb	(Revision 0)
+++ src/superio/ite/it8718f/Config.lb	(Revision 0)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
Index: src/superio/ite/it8718f/it8718f_early_serial.c
===================================================================
--- src/superio/ite/it8718f/it8718f_early_serial.c	(Revision 0)
+++ src/superio/ite/it8718f/it8718f_early_serial.c	(Revision 0)
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8718f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE                     0x2e
+#define SIO_INDEX                    SIO_BASE
+#define SIO_DATA                     SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8718F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8718F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8718F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8718F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+
+#define IT8718F_CONFIGURATION_PORT   0x2e /* Write-only. */
+
+/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8718F Super IO chip. */
+static void it8718f_enable_serial(device_t dev, unsigned iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x2e. */
+	/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+	/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+	outb(0x87, IT8718F_CONFIGURATION_PORT);
+	outb(0x01, IT8718F_CONFIGURATION_PORT);
+	outb(0x55, IT8718F_CONFIGURATION_PORT);
+	outb(0x55, IT8718F_CONFIGURATION_PORT);
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Select the chip to configure (if there's more than one).
+         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+         * If this register is not written, both chips are configured. */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+	/* Enable all devices. */
+	it8718f_sio_write(IT8718F_FDC,  0x30, 0x1); /* Floppy */
+	it8718f_sio_write(IT8718F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8718f_sio_write(IT8718F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8718f_sio_write(IT8718F_PP,   0x30, 0x1); /* Parallel port */
+	it8718f_sio_write(IT8718F_EC,   0x30, 0x1); /* Environment controller */
+	it8718f_sio_write(IT8718F_KBCK, 0x30, 0x1); /* Keyboard */
+	it8718f_sio_write(IT8718F_KBCM, 0x30, 0x1); /* Mouse */
+	it8718f_sio_write(IT8718F_IR,   0x30, 0x1); /* Consumer IR */
+
+	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x00); */
+
+	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); 
+}
+
Index: src/superio/ite/it8718f/superio.c
===================================================================
--- src/superio/ite/it8718f/superio.c	(Revision 0)
+++ src/superio/ite/it8718f/superio.c	(Revision 0)
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "it8718f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8718f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8718F_FDC: /* TODO. */
+		break;
+	case IT8718F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8718F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8718F_PP: /* TODO. */
+		break;
+	case IT8718F_EC: /* TODO. */
+		break;
+	case IT8718F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	case IT8718F_KBCM: /* TODO. */
+		break;
+	case IT8718F_IR: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, EC, KBCM, IR. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8718F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8718F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8718f_ops = {
+	CHIP_NAME("ITE it8718f")
+	.enable_dev = enable_dev,
+};
+
Index: src/superio/ite/it8718f/chip.h
===================================================================
--- src/superio/ite/it8718f/chip.h	(Revision 0)
+++ src/superio/ite/it8718f/chip.h	(Revision 0)
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8718F
+#define _SUPERIO_ITE_IT8718F
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8718f_ops;
+
+struct superio_ITE_it8718f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif /* _SUPERIO_ITE_IT8718F */
+
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060829/73939002/attachment.sig>

From stepan at coresystems.de  Tue Aug 29 18:33:31 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 29 Aug 2006 18:33:31 +0200
Subject: [LinuxBIOS] License clarification, round 1
In-Reply-To: <20060829101600.GE6649@aragorn>
References: <20060829101600.GE6649@aragorn>
Message-ID: <20060829163331.GA23377@coresystems.de>

Hi Uwe,

thank you very much for your acribic arduousness. 

I hope I can lower your apprehensions in this case a bit:

* Uwe Hermann <uwe at hermann-uwe.de> [060829 12:16]:
> I've started looking at _all_ files in svn and checking their respective
> license to see if it's GPL'd or at least has another Free Software license.
> Also, all such licenses must be GPL compatible, too, AFAIK (but I'm no
> lawyer).
 
The answer here is easy. Every line of LinuxBIOS code is GPL. And 
every line of code we will include in the future will become GPL by the
implicit agreement of the contributor to use LinuxBIOS and to enhance
it. 

> and b) for the legal status of the LinuxBIOS project itself, as
> any non-free-software/non-gpl-compatible code in the repository would
> probably be illegal to distribute (depending on the exact license
> terms), may cause all kinds of other legal hassle and just simply
> compromise the whole idea of the project - to have a _free_ implementation.
 
This is why we have been doing code reviews and have been in close
contact with the contributors to make sure we do not include otherwise
licensed or protected code.

> So here I am, reading through all files, taking notes which of them
> are not GPL'd. Please check the list and clarify the exact license
> status of the files, e.g. by adding a GPL header similar to this one below:
 
All of them are GPLed, as a consequence of the inclusion in LinuxBIOS.
Also, files do not need a header stating their license, as the license
is absolutely obvious to everyone downloading the code. We might want to
have them in most files anyways.

> I'm happy to provide patches which add the above license header to all files,
> but someone has to tell me who wrote the code, when, and which license applies
> (if that's not obvious from the code).
> 
> I noticed that many files do not have any license header at all (some don't
> even say who the author is); such files have an unclear status and must be
> considered non-free usually, so in cases where that's just an oversight,
> please add a respective license note.

No they must not. Who would say they must? Legally absolutely obvious
that the files have been checked by those with checkin capabilities to
be free.

An example: Not every song on a CD needs a copyright note spoken before
the song starts. it is completely sufficient to print the copyright once
on the CD.

> If the file was taken from another
> project, please add a note saying so, and mention the license of that project
> in the file.
 
As we are using GPL as the license, only files with GPL license or with
licenses compatible to the GPL license have been included. All files in
the repository are licensed under the GPL. No exceptions. 

> Assumption: All *.lb config files are GPL'd even though they don't have
> the lengthy GPL header in them. Correct? I don't think it's necessary for
> those files. The same is probably true for ChangeLog, NEWS, and
> documentation/ChangeLog.cvsimport, etc.

Yes it is not necessary, and we need to be careful not to bloat the
readability with comments like this. If we want to comment the 

> 
> The biggest problems I notices so far is the code from IBM and AMD, which says
> things like "Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved"

There is no problem with this. The fact that AMD released these files to
the public as GPL does not touch the fact that they own a copyright to
it. In fact, in Europe signing over copyrights is impossible as of
current law, so these notes are just fine. They read "This part has been
sponsored by AMD and they are allowed to make copies of it"

> or stuff like:

>   LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 
> That alone (which no additional "this is GPL'd" text would make the
> code non-free and GPL-incompatible, I guess. I hope this can be
> resolved or clarified somehow.
 
I would not see a legal regulation to back your assumption. The fact
that it is "licensed" does not make it non-free. the license is GPL,
because IBM acknowledged making it GPL by contributing to a GPL project.

And that its their property is not an issue. All programs a person
writes is that person's property unless the person does the development
work on a contractual basis in wich case the contractor owns the
property. This is an exciting area of law, but it has absolutely nothing
to do with wether LinuxBIOS is GPLed or not.

>   * I assume this is GPL'd as LinuxBIOS-AMD64.tex is GPL'd. Correct?
> src/arch/i386/boot/acpi.c:
>     "Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved."
>     which is bad as it means it's NOT GPL'd and you cannot use it for anything

where does it say that it is not GPL? Could not find the paragraph you
are talking about. Search the mailinglist archives for details on above
code. 

>     really. No explicit permissions means you have no rights according to
>     international copyright laws, AFAIK (but I'm no lawyer).

The "opus" (Werk) as such is explicitly GPL licensed, so the GPL applies
for every single line of code. I am not a lawyer either but I asked mine.

The single parts of the opus are of no more concern. Be it a file, a
subdirectory or a single line of the opus. They are all subordinated.



So unless we have an indication stating something different I suggest
what we do is emphasize that the whole of LinuxBIOS is GPL licensed by
the respective copyright holders. 

To make things clearer, I also suggest removing license descriptions
from every single source file in the tree and only have a single license
file stating the only valid project license. this way there will not be
confusion and we dont bloat the code with comments that dont comment
the code.


In case of such an indication we will immediately remove the code from
the repository.

Comments?


Stefan



From smithbone at gmail.com  Tue Aug 29 18:57:48 2006
From: smithbone at gmail.com (Richard Smith)
Date: Tue, 29 Aug 2006 11:57:48 -0500
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060829162747.GA25404@aragorn>
References: <20060829162747.GA25404@aragorn>
Message-ID: <8a0c36780608290957h391fc469ydf3beff7da824128@mail.gmail.com>

> Btw, is the code for the Super IOs supposed to initialize/enable _all_
> supported devices or merely COM1/COM2 and the rest gets enabled
> later on?
>

First it depends on the config file.  If the device is not enabled in
the config file then don't turn it on.  Com 1 being the exception..

Second depends if the kernel can turn it on or not.  In a lot of cases
if the kernel gets back an invalid read of the base address it assumes
the device is just not there or disabled for a reason.

Generally though for superIO stuff if the kernel can find it then it
can init it so just turning on the device so the base address shows up
should be enough.

-- 
Richard A. Smith



From svn at openbios.org  Tue Aug 29 19:41:14 2006
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 29 Aug 2006 19:41:14 +0200
Subject: [LinuxBIOS] r2394 - in trunk/LinuxBIOSv2/src/superio/ite: . it8671f
	it8718f
Message-ID: <E1GI7aM-0007xe-En@khepri.openbios.org>

Author: stepan
Date: 2006-08-29 19:41:14 +0200 (Tue, 29 Aug 2006)
New Revision: 2394

Added:
   trunk/LinuxBIOSv2/src/superio/ite/it8718f/
   trunk/LinuxBIOSv2/src/superio/ite/it8718f/Config.lb
   trunk/LinuxBIOSv2/src/superio/ite/it8718f/chip.h
   trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f.h
   trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c
   trunk/LinuxBIOSv2/src/superio/ite/it8718f/superio.c
Modified:
   trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h
   trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c
   trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c
Log:
merge latest code from Uwe Hermann


Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h	2006-08-29 00:45:42 UTC (rev 2393)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f.h	2006-08-29 17:41:14 UTC (rev 2394)
@@ -16,11 +16,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* TODO: Find datasheet and check for correct values. */
 #define IT8671F_FDC  0x00 /* Floppy */
-/* #define IT8671F_PP   0x01 */ /* Parallel port */
+#define IT8671F_SP1  0x01 /* Com1 */
 #define IT8671F_SP2  0x02 /* Com2 */
-#define IT8671F_SP1  0x03 /* Com1 */
-#define IT8671F_KBCK 0x06 /* Keyboard */
-/* #define IT8671F_FAN  0x09 */
+#define IT8671F_PP   0x03 /* Parallel port */
+#define IT8671F_KBCK 0x05 /* Keyboard */
+#define IT8671F_KBCM 0x06 /* Mouse */
 

Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c	2006-08-29 00:45:42 UTC (rev 2393)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c	2006-08-29 17:41:14 UTC (rev 2394)
@@ -20,18 +20,18 @@
 #include "it8671f.h"
 
 /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE  0x3f0
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA  SIO_BASE+1
+#define SIO_BASE                    0x3f0
+#define SIO_INDEX                   SIO_BASE
+#define SIO_DATA                    SIO_BASE+1
 
-/* TODO: These values are actually from the IT8673F datasheet; check if
-   they're also valid for the IT8671F. */
-#define IT8671F_CONFIG_REG_CC       0x02 /* Configure Control. */
-#define IT8671F_CONFIG_REG_LDN      0x07 /* Logical Device Number. */
-#define IT8671F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8671F_CONFIG_REG_SWSUSP   0x24 /* Software Suspend. */
+/* Global Configuration Registers. */
+#define IT8671F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
+#define IT8671F_CONFIG_REG_LDN     0x07   /* Logical Device Number. */
+#define IT8671F_CONFIG_REG_LDE     0x23   /* PnP Logical Device Enable. */
+#define IT8671F_CONFIG_REG_SWSUSP  0x24   /* Software Suspend. */
 
-#define IT8671F_ADDRESS_PORT        0x279
+#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
+#define IT8671F_WRITE_DATA_PORT    0x0A79 /* Write-only. */
 
 /* Special values used for entering MB PnP mode. The first four bytes of
  * each line determine the address port, the last four are data. */
@@ -42,7 +42,7 @@
 	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
 };
 
-/* The content of IT8671F_CONFIG_REG_LDN (index 07h) must be set to the
+/* The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the
  * LDN the register belongs to, before you can access the register. */
 static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 {
@@ -63,10 +63,10 @@
 	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
 	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
 	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
-	outb(0x86, IT8671F_ADDRESS_PORT);
-	outb(0x80, IT8671F_ADDRESS_PORT);
-	outb(0x55, IT8671F_ADDRESS_PORT);
-	outb(0x55, IT8671F_ADDRESS_PORT);
+	outb(0x86, IT8671F_CONFIGURATION_PORT);
+	outb(0x80, IT8671F_CONFIGURATION_PORT);
+	outb(0x55, IT8671F_CONFIGURATION_PORT);
+	outb(0x55, IT8671F_CONFIGURATION_PORT);
 
 	/* Sequentially write the 32 special values. */
 	for (i = 0; i < 32; i++) {
@@ -75,14 +75,20 @@
 
 	/* (2) Modify the data of configuration registers. */
 
-	/* Enable parallel port, serial port 1, serial port 2, floppy. */
-	it8671f_sio_write(0x00, 0x23, 0x0f);
+	/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
+           PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
+	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
 
-	/* Activate serial port 1 and 2. */
-	it8671f_sio_write(0x01, 0x30, 0x1);
-	it8671f_sio_write(0x02, 0x30, 0x1);
+	/* Activate all devices. */  
+	it8671f_sio_write(IT8671F_FDC,  0x30, 0x01); /* Floppy */
+	it8671f_sio_write(IT8671F_SP1,  0x30, 0x01); /* Serial port 1 */
+	it8671f_sio_write(IT8671F_SP2,  0x30, 0x01); /* Serial port 2 */
+	it8671f_sio_write(IT8671F_PP,   0x30, 0x01); /* Parallel port */
+	it8671f_sio_write(IT8671F_KBCK, 0x30, 0x01); /* Keyboard */
+	it8671f_sio_write(IT8671F_KBCM, 0x30, 0x01); /* Mouse */
 
-	/* Select 24MHz CLKIN and clear software suspend mode. */
+	/* Select 24MHz CLKIN (clear bit 6) and clear software suspend
+	   mode (clear bit 0). */
 	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
 
 	/* (3) Exit the configuration state (MB PnP mode). */

Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c	2006-08-29 00:45:42 UTC (rev 2393)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/superio.c	2006-08-29 17:41:14 UTC (rev 2394)
@@ -33,8 +33,7 @@
 	conf = dev->chip_info;
 
 	switch (dev->path.u.pnp.device) {
-	case IT8671F_FDC:
-		/* TODO. */
+	case IT8671F_FDC: /* TODO. */
 		break;
 	case IT8671F_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
@@ -44,11 +43,15 @@
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		init_uart8250(res0->base, &conf->com2);
 		break;
+	case IT8671F_PP: /* TODO. */
+		break;
 	case IT8671F_KBCK:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		res1 = find_resource(dev, PNP_IDX_IO1);
 		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
 		break;
+	case IT8671F_KBCM: /* TODO. */
+		break;
 	}
 }
 
@@ -60,12 +63,10 @@
 	.init             = init,
 };
 
-/* TODO: Find and check datasheet. */
+/* TODO: FDC, PP, KBCM. */
 static struct pnp_info pnp_dev_info[] = {
- { &ops, IT8671F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
- /* { &ops, IT8671F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, */
+ { &ops, IT8671F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
  { &ops, IT8671F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
- { &ops, IT8671F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
  { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
 };
 

Added: trunk/LinuxBIOSv2/src/superio/ite/it8718f/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8718f/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8718f/Config.lb	2006-08-29 17:41:14 UTC (rev 2394)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o

Added: trunk/LinuxBIOSv2/src/superio/ite/it8718f/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8718f/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8718f/chip.h	2006-08-29 17:41:14 UTC (rev 2394)
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SUPERIO_ITE_IT8718F
+#define _SUPERIO_ITE_IT8718F
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ITE_it8718f_ops;
+
+struct superio_ITE_it8718f_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif /* _SUPERIO_ITE_IT8718F */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f.h	2006-08-29 17:41:14 UTC (rev 2394)
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
+/* Status: untested on real hardware, but it compiles. */
+
+#define IT8718F_FDC  0x00 /* Floppy */
+#define IT8718F_SP1  0x01 /* Com1 */
+#define IT8718F_SP2  0x02 /* Com2 */
+#define IT8718F_PP   0x03 /* Parallel port */
+#define IT8718F_EC   0x04 /* Environment controller */
+#define IT8718F_KBCK 0x05 /* Keyboard */
+#define IT8718F_KBCM 0x06 /* Mouse */
+#define IT8718F_IR   0x0a /* Consumer IR */
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c	2006-08-29 17:41:14 UTC (rev 2394)
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "it8718f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE                     0x2e
+#define SIO_INDEX                    SIO_BASE
+#define SIO_DATA                     SIO_BASE+1
+
+/* Global Configuration Registers. */
+#define IT8718F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8718F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8718F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8718F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+
+#define IT8718F_CONFIGURATION_PORT   0x2e /* Write-only. */
+
+/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the
+ * LDN the register belongs to, before you can access the register. */
+static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+	outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+/* Enable the peripheral devices on the IT8718F Super IO chip. */
+static void it8718f_enable_serial(device_t dev, unsigned iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+
+	/* Perform MB PnP setup to put the SIO chip at 0x2e. */
+	/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+	/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+	outb(0x87, IT8718F_CONFIGURATION_PORT);
+	outb(0x01, IT8718F_CONFIGURATION_PORT);
+	outb(0x55, IT8718F_CONFIGURATION_PORT);
+	outb(0x55, IT8718F_CONFIGURATION_PORT);
+
+	/* (2) Modify the data of configuration registers. */
+
+	/* Select the chip to configure (if there's more than one).
+         * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+         * If this register is not written, both chips are configured. */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+	/* Enable all devices. */
+	it8718f_sio_write(IT8718F_FDC,  0x30, 0x1); /* Floppy */
+	it8718f_sio_write(IT8718F_SP1,  0x30, 0x1); /* Serial port 1 */
+	it8718f_sio_write(IT8718F_SP2,  0x30, 0x1); /* Serial port 2 */
+	it8718f_sio_write(IT8718F_PP,   0x30, 0x1); /* Parallel port */
+	it8718f_sio_write(IT8718F_EC,   0x30, 0x1); /* Environment controller */
+	it8718f_sio_write(IT8718F_KBCK, 0x30, 0x1); /* Keyboard */
+	it8718f_sio_write(IT8718F_KBCM, 0x30, 0x1); /* Mouse */
+	it8718f_sio_write(IT8718F_IR,   0x30, 0x1); /* Consumer IR */
+
+	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x00); */
+
+	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); 
+}
+

Added: trunk/LinuxBIOSv2/src/superio/ite/it8718f/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/ite/it8718f/superio.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/ite/it8718f/superio.c	2006-08-29 17:41:14 UTC (rev 2394)
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "it8718f.h"
+
+static void init(device_t dev)
+{
+	struct superio_ITE_it8718f_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+	case IT8718F_FDC: /* TODO. */
+		break;
+	case IT8718F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8718F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8718F_PP: /* TODO. */
+		break;
+	case IT8718F_EC: /* TODO. */
+		break;
+	case IT8718F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	case IT8718F_KBCM: /* TODO. */
+		break;
+	case IT8718F_IR: /* TODO. */
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+/* TODO: FDC, PP, EC, KBCM, IR. */
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, IT8718F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, IT8718F_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_ITE_it8718f_ops = {
+	CHIP_NAME("ITE it8718f")
+	.enable_dev = enable_dev,
+};
+




From bari at onelabs.com  Tue Aug 29 19:46:51 2006
From: bari at onelabs.com (Bari Ari)
Date: Tue, 29 Aug 2006 12:46:51 -0500
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060829162747.GA25404@aragorn>
References: <20060829162747.GA25404@aragorn>
Message-ID: <44F47D8B.7060707@onelabs.com>

Uwe Hermann wrote:
> Hi, here's some code for the IT8718F. Untested, but compiles.
>
>   
Are you working on the support for these devices by just using the data 
sheets and without hardware to test this? It's great if you are. It's a 
good starting point for someone else with hardware.

Bari



From g.watson at computer.org  Tue Aug 29 20:45:00 2006
From: g.watson at computer.org (Greg Watson)
Date: Tue, 29 Aug 2006 12:45:00 -0600
Subject: [LinuxBIOS] License clarification, round 1
In-Reply-To: <20060829163331.GA23377@coresystems.de>
References: <20060829101600.GE6649@aragorn>
	<20060829163331.GA23377@coresystems.de>
Message-ID: <F80DB154-3D7B-493F-A857-BE921FD42160@computer.org>

Any files in the PPC tree I either wrote myself (hence are released  
under the GPL) or I obtained from the u-boot project (http://u- 
boot.sourceforge.net/) which is also GPL'd. The weird licenses were  
already in the files. If someone wants to go and tidy them all up  
then feel free.

Greg

On Aug 29, 2006, at 10:33 AM, Stefan Reinauer wrote:

> Hi Uwe,
>
> thank you very much for your acribic arduousness.
>
> I hope I can lower your apprehensions in this case a bit:
>
> * Uwe Hermann <uwe at hermann-uwe.de> [060829 12:16]:
>> I've started looking at _all_ files in svn and checking their  
>> respective
>> license to see if it's GPL'd or at least has another Free Software  
>> license.
>> Also, all such licenses must be GPL compatible, too, AFAIK (but  
>> I'm no
>> lawyer).
>
> The answer here is easy. Every line of LinuxBIOS code is GPL. And
> every line of code we will include in the future will become GPL by  
> the
> implicit agreement of the contributor to use LinuxBIOS and to enhance
> it.
>
>> and b) for the legal status of the LinuxBIOS project itself, as
>> any non-free-software/non-gpl-compatible code in the repository would
>> probably be illegal to distribute (depending on the exact license
>> terms), may cause all kinds of other legal hassle and just simply
>> compromise the whole idea of the project - to have a _free_  
>> implementation.
>
> This is why we have been doing code reviews and have been in close
> contact with the contributors to make sure we do not include otherwise
> licensed or protected code.
>
>> So here I am, reading through all files, taking notes which of them
>> are not GPL'd. Please check the list and clarify the exact license
>> status of the files, e.g. by adding a GPL header similar to this  
>> one below:
>
> All of them are GPLed, as a consequence of the inclusion in LinuxBIOS.
> Also, files do not need a header stating their license, as the license
> is absolutely obvious to everyone downloading the code. We might  
> want to
> have them in most files anyways.
>
>> I'm happy to provide patches which add the above license header to  
>> all files,
>> but someone has to tell me who wrote the code, when, and which  
>> license applies
>> (if that's not obvious from the code).
>>
>> I noticed that many files do not have any license header at all  
>> (some don't
>> even say who the author is); such files have an unclear status and  
>> must be
>> considered non-free usually, so in cases where that's just an  
>> oversight,
>> please add a respective license note.
>
> No they must not. Who would say they must? Legally absolutely obvious
> that the files have been checked by those with checkin capabilities to
> be free.
>
> An example: Not every song on a CD needs a copyright note spoken  
> before
> the song starts. it is completely sufficient to print the copyright  
> once
> on the CD.
>
>> If the file was taken from another
>> project, please add a note saying so, and mention the license of  
>> that project
>> in the file.
>
> As we are using GPL as the license, only files with GPL license or  
> with
> licenses compatible to the GPL license have been included. All  
> files in
> the repository are licensed under the GPL. No exceptions.
>
>> Assumption: All *.lb config files are GPL'd even though they don't  
>> have
>> the lengthy GPL header in them. Correct? I don't think it's  
>> necessary for
>> those files. The same is probably true for ChangeLog, NEWS, and
>> documentation/ChangeLog.cvsimport, etc.
>
> Yes it is not necessary, and we need to be careful not to bloat the
> readability with comments like this. If we want to comment the
>
>>
>> The biggest problems I notices so far is the code from IBM and  
>> AMD, which says
>> things like "Copyright 2005 ADVANCED MICRO DEVICES, INC. All  
>> Rights Reserved"
>
> There is no problem with this. The fact that AMD released these  
> files to
> the public as GPL does not touch the fact that they own a copyright to
> it. In fact, in Europe signing over copyrights is impossible as of
> current law, so these notes are just fine. They read "This part has  
> been
> sponsored by AMD and they are allowed to make copies of it"
>
>> or stuff like:
>
>>   LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
>
>> That alone (which no additional "this is GPL'd" text would make the
>> code non-free and GPL-incompatible, I guess. I hope this can be
>> resolved or clarified somehow.
>
> I would not see a legal regulation to back your assumption. The fact
> that it is "licensed" does not make it non-free. the license is GPL,
> because IBM acknowledged making it GPL by contributing to a GPL  
> project.
>
> And that its their property is not an issue. All programs a person
> writes is that person's property unless the person does the  
> development
> work on a contractual basis in wich case the contractor owns the
> property. This is an exciting area of law, but it has absolutely  
> nothing
> to do with wether LinuxBIOS is GPLed or not.
>
>>   * I assume this is GPL'd as LinuxBIOS-AMD64.tex is GPL'd. Correct?
>> src/arch/i386/boot/acpi.c:
>>     "Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights  
>> Reserved."
>>     which is bad as it means it's NOT GPL'd and you cannot use it  
>> for anything
>
> where does it say that it is not GPL? Could not find the paragraph you
> are talking about. Search the mailinglist archives for details on  
> above
> code.
>
>>     really. No explicit permissions means you have no rights  
>> according to
>>     international copyright laws, AFAIK (but I'm no lawyer).
>
> The "opus" (Werk) as such is explicitly GPL licensed, so the GPL  
> applies
> for every single line of code. I am not a lawyer either but I asked  
> mine.
>
> The single parts of the opus are of no more concern. Be it a file, a
> subdirectory or a single line of the opus. They are all subordinated.
>
>
>
> So unless we have an indication stating something different I suggest
> what we do is emphasize that the whole of LinuxBIOS is GPL licensed by
> the respective copyright holders.
>
> To make things clearer, I also suggest removing license descriptions
> from every single source file in the tree and only have a single  
> license
> file stating the only valid project license. this way there will  
> not be
> confusion and we dont bloat the code with comments that dont comment
> the code.
>
>
> In case of such an indication we will immediately remove the code from
> the repository.
>
> Comments?
>
>
> Stefan
>
> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios




From fourstar10_2000 at yahoo.com  Tue Aug 29 21:46:05 2006
From: fourstar10_2000 at yahoo.com (steve yannalfo)
Date: Tue, 29 Aug 2006 12:46:05 -0700 (PDT)
Subject: [LinuxBIOS] VGA Fonts
Message-ID: <20060829194605.229.qmail@web38907.mail.mud.yahoo.com>

Hello Everyone,

    I have had very good success with LB but I am having trouble with the VGA fonts during boot but, the screen becomes readable when the kernel loads "setfont" in the init-scripts. (that uses ioctls etc.) Also, xdm loads fine. (Also, the display is cleaner sooner if I use FB in the kernel, but I loose output again during init-scripts, and then OK for login prompt.)

I have an on-board ATI M9, and have included the vgabios part in th LB image.

I have tried many sequences of writing to the VGA regs in vga_console.c->vga_hardware_fixup() including loading fonts & colormaps but, nothing I do there seems to affect the display output.
I know I am in that function ok... just,  nothing to seems to work.

    // sequencer
    outw(0x0612,0x3C4 );                         /* unlock ext regs    */
    mdelay(5);
    outw(0x0700,0x3C4);                        /* reset ext sequence mode  */
    mdelay(5);
    outw(0x0120,0x3C4);                        /* disable video */
    mdelay(5);
    
    setTextRegs(VgaTextRegs);                /* initial register setup */
    mdelay(5);
    setTextCLUT();                                /* load color lookup table */
    mdelay(5);
    loadFont();                                        /* load font */
    mdelay(5);
    setTextRegs(VgaTextRegs);                /* reload registers */
    mdelay(5);
    
    outw(0x0100,0x3C4);                        /* re-enable video  */
    mdelay(5);
    outb(0x63,0x3c2);                            /* MISC */
    mdelay(50);

It is like the vga part of the bios has intentionally left out the fonts, and any writes to 0xa0000000 or the vga regs have no effect.

The vga bios is copied correctly:
rom address for PCI: 03:01.0 = fff80000
copying VGA ROM Image from 0xfff80000 to 0xc0000, 0xf000 bytes
entering emulator
halt_sys: file /work/bios/linuxbios/src/devices/emulator/x86emu/ops.c, line 4485
OK


thanks
steve

I know I am asking a lot...:-)



 __________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060829/8031213a/attachment.html>

From yinghai.lu at amd.com  Tue Aug 29 22:43:17 2006
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Tue, 29 Aug 2006 13:43:17 -0700
Subject: [LinuxBIOS] Nvidia MCP55 support
Message-ID: <6F7DA19D05F3CF40B890C7CA2DB13A42070041B1@ssvlexmb2.amd.com>

I'm working on MCP55 support. There is some blank in
mcp55_early_setup.c, So Current Only IDE and USB are working but the
sata/nic/pcie don't work.

 

There is another option is use Nvidia binary code (NVMM) directly.

 

So questions is

nvidia would allow AMD to release NVMM binary to LinuxBIOS. .., Is it ok
to LinuxBIOS? Does is voliatiote the GPL?. Because this code will be
called by LinuxBIOS. And it is not loaded and started by LinuxBIOS. (cpu
microcode patch code and scsi firmare is loaded and started by LinuxBIOS
but setting some register).

 

Is VSM loaded and started only for OLPC?

 

Thanks

 

Yinghai Lu

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060829/aa277b37/attachment.html>

From c-d.hailfinger.devel.2006 at gmx.net  Tue Aug 29 23:06:49 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 29 Aug 2006 23:06:49 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <44F47D8B.7060707@onelabs.com>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
Message-ID: <44F4AC69.20006@gmx.net>

Bari Ari wrote:
> Uwe Hermann wrote:
>> Hi, here's some code for the IT8718F. Untested, but compiles.
>>
>>   
> Are you working on the support for these devices by just using the data 
> sheets and without hardware to test this? It's great if you are. It's a 
> good starting point for someone else with hardware.

Yes, he is. This has the potential to get quite a lot of people started
and getting any output at all is a major motivation factor even if the
rest of the code for bringup has yet to be written.

Can we build a ROM which does nothing but execute early serial code
for a given SuperIO, prints a few messages and then halts? So that if
somebody knows the SuperIO on his mainboard he can build a ROM testing
the code we have for it? Or does the early serial code also depend on
northbridge/southbridge/CPU?

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From yinghai.lu at amd.com  Tue Aug 29 23:20:25 2006
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Tue, 29 Aug 2006 14:20:25 -0700
Subject: [LinuxBIOS] IT8718F support.
Message-ID: <6F7DA19D05F3CF40B890C7CA2DB13A42070041B4@ssvlexmb2.amd.com>

Some SB need special setting about LPC decoding on PCI conf space.

YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Carl-Daniel
Hailfinger
Sent: Tuesday, August 29, 2006 2:07 PM
To: bari at onelabs.com
Cc: Uwe Hermann; linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] IT8718F support.

Bari Ari wrote:
> Uwe Hermann wrote:
>> Hi, here's some code for the IT8718F. Untested, but compiles.
>>
>>   
> Are you working on the support for these devices by just using the
data 
> sheets and without hardware to test this? It's great if you are. It's
a 
> good starting point for someone else with hardware.

Yes, he is. This has the potential to get quite a lot of people started
and getting any output at all is a major motivation factor even if the
rest of the code for bringup has yet to be written.

Can we build a ROM which does nothing but execute early serial code
for a given SuperIO, prints a few messages and then halts? So that if
somebody knows the SuperIO on his mainboard he can build a ROM testing
the code we have for it? Or does the early serial code also depend on
northbridge/southbridge/CPU?

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/

-- 
linuxbios mailing list
linuxbios at linuxbios.org
http://www.openbios.org/mailman/listinfo/linuxbios







From stepan at coresystems.de  Tue Aug 29 23:31:23 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 29 Aug 2006 23:31:23 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <44F4AC69.20006@gmx.net>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net>
Message-ID: <20060829213123.GB21904@coresystems.de>

* Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060829 23:06]:
> Yes, he is. This has the potential to get quite a lot of people started
> and getting any output at all is a major motivation factor even if the
> rest of the code for bringup has yet to be written.
 
Definitely. Uwe, can you (or someone else) have a look what SuperIOs
boards usually use, so we can try to support an as large as possible 
set of boards theoretically. (thinking mainstream)

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug 30 00:13:55 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 30 Aug 2006 00:13:55 +0200
Subject: [LinuxBIOS] Nvidia MCP55 support
In-Reply-To: <6F7DA19D05F3CF40B890C7CA2DB13A42070041B1@ssvlexmb2.amd.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A42070041B1@ssvlexmb2.amd.com>
Message-ID: <44F4BC23.8070502@gmx.net>

Lu, Yinghai wrote:
> I'm working on MCP55 support. There is some blank in
> mcp55_early_setup.c, So Current Only IDE and USB are working but the
> sata/nic/pcie don't work.
> 
> There is another option is use Nvidia binary code (NVMM) directly.

Using NVMM may be easier, but what happens if we want to change
parts of it? This is probably not allowed and could be a serious
problem.

How much work is it to complete mcp55_early_setup.c without NVMM?

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug 30 00:11:14 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 30 Aug 2006 00:11:14 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060829213123.GB21904@coresystems.de>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
Message-ID: <44F4BB82.2030109@gmx.net>

Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060829 23:06]:
>> Yes, he is. This has the potential to get quite a lot of people started
>> and getting any output at all is a major motivation factor even if the
>> rest of the code for bringup has yet to be written.
>  
> Definitely. Uwe, can you (or someone else) have a look what SuperIOs
> boards usually use, so we can try to support an as large as possible 
> set of boards theoretically. (thinking mainstream)

The FSF has a campaign (http://www.fsf.org/campaigns/free-bios.html)
we could use for sampling which SuperIOs are used in commonly sold
boards. Their "how can you help" section could state prominently that
we need a list of boards with matching SuperIOs.

Suggested text follows:
"The LinuxBIOS project needs your help to make LinuxBIOS work on
your mainboard. A first important step is to know which SuperIO your
mainboard uses. This information can be obtained easily following
the directions on <some LinuxBIOS wiki page>. Once that is known,
you can download a matching experimental BIOS image and test the
code."

The LinuxBIOS wiki page could read as follows:
"How to find the SuperIO on your mainboard? There are two ways to
do it:
1. Find the chip on the board (usually a bigger chip with ITE, NSC,
   SMSC, VIA or Winbond written on it). See <photo> and <photo>
   for reference.
2. Find the chip with sensors-detect and look for something named
   SuperIO. See <sample output> for reference. Equipped with that
   information, you may also want to find out if that chip is really
   soldered on your board.
Please add this your findings to the wiki so others can verify
and profit from it.

<example board> <example superio> <link to bios image>
<example board> <example superio> <link to bios image>"


What do you think?

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug 30 00:51:49 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 30 Aug 2006 00:51:49 +0200
Subject: [LinuxBIOS] Nvidia MCP55 support
In-Reply-To: <6F7DA19D05F3CF40B890C7CA2DB13A42070041B1@ssvlexmb2.amd.com>
References: <6F7DA19D05F3CF40B890C7CA2DB13A42070041B1@ssvlexmb2.amd.com>
Message-ID: <44F4C505.5070203@gmx.net>

Lu, Yinghai wrote:
> nvidia would allow AMD to release NVMM binary to LinuxBIOS. .., Is it ok
> to LinuxBIOS? Does is voliatiote the GPL?. Because this code will be
> called by LinuxBIOS. And it is not loaded and started by LinuxBIOS. (cpu
> microcode patch code and scsi firmare is loaded and started by LinuxBIOS
> but setting some register).
> 
> Is VSM loaded and started only for OLPC?

I think the VSA is different from NVMM because we have the source for
the VSA (http://www.mail-archive.com/devel at laptop.org/msg00184.html).
At least that is what I believe. Ron probably knows more.

Regards,
Carl-Daniel




From uwe at hermann-uwe.de  Wed Aug 30 14:14:28 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 30 Aug 2006 14:14:28 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <44F47D8B.7060707@onelabs.com>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
Message-ID: <20060830121428.GA28991@aragorn>

Hi,

On Tue, Aug 29, 2006 at 12:46:51PM -0500, Bari Ari wrote:
> Are you working on the support for these devices by just using the data 
> sheets and without hardware to test this?

Yes, exactly. I decided to just add support for _all_ ITE Super IOs for
which I'm able to find datasheets.


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060830/26b04376/attachment.sig>

From uwe at hermann-uwe.de  Wed Aug 30 14:24:14 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 30 Aug 2006 14:24:14 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060829213123.GB21904@coresystems.de>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
Message-ID: <20060830122414.GB28991@aragorn>

Hi,

On Tue, Aug 29, 2006 at 11:31:23PM +0200, Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060829 23:06]:
> > Yes, he is. This has the potential to get quite a lot of people started
> > and getting any output at all is a major motivation factor even if the
> > rest of the code for bringup has yet to be written.

That's a great idea! I figure it should be possible to create a
repository of some sort which contains such ROM images.
That eliminates the need to understand the build process and compile
stuff, which will lower the entry bar for a few people and might get
them interested in the project.

 
> Definitely. Uwe, can you (or someone else) have a look what SuperIOs
> boards usually use, so we can try to support an as large as possible 
> set of boards theoretically. (thinking mainstream)

Yes, that shouldn't be a problem for recent boards. We can just scan all
major online computer stores for board names and then get the datasheets
of the vendors; or simply visit the websites of the 10 biggest vendors
or so and simply get _all_ their datasheets. Then we can do some
statistics etc.

As for the Super IOs I'd use another approach; simply download all
datasheets you can get your hands on and add support for the respective
part (which is what I'm doing with the ITEs; when Im done I'll probably
continue with Winbond).


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060830/86098fe1/attachment.sig>

From uwe at hermann-uwe.de  Wed Aug 30 14:37:59 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 30 Aug 2006 14:37:59 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <44F4BB82.2030109@gmx.net>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<44F4BB82.2030109@gmx.net>
Message-ID: <20060830123758.GC28991@aragorn>

Hi,

On Wed, Aug 30, 2006 at 12:11:14AM +0200, Carl-Daniel Hailfinger wrote:
> The FSF has a campaign (http://www.fsf.org/campaigns/free-bios.html)
> we could use for sampling which SuperIOs are used in commonly sold
> boards. Their "how can you help" section could state prominently that
> we need a list of boards with matching SuperIOs.
> 
> Suggested text follows:
> "The LinuxBIOS project needs your help to make LinuxBIOS work on
> your mainboard. A first important step is to know which SuperIO your
> mainboard uses. This information can be obtained easily following
> the directions on <some LinuxBIOS wiki page>. Once that is known,
> you can download a matching experimental BIOS image and test the
> code."
> 
> The LinuxBIOS wiki page could read as follows:
> "How to find the SuperIO on your mainboard? There are two ways to
> do it:
> 1. Find the chip on the board (usually a bigger chip with ITE, NSC,
>    SMSC, VIA or Winbond written on it). See <photo> and <photo>
>    for reference.
> 2. Find the chip with sensors-detect and look for something named
>    SuperIO. See <sample output> for reference. Equipped with that
>    information, you may also want to find out if that chip is really
>    soldered on your board.
> Please add this your findings to the wiki so others can verify
> and profit from it.
> 
> <example board> <example superio> <link to bios image>
> <example board> <example superio> <link to bios image>"
> 
> 
> What do you think?

Asking for help in the FSF campaign is definately a good idea, as it
reaches quite a lot of people, I guess.

I'm not sure whether a list of Super IOs is all that useful, though. We can
simply support all of them (a coordinated effort shouldn't take more
than a few weeks to support almost all Super IOs you can get a datasheet
for).

I'm sure there are other areas where the project needs lots more help;
Someone who is more involved with the project than I am should
probably create a list of such areas.

IMHO these things are quite important:

 1) publicity among non-coders to make the project well-known, and to
    make the fact known that there's a viable, working Free Software
    alternative to proprietary BIOSes.

 2) Get as many coders as possible involved. Create incentive to try
    LinuxBIOS, which will result in active contributions in many
    cases. It's crucial to have support for a wide range of hardware,
    as only that will really ensure a wide-spread use of LinuxBIOS
    (I'm especially thinking about desktop machines here).

 3) Create pressure on those companies which do not give out datasheets
    for various hardware parts. This is much easier if 1) is successful
    and many people/customers demand LinuxBIOS support.


HTH, Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060830/a1975b4e/attachment.sig>

From uwe at hermann-uwe.de  Wed Aug 30 14:41:04 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 30 Aug 2006 14:41:04 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <8a0c36780608290957h391fc469ydf3beff7da824128@mail.gmail.com>
References: <20060829162747.GA25404@aragorn>
	<8a0c36780608290957h391fc469ydf3beff7da824128@mail.gmail.com>
Message-ID: <20060830124104.GD28991@aragorn>

Hi,

On Tue, Aug 29, 2006 at 11:57:48AM -0500, Richard Smith wrote:
> First it depends on the config file.  If the device is not enabled in
> the config file then don't turn it on.  Com 1 being the exception..

Hm, I currently just turn on every supported Super IO device (FDC, Com1,
Com2, PP, etc. etc.) in the ITE code.
Should I check for some variables/#defines in the code and only
conditionally enable them? If so, how do I do that?
Or shall I simply continue to enable everything as you state below?


> Generally though for superIO stuff if the kernel can find it then it
> can init it so just turning on the device so the base address shows up
> should be enough.


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060830/62dfa399/attachment.sig>

From stepan at coresystems.de  Wed Aug 30 17:10:15 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 30 Aug 2006 17:10:15 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830123758.GC28991@aragorn>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<44F4BB82.2030109@gmx.net> <20060830123758.GC28991@aragorn>
Message-ID: <20060830151015.GA28321@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060830 14:37]:
> I'm not sure whether a list of Super IOs is all that useful, though. We can
> simply support all of them (a coordinated effort shouldn't take more
> than a few weeks to support almost all Super IOs you can get a datasheet
> for).

Supporting all of them for the sake of it makes no sense, by your leave.
SuperIO chips alone dont do the deed.  if we manage to get a
"coordinated effort", i'd much rather go and support "80% of the common
superio chips out there" with in the end 50% of the effort and instead
try to get some more southbridge/northbridge combinations supported with
this effort. On K8 we lack Via and ATI chipset support, for Via we lack
C7 support,... all that stuff will give us a user base. 100% superio
chips alone wont, given that in 2 months we're at 98% of the existing
superios again, and in 2 ys below 50%.

>  1) publicity among non-coders to make the project well-known, and to
>     make the fact known that there's a viable, working Free Software
>     alternative to proprietary BIOSes.
 
I completely agree. The key to success here is, in my opinion, to
provide ready-built and tested images on an automated base for certain
hardware. Also, we need to work on the configuration part to move more
mainboard specifics (irq routing, complete hw tree) in the config file.
A mainboard from all supported components should not need any code to be
touched. only configuration files. Well, maybe we go with an exception
of a little GPIO triggering here and there i f this can not be
automated, but other than that: no new code for _motherboards_ 

>  2) Get as many coders as possible involved. Create incentive to try
>     LinuxBIOS, which will result in active contributions in many
>     cases. It's crucial to have support for a wide range of hardware,
>     as only that will really ensure a wide-spread use of LinuxBIOS
>     (I'm especially thinking about desktop machines here).

Unlike normal userspace programs or even kernels, recovering from a bad
bios can be quite some work. How do we overcome this? Not everyone is
going to buy a galep iv for 400$, nor a bios savior for 30.

>  3) Create pressure on those companies which do not give out datasheets
>     for various hardware parts. This is much easier if 1) is successful
>     and many people/customers demand LinuxBIOS support.
 
what do you mean by pressure?
 
  Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Wed Aug 30 17:14:37 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 30 Aug 2006 17:14:37 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830122414.GB28991@aragorn>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<20060830122414.GB28991@aragorn>
Message-ID: <20060830151437.GB28321@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060830 14:24]:
> Hi,
> 
> On Tue, Aug 29, 2006 at 11:31:23PM +0200, Stefan Reinauer wrote:
> > * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060829 23:06]:
> > > Yes, he is. This has the potential to get quite a lot of people started
> > > and getting any output at all is a major motivation factor even if the
> > > rest of the code for bringup has yet to be written.
> 
> That's a great idea! I figure it should be possible to create a
> repository of some sort which contains such ROM images.
> That eliminates the need to understand the build process and compile
> stuff, which will lower the entry bar for a few people and might get
> them interested in the project.

ok, lets think this further: You get a LinuxBIOS-string on serial and
then you do _what_ with that image? Have a shell? Torsten Duwe's serial
loader or llshell might be candidates here.

> As for the Super IOs I'd use another approach; simply download all
> datasheets you can get your hands on and add support for the respective
> part (which is what I'm doing with the ITEs; when Im done I'll probably
> continue with Winbond).

After my last mail, thinking about it,... how many vendors are we
talking about here,..? and how many chips per vendor? 
It might indeed be a pretty good idea to exhaust the space just to get
some ground. SuperIOs age less than southbridges, do they?

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Wed Aug 30 17:18:06 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 30 Aug 2006 17:18:06 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830124104.GD28991@aragorn>
References: <20060829162747.GA25404@aragorn>
	<8a0c36780608290957h391fc469ydf3beff7da824128@mail.gmail.com>
	<20060830124104.GD28991@aragorn>
Message-ID: <20060830151806.GC28321@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [060830 14:41]:
> Hm, I currently just turn on every supported Super IO device (FDC, Com1,
> Com2, PP, etc. etc.) in the ITE code.
> Should I check for some variables/#defines in the code and only
> conditionally enable them? 

Yes, please have a look at the other superio implementations. You want
to be able to switch off certain devices in the config file. Because
they're not wired on the board or because you want to disable them, etc.

> Or shall I simply continue to enable everything as you state below?
 
no, please make sure the drivers have their hooks so they can be
controlled via the mainboard config files. 

We need to get all components to have all their choices available in the
config files, or we will have to patch and patch and patch code for
every board we want to support. That is something I want to get away
from --> more modular concept.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug 30 17:28:40 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 30 Aug 2006 17:28:40 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830151015.GA28321@coresystems.de>
References: <20060829162747.GA25404@aragorn>
	<44F47D8B.7060707@onelabs.com>	<44F4AC69.20006@gmx.net>
	<20060829213123.GB21904@coresystems.de>	<44F4BB82.2030109@gmx.net>
	<20060830123758.GC28991@aragorn>
	<20060830151015.GA28321@coresystems.de>
Message-ID: <44F5AEA8.1020204@gmx.net>

Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [060830 14:37]:
>>  2) Get as many coders as possible involved. Create incentive to try
>>     LinuxBIOS, which will result in active contributions in many
>>     cases. It's crucial to have support for a wide range of hardware,
>>     as only that will really ensure a wide-spread use of LinuxBIOS
>>     (I'm especially thinking about desktop machines here).
> 
> Unlike normal userspace programs or even kernels, recovering from a bad
> bios can be quite some work. How do we overcome this? Not everyone is
> going to buy a galep iv for 400$, nor a bios savior for 30.

In Germany you can get cheap flash chips at http://www.bios-chip.de/ .
SST 49LF008A (8 Mbit FWH) only costs 8.50 Eur, which is really affordable.
With such a chip, there is no need for a BIOS saviour. And 8 Mbit is
enough even if you want to fit a complete kernel in ROM.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug 30 18:17:35 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 30 Aug 2006 18:17:35 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830151437.GB28321@coresystems.de>
References: <20060829162747.GA25404@aragorn>
	<44F47D8B.7060707@onelabs.com>	<44F4AC69.20006@gmx.net>
	<20060829213123.GB21904@coresystems.de>	<20060830122414.GB28991@aragorn>
	<20060830151437.GB28321@coresystems.de>
Message-ID: <44F5BA1F.2060204@gmx.net>

Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [060830 14:24]:
>> Hi,
>>
>> On Tue, Aug 29, 2006 at 11:31:23PM +0200, Stefan Reinauer wrote:
>>> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060829 23:06]:
>>>> Yes, he is. This has the potential to get quite a lot of people started
>>>> and getting any output at all is a major motivation factor even if the
>>>> rest of the code for bringup has yet to be written.
>> That's a great idea! I figure it should be possible to create a
>> repository of some sort which contains such ROM images.
>> That eliminates the need to understand the build process and compile
>> stuff, which will lower the entry bar for a few people and might get
>> them interested in the project.
> 
> ok, lets think this further: You get a LinuxBIOS-string on serial and
> then you do _what_ with that image? Have a shell? Torsten Duwe's serial
> loader or llshell might be candidates here.

Both won't help if RAM and CAR don't work yet.
But the string alone should give us an idea the specific mainboard needs
additional setup before it can speak to the SuperIO or not.


>> As for the Super IOs I'd use another approach; simply download all
>> datasheets you can get your hands on and add support for the respective
>> part (which is what I'm doing with the ITEs; when Im done I'll probably
>> continue with Winbond).
> 
> After my last mail, thinking about it,... how many vendors are we
> talking about here,..? and how many chips per vendor? 
> It might indeed be a pretty good idea to exhaust the space just to get
> some ground. SuperIOs age less than southbridges, do they?

We face various constraints here:
* People are less likely to perform experiments with their newest machines
* Supporting Intel will be a headache
* flashrom should work on the systems we are targeting to eliminate the
  need for an EEPROM programmer
* Some boards are shipped without serial port
* we don't care which boards are/were best-sellers, we only care which
  boards we can find enough testers for

Considering these constraints, I suggest the following plan:
* Call for action via FSF, point to <website with further instructions>
* provide linuxbios-check .rpm/.deb/.tar.gz/ebuild with the following
  (half-)automated tests:
  - flashrom to find out on which boards we can flash the BIOS easily
  - sensors-detect for SuperIO detection
  - lspci -vvv
  - dmidecode
  - dmesg (or /var/log/boot.msg)
  - ask user whether he has a serial port onboard
  - ask user which parts of lspci are add-on cards
  - ask user for exact mainboard name
  - ask user for model of flash chip
  - ask user for SuperIO
  - upload results to <special address which feeds database>
  - if SuperIO or mainboard is known, offer ROM image for download
* once we have a reasonable overview of people willing to test and
  their respective boards, we can decide which boards to attack first
* after we have support for the first mass-marketed board, make sure
  to spread the word (and make people with unsupported boards envious)

Once I find some time, I'll implement the plan.

What do you think?

Regards,
Carl-Daniel



From uwe at hermann-uwe.de  Wed Aug 30 18:36:48 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 30 Aug 2006 18:36:48 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <44F5AEA8.1020204@gmx.net>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<44F4BB82.2030109@gmx.net> <20060830123758.GC28991@aragorn>
	<20060830151015.GA28321@coresystems.de> <44F5AEA8.1020204@gmx.net>
Message-ID: <20060830163648.GA14313@aragorn>

On Wed, Aug 30, 2006 at 05:28:40PM +0200, Carl-Daniel Hailfinger wrote:
> In Germany you can get cheap flash chips at http://www.bios-chip.de/ .

Yep. Or from Conrad (www.conrad.de) or other electronics vendors, I
guess. I also ripped some off of old and broken motherboards (e.g. from
flea markets etc.).


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060830/095c7102/attachment.sig>

From stepan at coresystems.de  Wed Aug 30 19:54:55 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 30 Aug 2006 19:54:55 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <44F5AEA8.1020204@gmx.net>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<44F4BB82.2030109@gmx.net> <20060830123758.GC28991@aragorn>
	<20060830151015.GA28321@coresystems.de> <44F5AEA8.1020204@gmx.net>
Message-ID: <20060830175454.GA16201@coresystems.de>

* Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060830 17:28]:
> In Germany you can get cheap flash chips at http://www.bios-chip.de/ .
> SST 49LF008A (8 Mbit FWH) only costs 8.50 Eur, which is really affordable.
> With such a chip, there is no need for a BIOS saviour. And 8 Mbit is
> enough even if you want to fit a complete kernel in ROM.

I know, I did chip hotswapping for several years now. 

While I think it is a great opportunity to be a cheap date, you do risk
messing up the hardware physically if you swap very often. 

And this is exactly the thing that keeps people from "playing around"
with LinuxBIOS as they do with other software projects...

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Wed Aug 30 20:38:57 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 30 Aug 2006 20:38:57 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <44F5BA1F.2060204@gmx.net>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<20060830122414.GB28991@aragorn>
	<20060830151437.GB28321@coresystems.de> <44F5BA1F.2060204@gmx.net>
Message-ID: <20060830183857.GB16201@coresystems.de>

* Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060830 18:17]:
> > ok, lets think this further: You get a LinuxBIOS-string on serial and
> > then you do _what_ with that image? Have a shell? Torsten Duwe's serial
> > loader or llshell might be candidates here.
> 
> Both won't help if RAM and CAR don't work yet.
> But the string alone should give us an idea the specific mainboard needs
> additional setup before it can speak to the SuperIO or not.
 
llshell was known to work all within registers, so it needs no ram.
the serial boot was at least partly written using romcc iirc. 

> We face various constraints here:
> * People are less likely to perform experiments with their newest machines

While we only care for exactly those because of the costs and time 
involved in supporting a system

> * flashrom should work on the systems we are targeting to eliminate the
>   need for an EEPROM programmer

This works on quite some systems that do not require special GPIO
sequences.

> * Some boards are shipped without serial port

which reminds me.. we purchased a net20dc usb debug device, but I 
did not get to write example code for any side of the debug connection.
I hope to find an opportunity after my current project. Or maybe one
of the USB adept experts in here can jump in?

> * we don't care which boards are/were best-sellers, we only care which
>   boards we can find enough testers for

Not all the way down. The boards that are supported in LinuxBIOS usually
are supported because there was a use case for one of the contributors
to do so. See the OLPC, or the machines that were supported because LANL
built clusters with that hardware. 

> Considering these constraints, I suggest the following plan:
> * Call for action via FSF, point to <website with further instructions>

BTW, will someone from the FSF join the LinuxBIOS symposium 2006? I am
still missing FSF names on the list!

> * provide linuxbios-check .rpm/.deb/.tar.gz/ebuild with the following
>   (half-)automated tests:
>   - flashrom to find out on which boards we can flash the BIOS easily
>   - sensors-detect for SuperIO detection
>   - lspci -vvv
>   - dmidecode
>   - dmesg (or /var/log/boot.msg)
>   - ask user whether he has a serial port onboard
>   - ask user which parts of lspci are add-on cards
>   - ask user for exact mainboard name
>   - ask user for model of flash chip
>   - ask user for SuperIO
>   - upload results to <special address which feeds database>
>   - if SuperIO or mainboard is known, offer ROM image for download

can you set something up for this? I can create a database on
linuxbios.org and also create a repository to check in the code and
optimize it.

The SuperIO can also be auto detected. I think I saw the code for this
somewhere. 

> * after we have support for the first mass-marketed board, make sure
>   to spread the word (and make people with unsupported boards envious)
 
there is plenty of support for "mass-marketed boards" already, or do I
get you wrong? Epia is among them. All the Tyan boards..

> Once I find some time, I'll implement the plan.

Let me know when you do so, we can probably coordinate.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From greg.lindahl at qlogic.com  Wed Aug 30 21:43:33 2006
From: greg.lindahl at qlogic.com (Greg Lindahl)
Date: Wed, 30 Aug 2006 12:43:33 -0700
Subject: [LinuxBIOS] License clarification, round 1
In-Reply-To: <20060829163331.GA23377@coresystems.de>
References: <20060829101600.GE6649@aragorn>
	<20060829163331.GA23377@coresystems.de>
Message-ID: <20060830194333.GC10753@greglaptop>

On Tue, Aug 29, 2006 at 06:33:31PM +0200, Stefan Reinauer wrote:

> The answer here is easy. Every line of LinuxBIOS code is GPL.

It seems that the standard for GPLed projects is to include the
boilerplate in all the source files. For example, the GPL v2 says:

|   To do so, attach the following notices to the program.  It is safest
| to attach them to the start of each source file to most effectively
| convey the exclusion of warranty; and each file should have at least
| the "copyright" line and a pointer to where the full notice is found.

Why should LinuxBIOS do different?

-- greg




From c-d.hailfinger.devel.2006 at gmx.net  Thu Aug 31 01:39:15 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 31 Aug 2006 01:39:15 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830183857.GB16201@coresystems.de>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<20060830122414.GB28991@aragorn>
	<20060830151437.GB28321@coresystems.de> <44F5BA1F.2060204@gmx.net>
	<20060830183857.GB16201@coresystems.de>
Message-ID: <44F621A3.7070008@gmx.net>

Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060830 18:17]:
> there is plenty of support for "mass-marketed boards" already, or do I
> get you wrong? Epia is among them. All the Tyan boards..

Ah sorry, wrong wording. "Sold in masses to Linux users" would have
described it better. That unfortunately excludes both Tyan and Via Epia.

>> Once I find some time, I'll implement the plan.
> 
> Let me know when you do so, we can probably coordinate.

Will do so.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Thu Aug 31 01:51:23 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 31 Aug 2006 01:51:23 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830183857.GB16201@coresystems.de>
References: <20060829162747.GA25404@aragorn>
	<44F47D8B.7060707@onelabs.com>	<44F4AC69.20006@gmx.net>
	<20060829213123.GB21904@coresystems.de>	<20060830122414.GB28991@aragorn>	<20060830151437.GB28321@coresystems.de>
	<44F5BA1F.2060204@gmx.net> <20060830183857.GB16201@coresystems.de>
Message-ID: <44F6247B.6080008@gmx.net>

Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [060830 18:17]:
> 
>> We face various constraints here:
>> * People are less likely to perform experiments with their newest machines
> 
> While we only care for exactly those because of the costs and time 
> involved in supporting a system

That's the question. Do we want to continue supporting highly expensive
boards like Tyan where hardly anyone will sacrifice a system to LinuxBIOS
testing or do we want to reach the masses. For the masses, anything less
than *perfect* support for the machine they use daily is unacceptable.
And we will probably not reach good support of a board until long after
the board is out of production, bringing us back to square one.
Just look at how many people use binary-only drivers to get a bit more
performance on their machines for daily use even if free drivers exist.

I'm for supporting slightly outdated systems (like AMD Socket 754/939)
and against putting any effort into the latest and greatest.

>> * flashrom should work on the systems we are targeting to eliminate the
>>   need for an EEPROM programmer
> 
>> * provide linuxbios-check .rpm/.deb/.tar.gz/ebuild with the following
>>   (half-)automated tests:
>>   - sensors-detect for SuperIO detection
> 
> The SuperIO can also be auto detected. I think I saw the code for this
> somewhere. 

You mean, a different method than probing SMBus?

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From stepan at coresystems.de  Thu Aug 31 15:41:34 2006
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 31 Aug 2006 15:41:34 +0200
Subject: [LinuxBIOS] Tyan s2895 clarification
In-Reply-To: <20060829150312.GE27931@capsaicin.mamane.lu>
References: <20060829150312.GE27931@capsaicin.mamane.lu>
Message-ID: <20060831134134.GB5186@coresystems.de>

* Lionel Elie Mamane <lionel at mamane.lu> [060829 17:03]:
> I'm confused. My Tyan s2895 has a 8Mbit LPC Flash ROM, so I thought I
> could not use a RD1 Bios Savior, as no 8Mbit model was available; this
> kept me from trying out LinuxBIOS by fear of turning my computer into
> an expensive paper weight. But now I see posts to this ML's archive
> (such as
> http://www.linuxbios.org/pipermail/linuxbios/2006-January/013420.html)
> that talk about using 4Mbit savior with the Tyan s2895.


While the original bios needs 1MB (8MBit), LinuxBIOS requires quite less
than that. So as long as you put LinuxBIOS in the bios savior chip and
leave the factory bios in its original chip, everything will work fine.
IOSS states that they can not be used because you can not stick another
8MBit BIOS on the savior itself.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From ward at gnu.org  Thu Aug 31 16:16:22 2006
From: ward at gnu.org (Ward Vandewege)
Date: Thu, 31 Aug 2006 10:16:22 -0400
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060830123758.GC28991@aragorn>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<44F4BB82.2030109@gmx.net> <20060830123758.GC28991@aragorn>
Message-ID: <20060831141622.GA6982@countzero.vandewege.net>

On Wed, Aug 30, 2006 at 02:37:59PM +0200, Uwe Hermann wrote:
> Asking for help in the FSF campaign is definately a good idea, as it
> reaches quite a lot of people, I guess.

We're happy to help. Updating the campaign page is no problem; just let us
know what you'd like to see there.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From c-d.hailfinger.devel.2006 at gmx.net  Thu Aug 31 16:33:11 2006
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 31 Aug 2006 16:33:11 +0200
Subject: [LinuxBIOS] IT8718F support.
In-Reply-To: <20060831141622.GA6982@countzero.vandewege.net>
References: <20060829162747.GA25404@aragorn>
	<44F47D8B.7060707@onelabs.com>	<44F4AC69.20006@gmx.net>
	<20060829213123.GB21904@coresystems.de>	<44F4BB82.2030109@gmx.net>
	<20060830123758.GC28991@aragorn>
	<20060831141622.GA6982@countzero.vandewege.net>
Message-ID: <44F6F327.6040201@gmx.net>

Ward Vandewege wrote:
> On Wed, Aug 30, 2006 at 02:37:59PM +0200, Uwe Hermann wrote:
>> Asking for help in the FSF campaign is definately a good idea, as it
>> reaches quite a lot of people, I guess.
> 
> We're happy to help. Updating the campaign page is no problem; just let us
> know what you'd like to see there.

I'm working on an updated text. Once it is finished (and has reached
consensus here), I'll tell you about it.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From ollie at lanl.gov  Thu Aug 31 17:56:55 2006
From: ollie at lanl.gov (ollie)
Date: Thu, 31 Aug 2006 09:56:55 -0600
Subject: [LinuxBIOS] VGA Fonts
In-Reply-To: <20060829194605.229.qmail@web38907.mail.mud.yahoo.com>
References: <20060829194605.229.qmail@web38907.mail.mud.yahoo.com>
Message-ID: <1157039815.1832.3.camel@logarithm.lanl.gov>

On Tue, 2006-08-29 at 12:46 -0700, steve yannalfo wrote:

>     // sequencer
>     outw(0x0612,0x3C4 );                         /* unlock ext regs
> */
>     mdelay(5);
>     outw(0x0700,0x3C4);                        /* reset ext sequence
> mode  */
>     mdelay(5);
>     outw(0x0120,0x3C4);                        /* disable video */
>     mdelay(5);
>     
>     setTextRegs(VgaTextRegs);                /* initial register setup
> */
>     mdelay(5);
>     setTextCLUT();                                /* load color lookup
> table */
>     mdelay(5);
>     loadFont();                                        /* load font */
>     mdelay(5);
>     setTextRegs(VgaTextRegs);                /* reload registers */
>     mdelay(5);
>     
>     outw(0x0100,0x3C4);                        /* re-enable video  */
>     mdelay(5);
>     outb(0x63,0x3c2);                            /* MISC */
>     mdelay(50);
> 

What is this piece of code? Where can I find it?

Ollie





From uwe at hermann-uwe.de  Thu Aug 31 23:55:32 2006
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 31 Aug 2006 23:55:32 +0200
Subject: [LinuxBIOS] flashrom, uniflash.
In-Reply-To: <20060830175454.GA16201@coresystems.de>
References: <20060829162747.GA25404@aragorn> <44F47D8B.7060707@onelabs.com>
	<44F4AC69.20006@gmx.net> <20060829213123.GB21904@coresystems.de>
	<44F4BB82.2030109@gmx.net> <20060830123758.GC28991@aragorn>
	<20060830151015.GA28321@coresystems.de> <44F5AEA8.1020204@gmx.net>
	<20060830175454.GA16201@coresystems.de>
Message-ID: <20060831215532.GA6142@aragorn>

Hi,

On Wed, Aug 30, 2006 at 07:54:55PM +0200, Stefan Reinauer wrote:
> While I think it is a great opportunity to be a cheap date, you do risk
> messing up the hardware physically if you swap very often. 
> 
> And this is exactly the thing that keeps people from "playing around"
> with LinuxBIOS as they do with other software projects...

Yes, sure it's a bit more risky to play with important hardware parts;
that's why I think we need to support lots of older boards, chips, etc.
which people are willing to play with and/or can easily and cheaply get
from flea markets, ebay etc.

Another important issue is that flashrom should support many, many chips
and baords, as few people will be willing to buy expensive hardware just
for flashing.

There's Uniflash, but that has the problem of being Pascal+DOS,
currently. I tried for a few minutes to build it with GNU Pascal or
FreePascal, but that didn't work easily (needs more work, maybe).
Has anybody else managed to build it for Linux?


Uwe.
-- 
Uwe Hermann 
http://www.hermann-uwe.de
http://www.it-services-uh.de  | http://www.crazy-hacks.org 
http://www.holsham-traders.de | http://www.unmaintained-free-software.org
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060831/29bf7f4f/attachment.sig>

From andrew.j.fish at intel.com  Mon Aug 28 20:13:11 2006
From: andrew.j.fish at intel.com (Fish, Andrew J)
Date: Mon, 28 Aug 2006 18:13:11 -0000
Subject: [LinuxBIOS] Microkernel  / Manufacturers
Message-ID: <08FC4EF6B9BF1A41BDF0B0547C074F5B6F8F70@fmsmsx413.amr.corp.intel.com>

Will,

The Edk2 project on www.TianoCore.org does not have silicon enabling
code but it does implement UEFI conformant interfaces. It currently
builds under Windows, Linux, and Mac OS X. So this code may be helpful
to you. It's all BSD license so you can use it how ever you like. 

If you have any EFI questions you can use the mailing lists on
www.TianoCore.org to get answers as a fair number of the people from
United EFI Forum board of directors companies (AMD, AMI, Dell, HP, IBM
Insyde, Intel, Microsoft, & Phoenix Technologies) and others hang out on
these mailing lists. Of course www.UEFI.org lets you get the official
UEFI info and latest versions of the specifications.  

I'm really excited about the future of EFI. The Intel based iMac in my
office is a cool machine and it's really great to see the innovation
Apple has done based on EFI. 

Andrew Fish
 
Simplicity is the ultimate sophistication.  - Leonardo da Vinci
 
"The content of this message is my personal opinion only and although I
am an employee of Intel, the statements I make here in no way represent
Intel's position on the issue, nor am I authorized to speak on behalf of
Intel on this matter."  Your lawyer may vary.


>-----Original Message-----
>From: William DUCK [mailto:guillaume.fortaine at wanadoo.fr]
>Sent: Saturday, August 26, 2006 10:55 AM
>To: users at edk2.tianocore.org; linuxbios at linuxbios.org; u-boot-
>users at lists.sourceforge.net; admin at uefi.org
>Subject: Microkernel / Manufacturers
>
>Hello,
>
>I am currently involved into the UEFI project.
>
>I would want to build an Open Source UEFI firmware in the style of
>U-Boot/LinuxBIOS but to boot a microkernel.
>
>Which manufacturer could I contact to build a firmware ? ( to have the
>specs/datasheets of the hardware)
>
>If you want to contact me, my mail is
>guillaume_dot_fortaine_at_wanadoo_dot_fr
>
>I will set up a mailing-list, a web server, a wiki and an IRC
>
>Thank you for your answer,
>
>Best Regards,
>
>                   WIll
>
>---------------------------------------------------------------------
>To unsubscribe, e-mail: users-unsubscribe at edk2.tianocore.org
>For additional commands, e-mail: users-help at edk2.tianocore.org



From rohit.venkatachalam at wipro.com  Wed Aug 30 13:15:51 2006
From: rohit.venkatachalam at wipro.com (rohit.venkatachalam at wipro.com)
Date: Wed, 30 Aug 2006 11:15:51 -0000
Subject: [LinuxBIOS] VGA bring up
Message-ID: <ACECBCCF77262F48BAAE49E651BE888401549D50@blr-m3-msg.wipro.com>



Hi,

    I have got LinuxBIOS running on my system. I have got serial console
output. I am trying to get the display(VGA) working. However, from the
serial output, I see  something like -

0000:4002 ILLEGAL EXTENDED X86 OPCODE
halt_sys:/home/rohit/LinuxBIOSv2/src/devices/emulator/x86emu/ops2.c line
60

and the VGA display does not start. The execution of LinuxBIOS continues
beyond this point but no VGA display. What could be the problem? Someone
please reply ASAP.

Regards ,

    Rohit.





The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments.

WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email.

www.wipro.com
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20060830/f7609c76/attachment.html>

From borg_no.one at gmx.net  Fri Aug 25 19:54:53 2006
From: borg_no.one at gmx.net (Borg No. One)
Date: Fri, 25 Aug 2006 17:54:53 -0000
Subject: [LinuxBIOS] testing with system emulator
In-Reply-To: <mailman.19.1156474960.13384.linuxbios@linuxbios.org>
References: <mailman.19.1156474960.13384.linuxbios@linuxbios.org>
Message-ID: <20060825175450.18960@gmx.net>

Hi.

VMware and bochs provide the capabilities to simply change their system BIOS.
In VMware and Bochs you can set a filename for the BIOS that the Emulator/Virtual Machines shall use.

More about: "VMware/Bochs<-->BIOS development/Option ROM development" can be found here:

http://etherboot.org/wiki/vmwarebios

There are also two links inside the article which refer to the VMware forums.
You should visit the links too.


Borg Number One

--BIOS Tool Collection--
--BIOS modifications and realtime desktop help service--
http://bnobtc.pix-art.com
http://bnobtc.pix-art.com/eservice

--BIOS Logo Gallery--
http://bnobtc.pix-art.com/bioslogo
http://bnobtc.pix-art.com/images/bioslogo


> Date: Fri, 25 Aug 2006 08:50:06 +0800
> From: "Rogelio Serrano" <rogelio.serrano at gmail.com>
> Subject: [LinuxBIOS] testing with system emulator
> To: linuxbios at linuxbios.org
> Message-ID:
> 	<a9951d2a0608241750h61965815l8a45d284dcbafbb6 at mail.gmail.com>
> Content-Type: text/plain; charset=UTF-8; format=flowed
> 
> Is there an emulator that we can use for development and testing?
> Something that i can customise with registers to look like my
> motherboard?
> 
> -- 
> things i hate about my linux pc:
> 
> 1. it takes more than a second to boot up
> 2. keeps asking about filenames and directories
> 3. does not remember what i was working on yesterday
> 4. does not remember all the changes i have ever made
> 5.cannot figure out necessary settings by itself
-- 


Der GMX SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen!
Ideal f?r Modem und ISDN: http://www.gmx.net/de/go/smartsurfer