[LinuxBIOS] 440bx stuff
smithbone at gmail.com
Sun Nov 5 17:07:58 CET 2006
Thinking about this some more, whats needed is a lot of grunt work that
doesn't necessarily have to be done by the same person who fixes the ram
Here's TODO from my past emails..
> 1. I named both the northbridge and the southbridge i440bx. While I
> don't think it s a huge problem. The southbridge code needs to be
> changed to piix4 since thats really what the part is. I'll hopefully
> be able to do that soon.
This has been done. It's now i82371eb.
> 2. I seemed to have based the framework on one of the VIA chips. But
> looking at things now I see a much better choice would have been the
> Intel e7501. Hopefully I can find some time to work on this a bit
> this week.
This still outstanding. If someone is feeling spunky they could go
through the code re-do most of the stuff thats there.
The only thing functional in the current code is the boot stuff and the
core SPD read functions, everything else is up for grabs. Its
possible, (but I won't promise anything) that if someone were to get the
framework all setup that I could come in and spend an hour or 2
comparing the ram init code to V1 and fixup the missing details.
One thing that can be done that doesn't require you to grok the ram init
code but is still necessary is verifying the SPD support code functions
are spiting out the right values.
The e7501 raminit code is _very_ well commented and pretty easy to
follow even if you don't understand whats happening. A lot of the
registers also seem very familiar to what I remember from the 440bx data
So the first step here is to start patching in the e7501 code and
auditing it against the 440bx datasheet and V1 and then checking to see
if the sane values are popping out of the various spd_support functions.
Things like number of dram sticks installed, what the min cas timing is
across all sticks, etc.
None of this is really hard just very time consuming. That would go a
_long_ way in helping me make this chipset fly again.
Richard A. Smith
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