[LinuxBIOS] 440BX progress.

Segher Boessenkool segher at kernel.crashing.org
Mon Nov 27 09:05:12 CET 2006

>> There _are_ differences, but nothing related to the RAM config
>> registers
>> as far as I can see.
> I'll have a look at it too, second pair of eyes...

Okay...  So, is this your DIMM?

100MHz SDRAM, 64MB, in last (4th) slot.  8-bit devices.
9 row bits, 14 column bits, 4 banks.  CL=3, RCD=3, RP=3
(all in clock cycles).

You did forget a few registers though -- the three bytes
at offset 0xca, and the 16 bytes at offset 0xe0.  Be careful
to set the enable bit (bit 7 in 0xe7) last.

Also, you probably didn't program the MRS on the memory.
You should do that with the register at 0x76.  The correct
sequence is:

- precharge all banks, wait tRP
- refresh, wait tRC (do this step 8 times)
- write to MRS, wait 2 memory cycles

(this system is slow enough that all those "waits" can be
NOPs, fwiw).

The bits in MRS you need are:
6..4: CAS latency (CL), 3 in your case (so 011) [the datasheet
       is wrong here];
3: burst type, only interleave (1) is supported on this chip;
2..0: burst length, 010=4 is the only thing supported on i440BX;
So, that makes 0111010 i.e. 0x3a.

...and then you can use the memory.

To figure out what host addresses you should use to get
onto the DRAM address pins A13..A0, look at the tables in
chapter 4.3.  I think shifting to the left by 15 bits would
work in your case, so accessing address 0x1d0000.  This
should be done per DIMM rank, but you only have one anyway :-)

Well there you go, experiment a bit and you'll get it right.
You're lucky this memory controller is so ancient (and very
simple even then).

Have fun,


More information about the coreboot mailing list