From jerj at coplanar.net Mon Oct 2 06:14:14 2006 From: jerj at coplanar.net (Jeremy Jackson) Date: Mon, 02 Oct 2006 00:14:14 -0400 Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L In-Reply-To: <8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com> References: <1154140868.9333.47.camel@cslewis> <8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com> Message-ID: <1159762454.13264.123.camel@ragnarok.coplanar.net> Hi, It's fantastic to see progress on a port to v2 for the 440BX, I had v1 working for a total of 5 minutes, about a year ago, which left me wanting more! I've got two Asus P2B here, some P2-99, and a P2B-F. I did an SVN checkout, configured an Etherboot payload, and flashed to SST 29F002 with Uniflash, to a P2B: LinuxBIOS-2.0.0.0Fallback Sun Oct 1 22:50:50 EDT 2006 starting... SMBus controller enabled dimm: 00.0: 50 00: 80 08 04 0c 09 01 40 00 01 75 54 00 80 10 00 01 10: 8f 04 04 01 01 00 0e 00 00 00 00 14 0e 14 2d 10 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 a3 40: 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 50: 53 41 30 33 30 30 39 00 00 00 00 00 00 00 00 00 60: 00 00 00 4d 53 33 38 36 34 55 50 53 2d 54 38 36 70: 41 33 00 00 00 00 00 00 00 00 00 00 00 00 64 cd 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 01.0: 51 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ..... the rest (dimm 1-3) are all 0xff, then: ..... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. my PCI POST card displays 12. I tried a 64, 128, and 256MB module. Any suggestions? Regards, Jeremy PS - After I get this going, Tyan S2865 is next. On Sat, 2006-07-29 at 08:24 -0500, Richard Smith wrote: > I've done this already. I'll push the code up in a few hours or so. > Its on a machine I don't have local access to right now. Its pretty > easy though just find an existing SuperIO in V2 copy over the > structure and replace the names and guts of the functions with the > stuff for the new SuperIO. The NSC chip that the Bitoworks IMS uses > would be a good example. .... > After I push up the p2b stuff, you can look at it. Its got some > debug output. The file you want to look at is auto.c. Thats the > first part of your mainboard config that is run. -- Jeremy Jackson jerj at coplanar.net Email/Jabber/Google Talk/MSN (519)489-4903 Coplanar Networks http://www.coplanar.net From smithbone at gmail.com Mon Oct 2 12:54:24 2006 From: smithbone at gmail.com (Richard Smith) Date: Mon, 2 Oct 2006 05:54:24 -0500 Subject: [LinuxBIOS] LinuxBIOS on ASUS P2B-L In-Reply-To: <1159762454.13264.123.camel@ragnarok.coplanar.net> References: <1154140868.9333.47.camel@cslewis> <8a0c36780607290624p2dfe09edw5e07256627fb920d@mail.gmail.com> <1159762454.13264.123.camel@ragnarok.coplanar.net> Message-ID: <8a0c36780610020354j7a918568r5c0c96df6b97d75e@mail.gmail.com> > Copying LinuxBIOS to ram. > Jumping to LinuxBIOS. > > my PCI POST card displays 12. > > I tried a 64, 128, and 256MB module. > > Any suggestions? > Yeah. Add the code to actually do the ram init. :) The current setup is broken. Don't mess with it any further. However, don't fear. We are all here at the Linux Symposium and we have at least 2 asus P2B's. A goal for either tonight or tomorrow evening is to make RAM init code work on the i440bx. -- Richard A. Smith From ward at gnu.org Mon Oct 2 15:39:40 2006 From: ward at gnu.org (Ward Vandewege) Date: Mon, 2 Oct 2006 15:39:40 +0200 Subject: [LinuxBIOS] request for programmers manual maintainer Message-ID: <20061002133939.GA9960@countzero.vandewege.net> Greetings from the LinuxBIOS symposium in Hamburg! We're on our second day, and things have been going very well. We've been having some very interesting sessions, and even started doing some (late-night) hacking. We got an OLPC demo - booting openfirmware and linux kernel payloads! The folks from AMD gave an interesting talk about AMD's linuxBIOS roadmap. We've talked about payloads, and about how to rework the configuration system. Lots of interesting stuff. The slides from the talks should be online soon - hopefully in a couple or days or so. Some pictures are already linked to from here: http://linuxbios.org/index.php/LinuxBIOS_Symposium_2006_Photos We'll post more links there as we upload more photos. Now; this morning we had a discussion about the creation of a Programmer's manual. The idea is to create much more documentation for people who want to start hacking on LinuxBIOS. People who contribute code would ideally also write documentation about that code - but there might be other contributors too, of course. The consensus of the discussion was that we need a coordinator for the Programmer's manual. Ideally someone who is *not* yet very familiar with the codebase, or even with low-level programming. Such a person would basically oversee the creation of the manual, encouraging (pestering?) coders to also contribute documentation, etc. It would be a great way to dive into LinuxBIOS programming - the coordinator is pretty much guaranteed to learn a lot as this manual takes shape. The question is - anyone here who would be interested in taking on this role? Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior System Administrator From c-d.hailfinger.devel.2006 at gmx.net Mon Oct 2 16:53:37 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 02 Oct 2006 16:53:37 +0200 Subject: [LinuxBIOS] request for programmers manual maintainer In-Reply-To: <20061002133939.GA9960@countzero.vandewege.net> References: <20061002133939.GA9960@countzero.vandewege.net> Message-ID: <452127F1.80205@gmx.net> Ward Vandewege wrote: > The question is - anyone here who would be interested in taking on this role? I am interested, but I won't be able to devote too much time to it before december because of university exams. Regards, Carl-Daniel From kononov195-lbl at yahoo.com Mon Oct 2 18:20:35 2006 From: kononov195-lbl at yahoo.com (Roman Kononov) Date: Mon, 02 Oct 2006 11:20:35 -0500 Subject: [LinuxBIOS] flashrom SST49LF080A patch Message-ID: <45213C53.2060205@yahoo.com> Hello, The first patch changes chip erase method from JEDEC Chip Erase to JEDEC Sector Erase for each sector. See the comment in util/flashrom/sst49lf040.c, line #40. Verified on a real SST49LF080A chip, for which JEDEC Chip Erase did not work as well. The second patch makes printf working [as designed]. Roman Index: util/flashrom/flashchips.c =================================================================== --- util/flashrom/flashchips.c (revision 2434) +++ util/flashrom/flashchips.c (working copy) @@ -67,7 +67,7 @@ {"SST49LF040", SST_ID, SST_49LF040, NULL, 512, 4096, probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF080A", SST_ID, SST_49LF080A, NULL, 1024, 4096, - probe_jedec, erase_chip_jedec, write_49lf040,NULL}, + probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF002A/B", SST_ID, SST_49LF002A, NULL, 256, 16 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub, NULL}, {"SST49LF003A/B", SST_ID, SST_49LF003A, NULL, 384, 64 * 1024, Index: util/flashrom/sst49lf040.c =================================================================== --- util/flashrom/sst49lf040.c (revision 2434) +++ util/flashrom/sst49lf040.c (working copy) @@ -59,13 +59,11 @@ erase_sector_jedec(bios, i * page_size); /* write to the sector */ - if((i&0xfff)==0xfff) - printf("%04d at address: 0x%08x ", i, i * page_size); + printf("%04d at address: 0x%08x ", i, i * page_size); write_sector_jedec(bios, buf + i * page_size, bios + i * page_size, page_size); - if((i&0xfff)==0xfff) - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); fflush(stdout); } printf("\n"); From yinghai.lu at amd.com Mon Oct 2 19:43:47 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Mon, 2 Oct 2006 10:43:47 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D63B@ssvlexmb2.amd.com> If you have problem with it, please let me know. Thanks Yinghai Lu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: rev_f_support_08042006.tar.bz2 Type: application/octet-stream Size: 87342 bytes Desc: rev_f_support_08042006.tar.bz2 URL: From c-d.hailfinger.devel.2006 at gmx.net Mon Oct 2 20:23:46 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 02 Oct 2006 20:23:46 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D63B@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D63B@ssvlexmb2.amd.com> Message-ID: <45215932.6060304@gmx.net> Hello Yinghai, Lu, Yinghai wrote: > If you have problem with it, please let me know. # grep -i opyri * x1_slit.diff:- * Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. x_f_failover_api.diff:+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. x_f_failover_api.diff:+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. x_f_failover_api.diff:+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. x_f_other.diff: /* Copyright 2005 AMD x_f_other.diff: Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. x_f_other.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * (C) Copyright 2005 Stefan Reinauer # grep -i gpl * # grep -i lice * was is intentional that this adds quite a few files which have a "Copyright 2005 AMD" tag, but do not mention the GPL? Regards, Carl-Daniel From yinghai.lu at amd.com Mon Oct 2 20:43:14 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Mon, 2 Oct 2006 11:43:14 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D63C@ssvlexmb2.amd.com> To my personal understanding, copyright is copyright, license is license. Every code in LinuxBIOS is under GPL. YH -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] Sent: Monday, October 02, 2006 11:24 AM To: Lu, Yinghai Cc: linuxbios at linuxbios.org Subject: Re: [LinuxBIOS] FW: rev F support code Hello Yinghai, Lu, Yinghai wrote: > If you have problem with it, please let me know. # grep -i opyri * x1_slit.diff:- * Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. x_f_failover_api.diff:+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. x_f_failover_api.diff:+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. x_f_failover_api.diff:+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. x_f_other.diff: /* Copyright 2005 AMD x_f_other.diff: Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. x_f_other.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * Copyright 2005 AMD x_mb.diff:+ * (C) Copyright 2005 Stefan Reinauer # grep -i gpl * # grep -i lice * was is intentional that this adds quite a few files which have a "Copyright 2005 AMD" tag, but do not mention the GPL? Regards, Carl-Daniel From stepan at coresystems.de Mon Oct 2 22:38:50 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Mon, 2 Oct 2006 22:38:50 +0200 Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <45213C53.2060205@yahoo.com> References: <45213C53.2060205@yahoo.com> Message-ID: <20061002203850.GA8845@coresystems.de> * Roman Kononov [061002 18:20]: > The second patch makes printf working [as designed]. putting this in will make it impossible to update the bios using a serial line. :-( -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From eswierk at arastra.com Mon Oct 2 23:52:40 2006 From: eswierk at arastra.com (Ed Swierk) Date: Mon, 2 Oct 2006 14:52:40 -0700 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D63B@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D63B@ssvlexmb2.amd.com> Message-ID: Does "rev F" include the AM2-socket Athlon 64 X2? I take it Serengeti refers to some internal AMD mainboard? Thanks, --Ed From yinghai.lu at amd.com Tue Oct 3 00:10:47 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Mon, 2 Oct 2006 15:10:47 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D642@ssvlexmb2.amd.com> Yes. Use cpu/amd/socket_AM2 instead of cpu/amd/socket_F in your MB Config. YH -----Original Message----- From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Ed Swierk Sent: Monday, October 02, 2006 2:53 PM To: linuxbios at linuxbios.org Subject: Re: [LinuxBIOS] FW: rev F support code Does "rev F" include the AM2-socket Athlon 64 X2? I take it Serengeti refers to some internal AMD mainboard? Thanks, --Ed -- linuxbios mailing list linuxbios at linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios From kononov195-lbl at yahoo.com Tue Oct 3 00:24:28 2006 From: kononov195-lbl at yahoo.com (Roman Kononov) Date: Mon, 02 Oct 2006 17:24:28 -0500 Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <20061002203850.GA8845@coresystems.de> References: <45213C53.2060205@yahoo.com> <20061002203850.GA8845@coresystems.de> Message-ID: <4521919C.5010304@yahoo.com> On 10/02/2006 03:38 PM, Stefan Reinauer wrote: > putting this in will make it impossible to update the bios using a > serial line. :-( Cannot get it. Why? Thanks From stepan at coresystems.de Tue Oct 3 00:36:59 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 3 Oct 2006 00:36:59 +0200 Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <4521919C.5010304@yahoo.com> References: <45213C53.2060205@yahoo.com> <20061002203850.GA8845@coresystems.de> <4521919C.5010304@yahoo.com> Message-ID: <20061002223659.GA17206@coresystems.de> * Roman Kononov [061003 00:24]: > On 10/02/2006 03:38 PM, Stefan Reinauer wrote: > > putting this in will make it impossible to update the bios using a > > serial line. :-( > > Cannot get it. Why? because you are trying to output 18874368 characters during a single flash. 1) it will mess up your timing during the write process. 2) if you are on a 9600 baud line, writing the flash 1* will require 262 minutes. ;-) -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From rminnich at lanl.gov Tue Oct 3 00:34:58 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Mon, 02 Oct 2006 16:34:58 -0600 Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <4521919C.5010304@yahoo.com> References: <45213C53.2060205@yahoo.com> <20061002203850.GA8845@coresystems.de> <4521919C.5010304@yahoo.com> Message-ID: <45219412.9070109@lanl.gov> Roman Kononov wrote: > On 10/02/2006 03:38 PM, Stefan Reinauer wrote: > >>putting this in will make it impossible to update the bios using a >>serial line. :-( > > > Cannot get it. Why? > > Thanks > > it's something like 20 chars per byte write, so for 1 MB part, you're talking 20 M chars. It will take 20 minutes to print at 9600. I did this once on a 1024-node cluster. it was really bad. 1 billion chars. ron From kononov195-lbl at yahoo.com Tue Oct 3 00:59:14 2006 From: kononov195-lbl at yahoo.com (Roman Kononov) Date: Mon, 02 Oct 2006 17:59:14 -0500 Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <45219412.9070109@lanl.gov> References: <45213C53.2060205@yahoo.com> <20061002203850.GA8845@coresystems.de> <4521919C.5010304@yahoo.com> <45219412.9070109@lanl.gov> Message-ID: <452199C2.3000509@yahoo.com> On 10/02/2006 05:34 PM, Ronald G Minnich wrote: > it's something like 20 chars per byte write, so for 1 MB part, you're > talking 20 M chars. It will take 20 minutes to print at 9600. I see. But in this case, before the patch, it printfs once per 4096 sectors, which is never. After the patch, it printfs once per sector, which is once per 64K. Roman From stepan at coresystems.de Tue Oct 3 01:17:54 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 3 Oct 2006 01:17:54 +0200 Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <45213C53.2060205@yahoo.com> References: <45213C53.2060205@yahoo.com> Message-ID: <20061002231754.GA27065@coresystems.de> * Roman Kononov [061002 18:20]: > Hello, > > The first patch changes chip erase method from JEDEC Chip Erase to JEDEC Sector Erase for > each sector. See the comment in util/flashrom/sst49lf040.c, line #40. Verified on a real > SST49LF080A chip, for which JEDEC Chip Erase did not work as well. > > The second patch makes printf working [as designed]. > > Roman Ups. It seems you are right on the printf part. Looks like too much hacking after midnight ;-) Let me test it when I am back from the LinuxBIOS symposium and had enough sleep ;) Guess we want this in. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From rminnich at lanl.gov Tue Oct 3 01:56:14 2006 From: rminnich at lanl.gov (Ronald G. Minnich) Date: Mon, 2 Oct 2006 17:56:14 -0600 (MDT) Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <452199C2.3000509@yahoo.com> References: <45213C53.2060205@yahoo.com> <20061002203850.GA8845@coresystems.de> <4521919C.5010304@yahoo.com> <45219412.9070109@lanl.gov> <452199C2.3000509@yahoo.com> Message-ID: <24262.128.165.0.81.1159833374.squirrel@webmail.lanl.gov> roman, mea culpa, I think you are right. We are all worn out here in hamburg and three of us misread the patch the same way. Sorry! I'll talk to stefan tomorrow and we'll probably go for it. Thanks for fixing that part. ron From jtd at mtnl.net.in Tue Oct 3 07:19:45 2006 From: jtd at mtnl.net.in (jtd) Date: Tue, 3 Oct 2006 10:49:45 +0530 Subject: [LinuxBIOS] request for programmers manual maintainer In-Reply-To: <20061002133939.GA9960@countzero.vandewege.net> References: <20061002133939.GA9960@countzero.vandewege.net> Message-ID: <200610031049.45590.jtd@sparc.net> On Monday 02 October 2006 19:09, Ward Vandewege wrote: > Greetings from the LinuxBIOS symposium in Hamburg! snip > Now; this morning we had a discussion about the creation of a > Programmer's manual. The idea is to create much more documentation > for people who want to start hacking on LinuxBIOS. People who > contribute code would ideally also write documentation about that > code - but there might be other contributors too, of course. > > The consensus of the discussion was that we need a coordinator for > the Programmer's manual. Ideally someone who is *not* yet very > familiar with the codebase, or even with low-level programming. > Such a person would basically oversee the creation of the manual, > encouraging (pestering?) coders to also contribute documentation, > etc. It would be a great way to dive into LinuxBIOS programming - > the coordinator is pretty much guaranteed to learn a lot as this > manual takes shape. > > The question is - anyone here who would be interested in taking on > this role? I have been hanging out on the list for quite sometime now. Wrote documentation for various hardware and software projects in the distant past. I live in Mumbai India (if that's of interest). I can take this up or assist whoever is assigned the task. -- Rgds JTD From tylerapohl at gmail.com Tue Oct 3 23:08:44 2006 From: tylerapohl at gmail.com (Tyler Pohl) Date: Tue, 3 Oct 2006 14:08:44 -0700 Subject: [LinuxBIOS] coordinator Message-ID: <503ab0210610031408w3429329cg8f779d3b0b9e77a4@mail.gmail.com> > Now; this morning we had a discussion about the creation of a > Programmer's manual. The idea is to create much more documentation > for people who want to start hacking on LinuxBIOS. People who > contribute code would ideally also write documentation about that > code - but there might be other contributors too, of course. > > The consensus of the discussion was that we need a coordinator for > the Programmer's manual. Ideally someone who is *not* yet very > familiar with the codebase, or even with low-level programming. > Such a person would basically oversee the creation of the manual, > encouraging (pestering?) coders to also contribute documentation, > etc. It would be a great way to dive into LinuxBIOS programming - > the coordinator is pretty much guaranteed to learn a lot as this > manual takes shape. > > The question is - anyone here who would be interested in taking on > this role? I'm very interested, I just wouldn't know where to start :) Could someone point me in a direction. Tyler Pohl -------------- next part -------------- An HTML attachment was scrubbed... URL: From tylerapohl at gmail.com Wed Oct 4 02:54:59 2006 From: tylerapohl at gmail.com (Tyler Pohl) Date: Tue, 3 Oct 2006 17:54:59 -0700 Subject: [LinuxBIOS] added support sst29sf020 Message-ID: <503ab0210610031754n781297dcle603f0344ad9f639@mail.gmail.com> I added support to the flashrom source for the sst29sf020. I though i would contribute. Source is attached. P.S. Good coding of the flashrom thank you. Very easy to modify. Tyler Pohl -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: sst29sf020.tar Type: application/x-tar Size: 358400 bytes Desc: not available URL: From tylerapohl at gmail.com Wed Oct 4 07:01:09 2006 From: tylerapohl at gmail.com (Tyler Pohl) Date: Tue, 3 Oct 2006 22:01:09 -0700 Subject: [LinuxBIOS] via/epia/ Message-ID: <503ab0210610032201p40cb63d2kda26ba32531c3794@mail.gmail.com> At first after flashing the eeprom i soft rebooted my output was: My monitor flashed colors Serial Output: ??X?a?inuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 0080 is the chip size 0008 is the MA type Slot 01 is SDRAM 04000000 bytes x2 0040 is the chip size 0008 is the MA type Slot 02 is empty Slot 03 is empty vt8601 done Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 booting... Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 0 set_pci_ops: seeking driver for 1106:601 class 60000 PCI: 00:00.0 [1106/0601] ops PCI: 00:00.0 [1106/0601] enabled malloc Enter, size 668, free_mem_ptr 00018000 malloc 0x00018000 set_pci_ops: seeking driver for 1106:8601 class 60400 Capability: 0x07 @ 0x80 Capability: 0x08 @ 0x80 Capability: 0x10 @ 0x80 PCI: 00:01.0 [1106/8601] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff set_pci_ops: seeking driver for 1106:8231 class 60100 PCI: 00:11.0 [1106/8231] bus ops PCI: 00:11.0 [1106/8231] enabled set_pci_ops: seeking driver for 1106:571 class 1018a PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled set_pci_ops: seeking driver for 1106:3038 class c0300 PCI: 00:11.2 [1106/3038] disabled set_pci_ops: seeking driver for 1106:3038 class c0300 PCI: 00:11.3 [1106/3038] disabled set_pci_ops: seeking driver for 1106:8235 class 68000 PCI: 00:11.4 [1106/8235] ops PCI: 00:11.4 [1106/8235] disabled set_pci_ops: seeking driver for 1106:3058 class 40100 PCI: 00:11.5 [1106/3058] disabled set_pci_ops: seeking driver for 1106:3068 class 78000 PCI: 00:11.6 [1106/3068] enabled PCI: devfn 0x8f, bad id 0xffffffff set_pci_ops: seeking driver for 1106:3065 class 20000 PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 1 malloc Enter, size 668, free_mem_ptr 0001829c malloc 0x0001829c set_pci_ops: seeking driver for 1023:8500 class 30000 PCI: 01:00.0 [1023/8500] enabled PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=01 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=01 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 0 LinuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 0080 is the chip size 0008 is the MA type Slot 01 is SDRAM 04000000 bytes x2 0040 is the chip size 0008 is the MA type Slot 02 is empty Slot 03 is empty vt8601 done Copying LinuxBIOS to ram. Jumping to LinuxBIOS. ____________________________________________- Then I powered down the via board and my output was: No video at all serial output: LinuxBIOS-2.0.0.0Normal Tue Oct 3 19:10:30 PDT 2006 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 0080 is the chip size 0008 is the MA type Slot 01 is SDRAM 04000000 bytes x2 0040 is the chip size 0008 is the MA type Slot 02 is empty Slot 03 is empty vt8601 done Copying LinuxBIOS to ram. Jumping to LinuxBIOS. Any sugestions? How do you enable the RAM test function? In mainboard/via/epia/auto.c ........... I did the following tring to enable the RAM test but when i do a make i get an error Unblocked the following beacuse i don't know how the conditional assembly works in this case. ram_check(0x00000000, msr.lo); static const struct { unsigned long lo, hi; } check_addrs[] = { /* Check 16MB of memory @ 0*/ { 0x00000000, 0x01000000 }, My make error: /home/tyler/LinuxBIOSv2/src/mainboard/via/epia/auto.c -o auto.inc auto.c:113.34: msr undeclared make[1]: *** [auto.inc] Error 1 make[1]: Leaving directory `/home/tyler/LinuxBIOSv2/targets/via/epia/epia/normal' make: *** [normal/linuxbios.rom] Error 1 Where or what should msr be decalred as ? Thanks Again. -------------- next part -------------- An HTML attachment was scrubbed... URL: From dev at stuffit.at Wed Oct 4 17:34:27 2006 From: dev at stuffit.at (Devils-Hawk) Date: Wed, 04 Oct 2006 17:34:27 +0200 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <4523D483.20002@stuffit.at> I am no expert myself but as far as i know, the license is all about copyright. So because you( more spec. AMD ) is the copyright holder and copyright law grants certain rights ( e.g. prohibiting copying, modifying, etc ) only you can add the GPL notice, which does in fact only state that you forever revoke some of the rights granted to you by copyright law. If somebody else does add the notice you, the copyright holder, still has the right to sue for copyright infringement whenever it is convenient, because you did not grant the right to modify the code in the first place. The problem is, even if you state per mail that you have no problem with somebody else adding the GPL notice, such an written agreement is not enforecable in court in most of the countries on this planet. And another problem is that the "All rights Reserved" clause is as far as i know not compatible with the GPL, because you cannot reserve all rights at the same time you willingly give away some of them. For more detailed information you should probably go to groklaw.net or ask your in house lawyers. http://www.gnu.org/licenses/gpl-faq.html is a pretty good source of information too. Kind regards, DevH > To my personal understanding, copyright is copyright, license is > license. > > Every code in LinuxBIOS is under GPL. > > YH From ben at hewson-venieri.com Wed Oct 4 19:08:47 2006 From: ben at hewson-venieri.com (Ben Hewson) Date: Wed, 04 Oct 2006 18:08:47 +0100 Subject: [LinuxBIOS] via/epia/ In-Reply-To: <503ab0210610032201p40cb63d2kda26ba32531c3794@mail.gmail.com> References: <503ab0210610032201p40cb63d2kda26ba32531c3794@mail.gmail.com> Message-ID: <4523EA9F.2070805@hewson-venieri.com> to enable the RAM check look for this bit of code in auto.c #if 0 static const struct { unsigned long lo, hi; } check_addrs[] = { /* Check 16MB of memory @ 0*/ { 0x00000000, 0x01000000 }, #if TOTAL_CPUS > 1 /* Check 16MB of memory @ 2GB */ { 0x80000000, 0x81000000 }, #endif }; int i; for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { ram_check(check_addrs[i].lo, check_addrs[i].hi); } #endif change the #if 0 to #if 1 to enable the ram check. be aware that it will fail at a0000 , not sure if the are enough 0's there, but you will see. There is a bug in rom_cc where the first line after any #else is skipped. Don't think it has been fixed yet. Unless you have changed the settings to use cl2 ram and 133 Mhz bus(default is cl3 and 100Mhz), it will not initialise ram properly. Do you ever experience any long delays/hangs when booting ? after the 1106 0601 message. My board is having problems with the smbus code. The first read of the spd data always seems to fail. Not sure if it is my ram modules or a problem with the code. Don't have any problems booting and running with the original bios. Not yet got to the bottom of the problem, kind of been busy of late. Ben Tyler Pohl wrote: > At first after flashing the eeprom i soft rebooted my output was: > My monitor flashed colors > > Serial Output: > ??X?a?inuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 starting... > 87 is the comm register > SMBus controller enabled > vt8601 init starting > 00000000 is the north > 1106 0601 > 0120d4 is the computed timing > NOP > PRECHARGE > DUMMY READS > CBR > MRS > NORMAL > set ref. rate > enable multi-page open > Slot 00 is SDRAM 08000000 bytes x2 > 0080 is the chip size > 0008 is the MA type > Slot 01 is SDRAM 04000000 bytes x2 > 0040 is the chip size > 0008 is the MA type > Slot 02 is empty > Slot 03 is empty > vt8601 done > Copying LinuxBIOS to ram. > Jumping to LinuxBIOS. > LinuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 booting... > Enumerating buses... > scan_static_bus for Root Device > Finding PCI configuration type. > PCI: Using configuration type 1 > PCI_DOMAIN: 0000 enabled > APIC_CLUSTER: 0 enabled > PCI_DOMAIN: 0000 scanning... > PCI: pci_scan_bus for bus 0 > set_pci_ops: seeking driver for 1106:601 class 60000 > PCI: 00:00.0 [1106/0601] ops > PCI: 00:00.0 [1106/0601] enabled > malloc Enter, size 668, free_mem_ptr 00018000 > malloc 0x00018000 > set_pci_ops: seeking driver for 1106:8601 class 60400 > Capability: 0x07 @ 0x80 > Capability: 0x08 @ 0x80 > Capability: 0x10 @ 0x80 > PCI: 00:01.0 [1106/8601] enabled > PCI: devfn 0x10, bad id 0xffffffff > PCI: devfn 0x18, bad id 0xffffffff > PCI: devfn 0x20, bad id 0xffffffff > PCI: devfn 0x28, bad id 0xffffffff > PCI: devfn 0x30, bad id 0xffffffff > PCI: devfn 0x38, bad id 0xffffffff > PCI: devfn 0x40, bad id 0xffffffff > PCI: devfn 0x48, bad id 0xffffffff > PCI: devfn 0x50, bad id 0xffffffff > PCI: devfn 0x58, bad id 0xffffffff > PCI: devfn 0x60, bad id 0xffffffff > PCI: devfn 0x68, bad id 0xffffffff > PCI: devfn 0x70, bad id 0xffffffff > PCI: devfn 0x78, bad id 0xffffffff > PCI: devfn 0x80, bad id 0xffffffff > set_pci_ops: seeking driver for 1106:8231 class 60100 > PCI: 00:11.0 [1106/8231] bus ops > PCI: 00:11.0 [1106/8231] enabled > set_pci_ops: seeking driver for 1106:571 class 1018a > PCI: 00:11.1 [1106/0571] ops > PCI: 00:11.1 [1106/0571] enabled > set_pci_ops: seeking driver for 1106:3038 class c0300 > PCI: 00:11.2 [1106/3038] disabled > set_pci_ops: seeking driver for 1106:3038 class c0300 > PCI: 00:11.3 [1106/3038] disabled > set_pci_ops: seeking driver for 1106:8235 class 68000 > PCI: 00:11.4 [1106/8235] ops > PCI: 00:11.4 [1106/8235] disabled > set_pci_ops: seeking driver for 1106:3058 class 40100 > PCI: 00:11.5 [1106/3058] disabled > set_pci_ops: seeking driver for 1106:3068 class 78000 > PCI: 00:11.6 [1106/3068] enabled > PCI: devfn 0x8f, bad id 0xffffffff > set_pci_ops: seeking driver for 1106:3065 class 20000 > PCI: 00:12.0 [1106/3065] ops > PCI: 00:12.0 [1106/3065] enabled > PCI: devfn 0x98, bad id 0xffffffff > PCI: devfn 0xa0, bad id 0xffffffff > PCI: devfn 0xa8, bad id 0xffffffff > PCI: devfn 0xb0, bad id 0xffffffff > PCI: devfn 0xb8, bad id 0xffffffff > PCI: devfn 0xc0, bad id 0xffffffff > PCI: devfn 0xc8, bad id 0xffffffff > PCI: devfn 0xd0, bad id 0xffffffff > PCI: devfn 0xd8, bad id 0xffffffff > PCI: devfn 0xe0, bad id 0xffffffff > PCI: devfn 0xe8, bad id 0xffffffff > PCI: devfn 0xf0, bad id 0xffffffff > PCI: devfn 0xf8, bad id 0xffffffff > do_pci_scan_bridge for PCI: 00:01.0 > PCI: pci_scan_bus for bus 1 > malloc Enter, size 668, free_mem_ptr 0001829c > malloc 0x0001829c > set_pci_ops: seeking driver for 1023:8500 class 30000 > PCI: 01:00.0 [1023/8500] enabled > PCI: devfn 0x8, bad id 0xffffffff > PCI: devfn 0x10, bad id 0xffffffff > PCI: devfn 0x18, bad id 0xffffffff > PCI: devfn 0x20, bad id 0xffffffff > PCI: devfn 0x28, bad id 0xffffffff > PCI: devfn 0x30, bad id 0xffffffff > PCI: devfn 0x38, bad id 0xffffffff > PCI: devfn 0x40, bad id 0xffffffff > PCI: devfn 0x48, bad id 0xffffffff > PCI: devfn 0x50, bad id 0xffffffff > PCI: devfn 0x58, bad id 0xffffffff > PCI: devfn 0x60, bad id 0xffffffff > PCI: devfn 0x68, bad id 0xffffffff > PCI: devfn 0x70, bad id 0xffffffff > PCI: devfn 0x78, bad id 0xffffffff > PCI: devfn 0x80, bad id 0xffffffff > PCI: devfn 0x88, bad id 0xffffffff > PCI: devfn 0x90, bad id 0xffffffff > PCI: devfn 0x98, bad id 0xffffffff > PCI: devfn 0xa0, bad id 0xffffffff > PCI: devfn 0xa8, bad id 0xffffffff > PCI: devfn 0xb0, bad id 0xffffffff > PCI: devfn 0xb8, bad id 0xffffffff > PCI: devfn 0xc0, bad id 0xffffffff > PCI: devfn 0xc8, bad id 0xffffffff > PCI: devfn 0xd0, bad id 0xffffffff > PCI: devfn 0xd8, bad id 0xffffffff > PCI: devfn 0xe0, bad id 0xffffffff > PCI: devfn 0xe8, bad id 0xffffffff > PCI: devfn 0xf0, bad id 0xffffffff > PCI: devfn 0xf8, bad id 0xffffffff > PCI: pci_scan_bus returning with max=01 > do_pci_scan_bridge returns max 1 > scan_static_bus for PCI: 00:11.0 > PNP: 002e.0 enabled > PNP: 002e.1 disabled > PNP: 002e.2 enabled > PNP: 002e.3 disabled > PNP: 002e.5 enabled > PNP: 002e.6 disabled > PNP: 002e.7 disabled > PNP: 002e.8 disabled > PNP: 002e.9 disabled > PNP: 002e.a disabled > PNP: 002e.b enabled > scan_static_bus for PCI: 00:11.0 done > PCI: pci_scan_bus returning with max=01 > scan_static_bus for Root Device done > done > Allocating resources... > Reading resources... > Root Device compute_allocate_io: base: 00000400 size: 00000000 align: > 0 gran: 0 > Root Device read_resources bus 0 link: 0 > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 > 0 > > LinuxBIOS-2.0.0.0Fallback Tue Oct 3 19:11:16 PDT 2006 starting... > 87 is the comm register > SMBus controller enabled > vt8601 init starting > 00000000 is the north > 1106 0601 > 0120d4 is the computed timing > NOP > PRECHARGE > DUMMY READS > CBR > MRS > NORMAL > set ref. rate > enable multi-page open > Slot 00 is SDRAM 08000000 bytes x2 > 0080 is the chip size > 0008 is the MA type > Slot 01 is SDRAM 04000000 bytes x2 > 0040 is the chip size > 0008 is the MA type > Slot 02 is empty > Slot 03 is empty > vt8601 done > Copying LinuxBIOS to ram. > Jumping to LinuxBIOS. > > > ____________________________________________- > > Then I powered down the via board and my output was: > > No video at all > > serial output: > LinuxBIOS-2.0.0.0Normal Tue Oct 3 19:10:30 PDT 2006 starting... > 87 is the comm register > SMBus controller enabled > vt8601 init starting > 00000000 is the north > 1106 0601 > 0120d4 is the computed timing > NOP > PRECHARGE > DUMMY READS > CBR > MRS > NORMAL > set ref. rate > enable multi-page open > Slot 00 is SDRAM 08000000 bytes x2 > 0080 is the chip size > 0008 is the MA type > Slot 01 is SDRAM 04000000 bytes x2 > 0040 is the chip size > 0008 is the MA type > Slot 02 is empty > Slot 03 is empty > vt8601 done > Copying LinuxBIOS to ram. > Jumping to LinuxBIOS. > > Any sugestions? > > > > How do you enable the RAM test function? > In mainboard/via/epia/auto.c ........... I did the following tring to > enable the RAM test but when i do a make i get an error > > Unblocked the following beacuse i don't know how the conditional > assembly works in this case. > > ram_check(0x00000000, msr.lo); > > static const struct { > unsigned long lo, hi; > } check_addrs[] = { > /* Check 16MB of memory @ 0*/ > { 0x00000000, 0x01000000 }, > > > > > My make error: > /home/tyler/LinuxBIOSv2/src/mainboard/via/epia/auto.c -o auto.inc > auto.c:113.34: > msr undeclared > make[1]: *** [auto.inc] Error 1 > make[1]: Leaving directory > `/home/tyler/LinuxBIOSv2/targets/via/epia/epia/normal' > make: *** [normal/linuxbios.rom] Error 1 > > Where or what should msr be decalred as ? > > > Thanks Again. > > > > > > > > > > > > > > > From a.mimms at f5.com Wed Oct 4 20:27:50 2006 From: a.mimms at f5.com (Alan Mimms) Date: Wed, 4 Oct 2006 11:27:50 -0700 Subject: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? Message-ID: <4E497EE4DD5F9347B242A83387F27DC8BFDAB2@exchsix.olympus.f5net.com> We have AMD dual Opteron hardware with AMD 8131+8111 chipsets attached. Using LinuxBIOS, we have a slight problem, that APPEARS to be related to the last 64Kbytes of RAM. Our kboot based environment, running in 32 bit instruction set, seems to randomly crash, and the implicated area of memory is this last 64KB. When we run a commercial BIOS on nearly identical hardware, we see that that BIOS has created in the E820 table an ACPI Non-Volatile-Storage area covering this last 64KB. LinuxBIOS is NOT doing that; LinuxBIOS is treating all of the space as simple USABLE space. In trying to figure this out, we have used the AMD HDT tool to read the last 64KB. We (SOMETIMES) the system crashes when we read this area using HDT. Can someone please explain what this area is for and why it's strange to read even using a hardware debugging tool? Is it REALLY in use for the ACPI NVS, and can we simply tell Linux to ignore it (map it out) by creating an entry in E820 table so it won't be used (we don't use ACPI suspend/resume)? Thanks very much for any information. Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center 1322 North Whitman Lane Liberty Lake, Washington 99019 v: 509-343-3524 f: 509-343-3501 -------------- next part -------------- An HTML attachment was scrubbed... URL: From yinghai.lu at amd.com Wed Oct 4 21:04:39 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Wed, 4 Oct 2006 12:04:39 -0700 Subject: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? Message-ID: <5986589C150B2F49A46483AC44C7BCA412D64C@ssvlexmb2.amd.com> What's your total RAM installed? 4G or more. With HW memory hole enable? YH ________________________________ From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Alan Mimms Sent: Wednesday, October 04, 2006 11:28 AM To: linuxbios at linuxbios.org Subject: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? We have AMD dual Opteron hardware with AMD 8131+8111 chipsets attached. Using LinuxBIOS, we have a slight problem, that APPEARS to be related to the last 64Kbytes of RAM. Our kboot based environment, running in 32 bit instruction set, seems to randomly crash, and the implicated area of memory is this last 64KB. When we run a commercial BIOS on nearly identical hardware, we see that that BIOS has created in the E820 table an ACPI Non-Volatile-Storage area covering this last 64KB. LinuxBIOS is NOT doing that; LinuxBIOS is treating all of the space as simple USABLE space. In trying to figure this out, we have used the AMD HDT tool to read the last 64KB. We (SOMETIMES) the system crashes when we read this area using HDT. Can someone please explain what this area is for and why it's strange to read even using a hardware debugging tool? Is it REALLY in use for the ACPI NVS, and can we simply tell Linux to ignore it (map it out) by creating an entry in E820 table so it won't be used (we don't use ACPI suspend/resume)? Thanks very much for any information. Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center 1322 North Whitman Lane Liberty Lake, Washington 99019 v: 509-343-3524 f: 509-343-3501 -------------- next part -------------- An HTML attachment was scrubbed... URL: From a.mimms at f5.com Wed Oct 4 21:59:18 2006 From: a.mimms at f5.com (Alan Mimms) Date: Wed, 4 Oct 2006 12:59:18 -0700 Subject: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D64C@ssvlexmb2.amd.com> Message-ID: <4E497EE4DD5F9347B242A83387F27DC8BFDACF@exchsix.olympus.f5net.com> The problem occurs with 1GB, 2GB or 4GB of memory installed for sure. I do not know about the HW memory hole. Can you explain what that is? Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center 1322 North Whitman Lane Liberty Lake, Washington 99019 v: 509-343-3524 f: 509-343-3501 ________________________________ From: Lu, Yinghai [mailto:yinghai.lu at amd.com] Sent: Wednesday, October 04, 2006 12:05 PM To: Alan Mimms; linuxbios at linuxbios.org; Andi Kleen Subject: RE: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? What's your total RAM installed? 4G or more. With HW memory hole enable? YH ________________________________ From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Alan Mimms Sent: Wednesday, October 04, 2006 11:28 AM To: linuxbios at linuxbios.org Subject: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? We have AMD dual Opteron hardware with AMD 8131+8111 chipsets attached. Using LinuxBIOS, we have a slight problem, that APPEARS to be related to the last 64Kbytes of RAM. Our kboot based environment, running in 32 bit instruction set, seems to randomly crash, and the implicated area of memory is this last 64KB. When we run a commercial BIOS on nearly identical hardware, we see that that BIOS has created in the E820 table an ACPI Non-Volatile-Storage area covering this last 64KB. LinuxBIOS is NOT doing that; LinuxBIOS is treating all of the space as simple USABLE space. In trying to figure this out, we have used the AMD HDT tool to read the last 64KB. We (SOMETIMES) the system crashes when we read this area using HDT. Can someone please explain what this area is for and why it's strange to read even using a hardware debugging tool? Is it REALLY in use for the ACPI NVS, and can we simply tell Linux to ignore it (map it out) by creating an entry in E820 table so it won't be used (we don't use ACPI suspend/resume)? Thanks very much for any information. Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center 1322 North Whitman Lane Liberty Lake, Washington 99019 v: 509-343-3524 f: 509-343-3501 -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at openbios.org Wed Oct 4 22:46:17 2006 From: svn at openbios.org (svn at openbios.org) Date: Wed, 04 Oct 2006 22:46:17 +0200 Subject: [LinuxBIOS] r2435 - in trunk/LinuxBIOSv2: src/arch/i386 src/arch/i386/boot src/arch/i386/include/arch src/arch/i386/init src/arch/i386/lib src/config src/cpu/amd src/cpu/amd/car src/cpu/amd/dualcore src/cpu/amd/model_fxx src/cpu/amd/model_gx2 src/cpu/amd/model_lx src/cpu/amd/mtrr src/cpu/amd/socket_AM2 src/cpu/amd/socket_F src/cpu/x86/car src/cpu/x86/lapic src/cpu/x86/mtrr src/devices src/include/cpu/amd src/include/cpu/x86 src/include/device src/lib src/mainboard/Iwill/DK8HTX src/mainboard/Iwill/DK8S2 src/mainboard/Iwill/DK8X src/mainboard/agami/aruma src/mainboard/amd src/mainboard/amd/serenade src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah/dx src/mainboard/amd/serengeti_leopard src/mainboard/arima/hdama src/mainboard/broadcom/blast src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/newisys/khepri src/mainboard/sunw/ultra40 src/mainboard/tyan/s2850 src/mainboard/tyan/s2875 src/mainboard/tyan/s2880 src/mainboard/tyan/s2881 src/mainboard/tyan/s2882 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/mainboard/tyan/s4880 src/mainboard/tyan/s4882 src/northbridge/amd/amdk8 src/southbridge/amd/amd8111 src/southbridge/broadcom/bcm5785 src/southbridge/nvidia/ck804 src/stream targets/amd targets/amd/serengeti_cheetah Message-ID: Author: yhlu Date: 2006-10-04 22:46:15 +0200 (Wed, 04 Oct 2006) New Revision: 2435 Added: trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_apc.lb trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_failover.lb trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_fallback.lb trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/ trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/Config.lb trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/chip.h trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/socket_AM2.c trunk/LinuxBIOSv2/src/cpu/amd/socket_F/ trunk/LinuxBIOSv2/src/cpu/amd/socket_F/Config.lb trunk/LinuxBIOSv2/src/cpu/amd/socket_F/chip.h trunk/LinuxBIOSv2/src/cpu/amd/socket_F/socket_F.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/chip.h trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cmos.layout trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_isa.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_pic.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8151.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci0_hc.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/superio.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/fadt.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mainboard.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f_pci.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/spd_ddr2.h trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/ssdt.dsl trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/ trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/Config.lb trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/VERSION Modified: trunk/LinuxBIOSv2/src/arch/i386/Config.lb trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h trunk/LinuxBIOSv2/src/arch/i386/include/arch/cpu.h trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h trunk/LinuxBIOSv2/src/arch/i386/init/ldscript.lb trunk/LinuxBIOSv2/src/arch/i386/lib/cpu.c trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf2.c trunk/LinuxBIOSv2/src/config/Config.lb trunk/LinuxBIOSv2/src/config/Options.lb trunk/LinuxBIOSv2/src/config/linuxbios_ram.ld trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c trunk/LinuxBIOSv2/src/cpu/amd/dualcore/amd_sibling.c trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore.c trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore_id.c trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/Config.lb trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/fidvid.c trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_earlymtrr.c trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_mtrr.c trunk/LinuxBIOSv2/src/cpu/x86/car/copy_and_run.c trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic.c trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/LinuxBIOSv2/src/cpu/x86/mtrr/earlymtrr.c trunk/LinuxBIOSv2/src/cpu/x86/mtrr/mtrr.c trunk/LinuxBIOSv2/src/devices/device_util.c trunk/LinuxBIOSv2/src/devices/hypertransport.c trunk/LinuxBIOSv2/src/include/cpu/amd/microcode.h trunk/LinuxBIOSv2/src/include/cpu/amd/model_fxx_rev.h trunk/LinuxBIOSv2/src/include/cpu/x86/mem.h trunk/LinuxBIOSv2/src/include/device/device.h trunk/LinuxBIOSv2/src/include/device/hypertransport_def.h trunk/LinuxBIOSv2/src/include/device/pci.h trunk/LinuxBIOSv2/src/include/device/pci_def.h trunk/LinuxBIOSv2/src/lib/nrv2b.c trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8S2/auto.c trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8X/auto.c trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb trunk/LinuxBIOSv2/src/mainboard/amd/serenade/auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/Options.lb trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/Options.lb trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_acpi.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/get_sblk_pci1234.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/incoherent_ht.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/misc_control.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/northbridge.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.h trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_enable_rom.c trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_reset.c trunk/LinuxBIOSv2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c trunk/LinuxBIOSv2/src/stream/rom_stream.c Log: AMD Rev F support Modified: trunk/LinuxBIOSv2/src/arch/i386/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/Config.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -1,10 +1,26 @@ uses CONFIG_SMP uses CONFIG_PRECOMPRESSED_ROM_STREAM uses CONFIG_USE_INIT +uses HAVE_FAILOVER_BOOT +uses USE_FAILOVER_IMAGE +uses USE_FALLBACK_IMAGE init init/crt0.S.lb -ldscript init/ldscript.lb +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + ldscript init/ldscript_failover.lb + else + ldscript init/ldscript.lb + end +else + if USE_FALLBACK_IMAGE + ldscript init/ldscript_fallback.lb + else + ldscript init/ldscript.lb + end +end + makerule all depends "linuxbios.rom" end @@ -21,7 +37,7 @@ makerule payload depends "$(PAYLOAD)" - action "cp -f $< $@" + action "cp $< $@" end makerule payload.nrv2b @@ -53,9 +69,19 @@ makedefine PAYLOAD-1:=payload end -makerule linuxbios.rom - depends "linuxbios.strip buildrom $(PAYLOAD-1)" - action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)" +if USE_FAILOVER_IMAGE + makedefine LINUXBIOS_APC:= + makedefine LINUXBIOS_RAM_ROM:= + + makerule linuxbios.rom + depends "linuxbios.strip" + action "cp $< $@" + end +else + makerule linuxbios.rom + depends "linuxbios.strip buildrom $(PAYLOAD-1)" + action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)" + end end makerule crt0.S @@ -72,11 +98,11 @@ action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o" end - makerule linuxbios - depends "crt0.o init.o linuxbios_ram.rom ldscript.ld" + makerule linuxbios + depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o" action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" - end + end end Modified: trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -203,6 +203,31 @@ header->checksum = acpi_checksum((void *)srat, header->length); } +void acpi_create_slit(acpi_slit_t *slit) +{ + + acpi_header_t *header=&(slit->header); + unsigned long current=(unsigned long)slit+sizeof(acpi_slit_t); + + memset((void *)slit, 0, sizeof(acpi_slit_t)); + + /* fill out header fields */ + memcpy(header->signature, SLIT_NAME, 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, SLIT_TABLE, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_slit_t); + header->revision = 1; + +// current = acpi_fill_slit(current); + + /* recalculate length */ + header->length= current - (unsigned long)slit; + + header->checksum = acpi_checksum((void *)slit, header->length); +} + void acpi_create_hpet(acpi_hpet_t *hpet) { #define HPET_ADDR 0xfed00000ULL Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -6,12 +6,9 @@ * * The ACPI table structs are based on the Linux kernel sources. * - * ACPI FADT & FACS added by Nick Barker + */ +/* ACPI FADT & FACS added by Nick Barker * those parts (C) 2004 Nick Barker - * - * ACPI SRAT support added in 2005.9 by yhlu - * Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. - * */ @@ -32,11 +29,13 @@ #define HPET_NAME "HPET" #define MADT_NAME "APIC" #define SRAT_NAME "SRAT" +#define SLIT_NAME "SLIT" #define RSDT_TABLE "RSDT " #define HPET_TABLE "AMD64 " #define MADT_TABLE "MADT " #define SRAT_TABLE "SRAT " +#define SLIT_TABLE "SLIT " #define OEM_ID "LXBIOS" #define ASLC "NONE" @@ -49,7 +48,7 @@ char oem_id[6]; /* OEM ID, "LXBIOS" */ u8 revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */ u32 rsdt_address; /* physical address of RSDT */ - u32 length; /* total length of RSDP (incl. extended part) */ + u32 length; /* total length of RSDP (including extended part) */ u64 xsdt_address; /* physical address of XSDT */ u8 ext_checksum; /* chechsum of whole table */ u8 reserved[3]; @@ -84,16 +83,15 @@ /* RSDT */ typedef struct acpi_rsdt { struct acpi_table_header header; - u32 entry[5+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, MADT(APIC), SSDT, SSDTX */ + u32 entry[6+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX*/ } __attribute__ ((packed)) acpi_rsdt_t; /* XSDT */ typedef struct acpi_xsdt { struct acpi_table_header header; - u64 entry[5+ACPI_SSDTX_NUM]; + u64 entry[6+ACPI_SSDTX_NUM]; } __attribute__ ((packed)) acpi_xsdt_t; - /* HPET TIMERS */ typedef struct acpi_hpet { struct acpi_table_header header; @@ -138,6 +136,11 @@ u32 resv2[2]; } __attribute__ ((packed)) acpi_srat_mem_t; +/* SLIT */ +typedef struct acpi_slit { + struct acpi_table_header header; + /* followed by static resource allocation 8+byte[num*num]*/ +} __attribute__ ((packed)) acpi_slit_t; /* MADT */ Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/cpu.h =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/include/arch/cpu.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/cpu.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -141,6 +141,25 @@ return ci->index; } + +struct cpuinfo_x86 { + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; +}; + +static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms) +{ + c->x86 = (tfms >> 8) & 0xf; + c->x86_model = (tfms >> 4) & 0xf; + c->x86_mask = tfms & 0xf; + if (c->x86 == 0xf) + c->x86 += (tfms >> 20) & 0xff; + if (c->x86 >= 0x6) + c->x86_model += ((tfms >> 16) & 0xF) << 4; + +} #endif #endif /* ARCH_CPU_H */ Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -4,75 +4,36 @@ #include -static inline uint8_t read8(unsigned long addr) +static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) { return *((volatile uint8_t *)(addr)); } -static inline uint16_t read16(unsigned long addr) +static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) { return *((volatile uint16_t *)(addr)); } -static inline uint32_t read32(unsigned long addr) +static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) { return *((volatile uint32_t *)(addr)); } -static inline void write8(unsigned long addr, uint8_t value) +static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) { *((volatile uint8_t *)(addr)) = value; } -static inline void write16(unsigned long addr, uint16_t value) +static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) { *((volatile uint16_t *)(addr)) = value; } -static inline void write32(unsigned long addr, uint32_t value) +static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) { *((volatile uint32_t *)(addr)) = value; } -#if 0 -typedef __builtin_div_t div_t; -typedef __builtin_ldiv_t ldiv_t; -typedef __builtin_udiv_t udiv_t; -typedef __builtin_uldiv_t uldiv_t; -static inline div_t div(int numer, int denom) -{ - return __builtin_div(numer, denom); -} - -static inline ldiv_t ldiv(long numer, long denom) -{ - return __builtin_ldiv(numer, denom); -} - -static inline udiv_t udiv(unsigned numer, unsigned denom) -{ - return __builtin_udiv(numer, denom); -} - -static inline uldiv_t uldiv(unsigned long numer, unsigned long denom) -{ - return __builtin_uldiv(numer, denom); -} - - - -inline int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} -#endif - static inline int log2(int value) { unsigned int r = 0; @@ -98,16 +59,16 @@ } -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x07) << 8) | \ - ((WHERE) & 0xFF)) +#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12) | \ + ((WHERE) & 0xFFF)) -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x7) << 8)) +#define PCI_DEV(SEGBUS, DEV, FN) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) @@ -117,58 +78,103 @@ typedef unsigned device_t; -static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) { unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); return inb(0xCFC + (addr & 3)); } -static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) { + return pci_io_read_config8(dev, where); +} + +static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) +{ unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); return inw(0xCFC + (addr & 2)); } -static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) +static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) { + return pci_io_read_config16(dev, where); +} + + +static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) +{ unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); } -static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) { + return pci_io_read_config32(dev, where); +} + +static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +{ unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); } +static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) +{ + pci_io_write_config8(dev, where, value); +} + + +static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); +} + static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) { - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); + pci_io_write_config16(dev, where, value); } -static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) + +static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); } +static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) +{ + pci_io_write_config32(dev, where, value); +} + #define PCI_DEV_INVALID (0xffffffffU) +static device_t pci_io_locate_device(unsigned pci_id, device_t dev) +{ + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + static device_t pci_locate_device(unsigned pci_id, device_t dev) { - for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) { + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { @@ -180,11 +186,11 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + device_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); - + for(; dev <=last; dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); @@ -195,8 +201,6 @@ return PCI_DEV_INVALID; } - - /* Generic functions for pnp devices */ static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) { Modified: trunk/LinuxBIOSv2/src/arch/i386/init/ldscript.lb =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/init/ldscript.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/init/ldscript.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -36,16 +36,13 @@ SECTIONS { . = _ROMBASE; - + .ram . : { _ram = . ; linuxbios_ram.rom(*) _eram = . ; } - _x = .; - . = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x; - /* This section might be better named .setup */ .rom . : { _rom = .; Added: trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_apc.lb =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_apc.lb (rev 0) +++ trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_apc.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,13 @@ +INPUT(linuxbios_apc.rom) +SECTIONS +{ + .apcrom . : { + _apcrom = .; + linuxbios_apc.rom(*) + _eapcrom = .; + } + _iseg_apc = DCACHE_RAM_BASE; + _eiseg_apc = _iseg_apc + SIZEOF(.apcrom); + _liseg_apc = _apcrom; + _eliseg_apc = _eapcrom; +} Added: trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_failover.lb =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_failover.lb (rev 0) +++ trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_failover.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,56 @@ +/* + * Memory map: + * + * _RAMBASE + * : data segment + * : bss segment + * : heap + * : stack + * _ROMBASE + * : linuxbios text + * : readonly text + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* +ENTRY(_start) +*/ + +TARGET(binary) +SECTIONS +{ + . = _ROMBASE; + + /* This section might be better named .setup */ + .rom . : { + _rom = .; + *(.rom.text); + *(.rom.data); + *(.rom.data.*); + . = ALIGN(16); + _erom = .; + } + + _lrom = LOADADDR(.rom); + _elrom = LOADADDR(.rom) + SIZEOF(.rom); + + /DISCARD/ : { + *(.comment) + *(.note) + } +} Added: trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_fallback.lb =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_fallback.lb (rev 0) +++ trunk/LinuxBIOSv2/src/arch/i386/init/ldscript_fallback.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,71 @@ +/* + * Memory map: + * + * _RAMBASE + * : data segment + * : bss segment + * : heap + * : stack + * _ROMBASE + * : linuxbios text + * : readonly text + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* +ENTRY(_start) +*/ + +TARGET(binary) +INPUT(linuxbios_ram.rom) +SECTIONS +{ + . = _ROMBASE; + + .ram . : { + _ram = . ; + linuxbios_ram.rom(*) + _eram = . ; + } + + /* cut _start into last 64k*/ + _x = .; + . = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x; + + /* This section might be better named .setup */ + .rom . : { + _rom = .; + *(.rom.text); + *(.rom.data); + *(.rom.data.*); + . = ALIGN(16); + _erom = .; + } + + _lrom = LOADADDR(.rom); + _elrom = LOADADDR(.rom) + SIZEOF(.rom); + _iseg = _RAMBASE; + _eiseg = _iseg + SIZEOF(.ram); + _liseg = _ram; + _eliseg = _eram; + + /DISCARD/ : { + *(.comment) + *(.note) + } +} Modified: trunk/LinuxBIOSv2/src/arch/i386/lib/cpu.c =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/lib/cpu.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/lib/cpu.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -222,6 +222,8 @@ */ struct device *cpu; struct cpu_info *info; + struct cpuinfo_x86 c; + info = cpu_info(); printk_notice("Initializing CPU #%d\n", info->index); @@ -245,6 +247,11 @@ identify_cpu(cpu); printk_debug("CPU: vendor %s device %x\n", cpu_vendor_name(cpu->vendor), cpu->device); + + get_fms(&c, cpu->device); + + printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask); + /* Lookup the cpu's operations */ set_cpu_ops(cpu); Modified: trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -10,40 +10,40 @@ #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)) -static uint8_t pci_conf1_read_config8(struct bus *pbus, unsigned char bus, int devfn, int where) +static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + return inb(0xCFC + (where & 3)); } -static uint16_t pci_conf1_read_config16(struct bus *pbus, unsigned char bus, int devfn, int where) +static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + return inw(0xCFC + (where & 2)); } -static uint32_t pci_conf1_read_config32(struct bus *pbus, unsigned char bus, int devfn, int where) +static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - return inl(0xCFC); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + return inl(0xCFC); } -static void pci_conf1_write_config8(struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t value) +static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outb(value, 0xCFC + (where & 3)); } -static void pci_conf1_write_config16(struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t value) +static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outw(value, 0xCFC + (where & 2)); } -static void pci_conf1_write_config32(struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t value) +static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(value, 0xCFC); } #undef CONFIG_CMD Modified: trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf2.c =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf2.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf2.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -12,7 +12,7 @@ #define FUNC(devfn) (((devfn & 7) << 1) | 0xf0) #define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA); -static uint8_t pci_conf2_read_config8(struct bus *pbus, unsigned char bus, int devfn, int where) +static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, int where) { uint8_t value; SET(bus, devfn); @@ -21,7 +21,7 @@ return value; } -static uint16_t pci_conf2_read_config16(struct bus *pbus, unsigned char bus, int devfn, int where) +static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, int where) { uint16_t value; SET(bus, devfn); @@ -30,7 +30,7 @@ return value; } -static uint32_t pci_conf2_read_config32(struct bus *pbus, unsigned char bus, int devfn, int where) +static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, int where) { uint32_t value; SET(bus, devfn); @@ -39,21 +39,21 @@ return value; } -static void pci_conf2_write_config8(struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t value) +static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) { SET(bus, devfn); outb(value, IOADDR(devfn, where)); outb(0, 0xCF8); } -static void pci_conf2_write_config16(struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t value) +static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) { SET(bus, devfn); outw(value, IOADDR(devfn, where)); outb(0, 0xCF8); } -static void pci_conf2_write_config32(struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t value) +static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) { SET(bus, devfn); outl(value, IOADDR(devfn, where)); Modified: trunk/LinuxBIOSv2/src/config/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/config/Config.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/config/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -1,6 +1,7 @@ ## This is Architecture independant part of the makefile uses HAVE_OPTION_TABLE +uses CONFIG_AP_CODE_IN_CAR makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) @@ -31,6 +32,12 @@ action "$(OBJCOPY) -O binary linuxbios linuxbios.strip" end +makerule linuxbios.a + depends "$(OBJECTS)" + action "rm -f linuxbios.a" + action "ar cr linuxbios.a $(OBJECTS)" +end + makerule linuxbios_ram.o depends "$(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)" action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)" @@ -63,18 +70,61 @@ action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom" end +makedefine LINUXBIOS_APC:= + +if CONFIG_AP_CODE_IN_CAR + #for ap code in cache + + makerule linuxbios_apc.a + depends "apc_auto.o" + action "rm -f linuxbios_apc.a" + action "ar cr linuxbios_apc.a apc_auto.o" + end + + makerule linuxbios_apc.o + depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)" + action "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)" + end + + makerule linuxbios_apc + depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions" + action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o" + action "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map" + end + + ## + ## By default compress the part of linuxbios that runs from cache as ram + ## + makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b + makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin + + makerule linuxbios_apc.bin + depends "linuxbios_apc" + action "$(OBJCOPY) -O binary $< $@" + end + + makerule linuxbios_apc.nrv2b + depends "linuxbios_apc.bin nrv2b" + action "./nrv2b e $< $@" + end + + makerule linuxbios_apc.rom + depends "$(LINUXBIOS_APC-1)" + action "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom" + end + + makedefine LINUXBIOS_APC:=linuxbios_apc.rom + +end + +makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom + makerule linuxbios - depends "crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld" + depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)" action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" end -makerule linuxbios.a - depends "$(OBJECTS)" - action "rm -f linuxbios.a" - action "ar cr linuxbios.a $(OBJECTS)" -end - #makerule crt0.S # depends "$(CRT0)" # action "cp $< $@" @@ -159,7 +209,7 @@ action "rm -f ldscript.ld" action "rm -f a.out *.s *.l *.o *.E *.inc" action "rm -f TAGS tags romcc*" - action "rm -f docipl buildrom* chips.c *chip.c linuxbios_ram* linuxbios_pay*" + action "rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*" action "rm -f build_opt_tbl* nrv2b* option_table.c crt0.S" end Modified: trunk/LinuxBIOSv2/src/config/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/config/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/config/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -178,18 +178,36 @@ export always comment "Set if fallback booting required" end +define HAVE_FAILOVER_BOOT + format "%d" + default 0 + export always + comment "Set if failover booting required" +end define USE_FALLBACK_IMAGE format "%d" default 0 export used comment "Set to build a fallback image" end +define USE_FAILOVER_IMAGE + format "%d" + default 0 + export used + comment "Set to build a failover image" +end define FALLBACK_SIZE default 65536 format "0x%x" export used comment "Default fallback image size" end +define FAILOVER_SIZE + default 0 + format "0x%x" + export used + comment "Default failover image size" +end define ROM_SIZE default none format "0x%x" @@ -274,9 +292,9 @@ comment "Use data cache as temporary RAM if possible" end define DCACHE_RAM_BASE - default none + default 0xc0000 format "0x%x" - export used + export always comment "Base address of data cache when using it for temporary RAM" end define DCACHE_RAM_SIZE @@ -291,6 +309,21 @@ export always comment "Size of region that for global variable of cache as ram stage" end +define CONFIG_AP_CODE_IN_CAR + default 0 + export always + comment "will copy linuxbios_apc to AP cache ane execute in AP" +end +define MEM_TRAIN_SEQ + default 0 + export always + comment "0: three for in bsp, 1: on every core0, 2: one for on bsp" +end +define WAIT_BEFORE_CPUS_INIT + default 0 + export always + comment "execute cpus_ready_for_init if it is set to 1" +end define XIP_ROM_BASE default 0 format "0x%x" @@ -853,7 +886,7 @@ define HT_CHAIN_UNITID_BASE default 1 export always - comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0" + comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0" end define HT_CHAIN_END_UNITID_BASE @@ -868,30 +901,67 @@ comment "this will decided if only offset SB hypertransport chain" end -define K8_SB_HT_CHAIN_ON_BUS0 +define SB_HT_CHAIN_ON_BUS0 default 0 export always - comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0" + comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0" end -define K8_HW_MEM_HOLE_SIZEK +define HW_MEM_HOLE_SIZEK default 0 export always comment "Opteron E0 later memory hole size in K, 0 mean disable" end -define K8_HW_MEM_HOLE_SIZE_AUTO_INC +define HW_MEM_HOLE_SIZE_AUTO_INC default 0 export always comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek" end define K8_HT_FREQ_1G_SUPPORT - default 0 + default 0 export always comment "Optern E0 later could support 1G HT, but still depends MB design" end +define K8_REV_F_SUPPORT + default 0 + export always + comment "Opteron Rev F (DDR2) support" +end + +define CBB + default 0 + export always + comment "Opteron cpu bus num base" +end + +define CDB + default 0x18 + export always + comment "Opteron cpu device num base" +end + +define DIMM_SUPPORT + default 0x0108 + format "0x%x" + export always + comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg" +end + +define CPU_SOCKET_TYPE + default 0x10 + export always + comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3" +end + +define CPU_ADDR_BITS + default 36 + export always + comment "CPU hardware address lines num, for AMD K8 could be 40, and GH could be 48" +end + define CONFIG_PCI_ROM_RUN default 0 export always Modified: trunk/LinuxBIOSv2/src/config/linuxbios_ram.ld =================================================================== --- trunk/LinuxBIOSv2/src/config/linuxbios_ram.ld 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/config/linuxbios_ram.ld 2006-10-04 20:46:15 UTC (rev 2435) @@ -109,7 +109,7 @@ _ram_seg = _text; _eram_seg = _eheap; - _bogus = ASSERT( ((_eram_seg>>10)>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK"); _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M"); Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2006-10-04 20:46:15 UTC (rev 2435) @@ -17,7 +17,7 @@ cache_as_ram_setup: /* hope we can skip the double set for normal part */ -#if USE_FALLBACK_IMAGE == 1 +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1)) /* check if cpu_init_detected */ movl $MTRRdefType_MSR, %ecx rdmsr @@ -56,16 +56,32 @@ wrmsr movl $0x269, %ecx wrmsr -#else +#endif - #if CacheSize == 0x8000 +#if CacheSize == 0xc000 + /* enable caching for 16K using fixed mtrr */ + movl $0x268, %ecx /* fix4k_c4000*/ + movl $0x06060606, %edx /* WB IO type */ + xorl %eax, %eax + wrmsr /* enable caching for 32K using fixed mtrr */ movl $0x269, %ecx /* fix4k_c8000*/ movl $0x06060606, %eax /* WB IO type */ + movl %eax, %edx + wrmsr + +#endif + + +#if CacheSize == 0x8000 + /* enable caching for 32K using fixed mtrr */ + movl $0x269, %ecx /* fix4k_c8000*/ + movl $0x06060606, %eax /* WB IO type */ movl %eax, %edx wrmsr - #else +#endif +#if CacheSize < 0x8000 /* enable caching for 16K/8K/4K using fixed mtrr */ movl $0x269, %ecx /* fix4k_cc000*/ #if CacheSize == 0x4000 @@ -79,8 +95,6 @@ #endif xorl %eax, %eax wrmsr - #endif - #endif /* enable memory access for first MBs using top_mem */ @@ -88,9 +102,10 @@ xorl %edx, %edx movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#endif /* USE_FALLBACK_IMAGE == 1*/ +#endif /* USE_FAILOVER_IMAGE == 1*/ -#if USE_FALLBACK_IMAGE == 0 + +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==0)) /* disable cache */ movl %cr0, %eax orl $(0x1<<30),%eax @@ -108,12 +123,12 @@ wrmsr movl $0x203, %ecx - movl $0x0000000f, %edx /* AMD 40 bit */ + movl $((1<<(CPU_ADDR_BITS-32))-1), %edx /* AMD 40 bit */ movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr #endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ -#if USE_FALLBACK_IMAGE == 1 +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1)) /* Set the default memory type and enable fixed and variable MTRRs */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx @@ -133,23 +148,25 @@ andl $0x9fffffff,%eax movl %eax, %cr0 -#if USE_FALLBACK_IMAGE == 1 +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1)) /* Read the range with lodsl*/ cld movl $CacheBase, %esi movl $(CacheSize>>2), %ecx - rep lodsl + rep + lodsl /* Clear the range */ movl $CacheBase, %edi movl $(CacheSize>>2), %ecx xorl %eax, %eax - rep stosl + rep + stosl -#endif /*USE_FALLBACK_IMAGE == 1*/ +#endif /*USE_FAILOVER_IMAGE == 1*/ /* set up the stack pointer */ - movl $(CacheBase+CacheSize - 4 - GlobalVarSize), %eax + movl $(CacheBase+CacheSize - GlobalVarSize), %eax movl %eax, %esp /* Restore the BIST result */ Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -2,7 +2,6 @@ moved from nrv2v.c and some lines from crt0.S 2006/05/02 - stepan: move nrv2b to an extra file. */ - static inline void print_debug_cp_run(const char *strval, uint32_t val) { #if CONFIG_USE_INIT @@ -46,8 +45,13 @@ print_debug_cp_run("src=",(uint32_t)src); print_debug_cp_run("dst=",(uint32_t)dst); - olen = unrv2b(src, dst); +// dump_mem(src, src+0x100); + + olen = unrv2b(src, dst, &ilen); + print_debug_cp_run("linxbios_ram.nrv2b length = ", ilen); + #endif +// dump_mem(dst, dst+0x100); print_debug_cp_run("linxbios_ram.bin length = ", olen); @@ -61,3 +65,55 @@ ); } + +#if CONFIG_AP_CODE_IN_CAR == 1 + +static void copy_and_run_ap_code_in_car(unsigned ret_addr) +{ + uint8_t *src, *dst; + unsigned long ilen, olen; + +// print_debug("Copying LinuxBIOS AP code to CAR.\r\n"); + +#if !CONFIG_COMPRESS + __asm__ volatile ( + "leal _liseg_apc, %0\n\t" + "leal _iseg_apc, %1\n\t" + "leal _eiseg_apc, %2\n\t" + "subl %1, %2\n\t" + : "=a" (src), "=b" (dst), "=c" (olen) + ); + memcpy(dst, src, olen); +#else + + __asm__ volatile ( + "leal _liseg_apc, %0\n\t" + "leal _iseg_apc, %1\n\t" + : "=a" (src) , "=b" (dst) + ); + +// print_debug_cp_run("src=",(uint32_t)src); +// print_debug_cp_run("dst=",(uint32_t)dst); + +// dump_mem(src, src+0x100); + + olen = unrv2b(src, dst, &ilen); +// print_debug_cp_run("linxbios_apc.nrv2b length = ", ilen); + +#endif +// dump_mem(dst, dst+0x100); + +// print_debug_cp_run("linxbios_apc.bin length = ", olen); + +// print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n"); + + __asm__ volatile ( + "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */ + "cli\n\t" + "leal _iseg_apc, %%edi\n\t" + "jmp *%%edi\n\t" + :: "a"(ret_addr) + ); + +} +#endif Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -18,12 +18,13 @@ { __asm__ volatile( "cld\n\t" - "rep movsl\n\t" + "rep; movsl\n\t" : /* No outputs */ : "S" (src), "D" (dest), "c" ((bytes)>>2) ); } + static void post_cache_as_ram(void) { @@ -49,24 +50,34 @@ #error "You need to set CONFIG_LB_MEM_TOPK greater than 1024" #endif - set_init_ram_access(); + set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */ +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to ram -- switching to use ram as stack... "); /* from here don't store more data in CAR */ +#if 0 __asm__ volatile ( "pushl %eax\n\t" ); - memcopy((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE, DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline +#endif + + memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline +// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); + __asm__ volatile ( /* set new esp */ /* before _RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp +#if 0 __asm__ volatile ( "popl %eax\n\t" ); +#endif + + /* We can put data to stack again */ /* only global variable sysinfo in cache need to be offset */ @@ -77,14 +88,27 @@ disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); - clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)), that is used as stack in ram + clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) print_debug("Done\r\n"); +// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); + +#ifndef MEM_TRAIN_SEQ +#define MEM_TRAIN_SEQ 0 +#endif + set_sysinfo_in_ram(1); // So other core0 could start to train mem + +#if MEM_TRAIN_SEQ == 1 +// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + + // wait for ap memory to trained +// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c +#endif /*copy and execute linuxbios_ram */ copy_and_run(); /* We will not return */ - print_debug("should not be here -\r\n"); + print_debug("should not be here -\r\n"); } Modified: trunk/LinuxBIOSv2/src/cpu/amd/dualcore/amd_sibling.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/dualcore/amd_sibling.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/dualcore/amd_sibling.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -11,6 +11,7 @@ #include #include #include +#include static int first_time = 1; static int disable_siblings = !CONFIG_LOGICAL_CPUS; @@ -168,7 +169,16 @@ /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8); + if(id.nodeid == 0) { + // need some special processing, because may the bsp is not lifted, but the core1 is lifted + //defined in northbridge.c + if(sysconf.enabled_apic_ext_id && (!sysconf.lift_bsp_apicid)) { + cpu->path.u.apic.apic_id += sysconf.apicid_offset; + } + } + + /* See if I can find the cpu */ new = find_dev_path(cpu->bus, &cpu_path); /* Allocate the new cpu device structure */ Modified: trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -19,7 +19,9 @@ #if SET_NB_CFG_54 == 1 static inline uint8_t set_apicid_cpuid_lo(void) { +#if K8_REV_F_SUPPORT == 0 if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set +#endif // set the NB_CFG[54]=1; why the OS will be happy with that ??? msr_t msr; Modified: trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore_id.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore_id.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/dualcore/dualcore_id.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -20,6 +20,8 @@ } //called by amd_siblings too +#define CORE_ID_BIT 1 +#define NODE_ID_BIT 3 struct node_core_id get_node_core_id(unsigned nb_cfg_54) { struct node_core_id id; @@ -27,15 +29,15 @@ if( nb_cfg_54) { // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] id.coreid = (cpuid_ebx(1) >> 24) & 0xf; - id.nodeid = (id.coreid>>1); - id.coreid &= 1; + id.nodeid = (id.coreid>>CORE_ID_BIT); + id.coreid &= ((1<> 24) & 0xf; - id.coreid = (id.nodeid>>3); - id.nodeid &= 7; + id.coreid = (id.nodeid>>NODE_ID_BIT); + id.nodeid &= ((1<>(48-32)) & 0x3f; - fid_max = (msr.lo>>16) & 0x3f; + fid_max = ((msr.lo>>16) & 0x3f); //max fid +#if FX_SUPPORT + if(fid_max>=((25-4)*2)) { // FX max fid is 5G + fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G + if(fid_max >= ((25-4)*2)) { + fid_max = (10-4)*2; // hard set to 2G + } + } +#endif //set vid to max msr.hi = 1; msr.lo = (vid_max<<8) | (fid_cur); +#if SB_VFSMAF == 1 msr.lo |= (1<<16); // init changes +#endif wrmsr(0xc0010041, msr); +#if SB_VFSMAF == 0 + ldtstop_sb(); +#endif + for(loop=0;loop<100000;loop++){ msr = rdmsr(0xc0010042); @@ -159,8 +179,13 @@ //set target fid msr.hi = (100000/5); msr.lo = (vid_cur<<8) | fid_cur; +#if SB_VFSMAF == 1 msr.lo |= (1<<16); // init changes +#endif wrmsr(0xc0010041, msr); +#if SB_VFSMAF == 0 + ldtstop_sb(); +#endif #if K8_SET_FIDVID_DEBUG == 1 @@ -186,8 +211,13 @@ //set vid to final msr.hi = 1; msr.lo = (vid<<8) | (fid_cur); +#if SB_VFSMAF == 1 msr.lo |= (1<<16); // init changes +#endif wrmsr(0xc0010041, msr); +#if SB_VFSMAF == 0 + ldtstop_sb(); +#endif for(loop=0;loop<100000;loop++){ msr = rdmsr(0xc0010042); @@ -215,10 +245,21 @@ msr_t msr; uint32_t vid_cur; uint32_t fid_cur; + uint32_t fid_max; int loop; msr = rdmsr(0xc0010042); - send = ((msr.lo>>16) & 0x3f) << 8; //max fid + fid_max = ((msr.lo>>16) & 0x3f); //max fid +#if FX_SUPPORT + if(fid_max>=((25-4)*2)) { // FX max fid is 5G + fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G + if(fid_max >= ((25-4)*2)) { + fid_max = (10-4)*2; // hard set to 2G + } + } +#endif + send = fid_max<<8; + send |= ((msr.hi>>(48-32)) & 0x3f) << 16; //max vid send |= (apicid<<24); // ap apicid @@ -342,6 +383,14 @@ msr_t msr; msr = rdmsr(0xc0010042); fid_max = ((msr.lo>>16) & 0x3f); //max fid +#if FX_SUPPORT == 1 + if(fid_max>=((25-4)*2)) { // FX max fid is 5G + fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G + if(fid_max >= ((25-4)*2)) { + fid_max = (10-4)*2; // hard set to 2G + } + } +#endif vid_max = ((msr.hi>>(48-32)) & 0x3f); //max vid fv.common_fidvid = (fid_max<<8)|(vid_max<<16); @@ -366,6 +415,29 @@ #endif +#if 0 + unsigned fid, vid; + // Can we use max only? So we can only set fid in one around, otherwise we need to set that to max after raminit + // set fid vid to DQS training required + fid = (fv.common_fidvid >> 8) & 0x3f; + vid = (fv.common_fidvid >> 16) & 0x3f; + + if(fid>(10-4)*2) { + fid = (10-4)*2; //x10 + } + + if(vid>=0x1f) { + vid+= 4; //unit is 12.5mV + } else { + vid+= 2; //unit is 25mV + } + + fv.common_fidvid = (fid<<8) | (vid<<16); + + print_debug_fv("common_fidvid=", fv.common_fidvid); + +#endif + // set BSP fid and vid print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -1,6 +1,12 @@ //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID #ifndef K8_SET_FIDVID - #define K8_SET_FIDVID 0 + #if K8_REV_F_SUPPORT == 0 + #define K8_SET_FIDVID 0 + #else + // for rev F, need to set FID to max + #define K8_SET_FIDVID 1 + #endif + #endif #ifndef K8_SET_FIDVID_CORE0_ONLY @@ -8,6 +14,43 @@ #define K8_SET_FIDVID_CORE0_ONLY 1 #endif +static inline void print_initcpu8 (const char *strval, unsigned val) +{ +#if CONFIG_USE_INIT + printk_debug("%s%02x\r\n", strval, val); +#else + print_debug(strval); print_debug_hex8(val); print_debug("\r\n"); +#endif +} + +static inline void print_initcpu8_nocr (const char *strval, unsigned val) +{ +#if CONFIG_USE_INIT + printk_debug("%s%02x", strval, val); +#else + print_debug(strval); print_debug_hex8(val); +#endif +} + + +static inline void print_initcpu16 (const char *strval, unsigned val) +{ +#if CONFIG_USE_INIT + printk_debug("%s%04x\r\n", strval, val); +#else + print_debug(strval); print_debug_hex16(val); print_debug("\r\n"); +#endif +} + +static inline void print_initcpu(const char *strval, unsigned val) +{ +#if CONFIG_USE_INIT + printk_debug("%s%08x\r\n", strval, val); +#else + print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); +#endif +} + typedef void (*process_ap_t)(unsigned apicid, void *gp); //core_range = 0 : all cores @@ -44,7 +87,11 @@ j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3); if(nb_cfg_54) { if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation - e0_later_single_core = is_e0_later_in_bsp(i); // single core + #if K8_REV_F_SUPPORT == 0 + e0_later_single_core = is_e0_later_in_bsp(i); // single core + #else + e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 + #endif } if(e0_later_single_core) { j=1; @@ -57,14 +104,17 @@ if(core_range == 2) { jstart = 1; } + else { + jstart = 0; + } if(e0_later_single_core || disable_siblings || (core_range==1)) { jend = 0; } else { jend = siblings; - } - - + } + + for(j=jstart; j<=jend; j++) { ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); @@ -141,10 +191,10 @@ if((readback & 0xff) == state) break; //target cpu is in stage started } } - static void wait_ap_started(unsigned ap_apicid, void *gp ) { wait_cpu_state(ap_apicid, 0x33); // started + print_initcpu8_nocr(" ", ap_apicid); } static void wait_all_aps_started(unsigned bsp_apicid) @@ -152,9 +202,11 @@ for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0); } -static void wait_all_other_cores_started(unsigned bsp_apicid) +static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0 { + print_debug("started ap apicid: "); for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0); + print_debug("\r\n"); } static void allow_all_aps_stop(unsigned bsp_apicid) @@ -162,8 +214,23 @@ lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop } +static void STOP_CAR_AND_CPU(void) +{ + disable_cache_as_ram(); // inline + stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... +} +#if RAMINIT_SYSINFO == 1 +#if MEM_TRAIN_SEQ != 1 +static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) {} +#else +static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); +#endif + +#endif + #if RAMINIT_SYSINFO == 1 + static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo) #else static unsigned init_cpus(unsigned cpu_init_detectedx) @@ -251,14 +318,16 @@ init_fidvid_ap(bsp_apicid, apicid); #endif - // We need to stop the CACHE as RAM for this CPU, really? - wait_cpu_state(bsp_apicid, 0x44); - lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu + // We need to stop the CACHE as RAM for this CPU, really? + wait_cpu_state(bsp_apicid, 0x44); + lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu + set_init_ram_access(); + #if RAMINIT_SYSINFO == 1 + train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU); + #endif - set_init_ram_access(); - disable_cache_as_ram(); // inline - stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... - } + STOP_CAR_AND_CPU(); + } return bsp_apicid; } @@ -281,9 +350,13 @@ unsigned i; unsigned nodes = get_nodes(); - for(i=1;i #include #include +#include #include #include #include @@ -29,6 +30,17 @@ #include +void cpus_ready_for_init(void) +{ +#if MEM_TRAIN_SEQ == 1 + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + // wait for ap memory to trained + wait_all_core0_mem_trained(sysinfox); +#endif +} + + +#if K8_REV_F_SUPPORT == 0 int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -53,7 +65,19 @@ return e0_later; } +#endif +#if K8_REV_F_SUPPORT == 1 +int is_cpu_f0_in_bsp(int nodeid) +{ + uint32_t dword; + device_t dev; + dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3)); + dword = pci_read_config32(dev, 0xfc); + return (dword & 0xfff00) == 0x40f00; +} +#endif + #define MCI_STATUS 0x401 static inline msr_t rdmsr_amd(unsigned index) @@ -265,16 +289,20 @@ startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2; endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000; -#if K8_HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 + #if K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { + #endif uint32_t val; val = pci_read_config32(f1_dev, 0xf0); if(val & 1) { hole_startk = ((val & (0xff<<24)) >> 10); } + #if K8_REV_F_SUPPORT == 0 } + #endif #endif @@ -294,7 +322,7 @@ disable_lapic(); /* Walk through 2M chunks and zero them */ -#if K8_HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */ if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) { for(basek = begink; basek < hole_startk; @@ -336,9 +364,11 @@ printk_debug(" done\n"); } + static inline void k8_errata(void) { msr_t msr; +#if K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Erratum 63... */ msr = rdmsr(HWCR_MSR); @@ -406,8 +436,11 @@ msr.hi |=1; wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr); } +#endif +#if K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) +#endif { /* Erratum 110 ... */ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); @@ -420,9 +453,96 @@ msr.lo |= 1 << 6; wrmsr(HWCR_MSR, msr); +#if K8_REV_F_SUPPORT == 1 + /* Erratum 131... */ + msr = rdmsr(NB_CFG_MSR); + msr.lo |= 1 << 20; + wrmsr(NB_CFG_MSR, msr); +#endif + } +#if K8_REV_F_SUPPORT == 1 +static void amd_set_name_string_f(device_t dev) +{ + unsigned socket; + unsigned cmpCap; + unsigned pwrLmt; + unsigned brandId; + unsigned brandTableIndex; + unsigned nN; + unsigned unknown = 1; + uint8_t str[48]; + uint32_t *p; + + msr_t msr; + unsigned i; + + brandId = cpuid_ebx(0x80000001) & 0xffff; + + printk_debug("brandId=%04x\n", brandId); + pwrLmt = ((brandId>>14) & 1) | ((brandId>>5) & 0x0e); + brandTableIndex = (brandId>>9) & 0x1f; + nN = (brandId & 0x3f) | ((brandId>>(15-6)) &(1<<6)); + + socket = (dev->device >> 4) & 0x3; + + cmpCap = cpuid_ecx(0x80000008) & 0xff; + + + if((brandTableIndex == 0) && (pwrLmt == 0)) { + memset(str, 0, 48); + sprintf(str, "AMD Engineering Sample"); + unknown = 0; + } else { + + memset(str, 0, 48); + sprintf(str, "AMD Processor model unknown"); + + #if CPU_SOCKET_TYPE == 0x10 + if(socket == 0x01) { // socket F + if ((cmpCap == 1) && ((brandTableIndex==0) ||(brandTableIndex ==1) ||(brandTableIndex == 4)) ) { + uint8_t pc[2]; + unknown = 0; + switch (pwrLmt) { + case 2: pc[0]= 'E'; pc[1] = 'E'; break; + case 6: pc[0]= 'H'; pc[1] = 'E'; break; + case 0xa: pc[0]= ' '; pc[1] = ' '; break; + case 0xc: pc[0]= 'S'; pc[1] = 'E'; break; + default: unknown = 1; + + } + if(!unknown) { + memset(str, 0, 48); + sprintf(str, "Dual-Core AMD Opteron(tm) Processor %1d2%2d %c%c", brandTableIndex<<1, (nN-1)&0x3f, pc[0], pc[1]); + } + } + } + #else + #if CPU_SOCKET_TYPE == 0x11 + if(socket == 0x00) { // socket AM2 + if(cmpCap == 0) { + sprintf(str, "Athlon 64"); + } else { + sprintf(str, "Athlon 64 Dual Core"); + } + + } + #endif + #endif + } + + p = str; + for(i=0;i<6;i++) { + msr.lo = *p; p++; msr.hi = *p; p++; + wrmsr(0xc0010030+i, msr); + } + + +} +#endif + extern void model_fxx_update_microcode(unsigned cpu_deviceid); int init_processor_name(void); @@ -435,6 +555,16 @@ unsigned siblings; #endif +#if K8_REV_F_SUPPORT == 1 + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + if((c.x86_model & 0xf0) == 0x40) { + amd_set_name_string_f(dev); + } +#endif + /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); @@ -504,6 +634,7 @@ .init = model_fxx_init, }; static struct cpu_device_id cpu_table[] = { +#if K8_REV_F_SUPPORT == 0 { X86_VENDOR_AMD, 0xf50 }, /* B3 */ { X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */ { X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */ @@ -540,7 +671,26 @@ { X86_VENDOR_AMD, 0x20fc2 }, { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */ { X86_VENDOR_AMD, 0x20f32 }, +#endif +#if K8_REV_F_SUPPORT == 1 +//AMD_F0_SUPPORT + { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 Socket F (1207): Opteron */ + { X86_VENDOR_AMD, 0x40f70 }, /* AM2: Athlon64/Athlon64 FX */ + { X86_VENDOR_AMD, 0x40f40 }, /* S1g1: Mobile Athlon64 */ + { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 Socket F (1207): Opteron Dual Core */ + { X86_VENDOR_AMD, 0x40f31 }, /* AM2: Athlon64 x2/Athlon64 FX Dual Core */ + { X86_VENDOR_AMD, 0x40f01 }, /* S1g1: Mobile Athlon64 */ + { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 Socket F (1207): Opteron Dual Core */ + { X86_VENDOR_AMD, 0x40f32 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */ + { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */ + { X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */ + { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */ + { X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */ + { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */ + { X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */ +#endif + { 0, 0 }, }; static struct cpu_driver model_fxx __cpu_driver = { Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -1,5 +1,5 @@ /* Copyright 2005 AMD - * 2005.08 yhlu add microcode support + * 2005.08 yhlu add microcode support */ /*============================================================================ Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. @@ -52,10 +52,15 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { -#include "microcode_rev_c.h" -#include "microcode_rev_d.h" -#include "microcode_rev_e.h" +#if K8_REV_F_SUPPORT == 0 + #include "microcode_rev_c.h" + #include "microcode_rev_d.h" + #include "microcode_rev_e.h" +#endif +#if K8_REV_F_SUPPORT == 1 +// #include "microcode_rev_f.h" +#endif /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -65,6 +70,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { + #if K8_REV_F_SUPPORT == 0 0x0f48, 0x0048, 0x0f58, 0x0048, @@ -85,7 +91,12 @@ 0x20f12, 0x0210, 0x20f32, 0x0210, 0x20fb1, 0x0210, + #endif + #if K8_REV_F_SUPPORT == 1 + + #endif + }; Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_gx2/vsmsetup.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -254,6 +254,7 @@ unsigned char *buf; unsigned int size = SMM_SIZE*1024; int i; + unsigned long ilen, olen; printk_err("do_vsmbios\n"); /* clear vsm bios data area */ @@ -273,7 +274,8 @@ rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024); buf = (unsigned char *) 0x60000; - unrv2b((uint8_t *)rom, buf); + olen = unrv2b((uint8_t *)rom, buf, &ilen); + printk_debug("buf ilen %d olen%d\n", ilen, olen); printk_debug("buf %p *buf %d buf[256k] %d\n", buf, buf[0], buf[SMM_SIZE*1024]); printk_debug("buf[0x20] signature is %x:%x:%x:%x\n", Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -295,6 +295,7 @@ unsigned char *buf; unsigned int size = SMM_SIZE*1024; int i; + unsigned long ilen, olen; printk_err("do_vsmbios\n"); /* clear vsm bios data area */ @@ -316,7 +317,8 @@ rom = 0xfffc8000; buf = (unsigned char *) VSA2_BUFFER; - unrv2b((uint8_t *)rom, buf); + olen = unrv2b((uint8_t *)rom, buf, &ilen); + printk_debug("buf ilen %d olen%d\n", ilen, olen); printk_debug("buf %p *buf %d buf[256k] %d\n", buf, buf[0], buf[SMM_SIZE*1024]); printk_debug("buf[0x20] signature is %x:%x:%x:%x\n", Modified: trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_earlymtrr.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_earlymtrr.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_earlymtrr.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -15,7 +15,6 @@ */ msr_t msr; const unsigned long *msr_addr; - unsigned long cr0; #if 0 /* Enable the access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); Modified: trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_mtrr.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_mtrr.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/amd/mtrr/amd_mtrr.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -149,7 +149,7 @@ msr.lo = state.mmio_basek << 10; wrmsr(TOP_MEM, msr); - if(state.tomk>(4*1024*1024)) { + if(state.tomk > (4*1024*1024)) { /* Setup TOP_MEM2 */ msr.hi = state.tomk >> 22; msr.lo = state.tomk << 10; @@ -180,7 +180,7 @@ /* FIXME we should probably query the cpu for this * but so far this is all any recent AMD cpu has supported. */ - address_bits = 40; + address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,19 @@ +uses CONFIG_CHIP_NAME +uses K8_REV_F_SUPPORT +uses K8_HT_FREQ_1G_SUPPORT +uses DIMM_SUPPORT +uses CPU_SOCKET_TYPE + +if CONFIG_CHIP_NAME + config chip.h +end + +default K8_REV_F_SUPPORT=1 +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 +default DIMM_SUPPORT=0x0004 #DDR2 unbuffered +default CPU_SOCKET_TYPE=0x11 + +object socket_AM2.o + +dir /cpu/amd/model_fxx Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/chip.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_amd_socket_AM2_ops; + +struct cpu_amd_socket_AM2_config { +}; Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/socket_AM2.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/socket_AM2.c (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_AM2/socket_AM2.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,6 @@ +#include +#include "chip.h" + +struct chip_operations cpu_amd_socket_AM2_ops = { + CHIP_NAME("socket AM2") +}; Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_F/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_F/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_F/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,19 @@ +uses CONFIG_CHIP_NAME +uses K8_REV_F_SUPPORT +uses K8_HT_FREQ_1G_SUPPORT +uses DIMM_SUPPORT +uses CPU_SOCKET_TYPE + +if CONFIG_CHIP_NAME + config chip.h +end + +default K8_REV_F_SUPPORT=1 +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 +default DIMM_SUPPORT=0x0104 #DDR2 and REG +default CPU_SOCKET_TYPE=0x10 + +object socket_F.o + +dir /cpu/amd/model_fxx Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_F/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_F/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_F/chip.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_amd_socket_F_ops; + +struct cpu_amd_socket_F_config { +}; Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_F/socket_F.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_F/socket_F.c (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_F/socket_F.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,6 @@ +#include +#include "chip.h" + +struct chip_operations cpu_amd_socket_F_ops = { + CHIP_NAME("socket F") +}; Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/copy_and_run.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/x86/car/copy_and_run.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/x86/car/copy_and_run.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -44,7 +44,7 @@ // dump_mem(src, src+0x100); - olen=unrv2b(src, dst); + olen = unrv2b(src, dst, &ilen); #endif // dump_mem(dst, dst+0x100); Modified: trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -55,7 +55,7 @@ LAPIC_DELIVERY_MODE_NMI) ); - printk_debug(" apic_id: %d ", lapicid()); + printk_debug(" apic_id: 0x%02x ", lapicid()); #else /* !NEED_LLAPIC */ /* Only Pentium Pro and later have those MSR stuff */ Modified: trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic_cpu_init.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic_cpu_init.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -322,7 +322,7 @@ if (!start_cpu(cpu)) { /* Record the error in cpu? */ - printk_err("CPU %u would not start!\n", + printk_err("CPU 0x%02x would not start!\n", cpu->path.u.apic.apic_id); } #if SERIAL_CPU_INIT == 1 @@ -354,7 +354,7 @@ continue; } if (!cpu->initialized) { - printk_err("CPU %u did not initialize!\n", + printk_err("CPU 0x%02x did not initialize!\n", cpu->path.u.apic.apic_id); #warning "FIXME do I need a mainboard_cpu_fixup function?" } @@ -366,6 +366,10 @@ #define initialize_other_cpus(root) do {} while(0) #endif /* CONFIG_SMP */ +#if WAIT_BEFORE_CPUS_INIT==0 + #define cpus_ready_for_init() do {} while(0) +#endif + void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; @@ -394,6 +398,8 @@ copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif + cpus_ready_for_init(); + #if CONFIG_SMP == 1 #if SERIAL_CPU_INIT == 0 /* start all aps at first, so we can init ECC all together */ @@ -407,7 +413,6 @@ #if CONFIG_SMP == 1 #if SERIAL_CPU_INIT == 1 - /* start all aps */ start_other_cpus(cpu_bus, info->cpu); #endif Modified: trunk/LinuxBIOSv2/src/cpu/x86/mtrr/earlymtrr.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/x86/mtrr/earlymtrr.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/x86/mtrr/earlymtrr.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -47,10 +47,29 @@ basem.hi = 0; wrmsr(MTRRphysBase_MSR(reg), basem); maskm.lo = ~(size - 1) | 0x800; - maskm.hi = 0x0f; + maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; wrmsr(MTRRphysMask_MSR(reg), maskm); } +static void set_var_mtrr_x( + unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type) + +{ + /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ + msr_t basem, maskm; + basem.lo = (base_lo & 0xfffff000) | type; + basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1); + wrmsr(MTRRphysBase_MSR(reg), basem); + maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; + if(size_lo) { + maskm.lo = ~(size_lo - 1) | 0x800; + } else { + maskm.lo = 0x800; + maskm.hi &= ~(size_hi - 1); + } + wrmsr(MTRRphysMask_MSR(reg), maskm); +} + static void cache_lbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ @@ -70,7 +89,6 @@ */ msr_t msr; const unsigned long *msr_addr; - unsigned long cr0; /* Inialize all of the relevant msrs to 0 */ msr.lo = 0; Modified: trunk/LinuxBIOSv2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/x86/mtrr/mtrr.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/cpu/x86/mtrr/mtrr.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -70,6 +70,25 @@ msr_t base, mask; unsigned address_mask_high; + if (reg >= 8) + return; + + // it is recommended that we disable and enable cache when we + // do this. + if (sizek == 0) { + disable_cache(); + + msr_t zero; + zero.lo = zero.hi = 0; + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR(reg), zero); + + enable_cache(); + return; + } + + address_mask_high = ((1u << (address_bits - 32u)) - 1u); base.hi = basek >> 22; @@ -86,25 +105,16 @@ mask.lo = 0; } - if (reg >= 8) - return; - // it is recommended that we disable and enable cache when we // do this. disable_cache(); - if (sizek == 0) { - msr_t zero; - zero.lo = zero.hi = 0; - /* The invalid bit is kept in the mask, so we simply clear the - relevant mask register to disable a range. */ - wrmsr (MTRRphysMask_MSR(reg), zero); - } else { - /* Bit 32-35 of MTRRphysMask should be set to 1 */ - base.lo |= type; - mask.lo |= 0x800; - wrmsr (MTRRphysBase_MSR(reg), base); - wrmsr (MTRRphysMask_MSR(reg), mask); - } + + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + base.lo |= type; + mask.lo |= 0x800; + wrmsr (MTRRphysBase_MSR(reg), base); + wrmsr (MTRRphysMask_MSR(reg), mask); + enable_cache(); } Modified: trunk/LinuxBIOSv2/src/devices/device_util.c =================================================================== --- trunk/LinuxBIOSv2/src/devices/device_util.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/devices/device_util.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -430,7 +430,7 @@ end = resource_end(resource); buf[0] = '\0'; if (resource->flags & IORESOURCE_PCI_BRIDGE) { - sprintf(buf, "bus %d ", dev->link[0].secondary); + sprintf(buf, "bus %02x ", dev->link[0].secondary); } printk_debug( "%s %02x <- [0x%010Lx - 0x%010Lx] %s%s%s\n", Modified: trunk/LinuxBIOSv2/src/devices/hypertransport.c =================================================================== --- trunk/LinuxBIOSv2/src/devices/hypertransport.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/devices/hypertransport.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -3,7 +3,6 @@ */ - #include #include #include @@ -78,9 +77,11 @@ /* AMD K8 Unsupported 1Ghz? */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { #if K8_HT_FREQ_1G_SUPPORT == 1 + #if K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT freq_cap &= ~(1 << HT_FREQ_1000Mhz); } + #endif #else freq_cap &= ~(1 << HT_FREQ_1000Mhz); #endif @@ -450,8 +451,8 @@ } flags &= ~0x1f; /* mask out base Unit ID */ - flags |= next_unitid & 0x1f; - pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags); + flags |= next_unitid & 0x1f; + pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags); /* Update the Unitd id in the device structure */ static_count = 1; @@ -490,7 +491,6 @@ dev->vendor, dev->device, (dev->enabled? "enabled": "disabled"), next_unitid); - } while((last_unitid != next_unitid) && (next_unitid <= (max_devfn >> 3))); end_of_chain: #if OPT_HT_LINK == 1 @@ -560,9 +560,17 @@ * * @return The maximum bus number found, after scanning all subordinate busses */ +unsigned int hypertransport_scan_chain_x(struct bus *bus, + unsigned min_devfn, unsigned max_devfn, unsigned int max) +{ + unsigned ht_unitid_base[4]; + unsigned offset_unitid = 1; + return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid); +} + unsigned int ht_scan_bridge(struct device *dev, unsigned int max) { - return do_pci_scan_bridge(dev, max, hypertransport_scan_chain); + return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x); } Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/microcode.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/amd/microcode.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/include/cpu/amd/microcode.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -2,4 +2,5 @@ #define CPU_AMD_MICORCODE_H void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); -#endif /* CPU_AMD_MICROCODE_H */ \ No newline at end of file +#endif /* CPU_AMD_MICROCODE_H */ + Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/model_fxx_rev.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/amd/model_fxx_rev.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/include/cpu/amd/model_fxx_rev.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -1,5 +1,6 @@ #include +#if K8_REV_F_SUPPORT == 0 static inline int is_cpu_rev_a0(void) { return (cpuid_eax(1) & 0xfffef) == 0x0f00; @@ -74,5 +75,46 @@ int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c #endif +#endif +#if K8_REV_F_SUPPORT == 1 +//AMD_F0_SUPPORT +static inline int is_cpu_pre_f0(void) +{ + return (cpuid_eax(1) & 0xfff0f) < 0x40f00; +} +static inline int is_cpu_f0(void) +{ + return (cpuid_eax(1) & 0xfff00) == 0x40f00; +} + +static inline int is_cpu_pre_f2(void) +{ + return (cpuid_eax(1) & 0xfff0f) < 0x40f02; +} + +#ifdef __ROMCC__ +//AMD_F0_SUPPORT +static int is_cpu_f0_in_bsp(int nodeid) +{ + uint32_t dword; + device_t dev; + dev = PCI_DEV(0, 0x18+nodeid, 3); + dword = pci_read_config32(dev, 0xfc); + return (dword & 0xfff00) == 0x40f00; +} +static int is_cpu_pre_f2_in_bsp(int nodeid) +{ + uint32_t dword; + device_t dev; + dev = PCI_DEV(0, 0x18+nodeid, 3); + dword = pci_read_config32(dev, 0xfc); + return (dword & 0xfff0f) < 0x40f02; +} +#else +int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c +#endif + +#endif + Modified: trunk/LinuxBIOSv2/src/include/cpu/x86/mem.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/x86/mem.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/include/cpu/x86/mem.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -6,7 +6,7 @@ { asm volatile( "cld \n\t" - "rep stosl\n\t" + "rep; stosl\n\t" : /* No outputs */ : "a" (0), "D" (addr), "c" (size>>2) ); Modified: trunk/LinuxBIOSv2/src/include/device/device.h =================================================================== --- trunk/LinuxBIOSv2/src/include/device/device.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/include/device/device.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -48,14 +48,14 @@ device_t children; /* devices behind this bridge */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link; /* The index of this link */ - unsigned char secondary; /* secondary bus number */ - unsigned char subordinate; /* max subordinate bus number */ + uint16_t secondary; /* secondary bus number */ + uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; }; -#define MAX_RESOURCES 12 +#define MAX_RESOURCES 12 #define MAX_LINKS 8 /* * There is one device structure for each slot-number/function-number Modified: trunk/LinuxBIOSv2/src/include/device/hypertransport_def.h =================================================================== --- trunk/LinuxBIOSv2/src/include/device/hypertransport_def.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/include/device/hypertransport_def.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -11,6 +11,11 @@ #define HT_FREQ_1200Mhz 7 #define HT_FREQ_1400Mhz 8 #define HT_FREQ_1600Mhz 9 +#define HT_FREQ_1800Mhz 10 +#define HT_FREQ_2000Mhz 11 +#define HT_FREQ_2200Mhz 12 +#define HT_FREQ_2400Mhz 13 +#define HT_FREQ_2600Mhz 14 #define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ #endif /* DEVICE_HYPERTRANSPORT_DEF_H */ Modified: trunk/LinuxBIOSv2/src/include/device/pci.h =================================================================== --- trunk/LinuxBIOSv2/src/include/device/pci.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/include/device/pci.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -29,12 +29,12 @@ /* Common pci bus operations */ struct pci_bus_operations { - uint8_t (*read8) (struct bus *pbus, unsigned char bus, int devfn, int where); - uint16_t (*read16) (struct bus *pbus, unsigned char bus, int devfn, int where); - uint32_t (*read32) (struct bus *pbus, unsigned char bus, int devfn, int where); - void (*write8) (struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t val); - void (*write16) (struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t val); - void (*write32) (struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t val); + uint8_t (*read8) (struct bus *pbus, int bus, int devfn, int where); + uint16_t (*read16) (struct bus *pbus, int bus, int devfn, int where); + uint32_t (*read32) (struct bus *pbus, int bus, int devfn, int where); + void (*write8) (struct bus *pbus, int bus, int devfn, int where, uint8_t val); + void (*write16) (struct bus *pbus, int bus, int devfn, int where, uint16_t val); + void (*write32) (struct bus *pbus, int bus, int devfn, int where, uint32_t val); }; struct pci_driver { Modified: trunk/LinuxBIOSv2/src/include/device/pci_def.h =================================================================== --- trunk/LinuxBIOSv2/src/include/device/pci_def.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/include/device/pci_def.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -201,6 +201,7 @@ #define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */ #define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */ #define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */ +#define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */ /* Power Management Registers */ Modified: trunk/LinuxBIOSv2/src/lib/nrv2b.c =================================================================== --- trunk/LinuxBIOSv2/src/lib/nrv2b.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/lib/nrv2b.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -28,18 +28,13 @@ #if ENDIAN == 0 && BITSIZE == 32 #define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen) #endif - -static unsigned long unrv2b(uint8_t * src, uint8_t * dst) +static unsigned long unrv2b(uint8_t * src, uint8_t * dst, unsigned long *ilen_p) { unsigned long ilen = 0, olen = 0, last_m_off = 1; uint32_t bb = 0; unsigned bc = 0; const uint8_t *m_pos; -// unsigned long file_len = *(unsigned long *) src; - // we only have printk_debug in copy_and_run.c if CONFIG_USE_INIT is - // not set, so comment it out. - // printk_debug("compressed file len is supposed to be %d bytes\n", file_len); // skip length src += 4; /* FIXME: check olen with the length stored in first 4 bytes */ @@ -81,9 +76,8 @@ } while (--m_len > 0); } - // we only have printk_debug in copy_and_run.c if CONFIG_USE_INIT is - // not set, so comment it out. - //printk_debug("computed len is %d, file len is %d\n", olen, file_len); + *ilen_p = ilen; + return olen; } Modified: trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -11,7 +11,6 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -23,7 +22,6 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -126,8 +124,10 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" #include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" #define FIRST_CPU 1 #define SECOND_CPU 1 Modified: trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8S2/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8S2/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8S2/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -11,7 +11,6 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -23,7 +22,6 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -126,8 +124,10 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" #define FIRST_CPU 1 #define SECOND_CPU 1 Modified: trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8X/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8X/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8X/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -11,7 +11,6 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -24,7 +23,6 @@ #include "superio/NSC/pc87360/pc87360_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) @@ -128,8 +126,10 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" #define FIRST_CPU 1 #define SECOND_CPU 1 Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -138,7 +138,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcc000 default DCACHE_RAM_SIZE=0x4000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serenade/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serenade/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serenade/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -13,7 +13,6 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -25,7 +24,6 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -128,8 +126,10 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" #include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" #define FIRST_CPU 1 #define SECOND_CPU 1 Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,406 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FAILOVER_IMAGE + default ROM_SECTION_SIZE = FAILOVER_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) +else + if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + default ROM_SECTION_OFFSET = 0 + end +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 + +if USE_FAILOVER_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +else + if USE_FALLBACK_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + else + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + end +end + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#dir /drivers/si/3114 + +#needed by irq_tables and mptable and acpi_tables +object get_bus_conf.o + +if HAVE_MP_TABLE + object mptable.o +end + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +#if HAVE_ACPI_TABLES +# object acpi_tables.o +# object fadt.o +# if SB_HT_CHAIN_ON_BUS0 +# object dsdt_bus0.o +# else +# object dsdt.o +# end +# object ssdt.o +# if ACPI_SSDTX_NUM +# if SB_HT_CHAIN_ON_BUS0 +# object ssdt2_bus0.o +# else +# object ssdt2.o +# end +# end +#end + +if HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + makerule dsdt.c + depends "$(MAINBOARD)/dx/dsdt_lb.dsl" + action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "mv dsdt_lb.hex dsdt.c" + end + object ./dsdt.o + + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + + if ACPI_SSDTX_NUM + makerule ssdt2.c + depends "$(MAINBOARD)/dx/pci2.asl" + action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" + action "mv pci2.hex ssdt2.c" + end + object ./ssdt2.o + end +end + +if USE_DCACHE_RAM + + if CONFIG_USE_INIT + # compile cache_as_ram.c to auto.o + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + end + + else + #compile cache_as_ram.c to auto.inc + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end + + end +end + +if USE_FAILOVER_IMAGE +else + if CONFIG_AP_CODE_IN_CAR + makerule ./apc_auto.o + depends "$(MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + end + ldscript /arch/i386/init/ldscript_apc.lb + end +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## + +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +end + +mainboardinit cpu/x86/32bit/entry32.inc +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +end + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +if USE_DCACHE_RAM + ## + ## Setup Cache-As-Ram + ## + mainboardinit cpu/amd/car/cache_as_ram.inc +end + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover_failover.lds + end + end +else + if USE_FALLBACK_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds + end + end +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +if USE_DCACHE_RAM + + if CONFIG_USE_INIT + initobject cache_as_ram_auto.o + else + mainboardinit ./cache_as_ram_auto.inc + end + +end + +## +## Include the secondary Configuration files +## +if CONFIG_CHIP_NAME + config chip.h +end + +# sample config for amd/serengeti_cheetah +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-2-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-2-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-3-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-3-1 + device i2c 57 on end + end + end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + + + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end + + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,329 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses HAVE_ACPI_TABLES +uses ACPI_SSDTX_NUM +uses USE_FALLBACK_IMAGE +uses USE_FAILOVER_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_FAILOVER_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses FAILOVER_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses CONFIG_COMPRESSED_ROM_STREAM +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses _RAMBASE +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZE_AUTO_INC +uses K8_HT_FREQ_1G_SUPPORT + +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_INIT + +uses SERIAL_CPU_INIT + +uses ENABLE_APIC_EXT_ID +uses APIC_ID_OFFSET +uses LIFT_BSP_APIC_ID + +uses CONFIG_PCI_64BIT_PREF_MEM + +uses CONFIG_LB_MEM_TOPK + +uses CONFIG_AP_CODE_IN_CAR + +uses MEM_TRAIN_SEQ + +uses WAIT_BEFORE_CPUS_INIT + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=524288 + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +#default FALLBACK_SIZE=131072 +#default FALLBACK_SIZE=0x40000 + +#FALLBACK: 256K-4K +default FALLBACK_SIZE=0x3f000 +#FAILOVER: 4K +default FAILOVER_SIZE=0x01000 + +#more 1M for pgtbl +default CONFIG_LB_MEM_TOPK=2048 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 +default HAVE_FAILOVER_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=11 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## ACPI tables will be included +default HAVE_ACPI_TABLES=1 +## extra SSDT num +default ACPI_SSDTX_NUM=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=8 +default CONFIG_MAX_PHYSICAL_CPUS=4 +default CONFIG_LOGICAL_CPUS=1 + +default SERIAL_CPU_INIT=0 + +default ENABLE_APIC_EXT_ID=0 +default APIC_ID_OFFSET=0x8 +default LIFT_BSP_APIC_ID=1 + +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 + +#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. +#2G +#default HW_MEM_HOLE_SIZEK=0x200000 +#1G +default HW_MEM_HOLE_SIZEK=0x100000 +#512M +#default HW_MEM_HOLE_SIZEK=0x80000 + +#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy +#default HW_MEM_HOLE_SIZE_AUTO_INC=1 + +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +#HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0xa + +#real SB Unit ID, default is 0x20, mean dont touch it at last +default HT_CHAIN_END_UNITID_BASE=0x6 + +#make the SB HT chain on bus 0, default is not (0) +default SB_HT_CHAIN_ON_BUS0=2 + +#only offset for SB chain?, default is yes(1) +#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + +#allow capable device use that above 4G +#default CONFIG_PCI_64BIT_PREF_MEM=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x08000 +default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_INIT=0 + +default CONFIG_AP_CODE_IN_CAR=1 +default MEM_TRAIN_SEQ=1 + +default WAIT_BEFORE_CPUS_INIT=1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="serengeti_cheetah" +default MAINBOARD_VENDOR="AMD" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00100000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM = 1 + +#default CONFIG_COMPRESSED_ROM_STREAM = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc-3.4.5 -m32" +default HOSTCC="gcc-3.4.5" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +### End Options.lb +end Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,25 @@ +echo "Creating for ACPI hex for bus 1 Conf" +cd dx +iasl -tc dsdt_lb.dsl +rm DSDT.aml +mv dsdt_lb.hex ../dsdt.c +iasl -tc pci2.asl +rm SSDT2.aml +perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex +mv pci2.hex ../ssdt2.c +cd .. +echo "Creating for ACPI hex for bus 0 Conf" +cd dx_bus0 +iasl -tc dsdt_lb.dsl +rm DSDT.aml +mv dsdt_lb.hex ../dsdt_bus0.c +iasl -tc pci2.asl +rm SSDT2.aml +perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex +mv pci2.hex ../ssdt2_bus0.c +cd .. +echo "Creating ssdt" +iasl -tc ssdt_lb_x.dsl +rm SSDT.aml +perl -e 's/AmlCode/AmlCode_ssdt/g' -pi ssdt_lb_x.hex +mv ssdt_lb_x.hex ssdt.c Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,268 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mb_sysconf.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(unsigned start, unsigned end) +{ + + unsigned i; + print_debug("dump_mem:"); + for(i=start;i= 1 +extern unsigned char AmlCode_ssdt2[]; +//extern unsigned char AmlCode_ssdt3[]; +//extern unsigned char AmlCode_ssdt4[]; +//extern unsigned char AmlCode_ssdt5[]; +//extern unsigned char AmlCode_ssdt6[]; +//extern unsigned char AmlCode_ssdt7[]; +//extern unsigned char AmlCode_ssdt8[]; +#endif + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base=0x18; + + struct mb_sysconf_t *m; + + m = sysconf.mb; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write 8111 IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, + IO_APIC_ADDR, 0); + + /* Write all 8131 IOAPICs */ + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, + res->base, gsi_base ); + gsi_base+=7; + + } + } + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, + res->base, gsi_base ); + gsi_base+=7; + } + } + } + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 0, 0, 2, 5 ); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high*/ + + + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + /* 1: LINT1 connect to NMI */ + + + return current; +} + +extern void get_bus_conf(void); + +extern void update_ssdt(void *ssdt); + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *ssdtx; + + unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM]; + + int i; + + get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + + /* Align ACPI tables to 16byte */ + start = ( start + 0x0f ) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk_debug("ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt,hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + acpi_add_table(rsdt,madt); + + + /* SRAT */ + printk_debug("ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current+=srat->header.length; + acpi_add_table(rsdt,srat); + + /* SLIT */ + printk_debug("ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + printk_debug("ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode_ssdt)->length; + memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length); + //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c + update_ssdt((void*)ssdt); + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + acpi_add_table(rsdt,ssdt); + +#if ACPI_SSDTX_NUM >= 1 + // we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1] + AmlCode_ssdtx[1] = AmlCode_ssdt2; +// AmlCode_ssdtx[2] = AmlCode_ssdt3; +// AmlCode_ssdtx[3] = AmlCode_ssdt4; +// AmlCode_ssdtx[4] = AmlCode_ssdt5; +// AmlCode_ssdtx[5] = AmlCode_ssdt6; +// AmlCode_ssdtx[6] = AmlCode_ssdt7; +// AmlCode_ssdtx[7] = AmlCode_ssdt8; + + //same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table + + for(i=1;ilength; + memcpy((void *)ssdtx, (void *)AmlCode_ssdtx[i], ((acpi_header_t *)AmlCode_ssdtx[i])->length); + acpi_add_table(rsdt,ssdtx); + } +#endif + + + /* FACS */ + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk_debug("ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode)->length; + memcpy((void *)dsdt,(void *)AmlCode, \ + ((acpi_header_t *)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + + /* FDAT */ + printk_debug("ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdt,fadt); + +#if DUMP_ACPI_TABLES == 1 + printk_debug("rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk_debug("rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk_debug("madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk_debug("srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk_debug("slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk_debug("ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk_debug("fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk_info("ACPI: done.\n"); + return current; +} + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,108 @@ +#define ASSEMBLY 1 +#define __ROMCC__ + +#define RAMINIT_SYSINFO 1 +#define CACHE_AS_RAM_ADDRESS_DEBUG 0 + +#define SET_NB_CFG_54 1 + +//used by raminit +#define QRANK_DIMM_SUPPORT 1 + +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 + +#include +#include +#include +#include +#include +#include +#include +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" + +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" + +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 + #include "lib/memcpy.c" +#endif + + +//#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +#include "northbridge/amd/amdk8/debug.c" + +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" + +#include "northbridge/amd/amdk8/amdk8_f.h" + +#include "cpu/x86/mtrr.h" +#include "cpu/amd/mtrr.h" +#include "cpu/x86/tsc.h" + +#include "northbridge/amd/amdk8/amdk8_f_pci.c" +#include "northbridge/amd/amdk8/raminit_f_dqs.c" + +#include "cpu/amd/dualcore/dualcore.c" + +void hardwaremain(int ret_addr) +{ + struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + + struct node_core_id id; + + id = get_node_core_id_x(); + + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + + train_ram(id.nodeid, sysinfo, sysinfox); + + /* + go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp + */ + + __asm__ volatile ( + "movl %0, %%edi\n\t" + "jmp *%%edi\n\t" + :: "a"(ret_addr) + ); + + + +} +struct eregs { + uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi; + uint32_t vector; + uint32_t error_code; + uint32_t eip; + uint32_t cs; + uint32_t eflags; +}; + +void x86_exception(struct eregs *info) +{ + do { + hlt(); + } while(1); +} + + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,5 @@ +rm dsdt.c +rm ssdt2.c +rm dsdt_bus0.c +rm ssdt2_bus0.c +rm ssdt.c Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,395 @@ +#define ASSEMBLY 1 +#define __ROMCC__ + +#define RAMINIT_SYSINFO 1 +#define CACHE_AS_RAM_ADDRESS_DEBUG 0 + +#define SET_NB_CFG_54 1 + +//used by raminit +#define QRANK_DIMM_SUPPORT 1 + +//used by incoherent_ht +//#define K8_SCAN_PCI_BUS 1 +//#define K8_ALLOCATE_IO_RANGE 1 + + +//used by init_cpus and fidvid +#define K8_SET_FIDVID 1 +//if we want to wait for core1 done before DQS training, set it to 0 +#define K8_SET_FIDVID_CORE0_ONLY 1 + +//0: three for in bsp, only this one support F0_F1 workaround +//1: on every core0 +//2: one for on bsp +//#define MEM_TRAIN_SEQ 1 + +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 + +#include +#include +#include +#include +#include +#include +#include +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" + +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif +#if USE_FAILOVER_IMAGE==0 +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#endif + + + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "cpu/x86/bist.h" + +#if USE_FAILOVER_IMAGE==0 + +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 + #include "lib/memcpy.c" +#endif +#include "northbridge/amd/amdk8/debug.c" +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" + +static void memreset_setup(void) +{ + //GPIO on amd8111 to enable MEMRST ???? + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +#define SMBUS_HUB 0x18 + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret!=0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); +} +#if 0 +static inline void change_i2c_mux(unsigned device) +{ +#define SMBUS_HUB 0x18 + int ret, i; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + } while ((ret!=0) && (i-->0)); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); +} +#endif + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/amdk8_f.h" +#include "northbridge/amd/amdk8/coherent_ht.c" + +#include "northbridge/amd/amdk8/incoherent_ht.c" + +#include "northbridge/amd/amdk8/raminit_f.c" + +#include "sdram/generic_sdram.c" + + /* tyan does not want the default */ +#include "resourcemap.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#define RC0 ((1<<0)<<8) +#define RC1 ((1<<1)<<8) +#define RC2 ((1<<2)<<8) +#define RC3 ((1<<3)<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57 + + +#include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + +#include "cpu/amd/model_fxx/fidvid.c" +#endif + +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) + +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ); + + fallback_image: +#if HAVE_FAILOVER_BOOT==1 + __asm__ volatile ("jmp __fallback_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ) +#endif + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ +#if HAVE_FAILOVER_BOOT==1 + #if USE_FAILOVER_IMAGE==1 + failover_process(bist, cpu_init_detectedx); + #else + real_main(bist, cpu_init_detectedx); + #endif +#else + #if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); + #endif + real_main(bist, cpu_init_detectedx); +#endif +} + +#if USE_FAILOVER_IMAGE==0 + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + //first node + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + // third node + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + // four node + RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, + RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, +#endif + + }; + + struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + + int needs_reset; int i; + unsigned bsp_apicid = 0; + + if (bist == 0) { + //It's the time to set ctrl in sysinfo now; + fill_mem_ctrl(CONFIG_MAX_PHYSICAL_CPUS, sysinfo->ctrl, spd_addr); + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); + + setup_serengeti_cheetah_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + +#if MEM_TRAIN_SEQ == 1 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram +#endif + setup_coherent_ht_domain(); // routing table and start other core0 + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + +#if 0 + //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); +#endif + +#if K8_SET_FIDVID == 1 + + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + + } + + enable_fid_change(); + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + init_fidvid_bsp(bsp_apicid); + + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + + } +#endif + +#if 1 + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } +#endif + allow_all_aps_stop(bsp_apicid); + +#if 0 + //It's the time to set ctrl in sysinfo now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); +#endif + + enable_smbus(); + +#if 0 + for(i=0;i<4;i++) { + activate_spd_rom(&cpu[i]); + dump_smbus_registers(); + } +#endif + +#if 0 + for(i=1;i<256;i<<=1) { + change_i2c_mux(i); + dump_smbus_registers(); + } +#endif + + memreset_setup(); + + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID + + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + +#if 0 + print_pci_devices(); +#endif + +#if 0 +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); + dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); +#endif + + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + +} +#endif Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/chip.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,6 @@ +extern struct chip_operations mainboard_amd_serengeti_cheetah_ops; + +struct mainboard_amd_serengeti_cheetah_config { +// int fixup_scsi; +// int fixup_vga; +}; Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cmos.layout (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,172 @@ +/* + * Copyright 2005 AMD + */ +//AMD8111 + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} + }) + + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0) + // Update the Device Number according to SBDN + Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) + + Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { + Return (PICM) + } + Else { + Return (APIC) + } + } + + Device (SBC3) + { + /* acpi smbus it should be 0x00040003 if 8131 present */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00010003)) + } + OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) + Field (PIRQ, ByteAcc, Lock, Preserve) + { + PIBA, 8, + PIDC, 8 + } +/* + OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) + Field (TS3_, DWordAcc, NoLock, Preserve) + { + PTS3, 16 + } +*/ + } + + Device (HPET) + { + Name (HPT, 0x00) + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + Return (BUF0) + } + } + + Include ("amd8111_pic.asl") + + Include ("amd8111_isa.asl") + + Device (TP2P) + { + /* 8111 P2P and it should 0x00030000 when 8131 present*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) } + Else { Return (Package (0x02) { 0x08, 0x01 }) } + } + + Device (USB0) + { + Name (_ADR, 0x00000000) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Device (USB1) + { + Name (_ADR, 0x00000001) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Name (APIC, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4 + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3 + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } + }) + + Name (PICM, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4 + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3 + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } + }) + + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_isa.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_isa.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_isa.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,176 @@ +/* + * Copyright 2005 AMD + */ +//AMD8111 isa + + Device (ISA) + { + /* lpc 0x00040000 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) + } + + OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers + Field (PIRY, ByteAcc, NoLock, Preserve) + { + Z000, 2, // Parallel Port Range + , 1, + ECP, 1, // ECP Enable + FDC1, 1, // Floppy Drive Controller 1 + FDC2, 1, // Floppy Drive Controller 2 + Offset (0x01), + Z001, 3, // Serial Port A Range + SAEN, 1, // Serial Post A Enabled + Z002, 3, // Serial Port B Range + SBEN, 1 // Serial Post B Enabled + } + + Device (PIC) + { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) + IRQ (Edge, ActiveHigh, Exclusive) {2} + }) + } + + Device (DMA1) + { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer16) {4} + }) + } + + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) + IRQ (Edge, ActiveHigh, Exclusive) {0} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) + IRQ (Edge, ActiveHigh, Exclusive) {8} + }) + } + + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) + }) + } + + Device (COPR) + { + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) + IRQ (Edge, ActiveHigh, Exclusive) {13} + }) + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x00) + Name (SYR1, ResourceTemplate () + { + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) + IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) + IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + }) + Method (_CRS, 0, NotSerialized) + { + Return (SYR1) + } + } + + Device (MEM) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF + Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404 + Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM + Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + }) + // Read the Video Memory length + CreateDWordField (BUF0, 0x14, CLEN) + CreateDWordField (BUF0, 0x10, CBAS) + + ShiftLeft (VGA1, 0x09, Local0) + Store (Local0, CLEN) + + Return (BUF0) + } + } + + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Method (_STA, 0, NotSerialized) + { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { Return (0x0F) } + Else { Return (0x00) } + } + } + + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + Include ("superio.asl") + + } + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_pic.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_pic.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8111_pic.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,360 @@ +/* + * Copyright 2005 AMD + */ +//AMD8111 pic LNKA B C D + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { // Routing enable + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) + Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) + ShiftLeft (Local1, 0x04, Local1) + Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) + Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + Method (_STA, 0, NotSerialized) + { + And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) + ShiftLeft (Local1, 0x04, Local1) + Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) + } + } + + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,119 @@ +/* + * Copyright 2005 AMD + */ + + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x14) + { + // Slot A - PIRQ BCDA + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, + + //Cypress Slot A - PIRQ BCDA + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, + + //Cypress Slot B - PIRQ CDAB + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, + + //Cypress Slot C - PIRQ DABC + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, + + //Cypress Slot D - PIRQ ABCD + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } + }) + Name (PICM, Package (0x14) + { + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { + // Slot A - PIRQ ABCD + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8151.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8151.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8151.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,29 @@ +// AMD8151 + Device (AGPB) + { + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,315 @@ +/* + * Copyright 2005 AMD + */ + +//AMD k8 util for BUSB and res range + + Scope (\_SB) + { + + Name (OSTB, Ones) + Method (OSTP, 0, NotSerialized) + { + If (LEqual (^OSTB, Ones)) + { + Store (0x00, ^OSTB) + } + + Return (^OSTB) + } + + Method (SEQL, 2, Serialized) + { + Store (SizeOf (Arg0), Local0) + Store (SizeOf (Arg1), Local1) + If (LNot (LEqual (Local0, Local1))) { Return (Zero) } + + Name (BUF0, Buffer (Local0) {}) + Store (Arg0, BUF0) + Name (BUF1, Buffer (Local0) {}) + Store (Arg1, BUF1) + Store (Zero, Local2) + While (LLess (Local2, Local0)) + { + Store (DerefOf (Index (BUF0, Local2)), Local3) + Store (DerefOf (Index (BUF1, Local2)), Local4) + If (LNot (LEqual (Local3, Local4))) { Return (Zero) } + + Increment (Local2) + } + + Return (One) + } + + + Method (DADD, 2, NotSerialized) + { + Store( Arg1, Local0) + Store( Arg0, Local1) + Add( ShiftLeft(Local1,16), Local0, Local0) + Return (Local0) + } + + + Method (GHCE, 1, NotSerialized) // check if the HC enabled + { + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + Else { Return (0x00) } + } + + Method (GHCN, 1, NotSerialized) // get the node num for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) + Return (Local0) + } + + Method (GHCL, 1, NotSerialized) // get the link num on node for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) + Return (Local0) + } + + Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) + Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 + Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 + Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Return (Local0) + } + + Method (GBUS, 2, NotSerialized) + { + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) + } + } + } + + Increment (Local0) + } + + Return (0x00) + } + + Method (GWBN, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0000, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0000,,,) + }) + CreateWordField (BUF0, 0x08, BMIN) + CreateWordField (BUF0, 0x0A, BMAX) + CreateWordField (BUF0, 0x0E, BLEN) + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) + Store (ShiftRight (Local1, 0x18), BMAX) + Subtract (BMAX, BMIN, BLEN) + Increment (BLEN) + Return (RTAG (BUF0)) + } + } + } + + Increment (Local0) + } + + Return (RTAG (BUF0)) + } + + Method (GMEM, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , AddressRangeMemory, TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, MMIN) + CreateDWordField (BUF0, 0x0E, MMAX) + CreateDWordField (BUF0, 0x16, MLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x10)) + { + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) + Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) + Or (MMAX, 0xFFFF, MMAX) + Subtract (MMAX, MMIN, MLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (\_SB.PCI0.TOM1, MMIN) + Subtract (MMAX, MMIN, MLEN) + Increment (MLEN) + } + + Store (RTAG (BUF0), Local3) + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (BUF0, Local3) + } + + Return (Local3) + } + + Method (GIOR, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, PMIN) + CreateDWordField (BUF0, 0x0E, PMAX) + CreateDWordField (BUF0, 0x16, PLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x08)) + { + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (And (Local1, 0x01FFF000), PMIN) + Store (And (Local2, 0x01FFF000), PMAX) + Or (PMAX, 0x0FFF, PMAX) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + If (LGreater (PMAX, PMIN)) + { + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (0x0D00, PMIN) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + } + + Store (RTAG (BUF0), Local3) + Increment (Local4) + } + + If (And (Local1, 0x10)) + { + Store (0x03B0, PMIN) + Store (0x03DF, PMAX) + Store (0x30, PLEN) + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + } + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (RTAG (BUF0), Local3) + } + + Return (Local3) + } + + Method (RTAG, 1, NotSerialized) + { + Store (Arg0, Local0) + Store (SizeOf (Local0), Local1) + Subtract (Local1, 0x02, Local1) + Multiply (Local1, 0x08, Local1) + CreateField (Local0, 0x00, Local1, RETB) + Store (RETB, Local2) + Return (Local2) + } + } + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,212 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_PR) + { + Processor (CPU0, 0x00, 0x0000C010, 0x06) {} + Processor (CPU1, 0x01, 0x00000000, 0x00) {} + Processor (CPU2, 0x02, 0x00000000, 0x00) {} + Processor (CPU3, 0x03, 0x00000000, 0x00) {} + + } + + Method (FWSO, 0, NotSerialized) { } + + Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) + Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 }) + Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 }) + Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 }) + + Scope (_SB) + { + Device (PCI0) + { + /* BUS0 root bus */ + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + External (CBST) + + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + Name (_UID, 0x01) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + \_SB.OSTP () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + Include ("pci0_hc.asl") + + } + Device (PCI1) + { + Name (_HID, "PNP0A03") + Name (_ADR, 0x00000000) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + Return (\_SB.PCI0.CBST) + } + Name (_BBN, 0x00) + } + + + } + + Scope (_GPE) + { + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI0, 0x02) //PME# Wakeup + } + + Method (_L0F, 0, NotSerialized) + { + Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup + } + + Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B + { + Notify (\_SB.PCI0.PG0B, 0x02) + } + + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + { + Notify (\_SB.PCI0.PG0A, 0x02) + } + } + + Method (_PTS, 1, NotSerialized) + { + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) + } +/* + Method (_WAK, 1, NotSerialized) + { + Or (Arg0, 0xE0, Local0) + Store (Local0, DBG1) + } +*/ + Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode + Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method + { + Store (Arg0, PICF) + } + + OperationRegion (DEBG, SystemIO, 0x80, 0x01) + Field (DEBG, ByteAcc, Lock, Preserve) + { + DBG1, 8 + } + + OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) + Field (EXTM, WordAcc, Lock, Preserve) + { + AMEM, 32 + } + + OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) + Field (VGAM, ByteAcc, Lock, Preserve) + { + VGA1, 8 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + OperationRegion (GSTS, SystemIO, 0xC028, 0x02) + Field (GSTS, ByteAcc, NoLock, Preserve) + { + , 4, + IRQR, 1 + } + + OperationRegion (Z007, SystemIO, 0x21, 0x01) + Field (Z007, ByteAcc, NoLock, Preserve) + { + Z008, 8 + } + + OperationRegion (Z009, SystemIO, 0xA1, 0x01) + Field (Z009, ByteAcc, NoLock, Preserve) + { + Z00A, 8 + } + + Include ("amdk8_util.asl") + +} + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci0_hc.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci0_hc.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci0_hc.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,2 @@ + Include ("amd8111.asl") //real SB at first + Include ("amd8131.asl") Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,68 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCI2) + { + + // BUS ? Second HT Chain + Name (HCIN, 0x01) // HC2 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00180000)) + } + + Name (_UID, 0x03) + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + Include ("pci2_hc.asl") + } + } + +} + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1 @@ + Include ("amd8151.asl") Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/superio.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/superio.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/superio.asl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1 @@ +// Include ("w83627hf.asl") Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/fadt.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/fadt.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/fadt.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,149 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2005 Stefan Reinauer + */ + +#include +#include +#include + +extern unsigned pm_base; /* pm_base should be set in sb acpi */ + +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ + + acpi_header_t *header=&(fadt->header); + + printk_debug("pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt,0,sizeof(acpi_fadt_t)); + memcpy(header->signature,"FACP",4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id,OEM_ID,6); + memcpy(header->oem_table_id,"LXBACPI ",8); + memcpy(header->asl_compiler_id,ASLC,4); + header->asl_compiler_revision=0; + + fadt->firmware_ctrl=(u32)facs; + fadt->dsdt= (u32)dsdt; + fadt->res1=0x0; + // 3=Workstation,4=Enterprise Server, 7=Performance Server + fadt->preferred_pm_profile=0x03; + fadt->sci_int=9; + // disable system management mode by setting to 0: + fadt->smi_cmd = 0;//pm_base+0x2f; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = pm_base; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = pm_base+0x04; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = 0x0000; + fadt->pm_tmr_blk = pm_base+0x08; + fadt->gpe0_blk = pm_base+0x20; + fadt->gpe1_blk = pm_base+0xb0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 8; + fadt->gpe1_base = 16; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; // 0x7d these have to be + fadt->mon_alrm = 0; // 0x7e added to cmos.layout + fadt->century = 0; // 0x7f to make rtc alrm work + fadt->iapc_boot_arch = 0x3; // See table 5-11 + fadt->flags = 0x25; + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pm_base; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pm_base+4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pm_base+0x08; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pm_base+0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 64; + fadt->x_gpe1_blk.bit_offset = 16; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = pm_base+0xb0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,140 @@ +#include +#include +#include +#include +#include +#if CONFIG_LOGICAL_CPUS==1 +#include +#endif + +#include + +#include "mb_sysconf.h" + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +struct mb_sysconf_t mb_sysconf; + +static unsigned pci1234x[] = +{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 +}; +static unsigned hcdnx[] = +{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + 0x20202020, + 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +}; + +extern void get_sblk_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + + unsigned apicid_base; + + device_t dev; + int i; + struct mb_sysconf_t *m; + + if(get_bus_conf_done == 1) return; //do it only once + + get_bus_conf_done = 1; + + sysconf.mb = &mb_sysconf; + + m = sysconf.mb; + + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 8) & 0xff; + m->sbdn3 = sysconf.hcdn[0] & 0xff; + m->sbdn5 = sysconf.hcdn[1] & 0xff; + + m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; + m->bus_8111_0 = m->bus_8132_0; + + /* 8111 */ + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); + if (dev) { + m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; +// printk_debug("bus_isa=%d\n",bus_isa); +#endif + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn); + } + + /* 8132-1 */ + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0)); + if (dev) { + m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3); + } + + /* 8132-2 */ + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); + if (dev) { + m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; +// printk_debug("bus_isa=%d\n",bus_isa); +#endif + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1); + } + + /* HT chain 1 */ + if((sysconf.pci1234[1] & 0x1) == 1) { + m->bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8151 */ + dev = dev_find_slot(m->bus_8151_0, PCI_DEVFN(m->sbdn5+1, 0)); + + if (dev) { + m->bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +// printk_debug("bus_8151_1=%d\n",bus_8151_1); + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151_0, m->sbdn5+1); + } + } + +/*I/O APICs: APIC ID Version State Address*/ +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(3); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + m->apicid_8111 = apicid_base+0; + m->apicid_8132_1 = apicid_base+1; + m->apicid_8132_2 = apicid_base+2; +} Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,139 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include +#include +#include +#include +#include +#include + +#include "mb_sysconf.h" + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +extern void get_bus_conf(void); + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + + uint8_t sum=0; + int i; + + struct mb_sysconf_t *m; + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + + m = sysconf.mb; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%x...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = m->bus_8111_0; + pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1022; + pirq->rtr_device = 0x746b; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; + + { + device_t dev; + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ3 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ11 + */ + pci_write_config16(dev, 0x56, 0xba53); + } + } + +//pci bridge + printk_debug("setting Onboard AMD Southbridge \n"); + static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; + pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); + write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + + printk_debug("setting Onboard AMD USB \n"); + static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; + pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); + write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + +//pcix bridge +// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++; + + if(sysconf.pci1234[1] & 0xf) { + //agp bridge + write_pirq_info(pirq_info, m->bus_8151_0, (m->sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + } + + pirq_info++; slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("done.\n"); + + return (unsigned long) pirq_info; + +} Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mainboard.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,12 @@ +#include +#include +#include +#include +#include +#include "chip.h" + +#if CONFIG_CHIP_NAME == 1 +struct chip_operations mainboard_amd_serengeti_cheetah_ops = { + CHIP_NAME("AMD serengeti_cheetah mainboard") +}; +#endif Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,23 @@ +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_isa; + unsigned char bus_8132_0; + unsigned char bus_8132_1; + unsigned char bus_8132_2; + unsigned char bus_8111_0; + unsigned char bus_8111_1; + unsigned char bus_8151_0; + unsigned char bus_8151_1; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + + unsigned sbdn3; + unsigned sbdn5; +}; + +#endif + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,145 @@ +#include +#include +#include +#include +#include +#if CONFIG_LOGICAL_CPUS==1 +#include +#endif + +#include +#include "mb_sysconf.h" + +extern void get_bus_conf(void); + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "AMD "; + static const char productid[12] = "SERENGETI "; + struct mp_config_table *mc; + + unsigned char bus_num; + int i; + struct mb_sysconf_t *m; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + + m = sysconf.mb; + +/*Bus: Bus ID Type*/ + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < m->bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, m->bus_isa, "ISA "); + +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111 + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); + } + } + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); + } + } + } + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_8111, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_8111, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_8111, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_8111, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_8111, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_8111, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_8111, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_8111, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_8111, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_8111, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_8111, 0xf); +//??? What + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); + +// Onboard AMD USB + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); + + if(sysconf.pci1234[1] & 0xf) { + // Slot AGP + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151_1, 0x0, m->apicid_8111, 0x11); + } + +//Slot 3 PCI 32 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + } + + +//Slot 4 PCI 32 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + } + + +//Slot 1 PCI-X 133/100/66 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // + } + + +//Slot 2 PCI-X 133/100/66 + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 + } + + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,30 @@ +At this time, For acpi support We got +1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c) +2. support MADT ---- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c) +3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c) +4. Chipset support: amd8111, amd8132 + +The developers need to change for different MB + +Change dx/dsdt_lb.dsl, according to MB layout + pci1, pci2, pci3, pci4, ...., pci8 + if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c + +Change acpi_tables.c + sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now. + if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed + +Regarding pci bridge apic and pic + need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c + +About other chipsets, need to develop their special asl such as + ck804.asl --- NB ck804 + bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000 + +use a to create hex file +use c to delele hex file + +yhlu + +09/18/2005 + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,265 @@ +/* + * AMD serengeti_cheetah needs a different resource map + * + */ + +static void setup_serengeti_cheetah_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1 + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + }; + + int max; + max = sizeof(register_values)/sizeof(register_values[0]); + setup_resource_map(register_values, max); +} + Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -56,14 +56,14 @@ #if HAVE_ACPI_TABLES # object acpi_tables.o # object fadt.o -# if K8_SB_HT_CHAIN_ON_BUS0 +# if SB_HT_CHAIN_ON_BUS0 # object dsdt_bus0.o # else # object dsdt.o # end # object ssdt.o # if ACPI_SSDTX_NUM -# if K8_SB_HT_CHAIN_ON_BUS0 +# if SB_HT_CHAIN_ON_BUS0 # object ssdt2_bus0.o # else # object ssdt2.o @@ -74,7 +74,7 @@ if HAVE_ACPI_TABLES object acpi_tables.o object fadt.o - if K8_SB_HT_CHAIN_ON_BUS0 + if SB_HT_CHAIN_ON_BUS0 makerule dsdt.c depends "$(MAINBOARD)/dx_bus0/dsdt_lb.dsl" action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/dsdt_lb.dsl" @@ -98,7 +98,7 @@ object ./ssdt.o if ACPI_SSDTX_NUM - if K8_SB_HT_CHAIN_ON_BUS0 + if SB_HT_CHAIN_ON_BUS0 makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -54,13 +54,13 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK -uses K8_HW_MEM_HOLE_SIZE_AUTO_INC +uses HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZE_AUTO_INC uses K8_HT_FREQ_1G_SUPPORT uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE -uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY uses USE_DCACHE_RAM @@ -152,14 +152,14 @@ #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -default K8_HW_MEM_HOLE_SIZEK=0x200000 +default HW_MEM_HOLE_SIZEK=0x200000 #1G -#default K8_HW_MEM_HOLE_SIZEK=0x100000 +#default HW_MEM_HOLE_SIZEK=0x100000 #512M -#default K8_HW_MEM_HOLE_SIZEK=0x80000 +#default HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default K8_HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 @@ -175,7 +175,7 @@ default HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default K8_SB_HT_CHAIN_ON_BUS0=1 +default SB_HT_CHAIN_ON_BUS0=1 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -186,7 +186,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcc000 default DCACHE_RAM_SIZE=0x4000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -12,7 +12,6 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -22,7 +21,6 @@ #include "superio/NSC/pc87360/pc87360_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) @@ -141,7 +139,9 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "debug.c" Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -53,10 +53,10 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE -uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_ON_BUS0 uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -128,7 +128,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console #default CONFIG_CONSOLE_VGA=1 @@ -141,7 +141,7 @@ default HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default K8_SB_HT_CHAIN_ON_BUS0=1 +default SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -13,7 +13,6 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -25,7 +24,6 @@ #include "superio/NSC/pc87366/pc87366_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) @@ -125,8 +123,10 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" #include "mainboard/ibm/e325/resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" #define FIRST_CPU 1 #define SECOND_CPU 1 Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -13,7 +13,6 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -25,7 +24,6 @@ #include "superio/NSC/pc87366/pc87366_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) @@ -125,8 +123,10 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" #include "mainboard/ibm/e326/resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" #define FIRST_CPU 1 #define SECOND_CPU 1 Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -18,12 +18,10 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" #include #include "superio/NSC/pc87360/pc87360_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) @@ -80,11 +78,13 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "sdram/generic_sdram.c" /* newisys khepri does not want the default */ #include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" #define NODE_RAM(x) \ .node_id = 0+x, \ Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM @@ -66,7 +66,7 @@ uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE -uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY ## ROM_SIZE is the size of boot ROM that this board will use. @@ -134,7 +134,7 @@ #default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 @@ -146,7 +146,7 @@ #default HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default K8_SB_HT_CHAIN_ON_BUS0=2 +default SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -122,7 +122,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -135,7 +135,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -123,7 +123,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -136,7 +136,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -122,7 +122,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -135,7 +135,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -122,7 +122,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console #default CONFIG_CONSOLE_VGA=1 @@ -135,7 +135,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -122,7 +122,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -135,7 +135,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -126,7 +126,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -139,7 +139,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 default ENABLE_APIC_EXT_ID=1 default APIC_ID_OFFSET=0x10 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -53,7 +53,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM @@ -69,7 +69,7 @@ uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE -uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK @@ -137,7 +137,7 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 @@ -149,7 +149,7 @@ #default HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default K8_SB_HT_CHAIN_ON_BUS0=2 +default SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -53,7 +53,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM @@ -63,7 +63,7 @@ uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE -uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY ## ROM_SIZE is the size of boot ROM that this board will use. @@ -129,7 +129,7 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 @@ -141,7 +141,7 @@ #default HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default K8_SB_HT_CHAIN_ON_BUS0=2 +default SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM @@ -66,7 +66,7 @@ uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE -uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY ## ROM_SIZE is the size of boot ROM that this board will use. @@ -134,7 +134,7 @@ #default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 @@ -146,7 +146,7 @@ #default HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default K8_SB_HT_CHAIN_ON_BUS0=2 +default SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -126,7 +126,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -139,7 +139,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 default ENABLE_APIC_EXT_ID=1 default APIC_ID_OFFSET=0x10 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/Options.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/Options.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -52,7 +52,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -126,7 +126,7 @@ default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #VGA Console #default CONFIG_CONSOLE_VGA=1 @@ -139,7 +139,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 default ENABLE_APIC_EXT_ID=1 default APIC_ID_OFFSET=0x10 Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -19,6 +19,14 @@ if HAVE_ACPI_TABLES object amdk8_acpi.o + makerule ssdt.c + depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" + action "/usr/sbin/iasl -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" + action "mv ssdt.hex ssdt.c" + end + object ./ssdt.o end + object get_sblk_pci1234.o Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -2,6 +2,10 @@ #define AMDK8_H +#if K8_REV_F_SUPPORT == 1 + #include "amdk8_f.h" + +#else /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -55,6 +59,7 @@ #define DRAM_CSBASE 0x40 #define DRAM_CSMASK 0x60 #define DRAM_BANK_ADDR_MAP 0x80 + #define DRAM_TIMING_LOW 0x88 #define DTL_TCL_SHIFT 0 #define DTL_TCL_MASK 0x7 @@ -96,6 +101,7 @@ #define DTL_TWR_BASE 2 #define DTL_TWR_MIN 2 #define DTL_TWR_MAX 3 + #define DRAM_TIMING_HIGH 0x8c #define DTH_TWTR_SHIFT 0 #define DTH_TWTR_MASK 0x1 @@ -122,6 +128,7 @@ #define DTH_TWCL_BASE 1 #define DTH_TWCL_MIN 1 #define DTH_TWCL_MAX 2 + #define DRAM_CONFIG_LOW 0x90 #define DCL_DLL_Disable (1<<0) #define DCL_D_DRV (1<<1) @@ -140,7 +147,7 @@ #define DCL_DisInRcvrs (1<<24) #define DCL_BypMax_SHIFT 25 #define DCL_En2T (1<<28) -#define DCL_UpperCSMap (1<<29) + #define DRAM_CONFIG_HIGH 0x94 #define DCH_ASYNC_LAT_SHIFT 0 #define DCH_ASYNC_LAT_MASK 0xf @@ -232,3 +239,5 @@ #define ConnectionPending (1 << 4) #endif + +#endif /* AMDK8_H */ Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_acpi.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_acpi.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -43,6 +43,7 @@ #include #include #include +#include //it seems these function can be moved arch/i386/boot/acpi.c @@ -112,6 +113,8 @@ return current; } + + static unsigned long resk(uint64_t value) { unsigned long resultk; @@ -153,7 +156,6 @@ state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV } - unsigned long acpi_fill_srat(unsigned long current) { struct acpi_srat_mem_state srat_mem_state; @@ -175,5 +177,157 @@ #endif return current; } + + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* need to find out the node num at first */ + /* fill the first 8 byte with that num */ + /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ + + /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */ + static uint8_t hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, + 1, 0, 2, 1, 3, 2, 4, 3, + 1, 2, 0, 1, 1, 2, 2, 3, + 2, 1, 1, 0, 2, 1, 3, 2, + 2, 3, 1, 2, 0, 1, 1, 2, + 3, 2, 2, 1, 1, 0, 2, 1, + 3, 4, 2, 3, 1, 2, 0, 1, + 4, 4, 3, 2, 2, 1, 1, 0 }; + +// uint8_t outer_node[8]; + + uint8_t *p = (uint8_t *)current; + int nodes = sysconf.nodes; + int i,j; + memset(p, 0, 8+nodes*nodes); +// memset((uint8_t *)outer_node, 0, 8); + *p = (uint8_t) nodes; + p += 8; + +#if 0 + for(i=0;i> 4) & 0xf] = 1; // mark the outer node + } +#endif + + for(i=0;i> (8*i)) & 0xff; + } +} + + +// used by acpi_tables.h + +void update_ssdt(void *ssdt) +{ + uint8_t *BUSN; + uint8_t *MMIO; + uint8_t *PCIO; + uint8_t *SBLK; + uint8_t *TOM1; + uint8_t *SBDN; + uint8_t *HCLK; + uint8_t *HCDN; + uint8_t *CBST; + + int i; + device_t dev; + uint32_t dword; + msr_t msr; + + BUSN = ssdt+0x3a; //+5 will be next BUSN + MMIO = ssdt+0x57; //+5 will be next MMIO + PCIO = ssdt+0xaf; //+5 will be next PCIO + SBLK = ssdt+0xdc; // one byte + TOM1 = ssdt+0xe3; // + SBDN = ssdt+0xed;// + HCLK = ssdt+0xfa; //+5 will be next HCLK + HCDN = ssdt+0x12a; //+5 will be next HCDN + CBST = ssdt+0x157; // + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + for(i=0;i<4;i++) { + dword = pci_read_config32(dev, 0xe0+i*4); + int_to_stream(dword, BUSN+i*5); + } + for(i=0;i<0x10;i++) { + dword = pci_read_config32(dev, 0x80+i*4); + int_to_stream(dword, MMIO+i*5); + } + for(i=0;i<0x08;i++) { + dword = pci_read_config32(dev, 0xc0+i*4); + int_to_stream(dword, PCIO+i*5); + } + + *SBLK = (uint8_t)(sysconf.sblk); + + msr = rdmsr(TOP_MEM); + int_to_stream(msr.lo, TOM1); + + for(i=0;i> 12) & 0xff) { //sb chain on other than bus 0 + *CBST = (uint8_t) (0x0f); + } + else { + *CBST = (uint8_t) (0x00); + } + +} + +//end Added: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,561 @@ +#ifndef AMDK8_F_H + +#define AMDK8_F_H +/* Definitions of various K8 registers */ +/* Function 0 */ +#define HT_TRANSACTION_CONTROL 0x68 +#define HTTC_DIS_RD_B_P (1 << 0) +#define HTTC_DIS_RD_DW_P (1 << 1) +#define HTTC_DIS_WR_B_P (1 << 2) +#define HTTC_DIS_WR_DW_P (1 << 3) +#define HTTC_DIS_MTS (1 << 4) +#define HTTC_CPU1_EN (1 << 5) +#define HTTC_CPU_REQ_PASS_PW (1 << 6) +#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) +#define HTTC_DIS_P_MEM_C (1 << 8) +#define HTTC_DIS_RMT_MEM_C (1 << 9) +#define HTTC_DIS_FILL_P (1 << 10) +#define HTTC_RSP_PASS_PW (1 << 11) +#define HTTC_CHG_ISOC_TO_ORD (1 << 12) +#define HTTC_BUF_REL_PRI_SHIFT 13 +#define HTTC_BUF_REL_PRI_MASK 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_LIMIT_CLDT_CFG (1 << 15) +#define HTTC_LINT_EN (1 << 16) +#define HTTC_APIC_EXT_BRD_CST (1 << 17) +#define HTTC_APIC_EXT_ID (1 << 18) +#define HTTC_APIC_EXT_SPUR (1 << 19) +#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) +#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 +#define HTTC_DS_NP_REQ_LIMIT_MASK 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3 +#define HTTC_MED_PRI_BYP_CNT_SHIFT 24 +#define HTTC_MED_PRI_BYP_CNT_MASK 3 +#define HTTC_HI_PRI_BYP_CNT_SHIFT 26 +#define HTTC_HI_PRI_BYP_CNT_MASK 3 + + +/* Function 1 */ +#define PCI_IO_BASE0 0xc0 +#define PCI_IO_BASE1 0xc8 +#define PCI_IO_BASE2 0xd0 +#define PCI_IO_BASE3 0xd8 +#define PCI_IO_BASE_VGA_EN (1 << 4) +#define PCI_IO_BASE_NO_ISA (1 << 5) + + +/* Function 2 */ +#define DRAM_CSBASE 0x40 +#define DRAM_CSMASK 0x60 +#define DRAM_BANK_ADDR_MAP 0x80 + +#define DRAM_CTRL 0x78 +#define DC_RdPtrInit_SHIFT 0 +#define DC_RdPrtInit_MASK 0xf +#define DC_RdPadRcvFifoDly_SHIFT 4 +#define DC_RdPadRcvFifoDly_MASK 7 +#define DC_RdPadRcvFiloDly_1_5_CLK 2 +#define DC_RdPadRcvFiloDly_2_CLK 3 +#define DC_RdPadRcvFiloDly_2_5_CLK 4 +#define DC_RdPadRcvFiloDly_3_CLK 5 +#define DC_RdPadRcvFiloDly_3_5_CLK 6 +#define DC_AltVidC3MemClkTriEn (1<<16) +#define DC_DllTempAdjTime_SHIFT 17 +#define DC_DllTempAdjTime_MASK 1 +#define DC_DllTempAdjTime_5_MS 0 +#define DC_DllTempAdjTime_1_MS 1 +#define DC_DqsRcvEnTrain (1<<18) + +#define DRAM_INIT 0x7c +#define DI_MrsAddress_SHIFT 0 +#define DI_MrsAddress_MASK 0xffff +#define DI_MrsBank_SHIFT 16 +#define DI_MrsBank_MASK 7 +#define DI_SendRchgAll (1<<24) +#define DI_SendAutoRefresh (1<<25) +#define DI_SendMrsCmd (1<<26) +#define DI_DeassertMemRstX (1<<27) +#define DI_AssertCke (1<<28) +#define DI_EnDramInit (1<<31) + +#define DRAM_TIMING_LOW 0x88 +#define DTL_TCL_SHIFT 0 +#define DTL_TCL_MASK 7 +#define DTL_TCL_BASE 1 +#define DTL_TCL_MIN 3 +#define DTL_TCL_MAX 6 +#define DTL_TRCD_SHIFT 4 +#define DTL_TRCD_MASK 3 +#define DTL_TRCD_BASE 3 +#define DTL_TRCD_MIN 3 +#define DTL_TRCD_MAX 6 +#define DTL_TRP_SHIFT 8 +#define DTL_TRP_MASK 3 +#define DTL_TRP_BASE 3 +#define DTL_TRP_MIN 3 +#define DTL_TRP_MAX 6 +#define DTL_TRTP_SHIFT 11 +#define DTL_TRTP_MASK 1 +#define DTL_TRTP_BASE 2 +#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ +#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ +#define DTL_TRAS_SHIFT 12 +#define DTL_TRAS_MASK 0xf +#define DTL_TRAS_BASE 3 +#define DTL_TRAS_MIN 5 +#define DTL_TRAS_MAX 18 +#define DTL_TRC_SHIFT 16 +#define DTL_TRC_MASK 0xf +#define DTL_TRC_BASE 11 +#define DTL_TRC_MIN 11 +#define DTL_TRC_MAX 26 +#define DTL_TWR_SHIFT 20 +#define DTL_TWR_MASK 3 +#define DTL_TWR_BASE 3 +#define DTL_TWR_MIN 3 +#define DTL_TWR_MAX 6 +#define DTL_TRRD_SHIFT 22 +#define DTL_TRRD_MASK 3 +#define DTL_TRRD_BASE 2 +#define DTL_TRRD_MIN 2 +#define DTL_TRRD_MAX 5 +#define DTL_MemClkDis_SHIFT 24 /* Channel A */ +#define DTL_MemClkDis3 (1 << 26) +#define DTL_MemClkDis2 (1 << 27) +#define DTL_MemClkDis1 (1 << 28) +#define DTL_MemClkDis0 (1 << 29) +#define DTL_MemClkDis1_AM2 (0x51 << 24) +#define DTL_MemClkDis0_AM2 (0xa2 << 24) +#define DTL_MemClkDis0_S1g1 (0xa2 << 24) + +/* DTL_MemClkDis for m2 and s1g1 is different */ + +#define DRAM_TIMING_HIGH 0x8c +#define DTH_TRWTTO_SHIFT 4 +#define DTH_TRWTTO_MASK 7 +#define DTH_TRWTTO_BASE 2 +#define DTH_TRWTTO_MIN 2 +#define DTH_TRWTTO_MAX 9 +#define DTH_TWTR_SHIFT 8 +#define DTH_TWTR_MASK 3 +#define DTH_TWTR_BASE 0 +#define DTH_TWTR_MIN 1 +#define DTH_TWTR_MAX 3 +#define DTH_TWRRD_SHIFT 10 +#define DTH_TWRRD_MASK 3 +#define DTH_TWRRD_BASE 0 +#define DTH_TWRRD_MIN 0 +#define DTH_TWRRD_MAX 3 +#define DTH_TWRWR_SHIFT 12 +#define DTH_TWRWR_MASK 3 +#define DTH_TWRWR_BASE 1 +#define DTH_TWRWR_MIN 1 +#define DTH_TWRWR_MAX 3 +#define DTH_TRDRD_SHIFT 14 +#define DTH_TRDRD_MASK 3 +#define DTH_TRDRD_BASE 2 +#define DTH_TRDRD_MIN 2 +#define DTH_TRDRD_MAX 5 +#define DTH_TREF_SHIFT 16 +#define DTH_TREF_MASK 3 +#define DTH_TREF_7_8_US 2 +#define DTH_TREF_3_9_US 3 +#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ +#define DTH_TRFC_MASK 7 +#define DTH_TRFC_75_256M 0 +#define DTH_TRFC_105_512M 1 +#define DTH_TRFC_127_5_1G 2 +#define DTH_TRFC_195_2G 3 +#define DTH_TRFC_327_5_4G 4 +#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ +#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ +#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ + +#define DRAM_CONFIG_LOW 0x90 +#define DCL_InitDram (1<<0) +#define DCL_ExitSelfRef (1<<1) +#define DCL_DramTerm_SHIFT 4 +#define DCL_DramTerm_MASK 3 +#define DCL_DramTerm_No 0 +#define DCL_DramTerm_75_OH 1 +#define DCL_DramTerm_150_OH 2 +#define DCL_DramTerm_50_OH 3 +#define DCL_DrvWeak (1<<7) +#define DCL_ParEn (1<<8) +#define DCL_SelfRefRateEn (1<<9) +#define DCL_BurstLength32 (1<<10) +#define DCL_Width128 (1<<11) +#define DCL_X4Dimm_SHIFT 12 +#define DCL_X4Dimm_MASK 0xf +#define DCL_UnBuffDimm (1<<16) +#define DCL_DimmEccEn (1<<19) + +#define DRAM_CONFIG_HIGH 0x94 +#define DCH_MemClkFreq_SHIFT 0 +#define DCH_MemClkFreq_MASK 7 +#define DCH_MemClkFreq_200MHz 0 +#define DCH_MemClkFreq_266MHz 1 +#define DCH_MemClkFreq_333MHz 2 +#define DCH_MemClkFreq_400MHz 3 +#define DCH_MemClkFreqVal (1<<3) +#define DCH_MaxAsyncLat_SHIFT 4 +#define DCH_MaxAsyncLat_MASK 0xf +#define DCH_MaxAsyncLat_BASE 0 +#define DCH_MaxAsyncLat_MIN 0 +#define DCH_MaxAsyncLat_MAX 15 +#define DCH_RDqsEn (1<<12) +#define DCH_DisDramInterface (1<<14) +#define DCH_PowerDownEn (1<<15) +#define DCH_PowerDownMode_SHIFT 16 +#define DCH_PowerDownMode_MASK 1 +#define DCH_PowerDownMode_Channel_CKE 0 +#define DCH_PowerDownMode_ChipSelect_CKE 1 +#define DCH_FourRankSODimm (1<<17) +#define DCH_FourRankRDimm (1<<18) +#define DCH_SlowAccessMode (1<<19) +#define DCH_BankSwizzleMode (1<<22) +#define DCH_DcqBypassMax_SHIFT 24 +#define DCH_DcqBypassMax_MASK 0xf +#define DCH_DcqBypassMax_BASE 0 +#define DCH_DcqBypassMax_MIN 0 +#define DCH_DcqBypassMax_MAX 15 +#define DCH_FourActWindow_SHIFT 28 +#define DCH_FourActWindow_MASK 0xf +#define DCH_FourActWindow_BASE 7 +#define DCH_FourActWindow_MIN 8 +#define DCH_FourActWindow_MAX 20 + + +// for 0x98 index and 0x9c data +#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 +#define DCAO_DctOffset_SHIFT 0 +#define DCAO_DctOffset_MASK 0x3fffffff +#define DCAO_DctAccessWrite (1<<30) +#define DCAO_DctAccessDone (1<<31) + +#define DRAM_CTRL_ADDI_DATA_PORT 0x9c + +#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00 +#define DODCC_CkeDrvStren_SHIFT 0 +#define DODCC_CkeDrvStren_MASK 3 +#define DODCC_CkeDrvStren_1_0X 0 +#define DODCC_CkeDrvStren_1_25X 1 +#define DODCC_CkeDrvStren_1_5X 2 +#define DODCC_CkeDrvStren_2_0X 3 +#define DODCC_CsOdtDrvStren_SHIFT 4 +#define DODCC_CsOdtDrvStren_MASK 3 +#define DODCC_CsOdtDrvStren_1_0X 0 +#define DODCC_CsOdtDrvStren_1_25X 1 +#define DODCC_CsOdtDrvStren_1_5X 2 +#define DODCC_CsOdtDrvStren_2_0X 3 +#define DODCC_AddrCmdDrvStren_SHIFT 8 +#define DODCC_AddrCmdDrvStren_MASK 3 +#define DODCC_AddrCmdDrvStren_1_0X 0 +#define DODCC_AddrCmdDrvStren_1_25X 1 +#define DODCC_AddrCmdDrvStren_1_5X 2 +#define DODCC_AddrCmdDrvStren_2_0X 3 +#define DODCC_ClkDrvStren_SHIFT 12 +#define DODCC_ClkDrvStren_MASK 3 +#define DODCC_ClkDrvStren_0_75X 0 +#define DODCC_ClkDrvStren_1_0X 1 +#define DODCC_ClkDrvStren_1_25X 2 +#define DODCC_ClkDrvStren_1_5X 3 +#define DODCC_DataDrvStren_SHIFT 16 +#define DODCC_DataDrvStren_MASK 3 +#define DODCC_DataDrvStren_0_75X 0 +#define DODCC_DataDrvStren_1_0X 1 +#define DODCC_DataDrvStren_1_25X 2 +#define DODCC_DataDrvStren_1_5X 3 +#define DODCC_DqsDrvStren_SHIFT 20 +#define DODCC_DqsDrvStren_MASK 3 +#define DODCC_DqsDrvStren_0_75X 0 +#define DODCC_DqsDrvStren_1_0X 1 +#define DODCC_DqsDrvStren_1_25X 2 +#define DODCC_DqsDrvStren_1_5X 3 +#define DODCC_ProcOdt_SHIFT 28 +#define DODCC_ProcOdt_MASK 3 +#define DODCC_ProcOdt_300_OHMS 0 +#define DODCC_ProcOdt_150_OHMS 1 +#define DODCC_ProcOdt_75_OHMS 2 + +#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01 +#define DWDTCL_WrDatTimeByte0_SHIFT 0 +#define DWDTC_WrDatTimeByte_MASK 0x3f +#define DWDTC_WrDatTimeByte_BASE 0 +#define DWDTC_WrDatTimeByte_MIN 0 +#define DWDTC_WrDatTimeByte_MAX 47 +#define DWDTCL_WrDatTimeByte1_SHIFT 8 +#define DWDTCL_WrDatTimeByte2_SHIFT 16 +#define DWDTCL_WrDatTimeByte3_SHIFT 24 + +#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02 +#define DWDTCH_WrDatTimeByte4_SHIFT 0 +#define DWDTCH_WrDatTimeByte5_SHIFT 8 +#define DWDTCH_WrDatTimeByte6_SHIFT 16 +#define DWDTCH_WrDatTimeByte7_SHIFT 24 + +#define DRAM_WRITE_DATA_ECC_TIMING_CTRL 0x03 +#define DWDETC_WrChkTime_SHIFT 0 +#define DWDETC_WrChkTime_MASK 0x3f +#define DWDETC_WrChkTime_BASE 0 +#define DWDETC_WrChkTime_MIN 0 +#define DWDETC_WrChkTime_MAX 47 + +#define DRAM_ADDR_TIMING_CTRL 0x04 +#define DATC_CkeFineDelay_SHIFT 0 +#define DATC_CkeFineDelay_MASK 0x1f +#define DATC_CkeFineDelay_BASE 0 +#define DATC_CkeFineDelay_MIN 0 +#define DATC_CkeFineDelay_MAX 31 +#define DATC_CkeSetup (1<<5) +#define DATC_CsOdtFineDelay_SHIFT 8 +#define DATC_CsOdtFineDelay_MASK 0x1f +#define DATC_CsOdtFineDelay_BASE 0 +#define DATC_CsOdtFineDelay_MIN 0 +#define DATC_CsOdtFineDelay_MAX 31 +#define DATC_CsOdtSetup (1<<13) +#define DATC_AddrCmdFineDelay_SHIFT 16 +#define DATC_AddrCmdFineDelay_MASK 0x1f +#define DATC_AddrCmdFineDelay_BASE 0 +#define DATC_AddrCmdFineDelay_MIN 0 +#define DATC_AddrCmdFineDelay_MAX 31 +#define DATC_AddrCmdSetup (1<<21) + +#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 +#define DRDTCL_RdDqsTimeByte0_SHIFT 0 +#define DRDTC_RdDqsTimeByte_MASK 0x3f +#define DRDTC_RdDqsTimeByte_BASE 0 +#define DRDTC_RdDqsTimeByte_MIN 0 +#define DRDTC_RdDqsTimeByte_MAX 47 +#define DRDTCL_RdDqsTimeByte1_SHIFT 8 +#define DRDTCL_RdDqsTimeByte2_SHIFT 16 +#define DRDTCL_RdDqsTimeByte3_SHIFT 24 + +#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06 +#define DRDTCH_RdDqsTimeByte4_SHIFT 0 +#define DRDTCH_RdDqsTimeByte5_SHIFT 8 +#define DRDTCH_RdDqsTimeByte6_SHIFT 16 +#define DRDTCH_RdDqsTimeByte7_SHIFT 24 + +#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07 +#define DRDETC_RdDqsTimeCheck_SHIFT 0 +#define DRDETC_RdDqsTimeCheck_MASK 0x3f +#define DRDETC_RdDqsTimeCheck_BASE 0 +#define DRDETC_RdDqsTimeCheck_MIN 0 +#define DRDETC_RdDqsTimeCheck_MAX 47 + +#define DRAM_DQS_RECV_ENABLE_TIME0 0x10 +#define DDRET_DqsRcvEnDelay_SHIFT 0 +#define DDRET_DqsRcvEnDelay_MASK 0xff +#define DDRET_DqsRcvEnDelay_BASE 0 +#define DDRET_DqsRcvEnDelay_MIN 0 +#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */ + +#define DRAM_DQS_RECV_ENABLE_TIME1 0x13 +#define DRAM_DQS_RECV_ENABLE_TIME2 0x16 +#define DRAM_DQS_RECV_ENABLE_TIME3 0x19 + +/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 +that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19 +*/ +#define DRAM_CTRL_MISC 0xa0 +#define DCM_MemClrStatus (1<<0) +#define DCM_DisableJitter (1<<1) +#define DCM_RdWrQByp_SHIFT 2 +#define DCM_RdWrQByp_MASK 3 +#define DCM_RdWrQByp_2 0 +#define DCM_RdWrQByp_4 1 +#define DCM_RdWrQByp_8 2 +#define DCM_RdWrQByp_16 3 +#define DCM_Mode64BitMux (1<<4) +#define DCM_DCC_EN (1<<5) +#define DCM_ILD_lmt_SHIFT 6 +#define DCM_ILD_lmt_MASK 7 +#define DCM_ILD_lmt_0 0 +#define DCM_ILD_lmt_4 1 +#define DCM_ILD_lmt_8 2 +#define DCM_ILD_lmt_16 3 +#define DCM_ILD_lmt_32 4 +#define DCM_ILD_lmt_64 5 +#define DCM_ILD_lmt_128 6 +#define DCM_ILD_lmt_256 7 +#define DCM_DramEnabled (1<<9) +#define DCM_MemClkDis_SHIFT 24 /* Channel B */ +#define DCM_MemClkDis3 (1 << 26) +#define DCM_MemClkDis2 (1 << 27) +#define DCM_MemClkDis1 (1 << 28) +#define DCM_MemClkDis0 (1 << 29) + + +/* Function 3 */ +#define MCA_NB_CONFIG 0x44 +#define MNC_ECC_EN (1 << 22) +#define MNC_CHIPKILL_EN (1 << 23) + +#define SCRUB_CONTROL 0x58 +#define SCRUB_NONE 0 +#define SCRUB_40ns 1 +#define SCRUB_80ns 2 +#define SCRUB_160ns 3 +#define SCRUB_320ns 4 +#define SCRUB_640ns 5 +#define SCRUB_1_28us 6 +#define SCRUB_2_56us 7 +#define SCRUB_5_12us 8 +#define SCRUB_10_2us 9 +#define SCRUB_20_5us 10 +#define SCRUB_41_0us 11 +#define SCRUB_81_9us 12 +#define SCRUB_163_8us 13 +#define SCRUB_327_7us 14 +#define SCRUB_655_4us 15 +#define SCRUB_1_31ms 16 +#define SCRUB_2_62ms 17 +#define SCRUB_5_24ms 18 +#define SCRUB_10_49ms 19 +#define SCRUB_20_97ms 20 +#define SCRUB_42ms 21 +#define SCRUB_84ms 22 +#define SC_DRAM_SCRUB_RATE_SHFIT 0 +#define SC_DRAM_SCRUB_RATE_MASK 0x1f +#define SC_L2_SCRUB_RATE_SHIFT 8 +#define SC_L2_SCRUB_RATE_MASK 0x1f +#define SC_L1D_SCRUB_RATE_SHIFT 16 +#define SC_L1D_SCRUB_RATE_MASK 0x1f + +#define SCRUB_ADDR_LOW 0x5C + +#define SCRUB_ADDR_HIGH 0x60 + +#define NORTHBRIDGE_CAP 0xE8 +#define NBCAP_128Bit (1 << 0) +#define NBCAP_MP (1 << 1) +#define NBCAP_BIG_MP (1 << 2) +#define NBCAP_ECC (1 << 3) +#define NBCAP_CHIPKILL_ECC (1 << 4) +#define NBCAP_MEMCLK_SHIFT 5 +#define NBCAP_MEMCLK_MASK 3 +#define NBCAP_MEMCLK_200MHZ 3 +#define NBCAP_MEMCLK_266MHZ 2 +#define NBCAP_MEMCLK_333MHZ 1 +#define NBCAP_MEMCLK_NOLIMIT 0 +#define NBCAP_MEMCTRL (1 << 8) +#define NBCAP_HtcCap (1<<10) +#define NBCAP_CmpCap_SHIFT 12 +#define NBCAP_CmpCap_MASK 3 + + +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) + + +#include "raminit.h" +//struct definitions + +struct dimm_size { + uint8_t per_rank; // it is rows + col + bank_lines + data lines */ + uint8_t rows; + uint8_t col; + uint8_t bank; //1, 2, 3 mean 2, 4, 8 + uint8_t rank; +} __attribute__((packed)); + +struct mem_info { // pernode + uint32_t dimm_mask; + struct dimm_size sz[DIMM_SOCKETS]; + uint32_t x4_mask; + uint32_t x16_mask; + uint32_t single_rank_mask; + uint32_t page_1k_mask; +// uint32_t ecc_mask; +// uint32_t registered_mask; + uint8_t is_opteron; + uint8_t is_registered; + uint8_t is_ecc; + uint8_t is_Width128; + uint8_t memclk_set; // we need to use this to retrieve the mem param + uint8_t rsv[3]; +} __attribute__((packed)); + +struct link_pair_st { + device_t udev; + uint32_t upos; + uint32_t uoffs; + device_t dev; + uint32_t pos; + uint32_t offs; + +} __attribute__((packed)); + +struct sys_info { + uint8_t ctrl_present[NODE_NUMS]; + struct mem_info meminfo[NODE_NUMS]; + struct mem_controller ctrl[NODE_NUMS]; + uint8_t mem_trained[NODE_NUMS]; + uint32_t tom_k; + uint32_t tom2_k; + + uint32_t mem_base[NODE_NUMS]; + uint32_t cs_base[NODE_NUMS*8]; //8 cs_idx + uint32_t hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it + + uint8_t dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9 + uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8 + uint32_t nodes; + struct link_pair_st link_pair[16];// enough? only in_conherent + uint32_t link_pair_num; + uint32_t ht_c_num; + uint32_t sbdn; + uint32_t sblk; + uint32_t sbbusn; +} __attribute__((packed)); + +#if MEM_TRAIN_SEQ == 1 + +static void wait_all_core0_mem_trained(struct sys_info *sysinfo) +{ + int i; + uint32_t mask = 0; + + if(sysinfo->nodes == 1) return; // in case only one cpu installed + + for(i=1; inodes; i++) { + if (!sysinfo->ctrl_present[ i ]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + mask |= (1<mem_trained[i])) { + mask &= ~(1<nodes; + } + +} +#endif + +#endif /* AMDK8_F_H */ Added: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f_pci.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f_pci.c (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f_pci.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,57 @@ +#ifndef AMDK8_F_PCI_C + +#define AMDK8_F_PCI_C +/* bit [10,8] are dev func, bit[1,0] are dev index */ +static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index) +{ + uint32_t dword; + + pci_write_config32(dev, index_reg, index); + + dword = pci_read_config32(dev, index_reg+0x4); + + return dword; +} + +static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +{ + + pci_write_config32(dev, index_reg, index); + + pci_write_config32(dev, index_reg + 0x4, data); + +} + +static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index) +{ + + uint32_t dword; + + index &= ~(1<<30); + pci_write_config32(dev, index_reg, index); + + do { + dword = pci_read_config32(dev, index_reg); + } while (!(dword & (1<<31))); + + dword = pci_read_config32(dev, index_reg+0x4); + + return dword; +} + +static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +{ + + uint32_t dword; + + pci_write_config32(dev, index_reg + 0x4, data); + + index |= (1<<30); + pci_write_config32(dev, index_reg, index); + do { + dword = pci_read_config32(dev, index_reg); + } while (!(dword & (1<<31))); + +} + +#endif Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -1642,6 +1642,10 @@ #endif } +static inline unsigned get_nodes(void) +{ + return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; +} static void coherent_ht_finalize(unsigned nodes) { Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -285,12 +285,14 @@ freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ +#if K8_REV_F_SUPPORT == 0 #if K8_HT_FREQ_1G_SUPPORT == 1 if (!is_cpu_pre_e0()) { return freq_cap; } #endif +#endif id = pci_read_config32(dev, 0); @@ -1590,7 +1592,9 @@ static void coherent_ht_finalize(unsigned nodes) { unsigned node; +#if K8_REV_F_SUPPORT == 0 int rev_a0; +#endif #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; @@ -1609,7 +1613,11 @@ */ print_spew("coherent_ht_finalize\r\n"); + +#if K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); +#endif + for (node = 0; node < nodes; node++) { device_t dev; uint32_t val; @@ -1638,11 +1646,13 @@ (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); +#if K8_REV_F_SUPPORT == 0 if (rev_a0) { pci_write_config32(dev, 0x94, 0); pci_write_config32(dev, 0xb4, 0); pci_write_config32(dev, 0xd4, 0); } +#endif } print_spew("done\r\n"); @@ -1656,6 +1666,7 @@ device_t dev; uint32_t cmd; dev = NODE_MC(node); +#if K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 66 @@ -1697,6 +1708,7 @@ needs_reset = 1; /* Needed? */ } } +#endif } return needs_reset; } @@ -1734,6 +1746,11 @@ return needs_reset; } +static inline unsigned get_nodes(void) +{ + return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; +} + static int optimize_link_coherent_ht(void) { int needs_reset = 0; Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/get_sblk_pci1234.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -39,7 +39,9 @@ #include #include +#include + #if 0 unsigned node_link_to_bus(unsigned node, unsigned link) { @@ -77,13 +79,6 @@ #endif -extern unsigned pci1234[]; -extern unsigned hcdn[]; -extern unsigned hc_possible_num; -extern unsigned sblk; - -unsigned hcdn_reg[4]; // defined in northbridge.c - /* why we need pci1234 array final result for pci1234 will be pci1234[0] will record sblink and bus range @@ -152,6 +147,13 @@ So Max HC_POSSIBLE_NUM is 8 + 1n: 3 + 2n: 2x2 - 1 + 4n: 1x4 - 2 + 6n: 2 + 8n: 2 + Total: 12 + just put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c on MB dir Also don't forget to increase the ACPI_SSDTX_NUM etc if you have too much SSDT @@ -169,11 +171,11 @@ /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); dword = pci_read_config32(dev, 0x64); - sblk = (dword>>8) & 0x3; + sysconf.sblk = (dword>>8) & 0x3; dword &=0x0300; dword |= 1; - pci1234[0] = dword; + sysconf.pci1234[0] = dword; /*about hardcode numbering for HT_IO support set the node_id and link_id that could have ht chain in the one array, @@ -189,35 +191,35 @@ dwordx = pci_read_config32(dev, 0xe0+j*4); dwordx &=0xffff0ff1; //keep bus num, node_id, link_num, enable bits if((dwordx & 0xff1) == dword) { //SBLINK - pci1234[0] = dwordx; - hcdn[0] = hcdn_reg[j]; + sysconf.pci1234[0] = dwordx; + sysconf.hcdn[0] = sysconf.hcdn_reg[j]; continue; } if((dwordx & 1) == 1) { // We need to find out the number of HC // for exact match - for(i=1;i #include #include @@ -22,10 +19,7 @@ #define K8_ALLOCATE_IO_RANGE 0 #endif -/* Do we need to allocate MMIO? Currently we direct the last 64M - * to the southbridge link only. We have to remain access to the - * 4G-4M range for the southbridge (Flash ROM) - */ +// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM #ifndef K8_ALLOCATE_MMIO_RANGE #define K8_ALLOCATE_MMIO_RANGE 0 #endif @@ -55,9 +49,7 @@ if (pos > PCI_CAP_LIST_NEXT) { pos = pci_read_config8(dev, pos); } - - /* loop through the linked list */ - while(pos != 0) { + while(pos != 0) { /* loop through the linked list */ uint8_t cap; cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { @@ -89,7 +81,7 @@ device_t dev; uint32_t id; - // actually, only for one HT device HT chain, and unitid is 0 + //actually, only for one HT device HT chain, and unitid is 0 #if HT_CHAIN_UNITID_BASE == 0 if(offset_unitid) { return; @@ -158,9 +150,11 @@ /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { #if K8_HT_FREQ_1G_SUPPORT == 1 + #if K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only E0 later support 1GHz freq_cap &= ~(1 << HT_FREQ_1000Mhz); } + #endif #else freq_cap &= ~(1 << HT_FREQ_1000Mhz); #endif @@ -268,33 +262,22 @@ return needs_reset; } - #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) #if RAMINIT_SYSINFO == 1 -static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, - unsigned offset_unitid, struct sys_info *sysinfo); - -static int scan_pci_bus(unsigned bus, struct sys_info *sysinfo) +static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo); +static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) #else -static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, - unsigned offset_unitid); - -static int scan_pci_bus(unsigned bus) +static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid); +static int scan_pci_bus( unsigned bus) #endif { - /* Here we already can access PCI_DEV(bus, 0, 0) to - * PCI_DEV(bus, 0x1f, 0x7). - * - * So scan these devices to find out whether there are more bridges. - * - * - If we find a pci bridge, set the bus number in the bridge, and - * continue with the next device. - * - * - For hypertransport bridges, set the bus number in the bridge and - * call ht_setup_chainx(), and scan_pci_bus() - * - */ + /* + here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7) + So We can scan these devices to find out if they are bridge + If it is pci bridge, We need to set busn in bridge, and go on + For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus + */ unsigned int devfn; unsigned new_bus; unsigned max_bus; @@ -356,18 +339,12 @@ ((unsigned int) max_bus << 16)); pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - /* Here we need to figure out if dev is a ht - * bridge. If it is, we need to call - * ht_setup_chainx() first - * - * Not verified --- yhlu - */ - - uint8_t upos; // is this valid C? - - // one func one ht sub - upos = ht_lookup_host_capability(dev); - + /* here we need to figure out if dev is a ht bridge + if it is ht bridge, we need to call ht_setup_chainx at first + Not verified --- yhlu + */ + uint8_t upos; + upos = ht_lookup_host_capability(dev); // one func one ht sub if (upos) { // sub ht chain uint8_t busn; busn = (new_bus & 0xff); @@ -390,7 +367,7 @@ buses = (buses & 0xff00ffff) | ((unsigned int) (new_bus & 0xff) << 16); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); + pci_write_config32(dev, PCI_PRIMARY_BUS, buses); pci_write_config16(dev, PCI_COMMAND, cr); @@ -405,7 +382,6 @@ * time probing another function. * Skip to next device. */ - if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80)) { devfn += 0x07; @@ -422,9 +398,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) #endif { - // execute this function even with HT_CHAIN_UNITID_BASE == 0, - // because of the end_of_chain check, and we need it to - // optimize the links + //even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link uint8_t next_unitid, last_unitid; unsigned uoffs; @@ -434,8 +408,7 @@ #endif #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - // record the device id of last ht device, so we can set the - // unit id to HT_CHAIN_END_UNITID_BASE + //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; int ht_dev_num = 0; @@ -519,17 +492,15 @@ next_unitid += count; - /* Find which side of the ht link we are on, by reading - * which direction our last write to PCI_CAP_FLAGS came - * from. + /* Find which side of the ht link we are on, + * by reading which direction our last write to PCI_CAP_FLAGS + * came from. */ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS; #if RAMINIT_SYSINFO == 1 - /* store the link pair here and we will setup the - * Hypertransport link later, after we get final FID/VID - */ + /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */ { struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num]; link_pair->udev = udev; @@ -544,7 +515,7 @@ reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, offs); #endif - /* Remember the location of the last device */ + /* Remeber the location of the last device */ udev = dev; upos = pos; uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS; @@ -586,8 +557,6 @@ } - - #if RAMINIT_SYSINFO == 1 static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo) #else @@ -618,10 +587,7 @@ return ht_setup_chainx(udev, upos, 0, offset_unitid); #endif } - - -static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, - uint8_t linkt, uint8_t val) +static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val) { uint32_t dword, dword_old; uint8_t link_type; @@ -630,17 +596,16 @@ dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); link_type = dword & 0xff; - dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc); - /* coherent link only linkt = 3, non coherent = 7*/ - if ( (link_type & 7) == linkt ) { + if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc); dword &= ~( 0xff<<(linkn *8) ); dword |= val << (linkn *8); - } - if (dword != dword_old) { - pci_write_config32(PCI_DEV(0,0x18+node,3), 0xdc, dword); - return 1; + if (dword != dword_old) { + pci_write_config32(PCI_DEV(0,0x18+node,3), 0xdc, dword); + return 1; + } } return 0; @@ -658,14 +623,22 @@ uint8_t nodeid, linkn; uint8_t busn; uint8_t val; + unsigned devn = 1; + #if HT_CHAIN_UNITID_BASE != 1 + #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + if(i==0) // to check if it is sb ht chain + #endif + devn = HT_CHAIN_UNITID_BASE; + #endif + reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); nodeid = ((reg & 0xf0)>>4); // nodeid linkn = ((reg & 0xf00)>>8); // link n busn = (reg & 0xff0000)>>16; //busn - - reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID); + + reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) { val = 0x25; } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) { @@ -681,18 +654,79 @@ return reset_needed; } +static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) +{ + uint32_t dword; + uint8_t link_type; + unsigned regpos; + device_t dev; + + /* This works on an Athlon64 because unimplemented links return 0 */ + regpos = 0x98 + (linkn * 0x20); + dev = PCI_DEV(0,0x18+node,0); + dword = pci_read_config32(dev, regpos); + link_type = dword & 0xff; + + if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ + regpos = 0x90 + (linkn * 0x20); + dword = pci_read_config32(dev, regpos ); + + if (dword != val) { + pci_write_config32(dev, regpos, val); + return 1; + } + } + + return 0; +} +static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) +{ + int reset_needed; + uint8_t i; + + reset_needed = 0; + + for (i = 0; i < ht_c_num; i++) { + uint32_t reg; + uint8_t nodeid, linkn; + uint8_t busn; + unsigned devn = 1; + + #if HT_CHAIN_UNITID_BASE != 1 + #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + if(i==0) // to check if it is sb ht chain + #endif + devn = HT_CHAIN_UNITID_BASE; + #endif + + reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); + if((reg & 3) != 3) continue; // not enabled + + nodeid = ((reg & 0xf0)>>4); // nodeid + linkn = ((reg & 0xf00)>>8); // link n + busn = (reg & 0xff0000)>>16; //busn + + reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? + if ( (reg & 0xffff) == vendorid ) { + reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); + } + } + + return reset_needed; +} + + #if RAMINIT_SYSINFO == 1 static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo) #else static int ht_setup_chains(uint8_t ht_c_num) #endif { - /* Assumption: The HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple - * non coherent links the appropriate bus registers for the + /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. + * On most boards this just happens. If a cpu has multiple + * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ - uint8_t upos; device_t udev; uint8_t i; @@ -717,14 +751,9 @@ reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); - // We need to setup 0x94, 0xb4, and 0xd4 according to reg - - // nodeid; it will decide 0x18 or 0x19 - devpos = ((reg & 0xf0)>>4)+0x18; - - // link n; it will decide 0x94 or 0xb4, 0x0xd4; - regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; - + //We need setup 0x94, 0xb4, and 0xd4 according to the reg + devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 + regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ; @@ -753,15 +782,12 @@ #endif #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) - /* You can not use use this in romcc, because recursive - * function calls in romcc will kill you - */ + /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */ bus = busn; // we need 32 bit #if RAMINIT_SYSINFO == 1 scan_pci_bus(bus, sysinfo); #else - // take out reset_needed that is stored in upword - reset_needed |= (scan_pci_bus(bus)>>16); + reset_needed |= (scan_pci_bus(bus)>>16); // take out reset_needed that stored in upword #endif #endif } @@ -774,12 +800,10 @@ } -static inline unsigned get_nodes(void) -{ - return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1; -} +#if defined (__GNUC__) +static inline unsigned get_nodes(void); +#endif - #if RAMINIT_SYSINFO == 1 static void ht_setup_chains_x(struct sys_info *sysinfo) #else @@ -803,15 +827,14 @@ /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ print_linkn_in("SBLink=", ((reg>>8) & 3) ); #if RAMINIT_SYSINFO == 1 - sysinfo->sblnk = (reg>>8) & 3; + sysinfo->sblk = (reg>>8) & 3; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; #endif tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg); - /* 0 will be used ht chain with SB we need to keep SB in bus 0 in auto stage */ - next_busn=0x3f+1; + next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ #if K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ @@ -825,9 +848,12 @@ /* clean others */ for(ht_c_num=1;ht_c_num<4; ht_c_num++) { pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); + +#if K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0); +#endif } for(nodeid=0; nodeid #endif +#include + +struct amdk8_sysconf_t sysconf; + #define FX_DEVS 8 static device_t __f0_dev[FX_DEVS]; static device_t __f1_dev[FX_DEVS]; @@ -97,8 +101,6 @@ return (dev->path.u.pci.devfn >> 3) - 0x18; } -unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234 - static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) { #if 0 @@ -160,17 +162,17 @@ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if K8_SB_HT_CHAIN_ON_BUS0 > 0 +#if SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here min_bus = max; } - #if K8_SB_HT_CHAIN_ON_BUS0 > 1 + #if SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 else { - min_bus = ((max>>6) + 1) * 0x40; + min_bus = ((max>>6) + 1) * 0x40; } - max = min_bus; + max = min_bus; #else //other ... else { @@ -248,7 +250,7 @@ temp |= (ht_unitid_base[i] & 0xff) << (i*8); } - hcdn_reg[index] = temp; + sysconf.hcdn_reg[index] = temp; } @@ -277,7 +279,7 @@ if(nodeid==0) { sblink = (pci_read_config32(dev, 0x64)>>8) & 3; -#if K8_SB_HT_CHAIN_ON_BUS0 > 0 +#if SB_HT_CHAIN_ON_BUS0 > 0 #if HT_CHAIN_UNITID_BASE != 1 offset_unitid = 1; #endif @@ -286,7 +288,7 @@ } for(link = 0; link < dev->links; link++) { -#if K8_SB_HT_CHAIN_ON_BUS0 > 0 +#if SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; @@ -773,7 +775,7 @@ #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) #endif -#if K8_HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -785,7 +787,7 @@ struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = K8_HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < 8; i++) { @@ -931,7 +933,7 @@ unsigned long mmio_basek; uint32_t pci_tolm; int i, idx; -#if K8_HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; unsigned reset_memhole = 1; #endif @@ -1015,12 +1017,14 @@ mmio_basek &= ~((64*1024) - 1); #endif -#if K8_HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * otherwise We reset the hole to the mmio_basek */ + #if K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { + #endif mem_hole = get_hw_mem_hole_info(); @@ -1032,13 +1036,13 @@ //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { - if(mem_hole.node_id!=-1) { // We need to select K8_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! + if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! // We need to reset our Mem Hole, because We want more big HOLE than we already set //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if K8_HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some uint32_t basek_pri; for (i = 0; i < 8; i++) { @@ -1059,7 +1063,9 @@ #endif } +#if K8_REV_F_SUPPORT == 0 } // is_cpu_pre_e0 +#endif #endif @@ -1098,9 +1104,11 @@ idx += 0x10; sizek -= pre_sizek; } - #if K8_HW_MEM_HOLE_SIZEK != 0 + #if HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) + #if K8_REV_F_SUPPORT == 0 if(!is_cpu_pre_e0() ) + #endif sizek += hoist_memory(mmio_basek,i); #endif @@ -1139,7 +1147,6 @@ f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { uint32_t httc; - int j; httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); httc &= ~HTTC_RSP_PASS_PW; if (!dev->link[0].disable_relaxed_ordering) { @@ -1169,24 +1176,20 @@ struct bus *cpu_bus; device_t dev_mc; int bsp_apicid; - int apicid_offset; int i,j; - int nodes; unsigned nb_cfg_54; - int enable_apic_ext_id; unsigned siblings; int e0_later_single_core; int disable_siblings; - unsigned lift_bsp_apicid; nb_cfg_54 = 0; - enable_apic_ext_id = 0; - lift_bsp_apicid = 0; + sysconf.enabled_apic_ext_id = 0; + sysconf.lift_bsp_apicid = 0; siblings = 0; /* Find the bootstrap processors apicid */ bsp_apicid = lapicid(); - apicid_offset = bsp_apicid; + sysconf.apicid_offset = bsp_apicid; disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 @@ -1203,24 +1206,25 @@ die("0:18.0 not found?"); } - nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1; + sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1; + if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { - enable_apic_ext_id = 1; + sysconf.enabled_apic_ext_id = 1; if(bsp_apicid == 0) { /* bsp apic id is not changed */ - apicid_offset = APIC_ID_OFFSET; + sysconf.apicid_offset = APIC_ID_OFFSET; } else { - lift_bsp_apicid = 1; + sysconf.lift_bsp_apicid = 1; } } /* Find which cpus are present */ cpu_bus = &dev->link[0]; - for(i = 0; i < nodes; i++) { + for(i = 0; i < sysconf.nodes; i++) { device_t dev, cpu; struct device_path cpu_path; @@ -1262,7 +1266,11 @@ // That is the typical case if(j == 0 ){ + #if K8_REV_F_SUPPORT == 0 e0_later_single_core = is_e0_later_in_bsp(i); // single core + #else + e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 + #endif } else { e0_later_single_core = 0; } @@ -1321,13 +1329,13 @@ if (cpu) { cpu->path.u.apic.node_id = i; cpu->path.u.apic.core_id = j; - if(enable_apic_ext_id) { - if(lift_bsp_apicid) { - cpu->path.u.apic.apic_id += apicid_offset; + if(sysconf.enabled_apic_ext_id) { + if(sysconf.lift_bsp_apicid) { + cpu->path.u.apic.apic_id += sysconf.apicid_offset; } else { if (cpu->path.u.apic.apic_id != 0) - cpu->path.u.apic.apic_id += apicid_offset; + cpu->path.u.apic.apic_id += sysconf.apicid_offset; } } printk_debug("CPU: %s %s\n", Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -18,7 +18,7 @@ #define K8_4RANK_DIMM_SUPPORT 0 #endif -#if USE_DCACHE_RAM == 1 +#if defined (__GNUC__) static void hard_reset(void); #endif @@ -44,8 +44,8 @@ print_debug("\r\n"); #endif #endif - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; + dev = register_values[i] & ~0xfff; + where = register_values[i] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2]; @@ -555,8 +555,8 @@ print_spew("\r\n"); #endif #endif - dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; - where = register_values[i] & 0xff; + dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; + where = register_values[i] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2]; @@ -886,7 +886,7 @@ /* Now set top of memory */ msr_t msr; - if(tom_k>(4*1024*1024)) { + if(tom_k > (4*1024*1024)) { msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); @@ -896,7 +896,7 @@ * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if K8_HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 if(hole_startk != 0) { tom_k = hole_startk; } else @@ -2183,7 +2183,7 @@ return; } -#if K8_HW_MEM_HOLE_SIZEK != 0 +#if HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2242,9 +2242,9 @@ uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - K8_HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; -#if K8_HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some uint32_t basek_pri; for(i=0; i +#include +#include +#include + +#include "raminit.h" +#include "amdk8_f.h" +#include "spd_ddr2.h" + +#ifndef QRANK_DIMM_SUPPORT +#define QRANK_DIMM_SUPPORT 0 +#endif + +static inline void print_raminit(const char *strval, uint32_t val) +{ +#if CONFIG_USE_INIT + printk_debug("%s:%08x\r\n", strval, val); +#else + print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); +#endif +} + +#define RAM_TIMING_DEBUG 0 + +static inline void print_tx(const char *strval, uint32_t val) +{ +#if RAM_TIMING_DEBUG == 1 + print_raminit(strval, val); +#endif +} + + +static inline void print_t(const char *strval) +{ +#if RAM_TIMING_DEBUG == 1 + print_debug(strval); +#endif +} + + + +#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 +# error "CONFIG_LB_MEM_TOPK must be a power of 2" +#endif + +#include "amdk8_f_pci.c" + + + // for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data + /* + index: + [29: 0] DctOffset (Dram Controller Offset) + [30:30] DctAccessWrite (Dram Controller Read/Write Select) + 0 = read access + 1 = write access + [31:31] DctAccessDone (Dram Controller Access Done) + 0 = Access in progress + 1 = No access is progress + + Data: + [31: 0] DctOffsetData (Dram Controller Offset Data) + + Read: + - Write the register num to DctOffset with DctAccessWrite = 0 + - poll the DctAccessDone until it = 1 + - Read the data from DctOffsetData + Write: + - Write the data to DctOffsetData + - Write register num to DctOffset with DctAccessWrite = 1 + - poll the DctAccessDone untio it = 1 + + */ + + +#if 1 +static void setup_resource_map(const unsigned int *register_values, int max) +{ + int i; + + for(i = 0; i < max; i += 3) { + device_t dev; + unsigned where; + unsigned long reg; + + dev = register_values[i] & ~0xff; + where = register_values[i] & 0xff; + reg = pci_read_config32(dev, where); + reg &= register_values[i+1]; + reg |= register_values[i+2]; + pci_write_config32(dev, where, reg); + } +} +#endif + +static int controller_present(const struct mem_controller *ctrl) +{ + return pci_read_config32(ctrl->f0, 0) == 0x11001022; +} + +static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +{ + static const unsigned int register_values[] = { + + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* DRAM CS Base Address i Registers + * F2:0x40 i = 0 + * F2:0x44 i = 1 + * F2:0x48 i = 2 + * F2:0x4C i = 3 + * F2:0x50 i = 4 + * F2:0x54 i = 5 + * F2:0x58 i = 6 + * F2:0x5C i = 7 + * [ 0: 0] Chip-Select Bank Enable + * 0 = Bank Disabled + * 1 = Bank Enabled + * [ 1: 1] Spare Rank + * [ 2: 2] Memory Test Failed + * [ 4: 3] Reserved + * [13: 5] Base Address (21-13) + * An optimization used when all DIMM are the same size... + * [18:14] Reserved + * [28:19] Base Address (36-27) + * This field defines the top 11 addresses bit of a 40-bit + * address that define the memory address space. These + * bits decode 32-MByte blocks of memory. + * [31:29] Reserved + */ + PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000, + /* DRAM CS Mask Address i Registers + * F2:0x60 i = 0,1 + * F2:0x64 i = 2,3 + * F2:0x68 i = 4,5 + * F2:0x6C i = 6,7 + * Select bits to exclude from comparison with the DRAM Base address register. + * [ 4: 0] Reserved + * [13: 5] Address Mask (21-13) + * Address to be excluded from the optimized case + * [18:14] Reserved + * [28:19] Address Mask (36-27) + * The bits with an address mask of 1 are excluded from address comparison + * [31:29] Reserved + * + */ + PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000, + PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000, + + /* DRAM Control Register + * F2:0x78 + * [ 3: 0] RdPtrInit ( Read Pointer Initial Value) + * 0x03-0x00: reserved + * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO) + * 000 = reserved + * 001 = reserved + * 010 = 1.5 Memory Clocks + * 011 = 2 Memory Clocks + * 100 = 2.5 Memory Clocks + * 101 = 3 Memory Clocks + * 110 = 3.5 Memory Clocks + * 111 = Reseved + * [15: 7] Reserved + * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable) + * Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. This bit has no effect if the DisNbClkRamp bit (F3, 0x88) is set + * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time) + * 0 = 5 ms + * 1 = 1 ms + * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode) + * 0 = Normal DQS Receiver enable operation + * 1 = DQS receiver enable training mode + * [31:19] reverved + */ + PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0), + + /* DRAM Initialization Register + * F2:0x7C + * [15: 0] MrsAddress (Address for MRS/EMRS Commands) + * this field specifies the dsata driven on the DRAM address pins 15-0 for MRS and EMRS commands + * [18:16] MrsBank (Bank Address for MRS/EMRS Commands) + * this files specifies the data driven on the DRAM bank pins for the MRS and EMRS commands + * [23:19] reverved + * [24:24] SendPchgAll (Send Precharge All Command) + * Setting this bit causes the DRAM controller to send a precharge all command. This bit is cleared by the hardware after the command completes + * [25:25] SendAutoRefresh (Send Auto Refresh Command) + * Setting this bit causes the DRAM controller to send an auto refresh command. This bit is cleared by the hardware after the command completes + * [26:26] SendMrsCmd (Send MRS/EMRS Command) + * Setting this bit causes the DRAM controller to send the MRS or EMRS command defined by the MrsAddress and MrsBank fields. This bit is cleared by the hardware adter the commmand completes + * [27:27] DeassertMemRstX (De-assert Memory Reset) + * Setting this bit causes the DRAM controller to de-assert the memory reset pin. This bit cannot be used to assert the memory reset pin + * [28:28] AssertCke (Assert CKE) + * setting this bit causes the DRAM controller to assert the CKE pins. This bit cannot be used to de-assert the CKE pins + * [30:29] reverved + * [31:31] EnDramInit (Enable DRAM Initialization) + * Setting this bit puts the DRAM controller in a BIOS controlled DRAM initialization mode. BIOS must clear this bit aster DRAM initialization is complete. + */ +// PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0, + + + /* DRAM Bank Address Mapping Register + * F2:0x80 + * Specify the memory module size + * [ 3: 0] CS1/0 + * [ 7: 4] CS3/2 + * [11: 8] CS5/4 + * [15:12] CS7/6 + * [31:16] + row col bank + 0: 13 9 2 :128M + 1: 13 10 2 :256M + 2: 14 10 2 :512M + 3: 13 11 2 :512M + 4: 13 10 3 :512M + 5: 14 10 3 :1G + 6: 14 11 2 :1G + 7: 15 10 3 :2G + 8: 14 11 3 :2G + 9: 15 11 3 :4G + 10: 16 10 3 :4G + 11: 16 11 3 :8G + */ + PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000, + /* DRAM Timing Low Register + * F2:0x88 + * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid) + * 000 = reserved + * 001 = reserved + * 010 = CL 3 + * 011 = CL 4 + * 100 = CL 5 + * 101 = CL 6 + * 110 = reserved + * 111 = reserved + * [ 3: 3] Reserved + * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay) + * 00 = 3 clocks + * 01 = 4 clocks + * 10 = 5 clocks + * 11 = 6 clocks + * [ 7: 6] Reserved + * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh) + * 00 = 3 clocks + * 01 = 4 clocks + * 10 = 5 clocks + * 11 = 6 clocks + * [10:10] Reserved + * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time) + * 0 = 2 clocks for Burst Length of 32 Bytes + * 4 clocks for Burst Length of 64 Bytes + * 1 = 3 clocks for Burst Length of 32 Bytes + * 5 clocks for Burst Length of 64 Bytes + * [15:12] Tras (Minimum Ras# Active Time) + * 0000 = reserved + * 0001 = reserved + * 0010 = 5 bus clocks + * ... + * 1111 = 18 bus clocks + * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto refresh of the same bank) + * 0000 = 11 bus clocks + * 0010 = 12 bus clocks + * ... + * 1110 = 25 bus clocks + * 1111 = 26 bus clocks + * [21:20] Twr (Write Recovery Time, From the last data to precharge, writes can go back-to-back) + * 00 = 3 bus clocks + * 01 = 4 bus clocks + * 10 = 5 bus clocks + * 11 = 6 bus clocks + * [23:22] Trrd (Active-to-active (Ras#-to-Ras#) Delay of different banks) + * 00 = 2 bus clocks + * 01 = 3 bus clocks + * 10 = 4 bus clocks + * 11 = 5 bus clocks + * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, BIOS should set it to reduce the power consumption) + * Bit F(1207) M2 Package S1g1 Package + * 0 N/A MA1_CLK1 N/A + * 1 N/A MA0_CLK1 MA0_CLK1 + * 2 MA3_CLK N/A N/A + * 3 MA2_CLK N/A N/A + * 4 MA1_CLK MA1_CLK0 N/A + * 5 MA0_CLK MA0_CLK0 MA0_CLK0 + * 6 N/A MA1_CLK2 N/A + * 7 N/A MA0_CLK2 MA0_CLK2 + */ + PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ , + /* DRAM Timing High Register + * F2:0x8C + * [ 3: 0] Reserved + * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention) + * 000 = 2 bus clocks + * 001 = 3 bus clocks + * 010 = 4 bus clocks + * 011 = 5 bus clocks + * 100 = 6 bus clocks + * 101 = 7 bus clocks + * 110 = 8 bus clocks + * 111 = 9 bus clocks + * [ 7: 7] Reserved + * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, minium write-to-read delay when both access the same chip select) + * 00 = Reserved + * 01 = 1 bus clocks + * 10 = 2 bus clocks + * 11 = 3 bus clocks + * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum write-to-read delay when accessing two different DIMMs) + * 00 = 0 bus clocks + * 01 = 1 bus clocks + * 10 = 2 bus clocks + * 11 = 3 bus clocks + * [13:12] Twrwr (Write to Write Timing) + * 00 = 1 bus clocks ( 0 idle cycle on the bus) + * 01 = 2 bus clocks ( 1 idle cycle on the bus) + * 10 = 3 bus clocks ( 2 idle cycles on the bus) + * 11 = Reserved + * [15:14] Trdrd ( Read to Read Timing) + * 00 = 2 bus clocks ( 1 idle cycle on the bus) + * 01 = 3 bus clocks ( 2 idle cycles on the bus) + * 10 = 4 bus clocks ( 3 idle cycles on the bus) + * 11 = 5 bus clocks ( 4 idel cycles on the bus) + * [17:16] Tref (Refresh Rate) + * 00 = Undefined behavior + * 01 = Reserved + * 10 = Refresh interval of 7.8 microseconds + * 11 = Refresh interval of 3.9 microseconds + * [19:18] Reserved + * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0, based on DRAM density and speed) + * 000 = 75 ns (all speeds, 256Mbit) + * 001 = 105 ns (all speeds, 512Mbit) + * 010 = 127.5 ns (all speeds, 1Gbit) + * 011 = 195 ns (all speeds, 2Gbit) + * 100 = 327.5 ns (all speeds, 4Gbit) + * 101 = reserved + * 110 = reserved + * 111 = reserved + * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1, based on DRAM density and speed) + * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2, based on DRAM density and speed) + * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3, based on DRAM density and speed) + */ + PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8), + /* DRAM Config Low Register + * F2:0x90 + * [ 0: 0] InitDram (Initialize DRAM) + * 1 = write 1 cause DRAM controller to execute the DRAM initialization, when done it read to 0 + * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command ) + * 1 = write 1 causes the DRAM controller to bring the DRAMs out fo self refresh mode + * [ 3: 2] Reserved + * [ 5: 4] DramTerm (DRAM Termination) + * 00 = On die termination disabled + * 01 = 75 ohms + * 10 = 150 ohms + * 11 = 50 ohms + * [ 6: 6] Reserved + * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode) + * 0 = Normal drive strength mode. + * 1 = Weak drive strength mode + * [ 8: 8] ParEn (Parity Enable) + * 1 = Enable address parity computation output, PAR, and enables the parity error input, ERR + * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable) + * 1 = Enable high temperature ( two times normal ) self refresh rate + * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes) + * 0 = 64-byte mode + * 1 = 32-byte mode + * [11:11] Width128 ( Width of DRAM interface) + * 0 = the controller DRAM interface is 64-bits wide + * 1 = the controller DRAM interface is 128-bits wide + * [12:12] X4Dimm (DIMM 0 is x4) + * [13:13] X4Dimm (DIMM 1 is x4) + * [14:14] X4Dimm (DIMM 2 is x4) + * [15:15] X4Dimm (DIMM 3 is x4) + * 0 = DIMM is not x4 + * 1 = x4 DIMM present + * [16:16] UnBuffDimm ( Unbuffered DIMMs) + * 0 = Buffered DIMMs + * 1 = Unbuffered DIMMs + * [18:17] Reserved + * [19:19] DimmEccEn ( DIMM ECC Enable ) + 1 = ECC checking is being enabled for all DIMMs on the DRAM controller ( Through F3 0x44[EccEn]) + * [31:20] Reserved + */ + PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010, + /* DRAM Config High Register + * F2:0x94 + * [ 0: 2] MemClkFreq ( Memory Clock Frequency) + * 000 = 200MHz + * 001 = 266MHz + * 010 = 333MHz + * 011 = reserved + * 1xx = reserved + * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid) + * 1 = BIOS need to set the bit when setting up MemClkFreq to the proper value + * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency) + * 0000 = 0 ns + * ... + * 1111 = 15 ns + * [11: 8] Reserved + * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 registered DIMMs are present in the system + * 0 = DM pins function as data mask pins + * 1 = DM pins function as read DQS pins + * [13:13] Reserved + * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit is set, the DRAM controller is disabled, and interface in low power state + * 0 = Enabled (default) + * 1 = Disabled + * [15:15] PowerDownEn ( Power Down Mode Enable ) + * 0 = Disabled (default) + * 1 = Enabled + * [16:16] PowerDown ( Power Down Mode ) + * 0 = Channel CKE Control + * 1 = Chip Select CKE Control + * [17:17] FourRankSODimm (Four Rank SO-DIMM) + * 1 = this bit is set by BIOS to indicate that a four rank SO-DIMM is present + * [18:18] FourRankRDimm (Four Rank Registered DIMM) + * 1 = this bit is set by BIOS to indicate that a four rank registered DIMM is present + * [19:19] Reserved + * [20:20] SlowAccessMode (Slow Access Mode (2T Mode)) + * 0 = DRAM address and control signals are driven for one MEMCLK cycle + * 1 = One additional MEMCLK of setup time is provided on all DRAM address and control signals except CS, CKE, and ODT; i.e., these signals are drivern for two MEMCLK cycles rather than one + * [21:21] Reserved + * [22:22] BankSwizzleMode ( Bank Swizzle Mode), + * 0 = Disabled (default) + * 1 = Enabled + * [23:23] Reserved + * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum) + * 0000 = No bypass; the oldest request is never bypassed + * 0001 = The oldest request may be bypassed no more than 1 time + * ... + * 1111 = The oldest request may be bypassed no more than 15 times + * [31:28] FourActWindow ( Four Bank Activate Window) , not more than 4 banks in a 8 bank device are activated + * 0000 = No tFAW window restriction + * 0001 = 8 MEMCLK cycles + * 0010 = 9 MEMCLK cycles + * ... + * 1101 = 20 MEMCLK cycles + * 111x = reserved + */ + PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000, + /* DRAM Delay Line Register + * F2:0xa0 + * [ 0: 0] MemClrStatus (Memory Clear Status) : ---------Readonly + * when set, this bit indicates that the memory clear function is complete. Only clear by reset. BIOS should not write or read the DRAM until this bit is set by hardware + * [ 1: 1] DisableJitter ( Disable Jitter) + * When set the DDR compensation circuit will not change the values unless the change is more than one step from the current value + * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count) + * 00 = 2 + * 01 = 4 + * 10 = 8 + * 11 = 16 + * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable) + * 1 When bit enables support for mismatched DIMMs when using 128-bit DRAM interface, the Width128 no effect, only for M2 and s1g1 + * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable) + * When set to 1, indicates that each entry in the page tables dynamically adjusts the idle cycle limit based on page Conflict/Page Miss (PC/PM) traffic + * [ 8: 6] ILD_lmt ( Idle Cycle Limit) + * 000 = 0 cycles + * 001 = 4 cycles + * 010 = 8 cycles + * 011 = 16 cycles + * 100 = 32 cycles + * 101 = 64 cycles + * 110 = 128 cycles + * 111 = 256 cycles + * [ 9: 9] DramEnabled ( DRAM Enabled) + * When Set, this bit indicates that the DRAM is enabled, this bit is set by hardware after DRAM initialization or on an exit from self refresh. The DRAM controller is intialized after the + * hardware-controlled initialization process ( initiated by the F2 0x90[DramInit]) completes or when the BIOS-controlled initialization process completes (F2 0x7c(EnDramInit] is + * written from 1 to 0) + * [23:10] Reserved + * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B, BIOS should set it to reduce the power consumption) + * Bit F(1207) M2 Package S1g1 Package + * 0 N/A MA1_CLK1 N/A + * 1 N/A MA0_CLK1 MA0_CLK1 + * 2 MA3_CLK N/A N/A + * 3 MA2_CLK N/A N/A + * 4 MA1_CLK MA1_CLK0 N/A + * 5 MA0_CLK MA0_CLK0 MA0_CLK0 + * 6 N/A MA1_CLK2 N/A + * 7 N/A MA0_CLK2 MA0_CLK2 + */ + PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000, + + /* DRAM Scrub Control Register + * F3:0x58 + * [ 4: 0] DRAM Scrube Rate + * [ 7: 5] reserved + * [12: 8] L2 Scrub Rate + * [15:13] reserved + * [20:16] Dcache Scrub + * [31:21] reserved + * Scrub Rates + * 00000 = Do not scrub + * 00001 = 40.00 ns + * 00010 = 80.00 ns + * 00011 = 160.00 ns + * 00100 = 320.00 ns + * 00101 = 640.00 ns + * 00110 = 1.28 us + * 00111 = 2.56 us + * 01000 = 5.12 us + * 01001 = 10.20 us + * 01011 = 41.00 us + * 01100 = 81.90 us + * 01101 = 163.80 us + * 01110 = 327.70 us + * 01111 = 655.40 us + * 10000 = 1.31 ms + * 10001 = 2.62 ms + * 10010 = 5.24 ms + * 10011 = 10.49 ms + * 10100 = 20.97 ms + * 10101 = 42.00 ms + * 10110 = 84.00 ms + * All Others = Reserved + */ + PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000, + /* DRAM Scrub Address Low Register + * F3:0x5C + * [ 0: 0] DRAM Scrubber Redirect Enable + * 0 = Do nothing + * 1 = Scrubber Corrects errors found in normal operation + * [ 5: 1] Reserved + * [31: 6] DRAM Scrub Address 31-6 + */ + PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000, + /* DRAM Scrub Address High Register + * F3:0x60 + * [ 7: 0] DRAM Scrubb Address 39-32 + * [31: 8] Reserved + */ + PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000, + }; + // for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data + /* + index: + [29: 0] DctOffset (Dram Controller Offset) + [30:30] DctAccessWrite (Dram Controller Read/Write Select) + 0 = read access + 1 = write access + [31:31] DctAccessDone (Dram Controller Access Done) + 0 = Access in progress + 1 = No access is progress + + Data: + [31: 0] DctOffsetData (Dram Controller Offset Data) + + Read: + - Write the register num to DctOffset with DctAccessWrite = 0 + - poll the DctAccessDone until it = 1 + - Read the data from DctOffsetData + Write: + - Write the data to DctOffsetData + - Write register num to DctOffset with DctAccessWrite = 1 + - poll the DctAccessDone untio it = 1 + + */ +#if 0 + static const unsigned int index_register_values[] = { + /* Output Driver Compensation Control Register + * Index: 0x00 + * [ 1: 0] CkeDrvStren (CKE Drive Strength) + * 00 = 1.0x + * 01 = 1.25x + * 10 = 1.5x (Default) + * 11 = 2.0x + * [ 3: 2] reserved + * [ 5: 4] CsOdtDrvStren (CS/ODT Drive Strength) + * 00 = 1.0x + * 01 = 1.25x + * 10 = 1.5x (Default) + * 11 = 2.0x + * [ 7: 6] reserved + * [ 9: 8] AddrCmdDrvStren (Address/Command Drive Strength) + * 00 = 1.0x + * 01 = 1.25x + * 10 = 1.5x (Default) + * 11 = 2.0x + * [11:10] reserved + * [13:12] ClkDrvStren (MEMCLK Drive Strength) + * 00 = 0.75x + * 01 = 1.0x Default) + * 10 = 1.25x + * 11 = 1.5x + * [15:14] reserved + * [17:16] DataDrvStren (Data Drive Strength) + * 00 = 0.75x + * 01 = 1.0x Default) + * 10 = 1.25x + * 11 = 1.5x + * [19:18] reserved + * [21:20] DqsDrvStren (DQS Drive Strength) + * 00 = 0.75x + * 01 = 1.0x Default) + * 10 = 1.25x + * 11 = 1.5x + * [27:22] reserved + * [29:28] ProcOdt ( Processor On-die Termination) + * 00 = 300 ohms +/- 20% + * 01 = 150 ohms +/- 20% + * 10 = 75 ohms +/- 20% + * 11 = reserved + * [31:30] reserved + */ + 0x00, 0xcfcccccc, 0x00000000, + 0x20, 0xcfcccccc, 0x00000000, + /* Write Data Timing Low Control Register + * Index 0x01 + * [ 5: 0] WrDatTimeByte0 (Write Data Byte 0 Timing Control) + * 000000 = no delay + * 000001 = 1/96 MEMCLK delay + * 000010 = 2/96 MEMCLK delay + * ... + * 101111 = 47/96 MEMCLK delay + * 11xxxx = reserved + * [ 7: 6] reserved + * [13: 8] WrDatTimeByte1 (Write Data Byte 1 Timing Control) + * [15:14] reserved + * [21:16] WrDatTimeByte2 (Write Data Byte 2 Timing Control) + * [23:22] reserved + * [29:24] WrDatTimeByte3 (Write Data Byte 3 Timing Control) + * [31:30] reserved + */ + 0x01, 0xc0c0c0c0, 0x00000000, + 0x21, 0xc0c0c0c0, 0x00000000, + /* Write Data Timing High Control Register + * Index 0x02 + * [ 5: 0] WrDatTimeByte4 (Write Data Byte 4 Timing Control) + * [ 7: 6] reserved + * [13: 8] WrDatTimeByte5 (Write Data Byte 5 Timing Control) + * [15:14] reserved + * [21:16] WrDatTimeByte6 (Write Data Byte 6 Timing Control) + * [23:22] reserved + * [29:24] WrDatTimeByte7 (Write Data Byte 7 Timing Control) + * [31:30] reserved + */ + 0x02, 0xc0c0c0c0, 0x00000000, + 0x22, 0xc0c0c0c0, 0x00000000, + + /* Write Data ECC Timing Control Register + * Index 0x03 + * [ 5: 0] WrChkTime (Write Data ECC Timing Control) + * 000000 = no delay + * 000001 = 1/96 MEMCLK delay + * 000010 = 2/96 MEMCLK delay + * ... + * 101111 = 47/96 MEMCLK delay + * 11xxxx = reserved + * [31: 6] reserved + */ + 0x03, 0x000000c0, 0x00000000, + 0x23, 0x000000c0, 0x00000000, + + /* Address Timing Control Register + * Index 0x04 + * [ 4: 0] CkeFineDelay (CKE Fine Delay) + * 00000 = no delay + * 00001 = 1/64 MEMCLK delay + * 00010 = 2/64 MEMCLK delay + * ... + * 11111 = 31/64 MEMCLK delay + * [ 5: 5] CkeSetup (CKE Setup Time) + * 0 = 1/2 MEMCLK + * 1 = 1 MEMCLK + * [ 7: 6] reserved + * [12: 8] CsOdtFineDelay (CS/ODT Fine Delay) + * 00000 = no delay + * 00001 = 1/64 MEMCLK delay + * 00010 = 2/64 MEMCLK delay + * ... + * 11111 = 31/64 MEMCLK delay + * [13:13] CsOdtSetup (CS/ODT Setup Time) + * 0 = 1/2 MEMCLK + * 1 = 1 MEMCLK + * [15:14] reserved + * [20:16] AddrCmdFineDelay (Address/Command Fine Delay) + * 00000 = no delay + * 00001 = 1/64 MEMCLK delay + * 00010 = 2/64 MEMCLK delay + * ... + * 11111 = 31/64 MEMCLK delay + * [21:21] AddrCmdSetup (Address/Command Setup Time) + * 0 = 1/2 MEMCLK + * 1 = 1 MEMCLK + * [31:22] reserved + */ + 0x04, 0xffc0c0c0, 0x00000000, + 0x24, 0xffc0c0c0, 0x00000000, + + /* Read DQS Timing Low Control Register + * Index 0x05 + * [ 5: 0] RdDqsTimeByte0 (Read DQS Byte 0 Timing Control) + * 000000 = no delay + * 000001 = 1/96 MEMCLK delay + * 000010 = 2/96 MEMCLK delay + * ... + * 101111 = 47/96 MEMCLK delay + * 11xxxx = reserved + * [ 7: 6] reserved + * [13: 8] RdDqsTimeByte1 (Read DQS Byte 1 Timing Control) + * [15:14] reserved + * [21:16] RdDqsTimeByte2 (Read DQS Byte 2 Timing Control) + * [23:22] reserved + * [29:24] RdDqsTimeByte3 (Read DQS Byte 3 Timing Control) + * [31:30] reserved + */ + 0x05, 0xc0c0c0c0, 0x00000000, + 0x25, 0xc0c0c0c0, 0x00000000, + + /* Read DQS Timing High Control Register + * Index 0x06 + * [ 5: 0] RdDqsTimeByte4 (Read DQS Byte 4 Timing Control) + * [ 7: 6] reserved + * [13: 8] RdDqsTimeByte5 (Read DQS Byte 5 Timing Control) + * [15:14] reserved + * [21:16] RdDqsTimeByte6 (Read DQS Byte 6 Timing Control) + * [23:22] reserved + * [29:24] RdDqsTimeByte7 (Read DQS Byte 7 Timing Control) + * [31:30] reserved + */ + 0x06, 0xc0c0c0c0, 0x00000000, + 0x26, 0xc0c0c0c0, 0x00000000, + + /* Read DQS ECC Timing Control Register + * Index 0x07 + * [ 5: 0] RdDqsTimeCheck (Read DQS ECC Timing Control) + * 000000 = no delay + * 000001 = 1/96 MEMCLK delay + * 000010 = 2/96 MEMCLK delay + * ... + * 101111 = 47/96 MEMCLK delay + * 11xxxx = reserved + * [31: 6] reserved + */ + 0x07, 0x000000c0, 0x00000000, + 0x27, 0x000000c0, 0x00000000, + + /* DQS Receiver Enable Timing Control Register + * Index 0x10, 0x13, 0x16, 0x19, + * [ 7: 0] Dqs RcvEnDelay (DQS Receiver Enable Delay) + * 0x00 = 0 ps + * 0x01 = 50 ps + * 0x02 = 100 ps + * ... + * 0xae = 8.7 ns + * 0xaf-0xff = reserved + * [31: 6] reserved + */ + 0x10, 0x000000ff, 0x00000000, + 0x13, 0x000000ff, 0x00000000, + 0x16, 0x000000ff, 0x00000000, + 0x19, 0x000000ff, 0x00000000, + 0x30, 0x000000ff, 0x00000000, + 0x33, 0x000000ff, 0x00000000, + 0x36, 0x000000ff, 0x00000000, + 0x39, 0x000000ff, 0x00000000, + }; +#endif + + int i; + int max; + +#if 1 + if (!controller_present(ctrl)) { +// print_debug("No memory controller present\r\n"); + sysinfo->ctrl_present[ctrl->node_id] = 0; + return; + } +#endif + sysinfo->ctrl_present[ctrl->node_id] = 1; + + print_spew("setting up CPU"); + print_spew_hex8(ctrl->node_id); + print_spew(" northbridge registers\r\n"); + max = sizeof(register_values)/sizeof(register_values[0]); + for(i = 0; i < max; i += 3) { + device_t dev; + unsigned where; + unsigned long reg; + dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; + where = register_values[i] & 0xff; + reg = pci_read_config32(dev, where); + reg &= register_values[i+1]; + reg |= register_values[i+2]; + pci_write_config32(dev, where, reg); + } + +#if 0 + // for index regs + max = sizeof(index_register_values)/sizeof(index_register_values[0]); + for(i = 0; i < max; i += 3) { + unsigned long reg; + unsigned index; + index = register_values[i]; + reg = pci_read_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index); + reg &= register_values[i+1]; + reg |= register_values[i+2]; + pci_write_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index, reg); + } +#endif + + print_spew("done.\r\n"); +} + +static int is_dual_channel(const struct mem_controller *ctrl) +{ + uint32_t dcl; + dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + return dcl & DCL_Width128; +} + +static int is_registered(const struct mem_controller *ctrl) +{ + /* Test to see if we are dealing with registered SDRAM. + * If we are not registered we are unbuffered. + * This function must be called after spd_handle_unbuffered_dimms. + */ + uint32_t dcl; + dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + return !(dcl & DCL_UnBuffDimm); +} + +static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) +{ + /* Calculate the log base 2 size of a DIMM in bits */ + int value; + sz->per_rank = 0; + sz->rows = 0; + sz->col = 0; + sz->rank = 0; + + value = spd_read_byte(device, SPD_ROW_NUM); /* rows */ + if (value < 0) goto hw_err; + if ((value & 0xff) == 0) goto val_err; // max is 16 ? + sz->per_rank += value & 0xff; + sz->rows = value & 0xff; + + value = spd_read_byte(device, SPD_COL_NUM); /* columns */ + if (value < 0) goto hw_err; + if ((value & 0xff) == 0) goto val_err; //max is 11 + sz->per_rank += value & 0xff; + sz->col = value & 0xff; + + value = spd_read_byte(device, SPD_BANK_NUM); /* banks */ + if (value < 0) goto hw_err; + if ((value & 0xff) == 0) goto val_err; + sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3 + sz->per_rank += sz->bank; + + /* Get the module data width and convert it to a power of two */ + value = spd_read_byte(device, SPD_DATA_WIDTH); + if (value < 0) goto hw_err; + value &= 0xff; + if ((value != 72) && (value != 64)) goto val_err; + sz->per_rank += log2(value) - 3; //64 bit So another 3 lines + + /* How many ranks? */ + value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK); /* number of physical banks */ + if (value < 0) goto hw_err; +// value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; + value &= SPD_MOD_ATTRIB_RANK_NUM_MASK; + value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4 + /* + rank == 1 only one rank or say one side + rank == 2 two side , and two ranks + rank == 4 two side , and four ranks total + Some one side two ranks, because of stacked + */ + if ((value != 1) && (value != 2) && (value != 4 )) { + goto val_err; + } + sz->rank = value; + + /* verify if per_rank is equal byte 31 + it has the DIMM size as a multiple of 128MB. + */ + value = spd_read_byte(device, SPD_RANK_SIZE); + if (value < 0) goto hw_err; + value &= 0xff; + value = log2(value); + if(value <=4 ) value += 8; // add back to 1G to high + value += (27-5); // make 128MB to the real lines + if( value != (sz->per_rank)) { + print_err("Bad RANK Size --\r\n"); + goto val_err; + } + + goto out; + + val_err: + die("Bad SPD value\r\n"); + /* If an hw_error occurs report that I have no memory */ +hw_err: + sz->per_rank = 0; + sz->rows = 0; + sz->col = 0; + sz->bank = 0; + sz->rank = 0; + out: + return; +} + +static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index, int is_Width128) +{ + uint32_t base0, base1; + + + /* For each base register. + * Place the dimm size in 32 MB quantities in the bits 31 - 21. + * The initialize dimm size is in bits. + * Set the base enable bit0. + */ + + base0 = base1 = 0; + + /* Make certain side1 of the dimm is at least 128MB */ + if (sz->per_rank >= 27) { + base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1; + } + + /* Make certain side2 of the dimm is at least 128MB */ + if (sz->rank > 1) { // 2 ranks or 4 ranks + base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1; + } + + /* Double the size if we are using dual channel memory */ + if (is_Width128) { + base0 = (base0 << 1) | (base0 & 1); + base1 = (base1 << 1) | (base1 & 1); + } + + /* Clear the reserved bits */ + base0 &= ~0xe007fffe; + base1 &= ~0xe007fffe; + + /* Set the appropriate DIMM base address register */ + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); +#if QRANK_DIMM_SUPPORT == 1 + if(sz->rank == 4) { + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); + } +#endif + + /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/ + if (base0) { + uint32_t dword; + uint32_t ClkDis0; +#if CPU_SOCKET_TYPE == 0x10 /* L1 */ + ClkDis0 = DTL_MemClkDis0; +#else + #if CPU_SOCKET_TYPE == 0x11 /* AM2 */ + ClkDis0 = DTL_MemClkDis0_AM2; + #endif +#endif + + dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A + dword &= ~(ClkDis0 >> index); +#if QRANK_DIMM_SUPPORT == 1 + if(sz->rank == 4) { + dword &= ~(ClkDis0 >> (index+2)); + } +#endif + pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword); + + if (is_Width128) { //Channel B + dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC); + dword &= ~(ClkDis0 >> index); +#if QRANK_DIMM_SUPPORT == 1 + if(sz->rank == 4) { + dword &= ~(ClkDis0 >> (index+2)); + } +#endif + pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword); + } + + } +} + +/* row col bank for 64 bit + 0: 13 9 2 :128M + 1: 13 10 2 :256M + 2: 14 10 2 :512M + 3: 13 11 2 :512M + 4: 13 10 3 :512M + 5: 14 10 3 :1G + 6: 14 11 2 :1G + 7: 15 10 3 :2G + 8: 14 11 3 :2G + 9: 15 11 3 :4G + 10: 16 10 3 :4G + 11: 16 11 3 :8G +*/ + +static void set_dimm_cs_map(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index) +{ + static const uint8_t cs_map_aaa[24] = { + /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ + //Bank2 + 0, 1, 3, + 0, 2, 6, + 0, 0, 0, + 0, 0, 0, + //Bank3 + 0, 4, 0, + 0, 5, 8, + 0, 7, 9, + 0,10,11, + }; + + uint32_t map; + + map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); + map &= ~(0xf << (index * 4)); +#if QRANK_DIMM_SUPPORT == 1 + if(sz->rank == 4) { + map &= ~(0xf << ( (index + 2) * 4)); + } +#endif + + /* Make certain side1 of the dimm is at least 128MB */ + if (sz->per_rank >= 27) { + unsigned temp_map; + temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ]; + map |= temp_map << (index*4); +#if QRANK_DIMM_SUPPORT == 1 + if(sz->rank == 4) { + map |= temp_map << ( (index + 2) * 4); + } +#endif + } + + pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map); + +} + +static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo) +{ + int i; + + for(i = 0; i < DIMM_SOCKETS; i++) { + struct dimm_size *sz = &(meminfo->sz[i]); + if (!(dimm_mask & (1 << i))) { + continue; + } + spd_get_dimm_size(ctrl->channel0[i], sz); + if (sz->per_rank == 0) { + return -1; /* Report SPD error */ + } + set_dimm_size(ctrl, sz, i, meminfo->is_Width128); + set_dimm_cs_map (ctrl, sz, i); + } + return dimm_mask; +} + +static void route_dram_accesses(const struct mem_controller *ctrl, + unsigned long base_k, unsigned long limit_k) +{ + /* Route the addresses to the controller node */ + unsigned node_id; + unsigned limit; + unsigned base; + unsigned index; + unsigned limit_reg, base_reg; + device_t device; + + node_id = ctrl->node_id; + index = (node_id << 3); + limit = (limit_k << 2); + limit &= 0xffff0000; + limit -= 0x00010000; + limit |= ( 0 << 8) | (node_id << 0); + base = (base_k << 2); + base &= 0xffff0000; + base |= (0 << 8) | (1<<1) | (1<<0); + + limit_reg = 0x44 + index; + base_reg = 0x40 + index; + for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) { + pci_write_config32(device, limit_reg, limit); + pci_write_config32(device, base_reg, base); + } +} + +static void set_top_mem(unsigned tom_k, unsigned hole_startk) +{ + /* Error if I don't have memory */ + if (!tom_k) { + die("No memory?"); + } + + /* Report the amount of memory. */ + print_debug("RAM: 0x"); + print_debug_hex32(tom_k); + print_debug(" KB\r\n"); + + msr_t msr; + if(tom_k > (4*1024*1024)) { + /* Now set top of memory */ + msr.lo = (tom_k & 0x003fffff) << 10; + msr.hi = (tom_k & 0xffc00000) >> 22; + wrmsr(TOP_MEM2, msr); + } + + /* Leave a 64M hole between TOP_MEM and TOP_MEM2 + * so I can see my rom chip and other I/O devices. + */ + if (tom_k >= 0x003f0000) { +#if HW_MEM_HOLE_SIZEK != 0 + if(hole_startk != 0) { + tom_k = hole_startk; + } else +#endif + tom_k = 0x3f0000; + } + msr.lo = (tom_k & 0x003fffff) << 10; + msr.hi = (tom_k & 0xffc00000) >> 22; + wrmsr(TOP_MEM, msr); +} + +static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128) +{ + /* 35 - 27 */ + + static const uint8_t csbase_low_f0_shift[] = { + /* 128MB */ (14 - (13-5)), + /* 256MB */ (15 - (13-5)), + /* 512MB */ (15 - (13-5)), + /* 512MB */ (16 - (13-5)), + /* 512MB */ (16 - (13-5)), + /* 1GB */ (16 - (13-5)), + /* 1GB */ (16 - (13-5)), + /* 2GB */ (16 - (13-5)), + /* 2GB */ (17 - (13-5)), + /* 4GB */ (17 - (13-5)), + /* 4GB */ (16 - (13-5)), + /* 8GB */ (17 - (13-5)), + }; + + /* cs_base_high is not changed */ + + uint32_t csbase_inc; + int chip_selects, index; + int bits; + unsigned common_size; + unsigned common_cs_mode; + uint32_t csbase, csmask; + + /* See if all of the memory chip selects are the same size + * and if so count them. + */ + chip_selects = 0; + common_size = 0; + common_cs_mode = 0xff; + for(index = 0; index < 8; index++) { + unsigned size; + unsigned cs_mode; + uint32_t value; + + value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + + /* Is it enabled? */ + if (!(value & 1)) { + continue; + } + chip_selects++; + size = (value >> 19) & 0x3ff; + if (common_size == 0) { + common_size = size; + } + /* The size differed fail */ + if (common_size != size) { + return 0; + } + + value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); + cs_mode =( value >> ((index>>1)*4)) & 0xf; + if(common_cs_mode == 0xff) { + common_cs_mode = cs_mode; + } + /* The cs_mode differed fail */ + if(common_cs_mode != cs_mode) { + return 0; + } + } + + /* Chip selects can only be interleaved when there is + * more than one and their is a power of two of them. + */ + bits = log2(chip_selects); + if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { //chip_selects max = 8 + return 0; + } + + /* Find the bits of csbase that we need to interleave on */ + csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]); + if(is_Width128) { + csbase_inc <<=1; + } + + + /* Compute the initial values for csbase and csbask. + * In csbase just set the enable bit and the base to zero. + * In csmask set the mask bits for the size and page level interleave. + */ + csbase = 0 | 1; + csmask = (((common_size << bits) - 1) << 19); + csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc); + for(index = 0; index < 8; index++) { + uint32_t value; + + value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + /* Is it enabled? */ + if (!(value & 1)) { + continue; + } + pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase); + if((index & 1) == 0) { //only have 4 CSMASK + pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask); + } + csbase += csbase_inc; + } + + print_debug("Interleaved\r\n"); + + /* Return the memory size in K */ + return common_size << ((27-10) + bits); +} +static unsigned long order_chip_selects(const struct mem_controller *ctrl) +{ + unsigned long tom; + + /* Remember which registers we have used in the high 8 bits of tom */ + tom = 0; + for(;;) { + /* Find the largest remaining canidate */ + unsigned index, canidate; + uint32_t csbase, csmask; + unsigned size; + csbase = 0; + canidate = 0; + for(index = 0; index < 8; index++) { + uint32_t value; + value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + + /* Is it enabled? */ + if (!(value & 1)) { + continue; + } + + /* Is it greater? */ + if (value <= csbase) { + continue; + } + + /* Has it already been selected */ + if (tom & (1 << (index + 24))) { + continue; + } + /* I have a new canidate */ + csbase = value; + canidate = index; + } + /* See if I have found a new canidate */ + if (csbase == 0) { + break; + } + + /* Remember the dimm size */ + size = csbase >> 19; + + /* Remember I have used this register */ + tom |= (1 << (canidate + 24)); + + /* Recompute the cs base register value */ + csbase = (tom << 19) | 1; + + /* Increment the top of memory */ + tom += size; + + /* Compute the memory mask */ + csmask = ((size -1) << 19); + csmask |= 0x3fe0; /* For now don't optimize */ + + /* Write the new base register */ + pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase); + /* Write the new mask register */ + if((canidate & 1) == 0) { //only have 4 CSMASK + pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate>>1) << 2), csmask); + } + + } + /* Return the memory size in K */ + return (tom & ~0xff000000) << (27-10); +} + +unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id) +{ + unsigned node_id; + unsigned end_k; + /* Find the last memory address used */ + end_k = 0; + for(node_id = 0; node_id < max_node_id; node_id++) { + uint32_t limit, base; + unsigned index; + index = node_id << 3; + base = pci_read_config32(ctrl->f1, 0x40 + index); + /* Only look at the limit if the base is enabled */ + if ((base & 3) == 3) { + limit = pci_read_config32(ctrl->f1, 0x44 + index); + end_k = ((limit + 0x00010000) & 0xffff0000) >> 2; + } + } + return end_k; +} + +static void order_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo) +{ + unsigned long tom_k, base_k; + + if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { + tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); + } else { + print_debug("Interleaving disabled\r\n"); + tom_k = 0; + } + if (!tom_k) { + tom_k = order_chip_selects(ctrl); + } + /* Compute the memory base address */ + base_k = memory_end_k(ctrl, ctrl->node_id); + tom_k += base_k; + route_dram_accesses(ctrl, base_k, tom_k); + set_top_mem(tom_k, 0); +} + +static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask, struct mem_info *meminfo) +{ + print_debug("disabling dimm"); + print_debug_hex8(index); + print_debug("\r\n"); + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0); + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); +#if QRANK_DIMM_SUPPORT == 1 + if(meminfo->sz[index].rank == 4) { + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), 0); + pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), 0); + } +#endif + + dimm_mask &= ~(1 << index); + return dimm_mask; +} + +static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo) +{ + int i; + uint32_t registered; + uint32_t dcl; + registered = 0; + for(i = 0; (i < DIMM_SOCKETS); i++) { + int value; + if (!(dimm_mask & (1 << i))) { + continue; + } + value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_TYPE); + if (value < 0) { + return -1; + } + /* Registered dimm ? */ + value &= 0x3f; + if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) { + //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)? + registered |= (1<f2, DRAM_CONFIG_LOW); + dcl &= ~DCL_UnBuffDimm; + meminfo->is_registered = 1; + if (!registered) { + dcl |= DCL_UnBuffDimm; + meminfo->is_registered = 0; + } + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + +#if 1 + if (meminfo->is_registered) { + print_debug("Registered\r\n"); + } else { + print_debug("Unbuffered\r\n"); + } +#endif + return dimm_mask; +} + +static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) +{ + unsigned dimm_mask; + int i; + dimm_mask = 0; + for(i = 0; i < DIMM_SOCKETS; i++) { + int byte; + unsigned device; + device = ctrl->channel0[i]; + if (device) { + byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */ + if (byte == SPD_MEM_TYPE_SDRAM_DDR2) { + dimm_mask |= (1 << i); + } + } + device = ctrl->channel1[i]; + if (device) { + byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE); + if (byte == SPD_MEM_TYPE_SDRAM_DDR2) { + dimm_mask |= (1 << (i + DIMM_SOCKETS)); + } + } + } + return dimm_mask; +} + +static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo) +{ + int i; + uint32_t nbcap; + /* SPD addresses to verify are identical */ + static const uint8_t addresses[] = { + 2, /* Type should be DDR2 SDRAM */ + 3, /* *Row addresses */ + 4, /* *Column addresses */ + 5, /* *Number of DIMM Ranks */ + 6, /* *Module Data Width*/ + 9, /* *Cycle time at highest CAS Latency CL=X */ + 11, /* *DIMM Conf Type */ + 13, /* *Pri SDRAM Width */ + 17, /* *Logical Banks */ + 18, /* *Supported CAS Latencies */ + 20, /* *DIMM Type Info */ + 21, /* *SDRAM Module Attributes */ + 23, /* *Cycle time at CAS Latnecy (CLX - 1) */ + 26, /* *Cycle time at CAS Latnecy (CLX - 2) */ + 27, /* *tRP Row precharge time */ + 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ + 29, /* *tRCD RAS to CAS */ + 30, /* *tRAS Activate to Precharge */ + 36, /* *Write recovery time (tWR) */ + 37, /* *Internal write to read command delay (tRDP) */ + 38, /* *Internal read to precharge commanfd delay (tRTP) */ + 41, /* *Extension of Byte 41 tRC and Byte 42 tRFC */ + 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */ + 42, /* *Minimum Auto Refresh Command Time(Trfc) */ + }; + /* If the dimms are not in pairs do not do dual channels */ + if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) != + ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { + goto single_channel; + } + /* If the cpu is not capable of doing dual channels don't do dual channels */ + nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + if (!(nbcap & NBCAP_128Bit)) { + goto single_channel; + } + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { + unsigned device0, device1; + int value0, value1; + int j; + /* If I don't have a dimm skip this one */ + if (!(dimm_mask & (1 << i))) { + continue; + } + device0 = ctrl->channel0[i]; + device1 = ctrl->channel1[i]; + for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + unsigned addr; + addr = addresses[j]; + value0 = spd_read_byte(device0, addr); + if (value0 < 0) { + return -1; + } + value1 = spd_read_byte(device1, addr); + if (value1 < 0) { + return -1; + } + if (value0 != value1) { + goto single_channel; + } + } + } + print_spew("Enabling dual channel memory\r\n"); + uint32_t dcl; + dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses + 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */ + dcl |= DCL_Width128; + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + meminfo->is_Width128 = 1; + return dimm_mask; + single_channel: + dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS)); + meminfo->is_Width128 = 0; + return dimm_mask; +} + +struct mem_param { + uint16_t cycle_time; + uint8_t divisor; /* In 1/40 ns increments */ + uint8_t TrwtTO; + uint8_t Twrrd; + uint8_t Twrwr; + uint8_t Trdrd; + uint8_t DcqByPassMax; + uint32_t dch_memclk; + char name[9]; +}; + + static const struct mem_param speed[] = { + { + .name = "200Mhz\r\n", + .cycle_time = 0x500, + .divisor = 200, // how many 1/40ns per clock + .dch_memclk = DCH_MemClkFreq_200MHz, //0 + .TrwtTO = 7, + .Twrrd = 2, + .Twrwr = 2, + .Trdrd = 3, + .DcqByPassMax = 4, + + }, + { + .name = "266Mhz\r\n", + .cycle_time = 0x375, + .divisor = 150, //???? + .dch_memclk = DCH_MemClkFreq_266MHz, //1 + .TrwtTO = 7, + .Twrrd = 2, + .Twrwr = 2, + .Trdrd = 3, + .DcqByPassMax = 4, + }, + { + .name = "333Mhz\r\n", + .cycle_time = 0x300, + .divisor = 120, + .dch_memclk = DCH_MemClkFreq_333MHz, //2 + .TrwtTO = 7, + .Twrrd = 2, + .Twrwr = 2, + .Trdrd = 3, + .DcqByPassMax = 4, + + }, + { + .name = "400Mhz\r\n", + .cycle_time = 0x250, + .divisor = 100, + .dch_memclk = DCH_MemClkFreq_400MHz,//3 + .TrwtTO = 7, + .Twrrd = 2, + .Twrwr = 2, + .Trdrd = 3, + .DcqByPassMax = 4, + }, + { + .cycle_time = 0x000, + }, + }; + +static const struct mem_param *get_mem_param(unsigned min_cycle_time) +{ + + const struct mem_param *param; + for(param = &speed[0]; param->cycle_time ; param++) { + if (min_cycle_time > (param+1)->cycle_time) { + break; + } + } + if (!param->cycle_time) { + die("min_cycle_time to low"); + } + print_spew(param->name); +#ifdef DRAM_MIN_CYCLE_TIME + print_debug(param->name); +#endif + return param; +} + +static uint8_t get_exact_divisor(int i, uint8_t divisor) +{ + //input divisor could be 200(200), 150(266), 120(333), 100 (400) + static const uint8_t dv_a[] = { + /* 200 266 333 400 */ + /*4 */ 250, 250, 250, 250, + /*5 */ 200, 200, 200, 100, + /*6 */ 200, 166, 166, 100, + /*7 */ 200, 171, 142, 100, + + /*8 */ 200, 150, 125, 100, + /*9 */ 200, 156, 133, 100, + /*10*/ 200, 160, 120, 100, + /*11*/ 200, 163, 127, 100, + + /*12*/ 200, 150, 133, 100, + /*13*/ 200, 153, 123, 100, + /*14*/ 200, 157, 128, 100, + /*15*/ 200, 160, 120, 100, + }; + + unsigned fid_cur; + int index; + + msr_t msr; + msr = rdmsr(0xc0010042); + fid_cur = msr.lo & 0x3f; + + index = fid_cur>>1; + + if(index>12) return divisor; + + if(i>3) return divisor; + + return dv_a[index * 4+i]; + +} + +struct spd_set_memclk_result { + const struct mem_param *param; + long dimm_mask; +}; + +static unsigned convert_to_linear(unsigned value) +{ + static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 }; + unsigned valuex; + + /* We need to convert value to more readable */ + if((value & 0xf) < 10) { //no .25, .33, .66, .75 + value <<= 4; + } else { + valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10]; + value = valuex; + } + return value; +} + +static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo) +{ + /* Compute the minimum cycle time for these dimms */ + struct spd_set_memclk_result result; + unsigned min_cycle_time, min_latency, bios_cycle_time; + int i; + uint32_t value; + + static const uint8_t latency_indicies[] = { 25, 23, 9 }; + + static const uint16_t min_cycle_times[] = { // use full speed to compare + [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */ + [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */ + [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */ + [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */ + }; + + + value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; + bios_cycle_time = min_cycle_times[ + read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; + if (bios_cycle_time > min_cycle_time) { + min_cycle_time = bios_cycle_time; + } + min_latency = 3; + + print_tx("1 min_cycle_time:", min_cycle_time); + + /* Compute the least latency with the fastest clock supported + * by both the memory controller and the dimms. + */ + for(i = 0; i < DIMM_SOCKETS; i++) { + int new_cycle_time, new_latency; + int index; + int latencies; + int latency; + + if (!(dimm_mask & (1 << i))) { + continue; + } + + /* First find the supported CAS latencies + * Byte 18 for DDR SDRAM is interpreted: + * bit 3 == CAS Latency = 3 + * bit 4 == CAS Latency = 4 + * bit 5 == CAS Latency = 5 + * bit 6 == CAS Latency = 6 + */ + new_cycle_time = 0x500; + new_latency = 6; + + latencies = spd_read_byte(ctrl->channel0[i], SPD_CAS_LAT); + if (latencies <= 0) continue; + + print_tx("i:",i); + print_tx("\tlatencies:", latencies); + /* Compute the lowest cas latency supported */ + latency = log2(latencies) - 2; + + /* Loop through and find a fast clock with a low latency */ + for(index = 0; index < 3; index++, latency++) { + int value; + if ((latency < 3) || (latency > 6) || + (!(latencies & (1 << latency)))) { + continue; + } + value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + if (value < 0) { + goto hw_error; + } + print_tx("\tindex:", index); + print_tx("\t\tlatency:", latency); + print_tx("\t\tvalue1:", value); + + value = convert_to_linear(value); + + print_tx("\t\tvalue2:", value); + + /* Only increase the latency if we decreas the clock */ + if (value >= min_cycle_time ) { + if(value < new_cycle_time) { + new_cycle_time = value; + new_latency = latency; + } else if (value == new_cycle_time) { + if(new_latency > latency) { + new_latency = latency; + } + } + } + print_tx("\t\tnew_cycle_time:", new_cycle_time); + print_tx("\t\tnew_latency:", new_latency); + + } + if (new_latency > 6){ + continue; + } + /* Does min_latency need to be increased? */ + if (new_cycle_time > min_cycle_time) { + min_cycle_time = new_cycle_time; + } + /* Does min_cycle_time need to be increased? */ + if (new_latency > min_latency) { + min_latency = new_latency; + } + + print_tx("2 min_cycle_time:", min_cycle_time); + print_tx("2 min_latency:", min_latency); + } + /* Make a second pass through the dimms and disable + * any that cannot support the selected memclk and cas latency. + */ + + print_tx("3 min_cycle_time:", min_cycle_time); + print_tx("3 min_latency:", min_latency); + + for(i = 0; (i < DIMM_SOCKETS) && (ctrl->channel0[i]); i++) { + int latencies; + int latency; + int index; + int value; + if (!(dimm_mask & (1 << i))) { + continue; + } + latencies = spd_read_byte(ctrl->channel0[i], SPD_CAS_LAT); + if (latencies < 0) goto hw_error; + if (latencies == 0) { + continue; +// goto dimm_err; + } + + /* Compute the lowest cas latency supported */ + latency = log2(latencies) -2; + + /* Walk through searching for the selected latency */ + for(index = 0; index < 3; index++, latency++) { + if (!(latencies & (1 << latency))) { + continue; + } + if (latency == min_latency) + break; + } + /* If I can't find the latency or my index is bad error */ + if ((latency != min_latency) || (index >= 3)) { + goto dimm_err; + } + + /* Read the min_cycle_time for this latency */ + value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + if (value < 0) goto hw_error; + + value = convert_to_linear(value); + /* All is good if the selected clock speed + * is what I need or slower. + */ + if (value <= min_cycle_time) { + continue; + } + /* Otherwise I have an error, disable the dimm */ + dimm_err: + dimm_mask = disable_dimm(ctrl, i, dimm_mask, meminfo); + } + + print_tx("4 min_cycle_time:", min_cycle_time); + + /* Now that I know the minimum cycle time lookup the memory parameters */ + result.param = get_mem_param(min_cycle_time); + + /* Update DRAM Config High with our selected memory speed */ + value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT); + + value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); + + print_debug(result.param->name); + + /* Update DRAM Timing Low with our selected cas latency */ + value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); + value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT; + pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); + + result.dimm_mask = dimm_mask; + return result; + hw_error: + result.param = (const struct mem_param *)0; + result.dimm_mask = -1; + return result; +} + +static unsigned convert_to_1_4(unsigned value) +{ + static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 }; + unsigned valuex; + + /* We need to convert value to more readable */ + valuex = fraction [value & 0x7]; + return valuex; +} +static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + unsigned clocks, old_clocks; + uint32_t dtl; + int value; + int value2; + value = spd_read_byte(ctrl->channel0[i], SPD_TRC); + if (value < 0) return -1; + + value2 = spd_read_byte(ctrl->channel0[i], SPD_TRC -1); + value <<= 2; + value += convert_to_1_4(value2>>4); + + value *=10; + + clocks = (value + param->divisor - 1)/param->divisor; + + if (clocks < DTL_TRC_MIN) { + clocks = DTL_TRC_MIN; + } + if (clocks > DTL_TRC_MAX) { + return 0; + } + + dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE; + if (old_clocks >= clocks) { //?? someone did it + // clocks = old_clocks; + return 1; + } + dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT); + dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT); + pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + return 1; +} + +static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo) +{ + unsigned clocks, old_clocks; + uint32_t dth; + int value; + +#if 0 + int value2; + + value = spd_read_byte(ctrl->channel0[i], SPD_TRFC); + if (value < 0) return -1; + + value2 = spd_read_byte(ctrl->channel0[i], SPD_TRC -1); + if(value2 & 1) value += 256; + value <<= 2; + value += convert_to_1_4(value2>>1); + + if (value == 0) { + value = param->tRFC; + } + value *= 10; + clocks = (value + param->divisor - 1)/param->divisor; +#endif + //get the cs_size --> logic dimm size + value = spd_read_byte(ctrl->channel0[i], SPD_PRI_WIDTH); + if (value < 0) { + return -1; + } + + value = 6 - log2(value); //4-->4, 8-->3, 16-->2 + + clocks = meminfo->sz[i].per_rank - 27 + 2 - value; + + dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + + old_clocks = ((dth >> (DTH_TRFC0_SHIFT+i*3)) & DTH_TRFC_MASK); + if (old_clocks >= clocks) { // some one did it? +// clocks = old_clocks; + return 1; + } + dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT+i*3)); + dth |= clocks << (DTH_TRFC0_SHIFT+i*3); + pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + return 1; +} + +static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, + unsigned TT_REG, + unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX ) +{ + unsigned clocks, old_clocks; + uint32_t dtl; + int value; + value = spd_read_byte(ctrl->channel0[i], SPD_TT); //already in 1/4 ns + if (value < 0) return -1; + value *=10; + clocks = (value + param->divisor -1)/param->divisor; + if (clocks < TT_MIN) { + clocks = TT_MIN; + } + if (clocks > TT_MAX) { + return 0; + } + dtl = pci_read_config32(ctrl->f2, TT_REG); + + old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE; + if (old_clocks >= clocks) { //some one did it? +// clocks = old_clocks; + return 1; + } + dtl &= ~(TT_MASK << TT_SHIFT); + dtl |= ((clocks - TT_BASE) << TT_SHIFT); + pci_write_config32(ctrl->f2, TT_REG, dtl); + return 1; +} + +static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX); +} + +static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX); +} + +static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + unsigned clocks, old_clocks; + uint32_t dtl; + int value; + value = spd_read_byte(ctrl->channel0[i], SPD_TRAS); //in 1 ns + if (value < 0) return -1; + print_tx("update_dimm_Tras: 0 value=", value); + + value<<=2; //convert it to in 1/4ns + + value *= 10; + print_tx("update_dimm_Tras: 1 value=", value); + + clocks = (value + param->divisor - 1)/param->divisor; + print_tx("update_dimm_Tras: divisor=", param->divisor); + print_tx("update_dimm_Tras: clocks=", clocks); + if (clocks < DTL_TRAS_MIN) { + clocks = DTL_TRAS_MIN; + } + if (clocks > DTL_TRAS_MAX) { + return 0; + } + dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE; + if (old_clocks >= clocks) { // someone did it? +// clocks = old_clocks; + return 1; + } + dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT); + dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT); + pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + return 1; +} + +static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX); +} + +static int update_dimm_Trtp(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo) +{ + //need to figure if it is 32 byte burst or 64 bytes burst + int offset = 2; + if(!meminfo->is_Width128) { + uint32_t dword; + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + if((dword & DCL_BurstLength32)) offset = 0; + } + return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset); +} + + +static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX); +} + + +static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + uint32_t dth, dth_old; + int value; + value = spd_read_byte(ctrl->channel0[i], SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us.... + if (value < 0) return -1; + + if(value == 1 ) { + value = 3; + } else { + value = 2; + } + + dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + + dth_old = dth; + dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); + dth |= (value << DTH_TREF_SHIFT); + if(dth_old != dth) { + pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + } + return 1; +} + +static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) +{ +#if QRANK_DIMM_SUPPRT == 1 + int value; + int i; + + + if(!(meminfo->is_registered)) return; + + value = 0; + + for(i = 0; i < DIMM_SOCKETS; i++) { + if (!(dimm_mask & (1 << i))) { + continue; + } + + if(meminfo->sz.rank == 4) { + value = 1; + break; + } + } + + if(value == 1) { + uint32_t dch; + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch |= DCH_FourRankRDimm; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif +} + + +static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, struct mem_info *meminfo) +{ + int i; + + uint32_t mask_x4; + uint32_t mask_x16; + uint32_t mask_single_rank; + uint32_t mask_page_1k; + int value; +#if QRANK_DIMM_SUPPORT == 1 + int rank; +#endif + + long dimm_mask = meminfo->dimm_mask; + + + mask_x4 = 0; + mask_x16 = 0; + mask_single_rank = 0; + mask_page_1k = 0; + + for(i = 0; i < DIMM_SOCKETS; i++) { + + if (!(dimm_mask & (1 << i))) { + continue; + } + + if(meminfo->sz[i].rank == 1) { + mask_single_rank |= 1<sz[i].col==10) { + mask_page_1k |= 1<channel0[i], SPD_PRI_WIDTH); + + #if QRANK_DIMM_SUPPORT == 1 + rank = meminfo->sz[i].rank; + #endif + + if(value==4) { + mask_x4 |= (1<x4_mask= mask_x4; + meminfo->x16_mask = mask_x16; + + meminfo->single_rank_mask = mask_single_rank; + meminfo->page_1k_mask = mask_page_1k; + + return mask_x4; + +} + + +static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) +{ + uint32_t dcl; + dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl &= ~(DCL_X4Dimm_MASK<x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT); + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); +} + +static int count_ones(uint32_t dimm_mask) +{ + int dimms; + unsigned index; + dimms = 0; + for(index = 0; index < DIMM_SOCKETS; index++, dimm_mask>>=1) { + if (dimm_mask & 1) { + dimms++; + } + } + return dimms; +} + + +static void set_DramTerm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) +{ + uint32_t dcl; + unsigned odt; + odt = 1; // 75 ohms + + if(param->divisor == 100) { //DDR2 800 + if(meminfo->is_Width128) { + if(count_ones(meminfo->dimm_mask & 0x0f)==2) { + odt = 3; //50 ohms + } + } + + } + dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl &= ~(DCL_DramTerm_MASK<f2, DRAM_CONFIG_LOW, dcl); +} + + +static void set_ecc(const struct mem_controller *ctrl,const struct mem_param *param, long dimm_mask, struct mem_info *meminfo) +{ + int i; + int value; + + uint32_t dcl, nbcap; + nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl &= ~DCL_DimmEccEn; + if (nbcap & NBCAP_ECC) { + dcl |= DCL_DimmEccEn; + } + if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + dcl &= ~DCL_DimmEccEn; + } + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + + meminfo->is_ecc = 1; + if(!(dcl & DCL_DimmEccEn)) { + meminfo->is_ecc = 0; + return; // already disabled the ECC, so don't need to read SPD any more + } + + for(i = 0; i < DIMM_SOCKETS; i++) { + + if (!(dimm_mask & (1 << i))) { + continue; + } + + value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE); + + if(!(value & SPD_DIMM_CONF_TYPE_ECC)) { + dcl &= ~DCL_DimmEccEn; + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + meminfo->is_ecc = 0; + return; + } + + } +} + +static int update_dimm_Twtr(const struct mem_controller *ctrl, const struct mem_param *param, int i) +{ + + return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX); + +} + +static void set_TT(const struct mem_controller *ctrl, const struct mem_param *param, unsigned TT_REG, + unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX, unsigned val, const char *str) +{ + uint32_t reg; + + if ((val < TT_MIN) || (val > TT_MAX)) { + print_err(str); + die(" Unknown\r\n"); + } + + reg = pci_read_config32(ctrl->f2, TT_REG); + reg &= ~(TT_MASK << TT_SHIFT); + reg |= ((val - TT_BASE) << TT_SHIFT); + pci_write_config32(ctrl->f2, TT_REG, reg); + return; +} + +static void set_TrwtTO(const struct mem_controller *ctrl, const struct mem_param *param) +{ + set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO"); +} + +static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param) +{ + set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd"); +} + +static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param) +{ + set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr"); +} + +static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param) +{ + set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd"); +} + +static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param) +{ + set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS +} + +static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) +{ + static const uint8_t faw_1k[] = {8, 10, 13, 14}; + static const uint8_t faw_2k[] = {10, 14, 17, 18}; + unsigned memclkfreq_index; + unsigned faw; + + + memclkfreq_index = param->dch_memclk; + + if(meminfo->page_1k_mask != 0) { //1k page + faw = faw_1k[memclkfreq_index]; + } + else { + faw = faw_2k[memclkfreq_index]; + } + + set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow"); + +} + + +static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) +{ + uint32_t dch; + unsigned async_lat; + + + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT); + + async_lat = 6+6; + + + dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT); + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); +} + +static void set_SlowAccessMode(const struct mem_controller *ctrl) +{ + uint32_t dch; + + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + + dch |= (1<<20); + + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); +} + + +/* + DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20 + DRAM_ADDR_TIMING_CTRL 04, 0x24 +*/ +static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo) +{ + uint32_t dword; + uint32_t dwordx; + unsigned SlowAccessMode = 0; + + long dimm_mask = meminfo->dimm_mask & 0x0f; + +#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */ + /* for REG DIMM */ + dword = 0x00111222; + dwordx = 0x002f0000; + switch (meminfo->memclk_set) { + case DCH_MemClkFreq_266MHz: + if( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { + dwordx = 0x002f2700; + } + break; + case DCH_MemClkFreq_333MHz: + if( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) { + if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there? + dwordx = 0x002f2f00; + } + } + break; + case DCH_MemClkFreq_400MHz: + dwordx = 0x002f3300; + break; + } + +#endif + +#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ + /* for UNBUF DIMM */ + dword = 0x00111222; + dwordx = 0x002f2f00; + switch (meminfo->memclk_set) { + case DCH_MemClkFreq_200MHz: + if(dimm_mask == 0x03) { + SlowAccessMode = 1; + dword = 0x00111322; + } + break; + case DCH_MemClkFreq_266MHz: + if(dimm_mask == 0x03) { + SlowAccessMode = 1; + dword = 0x00111322; + if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) { + switch (meminfo->single_rank_mask) { + case 0x03: + dwordx = 0x00002f00; //x8 single Rank + break; + case 0x00: + dwordx = 0x00342f00; //x8 double Rank + break; + default: + dwordx = 0x00372f00; //x8 single Rank and double Rank mixed + } + } else if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) { + dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed + } else if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) { + dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed + } + + } + else { + if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank + dwordx = 0x002f2f00; + } else { + dwordx = 0x002b2f00; + } + } + break; + case DCH_MemClkFreq_333MHz: + dwordx = 0x00202220; + if(dimm_mask == 0x03) { + SlowAccessMode = 1; + dword = 0x00111322; + if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) { + switch (meminfo->single_rank_mask) { + case 0x03: + dwordx = 0x00302220; //x8 single Rank + break; + case 0x00: + dwordx = 0x002b2220; //x8 double Rank + break; + defalut: + dwordx = 0x002a2220; //x8 single Rank and double Rank mixed + } + } else if((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) { + dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed + } else if((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) { + dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed + } + } + break; + case DCH_MemClkFreq_400MHz: + dwordx = 0x00202520; + SlowAccessMode = 1; + if(dimm_mask == 0x03) { + dword = 0x00113322; + } else { + dword = 0x00113222; + } + break; + } + + print_raminit("\tdimm_mask = ", meminfo->dimm_mask); + print_raminit("\tx4_mask = ", meminfo->x4_mask); + print_raminit("\tx16_mask = ", meminfo->x16_mask); + print_raminit("\tsingle_rank_mask = ", meminfo->single_rank_mask); + print_raminit("\tODC = ", dword); + print_raminit("\tAddr Timing= ", dwordx); +#endif + +#if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ + if(SlowAccessMode) { + set_SlowAccessMode(ctrl); + } +#endif + + /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */ + pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword); + if(meminfo->is_Width128) { + pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword); + } + + /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */ + pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx); + if(meminfo->is_Width128) { + pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx); + } + +} + + +static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) +{ +#if CPU_SOCKET_TYPE==0x10 + //only need to set for reg and x8 + uint32_t dch; + + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + + dch &= ~DCH_RDqsEn; + if((!meminfo->x4_mask) && (!meminfo->x16_mask)) { + dch |= DCH_RDqsEn; + } + + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); +#endif +} + + +static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) +{ + uint32_t dcm; + /* AMD says to Hardcode this */ + dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC); + dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT); + dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT; + dcm |= DCM_DCC_EN; + pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm); +} + +static void set_RdWrQByp(const struct mem_controller *ctrl, const struct mem_param *param) +{ + set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp"); +} + + + +static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask, struct mem_info *meminfo) +{ + int i; + + for(i = 0; i < DIMM_SOCKETS; i++) { + int rc; + if (!(dimm_mask & (1 << i))) { + continue; + } + print_tx("dimm socket: ", i); + /* DRAM Timing Low Register */ + print_t("\ttrc\r\n"); + if ((rc = update_dimm_Trc (ctrl, param, i)) <= 0) goto dimm_err; + + print_t("\ttrcd\r\n"); + if ((rc = update_dimm_Trcd(ctrl, param, i)) <= 0) goto dimm_err; + + print_t("\ttrrd\r\n"); + if ((rc = update_dimm_Trrd(ctrl, param, i)) <= 0) goto dimm_err; + + print_t("\ttras\r\n"); + if ((rc = update_dimm_Tras(ctrl, param, i)) <= 0) goto dimm_err; + + print_t("\ttrp\r\n"); + if ((rc = update_dimm_Trp (ctrl, param, i)) <= 0) goto dimm_err; + + print_t("\ttrtp\r\n"); + if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err; + + print_t("\ttwr\r\n"); + if ((rc = update_dimm_Twr (ctrl, param, i)) <= 0) goto dimm_err; + + /* DRAM Timing High Register */ + print_t("\ttref\r\n"); + if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err; + + print_t("\ttwtr\r\n"); + if ((rc = update_dimm_Twtr(ctrl, param, i)) <= 0) goto dimm_err; + + print_t("\ttrfc\r\n"); + if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err; + + /* DRAM Config Low */ + + continue; + dimm_err: + if (rc < 0) { + return -1; + } + dimm_mask = disable_dimm(ctrl, i, dimm_mask, meminfo); + } + + meminfo->dimm_mask = dimm_mask; // store final dimm_mask + + get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4 + /* DRAM Timing Low Register */ + + /* DRAM Timing High Register */ + set_TrwtTO(ctrl, param); + set_Twrrd (ctrl, param); + set_Twrwr (ctrl, param); + set_Trdrd (ctrl, param); + + set_4RankRDimm(ctrl, param, meminfo); + + /* DRAM Config High */ + set_Tfaw(ctrl, param, meminfo); + set_DcqBypassMax(ctrl, param); + set_max_async_latency(ctrl, param); + set_RDqsEn(ctrl, param, meminfo); + + /* DRAM Config Low */ + set_ecc(ctrl, param, dimm_mask, meminfo); + set_dimm_x4(ctrl, param, meminfo); + set_DramTerm(ctrl, param, meminfo); + + /* DRAM Control Misc */ + set_idle_cycle_limit(ctrl, param); + set_RdWrQByp(ctrl, param); + + return dimm_mask; +} + +static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +{ + struct spd_set_memclk_result result; + const struct mem_param *param; + struct mem_param paramx; + struct mem_info *meminfo; + long dimm_mask; +#if 1 + if (!sysinfo->ctrl_present[ctrl->node_id]) { +// print_debug("No memory controller present\r\n"); + return; + } +#endif + meminfo = &sysinfo->meminfo[ctrl->node_id]; + + print_debug_addr("sdram_set_spd_registers: paramx :", ¶mx); + + activate_spd_rom(ctrl); + dimm_mask = spd_detect_dimms(ctrl); + if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { + print_debug("No memory for this cpu\r\n"); + return; + } + dimm_mask = spd_enable_2channels(ctrl, dimm_mask, meminfo); + if (dimm_mask < 0) + goto hw_spd_err; + dimm_mask = spd_set_ram_size(ctrl , dimm_mask, meminfo); + if (dimm_mask < 0) + goto hw_spd_err; + dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask, meminfo); + if (dimm_mask < 0) + goto hw_spd_err; + result = spd_set_memclk(ctrl, dimm_mask, meminfo); + param = result.param; + dimm_mask = result.dimm_mask; + if (dimm_mask < 0) + goto hw_spd_err; + + //store memclk set to sysinfo, incase we need rebuilt param again + meminfo->memclk_set = param->dch_memclk; + + memcpy(¶mx, param, sizeof(paramx)); + + paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor); + + dimm_mask = spd_set_dram_timing(ctrl, ¶mx , dimm_mask, meminfo); // dimm_mask will be stored to meminfo->dimm_mask + if (dimm_mask < 0) + goto hw_spd_err; + + order_dimms(ctrl, meminfo); + + return; + hw_spd_err: + /* Unrecoverable error reading SPD data */ + print_err("SPD error - reset\r\n"); + hard_reset(); + return; +} + +#define TIMEOUT_LOOPS 300000 + +#include "raminit_f_dqs.c" + +#if HW_MEM_HOLE_SIZEK != 0 +static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) +{ + int ii; + uint32_t carry_over; + device_t dev; + uint32_t base, limit; + uint32_t basek; + uint32_t hoist; + int j; + + carry_over = (4*1024*1024) - hole_startk; + + for(ii=controllers - 1;ii>i;ii--) { + base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); + limit += (carry_over << 2 ); + base += (carry_over << 2 ); + for(j = 0; j < controllers; j++) { + pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit); + pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base ); + } + } + limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); + limit += (carry_over << 2); + for(j = 0; j < controllers; j++) { + pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit); + } + dev = ctrl[i].f1; + base = pci_read_config32(dev, 0x40 + (i << 3)); + basek = (base & 0xffff0000) >> 2; + if(basek == hole_startk) { + //don't need set memhole here, because hole off set will be 0, overflow + //so need to change base reg instead, new basek will be 4*1024*1024 + base &= 0x0000ffff; + base |= (4*1024*1024)<<2; + for(j = 0; j < controllers; j++) { + pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); + } + } + else + { + hoist = /* hole start address */ + ((hole_startk << 10) & 0xff000000) + + /* hole address to memory controller address */ + (((basek + carry_over) >> 6) & 0x0000ff00) + + /* enable */ + 1; + pci_write_config32(dev, 0xf0, hoist); + } + + return carry_over; +} + +static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) +{ + + uint32_t hole_startk; + int i; + + hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + +#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + //We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some + uint32_t basek_pri; + for(i=0; i> 2; + if(base_k == hole_startk) { + hole_startk -= (base_k - basek_pri)>>1; // decrease mem hole startk to make sure it is on middle of previous node + break; //only one hole + } + basek_pri = base_k; + } +#endif + //find node index that need do set hole + for(i=0; i> 2; + limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; + if ((base_k <= hole_startk) && (limit_k > hole_startk)) { + unsigned end_k; + hoist_memory(controllers, ctrl, hole_startk, i); + end_k = memory_end_k(ctrl, controllers); + set_top_mem(end_k, hole_startk); + break; //only one hole + } + } + +} + +#endif + +static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) +{ + int i; + + +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + unsigned cpu_f0_f1[8]; + tsc_t tsc, tsc0[8]; + + print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]); +#endif + uint32_t dword; + + /* Error if I don't have memory */ + if (memory_end_k(ctrl, controllers) == 0) { + die("No memory\r\n"); + } + + /* Before enabling memory start the memory clocks */ + for(i = 0; i < controllers; i++) { + uint32_t dtl, dch; + if (!sysinfo->ctrl_present[ i ]) + continue; + dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + + // if no memory installed, disabled the interface + if(sysinfo->meminfo[i].dimm_mask==0x00){ + dch |= DCH_DisDramInterface; + pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); + + } + else { + dch |= DCH_MemClkFreqVal; + pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); + /* address timing and Output driver comp Control */ + set_misc_timing(ctrl+i, sysinfo->meminfo+i ); + } + } + + /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */ + memreset(controllers, ctrl); + + for(i = 0; i < controllers; i++) { + uint32_t dcl, dch; + if (!sysinfo->ctrl_present[ i ]) + continue; + /* Skip everything if I don't have any memory on this controller */ + dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + if (!(dch & DCH_MemClkFreqVal)) { + continue; + } + + /* ChipKill */ + dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + if (dcl & DCL_DimmEccEn) { + uint32_t mnc; + print_spew("ECC enabled\r\n"); + mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); + mnc |= MNC_ECC_EN; + if (dcl & DCL_Width128) { + mnc |= MNC_CHIPKILL_EN; + } + pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); + } + +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); + if(cpu_f0_f1[i]) { + //Rev F0/F1 workaround +#if 1 + /* Set the DqsRcvEnTrain bit */ + dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); + dword |= DC_DqsRcvEnTrain; + pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword); +#endif + tsc0[i] = rdtsc(); + } +#endif + +#if 0 + /* Set the DqsRcvEnTrain bit */ + dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); + dword |= DC_DqsRcvEnTrain; + pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword); +#endif + + pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + dcl |= DCL_InitDram; + pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + + } + + for(i = 0; i < controllers; i++) { + uint32_t dcl, dch, dcm; + if (!sysinfo->ctrl_present[ i ]) + continue; + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + print_debug("Initializing memory: "); + int loops = 0; + do { + dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + loops++; + if ((loops & 1023) == 0) { + print_debug("."); + } + } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS)); + if (loops >= TIMEOUT_LOOPS) { + print_debug(" failed\r\n"); + continue; + } + + /* Wait until it is safe to touch memory */ + do { + dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); + } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ ); + +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + if(cpu_f0_f1[i]) { + tsc= rdtsc(); + + print_debug_dqs_tsc("\r\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2); + print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2); + + if(tsc.lotom_k = ((msr.hi<<24) | (msr.lo>>8))>>2; + + //[4G, TOM2) + msr = rdmsr(TOP_MEM2); + sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2; + } + + for(i = 0; i < controllers; i++) { + sysinfo->mem_trained[i] = 0; + } + +#if MEM_TRAIN_SEQ == 0 + #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + dqs_timing(controllers, ctrl, tsc0, sysinfo); + #else + dqs_timing(controllers, ctrl, sysinfo); + #endif +#else + + #if MEM_TRAIN_SEQ == 2 + //need to enable mtrr, so dqs training could access the test address + setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); + #endif + + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[ i ]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + dqs_timing(i, ctrl, sysinfo, 1); + + #if MEM_TRAIN_SEQ == 1 + break; // only train the first node with ram + #endif + } + + #if MEM_TRAIN_SEQ == 2 + clear_mtrr_dqs(sysinfo->tom2_k); + #endif + +#endif + + +} +static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) +{ + int i; + int j; + struct mem_controller *ctrl; + for(i=0;inode_id = i; + ctrl->f0 = PCI_DEV(0, 0x18+i, 0); + ctrl->f1 = PCI_DEV(0, 0x18+i, 1); + ctrl->f2 = PCI_DEV(0, 0x18+i, 2); + ctrl->f3 = PCI_DEV(0, 0x18+i, 3); + + if(spd_addr == (void *)0) continue; + + for(j=0;jchannel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; + ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; + } + } +} Added: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,2036 @@ +/* + yhlu 2005.10 dqs training +*/ +//0: mean no debug info +#define DQS_TRAIN_DEBUG 0 + +static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) +{ +#if DQS_TRAIN_DEBUG > 0 + if(DQS_TRAIN_DEBUG > level) { + #if CONFIG_USE_INIT == 1 + printk_debug("%s%x\r\n", str, val); + #else + print_debug(str); print_debug_hex32(val); print_debug("\r\n"); + #endif + } +#endif +} + +static inline void print_debug_dqs_pair(const char *str, unsigned val, const char *str2, unsigned val2, unsigned level) +{ +#if DQS_TRAIN_DEBUG > 0 + if(DQS_TRAIN_DEBUG > level) { + #if CONFIG_USE_INIT == 1 + printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); + #else + print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n"); + #endif + } +#endif +} + +static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val, unsigned val2, unsigned level) +{ +#if DQS_TRAIN_DEBUG > 0 + if(DQS_TRAIN_DEBUG > level) { + #if CONFIG_USE_INIT == 1 + printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); + #else + print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); + #endif + } +#endif +} + +static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) +{ + #if CONFIG_USE_INIT == 1 + printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); + #else + print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); + #endif + +} + +static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ctrl, struct sys_info *sysinfo) +{ + + int i; + sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3)); + + for(i=0;i<8; i++) { + sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2)); + } + + sysinfo->hole_reg[nodeid] = pci_read_config32(ctrl->f1, 0xf0); + +} +static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo) +{ + uint32_t dword; + uint32_t mem_base; + unsigned nodeid = ctrl->node_id; + +#if HW_MEM_HOLE_SIZEK != 0 + uint32_t hole_reg; +#endif + + //get the local base addr of the chipselect + dword = sysinfo->cs_base[nodeid * 8 + cs_idx]; + dword &= 0xfffffff0; + + //sys addr= node base + local cs base + mem_base = sysinfo->mem_base[nodeid]; + mem_base &= 0xffff0000; + + dword += mem_base; +#if HW_MEM_HOLE_SIZEK != 0 + hole_reg = sysinfo->hole_reg[nodeid]; + if(hole_reg & 1) { + unsigned hole_startk; + hole_startk = (hole_reg & (0xff<<24)) >> 10; + if( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { + dword += ((4*1024*1024 - hole_startk)<<2); + } + } +#endif + + //add 1MB offset to avoid compat area + dword += (1<<(20-8)); + + //So final result is upper 32 bit addr + + return dword; + +} + +static unsigned Get_RcvrSysAddr(const struct mem_controller * ctrl, unsigned channel, unsigned cs_idx, struct sys_info *sysinfo) +{ +#if 0 + //get SB_64MuxedMode + uint32_t dword; + dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC); + if((dword & DCM_Mode64BitMux) == DCM_Mode64BitMux) { + if(channel) cs_idx += 4; // translate Receiver number to Chipsel + } +#endif + + return Get_MCTSysAddr(ctrl, cs_idx, sysinfo); + +} + +static inline unsigned long read_cr4(void) +{ + unsigned long cr4; + asm volatile ("movl %%cr4, %0" : "=r" (cr4)); + return cr4; +} + +static inline void write_cr4(unsigned long cr4) +{ + asm volatile ("movl %0, %%cr4" : : "r" (cr4)); +} + + +static inline void enable_sse2() +{ + unsigned long cr4; + cr4 = read_cr4(); + cr4 |= (1<<9); + write_cr4(cr4); +} + +static inline void disable_sse2() +{ + unsigned long cr4; + cr4 = read_cr4(); + cr4 &= ~(1<<9); + write_cr4(cr4); +} + + +static void set_wrap32dis(void) { + msr_t msr; + + msr = rdmsr(0xc0010015); + msr.lo |= (1<<17); + + wrmsr(0xc0010015, msr); + +} + +static void clear_wrap32dis(void) { + msr_t msr; + + msr = rdmsr(0xc0010015); + msr.lo &= ~(1<<17); + + wrmsr(0xc0010015, msr); + +} + +static void set_FSBASE(uint32_t addr_hi) +{ + msr_t msr; + + //set fs and use fs prefix to access the mem + msr.hi = addr_hi; + msr.lo = 0; + wrmsr(0xc0000100, msr); //FS_BASE + +} + +#if 0 +static void write_mem(uint32_t addr_hi, uint32_t addr_lo, uint32_t value) +{ + if(addr_hi == 0) { + *((uint32_t *)addr_lo) = value; + return; + } + + set_FSBASE(addr_hi); + + __asm__ volatile ( + "movl %1, %%fs:(%0)\n\t" + :: "a" (addr_lo), "b" (value) + ); + +} + +static uint32_t read_mem(uint32_t addr_hi, uint32_t addr_lo) +{ + unsigned value; + if(addr_hi == 0) { + value = *((uint32_t *)addr_lo); + return value; + } + + set_FSBASE(addr_hi); + + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + + return value; + +} +#endif + +static unsigned ChipSelPresent(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo) +{ + unsigned enabled; + unsigned nodeid = ctrl->node_id; + + + enabled = sysinfo->cs_base[nodeid * 8 + cs_idx]; + enabled &= 1; + + return enabled; + +} + +static unsigned RcvrRankEnabled(const struct mem_controller *ctrl, int channel, int cs_idx, unsigned is_Width128, struct sys_info *sysinfo) +{ + if(!is_Width128) { + if(channel) return 0; // no channel b + } + + return ChipSelPresent(ctrl, cs_idx, sysinfo); +} + +static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_num) +{ + __asm__ volatile ( + "1:\n\t" + "movdqa (%3), %%xmm0\n\t" + "movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */ + "addl %1, %0\n\t" + "addl %1, %3\n\t" + "loop 1b\n\t" + + :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) + ); + + +} + +static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) +{ + uint8_t *buf; + if(p==1) { buf = buf_b; } + else { buf = buf_a; } + + set_FSBASE (addr>>24); + + WriteLNTestPattern(addr<<8, buf, 1); +} + +static void Read1LTestPattern(unsigned addr) +{ + unsigned value; + + set_FSBASE(addr>>24); + + /* 1st move causes read fill (to exclusive or shared)*/ + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr<<8) + ); + +} + +#define DQS_PASS 0 +#define DQS_FAIL 1 + +#define DQS_FIRST_PASS 1 +#define DQS_SECOND_PASS 2 + +#define SB_NORCVREN 11 +#define RCVREN_MARGIN 6 +#define SB_SmallRCVR 13 +#define SB_CHA2BRCVREN 12 +#define SB_NODQSPOS 14 +#define MIN_DQS_WNDW 3 +#define SB_SMALLDQS 15 + + +static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned pattern, const uint32_t *TestPattern0, const uint32_t *TestPattern1, const uint32_t *TestPattern2, unsigned Pass, unsigned is_Width128) +{ + uint32_t addr_lo; + uint32_t *test_buf; + uint32_t value; + uint32_t value_test; + unsigned result = DQS_FAIL; + + if(Pass == DQS_FIRST_PASS) { + if(pattern==1) { + test_buf = (uint32_t *)TestPattern1; + } + else { + test_buf = (uint32_t *)TestPattern0; + } + } + else { + test_buf = (uint32_t *)TestPattern2; + } + + set_FSBASE(addr>>24); + + addr_lo = addr<<8; + + if(is_Width128 && (channel == 1)) { + addr_lo += 8; //second channel + test_buf += 2; + } + + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + + value_test = *test_buf; + + + print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); + print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : addr_lo = ", addr_lo, " value = ", value, 4); + + if(value == value_test) { + addr_lo += 4; + test_buf++; + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + value_test = *test_buf; + print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); + print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4); + + if(value == value_test){ + result = DQS_PASS; + } + } + + if(Pass == DQS_SECOND_PASS) { // second pass need to be inverted + if(result==DQS_PASS) { + result = DQS_FAIL; + } + else { + result = DQS_PASS; + } + } + + return result; + +} + +static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly) +{ + uint32_t reg; + + dly += (20-1); // round it + dly /= 20; // convert from unit 50ps to 1ns + + dly += 6; + + + reg = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + reg &= ~(DCH_MaxAsyncLat_MASK <f2, DRAM_CONFIG_HIGH, reg); + +} + +/* + Set the Target range to WT IO (using an IORR overlapping the already existing + WB dram type). Use IORR0 +*/ +static void SetTargetWTIO(unsigned addr) +{ + msr_t msr; + msr.hi = addr>>24; + msr.lo = addr<<8; + wrmsr(0xc0010016, msr); //IORR0 BASE + + msr.hi = 0xff; + msr.lo = 0xfc000800; // 64MB Mask + wrmsr(0xc0010017, msr); // IORR0 Mask +} + +static void ResetTargetWTIO(void) +{ + msr_t msr; + + msr.hi = 0; + msr.lo = 0; + wrmsr(0xc0010017, msr); // IORR0 Mask +} + +static void proc_CLFLUSH(unsigned addr) +{ + + set_FSBASE(addr>>24); + + /* 1st move causes read fill (to exclusive or shared)*/ + __asm__ volatile ( + /* clflush fs:[eax] */ + "clflush %%fs:(%0)\n\t" + ::"a" (addr<<8) + ); + +} +static void proc_IOCLFLUSH(unsigned addr) +{ + SetTargetWTIO(addr); + proc_CLFLUSH(addr); + ResetTargetWTIO(); +} + +static void ResetDCTWrPtr(const struct mem_controller *ctrl) +{ + uint32_t dword; + unsigned index = 0x10; + + dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); + pci_write_config32_index_wait(ctrl->f2, 0x98, index, dword); + +} + + +static uint16_t get_exact_T1000(unsigned i) +{ + // 200 266, 333, 400 + const static uint16_t T1000_a[]= { 5000, 3759, 3003, 2500 }; + + static const uint16_t TT_a[] = { + /*200 266 333 400 */ + /*4 */ 6250, 6250, 6250, 6250, + /*5 */ 5000, 5000, 5000, 2500, + /*6 */ 5000, 4166, 4166, 2500, + /*7 */ 5000, 4285, 3571, 2500, + + /*8 */ 5000, 3750, 3125, 2500, + /*9 */ 5000, 3888, 3333, 2500, + /*10*/ 5000, 4000, 3000, 2500, + /*11*/ 5000, 4090, 3181, 2500, + + /*12*/ 5000, 3750, 3333, 2500, + /*13*/ 5000, 3846, 3076, 2500, + /*14*/ 5000, 3928, 3214, 2500, + /*15*/ 5000, 4000, 3000, 2500, + }; + + unsigned fid_cur; + int index; + + msr_t msr; + msr = rdmsr(0xc0010042); + fid_cur = msr.lo & 0x3f; + + index = fid_cur>>1; + + if(index>12) return T1000_a[i]; + + return TT_a[index * 4+i]; + +} + +static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) +{ + int i; + uint32_t dword; + + dword = 0x00000000; + for(i=1; i<=3; i++) { + /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ + pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); + pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); + } + + dword = 0x2f2f2f2f; + for(i=5; i<=7; i++) { + /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ + pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); + pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); + } + + +} +#ifndef K8_REV_F_SUPPORT_F0_F1_WORKAROUND +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1 +#endif + +static void TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) +{ + + const static uint32_t TestPattern0[] = { + 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, + 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, + 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, + 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, + }; + const static uint32_t TestPattern1[] = { + 0x55555555, 0x55555555, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0x55555555, 0x55555555, + }; + const static uint32_t TestPattern2[] = { + 0x12345678, 0x87654321, 0x23456789, 0x98765432, + 0x59385824, 0x30496724, 0x24490795, 0x99938733, + 0x40385642, 0x38465245, 0x29432163, 0x05067894, + 0x12349045, 0x98723467, 0x12387634, 0x34587623, + }; + + uint8_t pattern_buf_x[64 * 4 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ + uint8_t *buf_a, *buf_b; + uint32_t ecc_bit; + uint32_t dword; + uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8 + + int i; + + unsigned channel, receiver; + + unsigned Errors; + unsigned CTLRMaxDelay; + unsigned T1000; + + unsigned LastTest; + unsigned CurrTest; + unsigned Test0, Test1; + + unsigned RcvrEnDlyRmin; + + unsigned two_ranks; + unsigned RcvrEnDly; + + unsigned PatternA; + unsigned PatternB; + + unsigned TestAddr0, TestAddr0B, TestAddr1, TestAddr1B; + + unsigned CurrRcvrCHADelay; + + unsigned tmp; + + unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128; + + unsigned cpu_f0_f1; + + if(Pass == DQS_FIRST_PASS) { + InitDQSPos4RcvrEn(ctrl); + } + + //enable SSE2 + enable_sse2(); + + //wrap32dis + set_wrap32dis(); + + //disable ECC temp + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + ecc_bit = dword & DCL_DimmEccEn; + dword &= ~(DCL_DimmEccEn); + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); + + + if(Pass == DQS_FIRST_PASS) { +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + cpu_f0_f1 = is_cpu_pre_f2_in_bsp(ctrl->node_id); + if(!cpu_f0_f1) +#endif + { +#if 1 + /* Set the DqsRcvEnTrain bit */ + dword = pci_read_config32(ctrl->f2, DRAM_CTRL); + dword |= DC_DqsRcvEnTrain; + pci_write_config32(ctrl->f2, DRAM_CTRL, dword); +#endif + } + } + + //get T1000 figures (cycle time (ns)) * 1K + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dword &= DCH_MemClkFreq_MASK; + + T1000 = get_exact_T1000(dword); + + // SetupRcvrPattern + buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); + buf_b = buf_a + 128; //?? + if(Pass==DQS_FIRST_PASS) { + for(i=0;i<16;i++) { + *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; + *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; + } + } + else { + for(i=0;i<16;i++) { + *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; + *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; + } + } + + print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); + + print_debug_addr("TrainRcvEn: buf_a:", buf_a); + + Errors = 0; + /* for each channel */ + CTLRMaxDelay = 0; + for(channel = 0; (channel < 2) && (!Errors); channel++) + { + print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); + + /* for each rank */ + /* there are four recriver pairs, loosely associated with CS */ + for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) + { + + unsigned index=(receiver>>1) * 3 + 0x10; + + print_debug_dqs("\t\tTrainRcvEn52: index ", index, 2); + + if(is_Width128) { + if(channel) { + dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); + CurrRcvrCHADelay= dword & 0xff; + } + } + else { + if(channel) { + index += 0x20; + } + } + + LastTest = DQS_FAIL; + RcvrEnDlyRmin = 0xaf; + + if(!RcvrRankEnabled(ctrl, channel, receiver, is_Width128, sysinfo)) continue; + + /* for each DQS receiver enable setting */ + + TestAddr0 = Get_RcvrSysAddr(ctrl, channel, receiver, sysinfo); + + TestAddr0B = TestAddr0 + (1<<(20+2-8)); // 4MB + + if(RcvrRankEnabled(ctrl, channel, receiver+1, is_Width128, sysinfo)) { + TestAddr1 = Get_RcvrSysAddr(ctrl, channel, receiver+1, sysinfo); + TestAddr1B = TestAddr1 + (1<<(20+2-8)); //4MB + two_ranks = 1; + } + else { + two_ranks = 0; + } + + print_debug_dqs("\t\tTrainRcvEn53: TestAddr0B ", TestAddr0B, 2); + + Write1LTestPattern(TestAddr0, 0, buf_a, buf_b); // rank0 of dimm, test p0 + Write1LTestPattern(TestAddr0B, 1, buf_a, buf_b); //rank0 of dimm, test p1 + + if(two_ranks == 1) { + Write1LTestPattern(TestAddr1, 0, buf_a, buf_b); //rank 1 of dimm + Write1LTestPattern(TestAddr1B, 1, buf_a, buf_b);//rank 1 of dimm + } + + if(Pass == DQS_FIRST_PASS) { + RcvrEnDly = 0; + } else { + RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver]; + } + + while ( RcvrEnDly < 0xaf) { // Sweep Delay value here + print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); + + if(RcvrEnDly & 1) { + /* Odd steps get another pattern such that even + and odd steps alternate. + The pointers to the patterns will be swapped + at the end of the loop so they are correspond + */ + PatternA = 1; + PatternB = 0; + } + else { + /* Even step */ + PatternA = 0; + PatternB = 1; + } + + /* Program current Receiver enable delay */ + pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); + + if(is_Width128) { + /* Program current Receiver enable delay chaannel b */ + pci_write_config32_index_wait(ctrl->f2, 0x98, index+ 0x20, RcvrEnDly); + } + + /* Program the MaxAsyncLat filed with the + current DQS receiver enable setting plus 6ns + */ + /*Porgram MaxAsyncLat to correspond with current delay */ + SetMaxAL_RcvrDly(ctrl, RcvrEnDly); + + CurrTest = DQS_FAIL; + + Read1LTestPattern(TestAddr0); //Cache Fill + /* ROM vs cache compare */ + Test0 = CompareTestPatternQW0(channel, TestAddr0, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + proc_IOCLFLUSH(TestAddr0); + + ResetDCTWrPtr(ctrl); + + print_debug_dqs("\t\t\tTrainRcvEn542: Test0 ", Test0, 3); + + if(Test0 == DQS_PASS) { + + Read1LTestPattern(TestAddr0B); + Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + proc_IOCLFLUSH(TestAddr0B); + + ResetDCTWrPtr(ctrl); + + print_debug_dqs("\t\t\tTrainRcvEn543: Test1 ", Test1, 3); + + if(Test1 == DQS_PASS) { + if(two_ranks) { + Read1LTestPattern(TestAddr1); + Test0 = CompareTestPatternQW0(channel, TestAddr1, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + proc_IOCLFLUSH(TestAddr1); + ResetDCTWrPtr(ctrl); + + if(Test0 == DQS_PASS) { + Read1LTestPattern(TestAddr1B); + Test1 = CompareTestPatternQW0(channel, TestAddr1B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + proc_IOCLFLUSH(TestAddr1B); + ResetDCTWrPtr(ctrl); + + if(Test1 == DQS_PASS) { + CurrTest = DQS_PASS; + } + } + print_debug_dqs("\t\t\tTrainRcvEn544: Test0 ", Test0, 3); + } + else { + CurrTest = DQS_PASS; + } + } + } + + print_debug_dqs("\t\t\tTrainRcvEn55: RcvrEnDly ", RcvrEnDly, 3); + + if(CurrTest == DQS_PASS) { + if(LastTest == DQS_FAIL) { + RcvrEnDlyRmin = RcvrEnDly; + break; + } + } + + LastTest = CurrTest; + + /* swap the rank 0 pointers */ + tmp = TestAddr0; + TestAddr0 = TestAddr0B; + TestAddr0B = tmp; + + /* swap the rank 1 pointers */ + tmp = TestAddr1; + TestAddr1 = TestAddr1B; + TestAddr1B = tmp; + + print_debug_dqs("\t\t\tTrainRcvEn56: RcvrEnDly ", RcvrEnDly, 3); + + RcvrEnDly++; + + } // while RcvrEnDly + + print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); + + if(RcvrEnDlyRmin == 0xaf) { + //no passing window + Errors |= SB_NORCVREN; + } + + if(Pass == DQS_FIRST_PASS) { + // We need a better value for DQSPos trainning + RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */; + } else { + RcvrEnDly = RcvrEnDlyRmin; + } + + if(RcvrEnDly > 0xae) { + //passing window too narrow, too far delayed + Errors |= SB_SmallRCVR; + RcvrEnDly = 0xae; + } + + if(Pass == DQS_SECOND_PASS) { //second pass must average vales + RcvrEnDly += dqs_rcvr_dly_a[channel * 8 + receiver] /* - (RCVREN_MARGIN * T1000/64/50)*/; + RcvrEnDly >>= 1; + } + + dqs_rcvr_dly_a[channel * 8 + receiver] = RcvrEnDly; + + //Set final RcvrEnDly for this DIMM and Channel + pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); + + if(is_Width128) { + pci_write_config32_index_wait(ctrl->f2, 0x98, index+0x20, RcvrEnDly); // channel B + if(channel) { + pci_write_config32_index_wait(ctrl->f2, 0x98, index, CurrRcvrCHADelay); + if(RcvrEnDly > CurrRcvrCHADelay) { + dword = RcvrEnDly - CurrRcvrCHADelay; + } + else { + dword = CurrRcvrCHADelay - RcvrEnDly; + } + dword *= 50; + if(dword > T1000) { + Errors |= SB_CHA2BRCVREN; + } + } + } + + print_debug_dqs("\t\tTrainRcvEn63: RcvrEnDly ", RcvrEnDly, 2); + + if(RcvrEnDly > CTLRMaxDelay) { + CTLRMaxDelay = RcvrEnDly; + } + + print_debug_dqs("\t\tTrainRcvEn64: CTLRMaxDelay ", CTLRMaxDelay, 2); + + } /* receiver */ + } /* channel */ + + print_debug_dqs("\tTrainRcvEn65: CTLRMaxDelay ", CTLRMaxDelay, 1); + + /* Program the MaxAsysncLat field with the largest DQS Receiver Enable setting */ + SetMaxAL_RcvrDly(ctrl, CTLRMaxDelay); + ResetDCTWrPtr(ctrl); + + //Enable ECC again + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dword &= ~(DCL_DimmEccEn); + dword |= ecc_bit; + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); + + if(Pass == DQS_FIRST_PASS) { +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + if(!cpu_f0_f1) +#endif + { + dword = pci_read_config32(ctrl->f2, DRAM_CTRL); + dword &= ~DC_DqsRcvEnTrain; + pci_write_config32(ctrl->f2, DRAM_CTRL, dword); + } + } + + //Clear wrap32dis + + clear_wrap32dis(); + + //restore SSE2 setting + disable_sse2(); + +#if MEM_TRAIN_SEQ != 1 + /* We need tidy output for type 1 */ + #if CONFIG_USE_INIT == 1 + printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay); + #else + print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); + #endif +#endif + + if(CTLRMaxDelay==0xae) { + soft_reset(); // try more or downgrade? + } + +} + +#define DQS_READDIR 1 +#define DQS_WRITEDIR 0 + + +static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, unsigned bytelane, unsigned direction, unsigned dqs_delay) +{ //ByteLane could be 0-8, last is for ECC + unsigned index; + uint32_t dword; + unsigned shift; + + dqs_delay &= 0xff; + + index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2); + shift = bytelane; + while(shift>3) { + shift-=4; + } + shift <<= 3; // 8 bit + + dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); + dword &= ~(0x3f<f2, 0x98, index, dword); + +} + +static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channel, unsigned direction, unsigned dqs_delay) +{ + unsigned index; + uint32_t dword; + int i; + + dword = 0; + dqs_delay &= 0xff; + for(i=0;i<4;i++) { + dword |= dqs_delay<<(i*8); + } + + index = 1 + channel * 0x20 + direction * 4; + + for(i=0; i<2; i++) { + pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword); + } + +} + +static unsigned MiddleDQS(unsigned min_d, unsigned max_d) +{ + unsigned size_d; + size_d = max_d-min_d; + if(size_d & 1) { //need round up + min_d++; + } + return ( min_d + (size_d>>1)); +} + +static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay) +{ + dqs_delay_a[channel * 2*9 + direction * 9 + bytelane] = dqs_delay; +} + +static void WriteDQSTestPattern(unsigned addr_lo, unsigned pattern , uint8_t *buf_a) +{ + WriteLNTestPattern(addr_lo, buf_a, (pattern+1) * 9); +} + +static void ReadL18TestPattern(unsigned addr_lo) +{ + //set fs and use fs prefix to access the mem + __asm__ volatile ( + "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%esi), %%eax\n\t" //+1 + "movl %%fs:(%%esi), %%eax\n\t" //+2 + "movl %%fs:64(%%esi), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edi), %%eax\n\t" //+4 + "movl %%fs:-64(%%edi), %%eax\n\t" //+5 + "movl %%fs:(%%edi), %%eax\n\t" //+6 + "movl %%fs:64(%%edi), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "movl %%fs:-64(%%ebx), %%eax\n\t" //+9 + "movl %%fs:(%%ebx), %%eax\n\t" //+10 + "movl %%fs:64(%%ebx), %%eax\n\t" //+11 + + "movl %%fs:-128(%%ecx), %%eax\n\t" //+12 + "movl %%fs:-64(%%ecx), %%eax\n\t" //+13 + "movl %%fs:(%%ecx), %%eax\n\t" //+14 + "movl %%fs:64(%%ecx), %%eax\n\t" //+15 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+16 + "movl %%fs:-64(%%edx), %%eax\n\t" //+17 + + :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "S"(addr_lo+128), "D"(addr_lo+128+4*64) + ); + +} + +static void ReadL9TestPattern(unsigned addr_lo) +{ + + //set fs and use fs prefix to access the mem + __asm__ volatile ( + + "movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line + "movl %%fs:-64(%%ecx), %%eax\n\t" //+1 + "movl %%fs:(%%ecx), %%eax\n\t" //+2 + "movl %%fs:64(%%ecx), %%eax\n\t" //+3 + + "movl %%fs:-128(%%edx), %%eax\n\t" //+4 + "movl %%fs:-64(%%edx), %%eax\n\t" //+5 + "movl %%fs:(%%edx), %%eax\n\t" //+6 + "movl %%fs:64(%%edx), %%eax\n\t" //+7 + + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + + :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), "d"(addr_lo+128+4*64) + ); + +} + + +static void ReadDQSTestPattern(unsigned addr_lo, unsigned pattern) +{ + if(pattern == 0) { + ReadL9TestPattern(addr_lo); + } + else { + ReadL18TestPattern(addr_lo); + } +} + +static void FlushDQSTestPattern_L9(unsigned addr_lo) +{ + __asm__ volatile ( + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + + :: "b" (addr_lo+128+8*64), "c"(addr_lo+128), "a"(addr_lo+128+4*64) + ); + +} +static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo) +{ + __asm__ volatile ( + "clflush %%fs:-128(%%eax)\n\t" + "clflush %%fs:-64(%%eax)\n\t" + "clflush %%fs:(%%eax)\n\t" + "clflush %%fs:64(%%eax)\n\t" + + "clflush %%fs:-128(%%edi)\n\t" + "clflush %%fs:-64(%%edi)\n\t" + "clflush %%fs:(%%edi)\n\t" + "clflush %%fs:64(%%edi)\n\t" + + "clflush %%fs:-128(%%ebx)\n\t" + "clflush %%fs:-64(%%ebx)\n\t" + "clflush %%fs:(%%ebx)\n\t" + "clflush %%fs:64(%%ebx)\n\t" + + "clflush %%fs:-128(%%ecx)\n\t" + "clflush %%fs:-64(%%ecx)\n\t" + "clflush %%fs:(%%ecx)\n\t" + "clflush %%fs:64(%%ecx)\n\t" + + "clflush %%fs:-128(%%edx)\n\t" + "clflush %%fs:-64(%%edx)\n\t" + + :: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), "d" (addr_lo +128+16*64), "a"(addr_lo+128), "D"(addr_lo+128+4*64) + ); +} + +static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern ) +{ + + if(pattern == 0){ + FlushDQSTestPattern_L9(addr_lo); + } + else { + FlushDQSTestPattern_L18(addr_lo); + } +} + +static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsigned pattern, uint8_t *buf_a) +{ + uint32_t *test_buf; + unsigned bitmap = 0xff; + unsigned bytelane; + int i; + uint32_t value; + int j; + uint32_t value_test; + + test_buf = (uint32_t *)buf_a; + + + if(pattern && channel) { + addr_lo += 8; //second channel + test_buf+= 2; + } + + bytelane = 0; + for(i=0;i<9*64/4;i++) { + __asm__ volatile ( + "movl %%fs:(%1), %0\n\t" + :"=b"(value): "a" (addr_lo) + ); + value_test = *test_buf; + + print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); + print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7); + + for(j=0;j<4*8;j+=8) { + if(((value>>j)&0xff) != ((value_test>>j)& 0xff)) { + bitmap &= ~(1<>24); + + if(Direction == DQS_READDIR) { + print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read so write at first", 0, 4); + WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); + } + + for(DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); + if(MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes + SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); + if(Direction == DQS_WRITEDIR) { + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5); + WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); + } + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5); + ReadDQSTestPattern(TestAddr<<8, Pattern); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); + MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); + SetTargetWTIO(TestAddr); + FlushDQSTestPattern(TestAddr<<8, Pattern); + ResetTargetWTIO(); + } + } + + if(BanksPresent) + for(ByteLane = 0; ByteLane < 8; ByteLane++) { + print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); + + LastTest = DQS_FAIL; + RnkDlySeqPassMax = 0; + RnkDlyFilterMax = 0; + RnkDlyFilterMin = 0; + for(DQSDelay=0; DQSDelay<48; DQSDelay++) { + if(MutualCSPassW[DQSDelay] & (1<(RnkDlyFilterMax-RnkDlyFilterMin)){ + RnkDlyFilterMin = RnkDlySeqPassMin; + RnkDlyFilterMax = RnkDlySeqPassMax; + } + LastTest = DQS_PASS; + } + else { + LastTest = DQS_FAIL; + } + } + print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); + + if(RnkDlySeqPassMax == 0) { + Errors |= SB_NODQSPOS; // no passing window + } + else { + print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); + print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); + if((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ + Errors |= SB_SMALLDQS; + } + else { + unsigned middle_dqs; + middle_dqs = MiddleDQS(RnkDlyFilterMin, RnkDlyFilterMax); + print_debug_dqs("\t\t\t\tTrainDQSPos: 35 middle_dqs ",middle_dqs, 4); + SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, middle_dqs); + save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, middle_dqs); + } + } + + } + + print_debug_dqs("\t\t\tTrainDQSPos: end", 0xff, 3); + + return Errors; + + +} + +static unsigned TrainReadDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo) +{ + print_debug_dqs("\t\tTrainReadPos", 0, 2); + return TrainDQSPos(ctrl, channel, DQS_READDIR, pattern, buf_a, dqs_delay_a, sysinfo); +} + +static unsigned TrainWriteDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo) +{ + print_debug_dqs("\t\tTrainWritePos", 0, 2); + return TrainDQSPos(ctrl, channel, DQS_WRITEDIR, pattern, buf_a, dqs_delay_a, sysinfo); +} + + + +static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) +{ + const static uint32_t TestPatternJD1a[] = { + 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW0-1, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW2-3, ALL-EVEN + 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW4-5, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW6-7, ALL-EVEN + 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW0-1, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW2-3, DQ0-ODD + 0x01010101,0x01010101,0xFeFeFeFe,0xFeFeFeFe, // QW4-5, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0x01010101,0x01010101, // QW6-7, DQ0-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW0-1, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2-3, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0x02020202,0x02020202, // QW4-5, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW6-7, DQ1-ODD + 0x04040404,0x04040404,0xfBfBfBfB,0xfBfBfBfB, // QW0-1, DQ2-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW2-3, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4-5, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6-7, DQ2-ODD + 0x08080808,0x08080808,0xF7F7F7F7,0xF7F7F7F7, // QW0-1, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW2-3, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0x08080808,0x08080808, // QW4-5, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6-7, DQ3-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW0-1, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW2-3, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4-5, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0x10101010,0x10101010, // QW6-7, DQ4-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0-1, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0x20202020,0x20202020, // QW2-3, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4-5, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6-7, DQ5-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0-1, DQ6-ODD + 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW2-3, DQ6-ODD + 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW4-5, DQ6-ODD + 0x40404040,0x40404040,0xBfBfBfBf,0xBfBfBfBf, // QW6-7, DQ6-ODD + 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW0-1, DQ7-ODD + 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW2-3, DQ7-ODD + 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW4-5, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080 // QW6-7, DQ7-ODD + }; + const static uint32_t TestPatternJD1b[] = { + 0x00000000,0x00000000,0x00000000,0x00000000, // QW0,CHA-B, ALL-EVEN + 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW1,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW2,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW3,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW4,CHA-B, ALL-EVEN + 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW5,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW6,CHA-B, ALL-EVEN + 0x00000000,0x00000000,0x00000000,0x00000000, // QW7,CHA-B, ALL-EVEN + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW0,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW1,CHA-B, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW2,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW3,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW4,CHA-B, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW5,CHA-B, DQ0-ODD + 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW6,CHA-B, DQ0-ODD + 0x01010101,0x01010101,0x01010101,0x01010101, // QW7,CHA-B, DQ0-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW0,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW1,CHA-B, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2,CHA-B, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW3,CHA-B, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW4,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW5,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW6,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW7,CHA-B, DQ1-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW0,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW1,CHA-B, DQ2-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW2,CHA-B, DQ2-ODD + 0x04040404,0x04040404,0x04040404,0x04040404, // QW3,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW4,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW5,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW6,CHA-B, DQ2-ODD + 0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB,0xfBfBfBfB, // QW7,CHA-B, DQ2-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW0,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW1,CHA-B, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW2,CHA-B, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW3,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW4,CHA-B, DQ3-ODD + 0x08080808,0x08080808,0x08080808,0x08080808, // QW5,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW6,CHA-B, DQ3-ODD + 0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7,0xF7F7F7F7, // QW7,CHA-B, DQ3-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW0,CHA-B, DQ4-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW1,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW2,CHA-B, DQ4-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW3,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW4,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW5,CHA-B, DQ4-ODD + 0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF,0xeFeFeFeF, // QW6,CHA-B, DQ4-ODD + 0x10101010,0x10101010,0x10101010,0x10101010, // QW7,CHA-B, DQ4-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW0,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW1,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW2,CHA-B, DQ5-ODD + 0x20202020,0x20202020,0x20202020,0x20202020, // QW3,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW4,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW5,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW6,CHA-B, DQ5-ODD + 0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF,0xdFdFdFdF, // QW7,CHA-B, DQ5-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW0,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW1,CHA-B, DQ6-ODD + 0x40404040,0x40404040,0x40404040,0x40404040, // QW2,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW3,CHA-B, DQ6-ODD + 0x40404040,0x40404040,0x40404040,0x40404040, // QW4,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW5,CHA-B, DQ6-ODD + 0x40404040,0x40404040,0x40404040,0x40404040, // QW6,CHA-B, DQ6-ODD + 0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf,0xBfBfBfBf, // QW7,CHA-B, DQ6-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW0,CHA-B, DQ7-ODD + 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW1,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW2,CHA-B, DQ7-ODD + 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW3,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW4,CHA-B, DQ7-ODD + 0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F,0x7F7F7F7F, // QW5,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080, // QW6,CHA-B, DQ7-ODD + 0x80808080,0x80808080,0x80808080,0x80808080 // QW7,CHA-B, DQ7-ODD + }; + uint8_t pattern_buf_x[64 * 18 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ + uint8_t *buf_a; + + unsigned pattern; + uint32_t dword; + uint32_t ecc_bit; + unsigned Errors; + unsigned channel; + int i; + unsigned DQSWrDelay; + unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128; + uint8_t *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9 + + //enable SSE2 + enable_sse2(); + + //wrap32dis + set_wrap32dis(); + + //disable ECC temp + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + ecc_bit = dword & DCL_DimmEccEn; + dword &= ~(DCL_DimmEccEn); + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); + + //SetupDqsPattern + buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf)); + + if(is_Width128){ + pattern = 1; + for(i=0;i<16*18;i++) { + *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; + } + } + else { + pattern = 0; + for(i=0; i<16*9;i++) { + *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; + } + + } + + print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); + + print_debug_addr("TrainDQSRdWrPos: buf_a:", buf_a); + + Errors = 0; + + channel = 0; + while( (channel<2) && (!Errors)) { + print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); + for(DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { + unsigned err; + SetDQSDelayAllCSR(ctrl, channel, DQS_WRITEDIR, DQSWrDelay); + print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); + err= TrainReadDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); + print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2); + if(err == 0) break; + Errors |= err; + } + + print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1); + + if(DQSWrDelay < 48) { + Errors = TrainWriteDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); + print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1); + + } + channel++; + if(!is_Width128){ + channel++; // skip channel if 64-bit mode + } + } + + //Enable ECC again + dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dword &= ~(DCL_DimmEccEn); + dword |= ecc_bit; + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); + + //Clear wrap32dis + + clear_wrap32dis(); + + //restore SSE2 setting + disable_sse2(); + + print_debug_dqs("TrainDQSRdWrPos: ", 5, 0); + + return Errors; + +} +static inline uint8_t get_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a) +{ + return dqs_delay_a[channel * 2*9 + direction * 9 + bytelane]; +} + +static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned ByteLane1, unsigned InterFactor, unsigned Direction, uint8_t *dqs_delay_a) +/* InterFactor: 0: 100% ByteLane 0 + 0x80: 50% between ByteLane 0 and 1 + 0xff: 99.6% ByteLane 1 and 0.4% like 0 +*/ +{ + unsigned DQSDelay0, DQSDelay1; + unsigned DQSDelay; + + DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a); + DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); + + if(DQSDelay0>DQSDelay1) { + DQSDelay = DQSDelay0 - DQSDelay1; + InterFactor = 0xff - InterFactor; + } + else { + DQSDelay = DQSDelay1 - DQSDelay0; + } + + DQSDelay *= InterFactor; + + DQSDelay >>= 8; // /255 + + if(DQSDelay0>DQSDelay1) { + DQSDelay += DQSDelay1; + } + else { + DQSDelay += DQSDelay0; + } + + return DQSDelay; + +} + +static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) +{ + unsigned channel; + unsigned ByteLane; + unsigned Direction; + unsigned lane0, lane1, ratio; + unsigned dqs_delay; + + unsigned direction[] = { DQS_READDIR, DQS_WRITEDIR }; + int i; + uint8_t *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9 + + ByteLane = 8; + + for(channel = 0; channel < 2; channel++) { + for(i=0;i<2;i++) { + Direction = direction[i]; + lane0 = 4; lane1 = 5; ratio = 0; + dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a); + print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2); + SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay); + save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay); + } + } +} + +static void train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) +{ + print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); + TrainRcvrEn(ctrl, Pass, sysinfo); + print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); + +} +static void train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) +{ + print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); + if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { + print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n"); + soft_reset(); + } + else { + SetEccDQSRdWrPos(ctrl, sysinfo); + } + print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); + +} + +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 +static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo) +{ + tsc_t tsc1[8]; + unsigned cpu_f0_f1[8]; + int i; + + print_debug_addr("dqs_timing: tsc1[8] :", tsc1); + + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[i]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + uint32_t dword; + + cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); + + if(!cpu_f0_f1[i]) continue; + + dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); + dword &= ~DC_DqsRcvEnTrain; + pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword); + + dword = pci_read_config32(ctrl[i].f2, DRAM_INIT); + dword |= DI_EnDramInit; + pci_write_config32(ctrl[i].f2, DRAM_INIT, dword); + dword &= ~DI_EnDramInit; + pci_write_config32(ctrl[i].f2, DRAM_INIT, dword); + + tsc1[i] = rdtsc(); + print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); + + dword = tsc1[i].lo + tsc0[i].lo; + if((dwordctrl_present[i]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + if(!cpu_f0_f1[i]) continue; + + tsc_t tsc; + + do { + tsc = rdtsc(); + } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo))); + + print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2); + } + +} + +#endif + + +/* setting variable mtrr, comes from linux kernel source */ +static void set_var_mtrr_dqs( + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned char type, unsigned address_bits) +{ + msr_t base, mask; + unsigned address_mask_high; + + address_mask_high = ((1u << (address_bits - 32u)) - 1u); + + base.hi = basek >> 22; + base.lo = basek << 10; + + if (sizek < 4*1024*1024) { + mask.hi = address_mask_high; + mask.lo = ~((sizek << 10) -1); + } + else { + mask.hi = address_mask_high & (~((sizek >> 22) -1)); + mask.lo = 0; + } + + if (reg >= 8) + return; + + if (sizek == 0) { + msr_t zero; + zero.lo = zero.hi = 0; + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR(reg), zero); + } else { + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + base.lo |= type; + mask.lo |= 0x800; + wrmsr (MTRRphysBase_MSR(reg), base); + wrmsr (MTRRphysMask_MSR(reg), mask); + } +} + + +/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ +static inline unsigned int fms(unsigned int x) +{ + int r; + + __asm__("bsrl %1,%0\n\t" + "jnz 1f\n\t" + "movl $0,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; +} + +/* fms: find least sigificant bit set */ +static inline unsigned int fls(unsigned int x) +{ + int r; + + __asm__("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; +} + +static unsigned int range_to_mtrr(unsigned int reg, + unsigned long range_startk, unsigned long range_sizek, + unsigned long next_range_startk, unsigned char type, unsigned address_bits) +{ + if (!range_sizek || (reg >= 8)) { + return reg; + } + while(range_sizek) { + unsigned long max_align, align; + unsigned long sizek; + /* Compute the maximum size I can make a range */ + max_align = fls(range_startk); + align = fms(range_sizek); + if (align > max_align) { + align = max_align; + } + sizek = 1 << align; +#if MEM_TRAIN_SEQ != 1 + #if CONFIG_USE_INIT == 1 + printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", + reg, range_startk >>10, sizek >> 10, + (type==MTRR_TYPE_UNCACHEABLE)?"UC": + ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + ); + #else + print_debug("Setting variable MTRR "); print_debug_hex8(reg); print_debug(", base: "); print_debug_hex16(range_startk>>10); + print_debug("MB, range: "); print_debug_hex16(sizek >> 10); print_debug("MB, type "); + print_debug( (type==MTRR_TYPE_UNCACHEABLE)?"UC\r\n": + ((type==MTRR_TYPE_WRBACK)?"WB\r\n":"Other\r\n") + ); + #endif +#endif + set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits); + range_startk += sizek; + range_sizek -= sizek; + if (reg >= 8) + break; + } + return reg; +} + +static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k) +{ + msr_t msr; + + /* Now set top of memory */ + msr.lo = (tom2_k & 0x003fffff) << 10; + msr.hi = (tom2_k & 0xffc00000) >> 22; + wrmsr(TOP_MEM2, msr); + + msr.lo = (tom_k & 0x003fffff) << 10; + msr.hi = (tom_k & 0xffc00000) >> 22; + wrmsr(TOP_MEM, msr); +} + +static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k){ + unsigned reg; + msr_t msr; + +#if 0 + //still enable from cache_as_ram.inc + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR,msr); +#endif + + //[0,512k), [512k, 640k) + msr.hi = 0x1e1e1e1e; + msr.lo = msr.hi; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + + //[1M, TOM) + reg = range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); + + //[4G, TOM2) + if(tom2_k) { + //enable tom2 and type + msr = rdmsr(SYSCFG_MSR); + msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB + wrmsr(SYSCFG_MSR, msr); + } + +} + +static void clear_mtrr_dqs(unsigned tom2_k){ + msr_t msr; + unsigned i; + + //still enable from cache_as_ram.inc + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR,msr); + + //[0,512k), [512k, 640k) + msr.hi = 0; + msr.lo = msr.hi; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + + //[1M, TOM) + for(i=0x204;i<0x210;i++) { + wrmsr(i, msr); + } + + //[4G, TOM2) + if(tom2_k) { + //enable tom2 and type + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB + wrmsr(SYSCFG_MSR, msr); + } +} + +static void set_htic_bit(unsigned i, unsigned val, unsigned bit) +{ + uint32_t dword; + dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL); + dword &= ~(1<tom_k, sysinfo->tom2_k); + + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[ i ]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); + } + + tsc[0] = rdtsc(); + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[ i ]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + print_debug("DQS Training:RcvrEn:Pass1: "); + print_debug_hex8(i); + train_DqsRcvrEn(ctrl+i, 1, sysinfo); + print_debug(" done\r\n"); + } + + tsc[1] = rdtsc(); +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + f0_svm_workaround(controllers, ctrl, tsc0, sysinfo); +#endif + + tsc[2] = rdtsc(); + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[i]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + print_debug("DQS Training:DQSPos: "); + print_debug_hex8(i); + train_DqsPos(ctrl+i, sysinfo); + print_debug(" done\r\n"); + } + + tsc[3] = rdtsc(); + for(i = 0; i < controllers; i++) { + if (!sysinfo->ctrl_present[i]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + + print_debug("DQS Training:RcvrEn:Pass2: "); + print_debug_hex8(i); + train_DqsRcvrEn(ctrl+i, 2, sysinfo); + print_debug(" done\r\n"); + sysinfo->mem_trained[i]=1; + } + + tsc[4] = rdtsc(); + clear_mtrr_dqs(sysinfo->tom2_k); + + + for(i=0;i<5;i++) { + print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo); + } + + + +} + +#endif + + +#if MEM_TRAIN_SEQ > 0 + +static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned v) +{ + + int ii; + + tsc_t tsc[4]; + + +#if MEM_TRAIN_SEQ == 1 + if(sysinfo->mem_trained[i]) return; + //need to enable mtrr, so dqs training could access the test address + setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); +#endif + + fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); + + if(v) { + tsc[0] = rdtsc(); + + print_debug("set DQS timing:RcvrEn:Pass1: "); + print_debug_hex8(i); + } + train_DqsRcvrEn(ctrl+i, 1, sysinfo); + + if(v) { + print_debug(" done\r\n"); + tsc[1] = rdtsc(); + print_debug("set DQS timing:DQSPos: "); + print_debug_hex8(i); + } + + train_DqsPos(ctrl+i, sysinfo); + + if(v) { + print_debug(" done\r\n"); + tsc[2] = rdtsc(); + + print_debug("set DQS timing:RcvrEn:Pass2: "); + print_debug_hex8(i); + } + train_DqsRcvrEn(ctrl+i, 2, sysinfo); + + if(v) { + print_debug(" done\r\n"); + + tsc[3] = rdtsc(); + } + +#if MEM_TRAIN_SEQ == 1 + clear_mtrr_dqs(sysinfo->tom2_k); +#endif + + if(v) { + for(ii=0;ii<4;ii++) { + print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); + } + } + + sysinfo->mem_trained[i]=1; + +} +#endif + +#if MEM_TRAIN_SEQ == 1 +static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) +{ + dqs_timing(nodeid, sysinfo->ctrl,sysinfo, 0); // keep the output tidy +// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); +// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); + sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; + +} +static void copy_and_run_ap_code_in_car(unsigned ret_addr); +static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) +{ + if(coreid) return; // only do it on core0 + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + wait_till_sysinfo_in_ram(); // use pci to get it + + if(sysinfox->mem_trained[nodeid] == 0) { + if (sysinfox->ctrl_present[ nodeid ] && sysinfox->meminfo[nodeid].dimm_mask) { + sysinfo->tom_k = sysinfox->tom_k; + sysinfo->tom2_k = sysinfox->tom2_k; + sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128; + set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's + #if CONFIG_AP_CODE_IN_CAR == 0 + print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n"); + train_ram(nodeid, sysinfo, sysinfox); + #else + /* Can copy dqs_timing to ap cache and run from cache? + * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ? + */ + copy_and_run_ap_code_in_car(retcall); + // will go back by jump + #endif + } + } +} +#endif Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -21,8 +21,8 @@ print_debug("\r\n"); #endif #endif - dev = (register_values[i] & ~0xff) + offset_pci_dev; - where = register_values[i] & 0xff; + dev = (register_values[i] & ~0xfff) + offset_pci_dev; + where = register_values[i] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2] + offset_io_base; @@ -58,13 +58,13 @@ #if RES_DEBUG #if CONFIG_USE_INIT printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", - i/4, register_values[i], + i>>2, register_values[i], register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) ); #else - print_debug_hex16(i/4); + print_debug_hex16(i>>2); print_debug(": "); print_debug_hex8(register_values[i]); print_debug(" "); @@ -84,8 +84,8 @@ device_t dev; unsigned where; unsigned long reg; - dev = (register_values[i+1] & ~0xff) + offset_pci_dev; - where = register_values[i+1] & 0xff; + dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; + where = register_values[i+1] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+2]; reg |= register_values[i+3]; @@ -173,8 +173,8 @@ device_t dev; unsigned where; unsigned long reg; - dev = register_values[i+1] & ~0xff; - where = register_values[i+1] & 0xff; + dev = register_values[i+1] & ~0xfff; + where = register_values[i+1] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+2]; reg |= register_values[i+3]; Added: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/spd_ddr2.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/spd_ddr2.h (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/spd_ddr2.h 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,66 @@ +/* SPDs for DDR2 SDRAM */ +#define SPD_MEM_TYPE 2 + #define SPD_MEM_TYPE_SDRAM_DDR 0x07 + #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 + +#define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/ + #define SPD_DIMM_TYPE_RDIMM (1<<0) + #define SPD_DIMM_TYPE_UDIMM (1<<1) + #define SPD_DIMM_TYPE_SODIMM (1<<2) + #define SPD_DIMM_TYPE_uDIMM (1<<3) + #define SPD_DIMM_TYPE_mRDIMM (1<<4) + #define SPD_DIMM_TYPE_mUDIMM (1<<5) +#define SPD_MOD_ATTRIB 21 + #define SPD_MOD_ATTRIB_DIFCK 0x20 + #define SPD_MOD_ATTRIB_REGADC 0x11 /* x */ + #define SPD_MOD_ATTRIB_PROBE 0x40 + +#define SPD_DEV_ATTRIB 22 /* Device attributes --- general */ +#define SPD_DIMM_CONF_TYPE 11 + #define SPD_DIMM_CONF_TYPE_ECC 0x02 + #define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */ + +#define SPD_ROW_NUM 3 /* Number of Row addresses */ +#define SPD_COL_NUM 4 /* Number of Column addresses */ +#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */ + +#define SPD_MOD_ATTRIB_RANK 5 /* include Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */ + #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0 + #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 + #define SPD_MOD_ATTRIB_RANK_NUM_BASE 1 + #define SPD_MOD_ATTRIB_RANK_NUM_MIN 1 + #define SPD_MOD_ATTRIB_RANK_NUM_MAX 8 + +#define SPD_RANK_SIZE 31 /* Only one bit is set */ + #define SPD_RANK_SIZE_1GB (1<<0) + #define SPD_RANK_SIZE_2GB (1<<1) + #define SPD_RANK_SIZE_4GB (1<<2) + #define SPD_RANK_SIZE_8GB (1<<3) + #define SPD_RANK_SIZE_16GB (1<<4) + #define SPD_RANK_SIZE_128MB (1<<5) + #define SPD_RANK_SIZE_256MB (1<<6) + #define SPD_RANK_SIZE_512MB (1<<7) + +#define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */ +#define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */ +#define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */ + +#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */ + #define SPD_CAS_LAT_2 (1<<2) + #define SPD_CAS_LAT_3 (1<<3) + #define SPD_CAS_LAT_4 (1<<4) + #define SPD_CAS_LAT_5 (1<<5) + #define SPD_CAS_LAT_6 (1<<6) + +#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */ +#define SPD_TRRD 28 +#define SPD_TRCD 29 +#define SPD_TRAS 30 +#define SPD_TWR 36 /* x */ +#define SPD_TWTR 37 /* x */ +#define SPD_TRTP 38 /* x */ + +#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/ +#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/ + +#define SPD_TREF 12 Added: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/ssdt.dsl =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/ssdt.dsl (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/ssdt.dsl 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,78 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440) +{ + /* + * These objects were referenced but not defined in this table + */ + External (\_SB_.PCI0, DeviceObj) + + Scope (\_SB.PCI0) + { + Name (BUSN, Package (0x04) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + Name (MMIO, Package (0x10) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee, + 0x11111111, + 0x22222222 + }) + Name (PCIO, Package (0x08) + { + 0x77777777, + 0x88888888, + 0x99999999, + 0xaaaaaaaa, + 0xbbbbbbbb, + 0xcccccccc, + 0xdddddddd, + 0xeeeeeeee + }) + Name (SBLK, 0x11) + Name (TOM1, 0xaaaaaaaa) + Name (SBDN, 0xbbbbbbbb) + Name (HCLK, Package (0x08) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (HCDN, Package (0x08) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + 0x55555555, + 0x66666666, + 0x77777777, + 0x88888888 + }) + Name (CBST, 0x88) + } +} + Modified: trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -10,7 +10,7 @@ PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), bus); - return (dev>>11) & 0x1f; + return (dev>>15) & 0x1f; } Modified: trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_enable_rom.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_enable_rom.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_enable_rom.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -6,10 +6,10 @@ /* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */ /* Locate the amd8111 */ - dev = pci_locate_device(PCI_ID(0x1022, 0x7468), 0); + dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0); /* Set the 5MB enable bits */ - byte = pci_read_config8(dev, 0x43); + byte = pci_io_read_config8(dev, 0x43); byte |= 0xC0; - pci_write_config8(dev, 0x43, byte); + pci_io_write_config8(dev, 0x43, byte); } Modified: trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_reset.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_reset.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_reset.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -2,9 +2,9 @@ #include #define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x7) << 8)) + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) @@ -14,7 +14,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) { unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); } @@ -22,7 +22,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) { unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); } @@ -30,7 +30,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where) { unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); } @@ -58,8 +58,8 @@ { device_t dev; unsigned bus; - unsigned node = 0; - unsigned link = get_sblk(); + unsigned node = 0; + unsigned link = get_sblk(); /* Find the device. * There can only be one 8111 on a hypertransport chain/bus. Modified: trunk/LinuxBIOSv2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -71,6 +71,48 @@ pci_write_config8(dev, 0x40, (1<<2)); } +static unsigned get_sbdn(unsigned bus) +{ + device_t dev; + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(0x1166, 0x0036), + bus); + + return (dev>>15) & 0x1f; + +} + +#define SB_VFSMAF 0 + +static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +{ + //ACPI Decode Enable + outb(0x0e, 0xcd6); + outb((1<<3), 0xcd7); + + // set port to 0x2060 + outb(0x67, 0xcd6); + outb(0x60, 0xcd7); + outb(0x68, 0xcd6); + outb(0x20, 0xcd7); + + outb(0x69, 0xcd6); + outb(7, 0xcd7); + + outb(0x64, 0xcd6); + outb(9, 0xcd7); +} + +static void ldtstop_sb(void) +{ + outb(1, 0x2060); +} + + static void hard_reset(void) { bcm5785_enable_wdt_port_cf9(); Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -2,58 +2,13 @@ * Copyright 2004 Tyan Computer * by yhlu at tyan.com */ -static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) -{ - uint32_t dword, dword_old; - uint8_t link_type; - - dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); - link_type = dword & 0xff; - - dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) ); - - if ( (link_type & 0x7) == linkt ) { - dword = val; - } - - if (dword != dword_old) { - pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword); - return 1; - } - - return 0; -} static int set_ht_link_ck804(uint8_t ht_c_num) { - int reset_needed; - uint8_t i; - - reset_needed = 0; - - for (i = 0; i < ht_c_num; i++) { - uint32_t reg; - uint8_t nodeid, linkn; - uint8_t busn; - unsigned val; - - reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); - if((reg & 3) != 3) continue; - - nodeid = ((reg & 0xf0)>>4); - linkn = ((reg & 0xf00)>>8); - busn = (reg & 0xff0000)>>16; - - reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID); - if ( (reg & 0xffff) == 0x10de ) { - val = 0x01610169; - reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); - } - } - - return reset_needed; + unsigned vendorid = 0x10de; + unsigned val = 0x01610169; + set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } - static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) { int i; Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -3,59 +3,14 @@ * by yhlu at tyan.com * 2005.12 yhlu make it for car so it could support more ck804s */ -static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) -{ - uint32_t dword, dword_old; - uint8_t link_type; - - /* This works on an Athlon64 because unimplemented links return 0 */ - dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); - link_type = dword & 0xff; - - dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) ); - - if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ - dword = val; - } - - if (dword != dword_old) { - pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword); - return 1; - } - - return 0; -} + static int set_ht_link_ck804(uint8_t ht_c_num) { - int reset_needed; - uint8_t i; - - reset_needed = 0; - - for (i = 0; i < ht_c_num; i++) { - uint32_t reg; - uint8_t nodeid, linkn; - uint8_t busn; - unsigned val; - - reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); - if((reg & 3) != 3) continue; - - nodeid = ((reg & 0xf0)>>4); - linkn = ((reg & 0xf00)>>8); - busn = (reg & 0xff0000)>>16; - - reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID); - if ( (reg & 0xffff) == 0x10de ) { - val = 0x01610169; - reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); - } - } - - return reset_needed; + unsigned vendorid = 0x10de; + unsigned val = 0x01610169; + set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } - static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) { int i; Modified: trunk/LinuxBIOSv2/src/stream/rom_stream.c =================================================================== --- trunk/LinuxBIOSv2/src/stream/rom_stream.c 2006-09-25 09:15:52 UTC (rev 2434) +++ trunk/LinuxBIOSv2/src/stream/rom_stream.c 2006-10-04 20:46:15 UTC (rev 2435) @@ -54,7 +54,8 @@ uncompress(uint8_t * rom_start, uint8_t *dest ) { #if (CONFIG_COMPRESSED_ROM_STREAM) || (CONFIG_COMPRESSED_ROM_STREAM_NRV2B) - return unrv2b(rom_start, dest); + unsigned long ilen; // used compressed stream length + return unrv2b(rom_start, dest, &ilen); #endif #if (CONFIG_COMPRESSED_ROM_STREAM_LZMA) return ulzma(rom_start, dest); Added: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/Config.lb 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1,85 @@ +# Sample config file for +# the amd serengeti_cheetah +# This will make a target directory of ./serengeti_cheetah + +target serengeti_cheetah +mainboard amd/serengeti_cheetah + +# serengeti_leopard +romimage "normal" +# 48K for SCSI FW +# option ROM_SIZE = 475136 +# 48K for SCSI FW and 48K for ATI ROM +# option ROM_SIZE = 425984 +# 64K for Etherboot +# option ROM_SIZE = 458752 + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=0 +# option ROM_IMAGE_SIZE=0x13800 +# option ROM_IMAGE_SIZE=0x18800 + option ROM_IMAGE_SIZE=0x20000 +# option ROM_IMAGE_SIZE=0x15800 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +# payload ../../../payloads/tg3--ide_disk.zelf +# payload ../../../payloads/filo.elf +# payload ../../../payloads/filo_mem.elf +# payload ../../../payloads/filo.zelf +# payload ../../../payloads/tg3--filo_hda2.zelf +# payload ../../../payloads/tg3.zelf +# payload ../../../../payloads/tg3_vga.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga.zelf + payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf +# payload ../../../../payloads/e1000_vga.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf +# payload ../../../payloads/tg3_com2.zelf +# payload ../../../payloads/e1000--filo.zelf +# payload ../../../payloads/tg3--e1000--filo.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf +end + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 +# option ROM_IMAGE_SIZE=0x13800 +# option ROM_IMAGE_SIZE=0x19800 + option ROM_IMAGE_SIZE=0x20000 +# option ROM_IMAGE_SIZE=0x15800 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" +# payload ../../../payloads/tg3--ide_disk.zelf +# payload ../../../payloads/filo.elf +# payload ../../../payloads/filo_mem.elf +# payload ../../../payloads/filo.zelf +# payload ../../../payloads/tg3--filo_hda2.zelf +# payload ../../../payloads/tg3.zelf +# payload ../../../../payloads/tg3_vga.zelf +# payload ../../../../payloads/memtest +# payload ../../../../payloads/adlo.elf +# payload ../../../../payloads/e1000_vga.zelf +# payload ../../../../payloads/filo_hda.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf + payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf +# payload ../../../../payloads/filo_hda2_novga.zelf +# payload ../../../payloads/tg3_com2.zelf +# payload ../../../payloads/e1000--filo.zelf +# payload ../../../payloads/tg3--e1000--filo.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf +# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" +end + + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" Added: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/VERSION =================================================================== --- trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/VERSION (rev 0) +++ trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah/VERSION 2006-10-04 20:46:15 UTC (rev 2435) @@ -0,0 +1 @@ +_serengenti_cheetah From yinghai.lu at amd.com Wed Oct 4 22:50:22 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Wed, 4 Oct 2006 13:50:22 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D64D@ssvlexmb2.amd.com> Commited. Stefan Can you check abuild with emulation/qemu-i386? It will create fallback and normal, and normal will use reset16. I assume you need to let abuild to create one config that only include fallback section. Thanks Yinghai Lu From svn at openbios.org Wed Oct 4 23:00:01 2006 From: svn at openbios.org (svn at openbios.org) Date: Wed, 04 Oct 2006 23:00:01 +0200 Subject: [LinuxBIOS] r2436 - trunk/LinuxBIOSv2/src/include/cpu/amd Message-ID: Author: yhlu Date: 2006-10-04 23:00:01 +0200 (Wed, 04 Oct 2006) New Revision: 2436 Added: trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h Log: amdk8_sysconf Added: trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h (rev 0) +++ trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h 2006-10-04 21:00:01 UTC (rev 2436) @@ -0,0 +1,28 @@ +#ifndef AMDK8_SYSCONF_H + +#define AMDK8_SYSINFO_H + +#define HC_POSSIBLE_NUM 8 + +struct amdk8_sysconf_t { + //ht + unsigned nodes; + unsigned hc_possible_num; + unsigned pci1234[HC_POSSIBLE_NUM]; + unsigned hcdn[HC_POSSIBLE_NUM]; + unsigned sbdn; + unsigned sblk; + + unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234 + + int enabled_apic_ext_id; + unsigned lift_bsp_apicid; + int apicid_offset; + + void *mb; // pointer for mb releated struct + +}; + +extern struct amdk8_sysconf_t sysconf; + +#endif From svn at openbios.org Wed Oct 4 23:04:50 2006 From: svn at openbios.org (svn at openbios.org) Date: Wed, 04 Oct 2006 23:04:50 +0200 Subject: [LinuxBIOS] r2437 - in trunk/LinuxBIOSv2/src/cpu/amd: . socket_939 Message-ID: Author: yhlu Date: 2006-10-04 23:04:49 +0200 (Wed, 04 Oct 2006) New Revision: 2437 Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_939/ trunk/LinuxBIOSv2/src/cpu/amd/socket_939/Config.lb trunk/LinuxBIOSv2/src/cpu/amd/socket_939/chip.h trunk/LinuxBIOSv2/src/cpu/amd/socket_939/socket_939.c Log: socket 939 Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_939/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_939/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_939/Config.lb 2006-10-04 21:04:49 UTC (rev 2437) @@ -0,0 +1,9 @@ +uses CONFIG_CHIP_NAME + +if CONFIG_CHIP_NAME + config chip.h +end + +object socket_939.o + +dir /cpu/amd/model_fxx Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_939/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_939/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_939/chip.h 2006-10-04 21:04:49 UTC (rev 2437) @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_amd_socket_939_ops; + +struct cpu_amd_socket_939_config { +}; Added: trunk/LinuxBIOSv2/src/cpu/amd/socket_939/socket_939.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/socket_939/socket_939.c (rev 0) +++ trunk/LinuxBIOSv2/src/cpu/amd/socket_939/socket_939.c 2006-10-04 21:04:49 UTC (rev 2437) @@ -0,0 +1,6 @@ +#include +#include "chip.h" + +struct chip_operations cpu_amd_socket_939_ops = { + CHIP_NAME("socket 939") +}; From svn at openbios.org Wed Oct 4 23:05:23 2006 From: svn at openbios.org (svn at openbios.org) Date: Wed, 04 Oct 2006 23:05:23 +0200 Subject: [LinuxBIOS] r2438 - in trunk/LinuxBIOSv2/src: arch/i386/lib config Message-ID: Author: yhlu Date: 2006-10-04 23:05:23 +0200 (Wed, 04 Oct 2006) New Revision: 2438 Added: trunk/LinuxBIOSv2/src/arch/i386/lib/failover_failover.lds trunk/LinuxBIOSv2/src/config/linuxbios_apc.ld Log: failover_failover apc lds Added: trunk/LinuxBIOSv2/src/arch/i386/lib/failover_failover.lds =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/lib/failover_failover.lds (rev 0) +++ trunk/LinuxBIOSv2/src/arch/i386/lib/failover_failover.lds 2006-10-04 21:05:23 UTC (rev 2438) @@ -0,0 +1,2 @@ + __fallback_image = (CONFIG_ROM_STREAM_START & 0xfffffff0) - 8; + __normal_image = ((CONFIG_ROM_STREAM_START - FALLBACK_SIZE) & 0xfffffff0) - 8; Added: trunk/LinuxBIOSv2/src/config/linuxbios_apc.ld =================================================================== --- trunk/LinuxBIOSv2/src/config/linuxbios_apc.ld (rev 0) +++ trunk/LinuxBIOSv2/src/config/linuxbios_apc.ld 2006-10-04 21:05:23 UTC (rev 2438) @@ -0,0 +1,100 @@ +/* + * Memory map: + * + * DCACHE_RAM_BASE + * : data segment + * : bss segment + * : heap + * : stack + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling + * 2006.05 yhlu tailed it to use it for AP code in cache + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +INCLUDE ldoptions + +ENTRY(_start) + +SECTIONS +{ + . = DCACHE_RAM_BASE; + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text : { + _text = .; + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } + .rodata : { + _rodata = .; + . = ALIGN(4); + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + _erodata = .; + } + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + . = ALIGN(0x1000); + _stack = .; + .stack . : { + . = 0x4000; + } + _estack = .; + _heap = .; + .heap . : { + . = ALIGN(4); + } + _eheap = .; + /* The ram segment + * This is all address of the memory resident copy of linuxBIOS. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "linuxbios_apc is too big"); + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} From info at coresystems.de Wed Oct 4 23:58:15 2006 From: info at coresystems.de (LinuxBIOS information) Date: Wed, 04 Oct 2006 23:58:15 +0200 Subject: [LinuxBIOS] r2436 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2436 to the LinuxBIOS source repository and caused the following changes: Change Log: amdk8_sysconf Build Log: Compilation of Iwill:DK8HTX has been fixed Compilation of Iwill:DK8S2 has been fixed Compilation of Iwill:DK8X has been fixed Compilation of agami:aruma has been fixed Compilation of amd:quartet has been fixed Compilation of amd:serenade has been fixed Compilation of amd:serengeti_cheetah is still broken Compilation of amd:serengeti_leopard has been fixed Compilation of amd:solo has been fixed Compilation of arima:hdama has been fixed Compilation of broadcom:blast has been fixed Compilation of emulation:qemu-i386 is still broken Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of newisys:khepri has been fixed Compilation of sunw:ultra40 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From info at coresystems.de Thu Oct 5 00:42:46 2006 From: info at coresystems.de (LinuxBIOS information) Date: Thu, 05 Oct 2006 00:42:46 +0200 Subject: [LinuxBIOS] r2437 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2437 to the LinuxBIOS source repository and caused the following changes: Change Log: socket 939 Build Log: Compilation of amd:serengeti_cheetah is still broken Compilation of emulation:qemu-i386 is still broken If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From svn at openbios.org Thu Oct 5 00:56:22 2006 From: svn at openbios.org (svn at openbios.org) Date: Thu, 05 Oct 2006 00:56:22 +0200 Subject: [LinuxBIOS] r2439 - in trunk/LinuxBIOSv2/src: arch/i386/include/arch arch/i386/lib config console cpu/amd/car cpu/amd/model_fxx devices drivers/i2c/adm1027 include/cpu/amd lib mainboard/Iwill/DK8HTX mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah/dx mainboard/amd/serengeti_leopard mainboard/amd/serengeti_leopard/dx northbridge/amd/amdk8 southbridge/nvidia/ck804 Message-ID: Author: yhlu Date: 2006-10-05 00:56:21 +0200 (Thu, 05 Oct 2006) New Revision: 2439 Added: trunk/LinuxBIOSv2/src/arch/i386/include/arch/mmio_conf.h trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_mmconf.c Removed: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx_bus0/ Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/pci_ops.h trunk/LinuxBIOSv2/src/arch/i386/include/arch/pciconf.h trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h trunk/LinuxBIOSv2/src/arch/i386/lib/Config.lb trunk/LinuxBIOSv2/src/arch/i386/lib/console.c trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c trunk/LinuxBIOSv2/src/config/Options.lb trunk/LinuxBIOSv2/src/console/Config.lb trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c trunk/LinuxBIOSv2/src/cpu/amd/car/disable_cache_as_ram.c trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/fidvid.c trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/LinuxBIOSv2/src/devices/device_util.c trunk/LinuxBIOSv2/src/devices/pci_device.c trunk/LinuxBIOSv2/src/drivers/i2c/adm1027/adm1027.c trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h trunk/LinuxBIOSv2/src/lib/Config.lb trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/acpi_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cmos.layout trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci2.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/mptable.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/debug.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/get_sblk_pci1234.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/incoherent_ht.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_reset.c Log: CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in serengeti_cheeatah Added: trunk/LinuxBIOSv2/src/arch/i386/include/arch/mmio_conf.h =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/include/arch/mmio_conf.h (rev 0) +++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/mmio_conf.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -0,0 +1,67 @@ +#ifndef ARCH_MMIO_H +#define ARCH_MMIO_H 1 + + +//extended read, GS is already set + +static inline __attribute__((always_inline)) uint8_t read8x(uint32_t addr) +{ + uint8_t value; + __asm__ volatile ( + "movb %%gs:(%1), %0\n\t" + :"=a"(value): "b" (addr) + ); + return value; +} + +static inline __attribute__((always_inline)) uint16_t read16x(uint32_t addr) +{ + uint16_t value; + __asm__ volatile ( + "movw %%gs:(%1), %0\n\t" + :"=a"(value): "b" (addr) + ); + + return value; + +} + +static inline __attribute__((always_inline)) uint32_t read32x(uint32_t addr) +{ + uint32_t value; + __asm__ volatile ( + "movl %%gs:(%1), %0\n\t" + :"=a"(value): "b" (addr) + ); + + return value; + +} + +static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t value) +{ + __asm__ volatile ( + "movb %1, %%gs:(%0)\n\t" + :: "b" (addr), "a" (value) + ); + +} + +static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16_t value) +{ + __asm__ volatile ( + "movw %1, %%gs:(%0)\n\t" + :: "b" (addr), "a" (value) + ); + +} + +static inline __attribute__((always_inline)) void write32x(uint32_t addr, uint32_t value) +{ + __asm__ volatile ( + "movl %1, %%gs:(%0)\n\t" + :: "b" (addr), "a" (value) + ); +} + +#endif /* ARCH_MMIO_H */ Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/pci_ops.h =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/include/arch/pci_ops.h 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/pci_ops.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -4,6 +4,10 @@ const struct pci_bus_operations pci_cf8_conf1; const struct pci_bus_operations pci_cf8_conf2; +#if MMCONF_SUPPORT==1 +const struct pci_bus_operations pci_ops_mmconf; +#endif + void pci_set_method(device_t dev); #endif /* ARCH_I386_PCI_OPS_H */ Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/pciconf.h =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/include/arch/pciconf.h 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/pciconf.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -4,6 +4,11 @@ // inclusive of ANYTHING that uses a PCI bus. #define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_DATA 0xcfc + +#if PCI_IO_CFG_EXT == 0 #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) +#else +#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) ) +#endif #endif Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -34,6 +34,12 @@ *((volatile uint32_t *)(addr)) = value; } +#if MMCONF_SUPPORT + +#include + +#endif + static inline int log2(int value) { unsigned int r = 0; @@ -76,87 +82,193 @@ #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -typedef unsigned device_t; +typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ +/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G, + * We don't need to set %fs, and %gs anymore + * Before that We need to use %gs, and leave %fs to other RAM access + */ + static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 +#endif outl(0x80000000 | (addr & ~3), 0xCF8); return inb(0xCFC + (addr & 3)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read8x(addr); +} +#endif static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) { +#if MMCONF_SUPPORT + return pci_mmio_read_config8(dev, where); +#else return pci_io_read_config8(dev, where); +#endif } static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); return inw(0xCFC + (addr & 2)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read16x(addr); +} +#endif + static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) { +#if MMCONF_SUPPORT + return pci_mmio_read_config16(dev, where); +#else return pci_io_read_config16(dev, where); +#endif } static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + return read32x(addr); +} +#endif + static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) { +#if MMCONF_SUPPORT + return pci_mmio_read_config32(dev, where); +#else return pci_io_read_config32(dev, where); +#endif } static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; + addr = dev | where; + write8x(addr, value); +} +#endif + static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) { +#if MMCONF_SUPPORT + pci_mmio_write_config8(dev, where, value); +#else pci_io_write_config8(dev, where, value); +#endif } static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); outw(value, 0xCFC + (addr & 2)); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; + addr = dev | where; + write16x(addr, value); +} +#endif + static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) { +#if MMCONF_SUPPORT + pci_mmio_write_config16(dev, where, value); +#else pci_io_write_config16(dev, where, value); +#endif } static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; +#if PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); } +#if MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; + addr = dev | where; + write32x(addr, value); +} +#endif + static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) { +#if MMCONF_SUPPORT + pci_mmio_write_config32(dev, where, value); +#else pci_io_write_config32(dev, where, value); +#endif } #define PCI_DEV_INVALID (0xffffffffU) @@ -174,7 +286,7 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev) { - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + for(; dev <= PCI_DEV(255|(((1< -#if CONFIG_USE_INIT == 0 +#if CONFIG_USE_PRINTK_IN_CAR == 0 static void __console_tx_byte(unsigned char byte) { uart_tx_byte(byte); Modified: trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -8,7 +8,11 @@ * Functions for accessing PCI configuration space with type 1 accesses */ +#if PCI_IO_CFG_EXT == 0 #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)) +#else +#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) ) +#endif static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where) { Added: trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_mmconf.c =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_mmconf.c (rev 0) +++ trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_mmconf.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -0,0 +1,63 @@ +#if MMCONF_SUPPORT + +#include +#include +#include +#include +#include +#include + + +/* + * Functions for accessing PCI configuration space with mmconf accesses + */ + +#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEVFN) & 0xFF) << 12) | \ + ((WHERE) & 0xFFF)) + +#include + +static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) +{ + return (read8x(PCI_MMIO_ADDR(bus, devfn, where))); +} + +static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) +{ + return (read16x(PCI_MMIO_ADDR(bus, devfn, where))); +} + +static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) +{ + return (read32x(PCI_MMIO_ADDR(bus, devfn, where))); +} + +static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) +{ + write8x(PCI_MMIO_ADDR(bus, devfn, where), value); +} + +static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) +{ + write8x(PCI_MMIO_ADDR(bus, devfn, where), value); +} + +static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) +{ + write8x(PCI_MMIO_ADDR(bus, devfn, where), value); +} + + +const struct pci_bus_operations pci_ops_mmconf = +{ + .read8 = pci_mmconf_read_config8, + .read16 = pci_mmconf_read_config16, + .read32 = pci_mmconf_read_config32, + .write8 = pci_mmconf_write_config8, + .write16 = pci_mmconf_write_config16, + .write32 = pci_mmconf_write_config32, +}; + +#endif Modified: trunk/LinuxBIOSv2/src/config/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/config/Options.lb 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/config/Options.lb 2006-10-04 22:56:21 UTC (rev 2439) @@ -485,6 +485,13 @@ export always comment "Default flow control settings for the 8250 serial console uart" end + +define CONFIG_USE_PRINTK_IN_CAR + default 0 + export always + comment "use printk instead of print in CAR stage code" +end + ############################################### # Mainboard options @@ -744,6 +751,12 @@ # Options for memory mapped I/O ############################################### +define PCI_IO_CFG_EXT + default 0 + export always + comment "allow 4K register space via io CFG port" +end + define PCIC0_CFGADDR default none format "0x%x" @@ -907,6 +920,18 @@ comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0" end +define PCI_BUS_SEGN_BITS + default 0 + export always + comment "It could be 0, 1, 2, 3 and 4 only" +end + +define MMCONF_SUPPORT + default 0 + export always + comment "enable mmconfig for pci conf" +end + define HW_MEM_HOLE_SIZEK default 0 export always Modified: trunk/LinuxBIOSv2/src/console/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/console/Config.lb 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/console/Config.lb 2006-10-04 22:56:21 UTC (rev 2439) @@ -3,6 +3,7 @@ uses CONFIG_CONSOLE_BTEXT uses CONFIG_CONSOLE_LOGBUF uses CONFIG_USE_INIT +uses CONFIG_USE_PRINTK_IN_CAR object printk.o if CONFIG_CONSOLE_SERIAL8250 @@ -24,5 +25,7 @@ object vsprintf.o if CONFIG_USE_INIT + if CONFIG_USE_PRINTK_IN_CAR initobject vtxprintf.o + end end Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -4,7 +4,7 @@ */ static inline void print_debug_cp_run(const char *strval, uint32_t val) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x\r\n", strval, val); #else print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/disable_cache_as_ram.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/disable_cache_as_ram.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/disable_cache_as_ram.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -2,6 +2,7 @@ /* be warned, this file will be used other cores and core 0 / node 0 */ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) { + __asm__ volatile ( /* We don't need cache as ram for now on */ @@ -43,27 +44,20 @@ ); } -/* be warned, this file will be used core 0 / node 0 and ram stack is ready*/ static void disable_cache_as_ram_bsp(void) { - __asm__ volatile ( - - "pushl %ecx\n\t" - "pushl %edx\n\t" - "pushl %eax\n\t" - + __asm__ volatile ( +// "pushl %eax\n\t" + "pushl %edx\n\t" + "pushl %ecx\n\t" ); disable_cache_as_ram(); - - __asm__ volatile ( - - "popl %eax\n\t" - "popl %edx\n\t" - "popl %ecx\n\t" - + __asm__ volatile ( + "popl %ecx\n\t" + "popl %edx\n\t" +// "popl %eax\n\t" ); } - Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -7,7 +7,7 @@ static inline void print_debug_pcar(const char *strval, uint32_t val) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x\r\n", strval, val); #else print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/fidvid.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/fidvid.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/fidvid.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -1,7 +1,9 @@ #if K8_SET_FIDVID == 1 -#define K8_SET_FIDVID_DEBUG 0 +#define K8_SET_FIDVID_DEBUG 0 +#define K8_SET_FIDVID_ONE_BY_ONE 1 + #define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 #ifndef SB_VFSMAF @@ -13,7 +15,7 @@ static inline void print_debug_fv(const char *str, unsigned val) { #if K8_SET_FIDVID_DEBUG == 1 - #if CONFIG_USE_INIT==1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%x\r\n", str, val); #else print_debug(str); print_debug_hex32(val); print_debug("\r\n"); @@ -24,7 +26,7 @@ static inline void print_debug_fv_8(const char *str, unsigned val) { #if K8_SET_FIDVID_DEBUG == 1 - #if CONFIG_USE_INIT==1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%02x\r\n", str, val); #else print_debug(str); print_debug_hex8(val); print_debug("\r\n"); @@ -35,7 +37,7 @@ static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2) { #if K8_SET_FIDVID_DEBUG == 1 - #if CONFIG_USE_INIT==1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%x%x\r\n", str, val, val2); #else print_debug(str); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); @@ -75,6 +77,25 @@ } } +#if K8_SET_FIDVID_ONE_BY_ONE == 0 +static unsigned set_fidvid_without_init(unsigned fidvid) +{ + + msr_t msr; + uint32_t vid; + uint32_t fid; + + fid = (fidvid >> 8) & 0x3f; + vid = (fidvid >> 16) & 0x3f; + + // set new FID/VID + msr.hi = 1; + msr.lo = (vid<<8) | fid; + wrmsr(0xc0010041, msr); + return fidvid; +} +#endif + static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) { //for (cur, new) there is one <1600MHz x8 to find out next_fid @@ -109,7 +130,7 @@ apicidx = lapicid(); if(apicid!=apicidx) { -#if CONFIG_USE_INIT == 1 +#if CONFIG_USE_PRINTK_IN_CAR printk_err("wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx); #else print_err("wrong apicid, we want change "); print_err_hex8(apicid); print_err(" but it is "); print_err_hex8(apicidx); print_err("\r\n"); @@ -228,9 +249,12 @@ fidvid = (vid_cur<< 16) | (fid_cur<<8); if(showmessage) { - if((fid!=fid_cur) || (vid!=vid_cur)) { - print_err("set fidvid failed\r\n"); + if(vid!=vid_cur) { + print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } + if(fid!=fid_cur) { + print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); + } } return fidvid; @@ -241,7 +265,8 @@ { uint32_t send; - uint32_t readback; + uint32_t readback = 0; + unsigned timeout = 1; msr_t msr; uint32_t vid_cur; uint32_t fid_cur; @@ -263,6 +288,7 @@ send |= ((msr.hi>>(48-32)) & 0x3f) << 16; //max vid send |= (apicid<<24); // ap apicid +#if K8_SET_FIDVID_ONE_BY_ONE == 1 vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; @@ -270,13 +296,17 @@ msr.hi = 1; msr.lo = (vid_cur<<8) | (fid_cur); wrmsr(0xc0010041, msr); +#endif - wait_cpu_state(bsp_apicid, 1); + timeout = wait_cpu_state(bsp_apicid, 1); + if(timeout) { + print_initcpu8("fidvid_ap_stage1: time out while reading from BSP on ", apicid); + } //send signal to BSP about this AP max fid and vid lapic_write(LAPIC_MSG_REG, send | 1); //AP at state 1 that sent our fid and vid // wait_cpu_state(bsp_apicid, 2);// don't need we can use apicid directly - loop = 100000; + loop = 1000000; while(--loop>0) { //remote read BSP signal that include vid and fid that need to set if(lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback)!=0) continue; @@ -284,14 +314,23 @@ } if(loop>0) { + #if K8_SET_FIDVID_ONE_BY_ONE == 1 readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP + #else + readback = set_fidvid_without_init(readback & 0xffff00); // this AP + #endif //send signal to BSP that this AP fid/vid is set // allow to change state2 is together with apicid send = (apicid<<24) | (readback & 0x00ffff00); // AP at state that We set the requested fid/vid + } else { + print_initcpu8("fidvid_ap_stage2: time out while reading from BSP on ", apicid); } lapic_write(LAPIC_MSG_REG, send | 2); - wait_cpu_state(bsp_apicid, 3); + timeout = wait_cpu_state(bsp_apicid, 3); + if(timeout) { + print_initcpu8("fidvid_ap_stage3: time out while reading from BSP on ", apicid); + } } static unsigned calc_common_fidvid(unsigned fidvid, unsigned fidvidx) @@ -311,18 +350,26 @@ static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp ) { - unsigned readback; + unsigned readback = 0; + unsigned timeout = 1; struct fidvid_st *fvp = gp; int loop; print_debug_fv("state 1: ap_apicid=", ap_apicid); - loop = 100000; + loop = 1000000; while(--loop > 0) { if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) continue; - if((readback & 0xff) == 1) break; //target ap is in stage 1 + if((readback & 0xff) == 1) { + timeout = 0; + break; //target ap is in stage 1 + } } + if(timeout) { + print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid); + return; + } print_debug_fv("\treadback=", readback); @@ -333,7 +380,8 @@ } static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp) { - unsigned readback; + unsigned readback = 0; + unsigned timeout = 1; struct fidvid_st *fvp = gp; int loop; @@ -342,12 +390,20 @@ lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid<<24) | 2); // all set to state2 - loop = 100000; + loop = 1000000; while(--loop > 0) { if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) continue; - if((readback & 0xff) == 2) break; // target ap is stage 2, and it'd FID has beed set + if((readback & 0xff) == 2) { + timeout = 0; + break; // target ap is stage 2, and it'd FID has beed set + } } + if(timeout) { + print_initcpu8("fidvid_bsp_stage2: time out while reading from ap ", ap_apicid); + return; + } + print_debug_fv("\treadback=", readback); } @@ -438,11 +494,13 @@ #endif +#if K8_SET_FIDVID_ONE_BY_ONE == 1 // set BSP fid and vid print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); print_debug_fv("common_fidvid=", fv.common_fidvid); +#endif //for all APs ( We know the APIC ID of all AP even the APIC ID is lifted) // send signal to the AP it could change it's fid/vid @@ -459,6 +517,14 @@ for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); #endif +#if K8_SET_FIDVID_ONE_BY_ONE == 0 + // set BSP fid and vid + print_debug_fv("bsp apicid=", bsp_apicid); + fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); + print_debug_fv("common_fidvid=", fv.common_fidvid); + +#endif + lapic_write(LAPIC_MSG_REG, fv.common_fidvid | (bsp_apicid<<24) | 3); // clear the state //here wait a while, so last ap could read pack, and stop it, don't call init_timer too early or just don't use init_timer Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -16,7 +16,7 @@ static inline void print_initcpu8 (const char *strval, unsigned val) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%02x\r\n", strval, val); #else print_debug(strval); print_debug_hex8(val); print_debug("\r\n"); @@ -25,7 +25,7 @@ static inline void print_initcpu8_nocr (const char *strval, unsigned val) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%02x", strval, val); #else print_debug(strval); print_debug_hex8(val); @@ -35,7 +35,7 @@ static inline void print_initcpu16 (const char *strval, unsigned val) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%04x\r\n", strval, val); #else print_debug(strval); print_debug_hex16(val); print_debug("\r\n"); @@ -44,7 +44,7 @@ static inline void print_initcpu(const char *strval, unsigned val) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x\r\n", strval, val); #else print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); @@ -171,30 +171,48 @@ static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str) { - #if CONFIG_USE_INIT == 0 + #if CONFIG_USE_PRINTK_IN_CAR + printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid); + #else print_debug(str); print_debug(" ---- {APICID = "); print_debug_hex8(apicid); print_debug(" NODEID = "), print_debug_hex8(id.nodeid); print_debug(" COREID = "), print_debug_hex8(id.coreid); print_debug("} --- \r\n"); - #else - printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid); #endif } -static void wait_cpu_state(unsigned apicid, unsigned state) +static unsigned wait_cpu_state(unsigned apicid, unsigned state) { - unsigned readback; - int loop =100000; + unsigned readback = 0; + unsigned timeout = 1; + int loop = 2000000; while(--loop>0) { if(lapic_remote_read(apicid, LAPIC_MSG_REG, &readback)!=0) continue; - if((readback & 0xff) == state) break; //target cpu is in stage started + if((readback & 0xff) == state) { + timeout = 0; + break; //target cpu is in stage started + } } + if(timeout) { + if(readback) { + timeout = readback; + } + } + + return timeout; } static void wait_ap_started(unsigned ap_apicid, void *gp ) { - wait_cpu_state(ap_apicid, 0x33); // started - print_initcpu8_nocr(" ", ap_apicid); + unsigned timeout; + timeout = wait_cpu_state(ap_apicid, 0x33); // started + if(timeout) { + print_initcpu8_nocr("*", ap_apicid); + print_initcpu("*", timeout); + } + else { + print_initcpu8_nocr(" ", ap_apicid); + } } static void wait_all_aps_started(unsigned bsp_apicid) @@ -219,18 +237,17 @@ disable_cache_as_ram(); // inline stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... } -#if RAMINIT_SYSINFO == 1 -#if MEM_TRAIN_SEQ != 1 -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) {} -#else -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); +#ifndef MEM_TRAIN_SEQ +#define MEM_TRAIN_SEQ 0 #endif + +#if MEM_TRAIN_SEQ == 1 +static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); #endif #if RAMINIT_SYSINFO == 1 - static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo) #else static unsigned init_cpus(unsigned cpu_init_detectedx) @@ -311,6 +328,8 @@ lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x33); // mark the cpu is started if(apicid != bsp_apicid) { + unsigned timeout=1; + unsigned loop = 100; #if K8_SET_FIDVID == 1 #if (CONFIG_LOGICAL_CPUS == 1) && (K8_SET_FIDVID_CORE0_ONLY == 1) if(id.coreid == 0 ) // only need set fid for core0 @@ -319,10 +338,15 @@ #endif // We need to stop the CACHE as RAM for this CPU, really? - wait_cpu_state(bsp_apicid, 0x44); + while(timeout && (loop-->0)) { + timeout = wait_cpu_state(bsp_apicid, 0x44); + } + if(timeout) { + print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid); + } lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu set_init_ram_access(); - #if RAMINIT_SYSINFO == 1 + #if MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU); #endif Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_init.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_init.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -686,9 +686,12 @@ { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */ { X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */ { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */ + { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 Socket AM2: Athlon64 */ { X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */ { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */ { X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */ + { X86_VENDOR_AMD, 0xc0f13 }, /* AM2 : Athlon64 FX*/ + { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 Socket AM2: Athlon64 */ #endif { 0, 0 }, Modified: trunk/LinuxBIOSv2/src/devices/device_util.c =================================================================== --- trunk/LinuxBIOSv2/src/devices/device_util.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/devices/device_util.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -139,9 +139,15 @@ memcpy(buffer, "Root Device", 12); break; case DEVICE_PATH_PCI: +#if PCI_BUS_SEGN_BITS + sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", + dev->bus->secondary>>8, dev->bus->secondary & 0xff, + PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn)); +#else sprintf(buffer, "PCI: %02x:%02x.%01x", dev->bus->secondary, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn)); +#endif break; case DEVICE_PATH_PNP: sprintf(buffer, "PNP: %04x.%01x", @@ -430,7 +436,11 @@ end = resource_end(resource); buf[0] = '\0'; if (resource->flags & IORESOURCE_PCI_BRIDGE) { +#if PCI_BUS_SEGN_BITS + sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link[0].secondary & 0xff); +#else sprintf(buf, "bus %02x ", dev->link[0].secondary); +#endif } printk_debug( "%s %02x <- [0x%010Lx - 0x%010Lx] %s%s%s\n", Modified: trunk/LinuxBIOSv2/src/devices/pci_device.c =================================================================== --- trunk/LinuxBIOSv2/src/devices/pci_device.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/devices/pci_device.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -761,9 +761,7 @@ return; } - printk_debug("%s: seeking driver for %x:%x class %x\n", - __FUNCTION__, dev->vendor, dev->device, dev->class); - /* Look through the list of setup drivers and find one for + /* Look through the list of setup drivers and find one for * this pci device */ for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { @@ -1004,7 +1002,11 @@ device_t old_devices; device_t child; - printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary); +#if PCI_BUS_SEGN_BITS + printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff); +#else + printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary); +#endif old_devices = bus->children; bus->children = 0; @@ -1062,7 +1064,7 @@ * * Return how far we've got finding sub-buses. */ - printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max); + printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max); post_code(0x55); return max; } Modified: trunk/LinuxBIOSv2/src/drivers/i2c/adm1027/adm1027.c =================================================================== --- trunk/LinuxBIOSv2/src/drivers/i2c/adm1027/adm1027.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/drivers/i2c/adm1027/adm1027.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -36,6 +36,7 @@ if (!(result & CFG1_STRT)) { printk_debug("ADM1027: monitoring would not enable\r\n"); } + printk_debug("ADM1027: monitoring enabled\r\n"); } static void adm1027_init(device_t dev) Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -10,6 +10,7 @@ unsigned hc_possible_num; unsigned pci1234[HC_POSSIBLE_NUM]; unsigned hcdn[HC_POSSIBLE_NUM]; + unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type unsigned sbdn; unsigned sblk; Modified: trunk/LinuxBIOSv2/src/lib/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/lib/Config.lb 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/lib/Config.lb 2006-10-04 22:56:21 UTC (rev 2439) @@ -1,5 +1,6 @@ uses HAVE_FALLBACK_BOOT uses CONFIG_USE_INIT +uses CONFIG_USE_PRINTK_IN_CAR object clog2.o object uart8250.o @@ -16,7 +17,9 @@ makedefine .PHONY : version.o if CONFIG_USE_INIT + if CONFIG_USE_PRINTK_IN_CAR initobject uart8250.c + end initobject memset.o initobject memcpy.o initobject memcmp.o Modified: trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -192,7 +192,7 @@ print_err("E\n"); enable_smbus(); -#if 1 +#if 0 dump_spd_registers(&cpu[0]); #endif print_err("F\n"); Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb 2006-10-04 22:56:21 UTC (rev 2439) @@ -105,6 +105,20 @@ action "mv pci2.hex ssdt2.c" end object ./ssdt2.o + makerule ssdt3.c + depends "$(MAINBOARD)/dx/pci3.asl" + action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" + action "mv pci3.hex ssdt3.c" + end + object ./ssdt3.o + makerule ssdt4.c + depends "$(MAINBOARD)/dx/pci4.asl" + action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" + action "mv pci4.hex ssdt4.c" + end + object ./ssdt4.o end end Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb 2006-10-04 22:56:21 UTC (rev 2439) @@ -89,6 +89,8 @@ uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_USE_PRINTK_IN_CAR + ### ### Build options ### @@ -212,9 +214,12 @@ default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 + +## +## for rev F training on AP purpose +## default CONFIG_AP_CODE_IN_CAR=1 default MEM_TRAIN_SEQ=1 - default WAIT_BEFORE_CPUS_INIT=1 ## @@ -271,8 +276,8 @@ ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc-3.4.5 -m32" -default HOSTCC="gcc-3.4.5" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -282,6 +287,7 @@ ## ## The Serial Console ## +default CONFIG_USE_PRINTK_IN_CAR=0 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Deleted: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a 2006-10-04 22:56:21 UTC (rev 2439) @@ -1,25 +0,0 @@ -echo "Creating for ACPI hex for bus 1 Conf" -cd dx -iasl -tc dsdt_lb.dsl -rm DSDT.aml -mv dsdt_lb.hex ../dsdt.c -iasl -tc pci2.asl -rm SSDT2.aml -perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex -mv pci2.hex ../ssdt2.c -cd .. -echo "Creating for ACPI hex for bus 0 Conf" -cd dx_bus0 -iasl -tc dsdt_lb.dsl -rm DSDT.aml -mv dsdt_lb.hex ../dsdt_bus0.c -iasl -tc pci2.asl -rm SSDT2.aml -perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex -mv pci2.hex ../ssdt2_bus0.c -cd .. -echo "Creating ssdt" -iasl -tc ssdt_lb_x.dsl -rm SSDT.aml -perl -e 's/AmlCode/AmlCode_ssdt/g' -pi ssdt_lb_x.hex -mv ssdt_lb_x.hex ssdt.c Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -42,12 +42,8 @@ #if ACPI_SSDTX_NUM >= 1 extern unsigned char AmlCode_ssdt2[]; -//extern unsigned char AmlCode_ssdt3[]; -//extern unsigned char AmlCode_ssdt4[]; -//extern unsigned char AmlCode_ssdt5[]; -//extern unsigned char AmlCode_ssdt6[]; -//extern unsigned char AmlCode_ssdt7[]; -//extern unsigned char AmlCode_ssdt8[]; +extern unsigned char AmlCode_ssdt3[]; +extern unsigned char AmlCode_ssdt4[]; #endif #define IO_APIC_ADDR 0xfec00000UL @@ -90,6 +86,51 @@ gsi_base+=7; } } + + int i; + int j = 0; + + for(i=1; i< sysconf.hc_possible_num; i++) { + unsigned d; + if(!(sysconf.pci1234[i] & 0x1) ) continue; + // 8131 need to use +4 + + switch (sysconf.hcid[i]) { + case 1: + d = 7; + break; + case 3: + d = 4; + break; + } + switch (sysconf.hcid[i]) { + case 1: + case 3: + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], + res->base, gsi_base ); + gsi_base+=d; + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], + res->base, gsi_base ); + gsi_base+=d; + + } + } + break; + } + + j++; + } + } current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) @@ -112,6 +153,29 @@ extern void update_ssdt(void *ssdt); +void update_ssdtx(void *ssdtx, int i) +{ + uint8_t *PCI; + uint8_t *HCIN; + uint8_t *UID; + + PCI = ssdtx + 0x32; + HCIN = ssdtx + 0x39; + UID = ssdtx + 0x40; + + if(i<7) { + *PCI = (uint8_t) ('4' + i - 1); + } + else { + *PCI = (uint8_t) ('A' + i - 1 - 6); + } + *HCIN = (uint8_t) i; + *UID = (uint8_t) (i+3); + + /* FIXME: need to update the GSI id in the ssdtx too */ + +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -126,6 +190,7 @@ acpi_header_t *dsdt; acpi_header_t *ssdt; acpi_header_t *ssdtx; + unsigned char *p; unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM]; @@ -195,28 +260,43 @@ acpi_add_table(rsdt,ssdt); #if ACPI_SSDTX_NUM >= 1 - // we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1] - AmlCode_ssdtx[1] = AmlCode_ssdt2; -// AmlCode_ssdtx[2] = AmlCode_ssdt3; -// AmlCode_ssdtx[3] = AmlCode_ssdt4; -// AmlCode_ssdtx[4] = AmlCode_ssdt5; -// AmlCode_ssdtx[5] = AmlCode_ssdt6; -// AmlCode_ssdtx[6] = AmlCode_ssdt7; -// AmlCode_ssdtx[7] = AmlCode_ssdt8; - //same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table - - for(i=1;ilength; - memcpy((void *)ssdtx, (void *)AmlCode_ssdtx[i], ((acpi_header_t *)AmlCode_ssdtx[i])->length); - acpi_add_table(rsdt,ssdtx); - } + //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + + for(i=1;ilength; + memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length); + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); + acpi_add_table(rsdt,ssdtx); + } #endif - /* FACS */ printk_debug("ACPI: * FACS\n"); facs = (acpi_facs_t *) current; Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -21,6 +21,16 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" + +#if CONFIG_USE_INIT == 0 + #include "lib/memcpy.c" + #if CONFIG_USE_PRINTK_IN_CAR == 1 + #include "lib/uart8250.c" + #include "console/vtxprintf.c" + #include "arch/i386/lib/printk_init.c" + #endif +#endif + #include "arch/i386/lib/console.c" #if 0 @@ -40,11 +50,7 @@ #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - //#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -72,7 +78,11 @@ id = get_node_core_id_x(); +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("CODE IN CACHE ON NODE: %02x\n"); +#else print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); +#endif train_ram(id.nodeid, sysinfo, sysinfox); Deleted: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c 2006-10-04 22:56:21 UTC (rev 2439) @@ -1,5 +0,0 @@ -rm dsdt.c -rm ssdt2.c -rm dsdt_bus0.c -rm ssdt2_bus0.c -rm ssdt.c Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -15,16 +15,13 @@ //used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define K8_SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -//0: three for in bsp, only this one support F0_F1 workaround -//1: on every core0 -//2: one for on bsp -//#define MEM_TRAIN_SEQ 1 - +#if K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 +#endif #include #include @@ -59,14 +56,19 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" #if USE_FAILOVER_IMAGE==0 +#include "cpu/x86/bist.h" #include "lib/delay.c" #if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" + #if CONFIG_USE_PRINTK_IN_CAR == 1 + #include "lib/uart8250.c" + #include "console/vtxprintf.c" + #include "arch/i386/lib/printk_init.c" + #endif #endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -123,12 +125,12 @@ return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8_f.h" +#include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" +#include "northbridge/amd/amdk8/raminit.c" #include "sdram/generic_sdram.c" @@ -263,8 +265,6 @@ unsigned bsp_apicid = 0; if (bist == 0) { - //It's the time to set ctrl in sysinfo now; - fill_mem_ctrl(CONFIG_MAX_PHYSICAL_CPUS, sysinfo->ctrl, spd_addr); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } @@ -281,7 +281,7 @@ print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); - setup_serengeti_cheetah_resource_map(); + setup_mb_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); @@ -350,10 +350,8 @@ #endif allow_all_aps_stop(bsp_apicid); -#if 0 //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); -#endif enable_smbus(); Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl 2006-10-04 22:56:21 UTC (rev 2439) @@ -23,21 +23,21 @@ External (\_SB.PCI0.LNKC, DeviceObj) External (\_SB.PCI0.LNKD, DeviceObj) - Device (PCI2) + Device (PCIX) { // BUS ? Second HT Chain - Name (HCIN, 0x01) // HC2 + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { - Return (DADD(GHCN(HCIN), 0x00180000)) + Return (DADD(GHCN(HCIN), 0x00000000)) } - Name (_UID, 0x03) - Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl 2006-10-04 22:56:21 UTC (rev 2439) @@ -1 +1 @@ - Include ("amd8151.asl") + Include ("amd8132_2.asl") Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -42,13 +42,44 @@ static unsigned get_bus_conf_done = 0; +static unsigned get_hcid(unsigned i) +{ + unsigned id = 0; + + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + + unsigned devn = sysconf.hcdn[i] & 0xff; + + device_t dev; + + dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + + switch (dev->device) { + case 0x7458: //8132 + id = 1; + break; + case 0x7454: //8151 + id = 2; + break; + case 0x7450: //8131 + id = 3; + break; + } + + // we may need more way to find out hcid: subsystem id? GPIO read ? + + // we need use id for 1. bus num, 2. mptable, 3. acpi table + + return id; +} + void get_bus_conf(void) { unsigned apicid_base; device_t dev; - int i; + int i, j; struct mb_sysconf_t *m; if(get_bus_conf_done == 1) return; //do it only once @@ -69,7 +100,6 @@ sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; - m->sbdn5 = sysconf.hcdn[1] & 0xff; m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_8111_0 = m->bus_8132_0; @@ -112,22 +142,69 @@ } /* HT chain 1 */ - if((sysconf.pci1234[1] & 0x1) == 1) { - m->bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; - /* 8151 */ - dev = dev_find_slot(m->bus_8151_0, PCI_DEVFN(m->sbdn5+1, 0)); + j=0; + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; - if (dev) { - m->bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -// printk_debug("bus_8151_1=%d\n",bus_8151_1); - m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - m->bus_isa++; - } - else { - printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151_0, m->sbdn5+1); - } + // check hcid type here + sysconf.hcid[i] = get_hcid(i); + + switch(sysconf.hcid[i]) { + + case 1: //8132 + case 3: //8131 + + m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; + + m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; + + /* 8132-1 */ + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0)); + if (dev) { + m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]); + } + + /* 8132-2 */ + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0)); + if (dev) { + m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; + // printk_debug("bus_isa=%d\n",bus_isa); + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1); + } + + break; + + case 2: //8151 + + m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; + m->sbdn5[j] = sysconf.hcdn[i] & 0xff; + /* 8151 */ + dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0)); + + if (dev) { + m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + // printk_debug("bus_8151_1=%d\n",bus_8151[j][1]); + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1); + } + + break; + } + + j++; } + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); @@ -137,4 +214,9 @@ m->apicid_8111 = apicid_base+0; m->apicid_8132_1 = apicid_base+1; m->apicid_8132_2 = apicid_base+2; + for(i=0;iapicid_8132a[i][0] = apicid_base + 3 + i*2; + m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1; + } + } Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -113,14 +113,20 @@ //pcix bridge // write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; + + int j = 0; + + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff; + + write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + j++; + + } - if(sysconf.pci1234[1] & 0xf) { - //agp bridge - write_pirq_info(pirq_info, m->bus_8151_0, (m->sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - } - - pirq_info++; slot_num++; - pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -9,14 +9,20 @@ unsigned char bus_8132_2; unsigned char bus_8111_0; unsigned char bus_8111_1; - unsigned char bus_8151_0; - unsigned char bus_8151_1; - unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned sbdn3; - unsigned sbdn5; + unsigned char bus_8132a[7][3]; + + unsigned char bus_8151[7][2]; + + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2]; + + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7]; + }; #endif Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -20,7 +20,7 @@ struct mp_config_table *mc; unsigned char bus_num; - int i; + int i, j; struct mb_sysconf_t *m; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -72,6 +72,34 @@ smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); } } + + j = 0; + + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + + switch(sysconf.hcid[i]) { + case 1: // 8132 + case 3: // 8131 + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); + } + } + break; + } + j++; + } + } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ @@ -95,11 +123,6 @@ // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); - if(sysconf.pci1234[1] & 0xf) { - // Slot AGP - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151_1, 0x0, m->apicid_8111, 0x11); - } - //Slot 3 PCI 32 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 @@ -123,7 +146,51 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 } + j = 0; + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + int ii; + device_t dev; + struct resource *res; + switch(sysconf.hcid[i]) { + case 1: + case 3: + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + //Slot 1 PCI-X 133/100/66 + for(ii=0;ii<4;ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + } + } + } + + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + //Slot 2 PCI-X 133/100/66 + for(ii=0;ii<4;ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + } + } + } + + break; + case 2: + + // Slot AGP + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); + break; + } + + j++; + } + + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -1,9 +1,8 @@ /* - * AMD serengeti_cheetah needs a different resource map * */ -static void setup_serengeti_cheetah_resource_map(void) +static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb 2006-10-04 22:56:21 UTC (rev 2439) @@ -2,12 +2,17 @@ ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## -if USE_FALLBACK_IMAGE +if USE_FAILOVER_IMAGE + default ROM_SECTION_SIZE = FAILOVER_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) +else + if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) default ROM_SECTION_OFFSET = 0 + end end ## @@ -30,8 +35,17 @@ ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +if USE_FAILOVER_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +else + if USE_FALLBACK_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + else + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + end +end + arch i386 end ## @@ -74,45 +88,22 @@ if HAVE_ACPI_TABLES object acpi_tables.o object fadt.o - if SB_HT_CHAIN_ON_BUS0 - makerule dsdt.c - depends "$(MAINBOARD)/dx_bus0/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/dsdt_lb.dsl" - action "mv dsdt_lb.hex dsdt.c" - end - else - makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" - action "mv dsdt_lb.hex dsdt.c" - end + makerule dsdt.c + depends "$(MAINBOARD)/dx/dsdt_lb.dsl" + action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o - makerule ssdt.c - depends "$(MAINBOARD)/ssdt_lb_x.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex" - action "mv ssdt_lb_x.hex ssdt.c" - end - object ./ssdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb if ACPI_SSDTX_NUM - if SB_HT_CHAIN_ON_BUS0 - makerule ssdt2.c + makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" - end - else - makerule ssdt2.c - depends "$(MAINBOARD)/dx_bus0/pci2.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/pci2.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" - action "mv pci2.hex ssdt2.c" - end - end + end object ./ssdt2.o end end @@ -123,7 +114,7 @@ # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else @@ -164,10 +155,16 @@ ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## - -if USE_FALLBACK_IMAGE +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end end mainboardinit cpu/x86/32bit/entry32.inc @@ -184,12 +181,22 @@ ## ## Build our reset vector (This is where linuxBIOS is entered) ## -if USE_FALLBACK_IMAGE +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds + end end if USE_DCACHE_RAM @@ -216,13 +223,21 @@ ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover_failover.lds + end + end +else + if USE_FALLBACK_IMAGE + if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds else ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end + end end ### Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb 2006-10-04 22:56:21 UTC (rev 2439) @@ -4,6 +4,8 @@ uses ACPI_SSDTX_NUM uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT +uses USE_FAILOVER_IMAGE +uses HAVE_FAILOVER_BOOT uses HAVE_HARD_RESET uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE @@ -13,6 +15,7 @@ uses CONFIG_IOAPIC uses CONFIG_SMP uses FALLBACK_SIZE +uses FAILOVER_SIZE uses ROM_SIZE uses ROM_SECTION_SIZE uses ROM_IMAGE_SIZE @@ -76,7 +79,10 @@ uses CONFIG_PCI_64BIT_PREF_MEM +uses CONFIG_LB_MEM_TOPK +uses CONFIG_USE_PRINTK_IN_CAR + ### ### Build options ### @@ -90,13 +96,20 @@ ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## #default FALLBACK_SIZE=131072 -#256K -default FALLBACK_SIZE=0x40000 +#default FALLBACK_SIZE=0x40000 +#FALLBACK: 256K-4K +default FALLBACK_SIZE=0x3f000 +#FAILOVER: 4K +default FAILOVER_SIZE=0x01000 + +default CONFIG_LB_MEM_TOPK=2048 + ## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1 +default HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from linuxBIOS @@ -141,7 +154,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +default SERIAL_CPU_INIT=0 default ENABLE_APIC_EXT_ID=0 default APIC_ID_OFFSET=0x8 @@ -152,9 +165,9 @@ #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -default HW_MEM_HOLE_SIZEK=0x200000 +#default HW_MEM_HOLE_SIZEK=0x200000 #1G -#default HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #512M #default HW_MEM_HOLE_SIZEK=0x80000 @@ -169,13 +182,13 @@ default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset -default HT_CHAIN_UNITID_BASE=0x4 +default HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default SB_HT_CHAIN_ON_BUS0=2 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -221,7 +234,7 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) ## ## LinuxBIOS C code runs at this location in RAM @@ -240,8 +253,8 @@ ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32" +default HOSTCC="gcc-4.0.2" ## ## Disable the gdb stub by default @@ -251,6 +264,7 @@ ## ## The Serial Console ## +default CONFIG_USE_PRINTK_IN_CAR=1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/acpi_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/acpi_tables.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/acpi_tables.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -15,8 +15,9 @@ #include #include #include +#include -#define DUMP_ACPI_TABLES 1 +#define DUMP_ACPI_TABLES 0 #if DUMP_ACPI_TABLES == 1 static void dump_mem(unsigned start, unsigned end) @@ -34,7 +35,6 @@ } #endif -#define HC_POSSIBLE_NUM 8 extern unsigned char AmlCode[]; extern unsigned char AmlCode_ssdt[]; @@ -62,12 +62,6 @@ extern unsigned apicid_8132_1; extern unsigned apicid_8132_2; -extern unsigned pci1234[]; -extern unsigned hc_possible_num; -extern unsigned sblk; -extern unsigned sbdn; -extern unsigned hcdn[]; - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base=0x18; @@ -83,7 +77,7 @@ { device_t dev; struct resource *res; - dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0]&0xff), 1)); + dev = dev_find_slot(bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -93,7 +87,7 @@ } } - dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0] & 0xff)+1, 1)); + dev = dev_find_slot(bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -120,79 +114,10 @@ return current; } -//FIXME: next could be moved to northbridge/amd/amdk8/amdk8_acpi.c or cpu/amd/k8/k8_acpi.c begin -static void int_to_stream(uint32_t val, uint8_t *dest) -{ - int i; - for(i=0;i<4;i++) { - *(dest+i) = (val >> (8*i)) & 0xff; - } -} - extern void get_bus_conf(void); -static void update_ssdt(void *ssdt) -{ - uint8_t *BUSN; - uint8_t *MMIO; - uint8_t *PCIO; - uint8_t *SBLK; - uint8_t *TOM1; - uint8_t *SBDN; - uint8_t *HCLK; - uint8_t *HCDN; +extern void update_ssdt(void *ssdt); - int i; - device_t dev; - uint32_t dword; - msr_t msr; - - BUSN = ssdt+0x3a; //+5 will be next BUSN - MMIO = ssdt+0x57; //+5 will be next MMIO - PCIO = ssdt+0xaf; //+5 will be next PCIO - SBLK = ssdt+0xdc; // one byte - TOM1 = ssdt+0xe3; // - SBDN = ssdt+0xed;// - HCLK = ssdt+0xfa; //+5 will be next HCLK - HCDN = ssdt+0x12a; //+5 will be next HCDN - - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - - for(i=0;i<4;i++) { - dword = pci_read_config32(dev, 0xe0+i*4); - int_to_stream(dword, BUSN+i*5); - } - - for(i=0;i<0x10;i++) { - dword = pci_read_config32(dev, 0x80+i*4); - int_to_stream(dword, MMIO+i*5); - } - - for(i=0;i<0x08;i++) { - dword = pci_read_config32(dev, 0xc0+i*4); - int_to_stream(dword, PCIO+i*5); - } - - *SBLK = (uint8_t)(sblk); - - msr = rdmsr(TOP_MEM); - int_to_stream(msr.lo, TOM1); - - for(i=0;ilength; Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -8,7 +8,7 @@ #endif //use by raminit -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 //used by incoherent_ht //#define K8_SCAN_PCI_BUS 1 @@ -23,6 +23,8 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" + +#if USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" @@ -43,12 +45,22 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +#if USE_FAILOVER_IMAGE==0 + #if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" + #if CONFIG_USE_PRINTK_IN_CAR == 1 + #include "lib/uart8250.c" + #include "console/vtxprintf.c" + #include "arch/i386/lib/printk_init.c" + #endif #endif -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -137,8 +149,10 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#endif +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) + #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -184,22 +198,35 @@ fallback_image: // post_code(0x25); +#if HAVE_FAILOVER_BOOT==1 + __asm__ volatile ("jmp __fallback_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ) +#endif ; } #endif - void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); +#if HAVE_FAILOVER_BOOT==1 + #if USE_FAILOVER_IMAGE==1 + failover_process(bist, cpu_init_detectedx); + #else + real_main(bist, cpu_init_detectedx); + #endif +#else + #if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); + #endif + real_main(bist, cpu_init_detectedx); #endif - real_main(bist, cpu_init_detectedx); - } +#if USE_FAILOVER_IMAGE==0 + void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -242,13 +269,17 @@ needs_reset = setup_coherent_ht_domain(); - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + needs_reset |= ht_setup_chains_x(); if (needs_reset) { @@ -287,3 +318,5 @@ post_cache_as_ram(); } + +#endif Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cmos.layout 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cmos.layout 2006-10-04 22:56:21 UTC (rev 2439) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl 2006-10-04 22:56:21 UTC (rev 2439) @@ -12,10 +12,10 @@ Name (PICM, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00}, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00} + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} }) Name (DNCG, Ones) @@ -147,20 +147,20 @@ Name (PICM, Package (0x0C) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //Slot 4 - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4 + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, //Slot 3 - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 } + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3 + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } }) Method (_PRT, 0, NotSerialized) Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl 2006-10-04 22:56:21 UTC (rev 2439) @@ -9,7 +9,7 @@ Name (_UID, 0x01) Method (_STA, 0, NotSerialized) { - And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local0) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0) If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled Else { Return (0x0B) } //Enabled } @@ -26,7 +26,7 @@ Method (_DIS, 0, NotSerialized) { Store (0x01, Local3) - And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) Store (Local1, Local2) If (LGreater (Local1, 0x07)) { @@ -35,7 +35,7 @@ ShiftLeft (Local3, Local1, Local3) Not (Local3, Local3) - And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) } Method (_CRS, 0, NotSerialized) @@ -48,7 +48,7 @@ CreateByteField (BUFA, 0x02, IRA2) Store (0x00, Local3) Store (0x00, Local4) - And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) If (LNot (LEqual (Local1, 0x00))) { // Routing enable If (LGreater (Local1, 0x07)) @@ -85,8 +85,8 @@ ShiftRight (Local0, 0x01, Local0) } - And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA) - Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) + Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) } } @@ -96,7 +96,7 @@ Name (_UID, 0x02) Method (_STA, 0, NotSerialized) { - And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local0) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0) If (LEqual (Local0, 0x00)) { Return (0x09) } Else { Return (0x0B) } } @@ -113,7 +113,7 @@ Method (_DIS, 0, NotSerialized) { Store (0x01, Local3) - And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) ShiftRight (Local1, 0x04, Local1) Store (Local1, Local2) If (LGreater (Local1, 0x07)) @@ -123,7 +123,7 @@ ShiftLeft (Local3, Local1, Local3) Not (Local3, Local3) - And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) } Method (_CRS, 0, NotSerialized) @@ -136,7 +136,7 @@ CreateByteField (BUFB, 0x02, IRB2) Store (0x00, Local3) Store (0x00, Local4) - And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1) + And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) ShiftRight (Local1, 0x04, Local1) If (LNot (LEqual (Local1, 0x00))) { @@ -174,9 +174,9 @@ ShiftRight (Local0, 0x01, Local0) } - And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA) + And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) ShiftLeft (Local1, 0x04, Local1) - Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA) + Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) } } @@ -186,7 +186,7 @@ Name (_UID, 0x03) Method (_STA, 0, NotSerialized) { - And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local0) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0) If (LEqual (Local0, 0x00)) { Return (0x09) } Else { Return (0x0B) } } @@ -203,7 +203,7 @@ Method (_DIS, 0, NotSerialized) { Store (0x01, Local3) - And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) Store (Local1, Local2) If (LGreater (Local1, 0x07)) { @@ -212,7 +212,7 @@ ShiftLeft (Local3, Local1, Local3) Not (Local3, Local3) - And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) } Method (_CRS, 0, NotSerialized) @@ -225,7 +225,7 @@ CreateByteField (BUFA, 0x02, IRA2) Store (0x00, Local3) Store (0x00, Local4) - And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) If (LNot (LEqual (Local1, 0x00))) { If (LGreater (Local1, 0x07)) @@ -262,8 +262,8 @@ ShiftRight (Local0, 0x01, Local0) } - And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC) - Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) + Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) } } @@ -273,7 +273,7 @@ Name (_UID, 0x04) Method (_STA, 0, NotSerialized) { - And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local0) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0) If (LEqual (Local0, 0x00)) { Return (0x09) } Else { Return (0x0B) } } @@ -290,7 +290,7 @@ Method (_DIS, 0, NotSerialized) { Store (0x01, Local3) - And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) ShiftRight (Local1, 0x04, Local1) Store (Local1, Local2) If (LGreater (Local1, 0x07)) @@ -300,7 +300,7 @@ ShiftLeft (Local3, Local1, Local3) Not (Local3, Local3) - And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) } Method (_CRS, 0, NotSerialized) @@ -313,7 +313,7 @@ CreateByteField (BUFB, 0x02, IRB2) Store (0x00, Local3) Store (0x00, Local4) - And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1) + And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) ShiftRight (Local1, 0x04, Local1) If (LNot (LEqual (Local1, 0x00))) { @@ -351,9 +351,9 @@ ShiftRight (Local0, 0x01, Local0) } - And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC) + And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) ShiftLeft (Local1, 0x04, Local1) - Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC) + Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) } } Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl 2006-10-04 22:56:21 UTC (rev 2439) @@ -50,30 +50,30 @@ }) Name (PICM, Package (0x14) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) { @@ -106,10 +106,10 @@ }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) { Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl 2006-10-04 22:56:21 UTC (rev 2439) @@ -15,10 +15,10 @@ }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 } + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) { Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl 2006-10-04 22:56:21 UTC (rev 2439) @@ -25,25 +25,6 @@ { /* BUS0 root bus */ -/* -//hardcode begin - Name (BUSN, Package (0x04) { 0x04010003, 0x06050013, 0x00000000, 0x00000000 }) - Name (MMIO, Package (0x10) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00f43003, 0x00f44f01, 0x0000d003, 0x00efff01, 0x00f40003, 0x00f42f00, 0x00f45003, 0x00f44f00 }) - Name (PCIO, Package (0x08) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001003, 0x00001000, 0x00002003, 0x00002001 }) - Name (SBLK, 0x00) - Name (TOM1, 0x40000000) - - // for AMD opteron we could have four chains, so we will have PCI1, PCI2, PCI3, PCI4 - // PCI1 must be SBLK Chain - // If you have HT IO card that is connected to PCI2, PCI3, PCI4, then you man put Device in SSDT2, SSDT3, SSDT4, - // in acpi_tables.c you can link those SSDT to RSDT according to it's presence. - // Otherwise put the PCI2, PCI3, PCI4 in this dsdt - Name (HCLK, Package (0x04) { 0x00000001, 0x00000011, 0x00000000, 0x00000000 }) //[0,3]=1 enable [4,7]=node_id, [8,15]=linkn - - Name (SBDN, 3) // 8111 UnitID Base -//hardcode end -*/ External (BUSN) External (MMIO) External (PCIO) @@ -52,35 +33,18 @@ External (HCLK) External (SBDN) External (HCDN) + External (CBST) + Name (_HID, EisaId ("PNP0A03")) Name (_ADR, 0x00180000) Name (_UID, 0x01) - Name (_BBN, 0) + Name (HCIN, 0x00) // HC1 - // define L1IC Link1 on node0 init completed, so node1 is installed - // We must make sure our bus is 0 ? - OperationRegion (LDT1, PCI_Config, 0xA4, 0x01) - Field (LDT1, ByteAcc, Lock, Preserve) - { - , 5, - L1IC, 1 - } - - } - - Device (PCI1) - { - - Name (HCIN, 0x00) // HC1 - // BUS 1 first HT Chain - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180000) // Fake - Name (_UID, 0x02) Method (_BBN, 0, NotSerialized) { - Return (GBUS (0x00, \_SB.PCI0.SBLK)) + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) } Method (_CRS, 0, NotSerialized) @@ -139,72 +103,44 @@ Return (Local3) } - Include ("pci1_hc.asl") + Include ("pci0_hc.asl") } -/* - Device (PCI2) + Device (PCI1) { - - // BUS ? Second HT Chain - Name (HCIN, 0x01) // HC2 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00180000)) - } - Name (_UID, 0x03) - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - + Name (_HID, "PNP0A03") + Name (_ADR, 0x00000000) + Name (_UID, 0x02) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.PCI0.CBST) } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - Include ("pci2_hc.asl") + Name (_BBN, 0x00) } -*/ + } Scope (_GPE) { Method (_L08, 0, NotSerialized) { - Notify (\_SB.PCI1, 0x02) //PME# Wakeup + Notify (\_SB.PCI0, 0x02) //PME# Wakeup } Method (_L0F, 0, NotSerialized) { - Notify (\_SB.PCI1.TP2P.USB0, 0x02) //USB Wakeup + Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup } Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B { - Notify (\_SB.PCI1.PG0B, 0x02) + Notify (\_SB.PCI0.PG0B, 0x02) } Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A { - Notify (\_SB.PCI1.PG0A, 0x02) + Notify (\_SB.PCI0.PG0A, 0x02) } } Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci2.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci2.asl 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci2.asl 2006-10-04 22:56:21 UTC (rev 2439) @@ -18,10 +18,10 @@ External (PICF) - External (\_SB.PCI1.LNKA, DeviceObj) - External (\_SB.PCI1.LNKB, DeviceObj) - External (\_SB.PCI1.LNKC, DeviceObj) - External (\_SB.PCI1.LNKD, DeviceObj) + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) Device (PCI2) { Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/get_bus_conf.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/get_bus_conf.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -7,9 +7,10 @@ #include #endif +#include + // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default unsigned char bus_isa = 7 ; unsigned char bus_8132_0 = 1; unsigned char bus_8132_1 = 2; @@ -22,8 +23,7 @@ unsigned apicid_8132_1; unsigned apicid_8132_2; -unsigned sblk; -unsigned pci1234[] = +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -35,9 +35,7 @@ // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -48,6 +46,7 @@ // 0x20202020, // 0x20202020, }; + unsigned sbdn3; unsigned sbdn5; @@ -61,25 +60,29 @@ unsigned apicid_base; device_t dev; + int i; if(get_bus_conf_done==1) return; //do it only once get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 8) & 0xff; - sbdn3 = hcdn[0] & 0xff; - sbdn5 = hcdn[1] & 0xff; + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + sbdn3 = sysconf.hcdn[0] & 0xff; + sbdn5 = sysconf.hcdn[1] & 0xff; -// bus_8132_0 = node_link_to_bus(0, sblk); - bus_8132_0 = (pci1234[0] >> 16) & 0xff; + bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_8111_0 = bus_8132_0; /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0)); + dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); #if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE @@ -89,35 +92,35 @@ #endif } else { - printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8111_0, sysconf.sbdn); } /* 8132-1 */ dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3,0)); if (dev) { bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; -// printk_debug("bus_isa=%d\n",bus_isa); -#endif } else { - printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8132_0); + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8132_0, sbdn3); } /* 8132-2 */ dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; +// printk_debug("bus_isa=%d\n",bus_isa); +#endif } else { - printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8132_0); + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8132_0, sbdn3+1); } /* HT chain 1 */ - if((pci1234[1] & 0x1) == 1) { - bus_8151_0 = (pci1234[1] >> 16) & 0xff; + if((sysconf.pci1234[1] & 0x1) == 1) { + bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; /* 8151 */ dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0)); @@ -127,6 +130,9 @@ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } + else { + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8151_0, sbdn5+1); + } } /*I/O APICs: APIC ID Version State Address*/ Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/irq_tables.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/irq_tables.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -9,6 +9,7 @@ #include #include #include +#include static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, @@ -36,10 +37,6 @@ extern unsigned char bus_8151_0; extern unsigned char bus_8151_1; -extern unsigned pci1234[]; - -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdn5; @@ -72,7 +69,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = bus_8111_0; - pirq->rtr_devfn = ((sbdn+1)<<3)|0; + pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; @@ -86,13 +83,13 @@ pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge // write_pirq_info(pirq_info, bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; - if(pci1234[1] & 0xf) { + if(sysconf.pci1234[1] & 0xf) { //agp bridge write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); } Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/mptable.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/mptable.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -7,6 +7,8 @@ #include #endif +#include + extern unsigned char bus_isa; extern unsigned char bus_8132_0; extern unsigned char bus_8132_1; @@ -19,9 +21,6 @@ extern unsigned apicid_8132_1; extern unsigned apicid_8132_2; -extern unsigned pci1234[]; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdn5; @@ -102,12 +101,12 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); - if(pci1234[1] & 0xf) { + if(sysconf.pci1234[1] & 0xf) { // Slot AGP smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x11); } Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -238,6 +238,35 @@ #define NonCoherent (1 << 2) #define ConnectionPending (1 << 4) +#include "raminit.h" +//struct definitions + +#if RAMINIT_SYSINFO==1 +struct link_pair_st { + device_t udev; + uint32_t upos; + uint32_t uoffs; + device_t dev; + uint32_t pos; + uint32_t offs; + +} __attribute__((packed)); + +struct sys_info { + uint8_t ctrl_present[NODE_NUMS]; + struct mem_controller ctrl[NODE_NUMS]; + + uint32_t nodes; + struct link_pair_st link_pair[16];// enough? only in_conherent + uint32_t link_pair_num; + uint32_t ht_c_num; + uint32_t sbdn; + uint32_t sblk; + uint32_t sbbusn; +} __attribute__((packed)); #endif + +#endif + #endif /* AMDK8_H */ Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h 2006-10-04 22:56:21 UTC (rev 2439) @@ -499,7 +499,7 @@ uint8_t ctrl_present[NODE_NUMS]; struct mem_info meminfo[NODE_NUMS]; struct mem_controller ctrl[NODE_NUMS]; - uint8_t mem_trained[NODE_NUMS]; + uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail uint32_t tom_k; uint32_t tom2_k; @@ -518,21 +518,23 @@ uint32_t sbbusn; } __attribute__((packed)); -#if MEM_TRAIN_SEQ == 1 +#ifdef __ROMCC__ +static void soft_reset(void); +#endif static void wait_all_core0_mem_trained(struct sys_info *sysinfo) { + int i; uint32_t mask = 0; + unsigned needs_reset = 0; + if(sysinfo->nodes == 1) return; // in case only one cpu installed for(i=1; inodes; i++) { - if (!sysinfo->ctrl_present[ i ]) - continue; - /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if(sysinfo->mem_trained[i]==0x00) continue; mask |= (1<mem_trained[i])) { + if((sysinfo->mem_trained[i])!=0x80) { mask &= ~(1<nodes; } -} + for(i=0; inodes; i++) { +#ifdef __ROMCC__ + print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); +#else + printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); #endif + switch(sysinfo->mem_trained[i]) { + case 0: //don't need train + case 1: //trained + break; + case 0x81: //recv1: fail + case 0x82: //Pos :fail + case 0x83: //recv2: fail + needs_reset = 1; + break; + } + } + if(needs_reset) { +#ifdef __ROMCC__ + print_debug("mem trained failed\r\n"); + soft_reset(); +#else + printk_debug("mem trained failed\n"); + hard_reset(); +#endif + } +} + #endif /* AMDK8_F_H */ Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -113,7 +113,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) { #if 1 -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%02x\r\n", strval, byteval); #else print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n"); @@ -285,14 +285,14 @@ freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if K8_REV_F_SUPPORT == 0 #if K8_HT_FREQ_1G_SUPPORT == 1 + #if K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) + #endif { return freq_cap; } #endif -#endif id = pci_read_config32(dev, 0); @@ -1503,7 +1503,7 @@ nodes = setup_smp8(); #endif -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%02x nodes initialized.\r\n", nodes); #else print_debug_hex8(nodes); @@ -1613,11 +1613,9 @@ */ print_spew("coherent_ht_finalize\r\n"); - #if K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif - for (node = 0; node < nodes; node++) { device_t dev; uint32_t val; Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/debug.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/debug.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/debug.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -6,7 +6,7 @@ static inline void print_debug_addr(const char *str, void *val) { #if CACHE_AS_RAM_ADDRESS_DEBUG == 1 - #if CONFIG_USE_INIT==1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("------Address debug: %s%x------\r\n", str, val); #else print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\r\n"); @@ -17,15 +17,15 @@ #if 1 static void print_debug_pci_dev(unsigned dev) { -#if CONFIG_USE_INIT - printk_debug("PCI: %02x:%02x.%02x", (dev>>16) & 0xff, (dev>>11) & 0x1f, (dev>>8) & 0x7); +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); #else print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); + print_debug_hex8((dev >> 20) & 0xff); print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); + print_debug_hex8((dev >> 15) & 0x1f); print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); + print_debug_hex8((dev >> 12) & 7); #endif } @@ -43,14 +43,14 @@ continue; } print_debug_pci_dev(dev); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug(" %04x:%04x\r\n", (id & 0xffff), (id>>16)); #else print_debug(" "); print_debug_hex32(id); print_debug("\r\n"); #endif - if(((dev>>8) & 0x07) == 0) { + if(((dev>>12) & 0x07) == 0) { uint8_t hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); if((hdr_type & 0x80) != 0x80) { @@ -68,7 +68,7 @@ for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("\r\n%02x:",i); #else print_debug("\r\n"); @@ -77,7 +77,7 @@ #endif } val = pci_read_config8(dev, i); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug(" %02x", val); #else print_debug_char(' '); @@ -87,6 +87,39 @@ print_debug("\r\n"); } +#if K8_REV_F_SUPPORT == 1 +static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); +static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) +{ + int i; + print_debug_pci_dev(dev); + print_debug(" -- index_reg="); print_debug_hex32(index_reg); + + for(i = 0; i < 0x40; i++) { + uint32_t val; + int j; +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("\r\n%02x:",i); +#else + print_debug("\r\n"); + print_debug_hex8(i); + print_debug_char(':'); +#endif + val = pci_read_config32_index_wait(dev, index_reg, i); + for(j=0;j<4;j++) { +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug(" %02x", val & 0xff); +#else + print_debug_char(' '); print_debug_hex8(val&0xff); +#endif + val >>= 8; + } + + } + print_debug("\r\n"); +} +#endif + static void dump_pci_devices(void) { device_t dev; @@ -102,7 +135,7 @@ } dump_pci_device(dev); - if(((dev>>8) & 0x07) == 0) { + if(((dev>>12) & 0x07) == 0) { uint8_t hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); if((hdr_type & 0x80) != 0x80) { @@ -127,7 +160,7 @@ } dump_pci_device(dev); - if(((dev>>8) & 0x07) == 0) { + if(((dev>>12) & 0x07) == 0) { uint8_t hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); if((hdr_type & 0x80) != 0x80) { @@ -137,6 +170,11 @@ } } +#ifndef DEBUG_SMBUS +#define DEBUG_SMBUS 0 +#endif + +#if DEBUG_SMBUS == 1 static void dump_spd_registers(const struct mem_controller *ctrl) { int i; @@ -146,7 +184,7 @@ device = ctrl->channel0[i]; if (device) { int j; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("dimm: %02x.0: %02x", i, device); #else print_debug("dimm: "); @@ -158,7 +196,7 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("\r\n%02x: ", j); #else print_debug("\r\n"); @@ -171,7 +209,7 @@ break; } byte = status & 0xff; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%02x ", byte); #else print_debug_hex8(byte); @@ -183,7 +221,7 @@ device = ctrl->channel1[i]; if (device) { int j; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("dimm: %02x.1: %02x", i, device); #else print_debug("dimm: "); @@ -195,7 +233,7 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("\r\n%02x: ", j); #else print_debug("\r\n"); @@ -208,7 +246,7 @@ break; } byte = status & 0xff; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%02x ", byte); #else print_debug_hex8(byte); @@ -226,7 +264,7 @@ for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("smbus: %02x", device); #else print_debug("smbus: "); @@ -240,7 +278,7 @@ break; } if ((j & 0xf) == 0) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("\r\n%02x: ",j); #else print_debug("\r\n"); @@ -249,7 +287,7 @@ #endif } byte = status & 0xff; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%02x ", byte); #else print_debug_hex8(byte); @@ -259,13 +297,14 @@ print_debug("\r\n"); } } +#endif static void dump_io_resources(unsigned port) { int i; udelay(2000); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%04x:\r\n", port); #else print_debug_hex16(port); @@ -274,7 +313,7 @@ for(i=0;i<256;i++) { uint8_t val; if ((i & 0x0f) == 0) { -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug("%02x:", i); #else print_debug_hex8(i); @@ -282,7 +321,7 @@ #endif } val = inb(port); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk_debug(" %02x",val); #else print_debug_char(' '); @@ -301,7 +340,7 @@ print_debug("dump_mem:"); for(i=start;i>3)& 0x1f, (devfn & 0x7), hdr_type, class); Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -3,6 +3,9 @@ 2004.12 yhlu add D0 support 2005.02 yhlu add E0 memory hole support */ +#if K8_REV_F_SUPPORT == 1 + #include "raminit_f.c" +#else #include #include @@ -35,7 +38,7 @@ unsigned where; unsigned long reg; #if 0 - #if CONFIG_USE_INIT + #if CONFIG_USE_PRINTK_IN_CAR prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]); #else print_debug_hex32(register_values[i]); @@ -66,7 +69,11 @@ return pci_read_config32(ctrl->f0, 0) == 0x11001022; } +#if RAMINIT_SYSINFO==1 +static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +#else static void sdram_set_registers(const struct mem_controller *ctrl) +#endif { static const unsigned int register_values[] = { @@ -546,7 +553,7 @@ unsigned where; unsigned long reg; #if 0 - #if CONFIG_USE_INIT + #if CONFIG_USE_PRINTK_IN_CAR prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]); #else print_spew_hex32(register_values[i]); @@ -2139,7 +2146,11 @@ return dimm_mask; } +#if RAMINIT_SYSINFO==1 +static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +#else static void sdram_set_spd_registers(const struct mem_controller *ctrl) +#endif { struct spd_set_memclk_result result; const struct mem_param *param; @@ -2288,7 +2299,11 @@ #endif #define TIMEOUT_LOOPS 300000 +#if RAMINIT_SYSINFO == 1 +static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) +#else static void sdram_enable(int controllers, const struct mem_controller *ctrl) +#endif { int i; @@ -2476,3 +2491,5 @@ } } #endif + +#endif Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -20,8 +20,8 @@ static inline void print_raminit(const char *strval, uint32_t val) { -#if CONFIG_USE_INIT - printk_debug("%s:%08x\r\n", strval, val); +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("%s%08x\r\n", strval, val); #else print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); #endif @@ -3005,8 +3005,22 @@ for(i = 0; i < controllers; i++) { sysinfo->mem_trained[i] = 0; + + if (!sysinfo->ctrl_present[ i ]) + continue; + + /* Skip everything if I don't have any memory on this controller */ + if(sysinfo->meminfo[i].dimm_mask==0x00) + continue; + + sysinfo->mem_trained[i] = 0x80; // mem need to be trained } +#if 0 + dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +#endif + #if MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 dqs_timing(controllers, ctrl, tsc0, sysinfo); @@ -3021,13 +3035,11 @@ #endif for(i = 0; i < controllers; i++) { - if (!sysinfo->ctrl_present[ i ]) - continue; - /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if(sysinfo->mem_trained[i]!=0x80) + continue; - dqs_timing(i, ctrl, sysinfo, 1); + dqs_timing(i, &ctrl[i], sysinfo, 1); #if MEM_TRAIN_SEQ == 1 break; // only train the first node with ram @@ -3040,7 +3052,15 @@ #endif +#if MEM_TRAIN_SEQ != 1 + wait_all_core0_mem_trained(sysinfo); +#endif +#if 0 + dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +#endif + } static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) { Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -8,7 +8,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_INIT == 1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%x\r\n", str, val); #else print_debug(str); print_debug_hex32(val); print_debug("\r\n"); @@ -21,7 +21,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_INIT == 1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); #else print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n"); @@ -34,7 +34,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - #if CONFIG_USE_INIT == 1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); #else print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); @@ -45,7 +45,7 @@ static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - #if CONFIG_USE_INIT == 1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); #else print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n"); @@ -501,7 +501,7 @@ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1 #endif -static void TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) +static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { const static uint32_t TestPattern0[] = { @@ -876,16 +876,14 @@ #if MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ - #if CONFIG_USE_INIT == 1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay); #else print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay); #endif #endif - if(CTLRMaxDelay==0xae) { - soft_reset(); // try more or downgrade? - } + return (CTLRMaxDelay==0xae)?1:0; } @@ -1544,24 +1542,28 @@ } } -static void train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) +static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); - TrainRcvrEn(ctrl, Pass, sysinfo); + if(TrainRcvrEn(ctrl, Pass, sysinfo)) { + return 1; + } print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); + return 0; } -static void train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) +static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n"); - soft_reset(); + return 1; } else { SetEccDQSRdWrPos(ctrl, sysinfo); } print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); + return 0; } @@ -1717,7 +1719,7 @@ } sizek = 1 << align; #if MEM_TRAIN_SEQ != 1 - #if CONFIG_USE_INIT == 1 + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": @@ -1880,7 +1882,7 @@ print_debug("DQS Training:RcvrEn:Pass1: "); print_debug_hex8(i); - train_DqsRcvrEn(ctrl+i, 1, sysinfo); + if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; print_debug(" done\r\n"); } @@ -1899,7 +1901,7 @@ print_debug("DQS Training:DQSPos: "); print_debug_hex8(i); - train_DqsPos(ctrl+i, sysinfo); + if(train_DqsPos(ctrl+i, sysinfo)) goto out; print_debug(" done\r\n"); } @@ -1913,11 +1915,12 @@ print_debug("DQS Training:RcvrEn:Pass2: "); print_debug_hex8(i); - train_DqsRcvrEn(ctrl+i, 2, sysinfo); + if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; print_debug(" done\r\n"); sysinfo->mem_trained[i]=1; } +out: tsc[4] = rdtsc(); clear_mtrr_dqs(sysinfo->tom2_k); @@ -1942,14 +1945,14 @@ tsc_t tsc[4]; + if(sysinfo->mem_trained[i] != 0x80) return; #if MEM_TRAIN_SEQ == 1 - if(sysinfo->mem_trained[i]) return; //need to enable mtrr, so dqs training could access the test address setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif - fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); + fill_mem_cs_sysinfo(i, ctrl, sysinfo); if(v) { tsc[0] = rdtsc(); @@ -1957,7 +1960,10 @@ print_debug("set DQS timing:RcvrEn:Pass1: "); print_debug_hex8(i); } - train_DqsRcvrEn(ctrl+i, 1, sysinfo); + if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { + sysinfo->mem_trained[i]=0x81; // + goto out; + } if(v) { print_debug(" done\r\n"); @@ -1966,7 +1972,10 @@ print_debug_hex8(i); } - train_DqsPos(ctrl+i, sysinfo); + if(train_DqsPos(ctrl, sysinfo)) { + sysinfo->mem_trained[i]=0x82; // + goto out; + } if(v) { print_debug(" done\r\n"); @@ -1975,7 +1984,10 @@ print_debug("set DQS timing:RcvrEn:Pass2: "); print_debug_hex8(i); } - train_DqsRcvrEn(ctrl+i, 2, sysinfo); + if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ + sysinfo->mem_trained[i]=0x83; // + goto out; + } if(v) { print_debug(" done\r\n"); @@ -1983,6 +1995,7 @@ tsc[3] = rdtsc(); } +out: #if MEM_TRAIN_SEQ == 1 clear_mtrr_dqs(sysinfo->tom2_k); #endif @@ -1992,16 +2005,18 @@ print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); } } + + if(sysinfo->mem_trained[i] == 0x80) { + sysinfo->mem_trained[i]=1; + } - sysinfo->mem_trained[i]=1; - } #endif #if MEM_TRAIN_SEQ == 1 static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { - dqs_timing(nodeid, sysinfo->ctrl,sysinfo, 0); // keep the output tidy + dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy // memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); // memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; @@ -2014,23 +2029,23 @@ struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); wait_till_sysinfo_in_ram(); // use pci to get it - if(sysinfox->mem_trained[nodeid] == 0) { - if (sysinfox->ctrl_present[ nodeid ] && sysinfox->meminfo[nodeid].dimm_mask) { - sysinfo->tom_k = sysinfox->tom_k; - sysinfo->tom2_k = sysinfox->tom2_k; - sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128; - set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's - #if CONFIG_AP_CODE_IN_CAR == 0 - print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n"); - train_ram(nodeid, sysinfo, sysinfox); - #else - /* Can copy dqs_timing to ap cache and run from cache? - * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ? - */ - copy_and_run_ap_code_in_car(retcall); - // will go back by jump - #endif - } + if(sysinfox->mem_trained[nodeid] == 0x80) { + sysinfo->tom_k = sysinfox->tom_k; + sysinfo->tom2_k = sysinfox->tom2_k; + sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128; + sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; + memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); + set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's + #if CONFIG_AP_CODE_IN_CAR == 0 + print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n"); + train_ram(nodeid, sysinfo, sysinfox); + #else + /* Can copy dqs_timing to ap cache and run from cache? + * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ? + */ + copy_and_run_ap_code_in_car(retcall); + // will go back by jump + #endif } } #endif Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -12,7 +12,7 @@ unsigned where; unsigned long reg; #if 0 - #if CONFIG_USE_INIT + #if CONFIG_USE_PRINTK_IN_CAR prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]); #else print_debug_hex32(register_values[i] + offset_pci_dev); @@ -56,7 +56,7 @@ #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - #if CONFIG_USE_INIT + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", i>>2, register_values[i], register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), @@ -151,7 +151,7 @@ #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - #if CONFIG_USE_INIT + #if CONFIG_USE_PRINTK_IN_CAR printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n", i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); #else Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_reset.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_reset.c 2006-10-04 21:05:23 UTC (rev 2438) +++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_reset.c 2006-10-04 22:56:21 UTC (rev 2439) @@ -6,16 +6,16 @@ #include #define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x7) << 8)) + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) typedef unsigned device_t; static void pci_write_config32(device_t dev, unsigned where, unsigned value) { unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); } @@ -23,7 +23,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where) { unsigned addr; - addr = dev | where; + addr = (dev>>4) | where; outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); } From svn at openbios.org Thu Oct 5 00:57:27 2006 From: svn at openbios.org (svn at openbios.org) Date: Thu, 05 Oct 2006 00:57:27 +0200 Subject: [LinuxBIOS] r2440 - in trunk/LinuxBIOSv2/targets: amd/serengeti_leopard emulation/qemu-i386 Message-ID: Author: yhlu Date: 2006-10-05 00:57:26 +0200 (Thu, 05 Oct 2006) New Revision: 2440 Added: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config-abuild.lb Modified: trunk/LinuxBIOSv2/targets/amd/serengeti_leopard/Config.lb Log: qemu abuild fix Modified: trunk/LinuxBIOSv2/targets/amd/serengeti_leopard/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/amd/serengeti_leopard/Config.lb 2006-10-04 22:56:21 UTC (rev 2439) +++ trunk/LinuxBIOSv2/targets/amd/serengeti_leopard/Config.lb 2006-10-04 22:57:26 UTC (rev 2440) @@ -8,11 +8,12 @@ # serengeti_leopard romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 +# option ROM_SIZE = 458752 + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 # option ROM_IMAGE_SIZE=0x13800 # option ROM_IMAGE_SIZE=0x17800 @@ -38,6 +39,7 @@ end romimage "fallback" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 # option ROM_IMAGE_SIZE=0x13800 # option ROM_IMAGE_SIZE=0x17800 @@ -52,8 +54,9 @@ # payload ../../../payloads/tg3--filo_hda2.zelf # payload ../../../payloads/tg3.zelf # payload ../../../payloads/tg3_vga.zelf + payload ../../../../payloads/memtest # payload ../../../../payloads/tg3--filo_hda2_vga.zelf - payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf +# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf # payload ../../../payloads/tg3_com2.zelf # payload ../../../payloads/e1000--filo.zelf # payload ../../../payloads/tg3--e1000--filo.zelf @@ -62,4 +65,13 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" Added: trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config-abuild.lb =================================================================== --- trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config-abuild.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/emulation/qemu-i386/Config-abuild.lb 2006-10-04 22:57:26 UTC (rev 2440) @@ -0,0 +1,20 @@ +# This will make a target directory of ./emulation_qemu-i386 + +target emulation_qemu-i386 +mainboard emulation/qemu-i386 + +option ROM_SIZE=256*1024 + +option CC="gcc -m32" + +option HAVE_PIRQ_TABLE=1 +option IRQ_SLOT_COUNT=6 + +romimage "image" + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION="-OpenBIOS" + payload PAYLOAD +end + +buildrom ./qemu-bios.rom ROM_SIZE "image" + From svn at openbios.org Thu Oct 5 01:09:10 2006 From: svn at openbios.org (svn at openbios.org) Date: Thu, 05 Oct 2006 01:09:10 +0200 Subject: [LinuxBIOS] r2441 - in trunk/LinuxBIOSv2/src/mainboard/amd: serengeti_cheetah/dx serengeti_leopard/dx Message-ID: Author: yhlu Date: 2006-10-05 01:09:09 +0200 (Thu, 05 Oct 2006) New Revision: 2441 Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131_2.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8132_2.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3_hc.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4_hc.asl trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci0_hc.asl Log: add missed asl for ht chain Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131_2.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131_2.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8131_2.asl 2006-10-04 23:09:09 UTC (rev 2441) @@ -0,0 +1,114 @@ +/* + * Copyright 2005 AMD + */ + + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x04) + { + // Slot A - PIRQ BCDA + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, + + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { + // Slot A - PIRQ ABCD + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8132_2.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8132_2.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/amd8132_2.asl 2006-10-04 23:09:09 UTC (rev 2441) @@ -0,0 +1,114 @@ +/* + * Copyright 2005 AMD + */ + + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x04) + { + // Slot A - PIRQ BCDA + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, + + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { + // Slot A - PIRQ ABCD + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3.asl 2006-10-04 23:09:09 UTC (rev 2441) @@ -0,0 +1,68 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + Include ("pci3_hc.asl") + } + } + +} + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3_hc.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3_hc.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci3_hc.asl 2006-10-04 23:09:09 UTC (rev 2441) @@ -0,0 +1 @@ + Include ("amd8151.asl") Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4.asl 2006-10-04 23:09:09 UTC (rev 2441) @@ -0,0 +1,68 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + Include ("pci4_hc.asl") + } + } + +} + Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4_hc.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4_hc.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci4_hc.asl 2006-10-04 23:09:09 UTC (rev 2441) @@ -0,0 +1 @@ + Include ("amd8131_2.asl") Added: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci0_hc.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci0_hc.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci0_hc.asl 2006-10-04 23:09:09 UTC (rev 2441) @@ -0,0 +1,2 @@ + Include ("amd8111.asl") //real SB at first + Include ("amd8131.asl") From stepan at coresystems.de Thu Oct 5 01:11:44 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Thu, 5 Oct 2006 01:11:44 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D64D@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D64D@ssvlexmb2.amd.com> Message-ID: <20061004231143.GA11022@coresystems.de> * Lu, Yinghai [061004 22:50]: > Can you check abuild with emulation/qemu-i386? > It will create fallback and normal, and normal will use reset16. > > I assume you need to let abuild to create one config that only include > fallback section. So you broke using a normal image? -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From yinghai.lu at amd.com Thu Oct 5 01:14:35 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Wed, 4 Oct 2006 16:14:35 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D64F@ssvlexmb2.amd.com> No. Your MB Config.lb is using reset16.*. So it only can be used for fallback. I removed "cut rom code into last 64k" in ldscript.lb. Also I added Config-abuild.lb for qemu-i386. and abuild is happy again. YH -----Original Message----- From: Stefan Reinauer [mailto:stepan at coresystems.de] Sent: Wednesday, October 04, 2006 4:12 PM To: Lu, Yinghai Cc: linuxbios at linuxbios.org Subject: Re: [LinuxBIOS] FW: rev F support code * Lu, Yinghai [061004 22:50]: > Can you check abuild with emulation/qemu-i386? > It will create fallback and normal, and normal will use reset16. > > I assume you need to let abuild to create one config that only include > fallback section. So you broke using a normal image? -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info at coresystems.de * http://www.coresystems.de/ From info at coresystems.de Thu Oct 5 01:24:31 2006 From: info at coresystems.de (LinuxBIOS information) Date: Thu, 05 Oct 2006 01:24:31 +0200 Subject: [LinuxBIOS] r2438 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2438 to the LinuxBIOS source repository and caused the following changes: Change Log: failover_failover apc lds Build Log: Compilation of amd:serengeti_cheetah has been fixed Compilation of emulation:qemu-i386 is still broken If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From stepan at coresystems.de Thu Oct 5 01:25:45 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Thu, 5 Oct 2006 01:25:45 +0200 Subject: [LinuxBIOS] r2439 - in trunk/LinuxBIOSv2/src: arch/i386/include/arch arch/i386/lib config console cpu/amd/car cpu/amd/model_fxx devices drivers/i2c/adm1027 include/cpu/amd lib mainboard/Iwill/DK8HTX mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah/dx mainboard/amd/serengeti_leopard mainboard/amd/serengeti_leopard/dx northbridge/amd/amdk8 southbridge/nvidia/ck804 In-Reply-To: References: Message-ID: <20061004232545.GA26955@coresystems.de> * svn at openbios.org [061005 00:56]: > Author: yhlu > Date: 2006-10-05 00:56:21 +0200 (Thu, 05 Oct 2006) > New Revision: 2439 > > Added: > trunk/LinuxBIOSv2/src/arch/i386/include/arch/mmio_conf.h > trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_mmconf.c > Removed: > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/a > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx_bus0/ > Modified: > trunk/LinuxBIOSv2/src/arch/i386/include/arch/pci_ops.h > trunk/LinuxBIOSv2/src/arch/i386/include/arch/pciconf.h > trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h > trunk/LinuxBIOSv2/src/arch/i386/lib/Config.lb > trunk/LinuxBIOSv2/src/arch/i386/lib/console.c > trunk/LinuxBIOSv2/src/arch/i386/lib/pci_ops_conf1.c > trunk/LinuxBIOSv2/src/config/Options.lb > trunk/LinuxBIOSv2/src/console/Config.lb > trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c > trunk/LinuxBIOSv2/src/cpu/amd/car/disable_cache_as_ram.c > trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c > trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/fidvid.c > trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c > trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/model_fxx_init.c > trunk/LinuxBIOSv2/src/devices/device_util.c > trunk/LinuxBIOSv2/src/devices/pci_device.c > trunk/LinuxBIOSv2/src/drivers/i2c/adm1027/adm1027.c > trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h > trunk/LinuxBIOSv2/src/lib/Config.lb > trunk/LinuxBIOSv2/src/mainboard/Iwill/DK8HTX/auto.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Config.lb > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/irq_tables.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/mptable.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/resourcemap.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/acpi_tables.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cmos.layout > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111.asl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8111_pic.asl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8131.asl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/amd8151.asl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/dsdt_lb.dsl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/dx/pci2.asl > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/get_bus_conf.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/irq_tables.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/mptable.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8_f.h > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/debug.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/get_sblk_pci1234.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/incoherent_ht.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f_dqs.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/setup_resource_map.c > trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_reset.c > Log: > CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in > serengeti_cheeatah Which part of this changelog describes the MMCONF_SUPPORT and the PCI_IO_CFG_EXT parts of the patch? ... And the LinuxBIOS in 64bit stuff? And the ACPI changes? And why all the changes in leopard? They are not mentioned in the changelog at all... I think about backing this commit out, it must be an accidental slip of the whole tree instead of 2 changes you describe? > +define PCI_BUS_SEGN_BITS > + default 0 > + export always > + comment "It could be 0, 1, 2, 3 and 4 only" > +end Please describe what it does, in addition to the values it can take. The descriptions in this file are completely useless, we could as well drop them. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From c-d.hailfinger.devel.2006 at gmx.net Thu Oct 5 01:23:52 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 05 Oct 2006 01:23:52 +0200 Subject: [LinuxBIOS] nVidia MCP55 In-Reply-To: References: Message-ID: <45244288.9050308@gmx.net> Hi, Ed Swierk wrote: > I'm about to start getting LinuxBIOS to work on an nVidia MCP55-based > mainboard, and wonder whether other folks have already began work on > this chipset. Yinghai Lu has some code for MCP55, but I don't know whether he has already finished writing a replacement for NVMM. A month ago, he wrote: "So Current Only IDE and USB are working but the sata/nic/pcie don't work" > I haven't managed to get hold of any nVidia specs yet. Any clues how > to enable the serial port on the MCP55? Will it require some SMBus > diddling? Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at openbios.org Thu Oct 5 01:57:50 2006 From: svn at openbios.org (svn at openbios.org) Date: Thu, 05 Oct 2006 01:57:50 +0200 Subject: [LinuxBIOS] r2442 - in trunk/LinuxBIOSv2: src/mainboard/broadcom/blast src/mainboard/tyan/s2881 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 targets/tyan/s2895 Message-ID: Author: yhlu Date: 2006-10-05 01:57:49 +0200 (Thu, 05 Oct 2006) New Revision: 2442 Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/mptable.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/mptable.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/mptable.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Config.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/mptable.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/resourcemap.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Config.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/mptable.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/resourcemap.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Config.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/get_bus_conf.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/mptable.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/resourcemap.c trunk/LinuxBIOSv2/targets/tyan/s2895/Config.lb Log: get_bus_cong using sysconf instead Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -4,7 +4,7 @@ //#define K8_SCAN_PCI_BUS 1 -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/get_bus_conf.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/get_bus_conf.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -7,10 +7,22 @@ #include #endif -unsigned sblk; -unsigned pci1234[] = +#include + + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +//busnum is default +unsigned char bus_isa = 10; +unsigned char bus_bcm5780[7]; +unsigned char bus_bcm5785_0 = 1; +unsigned char bus_bcm5785_1 = 8; +unsigned char bus_bcm5785_1_1 = 9; +unsigned apicid_bcm5785[3]; + + +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -20,9 +32,7 @@ // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -33,16 +43,6 @@ // 0x20202020, // 0x20202020, }; - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default -unsigned char bus_isa = 10; -unsigned char bus_bcm5780[7]; -unsigned char bus_bcm5785_0 = 1; -unsigned char bus_bcm5785_1 = 8; -unsigned char bus_bcm5785_1_1 = 9; -unsigned apicid_bcm5785[3]; - unsigned sbdn2; extern void get_sblk_pci1234(void); @@ -61,18 +61,22 @@ get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 8) & 0xff; - sbdn2 = hcdn[0] & 0xff; // bcm5780 + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 - bus_bcm5785_0 = (pci1234[0] >> 16) & 0xff; + bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_bcm5780[0] = bus_bcm5785_0; /* bcm5785 */ - dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sbdn,0)); + dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d,0)); Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/irq_tables.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/irq_tables.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -10,9 +10,7 @@ #include #include -extern unsigned pci1234[]; -extern unsigned sbdn; -extern unsigned hcdn[]; +#include static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, @@ -71,7 +69,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = bus_bcm5785_0; - pirq->rtr_devfn = (sbdn<<3)|0; + pirq->rtr_devfn = (sysconf.sbdn<<3)|0; pirq->exclusive_irqs = 0; @@ -87,7 +85,7 @@ pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_bcm5785_0, (sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; pirq->size = 32 + 16 * slot_num; Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/mptable.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/mptable.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -8,9 +8,7 @@ #include #endif -extern unsigned pci1234[]; -extern unsigned sbdn; -extern unsigned hcdn[]; +#include extern unsigned char bus_isa; extern unsigned char bus_bcm5780[7]; @@ -95,7 +93,7 @@ //IDE outb(0x02, 0xc00); outb(0x0e, 0xc01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); @@ -104,7 +102,7 @@ //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); for(i=0;i<3;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // } Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Options.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -54,6 +54,11 @@ uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE @@ -121,6 +126,18 @@ #CHIP_NAME ? default CONFIG_CHIP_NAME=1 +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0a + +##real SB Unit ID, default is 0x20, mean dont touch it at last +default HT_CHAIN_END_UNITID_BASE=0x06 + +#make the SB HT chain on bus 0, default is not (0) +default SB_HT_CHAIN_ON_BUS0=0 + +##only offset for SB chain?, default is yes(1) +#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -20,7 +20,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include +#include "northbridge/amd/amdk8/cpu_rev.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -1,7 +1,7 @@ #define ASSEMBLY 1 #define __ROMCC__ -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -19,7 +19,19 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + #include + #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -113,9 +125,11 @@ enumerate_ht_chain(); + /* Setup the ck804 */ amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -127,12 +141,14 @@ goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ ); fallback_image: +// post_code(0x25); ; } #endif @@ -170,6 +186,7 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } +// post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); @@ -179,6 +196,10 @@ report_bist_failure(bist); setup_s2881_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif needs_reset = setup_coherent_ht_domain(); @@ -197,6 +218,12 @@ } enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif +#if 0 + dump_smbus_registers(); +#endif allow_all_aps_stop(bsp_apicid); @@ -207,6 +234,9 @@ memreset_setup(); sdram_initialize(nodes, ctrl); +#if 0 + dump_pci_devices(); +#endif post_cache_as_ram(); } Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/get_bus_conf.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/get_bus_conf.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -7,7 +7,9 @@ #include #endif +#include + // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default unsigned char bus_isa = 5 ; @@ -20,8 +22,7 @@ unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned sblk; -unsigned pci1234[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -33,9 +34,7 @@ // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -58,23 +57,28 @@ unsigned apicid_base; device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 8) & 0xff; - sbdn3 = hcdn[0] & 0xff; + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + sbdn3 = sysconf.hcdn[0] & 0xff; - bus_8131_0 = (pci1234[0] >> 16) & 0xff; + bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_8111_0 = bus_8131_0; /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0)); + dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); #if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE @@ -91,11 +95,6 @@ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; -// printk_debug("bus_isa=%d\n",bus_isa); -#endif } else { printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); @@ -105,6 +104,11 @@ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; +// printk_debug("bus_isa=%d\n",bus_isa); +#endif } else { printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/irq_tables.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/irq_tables.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -10,6 +10,8 @@ #include #include +#include + static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) @@ -34,8 +36,6 @@ extern unsigned char bus_8111_0; extern unsigned char bus_8111_1; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern void get_bus_conf(void); @@ -67,7 +67,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = bus_8111_0; - pirq->rtr_devfn = ((sbdn+1)<<3)|0; + pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; @@ -81,7 +81,7 @@ pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge // write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/mptable.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/mptable.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -4,6 +4,8 @@ #include #include +#include + extern unsigned char bus_isa; extern unsigned char bus_8131_0; extern unsigned char bus_8131_1; @@ -14,14 +16,10 @@ extern unsigned apicid_8131_1; extern unsigned apicid_8131_2; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern void get_bus_conf(void); - - void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -100,7 +98,7 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //8111 LPC ???? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13); //On Board AMD USB ??? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Options.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -63,6 +63,13 @@ uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_LB_MEM_TOPK + ### ### Build options ### @@ -125,6 +132,18 @@ #CHIP_NAME ? default CONFIG_CHIP_NAME=1 +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0a + +##real SB Unit ID, default is 0x20, mean dont touch it at last +default HT_CHAIN_END_UNITID_BASE=0x06 + +#make the SB HT chain on bus 0, default is not (0) +default SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -19,7 +19,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include +#include "northbridge/amd/amdk8/cpu_rev.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -13,7 +13,19 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + #include + #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -68,7 +80,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -113,9 +125,11 @@ enumerate_ht_chain(); + /* Setup the ck804 */ amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -127,12 +141,14 @@ goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ ); fallback_image: +// post_code(0x25); ; } #endif @@ -170,15 +186,22 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } +// post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s2885_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif needs_reset = setup_coherent_ht_domain(); @@ -188,7 +211,7 @@ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + needs_reset |= ht_setup_chains_x(); if (needs_reset) { @@ -208,6 +231,10 @@ memreset_setup(); sdram_initialize(nodes, ctrl); +#if 0 + dump_pci_devices(); +#endif + post_cache_as_ram(); } Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/get_bus_conf.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/get_bus_conf.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -7,6 +7,7 @@ #include #endif +#include // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -22,8 +23,7 @@ unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned sblk; -unsigned pci1234[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -35,9 +35,7 @@ // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -61,24 +59,29 @@ unsigned apicid_base; device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 8) & 0xff; - sbdn3 = hcdn[0] & 0xff; - sbdn5 = hcdn[1] & 0xff; + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + sbdn3 = sysconf.hcdn[0] & 0xff; + sbdn5 = sysconf.hcdn[1] & 0xff; - bus_8131_0 = (pci1234[0] >> 16) & 0xff; + bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; bus_8111_0 = bus_8131_0; /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0)); + dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); #if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE @@ -95,11 +98,6 @@ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; -// printk_debug("bus_isa=%d\n",bus_isa); -#endif } else { printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); @@ -109,6 +107,12 @@ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; +// printk_debug("bus_isa=%d\n",bus_isa); +#endif + } else { printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); @@ -116,7 +120,7 @@ /* HT chain 1 */ // it is on node0, so it must be there - bus_8151_0 = (pci1234[1] >> 16) & 0xff; + bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff; /* 8151 */ dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0)); Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/irq_tables.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/irq_tables.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -10,6 +10,8 @@ #include #include +#include + static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) @@ -36,8 +38,6 @@ extern unsigned char bus_8151_0; extern unsigned char bus_8151_1; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdn5; @@ -70,7 +70,7 @@ pirq->version = PIRQ_VERSION; pirq->rtr_bus = bus_8111_0; - pirq->rtr_devfn = ((sbdn+1)<<3)|0; + pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; @@ -84,7 +84,7 @@ pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge // write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/mptable.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/mptable.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -4,6 +4,8 @@ #include #include +#include + extern unsigned char bus_isa; extern unsigned char bus_8131_0; extern unsigned char bus_8131_1; @@ -16,8 +18,6 @@ extern unsigned apicid_8131_1; extern unsigned apicid_8131_2; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdn5; @@ -99,9 +99,9 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13); //Onboard AMD AC97 Audio - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Config.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Config.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -314,8 +314,8 @@ # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 7.0 on end - # register "rom_address" = "0xfff80000" #for 512K - register "rom_address" = "0xfff00000" #for 1M + register "rom_address" = "0xfff80000" #for 512K + # register "rom_address" = "0xfff00000" #for 1M end end device pci a.0 off end # NIC Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -54,7 +54,6 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -74,12 +73,13 @@ uses CONFIG_LB_MEM_TOPK + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -#default ROM_SIZE=524288 +default ROM_SIZE=524288 #1M bytes -default ROM_SIZE=1048576 +#default ROM_SIZE=1048576 ## @@ -139,9 +139,6 @@ #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000 -#Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 - ##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0 @@ -152,9 +149,8 @@ default SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -229,8 +225,8 @@ ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CROSS_COMPILE)gcc-3.3.6 -m32" +default HOSTCC="gcc-3.3.6" ## ## Disable the gdb stub by default Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -12,7 +12,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include +#include "northbridge/amd/amdk8/cpu_rev.c" #define K8_HT_FREQ_1G_SUPPORT 0 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -2,7 +2,7 @@ #define __ROMCC__ //used by raminit -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -21,7 +21,19 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + #include + #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -42,6 +54,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void memreset_setup(void) { } @@ -92,15 +105,21 @@ uint32_t dword; uint8_t byte; - byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + /* subject decoding*/ + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + /* LPC Positive Decode 0 */ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + /* Serial 0, Serial 1 */ dword |= (1<<0) | (1<<1); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); #if 1 + /* s2891 has onboard LPC port 80 */ + /*Hope I can enable port 80 here + It will decode port 80 to LPC, If you are using PCI post code you can not do this */ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); @@ -133,6 +152,7 @@ ck804_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -144,12 +164,14 @@ goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist) , "b" (cpu_init_detectedx)/* inputs */ ); fallback_image: +// post_code(0x25); ; } #endif @@ -187,6 +209,8 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } +// post_code(0x32); + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -195,6 +219,10 @@ report_bist_failure(bist); setup_s2891_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif needs_reset = setup_coherent_ht_domain(); @@ -211,7 +239,7 @@ if (needs_reset) { print_info("ht reset -\r\n"); - soft_reset(); +// soft_reset(); } allow_all_aps_stop(bsp_apicid); @@ -221,9 +249,23 @@ fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif +#if 0 + dump_smbus_registers(); +#endif memreset_setup(); sdram_initialize(nodes, ctrl); +#if 0 + print_pci_devices(); +#endif + +#if 0 + dump_pci_devices(); +#endif + post_cache_as_ram(); } Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/get_bus_conf.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/get_bus_conf.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -7,6 +7,7 @@ #include #endif +#include // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -24,9 +25,9 @@ unsigned apicid_ck804; unsigned apicid_8131_1; unsigned apicid_8131_2; + -unsigned sblk; -unsigned pci1234[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000000, @@ -38,9 +39,7 @@ // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -65,29 +64,29 @@ unsigned apicid_base; device_t dev; + unsigned sbdn; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 16) & 0xff; + bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; - if(pci1234[2] & 1) { - bus_coproc_0 = (pci1234[2] >> 16) & 0xff; - coprocdn = (hcdn[2] & 0xff); - } - - /* CK804 */ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); if (dev) { @@ -153,16 +152,14 @@ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); if (dev) { bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_0++; - bus_isa = bus_8131_0; // incase only one installed + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - } - bus_8131_0 = (pci1234[1] >> 16) & 0xff; + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); @@ -191,8 +188,12 @@ bus_isa = bus_8131_1+2; } + if(sysconf.pci1234[2] & 1) { + bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff; + coprocdn = (sysconf.hcdn[2] & 0xff); + } + - /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/irq_tables.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/irq_tables.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -10,6 +10,8 @@ #include #include +#include + static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) @@ -40,10 +42,7 @@ extern unsigned char bus_8131_2;//9 extern unsigned char bus_coproc_0; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; -extern unsigned pci1234[]; extern unsigned coprocdn; extern void get_bus_conf(void); @@ -58,8 +57,10 @@ uint8_t sum=0; int i; + unsigned sbdn; - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; /* Align the table to be 16 byte aligned. */ addr += 15; @@ -94,12 +95,11 @@ //pcix bridge write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - //co processor - if(pci1234[2] & 1) { - write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - } + if(sysconf.pci1234[2] & 1) { + write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + } #if 0 //smbus Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/mptable.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/mptable.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -4,6 +4,8 @@ #include #include +#include + extern unsigned char bus_isa; extern unsigned char bus_ck804_0; //1 extern unsigned char bus_ck804_1; //2 @@ -18,8 +20,6 @@ extern unsigned apicid_8131_1; extern unsigned apicid_8131_2; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern void get_bus_conf(void); @@ -30,6 +30,7 @@ static const char oem[8] = "TYAN "; static const char productid[12] = "S2891 "; struct mp_config_table *mc; + unsigned sbdn; unsigned char bus_num; int i; @@ -54,6 +55,7 @@ smp_write_processors(mc); get_bus_conf(); + sbdn = sysconf.sbdn; /*Bus: Bus ID Type*/ /* define bus and isa numbers */ @@ -75,6 +77,7 @@ smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } + /* Initialize interrupt mapping*/ dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); @@ -83,7 +86,6 @@ pci_write_config32(dev, 0x80, dword); dword = 0x0000007d; - pci_write_config32(dev, 0x84, dword); } Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/resourcemap.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/resourcemap.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/resourcemap.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -258,8 +258,8 @@ * This field defines the highest bus number in configuration region i */ #if 1 -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, #endif Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Config.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Config.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -313,8 +313,7 @@ # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - # register "rom_address" = "0xfff80000" #for 512K - register "rom_address" = "0xfff00000" #for 1M + register "rom_address" = "0xfff80000" end chip drivers/pci/onboard device pci 8.0 on end Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -54,7 +54,6 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -66,12 +65,14 @@ uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_LB_MEM_TOPK + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -#default ROM_SIZE=524288 +default ROM_SIZE=524288 #1M bytes -default ROM_SIZE=1048576 +#default ROM_SIZE=1048576 ## @@ -128,12 +129,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -#1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 - -#Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 - ##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0 @@ -146,6 +141,9 @@ ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#1G memory hole +default HW_MEM_HOLE_SIZEK=0x100000 + #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -161,6 +159,7 @@ default DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 + ## ## Build code to setup a generic IOAPIC ## Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -12,7 +12,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include +#include "northbridge/amd/amdk8/cpu_rev.c" #define K8_HT_FREQ_1G_SUPPORT 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -13,6 +13,17 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" @@ -54,7 +65,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -98,7 +109,7 @@ uint32_t dword; uint8_t byte; - byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); @@ -106,7 +117,6 @@ dword |= (1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - } void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -132,6 +142,7 @@ ck804_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -143,12 +154,14 @@ goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ ); fallback_image: +// post_code(0x25); ; } #endif @@ -167,46 +180,42 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, + + static const uint16_t spd_addr [] = { + (0xa<<3)|0, (0xa<<3)|2, 0, 0, + (0xa<<3)|1, (0xa<<3)|3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, + (0xa<<3)|4, (0xa<<3)|6, 0, 0, + (0xa<<3)|5, (0xa<<3)|7, 0, 0, #endif - }; + }; - unsigned bsp_apicid = 0; int needs_reset; + unsigned bsp_apicid = 0; + struct mem_controller ctrl[8]; + unsigned nodes; + if (bist == 0) { init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + setup_s2892_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif - needs_reset = setup_coherent_ht_domain(); + needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 @@ -219,15 +228,35 @@ needs_reset |= ck804_early_setup_x(); - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } - enable_smbus(); + allow_all_aps_stop(bsp_apicid); - memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); - post_cache_as_ram(); + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif +#if 0 + dump_smbus_registers(); +#endif + + memreset_setup(); + sdram_initialize(nodes, ctrl); + +#if 0 + print_pci_devices(); +#endif + +#if 0 + dump_pci_devices(); +#endif + + post_cache_as_ram(); } Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/get_bus_conf.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/get_bus_conf.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -7,6 +7,7 @@ #include #endif +#include // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default @@ -24,8 +25,7 @@ unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned sblk; -unsigned pci1234[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -37,9 +37,7 @@ // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -61,23 +59,29 @@ { unsigned apicid_base; + unsigned sbdn; device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 16) & 0xff; + bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; /* CK804 */ @@ -145,16 +149,15 @@ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); if (dev) { bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_8131_0++; - bus_isa = bus_8131_0; // incase only one installed + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; } else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - } - bus_8131_0 = (pci1234[1] >> 16) & 0xff; + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; + /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/irq_tables.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/irq_tables.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -10,6 +10,8 @@ #include #include +#include + static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) @@ -39,8 +41,6 @@ extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_2;//9 -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern void get_bus_conf(void); @@ -52,11 +52,13 @@ struct irq_info *pirq_info; unsigned slot_num; uint8_t *v; + unsigned sbdn; uint8_t sum=0; int i; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; /* Align the table to be 16 byte aligned. */ addr += 15; Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/mptable.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/mptable.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -4,6 +4,8 @@ #include #include +#include + extern unsigned char bus_isa; extern unsigned char bus_ck804_0; //1 extern unsigned char bus_ck804_1; //2 @@ -18,8 +20,6 @@ extern unsigned apicid_8131_1; extern unsigned apicid_8131_2; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; @@ -29,6 +29,7 @@ static const char oem[8] = "TYAN "; static const char productid[12] = "S2892 "; struct mp_config_table *mc; + unsigned sbdn; unsigned char bus_num; int i; @@ -53,6 +54,7 @@ smp_write_processors(mc); get_bus_conf(); + sbdn = sysconf.sbdn; /*Bus: Bus ID Type*/ /* define bus and isa numbers */ @@ -74,11 +76,12 @@ smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } + /* Initialize interrupt mapping*/ + dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); dword = 0x12008a00; - pci_write_config32(dev, 0x80, dword); dword = 0x0000007d; Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/resourcemap.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/resourcemap.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/resourcemap.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -258,8 +258,8 @@ * This field defines the highest bus number in configuration region i */ #if 1 -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, #endif Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Config.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Config.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -2,12 +2,17 @@ ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## -if USE_FALLBACK_IMAGE +if USE_FAILOVER_IMAGE + default ROM_SECTION_SIZE = FAILOVER_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) +else + if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) default ROM_SECTION_OFFSET = 0 + end end ## @@ -16,7 +21,6 @@ ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_STREAM = 1 ## ## Compute where this copy of linuxBIOS will start in the boot rom @@ -31,11 +35,19 @@ ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +if USE_FAILOVER_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +else + if USE_FALLBACK_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + else + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + end +end + arch i386 end - ## ## Build the objects we have code for in this directory. ## @@ -92,9 +104,16 @@ ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end end mainboardinit cpu/x86/32bit/entry32.inc @@ -113,12 +132,22 @@ ## ## Build our reset vector (This is where linuxBIOS is entered) ## -if USE_FALLBACK_IMAGE +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds + end end if USE_DCACHE_RAM @@ -136,13 +165,18 @@ ## ## ROMSTRAP table for CK804 ## -if USE_FALLBACK_IMAGE +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit southbridge/nvidia/ck804/romstrap.inc + ldscript /southbridge/nvidia/ck804/romstrap.lds + end end - - if USE_DCACHE_RAM ## ## Setup Cache-As-Ram @@ -155,12 +189,20 @@ ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover_failover.lds + end + end +else + if USE_FALLBACK_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds else - mainboardinit ./failover.inc + mainboardinit ./failover.inc end + end end ## Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -2,6 +2,8 @@ uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT +uses USE_FAILOVER_IMAGE +uses HAVE_FAILOVER_BOOT uses HAVE_HARD_RESET uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE @@ -11,6 +13,7 @@ uses CONFIG_IOAPIC uses CONFIG_SMP uses FALLBACK_SIZE +uses FAILOVER_SIZE uses ROM_SIZE uses ROM_SECTION_SIZE uses ROM_IMAGE_SIZE @@ -60,6 +63,8 @@ uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT +uses SERIAL_CPU_INIT + uses ENABLE_APIC_EXT_ID uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID @@ -69,28 +74,34 @@ uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_LB_MEM_TOPK + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -#default ROM_SIZE=524288 +default ROM_SIZE=524288 #1M bytes -default ROM_SIZE=1048576 +#default ROM_SIZE=1048576 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## #default FALLBACK_SIZE=131072 -#256K -default FALLBACK_SIZE=0x40000 +#default FALLBACK_SIZE=0x40000 -### -### Build options -### +#FALLBACK: 256K-4K +default FALLBACK_SIZE=0x3f000 +#FAILOVER: 4K +default FAILOVER_SIZE=0x01000 +#more 1M for pgtbl +default CONFIG_LB_MEM_TOPK=2048 + ## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1 +default HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from linuxBIOS @@ -130,15 +141,14 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 +default SERIAL_CPU_INIT=0 + #CHIP_NAME ? #default CONFIG_CHIP_NAME=1 #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000 -#Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 - ##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0 @@ -151,6 +161,9 @@ ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + #VGA default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 @@ -163,7 +176,7 @@ default DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 +default ENABLE_APIC_EXT_ID=0 default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=0 @@ -201,12 +214,12 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) ## ## LinuxBIOS C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default _RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -220,8 +233,8 @@ ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32" +default HOSTCC="gcc-4.0.2" ## ## Disable the gdb stub by default Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -13,7 +13,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" -#include +#include "northbridge/amd/amdk8/cpu_rev.c" //#define K8_HT_FREQ_1G_SUPPORT 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" @@ -23,7 +23,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include +#include "cpu/amd/model_fxx/model_fxx_msr.h" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -6,7 +6,7 @@ //#define K8_SCAN_PCI_BUS 1 -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -21,31 +21,54 @@ #include #include "option_table.h" #include "pc80/mc146818rtc_early.c" + +#if USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x8000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + #include + #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" #endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" +#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c" +#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#define SUPERIO_GPIO_IO_BASE 0x400 + +#if USE_FAILOVER_IMAGE==0 + #include "cpu/x86/bist.h" -#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c" +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif +#include "northbridge/amd/amdk8/debug.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" + + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) @@ -58,10 +81,7 @@ { } -#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) -#define SUPERIO_GPIO_IO_BASE 0x400 - static void sio_gpio_setup(void){ unsigned value; @@ -94,6 +114,7 @@ #include "cpu/amd/dualcore/dualcore.c" #define CK804_NUM 2 +#define CK804B_BUSN 0x80 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 @@ -116,8 +137,9 @@ #include "cpu/amd/model_fxx/init_cpus.c" +#endif -#if USE_FALLBACK_IMAGE == 1 +#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -133,7 +155,7 @@ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); - byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); @@ -141,13 +163,14 @@ dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); -#if 1 + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); - value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); -#endif } @@ -175,6 +198,7 @@ ck804_enable_rom(); /* Is this a deliberate reset by the bios */ +// post_code(0x22); if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } @@ -186,28 +210,43 @@ goto fallback_image; } normal_image: +// post_code(0x23); __asm__ volatile ("jmp __normal_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ ); fallback_image: +// post_code(0x25); +#if HAVE_FAILOVER_BOOT==1 + __asm__ volatile ("jmp __fallback_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ) +#endif ; } #endif - void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); +#if HAVE_FAILOVER_BOOT==1 + #if USE_FAILOVER_IMAGE==1 + failover_process(bist, cpu_init_detectedx); + #else + real_main(bist, cpu_init_detectedx); + #endif +#else + #if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); + #endif + real_main(bist, cpu_init_detectedx); #endif - real_main(bist, cpu_init_detectedx); - } +#if USE_FAILOVER_IMAGE==0 + void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -229,6 +268,8 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } +// post_code(0x32); + lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -236,15 +277,21 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - setup_s2895_resource_map(); + sio_gpio_setup(); + setup_mb_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + needs_reset = setup_coherent_ht_domain(); - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); @@ -253,7 +300,7 @@ if (needs_reset) { print_info("ht reset -\r\n"); - soft_reset(); + // soft_reset(); } allow_all_aps_stop(bsp_apicid); @@ -263,9 +310,24 @@ fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif +#if 0 + dump_smbus_registers(); +#endif memreset_setup(); sdram_initialize(nodes, ctrl); +#if 0 + print_pci_devices(); +#endif + +#if 0 + dump_pci_devices(); +#endif + post_cache_as_ram(); } +#endif Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/get_bus_conf.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/get_bus_conf.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/get_bus_conf.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -7,7 +7,9 @@ #include #endif +#include + // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default unsigned char bus_isa; @@ -31,8 +33,7 @@ unsigned apicid_8131_2; unsigned apicid_ck804b; -unsigned sblk; -unsigned pci1234[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -44,9 +45,7 @@ // 0x0000ff0, // 0x0000ff0 }; -unsigned hc_possible_num; -unsigned sbdn; -unsigned hcdn[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -68,26 +67,32 @@ { unsigned apicid_base; + unsigned sbdn; device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done==1) return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]); - - get_sblk_pci1234(); - - sbdn = (hcdn[0] & 0xff); // first byte of first chain + sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); + for(i=0;i> 16) & 0xff; + sbdn3 = (sysconf.hcdn[1] & 0xff); + sbdnb = (sysconf.hcdn[2] & 0xff); // first byte of second chain + + bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff; + /* CK804 */ dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); if (dev) { @@ -158,7 +163,7 @@ printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); } - bus_8131_0 = (pci1234[1] >> 16) & 0xff; + bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { @@ -187,8 +192,8 @@ /* CK804b */ - if(pci1234[2] & 0xf) { //if the second cpu is installed - bus_ck804b_0 = (pci1234[2]>>16) & 0xff; + if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed + bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff; #if 0 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0)); if (dev) { Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/irq_tables.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/irq_tables.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -10,6 +10,8 @@ #include #include +#include + static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) @@ -44,10 +46,7 @@ extern unsigned char bus_ck804b_4;//e extern unsigned char bus_ck804b_5;//f -extern unsigned pci1234[]; -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdnb; @@ -58,11 +57,13 @@ struct irq_info *pirq_info; unsigned slot_num; uint8_t *v; + unsigned sbdn; uint8_t sum=0; int i; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + sbdn = sysconf.sbdn; /* Align the table to be 16 byte aligned. */ addr += 15; @@ -98,7 +99,7 @@ write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - if(pci1234[2] & 0xf) { + if(sysconf.pci1234[2] & 0xf) { //second pci beidge write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); pirq_info++; slot_num++; Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/mptable.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/mptable.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/mptable.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -4,6 +4,8 @@ #include #include +#include + extern unsigned char bus_isa; extern unsigned char bus_ck804_0; //1 extern unsigned char bus_ck804_1; //2 @@ -25,10 +27,6 @@ extern unsigned apicid_8131_2; extern unsigned apicid_ck804b; -extern unsigned pci1234[]; - -extern unsigned sbdn; -extern unsigned hcdn[]; extern unsigned sbdn3; extern unsigned sbdnb; @@ -38,6 +36,7 @@ static const char oem[8] = "TYAN "; static const char productid[12] = "S2895 "; struct mp_config_table *mc; + unsigned sbdn; unsigned char bus_num; int i; @@ -62,6 +61,7 @@ smp_write_processors(mc); get_bus_conf(); + sbdn = sysconf.sbdn; /*Bus: Bus ID Type*/ /* define bus and isa numbers */ @@ -83,6 +83,7 @@ smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } + /* Initialize interrupt mapping*/ dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); @@ -110,7 +111,7 @@ } } - if(pci1234[2] & 0xf) { + if(sysconf.pci1234[2] & 0xf) { dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); @@ -181,7 +182,7 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); } - if(pci1234[2] & 0xf) { + if(sysconf.pci1234[2] & 0xf) { //Onboard ck804b NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/resourcemap.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/resourcemap.c 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/resourcemap.c 2006-10-04 23:57:49 UTC (rev 2442) @@ -3,7 +3,7 @@ * */ -static void setup_s2895_resource_map(void) +static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ @@ -183,7 +183,7 @@ * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, // need to talk to ANALOG of second CK804 to release PCI E reset PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -253,10 +253,10 @@ * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */ + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */ }; Modified: trunk/LinuxBIOSv2/targets/tyan/s2895/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/tyan/s2895/Config.lb 2006-10-04 23:09:09 UTC (rev 2441) +++ trunk/LinuxBIOSv2/targets/tyan/s2895/Config.lb 2006-10-04 23:57:49 UTC (rev 2442) @@ -8,13 +8,14 @@ # Tyan s2895 romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 +# option ROM_SIZE = 458752 # 64K for NIC option 48K for Raid option rom -# option ROM_SIZE = 512*1024-64*1024-48*1024 +# option ROM_SIZE = 409600 + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 # option ROM_IMAGE_SIZE=0x11800 # option ROM_IMAGE_SIZE=0x13800 @@ -44,6 +45,7 @@ end romimage "fallback" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 # option ROM_IMAGE_SIZE=0x11800 # option ROM_IMAGE_SIZE=0x13800 @@ -69,4 +71,14 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" +end + + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" From yinghai.lu at amd.com Thu Oct 5 02:02:43 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Wed, 4 Oct 2006 17:02:43 -0700 Subject: [LinuxBIOS] r2439 - in trunk/LinuxBIOSv2/src: arch/i386/include/arch arch/i386/lib config console cpu/amd/car cpu/amd/model_fxx devices drivers/i2c/adm1027 include/cpu/amd lib mainboard/Iwill/DK8HTX mainboard/amd/serengeti_cheetah mainboard/amd/sereng Message-ID: <5986589C150B2F49A46483AC44C7BCA412D650@ssvlexmb2.amd.com> That is for MMIO config and PCI segment for PCIE and MMCONFIG later. YH From info at coresystems.de Thu Oct 5 02:04:08 2006 From: info at coresystems.de (LinuxBIOS information) Date: Thu, 05 Oct 2006 02:04:08 +0200 Subject: [LinuxBIOS] r2439 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2439 to the LinuxBIOS source repository and caused the following changes: Change Log: CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in serengeti_cheeatah Build Log: Compilation of amd:serengeti_cheetah has ben broken Compilation of amd:serengeti_leopard has ben broken Compilation of embeddedplanet:ep405pc has ben broken Compilation of emulation:qemu-i386 is still broken Compilation of motorola:sandpointx3_altimus_mpc7410 has ben broken Compilation of totalimpact:briq has ben broken If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From svn at openbios.org Thu Oct 5 02:27:44 2006 From: svn at openbios.org (svn at openbios.org) Date: Thu, 05 Oct 2006 02:27:44 +0200 Subject: [LinuxBIOS] r2443 - in trunk/LinuxBIOSv2/src: console lib Message-ID: Author: yhlu Date: 2006-10-05 02:27:44 +0200 (Thu, 05 Oct 2006) New Revision: 2443 Modified: trunk/LinuxBIOSv2/src/console/Config.lb trunk/LinuxBIOSv2/src/lib/Config.lb Log: make ppc happy for console Modified: trunk/LinuxBIOSv2/src/console/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/console/Config.lb 2006-10-04 23:57:49 UTC (rev 2442) +++ trunk/LinuxBIOSv2/src/console/Config.lb 2006-10-05 00:27:44 UTC (rev 2443) @@ -25,7 +25,7 @@ object vsprintf.o if CONFIG_USE_INIT - if CONFIG_USE_PRINTK_IN_CAR +# if CONFIG_USE_PRINTK_IN_CAR initobject vtxprintf.o - end +# end end Modified: trunk/LinuxBIOSv2/src/lib/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/lib/Config.lb 2006-10-04 23:57:49 UTC (rev 2442) +++ trunk/LinuxBIOSv2/src/lib/Config.lb 2006-10-05 00:27:44 UTC (rev 2443) @@ -17,9 +17,9 @@ makedefine .PHONY : version.o if CONFIG_USE_INIT - if CONFIG_USE_PRINTK_IN_CAR +# if CONFIG_USE_PRINTK_IN_CAR initobject uart8250.c - end +# end initobject memset.o initobject memcpy.o initobject memcmp.o From info at coresystems.de Thu Oct 5 02:45:06 2006 From: info at coresystems.de (LinuxBIOS information) Date: Thu, 05 Oct 2006 02:45:06 +0200 Subject: [LinuxBIOS] r2440 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2440 to the LinuxBIOS source repository and caused the following changes: Change Log: qemu abuild fix Build Log: Compilation of amd:serengeti_cheetah is still broken Compilation of amd:serengeti_leopard is still broken Compilation of embeddedplanet:ep405pc is still broken Compilation of emulation:qemu-i386 has been fixed Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken Compilation of totalimpact:briq is still broken If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From tylerapohl at gmail.com Thu Oct 5 03:31:49 2006 From: tylerapohl at gmail.com (Tyler Pohl) Date: Wed, 4 Oct 2006 18:31:49 -0700 Subject: [LinuxBIOS] via/epia Message-ID: <503ab0210610041831h1f5d7158o5aa364d76da7d2a2@mail.gmail.com> No i get no hangs at 1106 0601 I do however experience hangs at: Slot 00 is SDRAM 08000000 bytes x2 This hang happens the second time i cold boot my epia after a flash. The first time i cold boot it hangs at jmuping to linux bios. Tyler -------------- next part -------------- An HTML attachment was scrubbed... URL: From uwe at hermann-uwe.de Thu Oct 5 04:23:49 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Thu, 5 Oct 2006 04:23:49 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D63C@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D63C@ssvlexmb2.amd.com> Message-ID: <20061005022349.GB12765@greenwood> Hi, On Mon, Oct 02, 2006 at 11:43:14AM -0700, Lu, Yinghai wrote: > To my personal understanding, copyright is copyright, license is > license. True. > Every code in LinuxBIOS is under GPL. No all of it. Some parts are taken from other projects and may be under a GPL-compatible license, e.g. the BSD license. It's important to make it very clear what the exact licence of each file is and who is the copyright owner. Could you please add the standard GPL license header to your files in svn? Something like this, for example: /* * Copyright (C) 2006 ADVANCED MICRO DEVICES * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ That would be great! Cheers, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From yinghai.lu at amd.com Thu Oct 5 04:29:40 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Wed, 4 Oct 2006 19:29:40 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> How about /* * Copyright (C) 2006 ADVANCED MICRO DEVICES * * This code is under GPL * * main change log: * */ YH From info at coresystems.de Thu Oct 5 07:37:23 2006 From: info at coresystems.de (LinuxBIOS information) Date: Thu, 05 Oct 2006 07:37:23 +0200 Subject: [LinuxBIOS] r2441 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2441 to the LinuxBIOS source repository and caused the following changes: Change Log: add missed asl for ht chain Build Log: Compilation of amd:serengeti_cheetah has been fixed Compilation of amd:serengeti_leopard has been fixed Compilation of embeddedplanet:ep405pc is still broken Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken Compilation of totalimpact:briq is still broken If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From info at coresystems.de Thu Oct 5 08:15:59 2006 From: info at coresystems.de (LinuxBIOS information) Date: Thu, 05 Oct 2006 08:15:59 +0200 Subject: [LinuxBIOS] r2442 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2442 to the LinuxBIOS source repository and caused the following changes: Change Log: get_bus_cong using sysconf instead Build Log: Compilation of embeddedplanet:ep405pc is still broken Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken Compilation of totalimpact:briq is still broken If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From svn at openbios.org Thu Oct 5 08:24:22 2006 From: svn at openbios.org (svn at openbios.org) Date: Thu, 05 Oct 2006 08:24:22 +0200 Subject: [LinuxBIOS] r2444 - trunk/LinuxBIOSv2/src/arch/i386 Message-ID: Author: yhlu Date: 2006-10-05 08:24:21 +0200 (Thu, 05 Oct 2006) New Revision: 2444 Modified: trunk/LinuxBIOSv2/src/arch/i386/Config.lb Log: init.o Modified: trunk/LinuxBIOSv2/src/arch/i386/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/arch/i386/Config.lb 2006-10-05 00:27:44 UTC (rev 2443) +++ trunk/LinuxBIOSv2/src/arch/i386/Config.lb 2006-10-05 06:24:21 UTC (rev 2444) @@ -99,7 +99,7 @@ end makerule linuxbios - depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld" + depends "crt0.o init.o $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o" action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" end From info at coresystems.de Thu Oct 5 08:55:52 2006 From: info at coresystems.de (LinuxBIOS information) Date: Thu, 05 Oct 2006 08:55:52 +0200 Subject: [LinuxBIOS] r2443 build service Message-ID: Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "yhlu" checked in revision 2443 to the LinuxBIOS source repository and caused the following changes: Change Log: make ppc happy for console Build Log: Compilation of embeddedplanet:ep405pc has been fixed Compilation of motorola:sandpointx3_altimus_mpc7410 has been fixed Compilation of totalimpact:briq has been fixed If something broke during this checkin please be a pain in yhlu's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system From svn at openbios.org Thu Oct 5 08:59:57 2006 From: svn at openbios.org (svn at openbios.org) Date: Thu, 05 Oct 2006 08:59:57 +0200 Subject: [LinuxBIOS] r2445 - in trunk/LinuxBIOSv2/src: mainboard/agami/aruma mainboard/amd/serengeti_leopard mainboard/sunw/ultra40 mainboard/tyan/s2850 mainboard/tyan/s2875 mainboard/tyan/s2880 mainboard/tyan/s2881 mainboard/tyan/s2882 mainboard/tyan/s2885 mainboard/tyan/s2891 mainboard/tyan/s2892 mainboard/tyan/s2895 mainboard/tyan/s4880 mainboard/tyan/s4882 northbridge/amd/amdk8 Message-ID: Author: yhlu Date: 2006-10-05 08:59:56 +0200 (Thu, 05 Oct 2006) New Revision: 2445 Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/auto.c trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c Log: K8_4RANK to QRANK Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -8,7 +8,7 @@ #endif //use by raminit -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 //used by incoherent_ht //#define K8_SCAN_PCI_BUS 1 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -129,7 +129,7 @@ } //#include "northbridge/amd/amdk8/setup_resource_map.c" -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #if 0 Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -91,7 +91,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #if 0 Modified: trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -6,7 +6,7 @@ //#define K8_SCAN_PCI_BUS 1 -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -79,8 +79,6 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 - #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -68,7 +68,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -69,7 +69,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -107,7 +107,7 @@ } //#include "northbridge/amd/amdk8/setup_resource_map.c" -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -108,7 +108,7 @@ } #include "northbridge/amd/amdk8/setup_resource_map.c" -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -68,7 +68,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -106,7 +106,7 @@ } //#include "northbridge/amd/amdk8/setup_resource_map.c" -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #if 0 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -69,7 +69,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -69,7 +69,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -91,7 +91,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #if 0 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -83,7 +83,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -115,7 +115,7 @@ } #include "northbridge/amd/amdk8/setup_resource_map.c" -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #if 0 #define ENABLE_APIC_EXT_ID 1 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -92,7 +92,7 @@ return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 +#define QRANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c 2006-10-05 06:24:21 UTC (rev 2444) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c 2006-10-05 06:59:56 UTC (rev 2445) @@ -17,8 +17,8 @@ # error "CONFIG_LB_MEM_TOPK must be a power of 2" #endif -#ifndef K8_4RANK_DIMM_SUPPORT -#define K8_4RANK_DIMM_SUPPORT 0 +#ifndef QRANK_DIMM_SUPPORT +#define QRANK_DIMM_SUPPORT 0 #endif #if defined (__GNUC__) @@ -631,7 +631,7 @@ unsigned long side2; unsigned long rows; unsigned long col; -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 unsigned long rank; #endif }; @@ -645,7 +645,7 @@ sz.side2 = 0; sz.rows = 0; sz.col = 0; -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 sz.rank = 0; #endif @@ -689,7 +689,7 @@ if ((value != 2) && (value != 4 )) { goto val_err; } -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 sz.rank = value; #endif @@ -718,7 +718,7 @@ sz.side2 = 0; sz.rows = 0; sz.col = 0; -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 sz.rank = 0; #endif out: @@ -766,7 +766,7 @@ /* Set the appropriate DIMM base address register */ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); @@ -777,7 +777,7 @@ if (base0) { dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch |= DCH_MEMCLK_EN0 << index; -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { dch |= DCH_MEMCLK_EN0 << (index + 2); } @@ -800,7 +800,7 @@ map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { map &= ~(0xf << ( (index + 2) * 4)); } @@ -811,7 +811,7 @@ if (sz.side1 >= (25 +3)) { if(is_cpu_pre_d0()) { map |= (sz.side1 - (25 + 3)) << (index *4); -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4); } @@ -819,7 +819,7 @@ } else { map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4); -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4); } @@ -1538,7 +1538,7 @@ } #if 0 //down speed for full load 4 rank support -#if K8_4RANK_DIMM_SUPPORT +#if QRANK_DIMM_SUPPORT if(dimm_mask == (3|(3<channel0[i]); i++) { @@ -1804,7 +1804,7 @@ { uint32_t dcl; int value; -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 int rank; #endif int dimm; @@ -1813,7 +1813,7 @@ return -1; } -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */ if (rank < 0) { return -1; @@ -1821,7 +1821,7 @@ #endif dimm = 1<<(DCL_x4DIMM_SHIFT+i); -#if K8_4RANK_DIMM_SUPPORT == 1 +#if QRANK_DIMM_SUPPORT == 1 if(rank==4) { dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } From stepan at coresystems.de Thu Oct 5 10:42:39 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Thu, 5 Oct 2006 10:42:39 +0200 Subject: [LinuxBIOS] r2442 - in trunk/LinuxBIOSv2: src/mainboard/broadcom/blast src/mainboard/tyan/s2881 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 targets/tyan/s2895 In-Reply-To: References: Message-ID: <20061005084239.GA17766@coresystems.de> Yinghai, why are you backing out my patches? Is this just sleazyness while merging the trees? I think we should go back to 2434 and start reviewing all of what gets checked in. * svn at openbios.org [061005 01:57]: > --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) > +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) > @@ -78,10 +78,10 @@ > 7 9 Fallback_HDD > 7 10 Fallback_Floppy > #7 3 ROM > -8 0 DDR400 > -8 1 DDR333 > -8 2 DDR266 > -8 3 DDR200 > +8 0 200Mhz > +8 1 166Mhz > +8 2 133Mhz > +8 3 100Mhz > 9 0 off > 9 1 87.5% > 9 2 75.0% [...] Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Thu Oct 5 10:44:04 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Thu, 5 Oct 2006 10:44:04 +0200 Subject: [LinuxBIOS] r2439 - in trunk/LinuxBIOSv2/src: arch/i386/include/arch arch/i386/lib config console cpu/amd/car cpu/amd/model_fxx devices drivers/i2c/adm1027 include/cpu/amd lib mainboard/Iwill/DK8HTX mainboard/amd/serengeti_cheetah mainboard/amd/sereng In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D650@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D650@ssvlexmb2.amd.com> Message-ID: <20061005084404.GB17766@coresystems.de> * Lu, Yinghai [061005 02:02]: > That is for MMIO config and PCI segment for PCIE and MMCONFIG later. good, then please either make an extra patch, or mention it in the changelog at least, in the future. If we're having trouble at some point, nobody will know what this was about anymore. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Thu Oct 5 10:46:23 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Thu, 5 Oct 2006 10:46:23 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D64F@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D64F@ssvlexmb2.amd.com> Message-ID: <20061005084623.GA9670@coresystems.de> * Lu, Yinghai [061005 01:14]: > No. Your MB Config.lb is using reset16.*. So it only can be used for > fallback. Since when is this? And what is the correct way to fix it? > Also I added Config-abuild.lb for qemu-i386. and abuild is happy again. Thank you. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From uwe at hermann-uwe.de Thu Oct 5 11:07:53 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Thu, 5 Oct 2006 11:07:53 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> Message-ID: <20061005090753.GA27466@greenwood> Hi, On Wed, Oct 04, 2006 at 07:29:40PM -0700, Lu, Yinghai wrote: > How about > > /* > * Copyright (C) 2006 ADVANCED MICRO DEVICES > * > * This code is under GPL > * > * main change log: > * > */ It's better than nothing, but I would rather use the full GPL header, because that - includes a "no warranty" phrase - explicitly states whether it's "GPL v2" or "GPL v2 or later" - is the de-facto standard used in 98% or so of all GPL'd projects As for the changelog, I don't think that's necessary. That information is contained in the svn commit logs (at least it should), there's no need to duplicate it in the files... HTH, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From myles at pel.cs.byu.edu Thu Oct 5 15:27:43 2006 From: myles at pel.cs.byu.edu (Myles Watson) Date: Thu, 05 Oct 2006 07:27:43 -0600 Subject: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? In-Reply-To: <4E497EE4DD5F9347B242A83387F27DC8BFDACF@exchsix.olympus.f5net.com> Message-ID: <01M7ZQ1X8SS08YFLTE@EMAIL1.BYU.EDU> I found that the best way for me to learn about this was to play with the factory BIOS settings. The memory hole allows you to boost part of memory above 4GB so that you have more room for I/O devices without losing memory capacity. For example, if you had a graphics card with 256MB of memory and 4GB of RAM installed in the machine, you cannot address both and keep them inside 32-bits. The solution is to use registers on the Opteron to map some of your RAM above that limit. Myles _____ From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Alan Mimms Sent: Wednesday, October 04, 2006 1:59 PM To: Lu, Yinghai; linuxbios at linuxbios.org; Andi Kleen Subject: Re: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? The problem occurs with 1GB, 2GB or 4GB of memory installed for sure. I do not know about the HW memory hole. Can you explain what that is? Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center 1322 North Whitman Lane Liberty Lake, Washington 99019 v: 509-343-3524 f: 509-343-3501 _____ From: Lu, Yinghai [mailto:yinghai.lu at amd.com] Sent: Wednesday, October 04, 2006 12:05 PM To: Alan Mimms; linuxbios at linuxbios.org; Andi Kleen Subject: RE: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? What's your total RAM installed? 4G or more. With HW memory hole enable? YH _____ From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Alan Mimms Sent: Wednesday, October 04, 2006 11:28 AM To: linuxbios at linuxbios.org Subject: [LinuxBIOS] ACPI NVS and last 64k-ish area of RAM? We have AMD dual Opteron hardware with AMD 8131+8111 chipsets attached. Using LinuxBIOS, we have a slight problem, that APPEARS to be related to the last 64Kbytes of RAM. Our kboot based environment, running in 32 bit instruction set, seems to randomly crash, and the implicated area of memory is this last 64KB. When we run a commercial BIOS on nearly identical hardware, we see that that BIOS has created in the E820 table an ACPI Non-Volatile-Storage area covering this last 64KB. LinuxBIOS is NOT doing that; LinuxBIOS is treating all of the space as simple USABLE space. In trying to figure this out, we have used the AMD HDT tool to read the last 64KB. We (SOMETIMES) the system crashes when we read this area using HDT. Can someone please explain what this area is for and why it's strange to read even using a hardware debugging tool? Is it REALLY in use for the ACPI NVS, and can we simply tell Linux to ignore it (map it out) by creating an entry in E820 table so it won't be used (we don't use ACPI suspend/resume)? Thanks very much for any information. Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center 1322 North Whitman Lane Liberty Lake, Washington 99019 v: 509-343-3524 f: 509-343-3501 -------------- next part -------------- An HTML attachment was scrubbed... URL: From yinghailu at gmail.com Thu Oct 5 17:50:28 2006 From: yinghailu at gmail.com (yhlu) Date: Thu, 5 Oct 2006 08:50:28 -0700 Subject: [LinuxBIOS] r2442 - in trunk/LinuxBIOSv2: src/mainboard/broadcom/blast src/mainboard/tyan/s2881 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 targets/tyan/s2895 In-Reply-To: <20061005084239.GA17766@coresystems.de> References: <20061005084239.GA17766@coresystems.de> Message-ID: <2ea3fae10610050850n743d043fy32524decffaa084@mail.gmail.com> sorry, that is only for several MBs with get_bus_conf. I overwrote the whole dirs for 6 tyan MB and Blast. these cmos.layout should be backed to DDRXXX etc. YH On 10/5/06, Stefan Reinauer wrote: > Yinghai, why are you backing out my patches? > > Is this just sleazyness while merging the trees? > > I think we should go back to 2434 and start reviewing all of what gets > checked in. > > * svn at openbios.org [061005 01:57]: > > --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-04 23:09:09 UTC (rev 2441) > > +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-04 23:57:49 UTC (rev 2442) > > @@ -78,10 +78,10 @@ > > 7 9 Fallback_HDD > > 7 10 Fallback_Floppy > > #7 3 ROM > > -8 0 DDR400 > > -8 1 DDR333 > > -8 2 DDR266 > > -8 3 DDR200 > > +8 0 200Mhz > > +8 1 166Mhz > > +8 2 133Mhz > > +8 3 100Mhz > > 9 0 off > > 9 1 87.5% > > 9 2 75.0% > > [...] > > Stefan > > -- > coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 ? Fax: +49 761 7664613 > Email: info at coresystems.de ? http://www.coresystems.de/ > > -- > linuxbios mailing list > linuxbios at linuxbios.org > http://www.openbios.org/mailman/listinfo/linuxbios From yinghai.lu at amd.com Thu Oct 5 19:00:25 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Thu, 5 Oct 2006 10:00:25 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D652@ssvlexmb2.amd.com> http://www.openbios.org/viewcvs/trunk/LinuxBIOSv2/src/mainboard/emulatio n/qemu-i386/Config.lb?r1=2127&r2=2402 Ron modified. YH -----Original Message----- From: Stefan Reinauer [mailto:stepan at coresystems.de] Sent: Thursday, October 05, 2006 1:46 AM To: Lu, Yinghai Cc: linuxbios at linuxbios.org Subject: Re: [LinuxBIOS] FW: rev F support code * Lu, Yinghai [061005 01:14]: > No. Your MB Config.lb is using reset16.*. So it only can be used for > fallback. Since when is this? And what is the correct way to fix it? > Also I added Config-abuild.lb for qemu-i386. and abuild is happy again. Thank you. -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info at coresystems.de * http://www.coresystems.de/ From eswierk at arastra.com Thu Oct 5 19:41:19 2006 From: eswierk at arastra.com (Ed Swierk) Date: Thu, 5 Oct 2006 10:41:19 -0700 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D652@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D652@ssvlexmb2.amd.com> Message-ID: On 10/5/06, Lu, Yinghai wrote: > http://www.openbios.org/viewcvs/trunk/LinuxBIOSv2/src/mainboard/emulatio > n/qemu-i386/Config.lb?r1=2127&r2=2402 > > Ron modified. That was a patch I submitted a few weeks back. As I said in the accompanying email, I couldn't figure out the purpose of fallback image support for the qemu target or how to configure things so that the final ROM has only one image in it (fallback or not), so I removed the fallback stuff. --Ed From yinghai.lu at amd.com Thu Oct 5 20:00:53 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Thu, 5 Oct 2006 11:00:53 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D655@ssvlexmb2.amd.com> Then you should modify Config.lb in targets dir. YH -----Original Message----- From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Ed Swierk Sent: Thursday, October 05, 2006 10:41 AM To: LinuxBIOS Subject: Re: [LinuxBIOS] FW: rev F support code On 10/5/06, Lu, Yinghai wrote: > http://www.openbios.org/viewcvs/trunk/LinuxBIOSv2/src/mainboard/emulatio > n/qemu-i386/Config.lb?r1=2127&r2=2402 > > Ron modified. That was a patch I submitted a few weeks back. As I said in the accompanying email, I couldn't figure out the purpose of fallback image support for the qemu target or how to configure things so that the final ROM has only one image in it (fallback or not), so I removed the fallback stuff. --Ed -- linuxbios mailing list linuxbios at linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios From eswierk at arastra.com Thu Oct 5 20:06:57 2006 From: eswierk at arastra.com (Ed Swierk) Date: Thu, 5 Oct 2006 11:06:57 -0700 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D655@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D655@ssvlexmb2.amd.com> Message-ID: On 10/5/06, Lu, Yinghai wrote: > Then you should modify Config.lb in targets dir. Can you be a bit more specific? It's not clear to me what is currently broken. --Ed From yinghai.lu at amd.com Thu Oct 5 20:21:14 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Thu, 5 Oct 2006 11:21:14 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D657@ssvlexmb2.amd.com> The abuild will create one config.lb for test. The config will include fallback + normal. Normal image can not use reset16.lds, because reset16.lds need to make sure _start in last 64K near 4G. When Normal together fallback images there, it can not make it happen. YH -----Original Message----- From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Ed Swierk Sent: Thursday, October 05, 2006 11:07 AM To: LinuxBIOS Subject: Re: [LinuxBIOS] FW: rev F support code On 10/5/06, Lu, Yinghai wrote: > Then you should modify Config.lb in targets dir. Can you be a bit more specific? It's not clear to me what is currently broken. --Ed -- linuxbios mailing list linuxbios at linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios From eswierk at arastra.com Thu Oct 5 21:00:42 2006 From: eswierk at arastra.com (Ed Swierk) Date: Thu, 5 Oct 2006 12:00:42 -0700 Subject: [LinuxBIOS] Configuring PCI devices Message-ID: I'm working on porting LinuxBIOS to an AM2+MCP55-based mainboard (DFI LANParty UT NF590) using the latest AMD Rev F and MCP55 southbridge code from svn. I replaced most of the CK804 PCI device IDs with their MCP55 counterparts, and put the following in my mainboard Config.lb: chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_AM2 device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 #mc0 device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/ck804 device pci a.0 on end device pci a.1 on end device pci c.0 on end end end # device pci 18.0 device pci 18.0 on end # Link 1 device pci 18.0 on end # Link 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end #mc0 end # pci_domain end # root_complex Obviously this is not quite right, since I get the following output during boot: Jumping to LinuxBIOS. LinuxBIOS-2.0.0-FILO Thu Oct 5 11:34:43 PDT 2006 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:1e.0 [10de/0369] enabled PCI: 00:1f.0 [10de/0360] enabled PCI: 00:1f.1 [10de/0368] enabled PCI: 00:1f.2 [10de/036a] enabled Disabling static device: PCI: 00:0a.0 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/036c] enabled PCI: 00:00.1 [10de/036d] enabled PCI: 00:0a.0 PCI: 00:0a.1 PCI: 00:0c.0 PCI: Left over static devices. Check your Config.lb I'm pretty fuzzy on what exactly belongs in the device/chip section of the Config.lb, and how this affects the PCI device enumeration during boot (e.g. how did device 10de:036c get mapped to 00:00.0?). Is there a document that explains this? I've attached the output of lspci (using the factory BIOS), as well as my modified pci_ids.h and cache_as_ram_auto.c. Any pointers would be appreciated. --Ed -------------- next part -------------- A non-text attachment was scrubbed... Name: pci_ids.h.excerpt Type: application/octet-stream Size: 4031 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: cache_as_ram_auto.c Type: text/x-csrc Size: 4985 bytes Desc: not available URL: -------------- next part -------------- 00:00.0 RAM memory: nVidia Corporation C51 Host Bridge (rev a2) 00:00.1 RAM memory: nVidia Corporation C51 Memory Controller 0 (rev a2) 00:00.2 RAM memory: nVidia Corporation C51 Memory Controller 1 (rev a2) 00:00.3 RAM memory: nVidia Corporation C51 Memory Controller 5 (rev a2) 00:00.4 RAM memory: nVidia Corporation C51 Memory Controller 4 (rev a2) 00:00.5 RAM memory: nVidia Corporation C51 Host Bridge (rev a2) 00:00.6 RAM memory: nVidia Corporation C51 Memory Controller 3 (rev a2) 00:00.7 RAM memory: nVidia Corporation C51 Memory Controller 2 (rev a2) 00:04.0 PCI bridge: nVidia Corporation C51 PCI Express Bridge (rev a1) 00:08.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a1) 00:09.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a2) 00:09.1 SMBus: nVidia Corporation MCP55 SMBus (rev a2) 00:09.2 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a2) 00:0a.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) 00:0a.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) 00:0c.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) 00:0d.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) 00:0d.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) 00:0d.2 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) 00:0e.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) 00:0e.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2) 00:10.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) 00:11.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) 00:12.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) 00:13.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) 00:15.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) 00:16.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) 00:17.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:00.0 VGA compatible controller: nVidia Corporation NV44 [GeForce 6200 LE] (rev a1) 02:09.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) 04:00.0 RAID bus controller: Silicon Image, Inc. SiI 3132 Serial ATA Raid II Controller (rev 01) -------------- next part -------------- 00:00.0 0500: 10de:02f4 (rev a2) 00:00.1 0500: 10de:02fa (rev a2) 00:00.2 0500: 10de:02fe (rev a2) 00:00.3 0500: 10de:02f8 (rev a2) 00:00.4 0500: 10de:02f9 (rev a2) 00:00.5 0500: 10de:02ff (rev a2) 00:00.6 0500: 10de:027f (rev a2) 00:00.7 0500: 10de:027e (rev a2) 00:04.0 0604: 10de:02fb (rev a1) 00:08.0 0500: 10de:0369 (rev a1) 00:09.0 0601: 10de:0360 (rev a2) 00:09.1 0c05: 10de:0368 (rev a2) 00:09.2 0500: 10de:036a (rev a2) 00:0a.0 0c03: 10de:036c (rev a1) 00:0a.1 0c03: 10de:036d (rev a2) 00:0c.0 0101: 10de:036e (rev a1) 00:0d.0 0101: 10de:037f (rev a2) 00:0d.1 0101: 10de:037f (rev a2) 00:0d.2 0101: 10de:037f (rev a2) 00:0e.0 0604: 10de:0370 (rev a2) 00:0e.1 0403: 10de:0371 (rev a2) 00:10.0 0680: 10de:0373 (rev a2) 00:11.0 0680: 10de:0373 (rev a2) 00:12.0 0604: 10de:0376 (rev a2) 00:13.0 0604: 10de:0374 (rev a2) 00:15.0 0604: 10de:0378 (rev a2) 00:16.0 0604: 10de:0375 (rev a2) 00:17.0 0604: 10de:0377 (rev a2) 00:18.0 0600: 1022:1100 00:18.1 0600: 1022:1101 00:18.2 0600: 1022:1102 00:18.3 0600: 1022:1103 01:00.0 0300: 10de:0163 (rev a1) 02:09.0 0c00: 1106:3044 (rev 80) 04:00.0 0104: 1095:3132 (rev 01) -------------- next part -------------- -[0000:00]-+-00.0 nVidia Corporation C51 Host Bridge +-00.1 nVidia Corporation C51 Memory Controller 0 +-00.2 nVidia Corporation C51 Memory Controller 1 +-00.3 nVidia Corporation C51 Memory Controller 5 +-00.4 nVidia Corporation C51 Memory Controller 4 +-00.5 nVidia Corporation C51 Host Bridge +-00.6 nVidia Corporation C51 Memory Controller 3 +-00.7 nVidia Corporation C51 Memory Controller 2 +-04.0-[0000:01]----00.0 nVidia Corporation NV44 [GeForce 6200 LE] +-08.0 nVidia Corporation MCP55 Memory Controller +-09.0 nVidia Corporation MCP55 LPC Bridge +-09.1 nVidia Corporation MCP55 SMBus +-09.2 nVidia Corporation MCP55 Memory Controller +-0a.0 nVidia Corporation MCP55 USB Controller +-0a.1 nVidia Corporation MCP55 USB Controller +-0c.0 nVidia Corporation MCP55 IDE +-0d.0 nVidia Corporation MCP55 SATA Controller +-0d.1 nVidia Corporation MCP55 SATA Controller +-0d.2 nVidia Corporation MCP55 SATA Controller +-0e.0-[0000:02]----09.0 VIA Technologies, Inc. IEEE 1394 Host Controller +-0e.1 nVidia Corporation MCP55 High Definition Audio +-10.0 nVidia Corporation MCP55 Ethernet +-11.0 nVidia Corporation MCP55 Ethernet +-12.0-[0000:03]-- +-13.0-[0000:04]----00.0 Silicon Image, Inc. SiI 3132 Serial ATA Raid II Controller +-15.0-[0000:05]-- +-16.0-[0000:06]-- +-17.0-[0000:07]-- +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller \-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control From yinghai.lu at amd.com Thu Oct 5 21:59:37 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Thu, 5 Oct 2006 12:59:37 -0700 Subject: [LinuxBIOS] Configuring PCI devices Message-ID: <5986589C150B2F49A46483AC44C7BCA412D65A@ssvlexmb2.amd.com> The build tools will create on static.c that includes static devices. The hypertransport_scan_chain() will take some static devices from the device list and match them with probed device. So the probed device can get extra setting from the static device. The device num is adjusted according to ht unit base id too at that time. YH -----Original Message----- From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Ed Swierk Sent: Thursday, October 05, 2006 12:01 PM To: LinuxBIOS Subject: [LinuxBIOS] Configuring PCI devices I'm working on porting LinuxBIOS to an AM2+MCP55-based mainboard (DFI LANParty UT NF590) using the latest AMD Rev F and MCP55 southbridge code from svn. I replaced most of the CK804 PCI device IDs with their MCP55 counterparts, and put the following in my mainboard Config.lb: chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_AM2 device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 #mc0 device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/nvidia/ck804 device pci a.0 on end device pci a.1 on end device pci c.0 on end end end # device pci 18.0 device pci 18.0 on end # Link 1 device pci 18.0 on end # Link 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end #mc0 end # pci_domain end # root_complex Obviously this is not quite right, since I get the following output during boot: Jumping to LinuxBIOS. LinuxBIOS-2.0.0-FILO Thu Oct 5 11:34:43 PDT 2006 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:1e.0 [10de/0369] enabled PCI: 00:1f.0 [10de/0360] enabled PCI: 00:1f.1 [10de/0368] enabled PCI: 00:1f.2 [10de/036a] enabled Disabling static device: PCI: 00:0a.0 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/036c] enabled PCI: 00:00.1 [10de/036d] enabled PCI: 00:0a.0 PCI: 00:0a.1 PCI: 00:0c.0 PCI: Left over static devices. Check your Config.lb I'm pretty fuzzy on what exactly belongs in the device/chip section of the Config.lb, and how this affects the PCI device enumeration during boot (e.g. how did device 10de:036c get mapped to 00:00.0?). Is there a document that explains this? I've attached the output of lspci (using the factory BIOS), as well as my modified pci_ids.h and cache_as_ram_auto.c. Any pointers would be appreciated. --Ed From eswierk at arastra.com Fri Oct 6 02:42:05 2006 From: eswierk at arastra.com (Ed Swierk) Date: Thu, 5 Oct 2006 17:42:05 -0700 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM Message-ID: The attached patch adds a new option, CONFIG_XMODEM_ROM_STREAM, that allows LinuxBIOS to download its payload from the console via the XMODEM file transfer protocol. This is handy if you want to try out a payload that's too big to fit into ROM, and you haven't yet gotten IDE or USB devices to work. I chose to hook this into the ROM stream code so it can take advantage of the usual compression methods, but one could imagine moving it to a separate "serial stream" mechanism. Comments are welcome. --Ed -------------- next part -------------- A non-text attachment was scrubbed... Name: linuxbios-xmodem-rom-stream.patch Type: text/x-patch Size: 11857 bytes Desc: not available URL: From yinghai.lu at amd.com Fri Oct 6 03:29:03 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Thu, 5 Oct 2006 18:29:03 -0700 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM Message-ID: <5986589C150B2F49A46483AC44C7BCA412D65E@ssvlexmb2.amd.com> Can you move the xmodemTransmit and two mains etc to another file in util dir? Also could add print out seconds used... 4Mbyte will need 4*1024*1024*10/115200 = 364s... USB ROM emulator is very convient. YH -----Original Message----- From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Ed Swierk Sent: Thursday, October 05, 2006 5:42 PM To: LinuxBIOS Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM The attached patch adds a new option, CONFIG_XMODEM_ROM_STREAM, that allows LinuxBIOS to download its payload from the console via the XMODEM file transfer protocol. This is handy if you want to try out a payload that's too big to fit into ROM, and you haven't yet gotten IDE or USB devices to work. I chose to hook this into the ROM stream code so it can take advantage of the usual compression methods, but one could imagine moving it to a separate "serial stream" mechanism. Comments are welcome. --Ed From c-d.hailfinger.devel.2006 at gmx.net Fri Oct 6 03:12:59 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Oct 2006 03:12:59 +0200 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM In-Reply-To: References: Message-ID: <4525AD9B.6090602@gmx.net> Ed Swierk wrote: > The attached patch adds a new option, CONFIG_XMODEM_ROM_STREAM, that > allows LinuxBIOS to download its payload from the console via the > XMODEM file transfer protocol. > > This is handy if you want to try out a payload that's too big to fit > into ROM, and you haven't yet gotten IDE or USB devices to work. Great! I can see yet another use for this (after some modification): Testing LinuxBIOS code for additional devices without reflashing the ROM every time. The flash->plug-chip-in->test->rip-chip-out->flash cycle would become a flash->reboot->reboot cycle. As long as RAM and serial are working, additional bringup code could be tested easily. It would even enable us to create a "generic" ROM for a given chipset combination, leaving all the mainboard specific code to the serial stream. With some automation and LinuxBIOS architectural changes, it should be entirely possible to download all the code after RAM init via serial line, thereby geting us device bringup and testing almost for free. (I had once such self-writing driver stuff lying around (not for LinuxBIOS though), but it went down the drain when my harddisk died.) > I chose to hook this into the ROM stream code so it can take advantage > of the usual compression methods, but one could imagine moving it to a > separate "serial stream" mechanism. Compression is essential for anything that has to be downloaded over the serial line. > --- LinuxBIOSv2.old/src/stream/rom_stream.c 2006-10-05 17:30:22.000000000 -0700 > +++ LinuxBIOSv2/src/stream/rom_stream.c 2006-10-05 17:22:47.000000000 -0700 > @@ -49,6 +49,8 @@ > + unsigned char *x_start = (unsigned char *) (32 * 1024 * 1024); > + int x_len; > + > + printk_debug("rom_stream: start XMODEM transfer now!\n"); > + if ((x_len = xmodemReceive(x_start, 8 * 1024 * 1024)) > 0) { The ROM stream is put at 32 MB with max length 8 MB, right? Care to use #defines for these values? Regards, Carl-Daniel -- http://www.hailfinger.org/ From stepan at coresystems.de Fri Oct 6 12:07:41 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 12:07:41 +0200 Subject: [LinuxBIOS] Configuring PCI devices In-Reply-To: References: Message-ID: <20061006100741.GA30440@coresystems.de> * Ed Swierk [061005 21:00]: > PCI: 00:00.0 [10de/036c] enabled > PCI: 00:00.1 [10de/036d] enabled > PCI: 00:0a.0 > PCI: 00:0a.1 > PCI: 00:0c.0 > PCI: Left over static devices. Check your Config.lb > > I'm pretty fuzzy on what exactly belongs in the device/chip section of > the Config.lb, and how this affects the PCI device enumeration during > boot (e.g. how did device 10de:036c get mapped to 00:00.0?). Is there > a document that explains this? I think when you see this error the following happens: You are mentioning some device in the tree description which can not be found in the real system, so LinuxBIOS assumes there is something wrong with your bios image and refuses to continue. The first thing that looks suspicious is the CK804. LinuxBIOS probably finds the NForce5 instead of the expected NForce4 and pegs out. Please also check that the components are hanging off the correct hypertransport link. There is this funny notion in LinuxBIOS that you see pci 18.0 ... end 3 times, which reflects the 3 hypertransport links per CPU. To find out which one is the correct one, you can read out the CPU's HT config registers with factory bios, or read the mainboard schematics. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Fri Oct 6 12:22:30 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 12:22:30 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: References: <5986589C150B2F49A46483AC44C7BCA412D652@ssvlexmb2.amd.com> Message-ID: <20061006102230.GC30440@coresystems.de> * Ed Swierk [061005 19:41]: > That was a patch I submitted a few weeks back. As I said in the > accompanying email, I couldn't figure out the purpose of fallback > image support for the qemu target or how to configure things so that > the final ROM has only one image in it (fallback or not), so I removed > the fallback stuff. Right. I remember that. There will be a number of changes for v3, so I think we do not need to care for this anymore. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From rminnich at lanl.gov Fri Oct 6 16:57:57 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 08:57:57 -0600 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <20061005090753.GA27466@greenwood> References: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> <20061005090753.GA27466@greenwood> Message-ID: <45266EF5.8070207@lanl.gov> Uwe Hermann wrote: > Hi, > > On Wed, Oct 04, 2006 at 07:29:40PM -0700, Lu, Yinghai wrote: > >>How about >> >>/* >> * Copyright (C) 2006 ADVANCED MICRO DEVICES >> * >> * This code is under GPL >> * >> * main change log: >> * >> */ > > > It's better than nothing, but I would rather use the full GPL header, > because that > > - includes a "no warranty" phrase > - explicitly states whether it's "GPL v2" or "GPL v2 or later" > - is the de-facto standard used in 98% or so of all GPL'd projects > > As for the changelog, I don't think that's necessary. That information > is contained in the svn commit logs (at least it should), there's no > need to duplicate it in the files... > > > HTH, Uwe. > you can include it by reference, see drivers/net: Copyright 1993 United States Government as represented by the Director, National Security Agency. This software may only be used and distributed according to the terms of the GNU General Public License as modified by SRC, incorporated herein by reference. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The key part if it's good enough for the NSA ... ron From rminnich at lanl.gov Fri Oct 6 16:58:41 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 08:58:41 -0600 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D652@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D652@ssvlexmb2.amd.com> Message-ID: <45266F21.4020702@lanl.gov> Lu, Yinghai wrote: > http://www.openbios.org/viewcvs/trunk/LinuxBIOSv2/src/mainboard/emulatio > n/qemu-i386/Config.lb?r1=2127&r2=2402 > > Ron modified. > oh gosh, what did I do now? ron From stepan at coresystems.de Fri Oct 6 17:11:31 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 17:11:31 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <45266F21.4020702@lanl.gov> References: <5986589C150B2F49A46483AC44C7BCA412D652@ssvlexmb2.amd.com> <45266F21.4020702@lanl.gov> Message-ID: <20061006151131.GA26464@coresystems.de> * Ronald G Minnich [061006 16:58]: > Lu, Yinghai wrote: > >http://www.openbios.org/viewcvs/trunk/LinuxBIOSv2/src/mainboard/emulatio > >n/qemu-i386/Config.lb?r1=2127&r2=2402 > > > >Ron modified. > > > > oh gosh, what did I do now? everything ok with this one. we want to concentrate on getting things right in v3 rather than fixing linker magic in v2 -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Fri Oct 6 17:11:54 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 17:11:54 +0200 Subject: [LinuxBIOS] r2442 - in trunk/LinuxBIOSv2: src/mainboard/broadcom/blast src/mainboard/tyan/s2881 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 targets/tyan/s2895 In-Reply-To: <2ea3fae10610050850n743d043fy32524decffaa084@mail.gmail.com> References: <20061005084239.GA17766@coresystems.de> <2ea3fae10610050850n743d043fy32524decffaa084@mail.gmail.com> Message-ID: <20061006151154.GB26464@coresystems.de> * yhlu [061005 17:50]: > sorry, that is only for several MBs with get_bus_conf. I overwrote the > whole dirs for 6 tyan MB and Blast. these cmos.layout should be backed > to DDRXXX etc. Can you do that please? > > On 10/5/06, Stefan Reinauer wrote: > >Yinghai, why are you backing out my patches? > > > >Is this just sleazyness while merging the trees? > > > >I think we should go back to 2434 and start reviewing all of what gets > >checked in. > > > >* svn at openbios.org [061005 01:57]: > >> --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout > >2006-10-04 23:09:09 UTC (rev 2441) > >> +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout > >2006-10-04 23:57:49 UTC (rev 2442) > >> @@ -78,10 +78,10 @@ > >> 7 9 Fallback_HDD > >> 7 10 Fallback_Floppy > >> #7 3 ROM > >> -8 0 DDR400 > >> -8 1 DDR333 > >> -8 2 DDR266 > >> -8 3 DDR200 > >> +8 0 200Mhz > >> +8 1 166Mhz > >> +8 2 133Mhz > >> +8 3 100Mhz > >> 9 0 off > >> 9 1 87.5% > >> 9 2 75.0% > > > >[...] > > > >Stefan > > > >-- > >coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. > > Tel.: +49 761 7668825 ? Fax: +49 761 7664613 > >Email: info at coresystems.de ? http://www.coresystems.de/ > > > >-- > >linuxbios mailing list > >linuxbios at linuxbios.org > >http://www.openbios.org/mailman/listinfo/linuxbios > -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From rminnich at lanl.gov Fri Oct 6 17:44:15 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 09:44:15 -0600 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM In-Reply-To: References: Message-ID: <452679CF.8090605@lanl.gov> have not looked at this much buy why not make a rom stream in src/stream that is xmodem? That was the intent of that code. i.e. your comment on serial stream is correct. thanks ron From svn at openbios.org Fri Oct 6 18:05:14 2006 From: svn at openbios.org (svn at openbios.org) Date: Fri, 06 Oct 2006 18:05:14 +0200 Subject: [LinuxBIOS] r2446 - in trunk/LinuxBIOSv2/src/mainboard: broadcom/blast tyan/s2881 tyan/s2885 tyan/s2891 tyan/s2892 tyan/s2895 Message-ID: Author: yhlu Date: 2006-10-06 18:05:14 +0200 (Fri, 06 Oct 2006) New Revision: 2446 Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout Log: MEMCLK to DDRXXX Modified: trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-05 06:59:56 UTC (rev 2445) +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout 2006-10-06 16:05:14 UTC (rev 2446) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout 2006-10-05 06:59:56 UTC (rev 2445) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cmos.layout 2006-10-06 16:05:14 UTC (rev 2446) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout 2006-10-05 06:59:56 UTC (rev 2445) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cmos.layout 2006-10-06 16:05:14 UTC (rev 2446) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout 2006-10-05 06:59:56 UTC (rev 2445) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cmos.layout 2006-10-06 16:05:14 UTC (rev 2446) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout 2006-10-05 06:59:56 UTC (rev 2445) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cmos.layout 2006-10-06 16:05:14 UTC (rev 2446) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 9 0 off 9 1 87.5% 9 2 75.0% Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout 2006-10-05 06:59:56 UTC (rev 2445) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cmos.layout 2006-10-06 16:05:14 UTC (rev 2446) @@ -78,10 +78,10 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 9 0 off 9 1 87.5% 9 2 75.0% From stepan at coresystems.de Fri Oct 6 18:05:29 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 18:05:29 +0200 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM In-Reply-To: References: Message-ID: <20061006160529.GA11763@coresystems.de> * Ed Swierk [061006 02:42]: > The attached patch adds a new option, CONFIG_XMODEM_ROM_STREAM, that > allows LinuxBIOS to download its payload from the console via the > XMODEM file transfer protocol. > > This is handy if you want to try out a payload that's too big to fit > into ROM, and you haven't yet gotten IDE or USB devices to work. > I chose to hook this into the ROM stream code so it can take advantage > of the usual compression methods, but one could imagine moving it to a > separate "serial stream" mechanism. Moving it into a "serial stream" (which would need to use compression, too) would be a good idea I suppose. the rom stream is kind of crowded already.. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Fri Oct 6 18:06:14 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 18:06:14 +0200 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM In-Reply-To: References: Message-ID: <20061006160614.GB11763@coresystems.de> * Ed Swierk [061006 02:42]: > I chose to hook this into the ROM stream code so it can take advantage > of the usual compression methods, but one could imagine moving it to a > separate "serial stream" mechanism. > > Comments are welcome. I forgot to say: Very cool idea! We talked about something very similar on the LinuxBIOS symposium for v3 Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From yinghai.lu at amd.com Fri Oct 6 18:05:27 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Fri, 6 Oct 2006 09:05:27 -0700 Subject: [LinuxBIOS] r2442 - in trunk/LinuxBIOSv2: src/mainboard/broadcom/blast src/mainboard/tyan/s2881 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 targets/tyan/s2895 Message-ID: <5986589C150B2F49A46483AC44C7BCA412D669@ssvlexmb2.amd.com> Done. -----Original Message----- From: linuxbios-bounces at linuxbios.org [mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Stefan Reinauer Sent: Friday, October 06, 2006 8:12 AM To: yhlu Cc: linuxbios at linuxbios.org Subject: Re: [LinuxBIOS] r2442 - in trunk/LinuxBIOSv2: src/mainboard/broadcom/blast src/mainboard/tyan/s2881 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 targets/tyan/s2895 * yhlu [061005 17:50]: > sorry, that is only for several MBs with get_bus_conf. I overwrote the > whole dirs for 6 tyan MB and Blast. these cmos.layout should be backed > to DDRXXX etc. Can you do that please? > > On 10/5/06, Stefan Reinauer wrote: > >Yinghai, why are you backing out my patches? > > > >Is this just sleazyness while merging the trees? > > > >I think we should go back to 2434 and start reviewing all of what gets > >checked in. > > > >* svn at openbios.org [061005 01:57]: > >> --- trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout > >2006-10-04 23:09:09 UTC (rev 2441) > >> +++ trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cmos.layout > >2006-10-04 23:57:49 UTC (rev 2442) > >> @@ -78,10 +78,10 @@ > >> 7 9 Fallback_HDD > >> 7 10 Fallback_Floppy > >> #7 3 ROM > >> -8 0 DDR400 > >> -8 1 DDR333 > >> -8 2 DDR266 > >> -8 3 DDR200 > >> +8 0 200Mhz > >> +8 1 166Mhz > >> +8 2 133Mhz > >> +8 3 100Mhz > >> 9 0 off > >> 9 1 87.5% > >> 9 2 75.0% > > > >[...] > > > >Stefan > > > >-- > >coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. > > Tel.: +49 761 7668825 * Fax: +49 761 7664613 > >Email: info at coresystems.de * http://www.coresystems.de/ > > > >-- > >linuxbios mailing list > >linuxbios at linuxbios.org > >http://www.openbios.org/mailman/listinfo/linuxbios > -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info at coresystems.de * http://www.coresystems.de/ -- linuxbios mailing list linuxbios at linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios From stepan at coresystems.de Fri Oct 6 18:07:56 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 18:07:56 +0200 Subject: [LinuxBIOS] r2442 - in trunk/LinuxBIOSv2: src/mainboard/broadcom/blast src/mainboard/tyan/s2881 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 targets/tyan/s2895 In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D669@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D669@ssvlexmb2.amd.com> Message-ID: <20061006160756.GA13181@coresystems.de> * Lu, Yinghai [061006 18:05]: > Done. Thank you! -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From yinghai.lu at amd.com Fri Oct 6 18:09:54 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Fri, 6 Oct 2006 09:09:54 -0700 Subject: [LinuxBIOS] FW: rev F support code Message-ID: <5986589C150B2F49A46483AC44C7BCA412D66A@ssvlexmb2.amd.com> Actually it is some problem with abuild. Maybe we need to create Config-abuild.lb for all. Some MBs (Tyan s2895, Serengeti_*) are using normal+fallback+failover... And some MB only use Fallback. YH -----Original Message----- From: Stefan Reinauer [mailto:stepan at coresystems.de] Sent: Friday, October 06, 2006 8:12 AM To: Ronald G Minnich Cc: Lu, Yinghai; linuxbios at linuxbios.org Subject: Re: [LinuxBIOS] FW: rev F support code * Ronald G Minnich [061006 16:58]: > Lu, Yinghai wrote: > >http://www.openbios.org/viewcvs/trunk/LinuxBIOSv2/src/mainboard/emulati o > >n/qemu-i386/Config.lb?r1=2127&r2=2402 > > > >Ron modified. > > > > oh gosh, what did I do now? everything ok with this one. we want to concentrate on getting things right in v3 rather than fixing linker magic in v2 -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info at coresystems.de * http://www.coresystems.de/ From uwe at hermann-uwe.de Fri Oct 6 19:47:46 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 6 Oct 2006 19:47:46 +0200 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian Message-ID: <20061006174746.GA14977@greenwood> Hi, I just wanted to let you all know that amideco, awardeco, and phnxdeco by Anton Borisov have entered Debian unstable yesterday. I've prepared the packages quite a while ago, but it took rather long until they were approved and entered the Debian archive. So anyways, if you're running unstable you can now simply 'apt-get install amideco' etc. Thanks Anton for agreeing to license the code under the GPL (parts of it under the LGPL)! Cheers, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Fri Oct 6 19:52:49 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 6 Oct 2006 19:52:49 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <45266EF5.8070207@lanl.gov> References: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> <20061005090753.GA27466@greenwood> <45266EF5.8070207@lanl.gov> Message-ID: <20061006175249.GB14977@greenwood> Hi, On Fri, Oct 06, 2006 at 08:57:57AM -0600, Ronald G Minnich wrote: > you can include it by reference, see drivers/net: > > Copyright 1993 United States Government as represented by the > Director, > National Security Agency. This software may only be used and > distributed > according to the terms of the GNU General Public License as > modified by SRC, > incorporated herein by reference. > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > The key part > > if it's good enough for the NSA ... Hm, I don't really understand what the issue is here. I've never seen this "incorporated herein by reference" being used, but I guess it's not better or worse than a single line such as This code is distributed without warranty under the GPL v2 (see COPYING) which we have in the code already, in a few places. IMHO the clearest and most common header is the full 10-line or so version I posted. Disk space is cheap, cut'n'pasting is fast, so I don't see a reason to not use it... Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Oct 6 19:59:44 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Oct 2006 19:59:44 +0200 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <20061006174746.GA14977@greenwood> References: <20061006174746.GA14977@greenwood> Message-ID: <45269990.2090708@gmx.net> Uwe Hermann wrote: > I just wanted to let you all know that amideco, awardeco, and phnxdeco > by Anton Borisov have entered Debian unstable yesterday. > I've prepared the packages quite a while ago, but it took rather long > until they were approved and entered the Debian archive. Is there any interest in getting these included into openSUSE? Regards, Carl-Daniel -- http://www.hailfinger.org/ From uwe at hermann-uwe.de Fri Oct 6 20:01:16 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 6 Oct 2006 20:01:16 +0200 Subject: [LinuxBIOS] indent Message-ID: <20061006180116.GC14977@greenwood> Hi, out of curiosity I tried running indent on the whole source tree, and then running abuild to see whether things break. Short answer: they do. I used this???little script to indent the code: for f in `find . -name '*.[ch]'`; do indent -kr -i8 -ts8 -sob -l80 -ss -ncs $f done abuild fails because some code will be broken in the process, and some code will still work but look ugly. There are workarounds though, you can enclose paragraphs which should not be touched by indent as follows: /* *INDENT-OFF* */ /* *INDENT-ON* */ I suggest we should agree on some set of parameters for indent, add INDENT-OFF/INDENT-ON to the code where appropriate and then, as soon as abuild doesn't complain anymore, checkin the indented code. New checkins which don't conform to the coding style (and other guidelines which may apply) should not be allowed from that point on. Comments? Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Fri Oct 6 20:06:19 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 6 Oct 2006 20:06:19 +0200 Subject: [LinuxBIOS] Pending patches. Message-ID: <20061006180619.GD14977@greenwood> Hi, just a quick reminder for unapplied patches which probably got overlooked (what was the decision regarding a bug tracker? use the current one, install a new one, don't use any?). http://www.linuxbios.org/pipermail/linuxbios/2006-October/015978.html http://www.linuxbios.org/pipermail/linuxbios/2006-September/015968.html http://www.linuxbios.org/pipermail/linuxbios/2006-September/015648.html HTH, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From stepan at coresystems.de Fri Oct 6 20:07:47 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 20:07:47 +0200 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <45269990.2090708@gmx.net> References: <20061006174746.GA14977@greenwood> <45269990.2090708@gmx.net> Message-ID: <20061006180747.GA29552@coresystems.de> * Carl-Daniel Hailfinger [061006 19:59]: > Uwe Hermann wrote: > > I just wanted to let you all know that amideco, awardeco, and phnxdeco > > by Anton Borisov have entered Debian unstable yesterday. > > I've prepared the packages quite a while ago, but it took rather long > > until they were approved and entered the Debian archive. > > Is there any interest in getting these included into openSUSE? Yes! Are you planning to do packages? -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From c-d.hailfinger.devel.2006 at gmx.net Fri Oct 6 20:18:50 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Oct 2006 20:18:50 +0200 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <20061006180747.GA29552@coresystems.de> References: <20061006174746.GA14977@greenwood> <45269990.2090708@gmx.net> <20061006180747.GA29552@coresystems.de> Message-ID: <45269E0A.8090606@gmx.net> Stefan Reinauer wrote: > * Carl-Daniel Hailfinger [061006 19:59]: >> Uwe Hermann wrote: >>> I just wanted to let you all know that amideco, awardeco, and phnxdeco >>> by Anton Borisov have entered Debian unstable yesterday. >>> I've prepared the packages quite a while ago, but it took rather long >>> until they were approved and entered the Debian archive. >> Is there any interest in getting these included into openSUSE? > > Yes! Are you planning to do packages? Will take a look at creating such packages, but not before end of October. If somebody else has time to do it, I'd appreciate it. Besides that, creating a flashrom package would probably complete the offering we have and probably also give people the chance to conveniently flash their BIOSes from Linux. (That might give them some additional interest in helping us out with testing and coding.) Regards, Carl-Daniel -- http://www.hailfinger.org/ From rminnich at lanl.gov Fri Oct 6 20:25:43 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 12:25:43 -0600 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <20061006175249.GB14977@greenwood> References: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> <20061005090753.GA27466@greenwood> <45266EF5.8070207@lanl.gov> <20061006175249.GB14977@greenwood> Message-ID: <45269FA7.3040202@lanl.gov> Uwe Hermann wrote: > Disk space is cheap, cut'n'pasting is fast, so I don't see a reason to > not use it... good point. ron From rminnich at lanl.gov Fri Oct 6 20:28:38 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 12:28:38 -0600 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <20061006174746.GA14977@greenwood> References: <20061006174746.GA14977@greenwood> Message-ID: <4526A056.1060406@lanl.gov> Uwe Hermann wrote: > Hi, > > I just wanted to let you all know that amideco, awardeco, and phnxdeco > by Anton Borisov have entered Debian unstable yesterday. > I've prepared the packages quite a while ago, but it took rather long > until they were approved and entered the Debian archive. > > So anyways, if you're running unstable you can now simply > 'apt-get install amideco' etc. > > Thanks Anton for agreeing to license the code under the GPL (parts of it > under the LGPL)! > > > Cheers, Uwe. > can we put those in linuxbios util too? ron From rminnich at lanl.gov Fri Oct 6 20:29:46 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 12:29:46 -0600 Subject: [LinuxBIOS] indent In-Reply-To: <20061006180116.GC14977@greenwood> References: <20061006180116.GC14977@greenwood> Message-ID: <4526A09A.7060304@lanl.gov> Uwe Hermann wrote: > > New checkins which don't conform to the coding style (and other > guidelines which may apply) should not be allowed from that point on. > > Comments? I like it but what on earth is indent breaking? I don't like the idea of special comments. What's going on? thanks! ron From c-d.hailfinger.devel.2006 at gmx.net Fri Oct 6 20:50:25 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Oct 2006 20:50:25 +0200 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <4526A056.1060406@lanl.gov> References: <20061006174746.GA14977@greenwood> <4526A056.1060406@lanl.gov> Message-ID: <4526A571.6070707@gmx.net> Ronald G Minnich wrote: > Uwe Hermann wrote: >> Hi, >> >> I just wanted to let you all know that amideco, awardeco, and phnxdeco >> by Anton Borisov have entered Debian unstable yesterday. >> > can we put those in linuxbios util too? Why? Decompressing factory BIOS is not our main goal. It may be convenient to get the VGA BIOS from some factory BIOS in this way, but I hope we won't have to suck in loads of code from other projects for that. buildrom is already able to fetch additional packages from the net, why not reuse that functionality? Regards, Carl-Daniel -- http://www.hailfinger.org/ From stepan at coresystems.de Fri Oct 6 20:56:30 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 20:56:30 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <4526A09A.7060304@lanl.gov> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> Message-ID: <20061006185630.GA2964@coresystems.de> * Ronald G Minnich [061006 20:29]: > Uwe Hermann wrote: > > > > > New checkins which don't conform to the coding style (and other > > guidelines which may apply) should not be allowed from that point on. > > > > Comments? > > I like it but what on earth is indent breaking? I don't like the idea > of special comments. What's going on? Can we call this manually and fix the few things up before checkin? Also I am not sure if we really want to break at 80 columns, even though we really should ;-) -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From rminnich at lanl.gov Fri Oct 6 20:52:47 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 12:52:47 -0600 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <4526A571.6070707@gmx.net> References: <20061006174746.GA14977@greenwood> <4526A056.1060406@lanl.gov> <4526A571.6070707@gmx.net> Message-ID: <4526A5FF.5070601@lanl.gov> Carl-Daniel Hailfinger wrote: > Why? Decompressing factory BIOS is not our main goal. It may be convenient > to get the VGA BIOS from some factory BIOS in this way, but I hope we > won't have to suck in loads of code from other projects for that. Well, we do. The util directory is intended to be a set of handy utiltities that may be needed to build a bios. The only way people can get VGA bios today is via these tools. We don't have redistribution rights. I am happy these utils are in debian, but at the same time, I don't like the idea that we have to tell people to get debian to get a utility they need. BTW, one conclusion of the linuxbios summit this week was that we need to get permission from the companies to put their VGA bios on our web site, and/or get redistribution permission. Is someone willing to do this? Contact those vendors and see about redistribution permission? thanks ron From stepan at coresystems.de Fri Oct 6 21:11:23 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 21:11:23 +0200 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <4526A571.6070707@gmx.net> References: <20061006174746.GA14977@greenwood> <4526A056.1060406@lanl.gov> <4526A571.6070707@gmx.net> Message-ID: <20061006191123.GA3449@coresystems.de> * Carl-Daniel Hailfinger [061006 20:50]: > Why? Decompressing factory BIOS is not our main goal. It may be convenient > to get the VGA BIOS from some factory BIOS in this way, but I hope we > won't have to suck in loads of code from other projects for that. > buildrom is already able to fetch additional packages from the net, > why not reuse that functionality? yeah, buildrom would do a great job on that... the idea is really cool. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Fri Oct 6 21:26:04 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 21:26:04 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <45269FA7.3040202@lanl.gov> References: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> <20061005090753.GA27466@greenwood> <45266EF5.8070207@lanl.gov> <20061006175249.GB14977@greenwood> <45269FA7.3040202@lanl.gov> Message-ID: <20061006192604.GC7015@coresystems.de> * Ronald G Minnich [061006 20:25]: > Uwe Hermann wrote: > > > Disk space is cheap, cut'n'pasting is fast, so I don't see a reason to > > not use it... > > good point. Yes. I suggest we start putting in the patches as soon as someone comes up with them ;-) Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Fri Oct 6 21:29:44 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 6 Oct 2006 21:29:44 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D66A@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D66A@ssvlexmb2.amd.com> Message-ID: <20061006192944.GD7015@coresystems.de> * Lu, Yinghai [061006 18:09]: > Actually it is some problem with abuild. Maybe we need to create > Config-abuild.lb for all. Hm. This sounds like the lowest-effort solution, right? We dont want to become ueberartistic here, and instead try to fix things in the upcoming v3 without any linker magic. > Some MBs (Tyan s2895, Serengeti_*) are using normal+fallback+failover... So we want Config-abuild for those > And some MB only use Fallback. and for those as well? Or unify all boards? (or is that an illusion?) BTW: Config-abuild.lb should say payload PAYLOAD so that abuild can choose the payload during build time and replace it. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From ward at gnu.org Fri Oct 6 21:48:19 2006 From: ward at gnu.org (Ward Vandewege) Date: Fri, 6 Oct 2006 15:48:19 -0400 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <4526A5FF.5070601@lanl.gov> References: <20061006174746.GA14977@greenwood> <4526A056.1060406@lanl.gov> <4526A571.6070707@gmx.net> <4526A5FF.5070601@lanl.gov> Message-ID: <20061006194819.GA15305@countzero.vandewege.net> On Fri, Oct 06, 2006 at 12:52:47PM -0600, Ronald G Minnich wrote: > Carl-Daniel Hailfinger wrote: > > > Why? Decompressing factory BIOS is not our main goal. It may be convenient > > to get the VGA BIOS from some factory BIOS in this way, but I hope we > > won't have to suck in loads of code from other projects for that. > > > Well, we do. The util directory is intended to be a set of handy > utiltities that may be needed to build a bios. The only way people can > get VGA bios today is via these tools. We don't have redistribution rights. > > I am happy these utils are in debian, but at the same time, I don't like > the idea that we have to tell people to get debian to get a utility they > need. Err - for the record; the utilities are also downloadable as a tarball, the links are on the Wiki, see the 'How to retrieve a good video bios' on the FAQ page. Thanks, Ward. From rminnich at lanl.gov Fri Oct 6 21:45:11 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 13:45:11 -0600 Subject: [LinuxBIOS] amideco, awardeco, phnxdeco now in Debian In-Reply-To: <20061006194819.GA15305@countzero.vandewege.net> References: <20061006174746.GA14977@greenwood> <4526A056.1060406@lanl.gov> <4526A571.6070707@gmx.net> <4526A5FF.5070601@lanl.gov> <20061006194819.GA15305@countzero.vandewege.net> Message-ID: <4526B247.40002@lanl.gov> Ward Vandewege wrote: > Err - for the record; the utilities are also downloadable as a tarball, the > links are on the Wiki, see the 'How to retrieve a good video bios' on the FAQ > page. yeah, true but ... so why is it a problem to put them in util? ron From yinghai.lu at amd.com Fri Oct 6 21:53:54 2006 From: yinghai.lu at amd.com (Lu, Yinghai) Date: Fri, 6 Oct 2006 12:53:54 -0700 Subject: [LinuxBIOS] V3 Message-ID: <5986589C150B2F49A46483AC44C7BCA412D66B@ssvlexmb2.amd.com> You are talking about V3 several times. What is main feature for V3? Kconfig? YH From rminnich at lanl.gov Fri Oct 6 22:33:12 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 14:33:12 -0600 Subject: [LinuxBIOS] V3 In-Reply-To: <5986589C150B2F49A46483AC44C7BCA412D66B@ssvlexmb2.amd.com> References: <5986589C150B2F49A46483AC44C7BCA412D66B@ssvlexmb2.amd.com> Message-ID: <4526BD88.706@lanl.gov> Lu, Yinghai wrote: > You are talking about V3 several times. > > What is main feature for V3? Kconfig? > > YH > > read that document I sent :-) ron From rminnich at lanl.gov Fri Oct 6 22:41:37 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 14:41:37 -0600 Subject: [LinuxBIOS] well, a start Message-ID: <4526BF81.8070102@lanl.gov> here is where I need josiah :-) oh well will stumble on ... ron [rminnich at q src]$ make xconfig make[1]: Nothing to be done for `__build'. CHECK qt HOSTCC scripts/kconfig/conf.o /bin/sh: scripts/basic/fixdep: No such file or directory make[1]: *** [scripts/kconfig/ From segher at kernel.crashing.org Fri Oct 6 23:39:32 2006 From: segher at kernel.crashing.org (Segher Boessenkool) Date: Fri, 6 Oct 2006 23:39:32 +0200 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <20061006175249.GB14977@greenwood> References: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> <20061005090753.GA27466@greenwood> <45266EF5.8070207@lanl.gov> <20061006175249.GB14977@greenwood> Message-ID: <94DAC7FA-C49D-4D21-B14F-32C74181A2C0@kernel.crashing.org> > IMHO the clearest and most common header is the full 10-line or so > version I posted. > > Disk space is cheap, cut'n'pasting is fast, so I don't see a reason to > not use it... Just make sure you look at the newest version before you cut'n'paste it to lots of files (hint: the FSF moved offices some time ago). Segher From stuge-linuxbios at cdy.org Sat Oct 7 01:20:20 2006 From: stuge-linuxbios at cdy.org (Peter Stuge) Date: Sat, 7 Oct 2006 01:20:20 +0200 Subject: [LinuxBIOS] Slides from my talk Message-ID: <20061006232020.13042.qmail@cdy.org> http://stuge.se/lb.eu/ //Peter From eswierk at arastra.com Sat Oct 7 01:45:16 2006 From: eswierk at arastra.com (Ed Swierk) Date: Fri, 6 Oct 2006 16:45:16 -0700 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM In-Reply-To: <20061006160529.GA11763@coresystems.de> References: <20061006160529.GA11763@coresystems.de> Message-ID: Here's a new patch, hopefully addressing most of the feedback received so far. I'm not thrilled with the amount of overlap between rom_stream.c and serial_stream.c, but I tried to clean things up a bit in the latter. If folks are happy with the changes, I can apply them to rom_stream.c in another patch. Another issue is that the various CONFIG_COMPRESSED_ROM_STREAM options are now sort of misnamed, as they apply to serial streams as well. This can be addressed separately as well. --Ed -------------- next part -------------- A non-text attachment was scrubbed... Name: linuxbios-serial-stream.patch Type: text/x-patch Size: 10626 bytes Desc: not available URL: From svn at openbios.org Sat Oct 7 02:13:24 2006 From: svn at openbios.org (svn at openbios.org) Date: Sat, 07 Oct 2006 02:13:24 +0200 Subject: [LinuxBIOS] r2447 - in trunk/LinuxBIOSv2/src: config lib stream Message-ID: Author: stepan Date: 2006-10-07 02:13:24 +0200 (Sat, 07 Oct 2006) New Revision: 2447 Added: trunk/LinuxBIOSv2/src/lib/xmodem.c trunk/LinuxBIOSv2/src/stream/serial_stream.c Modified: trunk/LinuxBIOSv2/src/config/Options.lb trunk/LinuxBIOSv2/src/lib/uart8250.c trunk/LinuxBIOSv2/src/stream/Config.lb Log: Add serial stream payload support from Ed Swierk X-Signed-Off-By: Stefan Reinauer Modified: trunk/LinuxBIOSv2/src/config/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/config/Options.lb 2006-10-06 16:05:14 UTC (rev 2446) +++ trunk/LinuxBIOSv2/src/config/Options.lb 2006-10-07 00:13:24 UTC (rev 2447) @@ -629,6 +629,11 @@ export always comment "boot image is already compressed" end +define CONFIG_SERIAL_STREAM + default 0 + export always + comment "Download boot image from serial port" +end define CONFIG_FS_STREAM default 0 export always Modified: trunk/LinuxBIOSv2/src/lib/uart8250.c =================================================================== --- trunk/LinuxBIOSv2/src/lib/uart8250.c 2006-10-06 16:05:14 UTC (rev 2446) +++ trunk/LinuxBIOSv2/src/lib/uart8250.c 2006-10-07 00:13:24 UTC (rev 2447) @@ -64,6 +64,8 @@ outb(0x0, base_port + UART_IER); /* enable fifo's */ outb(0x01, base_port + UART_FCR); + /* assert DTR and RTS so the other end is happy */ + outb(0x03, base_port + UART_MCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ outb(0x80 | lcs, base_port + UART_LCR); outb(divisor & 0xFF, base_port + UART_DLL); Added: trunk/LinuxBIOSv2/src/lib/xmodem.c =================================================================== --- trunk/LinuxBIOSv2/src/lib/xmodem.c (rev 0) +++ trunk/LinuxBIOSv2/src/lib/xmodem.c 2006-10-07 00:13:24 UTC (rev 2447) @@ -0,0 +1,207 @@ +/* + Copyright 2006 Arastra, Inc. + Copyright 2001, 2002 Georges Menie (www.menie.org) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include + +extern void uart8250_tx_byte(unsigned, unsigned char); +extern int uart8250_can_rx_byte(unsigned); +extern unsigned char uart8250_rx_byte(unsigned); + +static int _inbyte(int msec) +{ + while (!uart8250_can_rx_byte(TTYS0_BASE)) { + udelay(1000); + if (msec-- <= 0) + return -1; + } + return uart8250_rx_byte(TTYS0_BASE); +} + +static void _outbyte(unsigned char c) +{ + uart8250_tx_byte(TTYS0_BASE, c); +} + +/* CRC16 implementation acording to CCITT standards */ + +static const unsigned short crc16tab[256]= { + 0x0000,0x1021,0x2042,0x3063,0x4084,0x50a5,0x60c6,0x70e7, + 0x8108,0x9129,0xa14a,0xb16b,0xc18c,0xd1ad,0xe1ce,0xf1ef, + 0x1231,0x0210,0x3273,0x2252,0x52b5,0x4294,0x72f7,0x62d6, + 0x9339,0x8318,0xb37b,0xa35a,0xd3bd,0xc39c,0xf3ff,0xe3de, + 0x2462,0x3443,0x0420,0x1401,0x64e6,0x74c7,0x44a4,0x5485, + 0xa56a,0xb54b,0x8528,0x9509,0xe5ee,0xf5cf,0xc5ac,0xd58d, + 0x3653,0x2672,0x1611,0x0630,0x76d7,0x66f6,0x5695,0x46b4, + 0xb75b,0xa77a,0x9719,0x8738,0xf7df,0xe7fe,0xd79d,0xc7bc, + 0x48c4,0x58e5,0x6886,0x78a7,0x0840,0x1861,0x2802,0x3823, + 0xc9cc,0xd9ed,0xe98e,0xf9af,0x8948,0x9969,0xa90a,0xb92b, + 0x5af5,0x4ad4,0x7ab7,0x6a96,0x1a71,0x0a50,0x3a33,0x2a12, + 0xdbfd,0xcbdc,0xfbbf,0xeb9e,0x9b79,0x8b58,0xbb3b,0xab1a, + 0x6ca6,0x7c87,0x4ce4,0x5cc5,0x2c22,0x3c03,0x0c60,0x1c41, + 0xedae,0xfd8f,0xcdec,0xddcd,0xad2a,0xbd0b,0x8d68,0x9d49, + 0x7e97,0x6eb6,0x5ed5,0x4ef4,0x3e13,0x2e32,0x1e51,0x0e70, + 0xff9f,0xefbe,0xdfdd,0xcffc,0xbf1b,0xaf3a,0x9f59,0x8f78, + 0x9188,0x81a9,0xb1ca,0xa1eb,0xd10c,0xc12d,0xf14e,0xe16f, + 0x1080,0x00a1,0x30c2,0x20e3,0x5004,0x4025,0x7046,0x6067, + 0x83b9,0x9398,0xa3fb,0xb3da,0xc33d,0xd31c,0xe37f,0xf35e, + 0x02b1,0x1290,0x22f3,0x32d2,0x4235,0x5214,0x6277,0x7256, + 0xb5ea,0xa5cb,0x95a8,0x8589,0xf56e,0xe54f,0xd52c,0xc50d, + 0x34e2,0x24c3,0x14a0,0x0481,0x7466,0x6447,0x5424,0x4405, + 0xa7db,0xb7fa,0x8799,0x97b8,0xe75f,0xf77e,0xc71d,0xd73c, + 0x26d3,0x36f2,0x0691,0x16b0,0x6657,0x7676,0x4615,0x5634, + 0xd94c,0xc96d,0xf90e,0xe92f,0x99c8,0x89e9,0xb98a,0xa9ab, + 0x5844,0x4865,0x7806,0x6827,0x18c0,0x08e1,0x3882,0x28a3, + 0xcb7d,0xdb5c,0xeb3f,0xfb1e,0x8bf9,0x9bd8,0xabbb,0xbb9a, + 0x4a75,0x5a54,0x6a37,0x7a16,0x0af1,0x1ad0,0x2ab3,0x3a92, + 0xfd2e,0xed0f,0xdd6c,0xcd4d,0xbdaa,0xad8b,0x9de8,0x8dc9, + 0x7c26,0x6c07,0x5c64,0x4c45,0x3ca2,0x2c83,0x1ce0,0x0cc1, + 0xef1f,0xff3e,0xcf5d,0xdf7c,0xaf9b,0xbfba,0x8fd9,0x9ff8, + 0x6e17,0x7e36,0x4e55,0x5e74,0x2e93,0x3eb2,0x0ed1,0x1ef0 +}; + +static unsigned short crc16_ccitt(const void *buf, int len) +{ + register int counter; + register unsigned short crc = 0; + for( counter = 0; counter < len; counter++) + crc = (crc<<8) ^ crc16tab[((crc>>8) ^ *(char *)buf++)&0x00FF]; + return crc; +} + +#define SOH 0x01 +#define STX 0x02 +#define EOT 0x04 +#define ACK 0x06 +#define NAK 0x15 +#define CAN 0x18 +#define CTRLZ 0x1A + +#define DLY_1S 1000 +#define MAXRETRANS 25 + +static int check(int crc, const unsigned char *buf, int sz) +{ + if (crc) { + unsigned short crc = crc16_ccitt(buf, sz); + unsigned short tcrc = (buf[sz]<<8)+buf[sz+1]; + if (crc == tcrc) + return 1; + } + else { + int i; + unsigned char cks = 0; + for (i = 0; i < sz; ++i) { + cks += buf[i]; + } + if (cks == buf[sz]) + return 1; + } + + return 0; +} + +static void flushinput(void) +{ + while (_inbyte(((DLY_1S)*3)>>1) >= 0) + ; +} + +int xmodemReceive(unsigned char *dest, int destsz) +{ + unsigned char xbuff[1030]; /* 1024 for XModem 1k + 3 head chars + 2 crc + nul */ + unsigned char *p; + int bufsz, crc = 0; + unsigned char trychar = 'C'; + unsigned char packetno = 1; + int i, c, len = 0; + int retry, retrans = MAXRETRANS; + + for(;;) { + for( retry = 0; retry < 16; ++retry) { + if (trychar) _outbyte(trychar); + if ((c = _inbyte((DLY_1S)<<1)) >= 0) { + switch (c) { + case SOH: + bufsz = 128; + goto start_recv; + case STX: + bufsz = 1024; + goto start_recv; + case EOT: + flushinput(); + _outbyte(ACK); + return len; /* normal end */ + case CAN: + if ((c = _inbyte(DLY_1S)) == CAN) { + flushinput(); + _outbyte(ACK); + return -1; /* canceled by remote */ + } + break; + default: + break; + } + } + } + if (trychar == 'C') { trychar = NAK; continue; } + flushinput(); + _outbyte(CAN); + _outbyte(CAN); + _outbyte(CAN); + return -2; /* sync error */ + + start_recv: + if (trychar == 'C') crc = 1; + trychar = 0; + p = xbuff; + *p++ = c; + for (i = 0; i < (bufsz+(crc?1:0)+3); ++i) { + if ((c = _inbyte(DLY_1S)) < 0) goto reject; + *p++ = c; + } + + if (xbuff[1] == (unsigned char)(~xbuff[2]) && + (xbuff[1] == packetno || xbuff[1] == (unsigned char)packetno-1) && + check(crc, &xbuff[3], bufsz)) { + if (xbuff[1] == packetno) { + register int count = destsz - len; + if (count > bufsz) count = bufsz; + if (count > 0) { + memcpy (&dest[len], &xbuff[3], count); + len += count; + } + ++packetno; + retrans = MAXRETRANS+1; + } + if (--retrans <= 0) { + flushinput(); + _outbyte(CAN); + _outbyte(CAN); + _outbyte(CAN); + return -3; /* too many retry error */ + } + _outbyte(ACK); + continue; + } + reject: + flushinput(); + _outbyte(NAK); + } +} Modified: trunk/LinuxBIOSv2/src/stream/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/stream/Config.lb 2006-10-06 16:05:14 UTC (rev 2446) +++ trunk/LinuxBIOSv2/src/stream/Config.lb 2006-10-07 00:13:24 UTC (rev 2447) @@ -2,6 +2,7 @@ uses CONFIG_IDE_STREAM uses CONFIG_FS_STREAM uses CONFIG_IDE +uses CONFIG_SERIAL_STREAM if CONFIG_ROM_STREAM object rom_stream.o @@ -16,3 +17,7 @@ object fs_stream.o dir fs end + +if CONFIG_SERIAL_STREAM + object serial_stream.o +end Added: trunk/LinuxBIOSv2/src/stream/serial_stream.c =================================================================== --- trunk/LinuxBIOSv2/src/stream/serial_stream.c (rev 0) +++ trunk/LinuxBIOSv2/src/stream/serial_stream.c 2006-10-07 00:13:24 UTC (rev 2447) @@ -0,0 +1,92 @@ +#include +#include +#include +#include +#include + +/* if they set the precompressed rom stream, they better have set a type */ +#if CONFIG_PRECOMPRESSED_ROM_STREAM && ((!CONFIG_COMPRESSED_ROM_STREAM) && (!CONFIG_COMPRESSED_ROM_STREAM_NRV2B) && (!CONFIG_COMPRESSED_ROM_STREAM_LZMA)) +#error "You set CONFIG_PRECOMPRESSED_ROM_STREAM but need to set CONFIG_COMPRESSED_ROM_STREAM (implies NRV2B, deprecated) or CONFIG_COMPRESSED_ROM_STREAM_NRV2B or CONFIG_COMPRESSED_ROM_STREAM_LZMA" +#endif + +#if (CONFIG_COMPRESSED_ROM_STREAM) || (CONFIG_COMPRESSED_ROM_STREAM_NRV2B) +#define HAVE_UNCOMPRESSER 1 +#include "../lib/nrv2b.c" +#endif + +#if (CONFIG_COMPRESSED_ROM_STREAM_LZMA) +#if HAVE_UNCOMPRESSER +#error "You're defining more than one compression type, which is not allowed (of course)" +#endif +#define HAVE_UNCOMPRESSER 1 +#include "../lib/lzma.c" +#endif + +#include "../lib/xmodem.c" + +/* Blocks of RAM for storing stream data */ +static unsigned char *stream_start = (unsigned char *) 0x02000000; +static unsigned char *stream_end; +static unsigned char *temp_start = (unsigned char *) 0x03000000; +static int stream_max_bytes = 0x00800000; + +#if HAVE_UNCOMPRESSER +static unsigned long uncompress(uint8_t *src, uint8_t *dest) +{ +#if (CONFIG_COMPRESSED_ROM_STREAM) || (CONFIG_COMPRESSED_ROM_STREAM_NRV2B) + unsigned long ilen; + return unrv2b(src, dest, &ilen); +#endif +#if (CONFIG_COMPRESSED_ROM_STREAM_LZMA) + return ulzma(src, dest); +#endif +} +#endif + +int stream_init(void) +{ + int len; + + printk_debug("serial_stream: downloading to 0x%08lx; start XMODEM transfer now!\n", temp_start); + if ((len = xmodemReceive(temp_start, stream_max_bytes)) <= 0) { + printk_debug("\nserial_stream: XMODEM transfer failed\n"); + return -1; + } + printk_debug("\nserial_stream: XMODEM transfer complete; %d bytes received\n", len); +#if HAVE_UNCOMPRESSER + printk_debug("serial_stream: uncompressing to 0x%08lx\n", stream_start); + len = uncompress((uint8_t *) temp_start, (uint8_t *) stream_start); + printk_debug("serial_stream: %d bytes uncompressed\n", len); +#else + printk_debug("serial_stream: copying to 0x%08lx\n", stream_start); + memcpy(stream_start, temp_start, len); +#endif + stream_end = stream_start + len - 1; + return 0; +} + +void stream_fini(void) +{ +} + +byte_offset_t stream_skip(byte_offset_t count) +{ + if ((stream_start + count) > stream_end) { + printk_warning("%6d:%s() - overflowed source buffer\n", + __LINE__, __FUNCTION__); + count = 0; + if (stream_start <= stream_end) { + count = (stream_end - stream_start) + 1; + } + } + stream_start += count; + return count; +} + +byte_offset_t stream_read(void *vdest, byte_offset_t count) +{ + unsigned char *old_start = stream_start; + count = stream_skip(count); + memcpy(vdest, old_start, count); + return count; +} From stepan at coresystems.de Sat Oct 7 02:15:18 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 7 Oct 2006 02:15:18 +0200 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM In-Reply-To: References: <20061006160529.GA11763@coresystems.de> Message-ID: <20061007001518.GA16679@coresystems.de> * Ed Swierk [061007 01:45]: > Here's a new patch, hopefully addressing most of the feedback received so > far. looks good, committed. > I'm not thrilled with the amount of overlap between rom_stream.c and > serial_stream.c, but I tried to clean things up a bit in the latter. > If folks are happy with the changes, I can apply them to rom_stream.c > in another patch. please > Another issue is that the various CONFIG_COMPRESSED_ROM_STREAM options > are now sort of misnamed, as they apply to serial streams as well. > This can be addressed separately as well. Yes, it should be CONFIG_COMPRESSED_STREAM instead. But please make sure to change all occurences of it in the tree, too.. great work! -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From svn at openbios.org Sat Oct 7 02:21:13 2006 From: svn at openbios.org (svn at openbios.org) Date: Sat, 07 Oct 2006 02:21:13 +0200 Subject: [LinuxBIOS] r2448 - trunk/LinuxBIOSv2/util/flashrom Message-ID: Author: stepan Date: 2006-10-07 02:21:13 +0200 (Sat, 07 Oct 2006) New Revision: 2448 Modified: trunk/LinuxBIOSv2/util/flashrom/flashchips.c trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c Log: Fix flashrom for sst49lf080a and small print bug, by Roman Kononov . X-Signed-Off-By: Stefan Reinauer Modified: trunk/LinuxBIOSv2/util/flashrom/flashchips.c =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flashchips.c 2006-10-07 00:13:24 UTC (rev 2447) +++ trunk/LinuxBIOSv2/util/flashrom/flashchips.c 2006-10-07 00:21:13 UTC (rev 2448) @@ -67,7 +67,7 @@ {"SST49LF040", SST_ID, SST_49LF040, NULL, 512, 4096, probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF080A", SST_ID, SST_49LF080A, NULL, 1024, 4096, - probe_jedec, erase_chip_jedec, write_49lf040,NULL}, + probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF002A/B", SST_ID, SST_49LF002A, NULL, 256, 16 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub, NULL}, {"SST49LF003A/B", SST_ID, SST_49LF003A, NULL, 384, 64 * 1024, Modified: trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c 2006-10-07 00:13:24 UTC (rev 2447) +++ trunk/LinuxBIOSv2/util/flashrom/sst49lf040.c 2006-10-07 00:21:13 UTC (rev 2448) @@ -1,4 +1,4 @@ -/* sst40lf020.c: driver for SST40LF040 flash models. +/* sst49lf040.c: driver for SST49LF040 flash models. * * * Copyright 2000 Silicon Integrated System Corporation @@ -59,13 +59,12 @@ erase_sector_jedec(bios, i * page_size); /* write to the sector */ - if((i&0xfff)==0xfff) - printf("%04d at address: 0x%08x ", i, i * page_size); + printf("%04d at address: 0x%08x ", i, i * page_size); write_sector_jedec(bios, buf + i * page_size, bios + i * page_size, page_size); - if((i&0xfff)==0xfff) - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); fflush(stdout); } printf("\n"); From svn at openbios.org Sat Oct 7 02:23:52 2006 From: svn at openbios.org (svn at openbios.org) Date: Sat, 07 Oct 2006 02:23:52 +0200 Subject: [LinuxBIOS] r2449 - trunk/LinuxBIOSv2/util/flashrom Message-ID: Author: stepan Date: 2006-10-07 02:23:51 +0200 (Sat, 07 Oct 2006) New Revision: 2449 Modified: trunk/LinuxBIOSv2/util/flashrom/flash_rom.c Log: Tiny patch to show the size of the detected flash part from Uwe Hermann X-Signed-Off-By: Stefan Reinauer Modified: trunk/LinuxBIOSv2/util/flashrom/flash_rom.c =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flash_rom.c 2006-10-07 00:21:13 UTC (rev 2448) +++ trunk/LinuxBIOSv2/util/flashrom/flash_rom.c 2006-10-07 00:23:51 UTC (rev 2449) @@ -298,7 +298,7 @@ exit(1); } - printf("Flash part is %s\n", flash->name); + printf("Flash part is %s (%d KB)\n", flash->name, flash->total_size); if (!filename && !erase_it) { // FIXME: Do we really want this feature implicitly? From stepan at coresystems.de Sat Oct 7 02:27:02 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 7 Oct 2006 02:27:02 +0200 Subject: [LinuxBIOS] flashrom SST49LF080A patch In-Reply-To: <45213C53.2060205@yahoo.com> References: <45213C53.2060205@yahoo.com> Message-ID: <20061007002702.GA27016@coresystems.de> * Roman Kononov [061002 18:20]: > Hello, > > The first patch changes chip erase method from JEDEC Chip Erase to JEDEC Sector Erase for > each sector. See the comment in util/flashrom/sst49lf040.c, line #40. Verified on a real > SST49LF080A chip, for which JEDEC Chip Erase did not work as well. > > The second patch makes printf working [as designed]. Thanks. Applied. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Sat Oct 7 02:33:53 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 7 Oct 2006 02:33:53 +0200 Subject: [LinuxBIOS] Pending patches. In-Reply-To: <20061006180619.GD14977@greenwood> References: <20061006180619.GD14977@greenwood> Message-ID: <20061007003353.GA1161@coresystems.de> * Uwe Hermann [061006 20:06]: > Hi, > > just a quick reminder for unapplied patches which probably got > overlooked (what was the decision regarding a bug tracker? use the current > one, install a new one, don't use any?). > > http://www.linuxbios.org/pipermail/linuxbios/2006-September/015968.html Can we just put /usr/sbin into the path for compilation in this one? This would solve all our problems I suppose. I think latest changes to the tree require redoing parts of the patch -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From uwe at hermann-uwe.de Sat Oct 7 03:19:16 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sat, 7 Oct 2006 03:19:16 +0200 Subject: [LinuxBIOS] flashrom: does writing work on ICH-2 et al? Message-ID: <20061007011915.GA30351@greenwood> Hi, I have problems writing flash chips with flashrom on multiple ICH-x boards, e.g. ICH-2 and ICH-4. The code is pretty much the same for all ICH-x so I guess all of them have the problem(?) Detecting and reading from a chip works fine. Writing _seems_ to work fine (no errors, doesn't abort), but when I try to verify (or just read the chip again) I get the same content as before the write. The hardware itself as well as the flash chip is ok, as I can write the chip using Uniflash. Has anybody successfully written any chip on an ICH-x? Is more code needed to make it work? Motherboard-specific code maybe? Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Sat Oct 7 03:23:12 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sat, 7 Oct 2006 03:23:12 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <20061006185630.GA2964@coresystems.de> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> <20061006185630.GA2964@coresystems.de> Message-ID: <20061007012312.GB30351@greenwood> Hi, On Fri, Oct 06, 2006 at 08:56:30PM +0200, Stefan Reinauer wrote: > Can we call this manually and fix the few things up before checkin? I guess so, but I'd rather temporarily use the INDENT-OFF markers where needed and then remove them. That's less work than manually fixing all the stuff indent changed which it shouldn't have changed. > Also I am not sure if we really want to break at 80 columns, even though > we really should ;-) I'd say we should, at least in most cases. Sometimes that may be not so good; in such cases leave the code as is (IMHO). Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From stepan at coresystems.de Sat Oct 7 03:35:02 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 7 Oct 2006 03:35:02 +0200 Subject: [LinuxBIOS] LinuxBIOS Symposium 2006 - Slides and Photos Message-ID: <20061007013502.GA20982@coresystems.de> Hi all, I've added my slides and photos the LinuxBIOS Symposium page at http://www.linuxbios.org/index.php/LinuxBIOS_Symposium_2006 If any of you has slides or photos left, please upload them or let me know so I can upload them for you.. :-) Have a nice weekend Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From rminnich at lanl.gov Sat Oct 7 04:02:40 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 20:02:40 -0600 Subject: [LinuxBIOS] Pending patches. In-Reply-To: <20061007003353.GA1161@coresystems.de> References: <20061006180619.GD14977@greenwood> <20061007003353.GA1161@coresystems.de> Message-ID: <45270AC0.9080205@lanl.gov> Stefan Reinauer wrote: > * Uwe Hermann [061006 20:06]: > >>Hi, >> >>just a quick reminder for unapplied patches which probably got >>overlooked (what was the decision regarding a bug tracker? use the current >>one, install a new one, don't use any?). >> >>http://www.linuxbios.org/pipermail/linuxbios/2006-September/015968.html > > > Can we just put /usr/sbin into the path for compilation in this one? > This would solve all our problems I suppose. yes, if a tool is not in your PATH, fix the PATH, don't modify the linuxbios build process :-) ron From rminnich at lanl.gov Sat Oct 7 04:26:44 2006 From: rminnich at lanl.gov (Ronald G Minnich) Date: Fri, 06 Oct 2006 20:26:44 -0600 Subject: [LinuxBIOS] FW: rev F support code In-Reply-To: <94DAC7FA-C49D-4D21-B14F-32C74181A2C0@kernel.crashing.org> References: <5986589C150B2F49A46483AC44C7BCA412D651@ssvlexmb2.amd.com> <20061005090753.GA27466@greenwood> <45266EF5.8070207@lanl.gov> <20061006175249.GB14977@greenwood> <94DAC7FA-C49D-4D21-B14F-32C74181A2C0@kernel.crashing.org> Message-ID: <45271064.7080105@lanl.gov> Segher Boessenkool wrote: > Just make sure you look at the newest version before you cut'n'paste > it to lots of files (hint: the FSF moved offices some time ago). I remember now that's why I like 'by reference'. I've had to change it on occasion and it can be a pain. ron From stepan at coresystems.de Sat Oct 7 10:29:40 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 7 Oct 2006 10:29:40 +0200 Subject: [LinuxBIOS] Pending patches. In-Reply-To: <45270AC0.9080205@lanl.gov> References: <20061006180619.GD14977@greenwood> <20061007003353.GA1161@coresystems.de> <45270AC0.9080205@lanl.gov> Message-ID: <20061007082940.GA1103@coresystems.de> * Ronald G Minnich [061007 04:02]: > >Can we just put /usr/sbin into the path for compilation in this one? > >This would solve all our problems I suppose. > > > yes, if a tool is not in your PATH, fix the PATH, don't modify the > linuxbios build process :-) Actually Uwe is trying to fix something I messed up here, because SUSE pack their development utilities in /usr/sbin ;-) His patch does the right thing: removing the fixed paths from iasl. But that will break autobuild. that could easily be fixed not an issue, but it would also break compilation for a couple of people out there. So in addition I was suggesting to do PATH=$PATH:/usr/sbin in the build process so nobody would notice we fixed it ;-) -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From segher at kernel.crashing.org Sat Oct 7 15:26:29 2006 From: segher at kernel.crashing.org (Segher Boessenkool) Date: Sat, 7 Oct 2006 15:26:29 +0200 Subject: [LinuxBIOS] r2447 - in trunk/LinuxBIOSv2/src: config lib stream In-Reply-To: References: Message-ID: > +/* CRC16 implementation acording to CCITT standards */ > + > +static const unsigned short crc16tab[256]= { > + 0x0000,0x1021,0x2042,0x3063,0x4084,0x50a5,0x60c6,0x70e7, This table isn't needed, a UART stream is so slow that you can just as well open-code the CRC algorithm and lose nothing (except for 512 bytes of table :-) ) Segher From uwe at hermann-uwe.de Sat Oct 7 23:30:05 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sat, 7 Oct 2006 23:30:05 +0200 Subject: [LinuxBIOS] PATCH: flashrom support for SST 49LF020A. Message-ID: <20061007213005.GA24632@greenwood> Hi, here's a small patch to add support for the SST 49LF020A to flashrom. I only tested probing and reading the chip, I don't want to test writing, as the chip on my test-board is soldered on. I'm guessing that it should work, though, as it shares most code with some very similar chips. Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- Index: flash.h =================================================================== --- flash.h (Revision 2449) +++ flash.h (Arbeitskopie) @@ -47,6 +47,7 @@ #define SST_39VF020 0xD6 /* SST 39VF020 device */ #define SST_49LF040B 0x50 /* SST 49LF040B device */ #define SST_49LF040 0x51 /* SST 49LF040 device */ +#define SST_49LF020A 0x52 /* SST 49LF020A device */ #define SST_49LF080A 0x5B /* SST 48LF080A device */ #define SST_49LF002A 0x57 /* SST 49LF002A device */ #define SST_49LF003A 0x1B /* SST 49LF003A device */ Index: flashchips.c =================================================================== --- flashchips.c (Revision 2449) +++ flashchips.c (Arbeitskopie) @@ -66,6 +66,8 @@ {"SST49LF040", SST_ID, SST_49LF040, NULL, 512, 4096, probe_jedec, erase_49lf040, write_49lf040,NULL}, + {"SST49LF020A", SST_ID, SST_49LF020A, NULL, 256, 16 * 1024, + probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF080A", SST_ID, SST_49LF080A, NULL, 1024, 4096, probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF002A/B", SST_ID, SST_49LF002A, NULL, 256, 16 * 1024, -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Sat Oct 7 23:31:11 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sat, 7 Oct 2006 23:31:11 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <4526A09A.7060304@lanl.gov> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> Message-ID: <20061007213111.GB24632@greenwood> Hi, On Fri, Oct 06, 2006 at 12:29:46PM -0600, Ronald G Minnich wrote: > I like it but what on earth is indent breaking? I don't like the idea > of special comments. What's going on? One example I noticed: - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), - bus); + dev = + pci_locate_device_on_bus(PCI_ID + (PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8111_ISA), bus); As PCI_ID is a macro breaking it over???multiple lines seems to cause trouble (in this case at least). Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From stuge-linuxbios at cdy.org Sun Oct 8 00:58:41 2006 From: stuge-linuxbios at cdy.org (Peter Stuge) Date: Sun, 8 Oct 2006 00:58:41 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <20061007213111.GB24632@greenwood> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> <20061007213111.GB24632@greenwood> Message-ID: <20061007225842.18465.qmail@cdy.org> On Sat, Oct 07, 2006 at 11:31:11PM +0200, Uwe Hermann wrote: > One example I noticed: > > - dev = pci_locate_device_on_bus( > - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), > - bus); > + dev = > + pci_locate_device_on_bus(PCI_ID > + (PCI_VENDOR_ID_AMD, > + PCI_DEVICE_ID_AMD_8111_ISA), bus); > > As PCI_ID is a macro breaking it over multiple lines seems to cause > trouble (in this case at least). Macro or no, I don't like the above change at all. I think the former is much more readable. //Peter From svn at openbios.org Sun Oct 8 00:59:04 2006 From: svn at openbios.org (svn at openbios.org) Date: Sun, 08 Oct 2006 00:59:04 +0200 Subject: [LinuxBIOS] r2450 - trunk/LinuxBIOSv2/util/flashrom Message-ID: Author: stepan Date: 2006-10-08 00:59:03 +0200 (Sun, 08 Oct 2006) New Revision: 2450 Modified: trunk/LinuxBIOSv2/util/flashrom/flash.h trunk/LinuxBIOSv2/util/flashrom/flashchips.c Log: here's a small patch to add support for the SST 49LF020A to flashrom. by Uwe Hermann X-Signed-Off-By: Stefan Reinauer Modified: trunk/LinuxBIOSv2/util/flashrom/flash.h =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flash.h 2006-10-07 00:23:51 UTC (rev 2449) +++ trunk/LinuxBIOSv2/util/flashrom/flash.h 2006-10-07 22:59:03 UTC (rev 2450) @@ -47,6 +47,7 @@ #define SST_39VF020 0xD6 /* SST 39VF020 device */ #define SST_49LF040B 0x50 /* SST 49LF040B device */ #define SST_49LF040 0x51 /* SST 49LF040 device */ +#define SST_49LF020A 0x52 /* SST 49LF020A device */ #define SST_49LF080A 0x5B /* SST 48LF080A device */ #define SST_49LF002A 0x57 /* SST 49LF002A device */ #define SST_49LF003A 0x1B /* SST 49LF003A device */ Modified: trunk/LinuxBIOSv2/util/flashrom/flashchips.c =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flashchips.c 2006-10-07 00:23:51 UTC (rev 2449) +++ trunk/LinuxBIOSv2/util/flashrom/flashchips.c 2006-10-07 22:59:03 UTC (rev 2450) @@ -66,6 +66,8 @@ {"SST49LF040", SST_ID, SST_49LF040, NULL, 512, 4096, probe_jedec, erase_49lf040, write_49lf040,NULL}, + {"SST49LF020A", SST_ID, SST_49LF020A, NULL, 256, 16 * 1024, + probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF080A", SST_ID, SST_49LF080A, NULL, 1024, 4096, probe_jedec, erase_49lf040, write_49lf040,NULL}, {"SST49LF002A/B", SST_ID, SST_49LF002A, NULL, 256, 16 * 1024, From stepan at coresystems.de Sun Oct 8 01:01:27 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 8 Oct 2006 01:01:27 +0200 Subject: [LinuxBIOS] added support sst29sf020 In-Reply-To: <503ab0210610031754n781297dcle603f0344ad9f639@mail.gmail.com> References: <503ab0210610031754n781297dcle603f0344ad9f639@mail.gmail.com> Message-ID: <20061007230127.GA24747@coresystems.de> * Tyler Pohl [061004 02:54]: > I added support to the flashrom source for the sst29sf020. I though i would > contribute. Source is attached. > > P.S. Good coding of the flashrom thank you. Very easy to modify. Thank you very much Can you please send this as a patch against the latest flashrom version? Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From stepan at coresystems.de Sun Oct 8 01:04:14 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 8 Oct 2006 01:04:14 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <20061007225842.18465.qmail@cdy.org> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> <20061007213111.GB24632@greenwood> <20061007225842.18465.qmail@cdy.org> Message-ID: <20061007230414.GA26176@coresystems.de> * Peter Stuge [061008 00:58]: > > As PCI_ID is a macro breaking it over multiple lines seems to cause > > trouble (in this case at least). > > Macro or no, I don't like the above change at all. I think the former > is much more readable. this is one of the nasty places indeed. but very often indent causes code to be much more readable. Just not sure if we can just run indent and check things on or if this requires a persevering hand job. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From segher at kernel.crashing.org Sun Oct 8 01:52:10 2006 From: segher at kernel.crashing.org (Segher Boessenkool) Date: Sun, 8 Oct 2006 01:52:10 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <20061007230414.GA26176@coresystems.de> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> <20061007213111.GB24632@greenwood> <20061007225842.18465.qmail@cdy.org> <20061007230414.GA26176@coresystems.de> Message-ID: >> Macro or no, I don't like the above change at all. I think the former >> is much more readable. Yah. > this is one of the nasty places indeed. but very often indent causes > code to be much more readable. Just not sure if we can just run indent > and check things on or if this requires a persevering hand job. If you want to run indent at all, do it _once_ (with all the right options! See lindent) and fix up the fallout later, whenever you stumble on it -- that's the least-effort way to go about it. Segher From stepan at coresystems.de Sun Oct 8 13:41:03 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 8 Oct 2006 13:41:03 +0200 Subject: [LinuxBIOS] indent In-Reply-To: References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> <20061007213111.GB24632@greenwood> <20061007225842.18465.qmail@cdy.org> <20061007230414.GA26176@coresystems.de> Message-ID: <20061008114103.GA30719@coresystems.de> * Segher Boessenkool [061008 01:52]: > If you want to run indent at all, do it _once_ (with all the right > options! See lindent) and fix up the fallout later, whenever you > stumble on it -- that's the least-effort way to go about it. some of our specialists send in patches that consist of 50% whitespace changes because they are using broken editors that convert tab to space. question is how to cope with that, especially if those people have commit rights themselfes and dont wait for a review to happen. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From segher at kernel.crashing.org Sun Oct 8 16:24:10 2006 From: segher at kernel.crashing.org (Segher Boessenkool) Date: Sun, 8 Oct 2006 16:24:10 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <20061008114103.GA30719@coresystems.de> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> <20061007213111.GB24632@greenwood> <20061007225842.18465.qmail@cdy.org> <20061007230414.GA26176@coresystems.de> <20061008114103.GA30719@coresystems.de> Message-ID: <5EE7F9E4-9853-492F-BD99-8E377DA42C6D@kernel.crashing.org> >> If you want to run indent at all, do it _once_ (with all the right >> options! See lindent) and fix up the fallout later, whenever you >> stumble on it -- that's the least-effort way to go about it. > > some of our specialists send in patches that consist of 50% whitespace > changes because they are using broken editors that convert tab to > space. > > question is how to cope with that, especially if those people have > commit rights themselfes and dont wait for a review to happen. pre-commit hook, run a regexp that finds the more standard problems, refuse if bad. The Linux kernel source code has some such regexp's for you. But do you really want to completely lock out "bad-looking" whitespace changes? You can't solve social problems using technology; you'll have to change people's habits instead. *Every* patch should be sent to the mailing list for review, it doesn't matter who you are. Segher From paul at astro.gla.ac.uk Sun Oct 8 17:19:10 2006 From: paul at astro.gla.ac.uk (Paul Millar) Date: Sun, 8 Oct 2006 16:19:10 +0100 Subject: [LinuxBIOS] coordinator In-Reply-To: <503ab0210610031408w3429329cg8f779d3b0b9e77a4@mail.gmail.com> References: <503ab0210610031408w3429329cg8f779d3b0b9e77a4@mail.gmail.com> Message-ID: <200610081619.15362.paul@astro.gla.ac.uk> On Tuesday 03 October 2006 22:08, Tyler Pohl wrote: > I'm very interested, I just wouldn't know where to start :) > Could someone point me in a direction. I don't have *too* much time (who does?), but I'd like to help out. Cheers, Paul. -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: From uwe at hermann-uwe.de Sun Oct 8 17:28:32 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sun, 8 Oct 2006 17:28:32 +0200 Subject: [LinuxBIOS] qemu images In-Reply-To: <1159631961.3015.1.camel@iridium.gnat.ca> References: <1159631961.3015.1.camel@iridium.gnat.ca> Message-ID: <20061008152832.GB865@greenwood> Hi, On Sat, Sep 30, 2006 at 09:59:21AM -0600, Nathanael D. Noblet wrote: > I have a semi related question. I see that the OLPC project uses > buildroot to create a root filesystem. I've done the same for a few > projects. I'm wondering though, how they convert the filesystem to a > disk image. I went over the docs on the wiki and used google, and I > don't know how they get a disk image from the filesystems it creates. You mean a way to convert an arbitrary filesystem (with any OS on it, be it Linux, Windows, or whatever) into a QEMU image? That would be very interesting indeed, not only for LinuxBIOS / OLPC. Does anybody know if or how it can be done? Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Sun Oct 8 17:37:08 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sun, 8 Oct 2006 17:37:08 +0200 Subject: [LinuxBIOS] indent In-Reply-To: <5EE7F9E4-9853-492F-BD99-8E377DA42C6D@kernel.crashing.org> References: <20061006180116.GC14977@greenwood> <4526A09A.7060304@lanl.gov> <20061007213111.GB24632@greenwood> <20061007225842.18465.qmail@cdy.org> <20061007230414.GA26176@coresystems.de> <20061008114103.GA30719@coresystems.de> <5EE7F9E4-9853-492F-BD99-8E377DA42C6D@kernel.crashing.org> Message-ID: <20061008153708.GC865@greenwood> Hi, On Sun, Oct 08, 2006 at 04:24:10PM +0200, Segher Boessenkool wrote: > You can't solve social problems using technology; you'll have to > change people's habits instead. *Every* patch should be sent to > the mailing list for review, it doesn't matter who you are. Yep, definately. We should write a wiki page containing some development guidelines ASAP and then point people to it and encourage everyone to follow them. Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Sun Oct 8 17:38:41 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sun, 8 Oct 2006 17:38:41 +0200 Subject: [LinuxBIOS] Pending patches. In-Reply-To: <20061007082940.GA1103@coresystems.de> References: <20061006180619.GD14977@greenwood> <20061007003353.GA1161@coresystems.de> <45270AC0.9080205@lanl.gov> <20061007082940.GA1103@coresystems.de> Message-ID: <20061008153841.GD865@greenwood> Hi, On Sat, Oct 07, 2006 at 10:29:40AM +0200, Stefan Reinauer wrote: > Actually Uwe is trying to fix something I messed up here, because SUSE > pack their development utilities in /usr/sbin ;-) > > His patch does the right thing: removing the fixed paths from iasl. > But that will break autobuild. that could easily be fixed not an issue, > but it would also break compilation for a couple of people out there. > > So in addition I was suggesting to do PATH=$PATH:/usr/sbin in the build > process so nobody would notice we fixed it ;-) Exactly. My patch plus PATH=$PATH:/usr/sbin should fix all issues. Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From stepan at coresystems.de Sun Oct 8 17:45:02 2006 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 8 Oct 2006 17:45:02 +0200 Subject: [LinuxBIOS] Pending patches. In-Reply-To: <20061008153841.GD865@greenwood> References: <20061006180619.GD14977@greenwood> <20061007003353.GA1161@coresystems.de> <45270AC0.9080205@lanl.gov> <20061007082940.GA1103@coresystems.de> <20061008153841.GD865@greenwood> Message-ID: <20061008154502.GA12188@coresystems.de> * Uwe Hermann [061008 17:38]: > > So in addition I was suggesting to do PATH=$PATH:/usr/sbin in the build > > process so nobody would notice we fixed it ;-) > > Exactly. My patch plus PATH=$PATH:/usr/sbin should fix all issues. question is where to put it. Suggestions? -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ From smithbone at gmail.com Sun Oct 8 19:19:00 2006 From: smithbone at gmail.com (Richard Smith) Date: Sun, 8 Oct 2006 12:19:00 -0500 Subject: [LinuxBIOS] cpio discussion summary Message-ID: <8a0c36780610081019q630a5599hd136a5bb60bf47d6@mail.gmail.com> Ok... I've been slugging throught all the e-mails you guys have been cranking out of the past few days. Would someone summarize what is is we are debating here? I've read all the mail but I'm not sure I have a clear picuture of the options on the table. -- Richard A. Smith From smithbone at gmail.com Sun Oct 8 19:19:26 2006 From: smithbone at gmail.com (Richard Smith) Date: Sun, 8 Oct 2006 12:19:26 -0500 Subject: [LinuxBIOS] Interesting article Message-ID: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> I think this is a timely article since we where just discussing this. http://www.linux.com/article.pl?sid=06/09/29/164207 Executive Summary: A buch of GPL code ended up getting distributed in binary only. Over a bunch of smally ports the license files ended up getting dropped. Key point of the article for LinuxBIOS: """ As Doelle points out, some of the problems might have been avoided if the GPL header had been included in each file, rather than depending on a single COPYING file containing the text of the GPL. At least this would make it more obvious to developers what the requirements are for their use of GPLed code. """ So we should probably do as Uwe says and start including the GPL header on all source files. -- Richard A. Smith From smithbone at gmail.com Sun Oct 8 19:19:51 2006 From: smithbone at gmail.com (Richard Smith) Date: Sun, 8 Oct 2006 12:19:51 -0500 Subject: [LinuxBIOS] qemu images In-Reply-To: <1159631961.3015.1.camel@iridium.gnat.ca> References: <1159631961.3015.1.camel@iridium.gnat.ca> Message-ID: <8a0c36780610081019p17d2c1cek9f6025e29d5e6f2c@mail.gmail.com> > I have a semi related question. I see that the OLPC project uses > buildroot to create a root filesystem. I've done the same for a few > projects. I'm wondering though, how they convert the filesystem to a > disk image. I went over the docs on the wiki and used google, and I > don't know how they get a disk image from the filesystems it creates. I think you are a bit confused with what OLPC buildrom does. Note thats 'buildrom' not 'buildroot'. OLPC buildrom is based on buildroot but has been customized for our use by Jordan Crouse of AMD. The output of buildrom is a 1 MiB ROM image called 'linuxbios.rom' that is ready to be programmed into the onboard flash. It contains linuxbios, EC, VSA code and linux kernel payload. The qemu images are created by Redhat in a totally separate build process and other than the fact that linuxbios.rom is included in the images have little to do with buildrom. -- Richard A. Smith From uwe at hermann-uwe.de Mon Oct 9 00:32:01 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 9 Oct 2006 00:32:01 +0200 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> Message-ID: <20061008223201.GA11910@greenwood> Hi, On Sun, Oct 08, 2006 at 12:19:26PM -0500, Richard Smith wrote: > So we should probably do as Uwe says and start including the GPL > header on all source files. I agree. Do as Uwe says ;-) Seriously though, here's a first patch which adds the GPL header to your som/ims/p2b code. This was an easy one as (accoring to svn logs) you are the sole author of all the code (please correct me if I'm wrong). For other parts of the code base some more elaborate investigations might be needed. I'd say everyone with svn commit access could/should just add the header to code where he/she is the sole author and owns all of the copyright to the code. We can then take care of the more complex cases later. Note: The header I used in this patch is the "GPLv2 or later" version. Richard, if you want to use another license, please say so before this gets committed. Is there a general guideline as to who licenses their code under which license? That would make it easier for me to prepare further patches. Examples: Stefan: GPLv2 or later? Who owns the copyright - you or coresystems GmbH or even SuSE(?) Ron: Is all of your work on behalf of LANL? Do they own the copyright or do you? Do you have to use the BSD-like LANL license???(see arch/i386/include/arch/intel.h for an example) or can you just license your stuff under the GPLv2 or later? If so, do you want to do so? Yinghai: Is all of your work on behalf of AMD? AMD owns the copyright for the code, correct? Is it ok to use the "GPL v2 or later" header as in this patch for the code? Richard: Is GPLv2 or later fine? Are you the copyright owner or maybe a company you work for? Others? HTH, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Mon Oct 9 00:36:01 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 9 Oct 2006 00:36:01 +0200 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <20061008223201.GA11910@greenwood> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> Message-ID: <20061008223601.GB11910@greenwood> Forgot the patch. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- Index: src/mainboard/advantech/som_gx533c/Config.lb =================================================================== --- src/mainboard/advantech/som_gx533c/Config.lb (Revision 2450) +++ src/mainboard/advantech/som_gx533c/Config.lb (Arbeitskopie) @@ -1,4 +1,23 @@ ## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + +## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## Index: src/mainboard/advantech/som_gx533c/reset.c =================================================================== --- src/mainboard/advantech/som_gx533c/reset.c (Revision 2450) +++ src/mainboard/advantech/som_gx533c/reset.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #if 0 //#include "arch/romcc_io.h" #include Index: src/mainboard/advantech/som_gx533c/irq_tables.c =================================================================== --- src/mainboard/advantech/som_gx533c/irq_tables.c (Revision 2450) +++ src/mainboard/advantech/som_gx533c/irq_tables.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up Index: src/mainboard/advantech/som_gx533c/Options.lb =================================================================== --- src/mainboard/advantech/som_gx533c/Options.lb (Revision 2450) +++ src/mainboard/advantech/som_gx533c/Options.lb (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE Index: src/mainboard/advantech/som_gx533c/debug.c =================================================================== --- src/mainboard/advantech/som_gx533c/debug.c (Revision 2450) +++ src/mainboard/advantech/som_gx533c/debug.c (Arbeitskopie) @@ -1,3 +1,20 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ static void print_debug_pci_dev(unsigned dev) { Index: src/mainboard/advantech/som_gx533c/failover.c =================================================================== --- src/mainboard/advantech/som_gx533c/failover.c (Revision 2450) +++ src/mainboard/advantech/som_gx533c/failover.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define ASSEMBLY 1 #include #include Index: src/mainboard/advantech/som_gx533c/auto.c =================================================================== --- src/mainboard/advantech/som_gx533c/auto.c (Revision 2450) +++ src/mainboard/advantech/som_gx533c/auto.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define ASSEMBLY 1 #include Index: src/mainboard/advantech/som_gx533c/chip.h =================================================================== --- src/mainboard/advantech/som_gx533c/chip.h (Revision 2450) +++ src/mainboard/advantech/som_gx533c/chip.h (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations mainboard_advantech_som_gx533c_ops; struct mainboard_advantech_som_gx533c_config { Index: src/mainboard/advantech/som_gx533c/cmos.layout =================================================================== --- src/mainboard/advantech/som_gx533c/cmos.layout (Revision 2450) +++ src/mainboard/advantech/som_gx533c/cmos.layout (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + entries #start-bit length config config-ID name Index: src/mainboard/advantech/som_gx533c/mainboard.c =================================================================== --- src/mainboard/advantech/som_gx533c/mainboard.c (Revision 2450) +++ src/mainboard/advantech/som_gx533c/mainboard.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include #include #include Index: src/mainboard/bitworks/ims/Config.lb =================================================================== --- src/mainboard/bitworks/ims/Config.lb (Revision 2450) +++ src/mainboard/bitworks/ims/Config.lb (Arbeitskopie) @@ -1,3 +1,22 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. Index: src/mainboard/bitworks/ims/reset.c =================================================================== --- src/mainboard/bitworks/ims/reset.c (Revision 2450) +++ src/mainboard/bitworks/ims/reset.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #if 0 //#include "arch/romcc_io.h" #include Index: src/mainboard/bitworks/ims/irq_tables.c =================================================================== --- src/mainboard/bitworks/ims/irq_tables.c (Revision 2450) +++ src/mainboard/bitworks/ims/irq_tables.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up Index: src/mainboard/bitworks/ims/Options.lb =================================================================== --- src/mainboard/bitworks/ims/Options.lb (Revision 2450) +++ src/mainboard/bitworks/ims/Options.lb (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE Index: src/mainboard/bitworks/ims/debug.c =================================================================== --- src/mainboard/bitworks/ims/debug.c (Revision 2450) +++ src/mainboard/bitworks/ims/debug.c (Arbeitskopie) @@ -1,3 +1,20 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ static void print_debug_pci_dev(unsigned dev) { Index: src/mainboard/bitworks/ims/failover.c =================================================================== --- src/mainboard/bitworks/ims/failover.c (Revision 2450) +++ src/mainboard/bitworks/ims/failover.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define ASSEMBLY 1 #include #include Index: src/mainboard/bitworks/ims/auto.c =================================================================== --- src/mainboard/bitworks/ims/auto.c (Revision 2450) +++ src/mainboard/bitworks/ims/auto.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define ASSEMBLY 1 #include Index: src/mainboard/bitworks/ims/chip.h =================================================================== --- src/mainboard/bitworks/ims/chip.h (Revision 2450) +++ src/mainboard/bitworks/ims/chip.h (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations mainboard_bitworks_ims_ops; struct mainboard_bitworks_ims_config { Index: src/mainboard/bitworks/ims/cmos.layout =================================================================== --- src/mainboard/bitworks/ims/cmos.layout (Revision 2450) +++ src/mainboard/bitworks/ims/cmos.layout (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + entries #start-bit length config config-ID name Index: src/mainboard/bitworks/ims/mainboard.c =================================================================== --- src/mainboard/bitworks/ims/mainboard.c (Revision 2450) +++ src/mainboard/bitworks/ims/mainboard.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include #include #include Index: src/mainboard/asus/p2b/Config.lb =================================================================== --- src/mainboard/asus/p2b/Config.lb (Revision 2450) +++ src/mainboard/asus/p2b/Config.lb (Arbeitskopie) @@ -1,3 +1,22 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. Index: src/mainboard/asus/p2b/reset.c =================================================================== --- src/mainboard/asus/p2b/reset.c (Revision 2450) +++ src/mainboard/asus/p2b/reset.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #if 0 //#include "arch/romcc_io.h" #include Index: src/mainboard/asus/p2b/irq_tables.c =================================================================== --- src/mainboard/asus/p2b/irq_tables.c (Revision 2450) +++ src/mainboard/asus/p2b/irq_tables.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up Index: src/mainboard/asus/p2b/Options.lb =================================================================== --- src/mainboard/asus/p2b/Options.lb (Revision 2450) +++ src/mainboard/asus/p2b/Options.lb (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE Index: src/mainboard/asus/p2b/debug.c =================================================================== --- src/mainboard/asus/p2b/debug.c (Revision 2450) +++ src/mainboard/asus/p2b/debug.c (Arbeitskopie) @@ -1,3 +1,20 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ static void print_debug_pci_dev(unsigned dev) { Index: src/mainboard/asus/p2b/failover.c =================================================================== --- src/mainboard/asus/p2b/failover.c (Revision 2450) +++ src/mainboard/asus/p2b/failover.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define ASSEMBLY 1 #include #include Index: src/mainboard/asus/p2b/auto.c =================================================================== --- src/mainboard/asus/p2b/auto.c (Revision 2450) +++ src/mainboard/asus/p2b/auto.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define ASSEMBLY 1 #include Index: src/mainboard/asus/p2b/chip.h =================================================================== --- src/mainboard/asus/p2b/chip.h (Revision 2450) +++ src/mainboard/asus/p2b/chip.h (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations mainboard_asus_p2b_ops; struct mainboard_asus_p2b_config { Index: src/mainboard/asus/p2b/cmos.layout =================================================================== --- src/mainboard/asus/p2b/cmos.layout (Revision 2450) +++ src/mainboard/asus/p2b/cmos.layout (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + entries #start-bit length config config-ID name Index: src/mainboard/asus/p2b/mainboard.c =================================================================== --- src/mainboard/asus/p2b/mainboard.c (Revision 2450) +++ src/mainboard/asus/p2b/mainboard.c (Arbeitskopie) @@ -1,3 +1,21 @@ +/* + * Copyright (C) 2006 Richard Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include #include #include Index: targets/advantech/som_gx533c/Config.lb =================================================================== --- targets/advantech/som_gx533c/Config.lb (Revision 2450) +++ targets/advantech/som_gx533c/Config.lb (Arbeitskopie) @@ -1,3 +1,22 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + # Config file for the Advantech eval kit with a SOM-DB2301 baseboard # and a SOM 2354 Cpu module. (gx533) # This will make a target directory of som_gx533c Index: targets/bitworks/ims/Config.lb =================================================================== --- targets/bitworks/ims/Config.lb (Revision 2450) +++ targets/bitworks/ims/Config.lb (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + # Config file for the Bitworks ims board # This will make a target directory of ./ims Index: targets/asus/p2b/Config.lb =================================================================== --- targets/asus/p2b/Config.lb (Revision 2450) +++ targets/asus/p2b/Config.lb (Arbeitskopie) @@ -1,3 +1,21 @@ +## +## Copyright (C) 2006 Richard Smith +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + # Config file for asus p2b board # This will make a target directory of ./p2b -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From yinghailu at gmail.com Mon Oct 9 02:43:03 2006 From: yinghailu at gmail.com (yhlu) Date: Sun, 8 Oct 2006 17:43:03 -0700 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <20061008223201.GA11910@greenwood> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> Message-ID: <2ea3fae10610081743o5d1448f1k9197ff3648cb76f6@mail.gmail.com> rev E dual core, raminit, Cache_as_ram and CK804 is for Tyan. ... others is for AMD. YH On 10/8/06, Uwe Hermann wrote: > Hi, > > On Sun, Oct 08, 2006 at 12:19:26PM -0500, Richard Smith wrote: > > So we should probably do as Uwe says and start including the GPL > > header on all source files. > > I agree. Do as Uwe says ;-) > > Seriously though, here's a first patch which adds the GPL header to > your som/ims/p2b code. This was an easy one as (accoring to svn logs) > you are the sole author of all the code (please correct me if I'm wrong). > > For other parts of the code base some more elaborate investigations > might be needed. > > I'd say everyone with svn commit access could/should just add the header > to code where he/she is the sole author and owns all of the copyright > to the code. We can then take care of the more complex cases later. > > > Note: The header I used in this patch is the "GPLv2 or later" version. > Richard, if you want to use another license, please say so before > this gets committed. > > > Is there a general guideline as to who licenses their code under which > license? That would make it easier for me to prepare further patches. > > Examples: > > Stefan: GPLv2 or later? Who owns the copyright - you or coresystems GmbH > or even SuSE(?) > > Ron: Is all of your work on behalf of LANL? Do they own the copyright > or do you? Do you have to use the BSD-like LANL license??(see > arch/i386/include/arch/intel.h for an example) or can you just > license your stuff under the GPLv2 or later? > If so, do you want to do so? > > Yinghai: Is all of your work on behalf of AMD? AMD owns the copyright > for the code, correct? Is it ok to use the "GPL v2 or later" > header as in this patch for the code? > > Richard: Is GPLv2 or later fine? Are you the copyright owner or maybe > a company you work for? > > Others? > > > > HTH, Uwe. > -- > Uwe Hermann > http://www.hermann-uwe.de > http://www.it-services-uh.de | http://www.crazy-hacks.org > http://www.holsham-traders.de | http://www.unmaintained-free-software.org > > > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.5 (GNU/Linux) > > iD8DBQFFKXxgXdVoV3jWIbQRAi84AJ9mDp7iA/Gx3M9oHCIoB/FNzV98IQCgkxRG > zx4iepiauUN9hpFwzJa8Byg= > =zf8L > -----END PGP SIGNATURE----- > > > -- > linuxbios mailing list > linuxbios at linuxbios.org > http://www.openbios.org/mailman/listinfo/linuxbios > > From smithbone at gmail.com Mon Oct 9 03:42:51 2006 From: smithbone at gmail.com (Richard Smith) Date: Sun, 8 Oct 2006 20:42:51 -0500 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <20061008223201.GA11910@greenwood> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> Message-ID: <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> >Richard: Is GPLv2 or later fine? Are you the copyright owner or maybe > a company you work for? GPLv2 or later is fine for me. That said however, very little of that som_gx533 and p2b code was created by me. The som stuff is a copy of the Rumba board and the p2b is a copy of the ims stuff. The ims stuff is a mix and match from several of the other boards. I just stuck it all together and then fixed a few quirks to make the SPD code work. -- Richard A. Smith From rminnich at gmail.com Mon Oct 9 03:53:34 2006 From: rminnich at gmail.com (ron minnich) Date: Sun, 8 Oct 2006 19:53:34 -0600 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> Message-ID: <13426df10610081853u2aa6978ds246677a77b1032b4@mail.gmail.com> gpl v2. Let's avoid "or later" until that controversy is resolved. All LANL code has that weird bsd-like license text, but note it is really GPL. So GPL V2. ron -------------- next part -------------- An HTML attachment was scrubbed... URL: From tylerapohl at gmail.com Mon Oct 9 08:46:48 2006 From: tylerapohl at gmail.com (Tyler Pohl) Date: Sun, 8 Oct 2006 23:46:48 -0700 Subject: [LinuxBIOS] via c3 Message-ID: <503ab0210610082346t2e90e8d7y3bc1f57e558cda9e@mail.gmail.com> Will linuxbios work with the older via c3 processors missing the "cmov" instruction? -------------- next part -------------- An HTML attachment was scrubbed... URL: From stuge-linuxbios at cdy.org Mon Oct 9 09:26:06 2006 From: stuge-linuxbios at cdy.org (Peter Stuge) Date: Mon, 9 Oct 2006 09:26:06 +0200 Subject: [LinuxBIOS] via c3 In-Reply-To: <503ab0210610082346t2e90e8d7y3bc1f57e558cda9e@mail.gmail.com> References: <503ab0210610082346t2e90e8d7y3bc1f57e558cda9e@mail.gmail.com> Message-ID: <20061009072606.24080.qmail@cdy.org> On Sun, Oct 08, 2006 at 11:46:48PM -0700, Tyler Pohl wrote: > Will linuxbios work with the older via c3 processors missing the "cmov" > instruction? LinuxBIOS works just fine on my EPIA-MII board which has a 600MHz C3. I can't check right now whether it has cmov or not though, but it seems that none of the c3 have cmov by design? Or did Via change it during the product lifetime? //Peter From rminnich at gmail.com Mon Oct 9 17:00:03 2006 From: rminnich at gmail.com (ron minnich) Date: Mon, 9 Oct 2006 09:00:03 -0600 Subject: [LinuxBIOS] peter stuge's car mp3 Message-ID: <13426df10610090800n7431a612t3eb239732216edad@mail.gmail.com> two short videos at youtube: http://www.youtube.com/watch?v=2jP4gBPAgTA and http://www.youtube.com/watch?v=kl1OWxbWCkA peter is going to get us a parts list, rom image, and so forth so people can clone this. Hmm, I just put peter on the spot, hope he does not mind :-) thanks ron From uwe at hermann-uwe.de Mon Oct 9 17:50:20 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 9 Oct 2006 17:50:20 +0200 Subject: [LinuxBIOS] LinuxBIOS logo license? Message-ID: <20061009155019.GA6921@greenwood> Hi, just a quick question???-- who created the LinuxBIOS logo in the wiki and what license applies? Can I use it to create a LinuxBIOS-related GPL'd artwork (icon)? Cheers, Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Mon Oct 9 17:56:23 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 9 Oct 2006 17:56:23 +0200 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> Message-ID: <20061009155623.GB6921@greenwood> Hi, On Sun, Oct 08, 2006 at 08:42:51PM -0500, Richard Smith wrote: > >Richard: Is GPLv2 or later fine? Are you the copyright owner or maybe > > a company you work for? > > GPLv2 or later is fine for me. That said however, very little of > that som_gx533 and p2b code was created by me. The som stuff is a > copy of the Rumba board and the p2b is a copy of the ims stuff. The > ims stuff is a mix and match from several of the other boards. I just > stuck it all together and then fixed a few quirks to make the SPD code > work. Hm, ok, so more investigations are needed. I think it's pretty common in the code-base that stuff gets copied and modified. We need to find the person(s) who created the original "template" code and add them as co-authors to those "Copyright 200x" lines... Do archives of the older CVS trees (with full history) still exist? The svn history only goes back to an "import of freebios2" or so entry. Ah, I just noted that the v1 tree seems to go back to an earlier date. Does it contain _all_ history of the code or was something used before CVS back then? Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From uwe at hermann-uwe.de Mon Oct 9 18:01:10 2006 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 9 Oct 2006 18:01:10 +0200 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <13426df10610081853u2aa6978ds246677a77b1032b4@mail.gmail.com> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> <13426df10610081853u2aa6978ds246677a77b1032b4@mail.gmail.com> Message-ID: <20061009160109.GC6921@greenwood> Hi, On Sun, Oct 08, 2006 at 07:53:34PM -0600, ron minnich wrote: > gpl v2. Let's avoid "or later" until that controversy is resolved. I don't see a problem with "v2 or later". Everybody who doesn't like to use GPLv3 (when it's released) can just chose to use v2. That's perfectly legal. If???we don't use "v2 or later" for the major parts _now_, but decide (at some point in the future) to convert to "v3 or later" we'll have to go through all of this relicensing stuff again... > All LANL code has that weird bsd-like license text, but note it is really > GPL. So GPL V2. Wait, the actual license is the GPL? It doesn't say so anywhere, so that definately needs to be clarified. As I understood things until now, was that the LANL-text is in itself a license, namely a BSD-ish one. Would LANL agree to relicense their code to GPL, and/or remove the BSD-ish text? It's really confusing... Uwe. -- Uwe Hermann http://www.hermann-uwe.de http://www.it-services-uh.de | http://www.crazy-hacks.org http://www.holsham-traders.de | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: From segher at kernel.crashing.org Mon Oct 9 18:23:34 2006 From: segher at kernel.crashing.org (Segher Boessenkool) Date: Mon, 9 Oct 2006 18:23:34 +0200 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <20061009160109.GC6921@greenwood> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> <13426df10610081853u2aa6978ds246677a77b1032b4@mail.gmail.com> <20061009160109.GC6921@greenwood> Message-ID: <8DBADC35-AEE4-42CD-A819-4FB902C0C849@kernel.crashing.org> >> gpl v2. Let's avoid "or later" until that controversy is resolved. > > I don't see a problem with "v2 or later". Everybody who doesn't > like to > use GPLv3 (when it's released) can just chose to use v2. That's > perfectly legal. FWIW, no one but the original author(s) can decide to re-license "v2 only" code to "v2 or later" (later licenses [can] include extra restrictions, which are explicitly not allowed by the v2 license). Segher From smithbone at gmail.com Mon Oct 9 18:28:35 2006 From: smithbone at gmail.com (Richard Smith) Date: Mon, 9 Oct 2006 11:28:35 -0500 Subject: [LinuxBIOS] PATCH: GPL Header for som/ims/p2b code. In-Reply-To: <20061009160109.GC6921@greenwood> References: <8a0c36780610081019x13ce600fjadeb3b2f9ab80c62@mail.gmail.com> <20061008223201.GA11910@greenwood> <8a0c36780610081842h16bd76c3xe34aee8a13d3303b@mail.gmail.com> <13426df10610081853u2aa6978ds246677a77b1032b4@mail.gmail.com> <20061009160109.GC6921@greenwood> Message-ID: <8a0c36780610090928o7936e626h5cb4d94ac74d79a0@mail.gmail.com> > I don't see a problem with "v2 or later". Everybody who doesn't like to > use GPLv3 (when it's released) can just chose to use v2. That's > perfectly legal. > Actually I don't think we have a choice. LWN.net just ran an article on the busybox GPLv2 GPLv3 issue which has caused a fork of busybox. One of the things I see in that article is that GPLv2 only code cannot co-exist with v3 code. We have included kernel code which is v2 only. Therefore our entire base must be v2 only. -- Richard A. Smith From smithbone at gmail.com Mon Oct 9 18:42:38 2006 From: smithbone at gmail.com (Richard Smith) Date: Mon, 9 Oct 2006 11:42:38 -0500 Subject: [LinuxBIOS] Slides from AMD Message-ID: <8a0c36780610090942p4a9be5d7vcd9a4ba0d58e8f40@mail.gmail.com> I've had a request for the slides from AMD on thier LinuxBIOS roadmap. Said person is designing an Opteron Rev F platform and is interested in using LinuxBIOS. Any luck on getting the documentation and permission in order so we can post them up on the website. -- Richard A. Smith From eswierk at arastra.com Mon Oct 9 18:44:12 2006 From: eswierk at arastra.com (Ed Swierk) Date: Mon, 9 Oct 2006 09:44:12 -0700 Subject: [LinuxBIOS] r2447 - in trunk/LinuxBIOSv2/src: config lib stream In-Reply-To: References: Message-ID: On 10/7/06, Segher Boessenkool wrote: > This table isn't needed, a UART stream is so slow that you can > just as well open-code the CRC algorithm and lose nothing (except > for 512 bytes of table :-) ) Good point. This patch replaces the table-driven CRC-16 implementation with a computational one. --Ed -------------- next part -------------- A non-text attachment was scrubbed... Name: linuxbios-xmodem-crc-notable.patch Type: text/x-patch Size: 2730 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Mon Oct 9 19:15:09 2006 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 09 Oct 2006 19:15:09 +0200 Subject: [LinuxBIOS] [PATCH] Download payload from console via XMODEM In-Reply-To: <20061007001518.GA16679@coresystems.de> References: <20061006160529.GA11763@coresystems.de> <20061007001518.GA16679@coresystems.de> Message-ID: <452A839D.80004@gmx.net> Stefan Reinauer wrote: > * Ed Swierk [061007 01:45]: >