[LinuxBIOS] Is the Cache as Ram for Gx2 processor?
segher at kernel.crashing.org
Sun Apr 8 14:54:26 CEST 2007
>> Could you give a quick description how cache-as-RAM
>> should be done on a Geode? Nothing detailed, just
>> the outline.
> Well, the outline is the same as the one used for AMD64 CAR: "Cache
> Initialization For General Storage During Boot" in the BKDG.
What's the BKDG?
> The current CAR code modifies that cacheability rules and mappings
> with fixed, variable, and default type MTRRs. The code is generic,
> except for one AMD64-specific MSR.
So it's the same "put stuff into the cache, then mark that memory
range as uncacheable" trick?
> I don't see why it wouldn't work on any proc with x86-compatible
I could come up with some scenarios but none look very realistic.
For example, the cache could do some "background" writebacks to
try to optimise performance. Unfortunately the public documentation
for x86 CPUs (any vendor) never seems to describe the caches'
behaviour in detail.
Thanks for the explanation,
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