[LinuxBIOS] i440bx RAM initialization code (SPD)

Alfred Wanga awanga at gmail.com
Mon Apr 30 16:47:42 CEST 2007

Ok, so I've been working on porting the SPD code, and this patch is
what I've got so far. Here are some of the outstanding issues/changes:

* SPD register code (tested using PCI/SMBus Dumps)
I ported the v1 assembly and made some modifications when the numbers
didn't really add up on my machine (particularly the DRB registers)
and added some minor functionality (CAS2/3 detection) that may or may
not work, although based on the results from the dataset I used, it
should work (at least for my current setup).

* PMCR - When should it be updated?
Looking at the assembly, it seems as though it's ok to just set the
final value before the RAM refresh code instead of waiting until
afterwards, but I don't know for sure, so I left the original code
alone. Judging from some of the recent 440bx discussions, it may not
make much of a difference anyway.

* sdram_enable delays
I changed all the RAM timing delays (tRP, tRC, tMRD) to 1usec, since
the timings are on the order of hundreds of nanoseconds (according to
SPD values) and the smallest resolution timer available seems to be
udelay() anyway. It should work for any SDRAM, and shaves a few
milliseconds off previous code.

Incidentally, I noticed that the v1 assembly sets the clock idle value
to 32 in the PGPOL register until SDRAM refresh is enabled, but it
seems like it should eventually be set back to zero (which is what the
patch does). Does it matter?

Anyway, enough verbosity... take a look and see what you think.
Unfortunately, besides testing the SPD code on memory dumps, I haven't
tested the image.

-------------- next part --------------
A non-text attachment was scrubbed...
Name: i440bx_raminit_spd.patch
Type: application/octet-stream
Size: 12537 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20070430/d8e3ee5d/attachment.obj>

More information about the coreboot mailing list