[LinuxBIOS] r536 - in LinuxBIOSv3: arch/x86 device include include/device lib northbridge/amd/geodelx northbridge/intel/i440bxemulation
svn at openbios.org
svn at openbios.org
Tue Dec 4 22:06:52 CET 2007
Author: uwe
Date: 2007-12-04 22:06:52 +0100 (Tue, 04 Dec 2007)
New Revision: 536
Removed:
LinuxBIOSv3/include/northbridgelib.h
LinuxBIOSv3/lib/northbridgelib.c
Modified:
LinuxBIOSv3/arch/x86/Makefile
LinuxBIOSv3/device/pci_device.c
LinuxBIOSv3/include/device/pci.h
LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c
LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c
Log:
Move the code from northbridgelib.c to pci_device.c.
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified: LinuxBIOSv3/arch/x86/Makefile
===================================================================
--- LinuxBIOSv3/arch/x86/Makefile 2007-12-03 20:41:02 UTC (rev 535)
+++ LinuxBIOSv3/arch/x86/Makefile 2007-12-04 21:06:52 UTC (rev 536)
@@ -172,7 +172,7 @@
#
STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \
- compute_ip_checksum.o string.o northbridgelib.o
+ compute_ip_checksum.o string.o
STAGE2_ARCH_X86_OBJ = archtables.o linuxbios_table.o udelay_io.o
STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
Modified: LinuxBIOSv3/device/pci_device.c
===================================================================
--- LinuxBIOSv3/device/pci_device.c 2007-12-03 20:41:02 UTC (rev 535)
+++ LinuxBIOSv3/device/pci_device.c 2007-12-04 21:06:52 UTC (rev 536)
@@ -449,6 +449,32 @@
pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
}
+/**
+ * Set resources for the PCI domain.
+ *
+ * A PCI domain contains the I/O and memory resource address space below it.
+ * Set up basic global ranges for I/O and memory. Allocation of sub-resources
+ * draws on these top-level resources in the usual hierarchical manner.
+ *
+ * @param dev The northbridge device.
+ */
+void pci_domain_read_resources(struct device *dev)
+{
+ struct resource *res;
+
+ /* Initialize the system-wide I/O space constraints. */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ res->limit = 0xffffUL;
+ res->flags =
+ IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+ /* Initialize the system-wide memory resources constraints. */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ res->limit = 0xffffffffULL;
+ res->flags =
+ IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
static void pci_set_resource(struct device *dev, struct resource *resource)
{
resource_t base, end;
@@ -580,6 +606,32 @@
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
}
+/**
+ * Create a RAM resource, by taking the passed-in size and creating
+ * a resource record.
+ *
+ * @param dev The device.
+ * @param index A resource index.
+ * @param basek Base memory address in KB.
+ * @param sizek Size of memory in KB.
+ */
+void ram_resource(struct device *dev, unsigned long index,
+ unsigned long basek, unsigned long sizek)
+{
+ struct resource *res;
+
+ if (!sizek)
+ return;
+
+ res = new_resource(dev, index);
+ res->base = ((resource_t) basek) << 10; /* Convert to bytes. */
+ res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */
+ res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size);
+}
+
void pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
@@ -1108,6 +1160,22 @@
}
/**
+ * Support for scan bus from the "tippy top" -- i.e. the PCI domain,
+ * not the 0:0.0 device.
+ *
+ * This function works for almost all chipsets (AMD K8 is the exception).
+ *
+ * @param dev The PCI domain device.
+ * @param max Maximum number of devices to scan.
+ * @return TODO
+ */
+unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max)
+{
+ /* There is only one link on this device, and it is always link 0. */
+ return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+}
+
+/**
* Scan a PCI bridge and the buses behind the bridge.
*
* Determine the existence of buses behind the bridge. Set up the bridge
Modified: LinuxBIOSv3/include/device/pci.h
===================================================================
--- LinuxBIOSv3/include/device/pci.h 2007-12-03 20:41:02 UTC (rev 535)
+++ LinuxBIOSv3/include/device/pci.h 2007-12-04 21:06:52 UTC (rev 536)
@@ -94,6 +94,12 @@
struct resource *pci_get_resource(struct device *dev, unsigned long index);
void pci_dev_set_subsystem(struct device * dev, unsigned vendor, unsigned device);
+void pci_domain_read_resources(struct device *dev);
+void ram_resource(struct device *dev, unsigned long index,
+ unsigned long basek, unsigned long sizek);
+unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
+
+
#define PCI_IO_BRIDGE_ALIGN 4096
#define PCI_MEM_BRIDGE_ALIGN (1024*1024)
Deleted: LinuxBIOSv3/include/northbridgelib.h
===================================================================
--- LinuxBIOSv3/include/northbridgelib.h 2007-12-03 20:41:02 UTC (rev 535)
+++ LinuxBIOSv3/include/northbridgelib.h 2007-12-04 21:06:52 UTC (rev 536)
@@ -1,26 +0,0 @@
-/*
- * This file is part of the LinuxBIOS project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-void pci_domain_read_resources(struct device *dev);
-void ram_resource(struct device *dev, unsigned long index,
- unsigned long basek, unsigned long sizek);
-unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
Deleted: LinuxBIOSv3/lib/northbridgelib.c
===================================================================
--- LinuxBIOSv3/lib/northbridgelib.c 2007-12-03 20:41:02 UTC (rev 535)
+++ LinuxBIOSv3/lib/northbridgelib.c 2007-12-04 21:06:52 UTC (rev 536)
@@ -1,92 +0,0 @@
-/*
- * This file is part of the LinuxBIOS project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <console.h>
-#include <device/device.h>
-#include <device/pci.h>
-
-/**
- * Set resources for the PCI domain.
- *
- * A PCI domain contains the I/O and memory resource address space below it.
- * Set up basic global ranges for I/O and memory. Allocation of sub-resources
- * draws on these top-level resources in the usual hierarchical manner.
- *
- * @param dev The northbridge device.
- */
-void pci_domain_read_resources(struct device *dev)
-{
- struct resource *res;
-
- /* Initialize the system-wide I/O space constraints. */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->limit = 0xffffUL;
- res->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system-wide memory resources constraints. */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->limit = 0xffffffffULL;
- res->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
-/**
- * Create a RAM resource, by taking the passed-in size and creating
- * a resource record.
- *
- * @param dev The device.
- * @param index A resource index.
- * @param basek Base memory address in KB.
- * @param sizek Size of memory in KB.
- */
-void ram_resource(struct device *dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *res;
-
- if (!sizek)
- return;
-
- res = new_resource(dev, index);
- res->base = ((resource_t) basek) << 10; /* Convert to bytes. */
- res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */
- res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size);
-}
-
-/**
- * Support for scan bus from the "tippy top" -- i.e. the PCI domain,
- * not the 0:0.0 device.
- *
- * This function works for almost all chipsets (AMD K8 is the exception).
- *
- * @param dev The PCI domain device.
- * @param max Maximum number of devices to scan.
- * @return TODO
- */
-unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max)
-{
- /* There is only one link on this device, and it is always link 0. */
- return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-}
Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-12-03 20:41:02 UTC (rev 535)
+++ LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-12-04 21:06:52 UTC (rev 536)
@@ -25,7 +25,6 @@
#include <device/pci_ids.h>
#include <msr.h>
#include <amd_geodelx.h>
-#include <northbridgelib.h>
/* Function prototypes */
extern void chipsetinit(void);
Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-12-03 20:41:02 UTC (rev 535)
+++ LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-12-04 21:06:52 UTC (rev 536)
@@ -43,7 +43,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
-#include <northbridgelib.h>
#include "i440bx.h"
#include "statictree.h"
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