From kononov195-lbl at yahoo.com  Thu Feb  1 00:35:21 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Wed, 31 Jan 2007 17:35:21 -0600
Subject: [LinuxBIOS] [PATCH] VGA is used before it is initialized
In-Reply-To: <45C0F371.7000602@coresystems.de>
References: <45AEB79A.6040308@yahoo.com>
	<45C0DF72.3040800@yahoo.com>	<45C0E48A.4060603@coresystems.de>
	<45C0EFC6.3050007@yahoo.com> <45C0F371.7000602@coresystems.de>
Message-ID: <45C127B9.4070603@yahoo.com>

This patch makes sure that VGA is initialized before it is used.
Additionally, VGA will be initialized if either CONFIG_PCI_ROM_RUN=1
or CONFIG_CONSOLE_VGA=1.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
---
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From roger at eskimo.com  Thu Feb  1 00:43:26 2007
From: roger at eskimo.com (roger)
Date: Wed, 31 Jan 2007 15:43:26 -0800
Subject: [LinuxBIOS] Nobody likes the Linuxbios FAQ page?
Message-ID: <1170287006.24545.4.camel@localhost2.localdomain>

Link for:
http://www.linuxbios.org/FAQ

Just shows a page with:

The original MediaWiki FAQ can be found at
http://meta.wikimedia.org/wiki/MediaWiki_FAQ.

A newer version is available at
http://www.mediawiki.org/wiki/Help:FAQ.


(mmm.. this doesn't look like the Linuxbios faq google.com
or I recall.)


(You would think the MEdiaWiki FAQ page would at least show a jpeg of
Britney or something less boring. :-/)

--
Roger
http://www.eskimo.com/~roger/index.html
Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61

Wed Jan 31 15:40:09 PST 2007




From stuge-linuxbios at cdy.org  Thu Feb  1 00:53:26 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 1 Feb 2007 00:53:26 +0100
Subject: [LinuxBIOS] [PATCH] VGA is used before it is initialized
In-Reply-To: <45C127B9.4070603@yahoo.com>
References: <45AEB79A.6040308@yahoo.com> <45C0DF72.3040800@yahoo.com>
	<45C0E48A.4060603@coresystems.de> <45C0EFC6.3050007@yahoo.com>
	<45C0F371.7000602@coresystems.de> <45C127B9.4070603@yahoo.com>
Message-ID: <20070131235327.12140.qmail@cdy.org>

On Wed, Jan 31, 2007 at 05:35:21PM -0600, Roman Kononov wrote:
> This patch makes sure that VGA is initialized before it is used.
> Additionally, VGA will be initialized if either CONFIG_PCI_ROM_RUN=1
> or CONFIG_CONSOLE_VGA=1.

Index: src/devices/pci_device.c
===================================================================
--- src/devices/pci_device.c    (revision 2539)
+++ src/devices/pci_device.c    (working copy)
@@ -633,7 +633,7 @@ void pci_dev_set_subsystem(device_t dev,

 void pci_dev_init(struct device *dev)
 {
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_CONSOLE_VGA=1  
        struct rom_header *rom, *ram;

        rom = pci_rom_probe(dev);


One or two = ? Which is it?


//Peter



From stefan.reinauer at coresystems.de  Thu Feb  1 00:52:56 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Feb 2007 00:52:56 +0100
Subject: [LinuxBIOS] Nobody likes the Linuxbios FAQ page?
In-Reply-To: <1170287006.24545.4.camel@localhost2.localdomain>
References: <1170287006.24545.4.camel@localhost2.localdomain>
Message-ID: <45C12BD8.4080401@coresystems.de>

roger wrote:
> Link for:
> http://www.linuxbios.org/FAQ
> 
> Just shows a page with:
> 
> The original MediaWiki FAQ can be found at
> http://meta.wikimedia.org/wiki/MediaWiki_FAQ.
> 
> A newer version is available at
> http://www.mediawiki.org/wiki/Help:FAQ.
> 
> 
> (mmm.. this doesn't look like the Linuxbios faq google.com
> or I recall.)

Oops. A local file has been hiding the real FAQ since the last MediaWiki
security update.

It's fixed now. Thanks for reporting this.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Thu Feb  1 01:10:06 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  1 Feb 2007 01:10:06 +0100
Subject: [LinuxBIOS] r2540 - in trunk/LinuxBIOSv2/src/southbridge/nvidia: .
	mcp55
Message-ID: <mailman.157.1355071056.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-01 01:10:05 +0100 (Thu, 01 Feb 2007)
New Revision: 2540

Added:
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/Config.lb
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/chip.h
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.inc
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.lds
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.h
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_aza.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ht.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ide.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_nic.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pci.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pcie.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_reset.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_sata.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.inc
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.lds
Log:
Add support for the NVIDIA MCP55 southbridge.

Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Yinghai Lu <yinghai.lu at amd.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/Config.lb	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,35 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+config chip.h
+driver mcp55.o
+driver mcp55_usb.o
+driver mcp55_lpc.o
+driver mcp55_smbus.o
+driver mcp55_ide.o
+driver mcp55_sata.o
+driver mcp55_usb2.o
+driver mcp55_aza.o
+driver mcp55_nic.o
+driver mcp55_pci.o
+driver mcp55_pcie.o
+driver mcp55_ht.o
+object mcp55_reset.o

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/chip.h	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MCP55_CHIP_H
+#define MCP55_CHIP_H
+
+struct southbridge_nvidia_mcp55_config
+{
+	unsigned int ide0_enable : 1;
+	unsigned int ide1_enable : 1;
+	unsigned int sata0_enable : 1;
+	unsigned int sata1_enable : 1;
+	unsigned int mac_eeprom_smbus;
+	unsigned int mac_eeprom_addr;
+};
+struct chip_operations;
+extern struct chip_operations southbridge_nvidia_mcp55_ops;
+
+#endif /* MCP55_CHIP_H */

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.inc
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.inc	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.inc	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+	.section ".id", "a", @progbits
+
+	.globl __id_start
+__id_start:
+vendor:
+	.asciz MAINBOARD_VENDOR
+part:
+	.asciz MAINBOARD_PART_NUMBER
+.long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
+.long __id_end + 0x80 - part    /* Reverse offset to the part number */
+.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this romimage */
+	.globl __id_end
+
+__id_end:
+.previous

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.lds
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.lds	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/id.lds	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+SECTIONS {
+	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+	.id (.): {
+		*(.id)
+	}
+}

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,248 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static uint32_t final_reg;
+
+static device_t find_lpc_dev( device_t dev,  unsigned devfn)
+{
+
+	device_t lpc_dev;
+
+	lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
+
+	if ( !lpc_dev ) return lpc_dev;
+
+	if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
+		(lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
+		(lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
+		) ) {
+			uint32_t id;
+			id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
+			if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
+				(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
+				) {
+				lpc_dev = 0;
+			}
+	}
+
+	return lpc_dev;
+}
+
+void mcp55_enable(device_t dev)
+{
+	device_t lpc_dev = 0;
+	device_t sm_dev = 0;
+	unsigned index = 0;
+	unsigned index2 = 0;
+	uint32_t reg_old, reg;
+	uint8_t byte;
+	unsigned deviceid;
+	unsigned vendorid;
+
+	struct southbridge_nvidia_mcp55_config *conf;
+	conf = dev->chip_info;
+	int i;
+
+	unsigned devfn;
+
+	if(dev->device==0x0000) {
+		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
+		deviceid = (vendorid>>16) & 0xffff;
+//		vendorid &= 0xffff;
+	} else {
+//		vendorid = dev->vendor;
+		deviceid = dev->device;
+	}
+
+	devfn = (dev->path.u.pci.devfn) & ~7;
+	switch(deviceid) {
+		case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
+			return;
+
+		case PCI_DEVICE_ID_NVIDIA_MCP55_SM2://?
+			index = 16;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
+			devfn -= (1<<3);
+			index = 8;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
+			devfn -= (1<<3);
+			index = 20;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: //two
+		case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE://two
+			devfn -= (7<<3);
+			index = 10;
+			for(i=0;i<2;i++) {
+				lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
+				if(!lpc_dev) continue;
+				index -= i;
+				devfn -= (i<<3);
+				break;
+			}
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
+			devfn -= (5<<3);
+			index = 11;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
+			devfn -= (3<<3);
+			index = 14;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: //three
+		case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
+			devfn -= (4<<3);
+			index = 22;
+			i = (dev->path.u.pci.devfn) & 7;
+			if(i>0) {
+				index -= (i+3);
+			}
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
+			devfn -= (5<<3);
+			index = 15;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
+			devfn -= (0x9<<3);  // to LPC
+			index2 = 9;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: //two
+			devfn -= (0xa<<3);  // to LPC
+			index2 = 8;
+			for(i=0;i<2;i++) {
+				lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
+				if(!lpc_dev) continue;
+				index2 -= i;
+				devfn -= (i<<3);
+				break;
+			}
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
+			devfn -= (0xc<<3);  // to LPC
+			index2 = 6;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
+			devfn -= (0xd<<3);  // to LPC
+			index2 = 5;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
+			devfn -= (0xe<<3);  // to LPC
+			index2 = 4;
+			break;
+		default:
+			index = 0;
+	}
+
+	if(!lpc_dev)
+		lpc_dev = find_lpc_dev(dev, devfn);
+
+	if ( !lpc_dev )	return;
+
+	if(index2!=0) {
+		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
+		if(!sm_dev) return;
+
+		if ( sm_dev ) {
+			reg_old = reg =  pci_read_config32(sm_dev, 0xe4);
+
+			if (!dev->enabled) { //disable it
+				reg |= (1<<index2);
+			}
+
+			if (reg != reg_old) {
+				pci_write_config32(sm_dev, 0xe4, reg);
+			}
+		}
+
+		index2 = 0;
+		return;
+	}
+
+
+	if ( index == 0) {  // for LPC
+
+		// expose ioapic base
+		byte = pci_read_config8(lpc_dev, 0x74);
+		byte |= ((1<<1)); // expose the BAR
+		pci_write_config8(dev, 0x74, byte);
+
+		// expose trap base
+		byte = pci_read_config8(lpc_dev, 0xdd);
+		byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
+		pci_write_config8(dev, 0xdd, byte);
+
+		return;
+
+	}
+
+	if( index == 16) {
+		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
+		if(!sm_dev) return;
+
+		final_reg = pci_read_config32(sm_dev, 0xe8);
+		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
+		pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
+#if 0
+		reg_old = reg = pci_read_config32(sm_dev, 0xe4);
+//		reg |= (1<<0);
+		reg &= ~(0x3f<<4);
+		if (reg != reg_old) {
+			printk_debug("mcp55.c pcie enabled\n");
+			pci_write_config32(sm_dev, 0xe4, reg);
+		}
+#endif
+	}
+
+	if (!dev->enabled) {
+		final_reg |= (1 << index);// disable it
+		//The reason for using final_reg, if diable func 1, the func 2 will be func 1 so We need disable them one time.
+	}
+
+	if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
+		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
+		if(!sm_dev) return;
+		reg_old = pci_read_config32(sm_dev, 0xe8);
+		if (final_reg != reg_old) {
+			pci_write_config32(sm_dev, 0xe8, final_reg);
+		}
+
+	}
+
+
+}
+
+struct chip_operations southbridge_nvidia_mcp55_ops = {
+	CHIP_NAME("Nvidia mcp55")
+	.enable_dev	= mcp55_enable,
+};

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55.h	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MCP55_H
+#define MCP55_H
+
+#include "chip.h"
+
+void mcp55_enable(device_t dev);
+
+#endif /* MCP55_H */

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_aza.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_aza.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_aza.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,267 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "mcp55.h"
+
+static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
+{
+	uint32_t dword;
+	int count;
+
+	val &= mask;
+	dword = readl(port);
+	dword &= ~mask;
+	dword |= val;
+	writel(dword, port);
+
+	count = 50;
+	do {
+		dword = readl(port);
+		dword &= mask;
+		udelay(100);
+	} while ((dword != val) && --count);
+
+	if(!count) return -1;
+
+	udelay(540);
+	return 0;
+
+}
+
+static int codec_detect(uint8_t *base)
+{
+	uint32_t dword;
+
+	/* 1 */
+	set_bits(base + 0x08, 1, 1);
+
+	/* 2 */
+	dword = readl(base + 0x0e);
+	dword |= 7;
+	writel(dword, base + 0x0e);
+
+	/* 3 */
+	set_bits(base + 0x08, 1, 0);
+
+	/* 4 */
+	set_bits(base + 0x08, 1, 1);
+
+	/* 5 */
+	dword = readl(base + 0xe);
+	dword &= 7;
+
+	/* 6 */
+	if(!dword) {
+		set_bits(base + 0x08, 1, 0);
+		printk_debug("No codec!\n");
+		return 0;
+	}
+	return dword;
+
+}
+
+static uint32_t verb_data[] = {
+#if 0
+	0x00172001,
+	0x001721e6,
+	0x00172200,
+	0x00172300,
+#endif
+
+	0x01471c10,
+	0x01471d44,
+	0x01471e01,
+	0x01471f01,
+//1
+	0x01571c12,
+	0x01571d14,
+	0x01571e01,
+	0x01571f01,
+//2
+	0x01671c11,
+	0x01671d60,
+	0x01671e01,
+	0x01671f01,
+//3
+	0x01771c14,
+	0x01771d20,
+	0x01771e01,
+	0x01771f01,
+//4
+	0x01871c30,
+	0x01871d9c,
+	0x01871ea1,
+	0x01871f01,
+//5
+	0x01971c40,
+	0x01971d9c,
+	0x01971ea1,
+	0x01971f02,
+//6
+	0x01a71c31,
+	0x01a71d34,
+	0x01a71e81,
+	0x01a71f01,
+//7
+	0x01b71c1f,
+	0x01b71d44,
+	0x01b71e21,
+	0x01b71f02,
+//8
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+//9
+	0x01d71c3e,
+	0x01d71d01,
+	0x01d71e83,
+	0x01d71f99,
+//10
+	0x01e71c20,
+	0x01e71d41,
+	0x01e71e45,
+	0x01e71f01,
+//11
+	0x01f71c50,
+	0x01f71d91,
+	0x01f71ec5,
+	0x01f71f01,
+};
+
+static unsigned find_verb(uint32_t viddid, uint32_t **verb)
+{
+	if(viddid != 0x10ec0880) return 0;
+	*verb =  (uint32_t *)verb_data;
+	return sizeof(verb_data)/sizeof(uint32_t);
+}
+
+
+static void codec_init(uint8_t *base, int addr)
+{
+	uint32_t dword;
+	uint32_t *verb;
+	unsigned verb_size;
+	int i;
+
+	/* 1 */
+	do {
+		dword = readl(base + 0x68);
+	} while (dword & 1);
+
+	dword = (addr<<28) | 0x000f0000;
+	writel(dword, base + 0x60);
+
+	do {
+		dword = readl(base + 0x68);
+	} while ((dword & 3)!=2);
+
+	dword = readl(base + 0x64);
+
+	/* 2 */
+	printk_debug("codec viddid: %08x\n", dword);
+	verb_size = find_verb(dword, &verb);
+
+	if(!verb_size) {
+		printk_debug("No verb!\n");
+		return;
+	}
+
+	printk_debug("verb_size: %d\n", verb_size);
+	/* 3 */
+	for(i=0; i<verb_size; i++) {
+		do {
+			dword = readl(base + 0x68);
+		} while (dword & 1);
+
+		writel(verb[i], base + 0x60);
+
+		do {
+			dword = readl(base + 0x68);
+		} while ((dword & 3) != 2);
+	}
+	printk_debug("verb loaded!\n");
+}
+
+static void codecs_init(uint8_t *base, uint32_t codec_mask)
+{
+	int i;
+	for(i=2; i>=0; i--) {
+		if( codec_mask & (1<<i) )
+			codec_init(base, i);
+	}
+}
+
+static void aza_init(struct device *dev)
+{
+	uint8_t *base;
+	struct resource *res;
+	uint32_t codec_mask;
+
+	res = find_resource(dev, 0x10);
+	if(!res)
+		return;
+
+	base =(uint8_t *) res->base;
+	printk_debug("base = %08x\n", base);
+
+	codec_mask = codec_detect(base);
+
+	if(codec_mask) {
+		printk_debug("codec_mask = %02x\n", codec_mask);
+		codecs_init(base, codec_mask);
+	}
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations aza_audio_ops  = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+//	.enable		= mcp55_enable,
+	.init		= aza_init,
+	.scan_bus	= 0,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver azaaudio_driver __pci_driver = {
+	.ops	= &aza_audio_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_AZA,
+};
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static unsigned get_sbdn(unsigned bus)
+{
+	device_t dev;
+
+	/* Find the device.
+	 */
+	dev = pci_locate_device_on_bus(
+		PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT),
+		bus);
+
+	return (dev>>15) & 0x1f;
+
+}
+
+static void hard_reset(void)
+{
+	set_bios_reset();
+
+	/* full reset */
+	outb(0x0a, 0x0cf9);
+	outb(0x0e, 0x0cf9);
+}
+static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+{
+/* default value for mcp55 is good */
+	/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+
+}
+
+static void soft_reset(void)
+{
+	set_bios_reset();
+#if 1
+	/* link reset */
+	outb(0x02, 0x0cf9);
+	outb(0x06, 0x0cf9);
+#endif
+}
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,427 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static int set_ht_link_mcp55(uint8_t ht_c_num)
+{
+	unsigned vendorid = 0x10de;
+	unsigned val = 0x01610109;
+	/* Nvidia mcp55 hardcode, hw can not set it automatically */
+	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
+}
+
+static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
+{
+	int i;
+
+	unsigned val;
+
+	val = inl(control);
+	val &= 0xfffffffe;
+	outl(val, control);
+
+	outl(0, index); //index
+	for(i = 0; i < max; i++) {
+		unsigned long reg;
+		reg = register_values[i];
+		outl(reg, where);
+	}
+
+	val = inl(control);
+	val |= 1;
+	outl(val, control);
+
+}
+
+/* SIZE 0x100 */
+#define ANACTRL_IO_BASE	0x2800
+#define ANACTRL_REG_POS	0x68
+
+/* SIZE 0x100 */
+#define SYSCTRL_IO_BASE	0x2400
+#define SYSCTRL_REG_POS	0x64
+
+/* SIZE 0x100 */
+#define ACPICTRL_IO_BASE	0x2000
+#define ACPICTRL_REG_POS	0x60
+
+/*
+	16 1 1 1 1 8 :0
+	16 0 4 0 0 8 :1
+	16 0 4 2 2 4 :2
+	 4 4 4 4 4 8 :3
+	 8 8 4 0 0 8 :4
+	 8 0 4 4 4 8 :5
+*/
+
+#ifndef MCP55_PCI_E_X_0
+	#define MCP55_PCI_E_X_0	4
+#endif
+#ifndef MCP55_PCI_E_X_1
+	#define MCP55_PCI_E_X_1	4
+#endif
+#ifndef MCP55_PCI_E_X_2
+	#define MCP55_PCI_E_X_2	4
+#endif
+#ifndef MCP55_PCI_E_X_3
+	#define MCP55_PCI_E_X_3	4
+#endif
+
+#ifndef MCP55_USE_NIC
+	#define MCP55_USE_NIC	0
+#endif
+
+#ifndef MCP55_USE_AZA
+	#define MCP55_USE_AZA	0
+#endif
+
+#define MCP55_CHIP_REV	3
+
+static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
+{
+
+	static const unsigned int ctrl_devport_conf[] = {
+		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
+		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
+		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
+	};
+
+	int j;
+	for(j = 0; j < mcp55_num; j++ ) {
+		setup_resource_map_offset(ctrl_devport_conf,
+			sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+	}
+}
+
+static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
+{
+
+	static const unsigned int ctrl_devport_conf_clear[] = {
+		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
+	};
+
+	int j;
+	for(j = 0; j < mcp55_num; j++ ) {
+		setup_resource_map_offset(ctrl_devport_conf_clear,
+			sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+	}
+
+
+}
+static void delayx(uint8_t value) {
+#if 1
+	int i;
+	for(i=0;i<0x8000;i++) {
+		outb(value, 0x80);
+	}
+#endif
+}
+
+static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
+{
+	uint32_t tgio_ctrl;
+	uint32_t pll_ctrl;
+	uint32_t dword;
+	int i;
+	device_t dev;
+	dev = PCI_DEV(busnx, devnx+1, 1);
+	dword = pci_read_config32(dev, 0xe4);
+	dword |= 0x3f0; // disable it at first
+	pci_write_config32(dev, 0xe4, dword);
+
+	for(i=0; i<3; i++) {
+		tgio_ctrl = inl(anactrl_io_base + 0xcc);
+		tgio_ctrl &= ~(3<<9);
+		tgio_ctrl |= (i<<9);
+		outl(tgio_ctrl, anactrl_io_base + 0xcc);
+		pll_ctrl = inl(anactrl_io_base + 0x30);
+		pll_ctrl |= (1<<31);
+		outl(pll_ctrl, anactrl_io_base + 0x30);
+		do {
+			pll_ctrl = inl(anactrl_io_base + 0x30);
+		} while (!(pll_ctrl & 1));
+	}
+	tgio_ctrl = inl(anactrl_io_base + 0xcc);
+	tgio_ctrl &= ~((7<<4)|(1<<8));
+	tgio_ctrl |= (pci_e_x<<4)|(1<<8);
+	outl(tgio_ctrl, anactrl_io_base + 0xcc);
+
+//	wait 100us
+	delayx(1);
+
+	dword = pci_read_config32(dev, 0xe4);
+	dword &= ~(0x3f0); // enable
+	pci_write_config32(dev, 0xe4, dword);
+
+//	need to wait 100ms
+	delayx(1000);
+}
+
+static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
+{
+
+    static const unsigned int ctrl_conf_1[] = {
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
+
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
+
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
+
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
+	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+
+	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
+	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+    };
+
+    static const unsigned int ctrl_conf_1_1[] = {
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
+    };
+
+
+    static const unsigned int ctrl_conf_mcp55_only[] = {
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
+
+	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
+
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
+
+#if MCP55_USE_AZA == 1
+	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
+
+//	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
+#endif
+// play a while with GPIO in MCP55
+#ifdef MCP55_MB_SETUP
+	MCP55_MB_SETUP
+#endif
+
+#if MCP55_USE_AZA == 1
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
+#endif
+
+
+    };
+
+    static const unsigned int ctrl_conf_master_only[] = {
+
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
+
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
+
+	//Master MCP55 ????YHLU
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
+
+    };
+
+    static const unsigned int ctrl_conf_2[] = {
+	/* I didn't put pcie related stuff here */
+
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
+
+	RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
+
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
+
+
+#if MCP55_USE_NIC == 1
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
+
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
+#endif
+
+    };
+
+
+	int j, i;
+
+	for(j=0; j<mcp55_num; j++) {
+		mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
+
+		setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+		for(i=0; i<3; i++) { // three SATA
+			setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
+				PCI_DEV(busn[j], devn[j], i), io_base[j]);
+		}
+		if(busn[j] == 0) {
+			setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+		}
+
+		if( (busn[j] == 0) && (mcp55_num>1) ) {
+			setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+		}
+
+		setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+
+	}
+
+#if 0
+	for(j=0; j< mcp55_num; j++) {
+		// PCI-E (XSPLL) SS table 0x40, x044, 0x48
+		// SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
+		// CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
+			io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
+			io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
+			io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
+	}
+#endif
+
+}
+
+#ifndef HT_CHAIN_NUM_MAX
+
+#define HT_CHAIN_NUM_MAX	4
+#define HT_CHAIN_BUSN_D	0x40
+#define HT_CHAIN_IOBASE_D	0x4000
+
+#endif
+
+static int mcp55_early_setup_x(void)
+{
+	/*find out how many mcp55 we have */
+	unsigned busn[HT_CHAIN_NUM_MAX];
+	unsigned devn[HT_CHAIN_NUM_MAX];
+	unsigned io_base[HT_CHAIN_NUM_MAX];
+	/*
+		FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation
+		Need to use same trick about pci1234 to verify node/link connection
+	*/
+	unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 };
+	int mcp55_num = 0;
+	unsigned busnx;
+	unsigned devnx;
+	int ht_c_index,j;
+
+	/* FIXME: multi pci segment handling */
+
+	/* Any system that only have IO55 without MCP55? */
+	for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) {
+		busnx = ht_c_index * HT_CHAIN_BUSN_D;
+		for(devnx=0;devnx<0x20;devnx++) {
+			uint32_t id;
+			device_t dev;
+			dev = PCI_DEV(busnx, devnx, 0);
+			id = pci_read_config32(dev, PCI_VENDOR_ID);
+			if(id == 0x036910de) {
+				busn[mcp55_num] = busnx;
+				devn[mcp55_num] = devnx;
+				io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55
+				mcp55_num++;
+				if(mcp55_num == MCP55_NUM) goto out;
+				break; // only one MCP55 on one chain
+			}
+		}
+	}
+
+out:
+	print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n");
+
+	mcp55_early_set_port(mcp55_num, busn, devn, io_base);
+	mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
+
+	mcp55_early_clear_port(mcp55_num, busn, devn, io_base);
+
+//	set_ht_link_mcp55(HT_CHAIN_NUM_MAX);
+
+	return 0;
+
+}
+
+
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static const unsigned int pcie_ss_tbl[] = {
+	0x0C504103f,
+	0x0C504103f,
+	0x0C504103f,
+	0x0C5042040,
+	0x0C5042040,
+	0x0C5042040,
+	0x0C5043041,
+	0x0C5043041,
+	0x0C5043041,
+	0x0C5043041,
+	0x0C5044042,
+	0x0C5044042,
+	0x0C5044042,
+	0x0C5045043,
+	0x0C5045043,
+	0x0C5045043,
+	0x0C5045043,
+	0x0C5045043,
+	0x0C5046044,
+	0x0C5046044,
+	0x0C5046044,
+	0x0C5046044,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5048046,
+	0x0C5048046,
+	0x0C5048046,
+	0x0C5048046,
+	0x0C5049047,
+	0x0C5049047,
+	0x0C5049047,
+	0x0C504a048,
+	0x0C504a048,
+	0x0C504b049,
+	0x0C504b049,
+	0x0C504a048,
+	0x0C504a048,
+	0x0C5049047,
+	0x0C5049047,
+	0x0C5048046,
+	0x0C5048046,
+	0x0C5048046,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5047045,
+	0x0C5046044,
+	0x0C5046044,
+	0x0C5046044,
+	0x0C5046044,
+	0x0C5045043,
+	0x0C5045043,
+	0x0C5045043,
+	0x0C5044042,
+	0x0C5044042,
+	0x0C5044042,
+	0x0C5043041,
+	0x0C5043041,
+	0x0C5042040,
+	0x0C5042040,
+};
+static const unsigned int sata_ss_tbl[] = {
+	0x0c9044042,
+	0x0c9044042,
+	0x0c9044042,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9046044,
+	0x0c9046044,
+	0x0c9046044,
+	0x0c9046044,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9048046,
+	0x0c9048046,
+	0x0c9048046,
+	0x0c9048046,
+	0x0c9049047,
+	0x0c9049047,
+	0x0c9049047,
+	0x0c9049047,
+	0x0c904a048,
+	0x0c904a048,
+	0x0c904a048,
+	0x0c904a048,
+	0x0c904b049,
+	0x0c904b049,
+	0x0c904b049,
+	0x0c904b049,
+	0x0c904b049,
+	0x0c904b049,
+	0x0c904a048,
+	0x0c904a048,
+	0x0c904a048,
+	0x0c904a048,
+	0x0c9049047,
+	0x0c9049047,
+	0x0c9049047,
+	0x0c9049047,
+	0x0c9048046,
+	0x0c9048046,
+	0x0c9048046,
+	0x0c9048046,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9047045,
+	0x0c9046044,
+	0x0c9046044,
+	0x0c9046044,
+	0x0c9046044,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9045043,
+	0x0c9044042,
+	0x0c9044042,
+	0x0c9044042,
+};
+
+static const unsigned int cpu_ss_tbl[] = {
+	0x0C5038036,
+	0x0C5038036,
+	0x0C5038036,
+	0x0C5037035,
+	0x0C5037035,
+	0x0C5037035,
+	0x0C5037035,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5034032,
+	0x0C5034032,
+	0x0C5034032,
+	0x0C5034032,
+	0x0C5034032,
+	0x0C5034032,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5035033,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5036034,
+	0x0C5037035,
+	0x0C5037035,
+	0x0C5037035,
+	0x0C5037035,
+	0x0C5038036,
+	0x0C5038036,
+	0x0C5038036,
+	0x0C5038036,
+	0x0C5039037,
+	0x0C5039037,
+	0x0C5039037,
+	0x0C5039037,
+	0x0C503a038,
+	0x0C503a038,
+	0x0C503a038,
+	0x0C503a038,
+	0x0C503b039,
+	0x0C503b039,
+	0x0C503b039,
+	0x0C503b039,
+	0x0C503b039,
+	0x0C503a038,
+	0x0C503a038,
+	0x0C503a038,
+	0x0C503a038,
+	0x0C503a038,
+	0x0C5039037,
+	0x0C5039037,
+	0x0C5039037,
+	0x0C5039037,
+};
+
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "mcp55_smbus.h"
+
+#define SMBUS0_IO_BASE	0x1000
+#define SMBUS1_IO_BASE	(0x1000+(1<<8))
+/*SIZE 0x40 */
+
+static void enable_smbus(void)
+{
+	device_t dev;
+	dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
+#if 0
+	if (dev == PCI_DEV_INVALID) {
+		die("SMBUS controller not found\r\n");
+	}
+
+	print_debug("SMBus controller enabled\r\n");
+#endif
+	/* set smbus iobase */
+	pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
+	pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1);
+	/* Set smbus iospace enable */
+	pci_write_config16(dev, 0x4, 0x01);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
+	outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
+}
+
+static int smbus_recv_byte(unsigned device)
+{
+	return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
+}
+static int smbus_send_byte(unsigned device, unsigned char val)
+{
+	return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
+}
+static int smbus_read_byte(unsigned device, unsigned address)
+{
+	return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
+}
+static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+{
+	return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
+}
+
+static int smbusx_recv_byte(unsigned smb_index, unsigned device)
+{
+	return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device);
+}
+static int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val)
+{
+	return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val);
+}
+static int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address)
+{
+	return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address);
+}
+static int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val)
+{
+	return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val);
+}
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+	#define MCP55_DEVN_BASE	HT_CHAIN_END_UNITID_BASE
+#else
+	#define MCP55_DEVN_BASE	HT_CHAIN_UNITID_BASE
+#endif
+
+static void mcp55_enable_rom(void)
+{
+	uint8_t byte;
+	uint16_t word;
+	device_t addr;
+
+	/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
+#if 0
+	/*	default MCP55 LPC single */
+	addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
+#else
+//	addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
+	addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0);
+#endif
+
+	/* Set the 4MB enable bit bit */
+	byte = pci_read_config8(addr, 0x88);
+	byte |= 0xff; //256K
+	pci_write_config8(addr, 0x88, byte);
+	byte = pci_read_config8(addr, 0x8c);
+	byte |= 0xff; //1M
+	pci_write_config8(addr, 0x8c, byte);
+	word = pci_read_config16(addr, 0x90);
+	word |= 0x7fff; //15M
+	pci_write_config16(addr, 0x90, word);
+}

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+	#define MCP55_DEVN_BASE	HT_CHAIN_END_UNITID_BASE
+#else
+	#define MCP55_DEVN_BASE	HT_CHAIN_UNITID_BASE
+#endif
+
+#define EHCI_BAR_INDEX	0x10
+#define EHCI_BAR	0xFEF00000
+#define EHCI_DEBUG_OFFSET	0x98
+
+static void set_debug_port(unsigned port)
+{
+	uint32_t dword;
+	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74);
+	dword &= ~(0xf<<12);
+	dword |= (port<<12);
+	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74, dword);
+
+}
+
+static void mcp55_enable_usbdebug_direct(unsigned port)
+{
+	set_debug_port(port);
+	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), EHCI_BAR_INDEX, EHCI_BAR);
+	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x04, 0x2); // mem space enabe
+}
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ht.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ht.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ht.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations ht_ops  = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init		= 0,
+	.scan_bus	= 0,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver ht_driver __pci_driver = {
+	.ops	= &ht_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_HT,
+};
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ide.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ide.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_ide.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static void ide_init(struct device *dev)
+{
+	struct southbridge_nvidia_mcp55_config *conf;
+	/* Enable ide devices so the linux ide driver will work */
+	uint32_t dword;
+	uint16_t word;
+	uint8_t byte;
+	conf = dev->chip_info;
+
+	word = pci_read_config16(dev, 0x50);
+	/* Ensure prefetch is disabled */
+	word &= ~((1 << 15) | (1 << 13));
+	if (conf->ide1_enable) {
+		/* Enable secondary ide interface */
+		word |= (1<<0);
+		printk_debug("IDE1 \t");
+	}
+	if (conf->ide0_enable) {
+		/* Enable primary ide interface */
+		word |= (1<<1);
+		printk_debug("IDE0\n");
+	}
+
+	word |= (1<<12);
+	word |= (1<<14);
+
+	pci_write_config16(dev, 0x50, word);
+
+
+	byte = 0x20 ; // Latency: 64-->32
+	pci_write_config8(dev, 0xd, byte);
+
+	dword = pci_read_config32(dev, 0xf8);
+	dword |= 12;
+	pci_write_config32(dev, 0xf8, dword);
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);
+#endif
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations ide_ops  = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init		= ide_init,
+	.scan_bus	= 0,
+//	.enable		= mcp55_enable,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver ide_driver __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_IDE,
+};
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,402 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * Copyright (C) 2003 SuSE Linux AG
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include <cpu/x86/lapic.h>
+#include "mcp55.h"
+
+#define NMI_OFF	0
+
+struct ioapicreg {
+	unsigned int reg;
+	unsigned int value_low, value_high;
+};
+
+static struct ioapicreg ioapicregvalues[] = {
+#define ALL		(0xff << 24)
+#define NONE		(0)
+#define DISABLED	(1 << 16)
+#define ENABLED		(0 << 16)
+#define TRIGGER_EDGE	(0 << 15)
+#define TRIGGER_LEVEL	(1 << 15)
+#define POLARITY_HIGH	(0 << 13)
+#define POLARITY_LOW	(1 << 13)
+#define PHYSICAL_DEST	(0 << 11)
+#define LOGICAL_DEST	(1 << 11)
+#define ExtINT		(7 << 8)
+#define NMI		(4 << 8)
+#define SMI		(2 << 8)
+#define INT		(1 << 8)
+	/* IO-APIC virtual wire mode configuration */
+	/* mask, trigger, polarity, destination, delivery, vector */
+	{   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
+	{   1, DISABLED, NONE},
+	{   2, DISABLED, NONE},
+	{   3, DISABLED, NONE},
+	{   4, DISABLED, NONE},
+	{   5, DISABLED, NONE},
+	{   6, DISABLED, NONE},
+	{   7, DISABLED, NONE},
+	{   8, DISABLED, NONE},
+	{   9, DISABLED, NONE},
+	{  10, DISABLED, NONE},
+	{  11, DISABLED, NONE},
+	{  12, DISABLED, NONE},
+	{  13, DISABLED, NONE},
+	{  14, DISABLED, NONE},
+	{  15, DISABLED, NONE},
+	{  16, DISABLED, NONE},
+	{  17, DISABLED, NONE},
+	{  18, DISABLED, NONE},
+	{  19, DISABLED, NONE},
+	{  20, DISABLED, NONE},
+	{  21, DISABLED, NONE},
+	{  22, DISABLED, NONE},
+	{  23, DISABLED, NONE},
+	/* Be careful and don't write past the end... */
+};
+
+static void setup_ioapic(unsigned long ioapic_base)
+{
+	int i;
+	unsigned long value_low, value_high;
+//	unsigned long ioapic_base = 0xfec00000;
+	volatile unsigned long *l;
+	struct ioapicreg *a = ioapicregvalues;
+
+	ioapicregvalues[0].value_high = lapicid()<<(56-32);
+
+	l = (unsigned long *) ioapic_base;
+
+	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+	     i++, a++) {
+		l[0] = (a->reg * 2) + 0x10;
+		l[4] = a->value_low;
+		value_low = l[4];
+		l[0] = (a->reg *2) + 0x11;
+		l[4] = a->value_high;
+		value_high = l[4];
+		if ((i==0) && (value_low == 0xffffffff)) {
+			printk_warning("IO APIC not responding.\n");
+			return;
+		}
+		printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
+			    a->reg, a->value_low, a->value_high);
+	}
+}
+
+// 0x7a or e3
+#define PREVIOUS_POWER_STATE	0x7A
+
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define SLOW_CPU_OFF	0
+#define SLOW_CPU__ON	1
+
+#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL	MAINBOARD_POWER_ON
+#endif
+
+static void lpc_common_init(device_t dev)
+{
+	uint8_t byte;
+	uint32_t dword;
+
+	/* IO APIC initialization */
+	byte = pci_read_config8(dev, 0x74);
+	byte |= (1<<0); // enable APIC
+	pci_write_config8(dev, 0x74, byte);
+	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+
+	setup_ioapic(dword);
+
+}
+
+static void lpc_slave_init(device_t dev)
+{
+	lpc_common_init(dev);
+}
+
+#if 0
+static void enable_hpet(struct device *dev)
+{
+	unsigned long hpet_address;
+
+	pci_write_config32(dev,0x44, 0xfed00001);
+	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
+	printk_debug("enabling HPET @0x%x\n", hpet_address);
+}
+#endif
+
+static void lpc_init(device_t dev)
+{
+	uint8_t byte;
+	uint8_t byte_old;
+	int on;
+	int nmi_option;
+
+	lpc_common_init(dev);
+
+#if 0
+	/* posted memory write enable */
+	byte = pci_read_config8(dev, 0x46);
+	pci_write_config8(dev, 0x46, byte | (1<<0));
+
+#endif
+	/* power after power fail */
+
+#if 1
+	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	get_option(&on, "power_on_after_fail");
+	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
+	byte &= ~0x40;
+	if (!on) {
+		byte |= 0x40;
+	}
+	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
+	printk_info("set power %s after power fail\n", on?"on":"off");
+#endif
+	/* Throttle the CPU speed down for testing */
+	on = SLOW_CPU_OFF;
+	get_option(&on, "slow_cpu");
+	if(on) {
+		uint16_t pm10_bar;
+		uint32_t dword;
+		pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
+		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
+		dword = inl(pm10_bar + 0x10);
+		on = 8-on;
+		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
+				(on*12)+(on>>1),(on&1)*5);
+	}
+
+#if 0
+// default is enabled
+	/* Enable Port 92 fast reset */
+	byte = pci_read_config8(dev, 0xe8);
+	byte |= ~(1 << 3);
+	pci_write_config8(dev, 0xe8, byte);
+#endif
+
+	/* Enable Error reporting */
+	/* Set up sync flood detected */
+	byte = pci_read_config8(dev, 0x47);
+	byte |= (1 << 1);
+	pci_write_config8(dev, 0x47, byte);
+
+	/* Set up NMI on errors */
+	byte = inb(0x70); // RTC70
+	byte_old = byte;
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte &= ~(1 << 7); /* set NMI */
+	} else {
+		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+	}
+	if( byte != byte_old) {
+		outb(0x70, byte);
+	}
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	/* Initialize the High Precision Event Timers */
+//	enable_hpet(dev);
+
+}
+
+static void mcp55_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+	unsigned long index;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
+
+	/* Add an extra subtractive resource for both memory and I/O */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ * This function is call by the global enable_resources() indirectly via the
+ * device_operation::enable_resources() method of devices.
+ *
+ * Indirect mutual recursion:
+ *      enable_childrens_resources() -> enable_resources()
+ *      enable_resources() -> device_operation::enable_resources()
+ *      device_operation::enable_resources() -> enable_children_resources()
+ */
+static void mcp55_lpc_enable_childrens_resources(device_t dev)
+{
+	unsigned link;
+	uint32_t reg, reg_var[4];
+	int i;
+	int var_num = 0;
+
+	reg = pci_read_config32(dev, 0xa0);
+
+	for (link = 0; link < dev->links; link++) {
+		device_t child;
+		for (child = dev->link[link].children; child; child = child->sibling) {
+			enable_resources(child);
+			if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+				for(i=0;i<child->resources;i++) {
+					struct resource *res;
+					unsigned long base, end; // don't need long long
+					res = &child->resource[i];
+					if(!(res->flags & IORESOURCE_IO)) continue;
+					base = res->base;
+					end = resource_end(res);
+					printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
+					switch(base) {
+					case 0x3f8: // COM1
+						reg |= (1<<0);	break;
+					case 0x2f8: // COM2
+						reg |= (1<<1);  break;
+					case 0x378: // Parallal 1
+						reg |= (1<<24); break;
+					case 0x3f0: // FD0
+						reg |= (1<<20); break;
+					case 0x220:  // Aduio 0
+						reg |= (1<<8);	break;
+					case 0x300:  // Midi 0
+						reg |= (1<<12);	break;
+					}
+					if( (base == 0x290) || (base >= 0x400)) {
+						if(var_num>=4) continue; // only 4 var ; compact them ?
+						reg |= (1<<(28+var_num));
+						reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0xa0, reg);
+	for(i=0;i<var_num;i++) {
+		pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
+	}
+
+
+}
+
+static void mcp55_lpc_enable_resources(device_t dev)
+{
+	pci_dev_enable_resources(dev);
+	mcp55_lpc_enable_childrens_resources(dev);
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources	= mcp55_lpc_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= mcp55_lpc_enable_resources,
+	.init		= lpc_init,
+	.scan_bus	= scan_static_bus,
+//	.enable		= mcp55_enable,
+	.ops_pci	= &lops_pci,
+};
+static struct pci_driver lpc_driver __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
+};
+
+static struct pci_driver lpc_driver_pro __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
+};
+
+static struct pci_driver lpc_driver_lpc2 __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
+};
+static struct pci_driver lpc_driver_lpc3 __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
+};
+static struct pci_driver lpc_driver_lpc4 __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
+};
+static struct pci_driver lpc_driver_lpc5 __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
+};
+static struct pci_driver lpc_driver_lpc6 __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
+};
+
+static struct device_operations lpc_slave_ops  = {
+	.read_resources	= mcp55_lpc_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init		= lpc_slave_init,
+//	.enable		= mcp55_enable,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver lpc_driver_slave __pci_driver = {
+	.ops	= &lpc_slave_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,
+};

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_nic.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_nic.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_nic.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,211 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "mcp55.h"
+
+static int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
+{
+	uint32_t dword;
+	unsigned loop = 0x100;
+	writel(0x8000, base+0x190); //Clear MDIO lock bit
+	mdelay(1);
+	dword = readl(base+0x190);
+	if(dword & (1<<15)) return -1;
+
+	writel(1, base+0x180);
+	writel((phy_addr<<5) | (phy_reg),base + 0x190);
+	do{
+		dword = readl(base + 0x190);
+		if(--loop==0) return -4;
+	} while ((dword & (1<<15)) );
+
+	dword = readl(base + 0x180);
+	if(dword & 1) return -3;
+
+	dword = readl(base + 0x194);
+
+	return dword;
+
+}
+
+static int phy_detect(uint8_t *base)
+{
+	uint32_t dword;
+	int i;
+	int val;
+	unsigned id;
+	dword = readl(base+0x188);
+	dword &= ~(1<<20);
+	writel(dword, base+0x188);
+
+	phy_read(base, 0, 1);
+
+	for(i=1; i<=32; i++) {
+		int phyaddr = i & 0x1f;
+		val = phy_read(base, phyaddr, 1);
+		if(val<0) continue;
+		if((val & 0xffff) == 0xfffff) continue;
+		if((val & 0xffff) == 0) continue;
+		if(!(val & 1)) {
+			break; // Ethernet PHY
+		}
+		val = phy_read(base, phyaddr, 3);
+		if (val < 0 || val == 0xffff) continue;
+		id = val & 0xfc00;
+		val = phy_read(base, phyaddr, 2);
+		if (val < 0 || val == 0xffff) continue;
+		id |= ((val & 0xffff)<<16);
+		printk_debug("MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
+//		if((id == 0xe0180000) || (id==0x0032cc00))
+			break;
+	}
+
+	if(i>32) {
+		printk_debug("MCP55 MAC PHY not found\n");
+	}
+
+}
+static void nic_init(struct device *dev)
+{
+	uint32_t dword, old;
+	uint32_t mac_h, mac_l;
+	int eeprom_valid = 0;
+	struct southbridge_nvidia_mcp55_config *conf;
+
+	static uint32_t nic_index = 0;
+
+	uint8_t *base;
+	struct resource *res;
+
+	res = find_resource(dev, 0x10);
+
+	if(!res) return;
+
+	base = res->base;
+
+	phy_detect(base);
+
+#define NvRegPhyInterface	0xC0
+#define PHY_RGMII	0x10000000
+
+	writel(PHY_RGMII, base + NvRegPhyInterface);
+
+	conf = dev->chip_info;
+
+	if(conf->mac_eeprom_smbus != 0) {
+//	read MAC address from EEPROM at first
+		struct device *dev_eeprom;
+		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
+
+		if(dev_eeprom) {
+		//	if that is valid we will use that
+			unsigned char dat[6];
+			int status;
+			int i;
+			for(i=0;i<6;i++) {
+				status = smbus_read_byte(dev_eeprom, i);
+				if(status < 0) break;
+				dat[i] = status & 0xff;
+			}
+			if(status >= 0) {
+				mac_l = 0;
+				for(i=3;i>=0;i--) {
+					mac_l <<= 8;
+					mac_l += dat[i];
+				}
+				if(mac_l != 0xffffffff) {
+					mac_l += nic_index;
+					mac_h = 0;
+					for(i=5;i>=4;i--) {
+						mac_h <<= 8;
+						mac_h += dat[i];
+					}
+					eeprom_valid = 1;
+				}
+			}
+		}
+	}
+//	if that is invalid we will read that from romstrap
+	if(!eeprom_valid) {
+		unsigned long mac_pos;
+		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
+		mac_l = readl(mac_pos) + nic_index; // overflow?
+		mac_h = readl(mac_pos + 4);
+
+	}
+#if 1
+//	set that into NIC MMIO
+#define NvRegMacAddrA	0xA8
+#define NvRegMacAddrB	0xAC
+	writel(mac_l, base + NvRegMacAddrA);
+	writel(mac_h, base + NvRegMacAddrB);
+#else
+//	set that into NIC
+	pci_write_config32(dev, 0xa8, mac_l);
+	pci_write_config32(dev, 0xac, mac_h);
+#endif
+
+	nic_index++;
+
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);// it will init option rom
+#endif
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations nic_ops  = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init		= nic_init,
+	.scan_bus	= 0,
+//	.enable		= mcp55_enable,
+	.ops_pci	= &lops_pci,
+};
+static struct pci_driver nic_driver __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_NIC,
+};
+static struct pci_driver nic_bridge_driver __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE,
+};

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pci.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pci.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pci.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,107 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static void pci_init(struct device *dev)
+{
+
+	uint32_t dword;
+	uint16_t word;
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+	device_t pci_domain_dev;
+	struct resource *mem1, *mem2;
+#endif
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (1<<30); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+#if 1
+	//only need (a01,xx]
+	word = pci_read_config16(dev, 0x48);
+	word |= (1<<0); /* MRL2MRM */
+	word |= (1<<2); /* MR2MRM */
+	pci_write_config16(dev, 0x48, word);
+#endif
+
+#if 1
+	dword = pci_read_config32(dev, 0x4c);
+	dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
+	pci_write_config32(dev, 0x4c, dword);
+#endif
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+	pci_domain_dev = dev->bus->dev;
+	while(pci_domain_dev) {
+		if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;
+		pci_domain_dev = pci_domain_dev->bus->dev;
+	}
+
+	if(!pci_domain_dev) return; // impossiable
+	mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
+	mem2 = find_resource(pci_domain_dev, 2); // mem
+	if(mem1->base > mem2->base) {
+		dword = mem2->base  & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
+	} else {
+		dword = mem1->base  & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
+	}
+#else
+	dword = dev_root.resource[1].base & (0xffff0000UL);
+	printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
+#endif
+	printk_debug("[0x50] <-- 0x%08x\n", dword);
+	pci_write_config32(dev, 0x50, dword); //TOM
+
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= 0,
+};
+
+static struct device_operations pci_ops  = {
+	.read_resources	= pci_bus_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init		= pci_init,
+	.scan_bus	= pci_scan_bridge,
+//	.enable		= mcp55_enable,
+	.reset_bus	= pci_bus_reset,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver pci_driver __pci_driver = {
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_PCI,
+};
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pcie.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pcie.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_pcie.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static void pcie_init(struct device *dev)
+{
+
+	/* Enable pci error detecting */
+	uint32_t dword;
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (1<<30); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= 0,
+};
+
+static struct device_operations pcie_ops  = {
+	.read_resources	= pci_bus_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init		= pcie_init,
+	.scan_bus	= pci_scan_bridge,
+//	.enable		= mcp55_enable,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver pciebc_driver __pci_driver = {
+	.ops	= &pcie_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C,
+};
+static struct pci_driver pciee_driver __pci_driver = {
+	.ops	= &pcie_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E,
+};
+static struct pci_driver pciea_driver __pci_driver = {
+	.ops	= &pcie_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A,
+};
+static struct pci_driver pcief_driver __pci_driver = {
+	.ops	= &pcie_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F,
+};
+static struct pci_driver pcied_driver __pci_driver = {
+	.ops	= &pcie_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D,
+};
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_reset.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_reset.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFFF) << 20) | \
+	(((DEV) & 0x1F) << 15) | \
+	(((FN)  & 0x7) << 12))
+
+typedef unsigned device_t;
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+	unsigned addr;
+	addr = (dev>>4) | where;
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+	addr = (dev>>4) | where;
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
+	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+}
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_sata.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_sata.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static void sata_init(struct device *dev)
+{
+	uint32_t dword;
+
+	struct southbridge_nvidia_mcp55_config *conf;
+	conf = dev->chip_info;
+
+	dword = pci_read_config32(dev, 0x50);
+	/* Ensure prefetch is disabled */
+	dword &= ~((1 << 15) | (1 << 13));
+	if(conf) {
+		if (conf->sata1_enable) {
+			/* Enable secondary SATA interface */
+			dword |= (1<<0);
+			printk_debug("SATA S \t");
+		}
+		if (conf->sata0_enable) {
+			/* Enable primary SATA interface */
+			dword |= (1<<1);
+			printk_debug("SATA P \n");
+		}
+	} else {
+		dword |= (1<<1) | (1<<0);
+		printk_debug("SATA P and S \n");
+	}
+
+
+#if 1
+	dword &= ~(0x1f<<24);
+	dword |= (0x15<<24);
+#endif
+	pci_write_config32(dev, 0x50, dword);
+
+	dword = pci_read_config32(dev, 0xf8);
+	dword |= 2;
+	pci_write_config32(dev, 0xf8, dword);
+
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations sata_ops = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+//	.enable		= mcp55_enable,
+	.init		= sata_init,
+	.scan_bus	= 0,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver sata0_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_SATA0,
+};
+
+static struct pci_driver sata1_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_SATA1,
+};

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/smbus.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include "mcp55.h"
+#include "mcp55_smbus.h"
+
+static int lsmbus_recv_byte(device_t dev)
+{
+	unsigned device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.u.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
+
+	return do_smbus_recv_byte(res->base, device);
+}
+
+static int lsmbus_send_byte(device_t dev, uint8_t val)
+{
+	unsigned device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.u.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
+
+	return do_smbus_send_byte(res->base, device, val);
+}
+
+static int lsmbus_read_byte(device_t dev, uint8_t address)
+{
+	unsigned device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.u.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
+
+	return do_smbus_read_byte(res->base, device, address);
+}
+
+static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
+{
+	unsigned device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.u.i2c.device;
+	pbus = get_pbus_smbus(dev);
+
+	res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
+
+	return do_smbus_write_byte(res->base, device, address, val);
+}
+static struct smbus_bus_operations lops_smbus_bus = {
+	.recv_byte	= lsmbus_recv_byte,
+	.send_byte	= lsmbus_send_byte,
+	.read_byte	= lsmbus_read_byte,
+	.write_byte	= lsmbus_write_byte,
+};
+
+#if HAVE_ACPI_TABLES == 1
+unsigned pm_base;
+#endif
+
+static void mcp55_sm_read_resources(device_t dev)
+{
+	struct resource *res;
+	unsigned long index;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.
+		pci_get_resource(dev, index);
+	}
+	compact_resources(dev);
+
+}
+
+static void mcp55_sm_init(device_t dev)
+{
+#if HAVE_ACPI_TABLES == 1
+	struct resource *res;
+
+	res = find_resource(dev, 0x60);
+
+	if (res)
+		pm_base = res->base;
+#endif
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+static struct device_operations smbus_ops = {
+	.read_resources	= mcp55_sm_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init		= mcp55_sm_init,
+	.scan_bus	= scan_static_bus,
+//	.enable		= mcp55_enable,
+	.ops_pci	= &lops_pci,
+	.ops_smbus_bus	= &lops_smbus_bus,
+};
+static struct pci_driver smbus_driver __pci_driver = {
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_SM2,
+};
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT	0x1
+#define SMBHSTPRTCL	0x0
+#define SMBHSTCMD	0x3
+#define SMBXMITADD	0x2
+#define SMBHSTDAT0	0x4
+#define SMBHSTDAT1	0x5
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT	(100*1000*10)
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;
+		if (val == 0) {
+			return 0;
+		}
+		outb(val,smbus_io_base + SMBHSTSTAT);
+	} while(--loops);
+	return -2;
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		if ( (val & 0xff) != 0) {
+			return 0;
+		}
+	} while(--loops);
+	return -3;
+}
+static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
+	smbus_delay();
+	/* set the command/address... */
+	outb(0, smbus_io_base + SMBHSTCMD);
+	smbus_delay();
+	/* byte data recv */
+	outb(0x05, smbus_io_base + SMBHSTPRTCL);
+	smbus_delay();
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	if (global_status_register != 0x80) { // lose check, otherwise it should be 0
+		return -1;
+	}
+	return byte;
+}
+static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+{
+	unsigned global_status_register;
+
+	outb(val, smbus_io_base + SMBHSTDAT0);
+	smbus_delay();
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
+	smbus_delay();
+
+	outb(0, smbus_io_base + SMBHSTCMD);
+	smbus_delay();
+
+	/* set up for a byte data write */
+	outb(0x04, smbus_io_base + SMBHSTPRTCL);
+	smbus_delay();
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;
+	}
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+
+	if (global_status_register != 0x80) {
+		return -1;
+	}
+	return 0;
+}
+static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
+	smbus_delay();
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+	smbus_delay();
+	/* byte data read */
+	outb(0x07, smbus_io_base + SMBHSTPRTCL);
+	smbus_delay();
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	if (global_status_register != 0x80) { // lose check, otherwise it should be 0
+		return -1;
+	}
+	return byte;
+}
+
+
+static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+{
+	unsigned global_status_register;
+
+	outb(val, smbus_io_base + SMBHSTDAT0);
+	smbus_delay();
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
+	smbus_delay();
+
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+	smbus_delay();
+
+	/* set up for a byte data write */
+	outb(0x06, smbus_io_base + SMBHSTPRTCL);
+	smbus_delay();
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;
+	}
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+
+	if (global_status_register != 0x80) {
+		return -1;
+	}
+	return 0;
+}
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations usb_ops = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init		= 0,
+//	.enable		= mcp55_enable,
+	.scan_bus	= 0,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver usb_driver __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_USB,
+};
+

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+#include <usbdebug_direct.h>
+
+extern struct ehci_debug_info dbg_info;
+
+static void usb2_init(struct device *dev)
+{
+	uint32_t dword;
+	dword = pci_read_config32(dev, 0xf8);
+	dword |= 40;
+	pci_write_config32(dev, 0xf8, dword);
+}
+
+static void usb2_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG_DIRECT
+	struct resource *res;
+	unsigned base;
+	unsigned old_debug;
+
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG_DIRECT
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res) return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x40,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem	= lpci_set_subsystem,
+};
+
+static struct device_operations usb2_ops  = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= usb2_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init		= usb2_init,
+//	.enable		= mcp55_enable,
+	.scan_bus	= 0,
+	.ops_pci	= &lops_pci,
+};
+
+static struct pci_driver usb2_driver __pci_driver = {
+	.ops	= &usb2_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_USB2,
+};

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.inc
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.inc	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.inc	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+	.section ".romstrap", "a", @progbits
+
+
+	.globl __romstrap_start
+__romstrap_start:
+rstables:
+	.long 0x2b16d065
+	.long 0x0
+	.long 0x0
+	.long linkedlist
+
+linkedlist:
+	.long 0x0003001C			// 10h
+	.long 0x08000000			// 14h
+	.long 0x00000000			// 18h
+	.long 0xFFFFFFFF			// 1Ch
+
+	.long 0xFFFFFFFF			// 20h
+	.long 0xFFFFFFFF			// 24h
+	.long 0xFFFFFFFF			// 28h
+	.long 0xFFFFFFFF			// 2Ch
+
+	.long 0x81543266			// 30h, MAC address low 4 byte ---> keep it in 0xffffffd0
+	.long 0x000000E0			// 34h, MAC address high 4 byte
+
+	.long 0x002309CE			// 38h, UUID low 4 byte
+	.long 0x00E08100			// 3Ch, UUID high 4 byte
+
+rspointers:
+	.long rstables				// It will be 0xffffffe0
+	.long rstables
+	.long rstables
+	.long rstables
+
+	.globl __romstrap_end
+
+__romstrap_end:
+.previous

Added: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.lds
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.lds	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/romstrap.lds	2007-02-01 00:10:05 UTC (rev 2540)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+SECTIONS {
+	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+	.romstrap (.): {
+		*(.romstrap)
+	}
+}




From bingxunshi at gmail.com  Thu Feb  1 01:10:14 2007
From: bingxunshi at gmail.com (bxshi)
Date: Thu, 1 Feb 2007 08:10:14 +0800
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <20070131180034.GA19669@greenwood>
References: <45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<20070128100901.GB16527@greenwood> <20070131180034.GA19669@greenwood>
Message-ID: <dcdcf0740701311610v4d75e724sdce239d3571f1db@mail.gmail.com>

>
>
> Ping? Can anybody point out problems with the patch or ACK it? I believe
> it's ready to be committed now.


Except mcp55_send_byte may need a little change as yinghai pointed, the
other is ok to me.
with yinghai's code ,MSI ms9282 works fine.
status is :
usb --- ok
sata--- ok
nic -----ok
broadcom nic----on pcie bridge ok

bxshi
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From stefan.reinauer at coresystems.de  Thu Feb  1 01:11:12 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Feb 2007 01:11:12 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
References: <45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
Message-ID: <45C13020.1030103@coresystems.de>

yhlu wrote:
> Good, Please apply at first. we may produce patch regarding with smbus
> for send/receive byte
> ( using CMD byte instead of DAT0)
> 

It's in. please go ahead.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/

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From adam.kaufman at pinnacle.com  Thu Feb  1 01:16:32 2007
From: adam.kaufman at pinnacle.com (Kaufman,  Adam)
Date: Wed, 31 Jan 2007 19:16:32 -0500
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>
	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
Message-ID: <B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local>

Well, I had to do a bit of messing around, but I got both pciutils and
flashrom to compile on my Solaris 10 box. My biggest concern was the
/dev/mem wouldn't allow the same access we get on linux...  here's what
I get:

bash-3.00# ./flashrom
Calibrating delay loop... ok
Can not mmap /dev/mem at 00000000 errno(6):No such device or address

Ideas?

Thanks,
-ak


-----Original Message-----
From: ron minnich [mailto:rminnich at gmail.com] 
Sent: Wednesday, January 31, 2007 4:44 PM
To: Kaufman, Adam
Cc: linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] LinuxBIOS Solaris Dev

I don't see a solaris port as a huge problem. flashrom just uses mmap
and solaris has that.

If you want to try a make and see what happens, I'd like to hear how it
goes.

ron



From kononov195-lbl at yahoo.com  Thu Feb  1 01:30:58 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Wed, 31 Jan 2007 18:30:58 -0600
Subject: [LinuxBIOS] [PATCH] VGA is used before it is initialized
In-Reply-To: <20070131235327.12140.qmail@cdy.org>
References: <45AEB79A.6040308@yahoo.com>
	<45C0DF72.3040800@yahoo.com>	<45C0E48A.4060603@coresystems.de>
	<45C0EFC6.3050007@yahoo.com>	<45C0F371.7000602@coresystems.de>
	<45C127B9.4070603@yahoo.com> <20070131235327.12140.qmail@cdy.org>
Message-ID: <45C134C2.1050802@yahoo.com>

On 01/31/2007 05:53 PM, Peter Stuge wrote:
> +#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_CONSOLE_VGA=1  
> One or two = ? Which is it?

None.

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From stuge-linuxbios at cdy.org  Thu Feb  1 01:33:47 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 1 Feb 2007 01:33:47 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>
	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
	<B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local>
Message-ID: <20070201003348.18620.qmail@cdy.org>

On Wed, Jan 31, 2007 at 07:16:32PM -0500, Kaufman,  Adam wrote:
> Well, I had to do a bit of messing around, but I got both pciutils and
> flashrom to compile on my Solaris 10 box. My biggest concern was the
> /dev/mem wouldn't allow the same access we get on linux...  here's what
> I get:
> 
> bash-3.00# ./flashrom
> Calibrating delay loop... ok
> Can not mmap /dev/mem at 00000000 errno(6):No such device or address
> 
> Ideas?

Dunno about userspace IO in Solaris.

Here are some semi-useful links about device drivers at least:

Writing Device Drivers
http://docs.sun.com/app/docs/doc/816-4854?q=816-4854
(Grab the PDF, I find docs.sun.com to be terribly slow.)

Writing 64-bit Clean Device Drivers for Solaris 10 for x64 Platforms:
A 32-bit and 64-bit Compatible Guide
http://partneradvantage.sun.com/protected/solaris10/adoptionkit/x86/Porting_wp.pdf


//Peter



From svn at openbios.org  Thu Feb  1 01:40:52 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  1 Feb 2007 01:40:52 +0100
Subject: [LinuxBIOS] r2541 - trunk/LinuxBIOSv2/src/include/cpu/amd
Message-ID: <mailman.158.1355071056.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-02-01 01:40:51 +0100 (Thu, 01 Feb 2007)
New Revision: 2541

Modified:
   trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h
Log:
This fixes a small typo.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h	2007-02-01 00:10:05 UTC (rev 2540)
+++ trunk/LinuxBIOSv2/src/include/cpu/amd/amdk8_sysconf.h	2007-02-01 00:40:51 UTC (rev 2541)
@@ -1,7 +1,6 @@
 #ifndef AMDK8_SYSCONF_H
+#define AMDK8_SYSCONF_H
 
-#define AMDK8_SYSINFO_H
-
 #define HC_POSSIBLE_NUM 8
 
 struct amdk8_sysconf_t {




From svn at openbios.org  Thu Feb  1 01:44:28 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  1 Feb 2007 01:44:28 +0100
Subject: [LinuxBIOS] r2542 - trunk/LinuxBIOSv2/src/arch/i386/boot
Message-ID: <mailman.159.1355071056.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-01 01:44:27 +0100 (Thu, 01 Feb 2007)
New Revision: 2542

Modified:
   trunk/LinuxBIOSv2/src/arch/i386/boot/linuxbios_table.c
Log:
great check-in message:

Linuxbios boots an Opteron motherboard with 1GB memory.

Linuxbios directly loads a recent linux kernel.
The memory layout is like this:

BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
   BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
   BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
   BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
   BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)

The f0000-f0400 region contains IRQ and ACPI tables.

At some point the kernel builds a resource table containing
all physical address ranges and type of hardware the addresses
are mapped to. The table is accessible via /proc/iomem:

# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
e0000000-efffffff : PCI Bus #03
    e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
    f4000000-f4ffffff : 0000:03:00.0
    f5000000-f5ffffff : 0000:03:00.0
    f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
    f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
    f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
    f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

As you can see, the 00000000000f0400-0000000040000000
region is not listed.

It is not listed because the kernel unconditionally adds
"000f0000-000fffff : System ROM" first (look for
"request_resource(&iomem_resource, &system_rom_resource)"),
and then the attempt to add f0400-40000000 range fails
because of overlapping.

The kernel does not care that the range is not listed there.
Kexec does. It uses the /proc/iomem file to instruct the
kexec system call how to place the segments of a new kernel
in the physical memory. Kexec fails to start a new kernel
because it cannot locate enough physical memory.

This must be fixed either in linux or linuxbios.

Assuming that linuxbios is to be fixed, I cooked a patch
which provides this memory layout:

BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
   BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
   BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
   BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
   BIOS-e820: 0000000000100000 - 0000000040000000 (usable)

The /proc/iomem contains:

# cat /proc/iomem 
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
00100000-3fffffff : System RAM
    00100000-00203c61 : Kernel code
    00203c62-00248c3f : Kernel data
e0000000-efffffff : PCI Bus #03
    e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
    f4000000-f4ffffff : 0000:03:00.0
    f5000000-f5ffffff : 0000:03:00.0
    f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
    f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
    f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
    f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

Kexec is happier with the patch.

Regards,

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com> 
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/LinuxBIOSv2/src/arch/i386/boot/linuxbios_table.c
===================================================================
--- trunk/LinuxBIOSv2/src/arch/i386/boot/linuxbios_table.c	2007-02-01 00:40:51 UTC (rev 2541)
+++ trunk/LinuxBIOSv2/src/arch/i386/boot/linuxbios_table.c	2007-02-01 00:44:27 UTC (rev 2542)
@@ -382,8 +382,9 @@
 		low_table_start, low_table_end - low_table_start);
 
 	/* Record the pirq table, acpi tables, and maybe the mptable */
+	table_size=rom_table_end-rom_table_start;
 	lb_add_memory_range(mem, LB_MEM_TABLE, 
-		rom_table_start, rom_table_end - rom_table_start);
+		rom_table_start, table_size<0x10000?0x10000:table_size);
 
 	/* Note:
 	 * I assume that there is always memory at immediately after




From eswierk at arastra.com  Thu Feb  1 01:53:58 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Wed, 31 Jan 2007 16:53:58 -0800
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <45C13020.1030103@coresystems.de>
References: <45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
Message-ID: <c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>

On 1/31/07, Stefan Reinauer <stefan.reinauer at coresystems.de> wrote:
> It's in. please go ahead.

Cool. Can you apply this patch next? It adds the MCP55 PCI IDs
(without which the southbridge code won't compile), and breaks an
unnecessary dependency on the usbdebug code.

Acked-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From uwe at hermann-uwe.de  Thu Feb  1 02:26:45 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 02:26:45 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <20070131221941.GA5178@greenwood>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>
	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
	<20070131221941.GA5178@greenwood> <45C11B63.6030708@coresystems.de>
Message-ID: <20070201012644.GA9824@greenwood>

On Wed, Jan 31, 2007 at 11:42:43PM +0100, Stefan Reinauer wrote:
> Uwe Hermann wrote:
> > On Wed, Jan 31, 2007 at 02:44:05PM -0700, ron minnich wrote:
> >> I don't see a solaris port as a huge problem. flashrom just uses mmap
> >> and solaris has that.
> >>
> >> If you want to try a make and see what happens, I'd like to hear how it goes.
> > 
> > Just a short note: if you build flashrom without having the whole
> > LinuxBIOS source tree around, you'll need to copy the file
> > src/include/boot/linuxbios_tables.h into the flashrom source directory
> > and apply the attached patch to make it use the file.
> > 
> > 
> > Btw, should we apply this in svn anyways? flashrom cannot be used
> > indepently otherwise...
> 
> Yes. Should we have a "make update_includes" target or something
> similar, or mention this in the README at least?

Hm, why not just put a copy of the file in util/flashrom? Will there be
(backwards-)compatibility problems when the file changes in LinuxBIOS?
I don't think so, but maybe I'm wrong.

Patch attached.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Feb  1 02:33:02 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 02:33:02 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <20070201012644.GA9824@greenwood>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>
	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
	<20070131221941.GA5178@greenwood> <45C11B63.6030708@coresystems.de>
	<20070201012644.GA9824@greenwood>
Message-ID: <20070201013302.GB9824@greenwood>

On Thu, Feb 01, 2007 at 02:26:45AM +0100, Uwe Hermann wrote:
> Patch attached.

Forgot the sign-off. New patch.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Feb  1 02:34:06 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 02:34:06 +0100
Subject: [LinuxBIOS] [PATCH] amdk8_sysconf.h type corrected
In-Reply-To: <45C11757.9020401@yahoo.com>
References: <45C103DD.60604@yahoo.com> <20070131211906.17840.qmail@cdy.org>
	<45C11757.9020401@yahoo.com>
Message-ID: <20070201013406.GC9824@greenwood>

On Wed, Jan 31, 2007 at 04:25:27PM -0600, Roman Kononov wrote:
> This fixes a small typo.
> 
> Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>

Committed, thanks.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Feb  1 02:36:00 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 02:36:00 +0100
Subject: [LinuxBIOS] r2540 - in
	trunk/LinuxBIOSv2/src/southbridge/nvidia: . mcp55
Message-ID: <20070201013559.GD9824@greenwood>

On Thu, Feb 01, 2007 at 01:10:06AM +0100, svn at openbios.org wrote:
> Log:
> Add support for the NVIDIA MCP55 southbridge.
> 
> Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> Acked-by: Yinghai Lu <yinghai.lu at amd.com>

This Acked-by shouldn't have been there, as Yinghai didn't post it
himself (it was merely suggested by me in case he acks the patch).


> Acked-by: Stefan Reinauer <stepan at coresystems.de>


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Feb  1 02:40:29 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 02:40:29 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
References: <45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
Message-ID: <20070201014028.GE9824@greenwood>

On Wed, Jan 31, 2007 at 04:53:58PM -0800, Ed Swierk wrote:
> On 1/31/07, Stefan Reinauer <stefan.reinauer at coresystems.de> wrote:
> >It's in. please go ahead.
> 
> Cool. Can you apply this patch next? It adds the MCP55 PCI IDs
> (without which the southbridge code won't compile), and breaks an
> unnecessary dependency on the usbdebug code.
> 
> Acked-by: Ed Swierk <eswierk at arastra.com>

I think you mean

Signed-off-by: Ed Swierk <eswierk at arastra.com>

Acked-by should be used to announce that you think a patch by someone
else is ok and can be committed. Signed-off-by says that you created
or modified the patch and are aware that the code you contribute is
licensed under the GPL etc. etc.

Otherwise the patch looks good to me (but I didn't test it).
Please repost with Signed-off-by.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stefan.reinauer at coresystems.de  Thu Feb  1 02:41:14 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Feb 2007 02:41:14 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
	<B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local>
Message-ID: <45C1453A.2050906@coresystems.de>

Kaufman, Adam wrote:
> Well, I had to do a bit of messing around, but I got both pciutils and
> flashrom to compile on my Solaris 10 box. My biggest concern was the
> /dev/mem wouldn't allow the same access we get on linux...  here's what
> I get:
> 
> bash-3.00# ./flashrom
> Calibrating delay loop... ok
> Can not mmap /dev/mem at 00000000 errno(6):No such device or address
> 
> Ideas?

It looks /dev/mem only contains ram on solaris, not the complete address
space.

There's a workaround, try using /dev/xsvc instead. It is part of X (or
XFree?) as it seems.

http://blogs.sun.com/dmick/entry/patch_for_dmidecode_2_6



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From eswierk at arastra.com  Thu Feb  1 02:43:48 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Wed, 31 Jan 2007 17:43:48 -0800
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <20070201014028.GE9824@greenwood>
References: <45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201014028.GE9824@greenwood>
Message-ID: <c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>

On 1/31/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> I think you mean

Oops. Here's the same patch.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From uwe at hermann-uwe.de  Thu Feb  1 02:47:34 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 02:47:34 +0100
Subject: [LinuxBIOS] [PATCH] amdk8_sysconf.h type corrected
In-Reply-To: <13426df10701311442u46af36f1n23bc9884419e5c3a@mail.gmail.com>
References: <45C103DD.60604@yahoo.com> <20070131211906.17840.qmail@cdy.org>
	<13426df10701311442u46af36f1n23bc9884419e5c3a@mail.gmail.com>
Message-ID: <20070201014733.GF9824@greenwood>

On Wed, Jan 31, 2007 at 03:42:47PM -0700, ron minnich wrote:
> On 1/31/07, Peter Stuge <stuge-linuxbios at cdy.org> wrote:
> 
> > Please have a look at http://linuxbios.org/Development_Guidelines
> > and specifically the "How to contribute" section, so your patches
> > can make it into svn faster.
> 
> apropos this comment. Could someone add a little clarification about
> what happens once an Acked-by: is added?
> 
> I would assume that if someone with commit rights adds an acked-by:,
> they take responsibility for the commit. But that is not spelled out.

Yes, basically. The Signed-off-by is legally important to have a clear
statement from the contributors that they can and want to legally contribute
the code under the GPL etc., while the Acked-by is just a mechanism to
somewhat enforce peer review of the patches.

One Acked-by is the minimum which is required to be able to commit a
patch (the more the better, of course). This means at least two people
looked at the patch and didn't notice any glaring bugs/problems (the
patch submitter + the one who sent the Acked-by).

People without svn commit access are welcome to review patches and send
Acked-by's too, but obviously someone _with_ commit access has to do
the actual commit then.


Cheers, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stuge-linuxbios at cdy.org  Thu Feb  1 02:52:49 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 1 Feb 2007 02:52:49 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
References: <2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201014028.GE9824@greenwood>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
Message-ID: <20070201015250.29957.qmail@cdy.org>

This patch adds the MCP55 PCI IDs (without which the southbridge code
won't compile), and breaks an unnecessary dependency on the usbdebug
code.

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Acked-by: Peter Stuge <peter at stuge.se>
-------------- next part --------------
Index: LinuxBIOSv2-2539/src/include/device/pci_ids.h
===================================================================
--- LinuxBIOSv2-2539.orig/src/include/device/pci_ids.h
+++ LinuxBIOSv2-2539/src/include/device/pci_ids.h
@@ -945,6 +945,33 @@
 #define PCI_DEVICE_ID_NVIDIA_CK8S_PCI          0x00ed
 #define PCI_DEVICE_ID_NVIDIA_CK8S_PCI_AGP      0x00e2
 
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC          0x0360
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE        0x0361
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2        0x0362
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3        0x0363
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4        0x0364
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5        0x0365
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6        0x0366
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO          0x0367
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2          0x0368
+#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE          0x036E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0        0x037E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1        0x037F
+#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC          0x0372
+#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE   0x0373
+#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA          0x0371
+#define PCI_DEVICE_ID_NVIDIA_MCP55_USB          0x036C
+#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2         0x036D
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI          0x0370
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C     0x0374
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E       0x0375
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A       0x0376
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F       0x0377
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D       0x0378
+#define PCI_DEVICE_ID_NVIDIA_MCP55_HT           0x0369
+#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM         0x036A
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU          0x036B
+
 #define PCI_VENDOR_ID_NVIDIA			0x10de
 #define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
 #define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028
Index: LinuxBIOSv2-2539/src/southbridge/nvidia/mcp55/mcp55_usb2.c
===================================================================
--- LinuxBIOSv2-2539.orig/src/southbridge/nvidia/mcp55/mcp55_usb2.c
+++ LinuxBIOSv2-2539/src/southbridge/nvidia/mcp55/mcp55_usb2.c
@@ -27,7 +27,9 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "mcp55.h"
+#if CONFIG_USBDEBUG_DIRECT
 #include <usbdebug_direct.h>
+#endif
 
 extern struct ehci_debug_info dbg_info;
 

From svn at openbios.org  Thu Feb  1 02:53:56 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  1 Feb 2007 02:53:56 +0100
Subject: [LinuxBIOS] r2543 - in trunk/LinuxBIOSv2/src: include/device
	southbridge/nvidia/mcp55
Message-ID: <mailman.160.1355071056.16123.coreboot@coreboot.org>

Author: stuge
Date: 2007-02-01 02:53:55 +0100 (Thu, 01 Feb 2007)
New Revision: 2543

Modified:
   trunk/LinuxBIOSv2/src/include/device/pci_ids.h
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c
Log:
This patch adds the MCP55 PCI IDs (without which the southbridge code
won't compile), and breaks an unnecessary dependency on the usbdebug
code.

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-02-01 00:44:27 UTC (rev 2542)
+++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-02-01 01:53:55 UTC (rev 2543)
@@ -945,6 +945,33 @@
 #define PCI_DEVICE_ID_NVIDIA_CK8S_PCI          0x00ed
 #define PCI_DEVICE_ID_NVIDIA_CK8S_PCI_AGP      0x00e2
 
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC          0x0360
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE        0x0361
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2        0x0362
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3        0x0363
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4        0x0364
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5        0x0365
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6        0x0366
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO          0x0367
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2          0x0368
+#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE          0x036E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0        0x037E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1        0x037F
+#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC          0x0372
+#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE   0x0373
+#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA          0x0371
+#define PCI_DEVICE_ID_NVIDIA_MCP55_USB          0x036C
+#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2         0x036D
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI          0x0370
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C     0x0374
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E       0x0375
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A       0x0376
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F       0x0377
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D       0x0378
+#define PCI_DEVICE_ID_NVIDIA_MCP55_HT           0x0369
+#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM         0x036A
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU          0x036B
+
 #define PCI_VENDOR_ID_NVIDIA			0x10de
 #define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
 #define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028

Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c	2007-02-01 00:44:27 UTC (rev 2542)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_usb2.c	2007-02-01 01:53:55 UTC (rev 2543)
@@ -27,7 +27,9 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "mcp55.h"
+#if CONFIG_USBDEBUG_DIRECT
 #include <usbdebug_direct.h>
+#endif
 
 extern struct ehci_debug_info dbg_info;
 




From uwe at hermann-uwe.de  Thu Feb  1 02:57:43 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 02:57:43 +0100
Subject: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O
In-Reply-To: <20070125221350.GA16656@greenwood>
References: <20070125221350.GA16656@greenwood>
Message-ID: <20070201015743.GG9824@greenwood>

On Thu, Jan 25, 2007 at 11:13:50PM +0100, Uwe Hermann wrote:
> Add support for the Winbond W83627EHG Super I/O.
> 
> Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> ---
> 
> This is from Yinghai's huge patch. I added missing license headers
> (Yinghai please complain if any of them is incorrect!), fixed some
> coding style issues and added a few comments.
> 
> The code is untested by me (didn't even test whether it builds)!
> Anybody wants to test this?

*Ping* :)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From bingxunshi at gmail.com  Thu Feb  1 03:02:08 2007
From: bingxunshi at gmail.com (bxshi)
Date: Thu, 1 Feb 2007 10:02:08 +0800
Subject: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O
In-Reply-To: <20070201015743.GG9824@greenwood>
References: <20070125221350.GA16656@greenwood>
	<20070201015743.GG9824@greenwood>
Message-ID: <dcdcf0740701311802r4800506bh531e6627c286fb62@mail.gmail.com>

>
>
> > This is from Yinghai's huge patch. I added missing license headers
> > (Yinghai please complain if any of them is incorrect!), fixed some
> > coding style issues and added a few comments.
> >
> > The code is untested by me (didn't even test whether it builds)!
> > Anybody wants to test this?


MSI ms9282 has w83627EHG. as I have tested ,yinghai's code is ok.

bxshi
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From adam.kaufman at pinnacle.com  Thu Feb  1 02:59:42 2007
From: adam.kaufman at pinnacle.com (Kaufman,  Adam)
Date: Wed, 31 Jan 2007 20:59:42 -0500
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
	<B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local>
	<45C1453A.2050906@coresystems.de>
Message-ID: <B336556B53FC0F42AE59AD52F8B8D5BDAE7DFC@exchange01.pdsi.local>

Awesome! I think that did it. I'm not at the office right now, so I don't want to reboot my test system, but it doesn't look like anything blew up. Thanks for the help! If everything is good, I'll clean it up and make a patch. Should be fairly minimal.

-ak

whodini# ./flashrom -w /mnt/adamk/tyan/2882v309.rom
Calibrating delay loop... ok
No LinuxBIOS table found.
Enabling flash write on AMD8111...OK
Pm49FL004 found at physical address: 0xfff80000
Flash part is Pm49FL004 (512 KB)
Flash image seems to be a legacy BIOS. Disabling checks.
Programming Page: 0007 at address: 0x00070000


-----Original Message-----
From: Stefan Reinauer [mailto:stefan.reinauer at coresystems.de]
Sent: Wed 31/01/2007 20:41
To: Kaufman,  Adam
Cc: linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] LinuxBIOS Solaris Dev
 
Kaufman, Adam wrote:
> Well, I had to do a bit of messing around, but I got both pciutils and
> flashrom to compile on my Solaris 10 box. My biggest concern was the
> /dev/mem wouldn't allow the same access we get on linux...  here's what
> I get:
> 
> bash-3.00# ./flashrom
> Calibrating delay loop... ok
> Can not mmap /dev/mem at 00000000 errno(6):No such device or address
> 
> Ideas?

It looks /dev/mem only contains ram on solaris, not the complete address
space.

There's a workaround, try using /dev/xsvc instead. It is part of X (or
XFree?) as it seems.

http://blogs.sun.com/dmick/entry/patch_for_dmidecode_2_6



-- 
coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 . Fax: +49 761 7664613
Email: info at coresystems.de  . http://www.coresystems.de/



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From uwe at hermann-uwe.de  Thu Feb  1 03:14:23 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 03:14:23 +0100
Subject: [LinuxBIOS] [PATCH] Remove hardcoded gcc versions in build
	environment
Message-ID: <20070201021423.GK9824@greenwood>

Remove hardcoded gcc versions, otherwise the build will break for
most people. Or is there any special reason to enforce a special
version of gcc? I don't think so.

Patch attached.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From corey_osgood at verizon.net  Thu Feb  1 08:45:22 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Thu, 01 Feb 2007 02:45:22 -0500
Subject: [LinuxBIOS] Add support for Via vt82c686a
In-Reply-To: <20070116061841.GA28012@greenwood>
References: <45AA9938.6020804@verizon.net> <20070114235739.GB20305@greenwood>
	<45AAE156.5030206@verizon.net>
	<366f3f5e6a46f27ea5e4a1edfac2d58c@kernel.crashing.org>
	<20070115175038.GA10359@greenwood>	<45ABD34A.1040609@verizon.net>
	<45AC2889.1070307@comcast.net> <20070116061841.GA28012@greenwood>
Message-ID: <45C19A92.2020802@verizon.net>

Please scratch the patch I submitted. vt82c686a and b are the same, the 
docs lied (and this is the first time I've looked at it on the machines, 
stupid me). I'm reworking a few things and cleaning up a few more 
things, and I'll submit a working, tested patch this weekend, if all 
goes well.

On a related note, does anyone know if any northbridge init is required 
to bring up the southbridge (and in this case also superio)? And is the 
rcn dc1100s from v1 working or not? I couldn't get it to run (no serial 
or video output at all) on the tyan s2507, which seems to be the same 
hardware.



From michalwan at hotmail.com  Thu Feb  1 03:44:11 2007
From: michalwan at hotmail.com (michal wan)
Date: Thu, 01 Feb 2007 10:44:11 +0800
Subject: [LinuxBIOS] hda: lost interrupt  when executing linux kernel
Message-ID: <BAY132-F280498C85E7761FBD626DB5A40@phx.gbl>

1 it looks ok running linuxbios and filo 
2 loading kernel ok

when  executing linux kernel, something occurs like "hda: lost interrupt"

there are some problems which can be seen from the output of linux kernel
1  AMD5536: not 100% native mode: will probe irqs lalater
2 AMD5536: neither IDE port enabled (BIOS)

another problem is below
in the function model_lx_init() from src/cpu/amd/model_lx/model_lx_init.c
if umcomment setup_lapic() and vsm_end_post_smi(), it will occur supported 
interrupt 13, then  die  
i have uncomment the object  irq_tables.o in file 
src/mainboard/artecgroup/dbe61/Options.lb

any advice would be appreciated!

_________________________________________________________________
???? MSN Explorer:   http://explorer.msn.com/lccn  
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From uwe at hermann-uwe.de  Thu Feb  1 12:01:54 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 12:01:54 +0100
Subject: [LinuxBIOS] Add support for Via vt82c686a
In-Reply-To: <45C19A92.2020802@verizon.net>
References: <45AA9938.6020804@verizon.net> <20070114235739.GB20305@greenwood>
	<45AAE156.5030206@verizon.net>
	<366f3f5e6a46f27ea5e4a1edfac2d58c@kernel.crashing.org>
	<20070115175038.GA10359@greenwood>
	<45ABD34A.1040609@verizon.net> <45AC2889.1070307@comcast.net>
	<20070116061841.GA28012@greenwood> <45C19A92.2020802@verizon.net>
Message-ID: <20070201110154.GA27621@greenwood>

Hi,

On Thu, Feb 01, 2007 at 02:45:22AM -0500, Corey Osgood wrote:
> Please scratch the patch I submitted. vt82c686a and b are the same, the 
> docs lied (and this is the first time I've looked at it on the machines, 
> stupid me). I'm reworking a few things and cleaning up a few more 
> things, and I'll submit a working, tested patch this weekend, if all 
> goes well.

OK, great!

 
> On a related note, does anyone know if any northbridge init is required 
> to bring up the southbridge (and in this case also superio)? And is the 
> rcn dc1100s from v1 working or not? I couldn't get it to run (no serial 
> or video output at all) on the tyan s2507, which seems to be the same 
> hardware.

I guess you need the northbridge (RAM init) for anything else to work.
I have a K7T Turbo which has a VIA VT82C686B southbridge, but
unfortunately the northbridge is a VIA Apollo KT133A (VT8363A) which
is not supported, and I don't have VIA data sheets...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From michalwan at hotmail.com  Thu Feb  1 11:48:12 2007
From: michalwan at hotmail.com (michal wan)
Date: Thu, 01 Feb 2007 18:48:12 +0800
Subject: [LinuxBIOS] bad page state when starting cups service of linux
	system
Message-ID: <BAY132-F610E067E83784EB09B90EB5A40@phx.gbl>


stepping into starting linux system process,  at the time of starting cups 
process,  linux reports bad page  state, then backtrace, the full log file 
is attached

any hint would be great help, thanks in advance!

_________________________________________________________________
??????????????? MSN Hotmail?  http://www.hotmail.com  
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From east at uw.hu  Thu Feb  1 14:38:08 2007
From: east at uw.hu (east)
Date: Thu, 1 Feb 2007 14:38:08 +0100 (CET)
Subject: [LinuxBIOS]  Intel 815
Message-ID: <48713.213.253.200.62.1170337088.squirrel@mail.ultraweb.hu>

Hello,

I'm new in the list and I like to use LinuxBIOS in my new project. I
searched the archive and the source about i815 support but I haven't find
any exact information. Somebody working on it?

My board is a HP Vectra mini ATX
Northbrigde: 82815
Southbridge: 82801AA


--------------------------------- Hirdet?s ---------------------------------

C2 MAIL: A nagy levelez-?.  http://mail.c2.hu





From eswierk at arastra.com  Thu Feb  1 18:16:25 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 1 Feb 2007 09:16:25 -0800
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential bugs
Message-ID: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>

This patch fixes a bunch of compiler warnings I ran into while
building an MCP55 target using gcc 4.1.1.

A few are real bugs, like the misspelled "default" in raminit_f.c and
the truncated 16-bit argument to delayx() in mcp55_early_setup_car.c.
The uninitialized variables in raminit_f_dqs.c are potential bugs.

gcc 4.1.x is famously paranoid about certain things, and some of its
warnings can only be considered compiler bugs, so I ignored those. The
minor warnings I fixed are mainly improper int/pointer casts and
unused variables.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From c-d.hailfinger.devel.2006 at gmx.net  Thu Feb  1 19:52:36 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Feb 2007 19:52:36 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
 bugs
In-Reply-To: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
Message-ID: <45C236F4.7030600@gmx.net>

Ed Swierk wrote:
> This patch fixes a bunch of compiler warnings I ran into while
> building an MCP55 target using gcc 4.1.1.
> 
> A few are real bugs, like the misspelled "default" in raminit_f.c and
> the truncated 16-bit argument to delayx() in mcp55_early_setup_car.c.
> The uninitialized variables in raminit_f_dqs.c are potential bugs.

Ack.

> gcc 4.1.x is famously paranoid about certain things, and some of its
> warnings can only be considered compiler bugs, so I ignored those. The
> minor warnings I fixed are mainly improper int/pointer casts and
> unused variables.

Hmmm. You know that the signedness of char is not defined?

Besides that, we definitely should enable -fno-strict-aliasing in the
gcc flags until we have audited all casts.

> --- LinuxBIOSv2-2540.orig/util/options/build_opt_tbl.c
> +++ LinuxBIOSv2-2540/util/options/build_opt_tbl.c
> @@ -332,7 +332,7 @@ int main(int argc, char **argv)
>  			fprintf(stderr, "Error - Length is to long in line \n%s\n",line);
>  			exit(1);
>  		}
> -		if (!is_ident(ce->name)) {
> +		if (!is_ident((char *) ce->name)) {
>  			fprintf(stderr, 
>  				"Error - Name %s is an invalid identifier in line\n %s\n", 
>  				ce->name, line);

Nack. Fix struct cmos_entries instead. is_ident_* needs a lot
of cleaning, too.

> @@ -341,7 +341,7 @@ int main(int argc, char **argv)
>  		/* put in the record type */
>  		ce->tag=LB_TAG_OPTION;
>  		/* calculate and save the record length */
> -		len=strlen(ce->name)+1;
> +		len=strlen((char *) ce->name)+1;
>  		/* make the record int aligned */
>  		if(len%4)
>  			len+=(4-(len%4));

ditto

> @@ -540,7 +540,7 @@ int main(int argc, char **argv)
>  			if (ce->config == 'r') {
>  				continue;
>  			}
> -			if (!is_ident(ce->name)) {
> +			if (!is_ident((char *) ce->name)) {
>  				fprintf(stderr, "Invalid identifier: %s\n",
>  					ce->name);
>  				exit(1);

ditto

> --- LinuxBIOSv2-2540.orig/src/cpu/amd/model_fxx/model_fxx_init.c
> +++ LinuxBIOSv2-2540/src/cpu/amd/model_fxx/model_fxx_init.c
> @@ -17,6 +17,7 @@
>  #include <cpu/x86/pae.h>
>  #include <pc80/mc146818rtc.h>
>  #include <cpu/x86/lapic.h>
> +#include <part/hard_reset.h>
>  
>  #include "../../../northbridge/amd/amdk8/amdk8.h"
>  
> @@ -473,7 +474,7 @@ static void amd_set_name_string_f(device
>  	unsigned nN;
>  	unsigned unknown = 1;
>  
> -	uint8_t str[48];
> +	char str[48];
>  	uint32_t *p;
>  
>  	msr_t msr;

Please remove the magic constant 48 when you change this line. Same for
all other magic 48.

> @@ -533,7 +534,7 @@ static void amd_set_name_string_f(device
>  	#endif
>  	}
>  
> -	p = str; 
> +	p = (uint32_t *) str;
>  	for(i=0;i<6;i++) {
>  		msr.lo = *p;  p++; msr.hi = *p; p++;
>  		wrmsr(0xc0010030+i, msr);

While I agree with this cast, gcc is free to break this code completely
unless we use -fno-strict-aliasing.

> Index: LinuxBIOSv2-2540/src/northbridge/amd/amdk8/coherent_ht_car.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/northbridge/amd/amdk8/coherent_ht_car.c
> +++ LinuxBIOSv2-2540/src/northbridge/amd/amdk8/coherent_ht_car.c
> @@ -1662,7 +1662,6 @@ static int apply_cpu_errata_fixes(unsign
>  	int needs_reset = 0;
>  	for(node = 0; node < nodes; node++) {
>  		device_t dev;
> -		uint32_t cmd;
>  		dev = NODE_MC(node);
>  #if K8_REV_F_SUPPORT == 0
>  		if (is_cpu_pre_c0()) {
> Index: LinuxBIOSv2-2540/src/northbridge/amd/amdk8/misc_control.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/northbridge/amd/amdk8/misc_control.c
> +++ LinuxBIOSv2-2540/src/northbridge/amd/amdk8/misc_control.c
> @@ -110,7 +110,10 @@ static void misc_control_init(struct dev
>  {
>  	uint32_t cmd, cmd_ref;
>  	int needs_reset;
> -	struct device *f0_dev, *f2_dev;
> +	struct device *f0_dev;
> +#if K8_REV_F_SUPPORT == 0
> +        struct device *f2_dev;
> +#endif
>  	
>  	printk_debug("NB: Function 3 Misc Control.. ");
>  	needs_reset = 0;
> Index: LinuxBIOSv2-2540/src/northbridge/amd/amdk8/raminit_f.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/northbridge/amd/amdk8/raminit_f.c
> +++ LinuxBIOSv2-2540/src/northbridge/amd/amdk8/raminit_f.c
> @@ -2506,7 +2506,7 @@ static void set_misc_timing(const struct
>                                  case 0x00:
>                                          dwordx = 0x002b2220; //x8 double Rank
>                                          break;
> -                                defalut:
> +                                default:
>                                          dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
>                                  }
>                          } else if((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {

Nice spot.

> @@ -2865,7 +2865,7 @@ static void sdram_enable(int controllers
>  
>  	/* Before enabling memory start the memory clocks */
>  	for(i = 0; i < controllers; i++) {
> -		uint32_t dtl, dch;
> +		uint32_t dch;
>  		if (!sysinfo->ctrl_present[ i ])
>  			continue;
>                  dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
> @@ -2938,7 +2938,7 @@ static void sdram_enable(int controllers
>  	}
>  
>  	for(i = 0; i < controllers; i++) {
> -		uint32_t dcl, dch, dcm;
> +		uint32_t dcl, dcm;
>  		if (!sysinfo->ctrl_present[ i ])
>  			continue;
>  		/* Skip everything if I don't have any memory on this controller */
> Index: LinuxBIOSv2-2540/src/northbridge/amd/amdk8/raminit_f_dqs.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/northbridge/amd/amdk8/raminit_f_dqs.c
> +++ LinuxBIOSv2-2540/src/northbridge/amd/amdk8/raminit_f_dqs.c
> @@ -551,13 +551,15 @@ static unsigned TrainRcvrEn(const struct
>  
>  	unsigned TestAddr0, TestAddr0B, TestAddr1, TestAddr1B;
>  
> -	unsigned CurrRcvrCHADelay;
> +	unsigned CurrRcvrCHADelay = 0;
>  
>  	unsigned tmp;
>  
>  	unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
>  
> +#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
>  	unsigned cpu_f0_f1;
> +#endif
>  
>  	if(Pass == DQS_FIRST_PASS) {
>  		InitDQSPos4RcvrEn(ctrl);
> @@ -1205,6 +1207,7 @@ static unsigned TrainDQSPos(const struct
>  
>  		LastTest = DQS_FAIL;
>  		RnkDlySeqPassMax = 0;
> +		RnkDlySeqPassMin = 0;
>  		RnkDlyFilterMax = 0;
>  		RnkDlyFilterMin = 0;
>  		for(DQSDelay=0; DQSDelay<48; DQSDelay++) {
> Index: LinuxBIOSv2-2540/src/pc80/mc146818rtc.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/pc80/mc146818rtc.c
> +++ LinuxBIOSv2-2540/src/pc80/mc146818rtc.c
> @@ -123,8 +123,10 @@ static void rtc_set_checksum(int range_s
>  
>  void rtc_init(int invalid)
>  {
> +#if HAVE_OPTION_TABLE
>  	unsigned char x;
>  	int cmos_invalid, checksum_invalid;
> +#endif
>  
>  	printk_debug("RTC Init\n");
>  
> Index: LinuxBIOSv2-2540/src/ram/ramtest.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/ram/ramtest.c
> +++ LinuxBIOSv2-2540/src/ram/ramtest.c
> @@ -94,7 +94,6 @@ static void ram_verify(unsigned long sta
>  
>  void ram_check(unsigned long start, unsigned long stop)
>  {
> -	int result;
>  	/*
>  	 * This is much more of a "Is my DRAM properly configured?"
>  	 * test than a "Is my DRAM faulty?" test.  Not all bits
> Index: LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_aza.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_aza.c
> +++ LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_aza.c
> @@ -27,6 +27,7 @@
>  #include <device/pci_ids.h>
>  #include <device/pci_ops.h>
>  #include <arch/io.h>
> +#include <delay.h>
>  #include "mcp55.h"
>  
>  static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
> @@ -228,7 +229,7 @@ static void aza_init(struct device *dev)
>  	if(!res)
>  		return;
>  
> -	base =(uint8_t *) res->base;
> +	base =(uint8_t *) ((uint32_t) res->base);
>  	printk_debug("base = %08x\n", base);
>  
>  	codec_mask = codec_detect(base);

Are you really sure you want to cast a uint64_t to uint32_t to uint8_t * ?

> Index: LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
> +++ LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
> @@ -175,7 +175,8 @@ static void mcp55_early_pcie_setup(unsig
>  	pci_write_config32(dev, 0xe4, dword);
>  
>  //	need to wait 100ms
> -	delayx(1000);
> +	for (i=0; i<10; i++)
> +	    delayx(100);
>  }
>  
>  static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)

Nack. You increased the delay by a factor of 10.

> Index: LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_lpc.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_lpc.c
> +++ LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_lpc.c
> @@ -243,7 +243,6 @@ static void lpc_init(device_t dev)
>  static void mcp55_lpc_read_resources(device_t dev)
>  {
>  	struct resource *res;
> -	unsigned long index;
>  
>  	/* Get the normal pci resources of this device */
>  	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
> Index: LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_nic.c
> ===================================================================
> --- LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_nic.c
> +++ LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_nic.c
> @@ -28,6 +28,7 @@
>  #include <device/pci_ids.h>
>  #include <device/pci_ops.h>
>  #include <arch/io.h>
> +#include <delay.h>
>  #include "mcp55.h"
>  
>  static int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
> @@ -55,7 +56,7 @@ static int phy_read(uint8_t *base, unsig
>  
>  }
>  
> -static int phy_detect(uint8_t *base)
> +static void phy_detect(uint8_t *base)
>  {
>  	uint32_t dword;
>  	int i;
> @@ -94,7 +95,6 @@ static int phy_detect(uint8_t *base)
>  }
>  static void nic_init(struct device *dev)
>  {
> -	uint32_t dword, old;
>  	uint32_t mac_h, mac_l;
>  	int eeprom_valid = 0;
>  	struct southbridge_nvidia_mcp55_config *conf;
> @@ -108,7 +108,7 @@ static void nic_init(struct device *dev)
>  
>  	if(!res) return;
>  
> -	base = res->base;
> +	base = (uint8_t *) ((uint32_t) res->base);
>  
>  	phy_detect(base);
>  
> @@ -154,8 +154,7 @@ static void nic_init(struct device *dev)
>  	}
>  //	if that is invalid we will read that from romstrap
>  	if(!eeprom_valid) {
> -		unsigned long mac_pos;
> -		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
> +		uint32_t *mac_pos = (uint32_t *) 0xffffffd0; // refer to romstrap.inc and romstrap.lds
>  		mac_l = readl(mac_pos) + nic_index; // overflow?
>  		mac_h = readl(mac_pos + 4);
>  

Hmmm. I have to reread that.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From corey_osgood at verizon.net  Thu Feb  1 20:06:05 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Thu, 01 Feb 2007 14:06:05 -0500
Subject: [LinuxBIOS] Intel 815
In-Reply-To: <48713.213.253.200.62.1170337088.squirrel@mail.ultraweb.hu>
References: <48713.213.253.200.62.1170337088.squirrel@mail.ultraweb.hu>
Message-ID: <45C23A1D.6090705@verizon.net>

east wrote:
> Hello,
> 
> I'm new in the list and I like to use LinuxBIOS in my new project. I
> searched the archive and the source about i815 support but I haven't find
> any exact information. Somebody working on it?
> 
> My board is a HP Vectra mini ATX
> Northbrigde: 82815
> Southbridge: 82801AA
> 
> 
> --------------------------------- Hirdet?s ---------------------------------
> 
> C2 MAIL: A nagy levelez-?.  http://mail.c2.hu
> 
> 
> 

The i815 is currently unsupported, I've been planning on looking at it
once I finish with another board, if noone beats me to it. The 82801AA
should be easy to get going, as it will probably work with the other
82801xx code already in linuxbios (perhaps a couple small changes).

-Corey




From eswierk at arastra.com  Thu Feb  1 20:46:02 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 1 Feb 2007 11:46:02 -0800
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <45C236F4.7030600@gmx.net>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
Message-ID: <c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>

On 2/1/07, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hmmm. You know that the signedness of char is not defined?

Yes, but if functions like strlen() take a char *, then shouldn't the
parameter be signed rather than unsigned?

> Besides that, we definitely should enable -fno-strict-aliasing in the
> gcc flags until we have audited all casts.

Agreed.

> Please remove the magic constant 48 when you change this line. Same for
> all other magic 48.

Oh boy. You're asking me to understand the code I'm tidying? :-)

> > Index: LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_aza.c
> > ===================================================================
> > --- LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_aza.c
> > +++ LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_aza.c
> > @@ -27,6 +27,7 @@
> >  #include <device/pci_ids.h>
> >  #include <device/pci_ops.h>
> >  #include <arch/io.h>
> > +#include <delay.h>
> >  #include "mcp55.h"
> >
> >  static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
> > @@ -228,7 +229,7 @@ static void aza_init(struct device *dev)
> >       if(!res)
> >               return;
> >
> > -     base =(uint8_t *) res->base;
> > +     base =(uint8_t *) ((uint32_t) res->base);
> >       printk_debug("base = %08x\n", base);
> >
> >       codec_mask = codec_detect(base);
>
> Are you really sure you want to cast a uint64_t to uint32_t to uint8_t * ?

I'm not sure. The current implementation truncates base to 32 bits, so
I suppose there ought to be a check that base doesn't exceed
0xffffffff. But in this case the double-cast is still necessary to
avoid gcc's complaint about truncating while casting to a pointer.

> > ===================================================================
> > --- LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
> > +++ LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
> > @@ -175,7 +175,8 @@ static void mcp55_early_pcie_setup(unsig
> >       pci_write_config32(dev, 0xe4, dword);
> >
> >  //   need to wait 100ms
> > -     delayx(1000);
> > +     for (i=0; i<10; i++)
> > +         delayx(100);
> >  }
> >
> >  static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
>
> Nack. You increased the delay by a factor of 10.

This alters the existing behavior, yes. But if the comments in the
code are to be believed, delayx(1) waits 100 usec, so for a 100-msec
delay we have to call delayx(100) 10 times.

--Ed



From kononov195-lbl at yahoo.com  Thu Feb  1 20:49:29 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Thu, 01 Feb 2007 13:49:29 -0600
Subject: [LinuxBIOS]  new feature - CrushK8-04 USB1 Controller Reset
Message-ID: <45C24449.501@yahoo.com>

I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforce
2200 (too many names, sounds like a criminal).

1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works fine.

2) Then I push the reset button.

3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
about wrong checksum of the mptable and crushes later.

An investigation showed that in 3), short after kernel A (v2.6.19.2) sets
the Bus Master Enable bit of the nVidia's USB1 controller (pci_set_master()),
the mptable gets two bytes at physical address 0x80 damaged.

Nothing is plugged to the USB ports. Other two Sun workstations had the same
behavior. This does not make sense to me unless the controller has a HW bug.

I believe, this should better be fixed in the kernel USB driver.

For now this patch offers a possibility for linuxbios to reset the USB
controller by setting HostControllerReset bit in HcCommandStatus Register.
It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
southbridge/nvidia/ck804' section of the mainboard's Config.lb.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>

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From kononov195-lbl at yahoo.com  Thu Feb  1 20:50:04 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Thu, 01 Feb 2007 13:50:04 -0600
Subject: [LinuxBIOS]  Sun Ultra40 patches
Message-ID: <45C2446C.8010403@yahoo.com>

This set of changes makes Sun Ultra40 working. Although not fully.

The working parts are: single CPU and nForce 2200 (CK804 Pro) with
all stuff connected to it. The still-not-working parts are: second
CPU and nForce 2050 with all stuff connected to it.

The changed files contain many things related to the non-working
second CPU and nForce 2050 commented out in order to make the
working system stable.

Thousand thanks to all who made the original Sun Ultra40 sources.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>

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From c-d.hailfinger.devel.2006 at gmx.net  Thu Feb  1 20:54:29 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Feb 2007 20:54:29 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
 bugs
In-Reply-To: <c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>	
	<45C236F4.7030600@gmx.net>
	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
Message-ID: <45C24575.1090401@gmx.net>

Ed Swierk wrote:
> On 2/1/07, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> wrote:
>> Hmmm. You know that the signedness of char is not defined?
> 
> Yes, but if functions like strlen() take a char *, then shouldn't the
> parameter be signed rather than unsigned?

For functions like strlen, we have no choice but to use naked char.
So yes, my complaint was superfluous in this case.

>> Besides that, we definitely should enable -fno-strict-aliasing in the
>> gcc flags until we have audited all casts.
> 
> Agreed.
> 
>> Please remove the magic constant 48 when you change this line. Same for
>> all other magic 48.
> 
> Oh boy. You're asking me to understand the code I'm tidying? :-)

Yes. Sacrificing a chicken would be nice, too.

>> > Index: LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_aza.c
>> > ===================================================================
>> > --- LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_aza.c
>> > +++ LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_aza.c
>> > @@ -27,6 +27,7 @@
>> >  #include <device/pci_ids.h>
>> >  #include <device/pci_ops.h>
>> >  #include <arch/io.h>
>> > +#include <delay.h>
>> >  #include "mcp55.h"
>> >
>> >  static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
>> > @@ -228,7 +229,7 @@ static void aza_init(struct device *dev)
>> >       if(!res)
>> >               return;
>> >
>> > -     base =(uint8_t *) res->base;
>> > +     base =(uint8_t *) ((uint32_t) res->base);
>> >       printk_debug("base = %08x\n", base);
>> >
>> >       codec_mask = codec_detect(base);
>>
>> Are you really sure you want to cast a uint64_t to uint32_t to uint8_t
>> * ?
> 
> I'm not sure. The current implementation truncates base to 32 bits, so
> I suppose there ought to be a check that base doesn't exceed
> 0xffffffff. But in this case the double-cast is still necessary to
> avoid gcc's complaint about truncating while casting to a pointer.

Agreed.

>> > ===================================================================
>> > ---
>> LinuxBIOSv2-2540.orig/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
>>
>> > +++
>> LinuxBIOSv2-2540/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
>> > @@ -175,7 +175,8 @@ static void mcp55_early_pcie_setup(unsig
>> >       pci_write_config32(dev, 0xe4, dword);
>> >
>> >  //   need to wait 100ms
>> > -     delayx(1000);
>> > +     for (i=0; i<10; i++)
>> > +         delayx(100);
>> >  }
>> >
>> >  static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
>> unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
>>
>> Nack. You increased the delay by a factor of 10.
> 
> This alters the existing behavior, yes. But if the comments in the
> code are to be believed, delayx(1) waits 100 usec, so for a 100-msec
> delay we have to call delayx(100) 10 times.

The code says something different.

static void delayx(uint8_t value) {
        int i;
        for(i=0;i<0x8000;i++) {
                outb(value, 0x80);
        }
}

The value is the POST code and has nothing to do with the delay.
So your patch changed the POST code from E8 (1000 mod 256) to 64 (100)
and called the delay function ten times.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From segher at kernel.crashing.org  Thu Feb  1 21:01:58 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Thu, 1 Feb 2007 21:01:58 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <45C236F4.7030600@gmx.net>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
Message-ID: <EE3C3F3D-CAC5-4223-BB51-8C4A62A9B129@kernel.crashing.org>

> Hmmm. You know that the signedness of char is not defined?

It is defined, but implementation-defined.  Maybe you mean
that "plain" char is a separate type from both signed char
and unsigned char?

> Besides that, we definitely should enable -fno-strict-aliasing in the
> gcc flags until we have audited all casts.

Well certainly as long as GCC keeps spitting warnings about
this, it almost never gets these warnings wrong.


Segher




From segher at kernel.crashing.org  Thu Feb  1 21:04:25 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Thu, 1 Feb 2007 21:04:25 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
Message-ID: <F5857A15-2E8D-4D03-9D17-6E230FD56874@kernel.crashing.org>


On 1-feb-2007, at 20:46, Ed Swierk wrote:

> On 2/1/07, Carl-Daniel Hailfinger <c-d.hailfinger.devel. 
> 2006 at gmx.net> wrote:
>> Hmmm. You know that the signedness of char is not defined?
>
> Yes, but if functions like strlen() take a char *, then shouldn't the
> parameter be signed rather than unsigned?

No; plain char is unsigned on almost all mainstream
architectures.


Segher




From eswierk at arastra.com  Thu Feb  1 21:06:06 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 1 Feb 2007 12:06:06 -0800
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <45C24575.1090401@gmx.net>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
	<45C24575.1090401@gmx.net>
Message-ID: <c1bf1cf0702011206r49ccd732l323ce495279f6c0c@mail.gmail.com>

On 2/1/07, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> The code says something different.
>
> static void delayx(uint8_t value) {
>         int i;
>         for(i=0;i<0x8000;i++) {
>                 outb(value, 0x80);
>         }
> }
>
> The value is the POST code and has nothing to do with the delay.
> So your patch changed the POST code from E8 (1000 mod 256) to 64 (100)
> and called the delay function ten times.

So delayx() actually sets the POST code by writing some value 32768
times, has nothing to do with delay, and the comments about delay are
completely irrelevant? My brain just exploded.

--Ed



From segher at kernel.crashing.org  Thu Feb  1 21:09:15 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Thu, 1 Feb 2007 21:09:15 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <c1bf1cf0702011206r49ccd732l323ce495279f6c0c@mail.gmail.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
	<45C24575.1090401@gmx.net>
	<c1bf1cf0702011206r49ccd732l323ce495279f6c0c@mail.gmail.com>
Message-ID: <BD0CA068-8C81-4EFB-9399-0F140610E43A@kernel.crashing.org>

>> static void delayx(uint8_t value) {
>>         int i;
>>         for(i=0;i<0x8000;i++) {
>>                 outb(value, 0x80);
>>         }
>> }
>>
>> The value is the POST code and has nothing to do with the delay.
>> So your patch changed the POST code from E8 (1000 mod 256) to 64  
>> (100)
>> and called the delay function ten times.
>
> So delayx() actually sets the POST code by writing some value 32768
> times, has nothing to do with delay, and the comments about delay are
> completely irrelevant? My brain just exploded.

Oh it certainly causes a delay -- a huge delay, irrespective
of its parameter.  A few millis at least.


Segher




From kononov195-lbl at yahoo.com  Thu Feb  1 21:17:09 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Thu, 01 Feb 2007 14:17:09 -0600
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
 bugs
In-Reply-To: <45C24575.1090401@gmx.net>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>		<45C236F4.7030600@gmx.net>	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
	<45C24575.1090401@gmx.net>
Message-ID: <45C24AC5.4050705@yahoo.com>

On 02/01/2007 01:54 PM, Carl-Daniel Hailfinger wrote:
> Ed Swierk wrote:
>>>>  static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
>>>> @@ -228,7 +229,7 @@ static void aza_init(struct device *dev)
>>>>       if(!res)
>>>>               return;
>>>>
>>>> -     base =(uint8_t *) res->base;
>>>> +     base =(uint8_t *) ((uint32_t) res->base);
>>>>       printk_debug("base = %08x\n", base);
>>>>
>>>>       codec_mask = codec_detect(base);
>>> Are you really sure you want to cast a uint64_t to uint32_t to uint8_t
>>> * ?
>> I'm not sure. The current implementation truncates base to 32 bits, so
>> I suppose there ought to be a check that base doesn't exceed
>> 0xffffffff. But in this case the double-cast is still necessary to
>> avoid gcc's complaint about truncating while casting to a pointer.
> 
> Agreed.

Generally, everyone wants to be able to deal with 64-bit resources.
The 32-bit linuxbios does not allow to do it easily. Potentially, it
will migrate to 64-bit on some platforms. Such double cast will
create a bug in 64-bit mode. I think you should either suppress
the warning in the command line or make a function or macro that
casts integers to pointers. Do not do (uint32_t).

----------------------------
-	uint8_t str[48];
+	char str[48];
  	uint32_t *p;

  	msr_t msr;
@@ -533,7 +534,7 @@ static void amd_set_name_string_f(device
  	#endif
  	}

-	p = str;
+	p = (uint32_t *) str;
  	for(i=0;i<6;i++) {
  		msr.lo = *p;  p++; msr.hi = *p; p++;
  		wrmsr(0xc0010030+i, msr);
----------------------------
Do not do this unless you are sure that ((char)-1)-((uint8_t)-1)==0;
Sign extension in 'msr.lo = *p' may be important.

Regards,

Roman




From rminnich at gmail.com  Thu Feb  1 21:27:44 2007
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Feb 2007 13:27:44 -0700
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <20070201015250.29957.qmail@cdy.org>
References: <20070201014028.GE9824@greenwood> <45BAB815.1080700@gmx.net>
	<20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
Message-ID: <13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>

On 1/31/07, Peter Stuge <stuge-linuxbios at cdy.org> wrote:
> This patch adds the MCP55 PCI IDs (without which the southbridge code
> won't compile), and breaks an unnecessary dependency on the usbdebug
> code.
>
> Signed-off-by: Ed Swierk <eswierk at arastra.com>
> Acked-by: Peter Stuge <peter at stuge.se>
>

I'd like to repeat my previous question. Does acked imply committed?
How/when does the commit happen if someone does not have commit privs,
e.g. if neither the signer or acker can commit?

Could we get a comment when people commit?

thanks

ron



From eswierk at arastra.com  Thu Feb  1 22:17:50 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 1 Feb 2007 13:17:50 -0800
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <45C24AC5.4050705@yahoo.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
	<45C24575.1090401@gmx.net> <45C24AC5.4050705@yahoo.com>
Message-ID: <c1bf1cf0702011317q5c3560bal85cb0060a69de9f3@mail.gmail.com>

Here's a fix for the one warning we can all agree is a bug. We can
deal with the other issues separately.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From c-d.hailfinger.devel.2006 at gmx.net  Thu Feb  1 22:33:04 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Feb 2007 22:33:04 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
 bugs
In-Reply-To: <EE3C3F3D-CAC5-4223-BB51-8C4A62A9B129@kernel.crashing.org>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>	<45C236F4.7030600@gmx.net>
	<EE3C3F3D-CAC5-4223-BB51-8C4A62A9B129@kernel.crashing.org>
Message-ID: <45C25C90.7070108@gmx.net>

Segher Boessenkool wrote:
>> Hmmm. You know that the signedness of char is not defined?
> 
> It is defined, but implementation-defined.  Maybe you mean
> that "plain" char is a separate type from both signed char
> and unsigned char?

Mostly. I wanted to say that the signedness of char is
implementation-defined and differs between the linux targets
on different architectures (see S390 vs. the rest for an example).

>> Besides that, we definitely should enable -fno-strict-aliasing in the
>> gcc flags until we have audited all casts.
> 
> Well certainly as long as GCC keeps spitting warnings about
> this, it almost never gets these warnings wrong.

I don't know whether it is spitting warnings about aliasing,
but we're violating the aliasing rules described in the gcc
man page.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Thu Feb  1 22:47:23 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Feb 2007 22:47:23 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
References: <20070201014028.GE9824@greenwood>
	<45BAB815.1080700@gmx.net>	<20070127140322.GB6231@greenwood>	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>	<45C13020.1030103@coresystems.de>	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
Message-ID: <45C25FEB.3060605@gmx.net>

ron minnich wrote:
> I'd like to repeat my previous question. Does acked imply committed?

No, it should just mean that you agree with the patch and did not
modify it. Anybody can ack a patch.

> How/when does the commit happen if someone does not have commit privs,
> e.g. if neither the signer or acker can commit?

Someone steps up and commits?

> Could we get a comment when people commit?

Suggestion:
* The one who commits replies to the patch with "Applied."
* The commit mail is sent to the list automatically (already happens).

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Thu Feb  1 22:51:24 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Feb 2007 22:51:24 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
 bugs
In-Reply-To: <c1bf1cf0702011206r49ccd732l323ce495279f6c0c@mail.gmail.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>	<45C236F4.7030600@gmx.net>	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>	<45C24575.1090401@gmx.net>
	<c1bf1cf0702011206r49ccd732l323ce495279f6c0c@mail.gmail.com>
Message-ID: <45C260DC.2020700@gmx.net>

Ed Swierk wrote:
> On 2/1/07, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> The code says something different.
>>
>> static void delayx(uint8_t value) {
>>         int i;
>>         for(i=0;i<0x8000;i++) {
>>                 outb(value, 0x80);
>>         }
>> }
>>
>> The value is the POST code and has nothing to do with the delay.
>> So your patch changed the POST code from E8 (1000 mod 256) to 64 (100)
>> and called the delay function ten times.
> 
> So delayx() actually sets the POST code by writing some value 32768
> times, has nothing to do with delay, and the comments about delay are
> completely irrelevant? My brain just exploded.

Prepare for more explosions. The POST code is written 32768 times and
a side effect of writing to an I/O port on x86 is that it takes ~3 usec
depending on whom you ask. Why writing the POST code, you ask? Simple.
Port 0x80 is probably the one I/O port with the least side effects.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From svn at openbios.org  Thu Feb  1 23:43:27 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  1 Feb 2007 23:43:27 +0100
Subject: [LinuxBIOS] r2544 - trunk/LinuxBIOSv2/src/northbridge/amd/amdk8
Message-ID: <mailman.161.1355071057.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-02-01 23:43:27 +0100 (Thu, 01 Feb 2007)
New Revision: 2544

Modified:
   trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c
Log:
Fix typo which breaks the build ('defalut' should be 'default').

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c	2007-02-01 01:53:55 UTC (rev 2543)
+++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit_f.c	2007-02-01 22:43:27 UTC (rev 2544)
@@ -2506,7 +2506,7 @@
                                 case 0x00:
                                         dwordx = 0x002b2220; //x8 double Rank
                                         break;
-                                defalut:
+                                default:
                                         dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
                                 }
                         } else if((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {




From uwe at hermann-uwe.de  Thu Feb  1 23:44:13 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 23:44:13 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <c1bf1cf0702011317q5c3560bal85cb0060a69de9f3@mail.gmail.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
	<45C24575.1090401@gmx.net> <45C24AC5.4050705@yahoo.com>
	<c1bf1cf0702011317q5c3560bal85cb0060a69de9f3@mail.gmail.com>
Message-ID: <20070201224413.GA26359@greenwood>

On Thu, Feb 01, 2007 at 01:17:50PM -0800, Ed Swierk wrote:
> Here's a fix for the one warning we can all agree is a bug. We can
> deal with the other issues separately.

Good idea. Committed.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Feb  1 23:48:27 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 23:48:27 +0100
Subject: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O
In-Reply-To: <dcdcf0740701311802r4800506bh531e6627c286fb62@mail.gmail.com>
References: <20070125221350.GA16656@greenwood>
	<20070201015743.GG9824@greenwood>
	<dcdcf0740701311802r4800506bh531e6627c286fb62@mail.gmail.com>
Message-ID: <20070201224827.GB26359@greenwood>

Hi,

On Thu, Feb 01, 2007 at 10:02:08AM +0800, bxshi wrote:
> >> This is from Yinghai's huge patch. I added missing license headers
> >> (Yinghai please complain if any of them is incorrect!), fixed some
> >> coding style issues and added a few comments.
> >>
> >> The code is untested by me (didn't even test whether it builds)!
> >> Anybody wants to test this?
> 
> MSI ms9282 has w83627EHG. as I have tested ,yinghai's code is ok.

Great to hear! Can you post an "official" Acked-by?

Btw, does this mean we can expect a patch for the ms9282 soon? :-)


Cheers, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Feb  1 23:55:45 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Feb 2007 23:55:45 +0100
Subject: [LinuxBIOS] help from ubuntu and FC6 experts
In-Reply-To: <45B915A7.2010906@verizon.net>
References: <45B679F0.6010809@gmail.com>
	<1655C02E-F994-4550-9681-666E23F1DA47@kernel.crashing.org>
	<13426df10701240754i68152ebcs3aaa86624420fe44@mail.gmail.com>
	<45B7F22C.9000706@prodigi.ch>
	<58272BAE-1784-45F4-B4D0-24A71D896AB3@kernel.crashing.org>
	<45B800EF.6010109@prodigi.ch>
	<768C062B-C941-4711-8751-8C0D02468C25@kernel.crashing.org>
	<45B84ABC.9000203@verizon.net>
	<Pine.LNX.4.64.0701251024330.3362@bigred.russwhit.org>
	<45B915A7.2010906@verizon.net>
Message-ID: <20070201225545.GC26359@greenwood>

Hi,

On Thu, Jan 25, 2007 at 03:40:07PM -0500, Corey Osgood wrote:
> I've done nothing different than with any other build, except change the 
> symlinks in /usr/bin to point to gcc-3.3, etc (ubuntu doesn't have any 
> gcc-config style setup for easy changing of gcc versions).

Didn't they take 'update-alternatives' from Debian into Ubuntu?
Try 'update-alternatives cc' which should allow you to set the default
C compiler.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From bingxunshi at gmail.com  Fri Feb  2 01:20:51 2007
From: bingxunshi at gmail.com (bxshi)
Date: Fri, 2 Feb 2007 08:20:51 +0800
Subject: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O
In-Reply-To: <20070201224827.GB26359@greenwood>
References: <20070125221350.GA16656@greenwood>
	<20070201015743.GG9824@greenwood>
	<dcdcf0740701311802r4800506bh531e6627c286fb62@mail.gmail.com>
	<20070201224827.GB26359@greenwood>
Message-ID: <dcdcf0740702011620h73cbbae6tf0c9d1206437df3e@mail.gmail.com>

>
>
> > MSI ms9282 has w83627EHG. as I have tested ,yinghai's code is ok.
>
> Great to hear! Can you post an "official" Acked-by?
>
> Btw, does this mean we can expect a patch for the ms9282 soon? :-)


OK.    Acked-by: Bingxun Shi*  <*bingxunshi at gmail.com>

when all the MCP55 code combined in the source tree , I will post the MS9282
patch.  ;)


bxshi
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From bingxunshi at gmail.com  Fri Feb  2 02:03:19 2007
From: bingxunshi at gmail.com (bxshi)
Date: Fri, 2 Feb 2007 09:03:19 +0800
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <45C13020.1030103@coresystems.de>
References: <45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
Message-ID: <dcdcf0740702011703y1d7a09bg8a02eeb61fec81a7@mail.gmail.com>

>
> >yhlu wrote:
> > Good, Please apply at first. we may produce patch regarding with smbus
> > for send/receive byte
> > ( using CMD byte instead of DAT0)
> >
>
> >It's in. please go ahead.


Nvidia MCP55 use CMD to send/receive byte instead of DAT0 , the same as
broadcom/bcm5785. I have write a patch to do this.

signed-off-by : bxshi < bingxunshi at gmail.com>
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===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_smbus.h  (revision 2544)
+++ src/southbridge/nvidia/mcp55/mcp55_smbus.h  (working copy)
@@ -80,9 +80,7 @@
        /* set the device I'm talking too */
        outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
        smbus_delay();
-       /* set the command/address... */
-       outb(0, smbus_io_base + SMBHSTCMD);
-       smbus_delay();
+
        /* byte data recv */
        outb(0x05, smbus_io_base + SMBHSTPRTCL);
        smbus_delay();
@@ -95,7 +93,7 @@
        global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */

        /* read results of transaction */
-       byte = inb(smbus_io_base + SMBHSTDAT0);
+       byte = inb(smbus_io_base + SMBHSTCMD);

        if (global_status_register != 0x80) { // lose check, otherwise it should be 0
                return -1;
@@ -109,13 +107,14 @@
        outb(val, smbus_io_base + SMBHSTDAT0);
        smbus_delay();

+       /* set the command... */
+        outb(val, smbus_io_base + SMBHSTCMD);
+       smbus_delay();
+
        /* set the device I'm talking too */
        outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
        smbus_delay();

-       outb(0, smbus_io_base + SMBHSTCMD);
-       smbus_delay();
-
        /* set up for a byte data write */
        outb(0x04, smbus_io_base + SMBHSTPRTCL);
        smbus_delay();

From rminnich at gmail.com  Fri Feb  2 03:16:32 2007
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Feb 2007 19:16:32 -0700
Subject: [LinuxBIOS] help from ubuntu and FC6 experts
In-Reply-To: <20070201225545.GC26359@greenwood>
References: <45B679F0.6010809@gmail.com>
	<13426df10701240754i68152ebcs3aaa86624420fe44@mail.gmail.com>
	<45B7F22C.9000706@prodigi.ch>
	<58272BAE-1784-45F4-B4D0-24A71D896AB3@kernel.crashing.org>
	<45B800EF.6010109@prodigi.ch>
	<768C062B-C941-4711-8751-8C0D02468C25@kernel.crashing.org>
	<45B84ABC.9000203@verizon.net>
	<Pine.LNX.4.64.0701251024330.3362@bigred.russwhit.org>
	<45B915A7.2010906@verizon.net> <20070201225545.GC26359@greenwood>
Message-ID: <13426df10702011816s2a0985edsa94489d560789e55@mail.gmail.com>

I think what we need is a step in buildtarget that probes the C
compiler and sets options correctly.

I will try to look at this tomorrow; I'm installing ubuntu on a system
I have at home.

ron



From dhbarr at gozelle.com  Fri Feb  2 04:54:51 2007
From: dhbarr at gozelle.com (David H. Barr)
Date: Thu, 1 Feb 2007 21:54:51 -0600
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <45C25FEB.3060605@gmx.net>
References: <20070201014028.GE9824@greenwood> <45BAB815.1080700@gmx.net>
	<20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
	<45C25FEB.3060605@gmx.net>
Message-ID: <e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>

On 2/1/07, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> ron minnich wrote:
> > I'd like to repeat my previous question. Does acked imply committed?
>
> No, it should just mean that you agree with the patch and did not
> modify it. Anybody can ack a patch.
>
> > How/when does the commit happen if someone does not have commit privs,
> > e.g. if neither the signer or acker can commit?
>
> Someone steps up and commits?
>
> > Could we get a comment when people commit?
>
> Suggestion:
> * The one who commits replies to the patch with "Applied."
> * The commit mail is sent to the list automatically (already happens).

Signed-off-by: Some Guy <some at guy.com>
Acked-by: Some Gal <some at gal.com>
Applied-by: David H. Barr <dhbarr at gozelle.com>
  OR
Commited-by: David H. Barr <dhbarr at gozelle.com>

Is there some blindingly obvious reason why one of these two wouldn't
be appropriate?

-dhbarr.



From Libo.Feng at amd.com  Fri Feb  2 05:15:57 2007
From: Libo.Feng at amd.com (Feng, Libo)
Date: Fri, 2 Feb 2007 12:15:57 +0800
Subject: [LinuxBIOS] The two load RAM codes.
Message-ID: <82E7E37A29548444867DD81058AA62CE3B547C@sbjgexmb1.amd.com>


I am studying the LinuxBios project. I have a question about the RAM code: from Makefile, it seems that LinuxBios could load codes from FLASH to RAM twice, first for linuxbios_ram, second for so-called payload. My understanding is correct or not. However, also from Makefile, it seems that linuxbios is dependent on LINUXBIOS_RAM_ROM, but doesn't include it. The below is abstracted from a Makefile for via epia-m based on LinuxBiosV2-2534:

linuxbios: crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld 
        $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS) 
        $(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map. 

So, there is no action on LINUXBIOS_RAM_ROM. Does it mean linuxbios_ram is not very important. Even without it, the system is also ok?

Feng Libo 


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From segher at kernel.crashing.org  Fri Feb  2 07:26:48 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 2 Feb 2007 07:26:48 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <45C24AC5.4050705@yahoo.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>		<45C236F4.7030600@gmx.net>	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
	<45C24575.1090401@gmx.net> <45C24AC5.4050705@yahoo.com>
Message-ID: <62762013-2B38-4611-B457-767FB789997E@kernel.crashing.org>

> I think you should either suppress
> the warning in the command line or make a function or macro that
> casts integers to pointers.

Actually, you shouldn't use pointers to represent system
resources at all, that's just crazy.


Segher




From segher at kernel.crashing.org  Fri Feb  2 07:29:55 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 2 Feb 2007 07:29:55 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <c1bf1cf0702011317q5c3560bal85cb0060a69de9f3@mail.gmail.com>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>
	<45C236F4.7030600@gmx.net>
	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>
	<45C24575.1090401@gmx.net> <45C24AC5.4050705@yahoo.com>
	<c1bf1cf0702011317q5c3560bal85cb0060a69de9f3@mail.gmail.com>
Message-ID: <3C489D66-07B5-4552-AB14-8AC11D053770@kernel.crashing.org>

> Here's a fix for the one warning we can all agree is a bug. We can
> deal with the other issues separately.

> SW5kZXg6IExpbnV4QklPU3YyLTI1NDAvc3JjL25vcnRoYnJpZGdlL2FtZC9hbWRrOC9yYW 
> 1pbml0
> X2YuYwo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT 
> 09PT09
> PT09PT09PT09PT09PT09Ci0tLSBMaW51eEJJT1N2Mi0yNTQwLm9yaWcvc3JjL25vcnRoYn 
> JpZGdl
> L2FtZC9hbWRrOC9yYW1pbml0X2YuYworKysgTGludXhCSU9TdjItMjU0MC9zcmMvbm9ydG 
> hicmlk
> Z2UvYW1kL2FtZGs4L3JhbWluaXRfZi5jCkBAIC0yNTA2LDcgKzI1MDYsNyBAQCBzdGF0aW 
> Mgdm9p
> ZCBzZXRfbWlzY190aW1pbmcoY29uc3Qgc3RydWN0CiAgICAgICAgICAgICAgICAgICAgIC 
> AgICAg
> ICAgICAgIGNhc2UgMHgwMDoKICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIC 
> AgICAg
> ICBkd29yZHggPSAweDAwMmIyMjIwOyAvL3g4IGRvdWJsZSBSYW5rCiAgICAgICAgICAgIC 
> AgICAg
> ICAgICAgICAgICAgICAgICAgICAgICAgYnJlYWs7Ci0gICAgICAgICAgICAgICAgICAgIC 
> AgICAg
> ICAgICAgIGRlZmFsdXQ6CisgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGRlZm 
> F1bHQ6
> CiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZHdvcmR4ID0gMH 
> gwMDJh
> MjIyMDsgLy94OCBzaW5nbGUgUmFuayBhbmQgZG91YmxlIFJhbmsgbWl4ZWQKICAgICAgIC 
> AgICAg
> ICAgICAgICAgICAgICAgICAgICAgfQogICAgICAgICAgICAgICAgICAgICAgICAgfSBlbH 
> NlIGlm
> KChtZW1pbmZvLT54NF9tYXNrID09IDApICYmIChtZW1pbmZvLT54MTZfbWFzayA9PSAweD 
> AxKSAm
> JiAobWVtaW5mby0+c2luZ2xlX3JhbmtfbWFzayA9PSAweDAxKSkgewo=

Well I'm not sure I agree this is a good idea?  :-)


Segher




From segher at kernel.crashing.org  Fri Feb  2 07:33:03 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 2 Feb 2007 07:33:03 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <45C25C90.7070108@gmx.net>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>	<45C236F4.7030600@gmx.net>
	<EE3C3F3D-CAC5-4223-BB51-8C4A62A9B129@kernel.crashing.org>
	<45C25C90.7070108@gmx.net>
Message-ID: <6E43337E-3955-46F2-962A-A92D13448E11@kernel.crashing.org>

>> Well certainly as long as GCC keeps spitting warnings about
>> this, it almost never gets these warnings wrong.
>
> I don't know whether it is spitting warnings about aliasing,
> but we're violating the aliasing rules described in the gcc
> man page.

Described in the C standard, even.  There's a GCC option to
make it complain about suspicious pointer casting; I believe
it's called -Wstrict-aliasing?  It helps a lot, we should
have it enabled :-)


Segher




From segher at kernel.crashing.org  Fri Feb  2 07:34:45 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 2 Feb 2007 07:34:45 +0100
Subject: [LinuxBIOS] [PATCH] Fix various compiler warnings and potential
	bugs
In-Reply-To: <45C260DC.2020700@gmx.net>
References: <c1bf1cf0702010916j222083d8u863cb9fcd187c9ab@mail.gmail.com>	<45C236F4.7030600@gmx.net>	<c1bf1cf0702011146l6f406afen154bc380a238f58@mail.gmail.com>	<45C24575.1090401@gmx.net>
	<c1bf1cf0702011206r49ccd732l323ce495279f6c0c@mail.gmail.com>
	<45C260DC.2020700@gmx.net>
Message-ID: <87290B1E-155A-4E64-B9BA-6007BF503F77@kernel.crashing.org>

> Prepare for more explosions. The POST code is written 32768 times and
> a side effect of writing to an I/O port on x86 is that it takes ~3  
> usec
> depending on whom you ask. Why writing the POST code, you ask? Simple.
> Port 0x80 is probably the one I/O port with the least side effects.

There's also 0xeb, which is guaranteed to be empty (which makes
it even slower, at least on actual ISA systems).


Segher




From segher at kernel.crashing.org  Fri Feb  2 08:20:34 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 2 Feb 2007 08:20:34 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
References: <20070201014028.GE9824@greenwood> <45BAB815.1080700@gmx.net>
	<20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
Message-ID: <FD1E549B-3A35-4101-9B4A-092A2C9AE15E@kernel.crashing.org>

> I'd like to repeat my previous question. Does acked imply committed?
> How/when does the commit happen if someone does not have commit privs,
> e.g. if neither the signer or acker can commit?
>
> Could we get a comment when people commit?


http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html


Acked-by doesn't mean anything(*).  If you commit something for
someone else you should add your own Signed-off-by.


Segher


(*) ...in this context, of course;  it _is_ useful documentation,
but has no (semi-)formal meaning.




From segher at kernel.crashing.org  Fri Feb  2 08:22:40 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 2 Feb 2007 08:22:40 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>
References: <20070201014028.GE9824@greenwood> <45BAB815.1080700@gmx.net>
	<20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
	<45C25FEB.3060605@gmx.net>
	<e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>
Message-ID: <5A7F7F8F-418A-49E1-B111-802F2ED64F5F@kernel.crashing.org>

> Signed-off-by: Some Guy <some at guy.com>
> Acked-by: Some Gal <some at gal.com>
> Applied-by: David H. Barr <dhbarr at gozelle.com>
>   OR
> Commited-by: David H. Barr <dhbarr at gozelle.com>
>
> Is there some blindingly obvious reason why one of these two wouldn't
> be appropriate?

Yes -- it's what Signed-off-by is for already :-)


Segher




From indrek.kruusa at artecdesign.ee  Fri Feb  2 09:01:37 2007
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Fri, 2 Feb 2007 10:01:37 +0200
Subject: [LinuxBIOS] hda: lost interrupt  when executing linux kernel
In-Reply-To: <BAY132-F280498C85E7761FBD626DB5A40@phx.gbl>
References: <BAY132-F280498C85E7761FBD626DB5A40@phx.gbl>
Message-ID: <200702021001.37498.indrek.kruusa@artecdesign.ee>

?hel kenal p?eval (neljap?ev 01 veebruar 2007 4:44 am) kirjutas michal wan:
> 1 it looks ok running linuxbios and filo
> 2 loading kernel ok
>
> when  executing linux kernel, something occurs like "hda: lost interrupt"
>
> there are some problems which can be seen from the output of linux kernel
> 1  AMD5536: not 100% native mode: will probe irqs lalater
> 2 AMD5536: neither IDE port enabled (BIOS)


You don't have CS5536 properly configured for IDE.
grepping  MDD_PIN_OPT in source would help. This register is referred as 
DIVIL_BALL_OPT in CS5536's datasheet.
I suppose that in the future somebody will fix the source to match the 
datasheet.

cheers,
Indrek



>
> another problem is below
> in the function model_lx_init() from src/cpu/amd/model_lx/model_lx_init.c
> if umcomment setup_lapic() and vsm_end_post_smi(), it will occur supported
> interrupt 13, then  die
> i have uncomment the object  irq_tables.o in file
> src/mainboard/artecgroup/dbe61/Options.lb
>
> any advice would be appreciated!
>
> _________________________________________________________________
> ???? MSN Explorer:   http://explorer.msn.com/lccn



From stepan at coresystems.de  Fri Feb  2 08:58:59 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Feb 2007 08:58:59 +0100
Subject: [LinuxBIOS] help from ubuntu and FC6 experts
In-Reply-To: <13426df10702011816s2a0985edsa94489d560789e55@mail.gmail.com>
References: <13426df10701240754i68152ebcs3aaa86624420fe44@mail.gmail.com>
	<45B7F22C.9000706@prodigi.ch>
	<58272BAE-1784-45F4-B4D0-24A71D896AB3@kernel.crashing.org>
	<45B800EF.6010109@prodigi.ch>
	<768C062B-C941-4711-8751-8C0D02468C25@kernel.crashing.org>
	<45B84ABC.9000203@verizon.net>
	<Pine.LNX.4.64.0701251024330.3362@bigred.russwhit.org>
	<45B915A7.2010906@verizon.net> <20070201225545.GC26359@greenwood>
	<13426df10702011816s2a0985edsa94489d560789e55@mail.gmail.com>
Message-ID: <20070202075859.GA739@coresystems.de>

* ron minnich <rminnich at gmail.com> [070202 03:16]:
> I think what we need is a step in buildtarget that probes the C
> compiler and sets options correctly.

abuild does something like this already. So far it does not probe for
supported compiler flags but for the available cross compilers.

We could hop up abuild to generally become the configure and build tool
for LinuxBIOS v2.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From adam.kaufman at pinnacle.com  Fri Feb  2 14:45:53 2007
From: adam.kaufman at pinnacle.com (Kaufman,  Adam)
Date: Fri, 2 Feb 2007 08:45:53 -0500
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <B336556B53FC0F42AE59AD52F8B8D5BDAE7DFC@exchange01.pdsi.local>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com><B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local><45C1453A.2050906@coresystems.de>
	<B336556B53FC0F42AE59AD52F8B8D5BDAE7DFC@exchange01.pdsi.local>
Message-ID: <B336556B53FC0F42AE59AD52F8B8D5BD012382EF@exchange01.pdsi.local>

Ok, here's what I came up with for a Solaris 10 patch. I don't know that
it's the best way, but I tried to make somewhat clean. Feel free to
rewrite/suggest anything. Note that Solaris 10 removed the ability to
compile libc static, and I don't know if we think it's worth the effort,
so I just made checks to disable it for SunOS.

 

Thanks,

Adam

 

________________________________

From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Kaufman, Adam
Sent: Wednesday, January 31, 2007 9:00 PM
To: linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] LinuxBIOS Solaris Dev

 

Awesome! I think that did it. I'm not at the office right now, so I
don't want to reboot my test system, but it doesn't look like anything
blew up. Thanks for the help! If everything is good, I'll clean it up
and make a patch. Should be fairly minimal.

-ak

whodini# ./flashrom -w /mnt/adamk/tyan/2882v309.rom
Calibrating delay loop... ok
No LinuxBIOS table found.
Enabling flash write on AMD8111...OK
Pm49FL004 found at physical address: 0xfff80000
Flash part is Pm49FL004 (512 KB)
Flash image seems to be a legacy BIOS. Disabling checks.
Programming Page: 0007 at address: 0x00070000


-----Original Message-----
From: Stefan Reinauer [mailto:stefan.reinauer at coresystems.de]
Sent: Wed 31/01/2007 20:41
To: Kaufman,  Adam
Cc: linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] LinuxBIOS Solaris Dev

Kaufman, Adam wrote:
> Well, I had to do a bit of messing around, but I got both pciutils and
> flashrom to compile on my Solaris 10 box. My biggest concern was the
> /dev/mem wouldn't allow the same access we get on linux...  here's
what
> I get:
>
> bash-3.00# ./flashrom
> Calibrating delay loop... ok
> Can not mmap /dev/mem at 00000000 errno(6):No such device or address
>
> Ideas?

It looks /dev/mem only contains ram on solaris, not the complete address
space.

There's a workaround, try using /dev/xsvc instead. It is part of X (or
XFree?) as it seems.

http://blogs.sun.com/dmick/entry/patch_for_dmidecode_2_6



--
coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 . Fax: +49 761 7664613
Email: info at coresystems.de  . http://www.coresystems.de/




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From stefan.reinauer at coresystems.de  Fri Feb  2 14:58:05 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Feb 2007 14:58:05 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <B336556B53FC0F42AE59AD52F8B8D5BD012382EF@exchange01.pdsi.local>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com><B336556B53FC0F42AE59AD52F8B8D5BD012382EE@exchange01.pdsi.local><45C1453A.2050906@coresystems.de>	<B336556B53FC0F42AE59AD52F8B8D5BDAE7DFC@exchange01.pdsi.local>
	<B336556B53FC0F42AE59AD52F8B8D5BD012382EF@exchange01.pdsi.local>
Message-ID: <45C3436D.1020702@coresystems.de>

Kaufman, Adam wrote:
> Ok, here?s what I came up with for a Solaris 10 patch. I don?t know that
> it?s the best way, but I tried to make somewhat clean. Feel free to
> rewrite/suggest anything. Note that Solaris 10 removed the ability to
> compile libc static, and I don?t know if we think it?s worth the effort,
> so I just made checks to disable it for SunOS.
> 

mem.h does not look right:
> #if defined(sunos)
> #define MEM_DEV "/dev/mem"
> #else
> #define MEM_DEV "/dev/xsvc"
> #endif

should it be

#if !defined(__sun)

maybe?

Please post a Signed-off-by:
http://linuxbios.org/Development_Guidelines#How_to_contribute

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From adam.kaufman at pinnacle.com  Fri Feb  2 15:20:45 2007
From: adam.kaufman at pinnacle.com (Kaufman,  Adam)
Date: Fri, 2 Feb 2007 09:20:45 -0500
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
Message-ID: <B336556B53FC0F42AE59AD52F8B8D5BD012382F1@exchange01.pdsi.local>

Oops. Sorry. Here we go.

Signed-off-by: Adam Kaufman <adam.kaufman at pinnacle.com>



-----Original Message-----
From: Stefan Reinauer [mailto:stefan.reinauer at coresystems.de] 
Sent: Friday, February 02, 2007 8:58 AM
To: Kaufman, Adam
Cc: linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] LinuxBIOS Solaris Dev

Kaufman, Adam wrote:
> Ok, here's what I came up with for a Solaris 10 patch. I don't know
that
> it's the best way, but I tried to make somewhat clean. Feel free to
> rewrite/suggest anything. Note that Solaris 10 removed the ability to
> compile libc static, and I don't know if we think it's worth the
effort,
> so I just made checks to disable it for SunOS.
> 

mem.h does not look right:
> #if defined(sunos)
> #define MEM_DEV "/dev/mem"
> #else
> #define MEM_DEV "/dev/xsvc"
> #endif

should it be

#if !defined(__sun)

maybe?

Please post a Signed-off-by:
http://linuxbios.org/Development_Guidelines#How_to_contribute

-- 
coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 * Fax: +49 761 7664613
Email: info at coresystems.de  * http://www.coresystems.de/
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From stefan.reinauer at coresystems.de  Fri Feb  2 17:50:04 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Feb 2007 17:50:04 +0100
Subject: [LinuxBIOS] Sun Ultra40 patches
In-Reply-To: <45C2446C.8010403@yahoo.com>
References: <45C2446C.8010403@yahoo.com>
Message-ID: <45C36BBC.3070003@coresystems.de>

Roman Kononov wrote:
> This set of changes makes Sun Ultra40 working. Although not fully.
> 
> The working parts are: single CPU and nForce 2200 (CK804 Pro) with
> all stuff connected to it. The still-not-working parts are: second
> CPU and nForce 2050 with all stuff connected to it.
> 
> The changed files contain many things related to the non-working
> second CPU and nForce 2050 commented out in order to make the
> working system stable.
> 
> Thousand thanks to all who made the original Sun Ultra40 sources.
> 
> Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
> 

Could you please rediff with -w ? Something terribly broke the indenting.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From rminnich at gmail.com  Fri Feb  2 17:50:23 2007
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Feb 2007 09:50:23 -0700
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>
References: <20070201014028.GE9824@greenwood> <20070127140322.GB6231@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
	<45C25FEB.3060605@gmx.net>
	<e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>
Message-ID: <13426df10702020850n49d84f5cqf45dda5a68b9a565@mail.gmail.com>

On 2/1/07, David H. Barr <dhbarr at gozelle.com> wrote:

> Signed-off-by: Some Guy <some at guy.com>
> Acked-by: Some Gal <some at gal.com>
> Applied-by: David H. Barr <dhbarr at gozelle.com>
>   OR
> Commited-by: David H. Barr <dhbarr at gozelle.com>
>
> Is there some blindingly obvious reason why one of these two wouldn't
> be appropriate?

These are fine. But we need this info in the wiki.

ron



From rminnich at gmail.com  Fri Feb  2 17:51:38 2007
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Feb 2007 09:51:38 -0700
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <5A7F7F8F-418A-49E1-B111-802F2ED64F5F@kernel.crashing.org>
References: <20070201014028.GE9824@greenwood>
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>
	<45C13020.1030103@coresystems.de>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
	<45C25FEB.3060605@gmx.net>
	<e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>
	<5A7F7F8F-418A-49E1-B111-802F2ED64F5F@kernel.crashing.org>
Message-ID: <13426df10702020851k796a4d8u9b8f500622fcf251@mail.gmail.com>

On 2/2/07, Segher Boessenkool <segher at kernel.crashing.org> wrote:
> > Signed-off-by: Some Guy <some at guy.com>
> > Acked-by: Some Gal <some at gal.com>
> > Applied-by: David H. Barr <dhbarr at gozelle.com>
> >   OR
> > Commited-by: David H. Barr <dhbarr at gozelle.com>
> >
> > Is there some blindingly obvious reason why one of these two wouldn't
> > be appropriate?
>
> Yes -- it's what Signed-off-by is for already :-)

you are assuming that signed-off-by implies commit rights, and it doesn't.

signed-off-by is necessary but not sufficient. acked-by is necessary
but not sufficient.

ron



From stefan.reinauer at coresystems.de  Fri Feb  2 17:59:43 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Feb 2007 17:59:43 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <13426df10702020851k796a4d8u9b8f500622fcf251@mail.gmail.com>
References: <20070201014028.GE9824@greenwood>	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>	<45C13020.1030103@coresystems.de>	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>	<20070201015250.29957.qmail@cdy.org>	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>	<45C25FEB.3060605@gmx.net>	<e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>	<5A7F7F8F-418A-49E1-B111-802F2ED64F5F@kernel.crashing.org>
	<13426df10702020851k796a4d8u9b8f500622fcf251@mail.gmail.com>
Message-ID: <45C36DFF.5010907@coresystems.de>

ron minnich wrote:
> On 2/2/07, Segher Boessenkool <segher at kernel.crashing.org> wrote:
>>> Signed-off-by: Some Guy <some at guy.com>
>>> Acked-by: Some Gal <some at gal.com>
>>> Applied-by: David H. Barr <dhbarr at gozelle.com>
>>>   OR
>>> Commited-by: David H. Barr <dhbarr at gozelle.com>
>>>
>>> Is there some blindingly obvious reason why one of these two wouldn't
>>> be appropriate?
>> Yes -- it's what Signed-off-by is for already :-)
> 
> you are assuming that signed-off-by implies commit rights, and it doesn't.
> 
> signed-off-by is necessary but not sufficient. acked-by is necessary
> but not sufficient.
> 

committed-by can be retrieved from the svn system per revision.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Fri Feb  2 18:08:04 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Feb 2007 18:08:04 +0100
Subject: [LinuxBIOS] r2545 - in trunk/LinuxBIOSv2/src/mainboard:
	amd/serengeti_leopard tyan/s2891 tyan/s2895
Message-ID: <mailman.162.1355071057.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-02 18:08:04 +0100 (Fri, 02 Feb 2007)
New Revision: 2545

Modified:
   trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb
Log:
Remove hardcoded gcc versions otherwise the build will break for
most people.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb	2007-02-01 22:43:27 UTC (rev 2544)
+++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Options.lb	2007-02-02 17:08:04 UTC (rev 2545)
@@ -254,8 +254,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32"
-default HOSTCC="gcc-4.0.2"
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default

Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb	2007-02-01 22:43:27 UTC (rev 2544)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb	2007-02-02 17:08:04 UTC (rev 2545)
@@ -226,8 +226,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc-3.3.6 -m32"
-default HOSTCC="gcc-3.3.6"
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default

Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb	2007-02-01 22:43:27 UTC (rev 2544)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb	2007-02-02 17:08:04 UTC (rev 2545)
@@ -234,8 +234,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32"
-default HOSTCC="gcc-4.0.2"
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default




From rminnich at gmail.com  Fri Feb  2 18:32:08 2007
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Feb 2007 10:32:08 -0700
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <45C36DFF.5010907@coresystems.de>
References: <20070201014028.GE9824@greenwood>
	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
	<45C25FEB.3060605@gmx.net>
	<e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>
	<5A7F7F8F-418A-49E1-B111-802F2ED64F5F@kernel.crashing.org>
	<13426df10702020851k796a4d8u9b8f500622fcf251@mail.gmail.com>
	<45C36DFF.5010907@coresystems.de>
Message-ID: <13426df10702020932r6bc6ebcs6eff453a5eb579f4@mail.gmail.com>

On 2/2/07, Stefan Reinauer <stefan.reinauer at coresystems.de> wrote:

> committed-by can be retrieved from the svn system per revision.

I guess I am not being clear. What I want to see, in email, is that a
fix got committed. We recently saw a bunch of patches hit the list,
with signed-off-by, then acked-by, and then I have no idea if that
particular set of patches was committed. So a committed-by would be
useful to me. I'd like to see it in the same thread of mail that the
discussion of the patches occurred in. Then I can look at the thread
and even search for a committed-by.

is there something about this that makes no sense?

ron



From rminnich at gmail.com  Fri Feb  2 18:40:34 2007
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Feb 2007 10:40:34 -0700
Subject: [LinuxBIOS] new feature - CrushK8-04 USB1 Controller Reset
In-Reply-To: <45C24449.501@yahoo.com>
References: <45C24449.501@yahoo.com>
Message-ID: <13426df10702020940ge2a3f23m9da0e5d65e33636b@mail.gmail.com>

Hi Roman, this patch looks fine save for one thing: I believe that the
// comments were supposed to be deprecated. I can not find a reference
for this, however; anybody care to correct me?

signed,

a former // coment user



From c-d.hailfinger.devel.2006 at gmx.net  Fri Feb  2 18:54:15 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 02 Feb 2007 18:54:15 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <13426df10702020932r6bc6ebcs6eff453a5eb579f4@mail.gmail.com>
References: <20070201014028.GE9824@greenwood>	<c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>	<20070201015250.29957.qmail@cdy.org>	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>	<45C25FEB.3060605@gmx.net>	<e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>	<5A7F7F8F-418A-49E1-B111-802F2ED64F5F@kernel.crashing.org>	<13426df10702020851k796a4d8u9b8f500622fcf251@mail.gmail.com>	<45C36DFF.5010907@coresystems.de>
	<13426df10702020932r6bc6ebcs6eff453a5eb579f4@mail.gmail.com>
Message-ID: <45C37AC7.1060000@gmx.net>

ron minnich wrote:
> On 2/2/07, Stefan Reinauer <stefan.reinauer at coresystems.de> wrote:
> 
>> committed-by can be retrieved from the svn system per revision.
> 
> I guess I am not being clear. What I want to see, in email, is that a
> fix got committed. We recently saw a bunch of patches hit the list,
> with signed-off-by, then acked-by, and then I have no idea if that
> particular set of patches was committed. So a committed-by would be
> useful to me. I'd like to see it in the same thread of mail that the
> discussion of the patches occurred in. Then I can look at the thread
> and even search for a committed-by.

Ah OK, that makes sense. So you want to find out quickly which version
of a patch was committed without manually comparing the checkin
message with all patches on the list.

> is there something about this that makes no sense?

Now that you cleared it up, I think it is a useful tool. But I would
not use Committed-by or such stuff. Simply a short reply "Applied."

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From uwe at hermann-uwe.de  Fri Feb  2 18:58:47 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Feb 2007 18:58:47 +0100
Subject: [LinuxBIOS] Sun Ultra40 patches
In-Reply-To: <45C36BBC.3070003@coresystems.de>
References: <45C2446C.8010403@yahoo.com> <45C36BBC.3070003@coresystems.de>
Message-ID: <20070202175847.GB3142@greenwood>

Hi,

On Fri, Feb 02, 2007 at 05:50:04PM +0100, Stefan Reinauer wrote:
> Roman Kononov wrote:
> > This set of changes makes Sun Ultra40 working. Although not fully.
> > 
> > The working parts are: single CPU and nForce 2200 (CK804 Pro) with
> > all stuff connected to it. The still-not-working parts are: second
> > CPU and nForce 2050 with all stuff connected to it.
> > 
> > The changed files contain many things related to the non-working
> > second CPU and nForce 2050 commented out in order to make the
> > working system stable.
> > 
> > Thousand thanks to all who made the original Sun Ultra40 sources.
> > 
> > Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
> > 
> 
> Could you please rediff with -w ? Something terribly broke the indenting.

I guess this was intended. It looks like Roman fixed the coding style(?)
E.g. replaced spaces with tabs in a number of places...

Such patches should be submitted separately from "real" code changes,
though, to make it easier to review the patches.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Feb  2 19:00:59 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Feb 2007 19:00:59 +0100
Subject: [LinuxBIOS] new feature - CrushK8-04 USB1 Controller Reset
In-Reply-To: <13426df10702020940ge2a3f23m9da0e5d65e33636b@mail.gmail.com>
References: <45C24449.501@yahoo.com>
	<13426df10702020940ge2a3f23m9da0e5d65e33636b@mail.gmail.com>
Message-ID: <20070202180059.GC3142@greenwood>

Hi,

On Fri, Feb 02, 2007 at 10:40:34AM -0700, ron minnich wrote:
> Hi Roman, this patch looks fine save for one thing: I believe that the
> // comments were supposed to be deprecated. I can not find a reference
> for this, however; anybody care to correct me?

Well, not sure. // comments are valid in C++, but not (ANSI?) C as far
as I know. But in practice compilers allow both, except if you pass some
command line options like -pedantic and others...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Feb  2 19:04:03 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Feb 2007 19:04:03 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <13426df10702020932r6bc6ebcs6eff453a5eb579f4@mail.gmail.com>
References: <c1bf1cf0701311743y1eda5680w6dc6dc97bfd1dd9a@mail.gmail.com>
	<c1bf1cf0701311653w6c3b6308rda3a21f4f2bd6d8c@mail.gmail.com>
	<20070201015250.29957.qmail@cdy.org>
	<13426df10702011227y60dd4af9w439dee7368a05b13@mail.gmail.com>
	<45C25FEB.3060605@gmx.net>
	<e8d467740702011954o55ac7d19s99ba351af48cb1c0@mail.gmail.com>
	<5A7F7F8F-418A-49E1-B111-802F2ED64F5F@kernel.crashing.org>
	<13426df10702020851k796a4d8u9b8f500622fcf251@mail.gmail.com>
	<45C36DFF.5010907@coresystems.de>
	<13426df10702020932r6bc6ebcs6eff453a5eb579f4@mail.gmail.com>
Message-ID: <20070202180403.GD3142@greenwood>

Hi,

On Fri, Feb 02, 2007 at 10:32:08AM -0700, ron minnich wrote:
> On 2/2/07, Stefan Reinauer <stefan.reinauer at coresystems.de> wrote:
> 
> > committed-by can be retrieved from the svn system per revision.
> 
> I guess I am not being clear. What I want to see, in email, is that a
> fix got committed. We recently saw a bunch of patches hit the list,
> with signed-off-by, then acked-by, and then I have no idea if that
> particular set of patches was committed. So a committed-by would be
> useful to me. I'd like to see it in the same thread of mail that the
> discussion of the patches occurred in. Then I can look at the thread
> and even search for a committed-by.

I don't think we need an explicit Committed-by or similar tag, but a
short email saying that the patch was committed should suffice, right?

We mostly already do this anyways...

If we lose the overview of pending patches that is a clear sign that we
should use the tracker more often.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Feb  2 19:08:37 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 02 Feb 2007 19:08:37 +0100
Subject: [LinuxBIOS] new feature - CrushK8-04 USB1 Controller Reset
In-Reply-To: <20070202180059.GC3142@greenwood>
References: <45C24449.501@yahoo.com>	<13426df10702020940ge2a3f23m9da0e5d65e33636b@mail.gmail.com>
	<20070202180059.GC3142@greenwood>
Message-ID: <45C37E25.7020203@gmx.net>

Uwe Hermann wrote:
> Hi,
> 
> On Fri, Feb 02, 2007 at 10:40:34AM -0700, ron minnich wrote:
>> Hi Roman, this patch looks fine save for one thing: I believe that the
>> // comments were supposed to be deprecated. I can not find a reference
>> for this, however; anybody care to correct me?
> 
> Well, not sure. // comments are valid in C++, but not (ANSI?) C as far
> as I know. But in practice compilers allow both, except if you pass some
> command line options like -pedantic and others...

IIRC the C99 standard is the first C standard to allow // comments.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From kononov195-lbl at yahoo.com  Fri Feb  2 21:10:13 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Fri, 02 Feb 2007 14:10:13 -0600
Subject: [LinuxBIOS] Sun Ultra40 patches
In-Reply-To: <20070202175847.GB3142@greenwood>
References: <45C2446C.8010403@yahoo.com> <45C36BBC.3070003@coresystems.de>
	<20070202175847.GB3142@greenwood>
Message-ID: <45C39AA5.1010202@yahoo.com>

On 02/02/2007 11:58 AM, Uwe Hermann wrote:
> On Fri, Feb 02, 2007 at 05:50:04PM +0100, Stefan Reinauer wrote:
>> Could you please rediff with -w ? Something terribly broke the indenting.
> 
> I guess this was intended. It looks like Roman fixed the coding style(?)
> E.g. replaced spaces with tabs in a number of places...
> 
> Such patches should be submitted separately from "real" code changes,
> though, to make it easier to review the patches.

Rediffing with -w will not help. Fixing coding style first will not help
either. This is not as simple as a patch. It is a major re-writing.
The current code in the repository is half-finished and works only
by an accident. Reviewers should apply the patch and try to understand
what is going on there.

Regards, Roman



From kononov195-lbl at yahoo.com  Fri Feb  2 21:21:52 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Fri, 02 Feb 2007 14:21:52 -0600
Subject: [LinuxBIOS] Sun Ultra40 patches
In-Reply-To: <45C36BBC.3070003@coresystems.de>
References: <45C2446C.8010403@yahoo.com> <45C36BBC.3070003@coresystems.de>
Message-ID: <45C39D60.2090108@yahoo.com>

On 02/02/2007 10:50 AM, Stefan Reinauer wrote:
> Could you please rediff with -w ? Something terribly broke the indenting.

Yes, indenting is broken. I diffed it with -Bb.
This one is diffed without -Bbw.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
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From kononov195-lbl at yahoo.com  Fri Feb  2 21:28:28 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Fri, 02 Feb 2007 14:28:28 -0600
Subject: [LinuxBIOS] new feature - CrushK8-04 USB1 Controller Reset
In-Reply-To: <45C37E25.7020203@gmx.net>
References: <45C24449.501@yahoo.com>	<13426df10702020940ge2a3f23m9da0e5d65e33636b@mail.gmail.com>	<20070202180059.GC3142@greenwood>
	<45C37E25.7020203@gmx.net>
Message-ID: <45C39EEC.6060903@yahoo.com>

On 02/02/2007 12:08 PM, Carl-Daniel Hailfinger wrote:
> IIRC the C99 standard is the first C standard to allow // comments.

I vote for allowing // comments since:

1. they are a C standard
2. they do not clutter so much
3. they make life easier for many people
4. the current code has too many GCC-specific things anyway

Roman




From uwe at hermann-uwe.de  Fri Feb  2 21:53:27 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Feb 2007 21:53:27 +0100
Subject: [LinuxBIOS] new feature - CrushK8-04 USB1 Controller Reset
In-Reply-To: <45C39EEC.6060903@yahoo.com>
References: <45C24449.501@yahoo.com>
	<13426df10702020940ge2a3f23m9da0e5d65e33636b@mail.gmail.com>
	<20070202180059.GC3142@greenwood> <45C37E25.7020203@gmx.net>
	<45C39EEC.6060903@yahoo.com>
Message-ID: <20070202205326.GA14359@greenwood>

Hi,

On Fri, Feb 02, 2007 at 02:28:28PM -0600, Roman Kononov wrote:
> On 02/02/2007 12:08 PM, Carl-Daniel Hailfinger wrote:
> > IIRC the C99 standard is the first C standard to allow // comments.
> 
> I vote for allowing // comments since:

Yeah, I agree. This is not so critical, IMHO. If we really care, we can
always replace them later... We got more important things to do right now :)

Besides, we already have lots of // comments in the code anyway.

 
> 4. the current code has too many GCC-specific things anyway

This is more important IMHO than the // comments. We should keep
LinuxBIOS as compiler-/toolchain-independant as possible (if we can).

Patches to improve the situation are welcome :)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From mcqmcqmcq at fastmail.fm  Fri Feb  2 21:53:52 2007
From: mcqmcqmcq at fastmail.fm (mcqmcqmcq at fastmail.fm)
Date: Fri, 02 Feb 2007 12:53:52 -0800
Subject: [LinuxBIOS] DK8-HTX: 8131 A-bus running slow
Message-ID: <1170449632.26053.1172646371@webmail.messagingengine.com>

Guys,

Once my DK8-HTX is up and running in Linux, I observe that the 8131 is
programmed thusly (full regdump and my cute little utility attached):

  /proc/bus/pci/00/0b.0: AMD 8131 PCI-X Tunnel PCI-X Bridge
  0x40 PCI-X Miscellaneous Register
     1-1  Conentional PCI mode frequency      RW    0    0 33 MHz
  0xa0 PCI-X Secondary Status Register
    24-22 Secondary clock frequency           R     0    3 133 MHz PCI-X

  /proc/bus/pci/00/0a.0: AMD 8131 PCI-X Tunnel PCI-X Bridge
  0x40 PCI-X Miscellaneous Register
     1-1  Conentional PCI mode frequency      RW    0    1 66 Mhz
  0xa0 PCI-X Secondary Status Register
    24-22 Secondary clock frequency           R     0    0 conventional PCI

In particular, the A-bus 0a.0 is massively horribly slow (50MB/s to my RAID
card as opposed to 350MB/s in the 0b.0 slot).  I only see one speed line during
LB bootup and would expect two (one for each bus):

  Capability: 0x07 @ 0xa0
  PCI: 03: 133MHz PCI-X

So my theory is that the A-bus is just never getting configued at all (nobody
who uses LB does I/O, right?  ;-).  Can anybody confirm or deny this theory, and
possibly point me toward what I might do to fix it?

As an aside, I'm still working from the r2520 I was ages ago.  YH, you were once
going to look into repeating the hangs I was seeing with a Pathscale HTX IB card
installed (during HT reset in iwill/dk8_htx/cache_as_ram_auto.c) -- did that ever
go anywhere?  Once I get this sucker fully tested, I'll summarize what I've done
to get it there and compare to svn head for you guys' continued entertainment.

Thanks, y'all,

-mcq
-- 
  
  mcqmcqmcq at fastmail.fm

-- 
http://www.fastmail.fm - Send your email first class

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From stefan.reinauer at coresystems.de  Fri Feb  2 22:12:47 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Feb 2007 22:12:47 +0100
Subject: [LinuxBIOS] Sun Ultra40 patches
In-Reply-To: <45C39AA5.1010202@yahoo.com>
References: <45C2446C.8010403@yahoo.com>
	<45C36BBC.3070003@coresystems.de>	<20070202175847.GB3142@greenwood>
	<45C39AA5.1010202@yahoo.com>
Message-ID: <45C3A94F.8060707@coresystems.de>

Roman Kononov wrote:
> Rediffing with -w will not help. Fixing coding style first will not help
> either. This is not as simple as a patch. It is a major re-writing.
> The current code in the repository is half-finished and works only
> by an accident. Reviewers should apply the patch and try to understand
> what is going on there.
> 

There's pretty much stuff like the following, which is obviously not one
of those parts of the major rewrite ;-)

But let me look into it some more, and get back to it.

>  ## Compute the start location and size size of
>  ## The linuxBIOS bootloader.
>  ##
> -default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
> +default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
>  default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
> -default CONFIG_ROM_PAYLOAD     = 1
> +default CONFIG_ROM_PAYLOAD       = 1
>  
>  ##
>  ## Compute where this copy of linuxBIOS will start in the boot rom
> @@ -33,7 +33,7 @@ default _ROMBASE      = ( CONFIG_ROM_PAY
>  default XIP_ROM_SIZE=65536
>  default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
>  
> -arch i386 end 
> +arch i386 end
>  
>  
>  ##




-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From kononov195-lbl at yahoo.com  Fri Feb  2 22:22:31 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Fri, 02 Feb 2007 15:22:31 -0600
Subject: [LinuxBIOS] [PATCH] romstream off-by-1
In-Reply-To: <45C36D7D.4000109@coresystems.de>
References: <45C11C24.2050502@yahoo.com> <45C36D7D.4000109@coresystems.de>
Message-ID: <45C3AB97.9060506@yahoo.com>

On 02/02/2007 10:57 AM, Stefan Reinauer wrote:
> I suggest comparing (rom + bytes - 1) > rom_end, because rom_end seems
> to be the logical border we're checking for.

(rom + bytes - 1 > rom_end) equals to (rom + bytes > rom_end + 1)
provided that
[rom,rom_end+1) does not cross 0x7fffffff+1 and ptrdiff_t is signed,
or
[rom,rom_end+1) does not corss 0xffffffff+1 and ptrdiff_t is unsigned.
In linuxbios, [rom,rom_end+1) crosses neither boundary.

Strictly speaking, an exception for the first statement is when
    ptrdiff_t is signed (which is our case);
    rom+bytes-1 does not overflow and is 0x7fffffff;
    rom+bytes does overflow and is 0x80000000;
    rom_end is, for example, 0xffff0000.
Then,
   (rom + bytes - 1 > rom_end) is true
   (rom + bytes > rom_end + 1) is false
For this to happen rom must be within
[0x00000000-0x7fffffff], which is impossible.

Any way, you flavor is attached.

Regards,

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>

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From svn at openbios.org  Fri Feb  2 23:40:11 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Feb 2007 23:40:11 +0100
Subject: [LinuxBIOS] r2546 - trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804
Message-ID: <mailman.163.1355071057.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2007-02-02 23:40:10 +0100 (Fri, 02 Feb 2007)
New Revision: 2546

Modified:
   trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h
   trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c
Log:
I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforce
2200 (too many names, sounds like a criminal).

1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works
fine.

2) Then I push the reset button.

3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
about wrong checksum of the mptable and crushes later.

An investigation showed that in 3), short after kernel A (v2.6.19.2)
sets
the Bus Master Enable bit of the nVidia's USB1 controller
(pci_set_master()),
the mptable gets two bytes at physical address 0x80 damaged.

Nothing is plugged to the USB ports. Other two Sun workstations had the
same
behavior. This does not make sense to me unless the controller has a HW
bug.

I believe, this should better be fixed in the kernel USB driver.

For now this patch offers a possibility for linuxbios to reset the USB
controller by setting HostControllerReset bit in HcCommandStatus
Register.
It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
southbridge/nvidia/ck804' section of the mainboard's Config.lb.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com



Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h	2007-02-02 17:08:04 UTC (rev 2545)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h	2007-02-02 22:40:10 UTC (rev 2546)
@@ -1,10 +1,11 @@
 #ifndef CK804_CHIP_H
 #define CK804_CHIP_H
 
-struct southbridge_nvidia_ck804_config 
+struct southbridge_nvidia_ck804_config
 {
-        unsigned int ide0_enable : 1;
-        unsigned int ide1_enable : 1;
+	unsigned int usb1_hc_reset : 1;
+	unsigned int ide0_enable : 1;
+	unsigned int ide1_enable : 1;
 	unsigned int sata0_enable : 1;
 	unsigned int sata1_enable : 1;
 	unsigned long nic_rom_address;

Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c	2007-02-02 17:08:04 UTC (rev 2545)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c	2007-02-02 22:40:10 UTC (rev 2546)
@@ -9,9 +9,22 @@
 #include <device/pci_ops.h>
 #include "ck804.h"
 
+static void usb1_init(struct device *dev) {
+	struct southbridge_nvidia_ck804_config const * conf=dev->chip_info;
+	if (conf->usb1_hc_reset) {
+		//Somehow the warm reset does not really resets the USB controller.
+		//Later, during boot, when the Bus Master bit is set, the USB
+		//controller trashes the memory, causing weird misbehavior.
+		//Was detected on Sun Ultra40, where mptable was damaged.
+		uint32_t bar0=pci_read_config32(dev,0x10);
+		uint32_t* regs=(uint32_t*)(bar0&~0xfff);
+		regs[2]|=1;	//OHCI USB HCCommandStatus Register, HostControllerReset bit
+	}
+}
+
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{       
-        pci_write_config32(dev, 0x40, 
+{
+        pci_write_config32(dev, 0x40,
                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 static struct pci_operations lops_pci = {
@@ -22,7 +35,7 @@
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
+	.init             = usb1_init,
 //	.enable           = ck804_enable,
 	.scan_bus         = 0,
 	.ops_pci          = &lops_pci,




From rminnich at gmail.com  Fri Feb  2 23:40:43 2007
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Feb 2007 15:40:43 -0700
Subject: [LinuxBIOS] new feature - CrushK8-04 USB1 Controller Reset
In-Reply-To: <45C24449.501@yahoo.com>
References: <45C24449.501@yahoo.com>
Message-ID: <13426df10702021440m7e42f72aic4508005736b32fa@mail.gmail.com>

On 2/1/07, Roman Kononov <kononov195-lbl at yahoo.com> wrote:
> I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforce
> 2200 (too many names, sounds like a criminal).
>
> 1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works fine.
>
> 2) Then I push the reset button.
>
> 3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
> about wrong checksum of the mptable and crushes later.
>
> An investigation showed that in 3), short after kernel A (v2.6.19.2) sets
> the Bus Master Enable bit of the nVidia's USB1 controller (pci_set_master()),
> the mptable gets two bytes at physical address 0x80 damaged.
>
> Nothing is plugged to the USB ports. Other two Sun workstations had the same
> behavior. This does not make sense to me unless the controller has a HW bug.
>
> I believe, this should better be fixed in the kernel USB driver.
>
> For now this patch offers a possibility for linuxbios to reset the USB
> controller by setting HostControllerReset bit in HcCommandStatus Register.
> It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
> southbridge/nvidia/ck804' section of the mainboard's Config.lb.
>
> Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Committed revision 2546.



From yinghai.lu at amd.com  Fri Feb  2 23:52:10 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 2 Feb 2007 14:52:10 -0800
Subject: [LinuxBIOS] r2546 -
 trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804
Message-ID: <5986589C150B2F49A46483AC44C7BCA4907407@ssvlexmb2.amd.com>

YES

-----Original Message-----
From: linuxbios-bounces+yinghai.lu=amd.com at linuxbios.org
[mailto:linuxbios-bounces+yinghai.lu=amd.com at linuxbios.org] On Behalf Of
svn at openbios.org
Sent: Friday, February 02, 2007 2:40 PM
To: linuxbios at linuxbios.org
Subject: [LinuxBIOS] r2546 -
trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804

Author: rminnich
Date: 2007-02-02 23:40:10 +0100 (Fri, 02 Feb 2007)
New Revision: 2546

Modified:
   trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h
   trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c
Log:
I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforce
2200 (too many names, sounds like a criminal).

1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works
fine.

2) Then I push the reset button.

3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
about wrong checksum of the mptable and crushes later.

An investigation showed that in 3), short after kernel A (v2.6.19.2)
sets
the Bus Master Enable bit of the nVidia's USB1 controller
(pci_set_master()),
the mptable gets two bytes at physical address 0x80 damaged.

Nothing is plugged to the USB ports. Other two Sun workstations had the
same
behavior. This does not make sense to me unless the controller has a HW
bug.

I believe, this should better be fixed in the kernel USB driver.

For now this patch offers a possibility for linuxbios to reset the USB
controller by setting HostControllerReset bit in HcCommandStatus
Register.
It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
southbridge/nvidia/ck804' section of the mainboard's Config.lb.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com



Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h
2007-02-02 17:08:04 UTC (rev 2545)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/chip.h
2007-02-02 22:40:10 UTC (rev 2546)
@@ -1,10 +1,11 @@
 #ifndef CK804_CHIP_H
 #define CK804_CHIP_H
 
-struct southbridge_nvidia_ck804_config 
+struct southbridge_nvidia_ck804_config
 {
-        unsigned int ide0_enable : 1;
-        unsigned int ide1_enable : 1;
+	unsigned int usb1_hc_reset : 1;
+	unsigned int ide0_enable : 1;
+	unsigned int ide1_enable : 1;
 	unsigned int sata0_enable : 1;
 	unsigned int sata1_enable : 1;
 	unsigned long nic_rom_address;

Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c
2007-02-02 17:08:04 UTC (rev 2545)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_usb.c
2007-02-02 22:40:10 UTC (rev 2546)
@@ -9,9 +9,22 @@
 #include <device/pci_ops.h>
 #include "ck804.h"
 
+static void usb1_init(struct device *dev) {
+	struct southbridge_nvidia_ck804_config const *
conf=dev->chip_info;
+	if (conf->usb1_hc_reset) {
+		//Somehow the warm reset does not really resets the USB
controller.
+		//Later, during boot, when the Bus Master bit is set,
the USB
+		//controller trashes the memory, causing weird
misbehavior.
+		//Was detected on Sun Ultra40, where mptable was
damaged.
+		uint32_t bar0=pci_read_config32(dev,0x10);
+		uint32_t* regs=(uint32_t*)(bar0&~0xfff);
+		regs[2]|=1;	//OHCI USB HCCommandStatus Register,
HostControllerReset bit
+	}
+}
+
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned
device)
-{       
-        pci_write_config32(dev, 0x40, 
+{
+        pci_write_config32(dev, 0x40,
                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 static struct pci_operations lops_pci = {
@@ -22,7 +35,7 @@
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
+	.init             = usb1_init,
 //	.enable           = ck804_enable,
 	.scan_bus         = 0,
 	.ops_pci          = &lops_pci,


-- 
linuxbios mailing list
linuxbios at linuxbios.org
http://www.openbios.org/mailman/listinfo/linuxbios







From yinghai.lu at amd.com  Sat Feb  3 01:02:17 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 2 Feb 2007 16:02:17 -0800
Subject: [LinuxBIOS] [PATCH] romstream off-by-1
Message-ID: <5986589C150B2F49A46483AC44C7BCA4907408@ssvlexmb2.amd.com>

+	if ((rom + bytes - 1) > rom_end) {

Would be good.

YH


Index: src/stream/rom_stream.c
===================================================================
--- src/stream/rom_stream.c	(revision 2542)
+++ src/stream/rom_stream.c	(working copy)
@@ -116,7 +116,7 @@ byte_offset_t stream_skip(byte_offset_t 
 {
 	byte_offset_t bytes;
 	bytes = count;
-	if ((rom + bytes) > rom_end) {
+	if (rom+bytes-1 > rom_end) {
 		printk_warning("%6d:%s() - overflowed source buffer\n",
 			__LINE__, __FUNCTION__);
 		bytes = 0;



-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Roman Kononov
Sent: Friday, February 02, 2007 1:23 PM
To: LinuxBIOS
Subject: Re: [LinuxBIOS] [PATCH] romstream off-by-1

On 02/02/2007 10:57 AM, Stefan Reinauer wrote:
> I suggest comparing (rom + bytes - 1) > rom_end, because rom_end seems
> to be the logical border we're checking for.

(rom + bytes - 1 > rom_end) equals to (rom + bytes > rom_end + 1)
provided that
[rom,rom_end+1) does not cross 0x7fffffff+1 and ptrdiff_t is signed,
or
[rom,rom_end+1) does not corss 0xffffffff+1 and ptrdiff_t is unsigned.
In linuxbios, [rom,rom_end+1) crosses neither boundary.

Strictly speaking, an exception for the first statement is when
    ptrdiff_t is signed (which is our case);
    rom+bytes-1 does not overflow and is 0x7fffffff;
    rom+bytes does overflow and is 0x80000000;
    rom_end is, for example, 0xffff0000.
Then,
   (rom + bytes - 1 > rom_end) is true
   (rom + bytes > rom_end + 1) is false
For this to happen rom must be within
[0x00000000-0x7fffffff], which is impossible.

Any way, you flavor is attached.

Regards,

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>






From yinghai.lu at amd.com  Sat Feb  3 01:04:33 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 2 Feb 2007 16:04:33 -0800
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
Message-ID: <5986589C150B2F49A46483AC44C7BCA4907409@ssvlexmb2.amd.com>

We may consider moving ids to mcp55_ids.h later like kernel do. Instead
of tough pci_ids.h


YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Ed Swierk
Sent: Wednesday, January 31, 2007 4:54 PM
To: LinuxBIOS
Subject: Re: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code

On 1/31/07, Stefan Reinauer <stefan.reinauer at coresystems.de> wrote:
> It's in. please go ahead.

Cool. Can you apply this patch next? It adds the MCP55 PCI IDs
(without which the southbridge code won't compile), and breaks an
unnecessary dependency on the usbdebug code.

Acked-by: Ed Swierk <eswierk at arastra.com>

--Ed





From yinghai.lu at amd.com  Sat Feb  3 01:05:17 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 2 Feb 2007 16:05:17 -0800
Subject: [LinuxBIOS] [PATCH] amdk8_sysconf.h type corrected
Message-ID: <5986589C150B2F49A46483AC44C7BCA490740A@ssvlexmb2.amd.com>

Good catch.

YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Roman Kononov
Sent: Wednesday, January 31, 2007 2:25 PM
To: LinuxBIOS
Subject: Re: [LinuxBIOS] [PATCH] amdk8_sysconf.h type corrected

This fixes a small typo.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
---

On 01/31/2007 03:19 PM, Peter Stuge wrote:
> Please have a look at http://linuxbios.org/Development_Guidelines

Thank you






From yinghai.lu at amd.com  Sat Feb  3 01:17:28 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 2 Feb 2007 16:17:28 -0800
Subject: [LinuxBIOS] [PATCH] e820 table correction
Message-ID: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>

Actually that is because of Andi's patch cause the problem.

I was wondering why we can not use these ram.

It is good if update kernel instead.

YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Roman Kononov
Sent: Wednesday, January 31, 2007 2:37 PM
To: LinuxBIOS
Subject: [LinuxBIOS] [PATCH] e820 table correction

Hello,

I have this situation:

Linuxbios boots an Opteron motherboard with 1GB memory.

Linuxbios directly loads a recent linux kernel.
The memory layout is like this:

BIOS-provided physical RAM map:
    BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
    BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
    BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
    BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
    BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)

The f0000-f0400 region contains IRQ and ACPI tables.

At some point the kernel builds a resource table containing
all physical address ranges and type of hardware the addresses
are mapped to. The table is accessible via /proc/iomem:

# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
e0000000-efffffff : PCI Bus #03
     e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
     f4000000-f4ffffff : 0000:03:00.0
     f5000000-f5ffffff : 0000:03:00.0
     f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
     f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
     f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
     f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

As you can see, the 00000000000f0400-0000000040000000
region is not listed.

It is not listed because the kernel unconditionally adds
"000f0000-000fffff : System ROM" first (look for
"request_resource(&iomem_resource, &system_rom_resource)"),
and then the attempt to add f0400-40000000 range fails
because of overlapping.

The kernel does not care that the range is not listed there.
Kexec does. It uses the /proc/iomem file to instruct the
kexec system call how to place the segments of a new kernel
in the physical memory. Kexec fails to start a new kernel
because it cannot locate enough physical memory.

This must be fixed either in linux or linuxbios.

Assuming that linuxbios is to be fixed, I cooked a patch
which provides this memory layout:

BIOS-provided physical RAM map:
    BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
    BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
    BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
    BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
    BIOS-e820: 0000000000100000 - 0000000040000000 (usable)

The /proc/iomem contains:

# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
00100000-3fffffff : System RAM
     00100000-00203c61 : Kernel code
     00203c62-00248c3f : Kernel data
e0000000-efffffff : PCI Bus #03
     e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
     f4000000-f4ffffff : 0000:03:00.0
     f5000000-f5ffffff : 0000:03:00.0
     f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
     f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
     f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
     f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

Kexec is happier with the patch.

Regards,

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
---


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From yinghai.lu at amd.com  Sat Feb  3 01:25:07 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 2 Feb 2007 16:25:07 -0800
Subject: [LinuxBIOS] The two load RAM codes.
Message-ID: <5986589C150B2F49A46483AC44C7BCA490740C@ssvlexmb2.amd.com>

LinuxBIOS have three parts

1.	linuxbios for init RAM, and Cache_as_RAM. Code is Flash, and
stack is in CACHE. From cache_as_ram_main()
2.	linuxbios_ram: for PCI device handling. ---  from hardwaremain()
Code is in ram and unzipped from rom by 1.
3.	payload: it could be Etherboot ( boot from Network) or Kernel.
Elfloader in 2 will load payload and jmp to it.

 

Also the flash will contain three linuxbios.rom

Normal+Fallback+Failover.

Failover will be used to init 64K above rom access.

 

YH

 

________________________________

From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Feng, Libo
Sent: Thursday, February 01, 2007 8:16 PM
To: linuxbios at linuxbios.org
Subject: [LinuxBIOS] The two load RAM codes.

 

 

I am studying the LinuxBios project. I have a question about the RAM
code: from Makefile, it seems that LinuxBios could load codes from FLASH
to RAM twice, first for linuxbios_ram, second for so-called payload. My
understanding is correct or not. However, also from Makefile, it seems
that linuxbios is dependent on LINUXBIOS_RAM_ROM, but doesn't include
it. The below is abstracted from a Makefile for via epia-m based on
LinuxBiosV2-2534:

linuxbios: crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM)
ldscript.ld
        $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld
crt0.o $(INIT-OBJECTS)
        $(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map. 

So, there is no action on LINUXBIOS_RAM_ROM. Does it mean linuxbios_ram
is not very important. Even without it, the system is also ok?

Feng Libo 

 

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From yinghai.lu at amd.com  Sat Feb  3 01:30:09 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Fri, 2 Feb 2007 16:30:09 -0800
Subject: [LinuxBIOS] DK8-HTX: 8131 A-bus running slow
Message-ID: <5986589C150B2F49A46483AC44C7BCA490740E@ssvlexmb2.amd.com>

Is there any jumper there?

YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of
mcqmcqmcq at fastmail.fm
Sent: Friday, February 02, 2007 12:54 PM
To: linuxbios at linuxbios.org
Subject: [LinuxBIOS] DK8-HTX: 8131 A-bus running slow

Guys,

Once my DK8-HTX is up and running in Linux, I observe that the 8131 is
programmed thusly (full regdump and my cute little utility attached):

  /proc/bus/pci/00/0b.0: AMD 8131 PCI-X Tunnel PCI-X Bridge
  0x40 PCI-X Miscellaneous Register
     1-1  Conentional PCI mode frequency      RW    0    0 33 MHz
  0xa0 PCI-X Secondary Status Register
    24-22 Secondary clock frequency           R     0    3 133 MHz PCI-X

  /proc/bus/pci/00/0a.0: AMD 8131 PCI-X Tunnel PCI-X Bridge
  0x40 PCI-X Miscellaneous Register
     1-1  Conentional PCI mode frequency      RW    0    1 66 Mhz
  0xa0 PCI-X Secondary Status Register
    24-22 Secondary clock frequency           R     0    0 conventional
PCI

In particular, the A-bus 0a.0 is massively horribly slow (50MB/s to my
RAID
card as opposed to 350MB/s in the 0b.0 slot).  I only see one speed line
during
LB bootup and would expect two (one for each bus):

  Capability: 0x07 @ 0xa0
  PCI: 03: 133MHz PCI-X

So my theory is that the A-bus is just never getting configued at all
(nobody
who uses LB does I/O, right?  ;-).  Can anybody confirm or deny this
theory, and
possibly point me toward what I might do to fix it?

As an aside, I'm still working from the r2520 I was ages ago.  YH, you
were once
going to look into repeating the hangs I was seeing with a Pathscale HTX
IB card
installed (during HT reset in iwill/dk8_htx/cache_as_ram_auto.c) -- did
that ever
go anywhere?  Once I get this sucker fully tested, I'll summarize what
I've done
to get it there and compare to svn head for you guys' continued
entertainment.

Thanks, y'all,

-mcq
-- 
  
  mcqmcqmcq at fastmail.fm

-- 
http://www.fastmail.fm - Send your email first class






From ebiederm at xmission.com  Sat Feb  3 01:45:53 2007
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Fri, 02 Feb 2007 17:45:53 -0700
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	(Yinghai Lu's message of "Fri, 2 Feb 2007 16:17:28 -0800")
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
Message-ID: <m1mz3w3w72.fsf@ebiederm.dsl.xmission.com>

"Lu, Yinghai" <yinghai.lu at amd.com> writes:

> Actually that is because of Andi's patch cause the problem.
>
> I was wondering why we can not use these ram.
>
> It is good if update kernel instead.

Yes.  It looks like we have a little fallout from this cleanup.
There is a related issue with just reserving part of the first initial
page confusing things as well.

I will try and look into this soon if no one beats me to it, but I
need a break hunting for the moment.

Eric



From stuge-linuxbios at cdy.org  Sat Feb  3 02:15:28 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Sat, 3 Feb 2007 02:15:28 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <B336556B53FC0F42AE59AD52F8B8D5BD012382EF@exchange01.pdsi.local>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>
	<B336556B53FC0F42AE59AD52F8B8D5BDAE7DFC@exchange01.pdsi.local>
	<B336556B53FC0F42AE59AD52F8B8D5BD012382EF@exchange01.pdsi.local>
Message-ID: <20070203011528.10135.qmail@cdy.org>

On Fri, Feb 02, 2007 at 08:45:53AM -0500, Kaufman,  Adam wrote:
> Ok, here's what I came up with for a Solaris 10 patch.

Could all of the defines be compressed into one place? Maybe one
mem.c per system and defines controlling the build process?
Am I being overzealous about portability?

Also, it would be nice if the error messages printed the device that
was being used.


//Peter



From michalwan at hotmail.com  Sat Feb  3 05:51:00 2007
From: michalwan at hotmail.com (michal wan)
Date: Sat, 03 Feb 2007 12:51:00 +0800
Subject: [LinuxBIOS] Unexpected Exception: 13
Message-ID: <BAY132-F34BCDCDCBBA068D67DC0A1B59A0@phx.gbl>

in the file src/cpu/amd/model_lx/model_lx_init.c

static void model_lx_init(device_t dev)
{
       printk_debug("model_lx_init\n");

       /* Turn on caching if we haven't already */

       x86_enable_cache();

       /* Enable the local cpu apics */
       //setup_lapic();

       // do VSA late init
       vsm_end_post_smi();

       // Set gate A20 (legacy vsm disables it in late init)
       printk_debug("A20 (0x92): %d\n",inb(0x92));
       outb(0x02,0x92);
       printk_debug("A20 (0x92): %d\n",inb(0x92));

       printk_debug("model_lx_init DONE\n");
};
~
when using vsm_end_post_smi() function, Unexpected Exception occures, any 
advice would be appreciated!

_________________________________________________________________
?????????????? MSN Messenger:  http://messenger.msn.com/cn  
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From ak at suse.de  Sat Feb  3 06:09:18 2007
From: ak at suse.de (Andi Kleen)
Date: Sat, 3 Feb 2007 06:09:18 +0100
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
Message-ID: <200702030609.18318.ak@suse.de>

On Saturday 03 February 2007 01:17, Lu, Yinghai wrote:
> Actually that is because of Andi's patch cause the problem.

What patch? 

-Andi



From iwill-KA266 at mytrashmail.com  Sat Feb  3 07:42:33 2007
From: iwill-KA266 at mytrashmail.com (iwill-KA266 at mytrashmail.com)
Date: Fri, 02 Feb 2007 23:42:33 -0700
Subject: [LinuxBIOS] iWill KA266 m/b
Message-ID: <1170484953.13276.1172697859@webmail.messagingengine.com>

Please advise on suitability for the latest LinuxBIOS.  The current BIOS
says net boot is possible, would like to use in LinuxBIOS.  (Yes two
sound devices, m/b plus a PCI card.)

Thanks - very nice work you do


iWill KA266 motherboard (ATX) (*not* KA266-R variant)
CPU = AMD Athlon 1333 MHz Socket 462
North Bridge = ALi M1647
South Bridge = ALi 1535D+
Current BIOS = Award Modular BIOS v6.00PG circa 2001

OEM Manual (PDF)
http://support.iwill.net/supports/manual/ka266.pdf


# lspci
0000:00:00.0 Host bridge: ALi Corporation M1647 Northbridge [MAGiK 1 /
MobileMAGiK 1] (rev 02)
0000:00:01.0 PCI bridge: ALi Corporation PCI to AGP Controller
0000:00:04.0 IDE interface: ALi Corporation M5229 IDE (rev c4)
0000:00:07.0 ISA bridge: ALi Corporation M1533 PCI to ISA Bridge
[Aladdin IV]
0000:00:0b.0 USB Controller: NEC Corporation USB (rev 41)
0000:00:0b.1 USB Controller: NEC Corporation USB (rev 41)
0000:00:0b.2 USB Controller: NEC Corporation USB 2.0 (rev 02)
0000:00:0c.0 Ethernet controller: Standard Microsystems Corp [SMC]
83c170 EPIC/100 Fast Ethernet Adapter (rev 08)
0000:00:0d.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1
(rev 07)
0000:00:0d.1 Input device controller: Creative Labs SB Live! MIDI/Game
Port (rev 07)
0000:00:0f.0 Multimedia audio controller: C-Media Electronics Inc CM8738
(rev 10)
0000:00:11.0 Bridge: ALi Corporation M7101 Power Management Controller
[PMU]
0000:01:00.0 VGA compatible controller: nVidia Corporation NV20
[GeForce3] (rev a3)




From svn at openbios.org  Sat Feb  3 11:43:48 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  3 Feb 2007 11:43:48 +0100
Subject: [LinuxBIOS] r2547 - trunk/LinuxBIOSv2/src/stream
Message-ID: <mailman.164.1355071057.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-03 11:43:48 +0100 (Sat, 03 Feb 2007)
New Revision: 2547

Modified:
   trunk/LinuxBIOSv2/src/stream/rom_stream.c
Log:
This eliminates an illegal and annoying warning.

'rom' is the current read pointer.
'rom_end' points to last valid byte of the stream. 

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/stream/rom_stream.c
===================================================================
--- trunk/LinuxBIOSv2/src/stream/rom_stream.c	2007-02-02 22:40:10 UTC (rev 2546)
+++ trunk/LinuxBIOSv2/src/stream/rom_stream.c	2007-02-03 10:43:48 UTC (rev 2547)
@@ -116,7 +116,7 @@
 {
 	byte_offset_t bytes;
 	bytes = count;
-	if ((rom + bytes) > rom_end) {
+	if ((rom + bytes - 1) > rom_end) {
 		printk_warning("%6d:%s() - overflowed source buffer\n",
 			__LINE__, __FUNCTION__);
 		bytes = 0;




From stefan.reinauer at coresystems.de  Sat Feb  3 11:44:23 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Feb 2007 11:44:23 +0100
Subject: [LinuxBIOS] [PATCH] romstream off-by-1
In-Reply-To: <45C3AB97.9060506@yahoo.com>
References: <45C11C24.2050502@yahoo.com> <45C36D7D.4000109@coresystems.de>
	<45C3AB97.9060506@yahoo.com>
Message-ID: <45C46787.8050203@coresystems.de>

Roman Kononov wrote:

> Regards,
> 
> Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
> 

applied.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stefan.reinauer at coresystems.de  Sat Feb  3 12:08:32 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Feb 2007 12:08:32 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA4907409@ssvlexmb2.amd.com>
References: <5986589C150B2F49A46483AC44C7BCA4907409@ssvlexmb2.amd.com>
Message-ID: <45C46D30.5030703@coresystems.de>

Lu, Yinghai wrote:
> We may consider moving ids to mcp55_ids.h later like kernel do. Instead
> of tough pci_ids.h

Is there a reason why we need all those IDs in one file?
Or, do we ever need IDs from more than 1 southbridge and 1 northbridge
vendor?



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stefan.reinauer at coresystems.de  Sat Feb  3 15:49:19 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Feb 2007 15:49:19 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <20070203011528.10135.qmail@cdy.org>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>	<B336556B53FC0F42AE59AD52F8B8D5BDAE7DFC@exchange01.pdsi.local>	<B336556B53FC0F42AE59AD52F8B8D5BD012382EF@exchange01.pdsi.local>
	<20070203011528.10135.qmail@cdy.org>
Message-ID: <45C4A0EF.7050100@coresystems.de>

Peter Stuge wrote:
> On Fri, Feb 02, 2007 at 08:45:53AM -0500, Kaufman,  Adam wrote:
>> Ok, here's what I came up with for a Solaris 10 patch.
> 
> Could all of the defines be compressed into one place? Maybe one
> mem.c per system and defines controlling the build process?
> Am I being overzealous about portability?

Check the attached patch. The utility is, as many parts of the linuxbios
source, a little bit overpopulated with includes.

There's no seperate mem.[ch] anymore, as the code is pretty much
identical except it is using a define instead of a hardcode now.

With 2 lines in flash.h you could make it work on BeOS as well. :-)

> Also, it would be nice if the error messages printed the device that
> was being used.

done.


If you're ok, please Ack this patch

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
-------------- next part --------------
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From svn at openbios.org  Sat Feb  3 16:23:34 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  3 Feb 2007 16:23:34 +0100
Subject: [LinuxBIOS] r2548 - trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55
Message-ID: <mailman.165.1355071057.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-03 16:23:34 +0100 (Sat, 03 Feb 2007)
New Revision: 2548

Modified:
   trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h
Log:
Nvidia MCP55 uses CMD to send/receive bytes instead of DAT0, 
that's the same as broadcom/bcm5785. 

Signed-off-by: bxshi <bingxunshi at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h	2007-02-03 10:43:48 UTC (rev 2547)
+++ trunk/LinuxBIOSv2/src/southbridge/nvidia/mcp55/mcp55_smbus.h	2007-02-03 15:23:34 UTC (rev 2548)
@@ -80,9 +80,7 @@
 	/* set the device I'm talking too */
 	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
 	smbus_delay();
-	/* set the command/address... */
-	outb(0, smbus_io_base + SMBHSTCMD);
-	smbus_delay();
+
 	/* byte data recv */
 	outb(0x05, smbus_io_base + SMBHSTPRTCL);
 	smbus_delay();
@@ -95,7 +93,7 @@
 	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
 
 	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
+	byte = inb(smbus_io_base + SMBHSTCMD);
 
 	if (global_status_register != 0x80) { // lose check, otherwise it should be 0
 		return -1;
@@ -109,13 +107,14 @@
 	outb(val, smbus_io_base + SMBHSTDAT0);
 	smbus_delay();
 
+	/* set the command... */
+	outb(val, smbus_io_base + SMBHSTCMD);
+	smbus_delay();
+
 	/* set the device I'm talking too */
 	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
 	smbus_delay();
 
-	outb(0, smbus_io_base + SMBHSTCMD);
-	smbus_delay();
-
 	/* set up for a byte data write */
 	outb(0x04, smbus_io_base + SMBHSTPRTCL);
 	smbus_delay();




From stefan.reinauer at coresystems.de  Sat Feb  3 16:23:56 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Feb 2007 16:23:56 +0100
Subject: [LinuxBIOS] [PATCH] cleaned up MCP55 chipset code
In-Reply-To: <dcdcf0740702011703y1d7a09bg8a02eeb61fec81a7@mail.gmail.com>
References: <45BAB815.1080700@gmx.net> <20070127140322.GB6231@greenwood>	
	<2ea3fae10701271851m1eba0059l775670012849a91b@mail.gmail.com>	
	<45C13020.1030103@coresystems.de>
	<dcdcf0740702011703y1d7a09bg8a02eeb61fec81a7@mail.gmail.com>
Message-ID: <45C4A90C.9020903@coresystems.de>

bxshi wrote:

> Nvidia MCP55 use CMD to send/receive byte instead of DAT0 , the same as
> broadcom/bcm5785. I have write a patch to do this.
>  
> signed-off-by : bxshi < bingxunshi at gmail.com <mailto:bingxunshi at gmail.com>>

Applied.

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coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Sat Feb  3 16:28:20 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  3 Feb 2007 16:28:20 +0100
Subject: [LinuxBIOS] r2549 - in trunk/LinuxBIOSv2/src/superio/winbond: .
	w83627ehg
Message-ID: <mailman.166.1355071057.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-03 16:28:20 +0100 (Sat, 03 Feb 2007)
New Revision: 2549

Added:
   trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/
   trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/Config.lb
   trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/chip.h
   trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/superio.c
   trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg.h
   trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_init.c
   trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c
Log:
Add support for the Winbond W83627EHG Super I/O.

Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Bingxun Shi  <bingxunshi at gmail.com>



Added: trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/Config.lb	2007-02-03 15:28:20 UTC (rev 2549)
@@ -0,0 +1,24 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+config chip.h
+object superio.o
+

Added: trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/chip.h	2007-02-03 15:28:20 UTC (rev 2549)
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SIO_COM1
+#define SIO_COM1_BASE 0x3f8
+#endif
+#ifndef SIO_COM2
+#define SIO_COM2_BASE 0x2f8
+#endif
+
+extern struct chip_operations superio_winbond_w83627ehg_ops;
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct superio_winbond_w83627ehg_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};

Added: trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/superio.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/superio.c	2007-02-03 15:28:20 UTC (rev 2549)
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan 
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <pc80/mc146818rtc.h>
+#include "chip.h"
+#include "w83627ehg.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+	outb(0x87, dev->path.u.pnp.port);
+	outb(0x87, dev->path.u.pnp.port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	outb(0xaa, dev->path.u.pnp.port);
+}
+
+static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
+{
+	outb(reg, port_base);
+	outb(value, port_base + 1);
+}
+
+static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
+{
+	outb(reg, port_base);
+	return inb(port_base + 1);
+}
+
+static void enable_hwm_smbus(device_t dev) {
+	/* Set the pin 91,92 as I2C bus. */
+	uint8_t reg, value;
+	reg = 0x2a;
+	value = pnp_read_config(dev, reg);
+	value |= (1 << 1);
+	pnp_write_config(dev, reg, value);
+}
+
+static void init_acpi(device_t dev)
+{
+	uint8_t value = 0x20;
+	int power_on = 1;
+
+	get_option(&power_on, "power_on_after_fail");
+	pnp_enter_ext_func_mode(dev);
+	pnp_write_index(dev->path.u.pnp.port, 7, 0x0a);
+	value = pnp_read_config(dev, 0xe4);
+	value &= ~(3 << 5);
+	if (power_on) {
+		value |= (1 << 5);
+	}
+	pnp_write_config(dev, 0xe4, value);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static void init_hwm(unsigned long base)
+{
+	int i;
+	uint8_t reg, value;
+
+	/* reg mask data */
+	unsigned hwm_reg_values[] = {
+		0x40, 0xff, 0x81, /* Start HWM. */
+		0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */
+	};
+
+	for(i = 0; i < sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i += 3) {
+		reg = hwm_reg_values[i];
+		value = pnp_read_index(base, reg);
+		value &= 0xff & (~(hwm_reg_values[i + 1]));
+		value |= 0xff & hwm_reg_values[i + 2];
+		// printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
+		pnp_write_index(base, reg, value);
+	}
+}
+
+static void w83627ehg_init(device_t dev)
+{
+	struct superio_winbond_w83627ehg_config *conf;
+	struct resource *res0, *res1;
+	if (!dev->enabled) {
+		return;
+	}
+	conf = dev->chip_info;
+	switch(dev->path.u.pnp.device) {
+	case W83627EHG_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case W83627EHG_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case W83627EHG_KBC:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	case W83627EHG_HWM:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+#define HWM_INDEX_PORT 5
+		init_hwm(res0->base + HWM_INDEX_PORT);
+		break;
+	case W83627EHG_ACPI:
+		init_acpi(dev);
+		break;
+	}
+}
+
+void w83627ehg_pnp_set_resources(device_t dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_resources(dev);
+	pnp_exit_ext_func_mode(dev);
+}
+
+void w83627ehg_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_enable_resources(dev);
+
+	switch (dev->path.u.pnp.device) {
+	case W83627EHG_HWM:
+		printk_debug("w83627ehg hwm smbus enabled\n");
+		enable_hwm_smbus(dev);
+		break;
+	}
+
+	pnp_exit_ext_func_mode(dev);
+}
+
+void w83627ehg_pnp_enable(device_t dev)
+{
+	if (!dev->enabled) {
+		pnp_enter_ext_func_mode(dev);
+		pnp_set_logical_device(dev);
+		pnp_set_enable(dev, 0);
+		pnp_exit_ext_func_mode(dev);
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = w83627ehg_pnp_set_resources,
+	.enable_resources = w83627ehg_pnp_enable_resources,
+	.enable           = w83627ehg_pnp_enable,
+	.init             = w83627ehg_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, W83627EHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	// No 4 { 0,},
+	{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627EHG_GPIO_GAME_MIDI, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
+	{ &ops, W83627EHG_WDTO_PLED, },
+	{ &ops, W83627EHG_GPIO_SUSLED, },
+	{ &ops, W83627EHG_ACPI, },
+	{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_winbond_w83627ehg_ops = {
+	CHIP_NAME("Winbond W83627EHG Super I/O")
+	.enable_dev = enable_dev,
+};
+

Added: trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg.h	2007-02-03 15:28:20 UTC (rev 2549)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define W83627EHG_FDC              0   /* Floppy */
+#define W83627EHG_PP               1   /* Parallel Port */
+#define W83627EHG_SP1              2   /* Com1 */
+#define W83627EHG_SP2              3   /* Com2 */
+#define W83627EHG_KBC              5   /* Keyboard & Mouse */
+#define W83627EHG_SFI              6   /* Serial Flash Interface */
+#define W83627EHG_GPIO_GAME_MIDI   7   /* GPIO1, GPIO6, Game Port and MIDI Port */
+#define W83627EHG_WDTO_PLED        8   /* TODO */
+#define W83627EHG_GPIO_SUSLED      9   /* GPIO2, GPIO3, GPIO4, GPIO5 and SUSLED */
+#define W83627EHG_ACPI            10   /* ACPI */
+#define W83627EHG_HWM             11   /* Hardware Monitor */
+

Added: trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_init.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_init.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_init.c	2007-02-03 15:28:20 UTC (rev 2549)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83627ehg.h"
+
+static void w83627ehg_disable_dev(device_t dev)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+}
+
+static void w83627ehg_enable_dev(device_t dev, unsigned iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}
+

Added: trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c	2007-02-03 15:28:20 UTC (rev 2549)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83627ehg.h"
+
+static inline void pnp_enter_ext_func_mode(device_t dev)
+{
+	unsigned port = dev >> 8;
+	outb(0x87, port);
+	outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	unsigned port = dev >> 8;
+	outb(0xaa, port);
+}
+
+static void w83627ehg_enable_serial(device_t dev, unsigned iobase)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_ext_func_mode(dev);
+}
+




From stefan.reinauer at coresystems.de  Sat Feb  3 16:30:38 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Feb 2007 16:30:38 +0100
Subject: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O
In-Reply-To: <20070125221350.GA16656@greenwood>
References: <20070125221350.GA16656@greenwood>
Message-ID: <45C4AA9E.7060708@coresystems.de>

Uwe Hermann wrote:
> Add support for the Winbond W83627EHG Super I/O.
> 
> Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

applied.

> This is from Yinghai's huge patch. I added missing license headers
> (Yinghai please complain if any of them is incorrect!), fixed some
> coding style issues and added a few comments.

What's still missing from Yinghai's patch now?



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stefan.reinauer at coresystems.de  Sat Feb  3 16:53:58 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Feb 2007 16:53:58 +0100
Subject: [LinuxBIOS] [PATCH] VGA is used before it is initialized
In-Reply-To: <45C134C2.1050802@yahoo.com>
References: <45AEB79A.6040308@yahoo.com>	<45C0DF72.3040800@yahoo.com>	<45C0E48A.4060603@coresystems.de>	<45C0EFC6.3050007@yahoo.com>	<45C0F371.7000602@coresystems.de>	<45C127B9.4070603@yahoo.com>
	<20070131235327.12140.qmail@cdy.org> <45C134C2.1050802@yahoo.com>
Message-ID: <45C4B016.2080601@coresystems.de>

Roman Kononov wrote:
> On 01/31/2007 05:53 PM, Peter Stuge wrote:
>> +#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_CONSOLE_VGA=1  One or two = ?
>> Which is it?
> 
> None.
> 

I cleaned the patch up a bit, and and added some comments. I will apply
it as soon as someone sends an Acked-by.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
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From yinghailu at gmail.com  Sun Feb  4 03:39:24 2007
From: yinghailu at gmail.com (yhlu)
Date: Sat, 3 Feb 2007 18:39:24 -0800
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <200702030609.18318.ak@suse.de>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	<200702030609.18318.ak@suse.de>
Message-ID: <2ea3fae10702031839h4c939910yeb40327f0f56e5f2@mail.gmail.com>

commit dbf9272e863bf4b17ee8e3c66c26682b2061d40d
Author: Andi Kleen <ak at suse.de>
Date:   Tue Sep 26 10:52:36 2006 +0200

    [PATCH] Don't force reserve the 640k-1MB range

    From i386 x86-64 inherited code to force reserve the 640k-1MB area.
    That was needed on some old systems.

    But we generally trust the e820 map to be correct on 64bit systems
    and mark all areas that are not memory correctly.

    This patch will allow to use the real memory in there.

    Or rather the only way to find out if it's still needed is to
    try. So far I'm optimistic.

    Signed-off-by: Andi Kleen <ak at suse.de>

diff --git a/arch/x86_64/kernel/e820.c b/arch/x86_64/kernel/e820.c
index 164d0b8..e06c271 100644
--- a/arch/x86_64/kernel/e820.c
+++ b/arch/x86_64/kernel/e820.c
@@ -71,12 +71,7 @@ static inline int bad_addr(unsigned long *addrp,
unsigned long size)
 		return 1;
 	}
 #endif
-	/* kernel code + 640k memory hole (later should not be needed, but
-	   be paranoid for now) */
-	if (last >= 640*1024 && addr < 1024*1024) {
-		*addrp = 1024*1024;
-		return 1;
-	}
+	/* kernel code */
 	if (last >= __pa_symbol(&_text) && last < __pa_symbol(&_end)) {
 		*addrp = __pa_symbol(&_end);
 		return 1;
@@ -519,13 +514,6 @@ static int __init sanitize_e820_map(struct
e820entry * biosmap, char * pnr_map)
  * If we're lucky and live on a modern system, the setup code
  * will have given us a memory map that we can use to properly
  * set up memory.  If we aren't, we'll fake a memory map.
- *
- * We check to see that the memory map contains at least 2 elements
- * before we'll use it, because the detection code in setup.S may
- * not be perfect and most every PC known to man has two memory
- * regions: one from 0 to 640k, and one from 1mb up.  (The IBM
- * thinkpad 560x, for example, does not cooperate with the memory
- * detection code.)
  */
 static int __init copy_e820_map(struct e820entry * biosmap, int nr_map)
 {
@@ -543,25 +531,6 @@ static int __init copy_e820_map(struct e820entry
* biosmap, int nr_map)
 		if (start > end)
 			return -1;

-		/*
-		 * Some BIOSes claim RAM in the 640k - 1M region.
-		 * Not right. Fix it up.
-		 *
-		 * This should be removed on Hammer which is supposed to not
-		 * have non e820 covered ISA mappings there, but I had some strange
-		 * problems so it stays for now.  -AK
-		 */
-		if (type == E820_RAM) {
-			if (start < 0x100000ULL && end > 0xA0000ULL) {
-				if (start < 0xA0000ULL)
-					add_memory_region(start, 0xA0000ULL-start, type);
-				if (end <= 0x100000ULL)
-					continue;
-				start = 0x100000ULL;
-				size = end - start;
-			}
-		}
-
 		add_memory_region(start, size, type);
 	} while (biosmap++,--nr_map);
 	return 0;



On 2/2/07, Andi Kleen <ak at suse.de> wrote:
> On Saturday 03 February 2007 01:17, Lu, Yinghai wrote:
> > Actually that is because of Andi's patch cause the problem.
>
> What patch?
>
> -Andi
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From lihao at mprc.pku.edu.cn  Sun Feb  4 06:21:27 2007
From: lihao at mprc.pku.edu.cn (lihao)
Date: Sun, 4 Feb 2007 13:21:27 +0800
Subject: [LinuxBIOS] UART questions on porting LinuxBIOS to GX2 + CS5535,
	help please!!
Message-ID: <200702041321212340125@mprc.pku.edu.cn>

Hi, all!
    I am doing porting jobs on GX2(GX-533 at 1.1w) + cs5535. I am using OLPC/rev_a directory as my starting point. I know that OLPC use GX2(GX-500 at 1.0w, right??) + cs5536. From POST card i see the code runs far behind the code of auto.c(src/mainboard/olpc/rev_a/auto.c), and there should be some information printed from uart1, actually there is none. 
    As for cs5536, i see cs5536_setup_onchipuart() called before uart_init(), and i find the MSRs handled in cs5536_setup_onchipuart do exist in cs5535. So i added a function named cs5535_setup_onchipuart in cs5535_early_setup.c, and call that functions in auto.c. The same result, nothing printed from uart1.
    I googled related information, i found someone said we must first loaded VSA before we can use internal uart of cs5535. I have a little bit understanding on VSA. From my point of view, i see VSA is an auto tools for OS to access standard x86 compatible registers and ios from not fully x86 compatible system like cs5535. And i think cs5535_setup_onchipuart handles accessing msr in cs5535 manually as what VSA should do and we do not need to firstly load VSA at auto.c. If I were right, why nothing appears from uart??
    Any advice would be well appreciated.




Regards
lihao
2007-02-04
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From lihao at mprc.pku.edu.cn  Sun Feb  4 07:53:37 2007
From: lihao at mprc.pku.edu.cn (lihao)
Date: Sun, 4 Feb 2007 14:53:37 +0800
Subject: [LinuxBIOS] UART questions on porting LinuxBIOS to GX2 + CS5535,
	help please!!
Message-ID: <200702041453330468376@mprc.pku.edu.cn>

Hi, all!
    I am doing porting jobs on GX2(GX-533 at 1.1w) + cs5535. I am using OLPC/rev_a directory as my starting point. 
I know that OLPC use GX2(GX-500 at 1.0w, right??) + cs5536. From POST card i see the code runs far behind the code 
of auto.c(src/mainboard/olpc/rev_a/auto.c), and there should be some information printed from uart1, actually there is 
none. 
    As for cs5536, i see cs5536_setup_onchipuart() called before uart_init(), and i find the MSRs handled in 
cs5536_setup_onchipuart do exist in cs5535. So i added a function named cs5535_setup_onchipuart in 
cs5535_early_setup.c, and call that functions in auto.c. The same result, nothing printed from uart1.
    I googled related information, i found someone said we must first loaded VSA before we can use internal uart of 
cs5535. I have a little bit understanding on VSA. From my point of view, i see VSA is an auto tools for OS to access 
standard x86 compatible registers and ios from not fully x86 compatible system like cs5535. And i think 
cs5535_setup_onchipuart handles accessing msr in cs5535 manually as what VSA should do and we do not need to 
firstly load VSA at auto.c. If I were right, why nothing appears from uart??
    Any advice would be well appreciated.




Regards
lihao
2007-02-04
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From ak at suse.de  Sun Feb  4 09:46:15 2007
From: ak at suse.de (Andi Kleen)
Date: Sun, 4 Feb 2007 09:46:15 +0100
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <2ea3fae10702031839h4c939910yeb40327f0f56e5f2@mail.gmail.com>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	<200702030609.18318.ak@suse.de>
	<2ea3fae10702031839h4c939910yeb40327f0f56e5f2@mail.gmail.com>
Message-ID: <200702040946.15872.ak@suse.de>

On Sunday 04 February 2007 03:39, yhlu wrote:
> commit dbf9272e863bf4b17ee8e3c66c26682b2061d40d
> Author: Andi Kleen <ak at suse.de>
> Date:   Tue Sep 26 10:52:36 2006 +0200
> 
>     [PATCH] Don't force reserve the 640k-1MB range

Ok, but if that breaks LinuxBios then the problem is clearly in LinuxBIOS
and needs to be fixed there.

-Andi



From stefan.reinauer at coresystems.de  Sun Feb  4 11:45:12 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sun, 04 Feb 2007 11:45:12 +0100
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <200702040946.15872.ak@suse.de>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>	<200702030609.18318.ak@suse.de>	<2ea3fae10702031839h4c939910yeb40327f0f56e5f2@mail.gmail.com>
	<200702040946.15872.ak@suse.de>
Message-ID: <45C5B938.1050209@coresystems.de>

Andi Kleen wrote:
> On Sunday 04 February 2007 03:39, yhlu wrote:
>> commit dbf9272e863bf4b17ee8e3c66c26682b2061d40d
>> Author: Andi Kleen <ak at suse.de>
>> Date:   Tue Sep 26 10:52:36 2006 +0200
>>
>>     [PATCH] Don't force reserve the 640k-1MB range
> 
> Ok, but if that breaks LinuxBios then the problem is clearly in LinuxBIOS
> and needs to be fixed there.

Why? Is LinuxBIOS breaking some standard here?


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stefan.reinauer at coresystems.de  Sun Feb  4 13:04:31 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sun, 04 Feb 2007 13:04:31 +0100
Subject: [LinuxBIOS] UART questions on porting LinuxBIOS to GX2 + CS5535,
 help please!!
In-Reply-To: <200702041321212340125@mprc.pku.edu.cn>
References: <200702041321212340125@mprc.pku.edu.cn>
Message-ID: <45C5CBCF.9070103@coresystems.de>

lihao wrote:
>     I googled related information, i found someone said we must first
> loaded VSA before we can use internal uart of cs5535. 

This sounds nasty. Are you sure you dont have another SuperIO on board
that has the serial port connected to it?

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Sun Feb  4 15:43:45 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 4 Feb 2007 15:43:45 +0100
Subject: [LinuxBIOS] Autoconf + Automake for flashrom?
Message-ID: <20070204144345.GA6437@greenwood>

Hi,

would anybody want to migrate flashrom to Autoconf+Automake or do you
have any objections?

On the one hand it might be a bit overkill, but on the other hand we
could improve/ease portability quite a bit, I guess. It also
"streamlines" the build process to what people are used to:

  ./configure && make && make install

I can provide patche? if we agree to do it. Opinions?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Sun Feb  4 16:06:21 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 4 Feb 2007 16:06:21 +0100
Subject: [LinuxBIOS] Autoconf + Automake for flashrom?
In-Reply-To: <20070204144345.GA6437@greenwood>
References: <20070204144345.GA6437@greenwood>
Message-ID: <20070204150620.GA14108@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070204 15:43]:
> Hi,
> 
> would anybody want to migrate flashrom to Autoconf+Automake or do you
> have any objections?

It works without. Why would you want to add that much maintenance
overhead?

> On the one hand it might be a bit overkill, but on the other hand we
> could improve/ease portability quite a bit, I guess. It also
> "streamlines" the build process to what people are used to:
 
Portability? What issues in particular? 




-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From pille at struction.de  Sun Feb  4 17:19:39 2007
From: pille at struction.de (pille)
Date: Sun, 04 Feb 2007 17:19:39 +0100
Subject: [LinuxBIOS] hardware info
Message-ID: <45C6079B.20302@struction.de>

hi,

at 23c3 you said that you'll need hardware information.
i didn't found anything in the wiki, but what information do you like
a simple lspci, or more?

cheers
   pille



From corey_osgood at verizon.net  Sun Feb  4 18:19:05 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Sun, 04 Feb 2007 12:19:05 -0500
Subject: [LinuxBIOS] hardware info
In-Reply-To: <45C6079B.20302@struction.de>
References: <45C6079B.20302@struction.de>
Message-ID: <45C61589.9030109@verizon.net>

pille wrote:
> hi,
> 
> at 23c3 you said that you'll need hardware information.
> i didn't found anything in the wiki, but what information do you like
> a simple lspci, or more?
> 
> cheers
>    pille
> 

lspci -v should do



From corey_osgood at verizon.net  Sun Feb  4 18:31:07 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Sun, 04 Feb 2007 12:31:07 -0500
Subject: [LinuxBIOS] iWill KA266 m/b
In-Reply-To: <1170484953.13276.1172697859@webmail.messagingengine.com>
References: <1170484953.13276.1172697859@webmail.messagingengine.com>
Message-ID: <45C6185B.6080502@verizon.net>

iwill-KA266 at mytrashmail.com wrote:
> Please advise on suitability for the latest LinuxBIOS.  The current BIOS
> says net boot is possible, would like to use in LinuxBIOS.  (Yes two
> sound devices, m/b plus a PCI card.)
> 
> Thanks - very nice work you do
> 
> 
> iWill KA266 motherboard (ATX) (*not* KA266-R variant)
> CPU = AMD Athlon 1333 MHz Socket 462
> North Bridge = ALi M1647
> South Bridge = ALi 1535D+
<snip>

LinuxBIOS doesn't currently support any ALi chipsets, most likely due to
the lack of documentation from the manufacturer.

-Corey



From pille at struction.de  Sun Feb  4 18:31:46 2007
From: pille at struction.de (pille)
Date: Sun, 04 Feb 2007 18:31:46 +0100
Subject: [LinuxBIOS] hardware info
In-Reply-To: <45C61589.9030109@verizon.net>
References: <45C6079B.20302@struction.de> <45C61589.9030109@verizon.net>
Message-ID: <45C61882.9060504@struction.de>

> lspci -v should do

ok, so here it is for a ThinkPad T43 Modell 266874G

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From ak at suse.de  Sun Feb  4 18:37:17 2007
From: ak at suse.de (Andi Kleen)
Date: Sun, 4 Feb 2007 18:37:17 +0100
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <45C5B938.1050209@coresystems.de>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	<200702040946.15872.ak@suse.de> <45C5B938.1050209@coresystems.de>
Message-ID: <200702041837.18127.ak@suse.de>

On Sunday 04 February 2007 11:45, Stefan Reinauer wrote:
> Andi Kleen wrote:
> > On Sunday 04 February 2007 03:39, yhlu wrote:
> >> commit dbf9272e863bf4b17ee8e3c66c26682b2061d40d
> >> Author: Andi Kleen <ak at suse.de>
> >> Date:   Tue Sep 26 10:52:36 2006 +0200
> >>
> >>     [PATCH] Don't force reserve the 640k-1MB range
> > 
> > Ok, but if that breaks LinuxBios then the problem is clearly in LinuxBIOS
> > and needs to be fixed there.
> 
> Why? Is LinuxBIOS breaking some standard here?

If anything between 640K and 1MB isn't memory it should report
that properly in the e820 map.

-Andi




From c-d.hailfinger.devel.2006 at gmx.net  Sun Feb  4 18:41:05 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 04 Feb 2007 18:41:05 +0100
Subject: [LinuxBIOS] Autoconf + Automake for flashrom?
In-Reply-To: <20070204144345.GA6437@greenwood>
References: <20070204144345.GA6437@greenwood>
Message-ID: <45C61AB1.5040705@gmx.net>

Uwe Hermann wrote:
> would anybody want to migrate flashrom to Autoconf+Automake or do you
> have any objections?

Please don't. Autotools introduce major portability problems. Building
software which was autotoolized on another arch or autoconf/automake
version will usually result in compile failures. I had to deal with
that stuff often enough to see that it usually makes things worse.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From c-d.hailfinger.devel.2006 at gmx.net  Sun Feb  4 18:43:14 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 04 Feb 2007 18:43:14 +0100
Subject: [LinuxBIOS] hardware info
In-Reply-To: <45C61882.9060504@struction.de>
References: <45C6079B.20302@struction.de> <45C61589.9030109@verizon.net>
	<45C61882.9060504@struction.de>
Message-ID: <45C61B32.20801@gmx.net>

pille wrote:
>> lspci -v should do
> 
> ok, so here it is for a ThinkPad T43 Modell 266874G

Sorry, laptops usually have embedded controllers for which no
datasheets are available. Besides that, IIRC your chipset is
not supported due to lack of docs (Intel might give you docs
if you can present a reasonable business case).

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From rminnich at gmail.com  Sun Feb  4 18:53:42 2007
From: rminnich at gmail.com (ron minnich)
Date: Sun, 4 Feb 2007 10:53:42 -0700
Subject: [LinuxBIOS] Autoconf + Automake for flashrom?
In-Reply-To: <45C61AB1.5040705@gmx.net>
References: <20070204144345.GA6437@greenwood> <45C61AB1.5040705@gmx.net>
Message-ID: <13426df10702040953m7c5e12c3n37270980e93355fa@mail.gmail.com>

I would not like to see the autoconf/automake/etc. stuff invade our
tree. Plus, it has been shown, it's not needed. The plan9ports code
(swtch.com/plan9ports) is quite portable and uses none of
autoconf/autotools.

If we need autoconf, it can indicate that our code is put together
wrong. Let's fix our code, if we have to.

thanks

ron



From rminnich at gmail.com  Sun Feb  4 19:03:14 2007
From: rminnich at gmail.com (ron minnich)
Date: Sun, 4 Feb 2007 11:03:14 -0700
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <200702041837.18127.ak@suse.de>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	<200702040946.15872.ak@suse.de> <45C5B938.1050209@coresystems.de>
	<200702041837.18127.ak@suse.de>
Message-ID: <13426df10702041003u4eb218ew834bb7e61fad52ab@mail.gmail.com>

On 2/4/07, Andi Kleen <ak at suse.de> wrote:
> On Sunday 04 February 2007 11:45, Stefan Reinauer wrote:
> > Andi Kleen wrote:
> > > On Sunday 04 February 2007 03:39, yhlu wrote:
> > >> commit dbf9272e863bf4b17ee8e3c66c26682b2061d40d
> > >> Author: Andi Kleen <ak at suse.de>
> > >> Date:   Tue Sep 26 10:52:36 2006 +0200
> > >>
> > >>     [PATCH] Don't force reserve the 640k-1MB range
> > >
> > > Ok, but if that breaks LinuxBios then the problem is clearly in LinuxBIOS
> > > and needs to be fixed there.
> >
> > Why? Is LinuxBIOS breaking some standard here?
>
> If anything between 640K and 1MB isn't memory it should report
> that properly in the e820 map.
>
> -Andi

Andi, I just reread Roman's original note. I am re-attaching it. It
does seem to me that there is some problem in how linux is handling
the map. Or am I missing something here? We're happy to fix any
linuxbios issues, I just can't see any LinuxBIOS issues in the bug
Roman describes.


From ebiederm at xmission.com  Sun Feb  4 19:33:00 2007
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Sun, 04 Feb 2007 11:33:00 -0700
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <200702041837.18127.ak@suse.de> (Andi Kleen's message of "Sun, 4
	Feb 2007 18:37:17 +0100")
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	<200702040946.15872.ak@suse.de> <45C5B938.1050209@coresystems.de>
	<200702041837.18127.ak@suse.de>
Message-ID: <m17iuxzsbn.fsf@ebiederm.dsl.xmission.com>

Andi Kleen <ak at suse.de> writes:

> On Sunday 04 February 2007 11:45, Stefan Reinauer wrote:
>> Andi Kleen wrote:
>> > On Sunday 04 February 2007 03:39, yhlu wrote:
>> >> commit dbf9272e863bf4b17ee8e3c66c26682b2061d40d
>> >> Author: Andi Kleen <ak at suse.de>
>> >> Date:   Tue Sep 26 10:52:36 2006 +0200
>> >>
>> >>     [PATCH] Don't force reserve the 640k-1MB range
>> > 
>> > Ok, but if that breaks LinuxBios then the problem is clearly in LinuxBIOS
>> > and needs to be fixed there.
>> 
>> Why? Is LinuxBIOS breaking some standard here?
>
> If anything between 640K and 1MB isn't memory it should report
> that properly in the e820 map.

No the problem was that the patch was incomplete.  Linux is still
reserving a ROM at 0xf0000-0xfffff.  Now when LinuxBIOS properly
reports that area as RAM that you can do something with, Linux ignores
it, because of the ROM reservation is reserved first.  But worse 
the whole range is thrown out which in this case was:
    BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)


So basically none of the memory below 4G is reported in /proc/iomem.
Which is painful.

When /sbin/kexec goes to regenerate the e820 map since we have huge
holes in the e820 map the whole thing falls over.

Which means we want to either delete the System ROM reservation,
perform the System ROM reservation after other reservations from
the e820 map, or improve the error handling.

I believe the following trivial patch will resolve the issue
but reserving the ROMs later.

diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index af425a8..f9610b7 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -522,8 +522,8 @@ void __init setup_arch(char **cmdline_p)
         * Request address space for all standard RAM and ROM resources
         * and also for regions reported as reserved by the e820.
         */
-       probe_roms();
        e820_reserve_resources(); 
+       probe_roms();
        e820_mark_nosave_regions();
 
        request_resource(&iomem_resource, &video_ram_resource);




From uwe at hermann-uwe.de  Sun Feb  4 21:52:58 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 4 Feb 2007 21:52:58 +0100
Subject: [LinuxBIOS] iWill KA266 m/b
In-Reply-To: <45C6185B.6080502@verizon.net>
References: <1170484953.13276.1172697859@webmail.messagingengine.com>
	<45C6185B.6080502@verizon.net>
Message-ID: <20070204205258.GA29665@greenwood>

On Sun, Feb 04, 2007 at 12:31:07PM -0500, Corey Osgood wrote:
> iwill-KA266 at mytrashmail.com wrote:
> > Please advise on suitability for the latest LinuxBIOS.  The current BIOS
> > says net boot is possible, would like to use in LinuxBIOS.  (Yes two
> > sound devices, m/b plus a PCI card.)
> > 
> > Thanks - very nice work you do
> > 
> > 
> > iWill KA266 motherboard (ATX) (*not* KA266-R variant)
> > CPU = AMD Athlon 1333 MHz Socket 462
> > North Bridge = ALi M1647
> > South Bridge = ALi 1535D+
> <snip>
> 
> LinuxBIOS doesn't currently support any ALi chipsets, most likely due to
> the lack of documentation from the manufacturer.

Yep, I couldn't find a public datasheet for these. We _do_ have some
support for ALi/Acer chipsets in v1, though:

- m1631
- m1535
- m1543

I don't know whether or not the code actually works, though.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Sun Feb  4 22:02:39 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 4 Feb 2007 22:02:39 +0100
Subject: [LinuxBIOS] Autoconf + Automake for flashrom?
In-Reply-To: <20070204150620.GA14108@coresystems.de>
References: <20070204144345.GA6437@greenwood>
	<20070204150620.GA14108@coresystems.de>
Message-ID: <20070204210239.GB29665@greenwood>

On Sun, Feb 04, 2007 at 04:06:21PM +0100, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070204 15:43]:
> > Hi,
> > 
> > would anybody want to migrate flashrom to Autoconf+Automake or do you
> > have any objections?
> 
> It works without. Why would you want to add that much maintenance
> overhead?

Dunno, it was just an idea ;) It's not _that_ much overhead usually,
though.

For LinuxBIOS itself Autoconf is obviously not a good idea, but for
flashrom (a userland application) this can be considered, IMHO.


> > On the one hand it might be a bit overkill, but on the other hand we
> > could improve/ease portability quite a bit, I guess. It also
> > "streamlines" the build process to what people are used to:
>  
> Portability? What issues in particular?

For example the recent /dev/mem issue. The 'configure' script can check
for tons of stuff, compilers, paths, command line options for some
toolchain programs, header files, libraries (libpci, libz for flashrom),
and lots more.

Sure, all of that can be done with plain Makefiles and a bit of hacking,
but if we need _lots_ of such workarounds/checks Autoconf might be the
better option.
Think about porting flashrom to *BSD, Mac OS, etc. I'm pretty sure
more issues will arise over time.

But yeah, I was expecting resistance against this, lots of people seem
to dislike the Autotools ;) That's why I first asked before wasting time
preparing patches.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From Reece at theptrgroup.com  Mon Feb  5 00:49:59 2007
From: Reece at theptrgroup.com (Reece R. Pollack)
Date: Sun, 4 Feb 2007 18:49:59 -0500
Subject: [LinuxBIOS] Configuration tool manual truncated?
Message-ID: <200702041849.59995.Reece@theptrgroup.com>

I took a look at the configuration tool manual today, to better understand the 
various configuration mechanisms (I'm adding a couple of new mainboards, 
targets, and Super I/O chips). What I got was a 4-page postscript file that 
appears to be incomplete -- it ends in mid-sentence on page 4.

Is there a more complete version of this file somewhere, or other 
documentation of the configuration file format?

-- 
--------------------------------------------------------------
Reece R. Pollack                                  301.461.2653
Principal Engineer                       reece at ThePTRGroup.com
www.ThePTRGroup.com              Embedded, Real-Time Solutions
--------------------------------------------------------------



From corey_osgood at verizon.net  Mon Feb  5 09:53:42 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Mon, 05 Feb 2007 03:53:42 -0500
Subject: [LinuxBIOS] Add support for Via vt82c686a
In-Reply-To: <20070201110154.GA27621@greenwood>
References: <45AA9938.6020804@verizon.net> <20070114235739.GB20305@greenwood>
	<45AAE156.5030206@verizon.net>
	<366f3f5e6a46f27ea5e4a1edfac2d58c@kernel.crashing.org>
	<20070115175038.GA10359@greenwood> <45ABD34A.1040609@verizon.net>
	<45AC2889.1070307@comcast.net> <20070116061841.GA28012@greenwood>
	<45C19A92.2020802@verizon.net> <20070201110154.GA27621@greenwood>
Message-ID: <45C6F096.4070202@verizon.net>

Uwe Hermann wrote:
> Hi,
> 
> On Thu, Feb 01, 2007 at 02:45:22AM -0500, Corey Osgood wrote:
>> Please scratch the patch I submitted. vt82c686a and b are the same, the 
>> docs lied (and this is the first time I've looked at it on the machines, 
>> stupid me). I'm reworking a few things and cleaning up a few more 
>> things, and I'll submit a working, tested patch this weekend, if all 
>> goes well.
> 
> OK, great!

So, this weekend just happened to be both the super bowl and my 21st
birthday, so I didn't get as much as I'd hoped to done. What I did get
means that either my serial setup on the monitoring PC is messed up
(very possible) or else this quick hack from vt8231 isn't going to work,
and I need to go back and work from v1, which I can only assume to be
working. I make no more promises, it will be done when it's done (duke
nukem forever anyone?)

> 
>  
>> On a related note, does anyone know if any northbridge init is required 
>> to bring up the southbridge (and in this case also superio)? And is the 
>> rcn dc1100s from v1 working or not? I couldn't get it to run (no serial 
>> or video output at all) on the tyan s2507, which seems to be the same 
>> hardware.
> 
> I guess you need the northbridge (RAM init) for anything else to work.
> I have a K7T Turbo which has a VIA VT82C686B southbridge, but
> unfortunately the northbridge is a VIA Apollo KT133A (VT8363A) which
> is not supported, and I don't have VIA data sheets...
> 

The vt82c686b datasheet is here (I also found an older version on some
obscure page of via's site, but can't find it now):
http://www.datasheets.org.uk/search.php?q=VT82C686B&sType=part
As for the 8363a, rom.by has the datasheet for both it and my 694x (and
ALi chipsets!), but I can't be sure if they're, well, supposed to or
not, so I'm avoiding touching them.

-Corey



From corey_osgood at verizon.net  Mon Feb  5 10:05:44 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Mon, 05 Feb 2007 04:05:44 -0500
Subject: [LinuxBIOS] Configuration tool manual truncated?
In-Reply-To: <200702041849.59995.Reece@theptrgroup.com>
References: <200702041849.59995.Reece@theptrgroup.com>
Message-ID: <45C6F368.9030601@verizon.net>

Reece R. Pollack wrote:
> I took a look at the configuration tool manual today, to better understand the 
> various configuration mechanisms (I'm adding a couple of new mainboards, 
> targets, and Super I/O chips). What I got was a 4-page postscript file that 
> appears to be incomplete -- it ends in mid-sentence on page 4.
> 
> Is there a more complete version of this file somewhere, or other 
> documentation of the configuration file format?
> 

I've attached the full document, which was in the LinuxBIOSv1 svn
repositories. Just to warn you though, much of this is specific to v1
and has been changed in v2. There isn't much documentation at all for
LBv2, which is one of the things that really should be taken care of, IMO.

-Corey
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From rminnich at gmail.com  Mon Feb  5 15:33:49 2007
From: rminnich at gmail.com (ron minnich)
Date: Mon, 5 Feb 2007 07:33:49 -0700
Subject: [LinuxBIOS] Configuration tool manual truncated?
In-Reply-To: <45C6F368.9030601@verizon.net>
References: <200702041849.59995.Reece@theptrgroup.com>
	<45C6F368.9030601@verizon.net>
Message-ID: <13426df10702050633i65aaecd1je2528fd05b8604c4@mail.gmail.com>

On 2/5/07, Corey Osgood <corey_osgood at verizon.net> wrote:

> There isn't much documentation at all for
> LBv2, which is one of the things that really should be taken care of, IMO.

You're right. Poor docs have been a problem. We're going to have that for v3.

ron



From kononov195-lbl at yahoo.com  Mon Feb  5 17:23:33 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Mon, 05 Feb 2007 10:23:33 -0600
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <m17iuxzsbn.fsf@ebiederm.dsl.xmission.com>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>	<200702040946.15872.ak@suse.de>
	<45C5B938.1050209@coresystems.de>	<200702041837.18127.ak@suse.de>
	<m17iuxzsbn.fsf@ebiederm.dsl.xmission.com>
Message-ID: <45C75A05.9040401@yahoo.com>

On 02/04/2007 12:33 PM, Eric W. Biederman wrote:
> Which means we want to either delete the System ROM reservation,
> perform the System ROM reservation after other reservations from
> the e820 map, or improve the error handling.

What is the point in making reservation of a ROM which does not
exist at all at its legacy physical location? It is disinformation.
I would not reserve any ROM (system, video, etc.) when there is no
ROM. The c0000-f0000 range is also wrongly converted from RAM to
ROM by the kernel.



From kononov195-lbl at yahoo.com  Mon Feb  5 17:44:54 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Mon, 05 Feb 2007 10:44:54 -0600
Subject: [LinuxBIOS] [PATCH] VGA is used before it is initialized
In-Reply-To: <45C4B016.2080601@coresystems.de>
References: <45AEB79A.6040308@yahoo.com>	<45C0DF72.3040800@yahoo.com>	<45C0E48A.4060603@coresystems.de>	<45C0EFC6.3050007@yahoo.com>	<45C0F371.7000602@coresystems.de>	<45C127B9.4070603@yahoo.com>	<20070131235327.12140.qmail@cdy.org>
	<45C134C2.1050802@yahoo.com> <45C4B016.2080601@coresystems.de>
Message-ID: <45C75F06.1030709@yahoo.com>

When CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1
VGA will not be initialized because of pci_rom_load()

What about vgainit-v3?

Roman


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From yinghai.lu at amd.com  Mon Feb  5 18:09:57 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Mon, 5 Feb 2007 09:09:57 -0800
Subject: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O
Message-ID: <5986589C150B2F49A46483AC44C7BCA4907411@ssvlexmb2.amd.com>

USB DEBUG port support.

YH

-----Original Message-----
From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On Behalf Of Stefan Reinauer
Sent: Saturday, February 03, 2007 7:31 AM
To: Uwe Hermann
Cc: linuxbios at linuxbios.org
Subject: Re: [LinuxBIOS] [PATCH] Support for Winbond W83627EHG Super I/O

Uwe Hermann wrote:
> Add support for the Winbond W83627EHG Super I/O.
> 
> Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

applied.

> This is from Yinghai's huge patch. I added missing license headers
> (Yinghai please complain if any of them is incorrect!), fixed some
> coding style issues and added a few comments.

What's still missing from Yinghai's patch now?



-- 
coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 * Fax: +49 761 7664613
Email: info at coresystems.de  * http://www.coresystems.de/

-- 
linuxbios mailing list
linuxbios at linuxbios.org
http://www.openbios.org/mailman/listinfo/linuxbios





From ebiederm at xmission.com  Mon Feb  5 18:28:07 2007
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Mon, 05 Feb 2007 10:28:07 -0700
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <45C75A05.9040401@yahoo.com> (Roman Kononov's message of "Mon, 05
	Feb 2007 10:23:33 -0600")
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	<200702040946.15872.ak@suse.de> <45C5B938.1050209@coresystems.de>
	<200702041837.18127.ak@suse.de>
	<m17iuxzsbn.fsf@ebiederm.dsl.xmission.com>
	<45C75A05.9040401@yahoo.com>
Message-ID: <m1abzsy0ns.fsf@ebiederm.dsl.xmission.com>

Roman Kononov <kononov195-lbl at yahoo.com> writes:

> On 02/04/2007 12:33 PM, Eric W. Biederman wrote:
>> Which means we want to either delete the System ROM reservation,
>> perform the System ROM reservation after other reservations from
>> the e820 map, or improve the error handling.
>
> What is the point in making reservation of a ROM which does not
> exist at all at its legacy physical location? It is disinformation.
> I would not reserve any ROM (system, video, etc.) when there is no
> ROM. The c0000-f0000 range is also wrongly converted from RAM to
> ROM by the kernel.


From lihao at mprc.pku.edu.cn  Mon Feb  5 20:12:47 2007
From: lihao at mprc.pku.edu.cn (lihao)
Date: Tue, 6 Feb 2007 03:12:47 +0800
Subject: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
Message-ID: <000001c74959$a1f69fc0$07c8a8c0@dionysus>

Hi all,

         I am running LinuxBIOS on gx2 and cs5535 platform. Now the code
begins to enumerate devices in northbridge. 

And the code hangs just after prints out _do_vsmbios_. 

         I find the next function called close to that print is
_unrv2b((uint8 *)rom, buffer, &ileg)_, and it seems that cpu is in dead
loop.

I am thinking that maybe my linuxbios image is not correctly built. The step
I build image is divided into 2:

         Firstly, I build out a _linuxbios.rom_ image;

         Secondly, I use _buildrom_ tool from util directory to build
vsa2.bin and linuxbios.rom together out as the final image.

         My flash is 512KB, so I put vsa2.bin at 0xfff80000, and
linuxbios.rom at another side of flash.

         Is my step correct??

 

         By the way, after I built out vsa image, it generates some other
images, which one should I choose? Including: vsa2.bin, olpcXXX.bin, some
vsms and so on..

 

         Any advice would be well appreciated.

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From talbotx at comcast.net  Mon Feb  5 21:40:23 2007
From: talbotx at comcast.net (Adam Talbot)
Date: Mon, 05 Feb 2007 12:40:23 -0800
Subject: [LinuxBIOS] Console for an embedded system, Hex inverter needed
In-Reply-To: <000001c74959$a1f69fc0$07c8a8c0@dionysus>
References: <000001c74959$a1f69fc0$07c8a8c0@dionysus>
Message-ID: <45C79637.4050708@comcast.net>

I have an embedded system with serial console, but its inverted.  I 
would normally use a hardware hex inverter chip, but currently dont have 
any sitting around.  Is there a way in linux/minicom to do hex inverting 
on the fly?  Or to capture and then convert?
-Adam Talbot



From stuge-linuxbios at cdy.org  Mon Feb  5 23:36:26 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Mon, 5 Feb 2007 23:36:26 +0100
Subject: [LinuxBIOS] Console for an embedded system, Hex inverter needed
In-Reply-To: <45C79637.4050708@comcast.net>
References: <000001c74959$a1f69fc0$07c8a8c0@dionysus>
	<45C79637.4050708@comcast.net>
Message-ID: <20070205223626.13321.qmail@cdy.org>

On Mon, Feb 05, 2007 at 12:40:23PM -0800, Adam Talbot wrote:
> I have an embedded system with serial console, but its inverted.  I 
> would normally use a hardware hex inverter chip, but currently dont
> have any sitting around.  Is there a way in linux/minicom to do hex
> inverting on the fly?  Or to capture and then convert?

minicom can capture.

Create a fifo on disk (mkfifo) have a software inverter read from it
and write to wherever, then use Alt-L or Ctrl-A L to activate
capturing in minicom. Use the fifo as capture file.


//Peter



From lihao at mprc.pku.edu.cn  Mon Feb  5 23:37:18 2007
From: lihao at mprc.pku.edu.cn (lihao)
Date: Tue, 6 Feb 2007 06:37:18 +0800
Subject: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
Message-ID: <000001c74976$3407e650$07c8a8c0@dionysus>

Hi all,

         I have made the codes run into the vsmbios. And it hangs on
pci_sanity_check(). Anyone has the same problems?

I have 2 questions:

1)      I have downloaded VSA code, and VSA implements a softVG, do I need
to make a VGABIOS myself from linux?

2)      If I need a VGABIOS, where should I put it in the image??

 

         Thanks, any advice would be well appreciated.

 

  _____  

???: lihao [mailto:lihao at mprc.pku.edu.cn] 
????: 2007?2?6? 3:13
???: 'linuxbios at linuxbios.org'
??: questions about VSA on Gx2 plus cs5535??

 

Hi all,

         I am running LinuxBIOS on gx2 and cs5535 platform. Now the code
begins to enumerate devices in northbridge. 

And the code hangs just after prints out _do_vsmbios_. 

         I find the next function called close to that print is
_unrv2b((uint8 *)rom, buffer, &ileg)_, and it seems that cpu is in dead
loop.

I am thinking that maybe my linuxbios image is not correctly built. The step
I build image is divided into 2:

         Firstly, I build out a _linuxbios.rom_ image;

         Secondly, I use _buildrom_ tool from util directory to build
vsa2.bin and linuxbios.rom together out as the final image.

         My flash is 512KB, so I put vsa2.bin at 0xfff80000, and
linuxbios.rom at another side of flash.

         Is my step correct??

 

         By the way, after I built out vsa image, it generates some other
images, which one should I choose? Including: vsa2.bin, olpcXXX.bin, some
vsms and so on?.

 

         Any advice would be well appreciated.

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From rminnich at gmail.com  Mon Feb  5 23:54:42 2007
From: rminnich at gmail.com (ron minnich)
Date: Mon, 5 Feb 2007 15:54:42 -0700
Subject: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
In-Reply-To: <000001c74976$3407e650$07c8a8c0@dionysus>
References: <000001c74976$3407e650$07c8a8c0@dionysus>
Message-ID: <13426df10702051454r8b5128fjec6a9c42927eefba@mail.gmail.com>

On 2/5/07, lihao <lihao at mprc.pku.edu.cn> wrote:
>
>
>
>
> Hi all,
>
>          I have made the codes run into the vsmbios. And it hangs on
> pci_sanity_check(). Anyone has the same problems?
>
> I have 2 questions:
>
> 1)      I have downloaded VSA code, and VSA implements a softVG, do I need
> to make a VGABIOS myself from linux?

yes.

On the systems we have done, we have first VSA, then VGA BIOS, then
linuxbios payload, then linuxbios.

I strongly recommend you build BIOS images with  the buildrom tool
from OLPC.  What size flash do you have? If it is < 1 MB, you want to
load either Open Firmware or FILO. FILO will likely be less work for
you.

thanks

ron



From indrek.kruusa at artecdesign.ee  Tue Feb  6 16:15:00 2007
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Tue, 6 Feb 2007 17:15:00 +0200
Subject: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
In-Reply-To: <000001c74976$3407e650$07c8a8c0@dionysus>
References: <000001c74976$3407e650$07c8a8c0@dionysus>
Message-ID: <200702061715.00182.indrek.kruusa@artecdesign.ee>

?hel kenal p?eval (teisip?ev 06 veebruar 2007 12:37 am) kirjutas lihao:
> Hi all,
>
>          I have made the codes run into the vsmbios. And it hangs on
> pci_sanity_check(). Anyone has the same problems?


Can you check that the signature of the loaded VSA is correct (e.g. by 
printing it out)?
Do you have VSA nrv2b compressed or not?


cheers,
Indrek



>
> I have 2 questions:
>
> 1)      I have downloaded VSA code, and VSA implements a softVG, do I need
> to make a VGABIOS myself from linux?
>
> 2)      If I need a VGABIOS, where should I put it in the image??
>
>
>
>          Thanks, any advice would be well appreciated.
>
>
>
>   _____
>
> ???: lihao [mailto:lihao at mprc.pku.edu.cn]
> ????: 2007?2?6? 3:13
> ???: 'linuxbios at linuxbios.org'
> ??: questions about VSA on Gx2 plus cs5535??
>
>
>
> Hi all,
>
>          I am running LinuxBIOS on gx2 and cs5535 platform. Now the code
> begins to enumerate devices in northbridge.
>
> And the code hangs just after prints out _do_vsmbios_.
>
>          I find the next function called close to that print is
> _unrv2b((uint8 *)rom, buffer, &ileg)_, and it seems that cpu is in dead
> loop.
>
> I am thinking that maybe my linuxbios image is not correctly built. The
> step I build image is divided into 2:
>
>          Firstly, I build out a _linuxbios.rom_ image;
>
>          Secondly, I use _buildrom_ tool from util directory to build
> vsa2.bin and linuxbios.rom together out as the final image.
>
>          My flash is 512KB, so I put vsa2.bin at 0xfff80000, and
> linuxbios.rom at another side of flash.
>
>          Is my step correct??
>
>
>
>          By the way, after I built out vsa image, it generates some other
> images, which one should I choose? Including: vsa2.bin, olpcXXX.bin, some
> vsms and so on?.
>
>
>
>          Any advice would be well appreciated.



From ak at suse.de  Tue Feb  6 17:46:31 2007
From: ak at suse.de (Andi Kleen)
Date: Tue, 6 Feb 2007 17:46:31 +0100
Subject: [LinuxBIOS] [PATCH] e820 table correction
In-Reply-To: <45C75A05.9040401@yahoo.com>
References: <5986589C150B2F49A46483AC44C7BCA490740B@ssvlexmb2.amd.com>
	<m17iuxzsbn.fsf@ebiederm.dsl.xmission.com>
	<45C75A05.9040401@yahoo.com>
Message-ID: <200702061746.31458.ak@suse.de>

On Monday 05 February 2007 17:23, Roman Kononov wrote:
> On 02/04/2007 12:33 PM, Eric W. Biederman wrote:
> > Which means we want to either delete the System ROM reservation,
> > perform the System ROM reservation after other reservations from
> > the e820 map, or improve the error handling.
> 
> What is the point in making reservation of a ROM which does not
> exist at all at its legacy physical location? It is disinformation.
> I would not reserve any ROM (system, video, etc.) when there is no
> ROM. The c0000-f0000 range is also wrongly converted from RAM to
> ROM by the kernel.

Yes I'm tempted to just remove all the rom probing code too together
with the sysrom because it shouldn't be needed.

-Andi




From svn at openbios.org  Tue Feb  6 20:47:50 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue,  6 Feb 2007 20:47:50 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
Message-ID: <mailman.169.1355071058.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-06 20:47:50 +0100 (Tue, 06 Feb 2007)
New Revision: 2550

Modified:
   trunk/LinuxBIOSv2/util/flashrom/82802ab.c
   trunk/LinuxBIOSv2/util/flashrom/Makefile
   trunk/LinuxBIOSv2/util/flashrom/flash.h
   trunk/LinuxBIOSv2/util/flashrom/flash_enable.c
   trunk/LinuxBIOSv2/util/flashrom/flash_rom.c
   trunk/LinuxBIOSv2/util/flashrom/lbtable.c
   trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c
   trunk/LinuxBIOSv2/util/flashrom/sst49lfxxxc.c
   trunk/LinuxBIOSv2/util/flashrom/sst_fwhub.c
Log:
This patch is a rework of Adam Kaufman's Solaris patch.

* flash.h:
  - add a license header
  - add system definitions
* flash_enable.c:
  - put io priviledge access in one single place
  - add includes required for Solaris.
* lbtable.c, flash_rom.c, 82802ab.c:
  - use MEM_DEV so it works on Solaris
* sst49lfxxxc.c, sharplhf00l04.c, sst_fwhub.c, 82802ab.c
  - drop unneeded include to sys/io.h
* Makefile
  - adapt to Solaris specifics.

Signed-off-by: Adam Kaufman <adam.kaufman at pinnacle.com>
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Adam Kaufman <adam.kaufman at pinnacle.com>



Modified: trunk/LinuxBIOSv2/util/flashrom/82802ab.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/82802ab.c	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/82802ab.c	2007-02-06 19:47:50 UTC (rev 2550)
@@ -26,7 +26,6 @@
 #include <errno.h>
 #include <fcntl.h>
 #include <sys/mman.h>
-#include <sys/io.h>
 #include <unistd.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -83,7 +82,7 @@
 			    flash->fd_mem, (off_t) (0 - 0x400000 - size));
 		if (bios == MAP_FAILED) {
 			// it's this part but we can't map it ...
-			perror("Error MMAP /dev/mem");
+			perror("Error MMAP memory using " MEM_DEV );
 			exit(1);
 		}
 

Modified: trunk/LinuxBIOSv2/util/flashrom/Makefile
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/Makefile	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/Makefile	2007-02-06 19:47:50 UTC (rev 2550)
@@ -12,9 +12,14 @@
 PREFIX  = /usr/local
 #CFLAGS  = -O2 -g -Wall -Werror
 CFLAGS  = -Os -Wall -Werror -DDISABLE_DOC # -DTS5300
+OS_ARCH	= $(shell uname)
+ifeq ($(OS_ARCH), SunOS)
+LDFLAGS = -lpci -lz
+else
 LDFLAGS = -lpci -lz -static 
+STRIP_ARGS = -s
+endif
 
-
 OBJS  = flash_enable.o udelay.o jedec.o sst28sf040.o am29f040b.o mx29f002.o  \
 	sst39sf020.o m29f400bt.o w49f002u.o 82802ab.o msys_doc.o pm49fl004.o \
 	sst49lf040.o sst49lfxxxc.o sst_fwhub.o layout.o lbtable.o \
@@ -24,7 +29,7 @@
 
 $(PROGRAM): $(OBJS)
 	$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
-	$(STRIP) -s $(PROGRAM)
+	$(STRIP) $(STRIP_ARGS) $(PROGRAM)
 
 clean:
 	rm -f *.o *~

Modified: trunk/LinuxBIOSv2/util/flashrom/flash.h
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/flash.h	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/flash.h	2007-02-06 19:47:50 UTC (rev 2550)
@@ -1,7 +1,34 @@
+/*
+ * flash.h: flash programming utility - central include file
+ *
+ * Copyright 2000 Silicon Integrated System Corporation
+ * Copyright 2000 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright 2005 coresystems GmbH <stepan at coresystems.de>
+ * 
+ *	This program is free software; you can redistribute it and/or modify
+ *	it under the terms of the GNU General Public License as published by
+ *	the Free Software Foundation; either version 2 of the License, or
+ *	(at your option) any later version.
+ *
+ *	This program is distributed in the hope that it will be useful,
+ *	but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *	GNU General Public License for more details.
+ *
+ *	You should have received a copy of the GNU General Public License
+ *	along with this program; if not, write to the Free Software
+ *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+
 #ifndef __FLASH_H__
 #define __FLASH_H__ 1
 
+#if defined(__GLIBC__)
 #include <sys/io.h>
+#endif
+
 #include <unistd.h>
 #include <stdint.h>
 
@@ -92,7 +119,18 @@
 #define S29C51004T	  0x03  /* SyncMOS S29C51004T/B */
 #define S29C31004T	  0x63  /* SyncMOS S29C31004T */
 
+/* function prototypes from udelay.h */
+
 extern void myusec_delay(int time);
 extern void myusec_calibrate_delay();
 extern int enable_flash_write(void);
+
+/* physical memory mapping device */
+
+#if defined (__sun) && (defined(__i386) || defined(__amd64))
+#  define MEM_DEV "/dev/xsvc"
+#else
+#  define MEM_DEV "/dev/mem"
+#endif
+
 #endif				/* !__FLASH_H__ */

Modified: trunk/LinuxBIOSv2/util/flashrom/flash_enable.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/flash_enable.c	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/flash_enable.c	2007-02-06 19:47:50 UTC (rev 2550)
@@ -11,12 +11,18 @@
  *
  */
 
-#include <sys/io.h>
 #include <stdio.h>
 #include <pci/pci.h>
 #include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
+#if defined (__sun) && (defined(__i386) || defined(__amd64))
+#include <strings.h>
+#include <sys/sysi86.h>
+#include <sys/psw.h>
+#include <asm/sunddi.h>
+#endif
+#include "flash.h"
 #include "lbtable.h"
 #include "debug.h"
 
@@ -27,12 +33,6 @@
 {
 	char b;
 
-	/* get io privilege access PCI configuration space */
-	if (iopl(3) != 0) {
-		perror("Can not set io priviliage");
-		exit(1);
-	}
-
 	/* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
 	outl(0x80000840, 0x0cf8);
 	b = inb(0x0cfc) | 0x0b;
@@ -164,12 +164,6 @@
 	unsigned int base;
 	int ok;
 
-	/* get io privilege access PCI configuration space */
-	if (iopl(3) != 0) {
-		perror("Can not set io priviliage");
-		exit(1);
-	}
-
 	old = pci_read_byte(dev, 0x40);
 
 	new = old | 0x10;
@@ -347,12 +341,6 @@
 	struct pci_filter f;
 	struct pci_dev *smbusdev;
 
-	/* get io privilege access */
-	if (iopl(3) != 0) {
-		perror("Can not set io priviliage");
-		exit(1);
-	}
-
 	/* then look for the smbus device */
 	pci_filter_init((struct pci_access *) 0, &f);
 	f.vendor = 0x1002;
@@ -491,12 +479,6 @@
  *  connected to the WinBond w83627hf GPIO 24.
  */
 
-	/* get io privilege access winbond config space */
-	if (iopl(3) != 0) {
-		perror("Can not set io priviliage");
-		exit(1);
-	}
-	
 	printf("Disabling mainboard flash write protection.\n");
 
 	outb(0x87, EFIR); // sequence to unlock extended functions
@@ -552,6 +534,18 @@
 	struct pci_dev *dev = 0;
 	FLASH_ENABLE *enable = 0;
 
+	/* get io privilege access PCI configuration space */
+#if defined (__sun) && (defined(__i386) || defined(__amd64))
+	if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0){
+#else
+	if (iopl(3) != 0) {
+#endif
+		perror("Can not set io privilege");
+		exit(1);
+	}
+
+
+	/* Initialize PCI access */
 	pacc = pci_alloc();	/* Get the pci_access structure */
 	/* Set all options you want -- here we stick with the defaults */
 	pci_init(pacc);		/* Initialize the PCI library */

Modified: trunk/LinuxBIOSv2/util/flashrom/flash_rom.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/flash_rom.c	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/flash_rom.c	2007-02-06 19:47:50 UTC (rev 2550)
@@ -52,8 +52,8 @@
 	volatile uint8_t *bios;
 	unsigned long size;
 
-	if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
-		perror("Error: Can not open /dev/mem. You need to be root.");
+	if ((fd_mem = open(MEM_DEV, O_RDWR)) < 0) {
+		perror("Error: Can not access memory using " MEM_DEV ". You need to be root.");
 		exit(1);
 	}
 

Modified: trunk/LinuxBIOSv2/util/flashrom/lbtable.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/lbtable.c	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/lbtable.c	2007-02-06 19:47:50 UTC (rev 2550)
@@ -7,6 +7,7 @@
 #include <string.h>
 #include <errno.h>
 #include <sys/mman.h>
+#include "flash.h"
 #include "../../src/include/boot/linuxbios_tables.h"
 #include "debug.h"
 
@@ -158,14 +159,14 @@
 	struct lb_record *rec, *last;
 	
 	int fd;
-	fd = open("/dev/mem", O_RDONLY);
+	fd = open(MEM_DEV, O_RDONLY);
 	if (fd < 0) {
-		fprintf(stderr, "Can not open /dev/mem\n");
+		fprintf(stderr, "Can not access memory using " MEM_DEV "\n");
 		exit(-1);
 	}
 	low_1MB = mmap(0, 1024*1024, PROT_READ, MAP_SHARED, fd, 0x00000000);
 	if (low_1MB == ((void *) -1)) {
-		fprintf(stderr, "Can not mmap /dev/mem at %08lx errno(%d):%s\n",
+		fprintf(stderr, "Can not mmap " MEM_DEV " at %08lx errno(%d):%s\n",
 			0x00000000UL, errno, strerror(errno));
 		exit(-2);
 	}

Modified: trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/sharplhf00l04.c	2007-02-06 19:47:50 UTC (rev 2550)
@@ -25,7 +25,6 @@
 #include <errno.h>
 #include <fcntl.h>
 #include <sys/mman.h>
-#include <sys/io.h>
 #include <unistd.h>
 #include <stdio.h>
 #include <stdlib.h>

Modified: trunk/LinuxBIOSv2/util/flashrom/sst49lfxxxc.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/sst49lfxxxc.c	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/sst49lfxxxc.c	2007-02-06 19:47:50 UTC (rev 2550)
@@ -28,11 +28,11 @@
 #include <errno.h>
 #include <fcntl.h>
 #include <sys/mman.h>
-#include <sys/io.h>
 #include <unistd.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdint.h>
+
 #include "flash.h"
 #include "jedec.h"
 #include "debug.h"

Modified: trunk/LinuxBIOSv2/util/flashrom/sst_fwhub.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/sst_fwhub.c	2007-02-03 15:28:20 UTC (rev 2549)
+++ trunk/LinuxBIOSv2/util/flashrom/sst_fwhub.c	2007-02-06 19:47:50 UTC (rev 2550)
@@ -23,7 +23,6 @@
 #include <errno.h>
 #include <fcntl.h>
 #include <sys/mman.h>
-#include <sys/io.h>
 #include <unistd.h>
 #include <stdio.h>
 #include <stdlib.h>




From stepan at coresystems.de  Tue Feb  6 20:53:46 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 6 Feb 2007 20:53:46 +0100
Subject: [LinuxBIOS] LinuxBIOS Solaris Dev
In-Reply-To: <20070201013302.GB9824@greenwood>
References: <B336556B53FC0F42AE59AD52F8B8D5BD012382ED@exchange01.pdsi.local>
	<13426df10701311344r7263318fn70ad85fa157c804f@mail.gmail.com>
	<20070131221941.GA5178@greenwood> <45C11B63.6030708@coresystems.de>
	<20070201012644.GA9824@greenwood> <20070201013302.GB9824@greenwood>
Message-ID: <20070206195346.GA13645@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070201 02:33]:
> On Thu, Feb 01, 2007 at 02:26:45AM +0100, Uwe Hermann wrote:
> > Patch attached.
> 
> Forgot the sign-off. New patch.
 
Acked-by: Stefan Reinauer <stepan at coresystems.de>

and applied.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Tue Feb  6 20:53:52 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue,  6 Feb 2007 20:53:52 +0100
Subject: [LinuxBIOS] r2551 - trunk/LinuxBIOSv2/util/flashrom
Message-ID: <mailman.170.1355071058.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-02-06 20:53:51 +0100 (Tue, 06 Feb 2007)
New Revision: 2551

Added:
   trunk/LinuxBIOSv2/util/flashrom/linuxbios_tables.h
Modified:
   trunk/LinuxBIOSv2/util/flashrom/lbtable.c
Log:
Include src/include/boot/linuxbios_tables.h in the flashrom source
tree to make it compilable independant of the LinuxBIOS source code.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/util/flashrom/lbtable.c
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/lbtable.c	2007-02-06 19:47:50 UTC (rev 2550)
+++ trunk/LinuxBIOSv2/util/flashrom/lbtable.c	2007-02-06 19:53:51 UTC (rev 2551)
@@ -8,7 +8,7 @@
 #include <errno.h>
 #include <sys/mman.h>
 #include "flash.h"
-#include "../../src/include/boot/linuxbios_tables.h"
+#include "linuxbios_tables.h"
 #include "debug.h"
 
 char *lb_part=NULL, *lb_vendor=NULL;

Added: trunk/LinuxBIOSv2/util/flashrom/linuxbios_tables.h
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/linuxbios_tables.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/util/flashrom/linuxbios_tables.h	2007-02-06 19:53:51 UTC (rev 2551)
@@ -0,0 +1,216 @@
+#ifndef LINUXBIOS_TABLES_H
+#define LINUXBIOS_TABLES_H
+
+#include <stdint.h>
+
+/* The linuxbios table information is for conveying information
+ * from the firmware to the loaded OS image.  Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as quering the hardware directly.
+ *
+ * All of the information should be Position Independent Data.  
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctnes changing.   For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed.  This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ *   a particular motherboard is constructed? (Assuming the kernel
+ *   has drivers for all of the hardware but it does not have
+ *   assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not.  This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped.  Of course it is polite and expidite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since LinuxBIOS is usually compiled 32bit, gcc will align 64bit 
+ * types to 32bit boundaries. If the LinuxBIOS table is dumped on a 
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries, 
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit LinuxBIOS table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+        uint64_t result;
+        result = value.hi;
+        result = (result << 32) + value.lo;
+        return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+        struct lb_uint64 result;
+        result.lo = (value >> 0) & 0xffffffff;
+        result.hi = (value >> 32) & 0xffffffff;
+        return result;
+}
+
+
+
+struct lb_header
+{
+	uint8_t  signature[4]; /* LBIO */
+	uint32_t header_bytes;
+	uint32_t header_checksum;
+	uint32_t table_bytes;
+	uint32_t table_checksum;
+	uint32_t table_entries;
+};
+
+/* Every entry in the boot enviroment list will correspond to a boot
+ * info record.  Encoding both type and size.  The type is obviously
+ * so you can tell what it is.  The size allows you to skip that
+ * boot enviroment record if you don't know what it easy.  This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+	uint32_t tag;		/* tag ID */
+	uint32_t size;		/* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED	0x0000
+
+#define LB_TAG_MEMORY	0x0001
+
+struct lb_memory_range {
+	struct lb_uint64 start;
+	struct lb_uint64 size;
+	uint32_t type;
+#define LB_MEM_RAM       1	/* Memory anyone can use */
+#define LB_MEM_RESERVED  2	/* Don't use this memory region */
+#define LB_MEM_TABLE     16	/* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+	uint32_t tag;
+	uint32_t size;
+	struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB	0x0002
+struct lb_hwrpb {
+	uint32_t tag;
+	uint32_t size;
+	uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
+#define LB_TAG_VERSION		0x0004
+#define LB_TAG_EXTRA_VERSION	0x0005
+#define LB_TAG_BUILD		0x0006
+#define LB_TAG_COMPILE_TIME	0x0007
+#define LB_TAG_COMPILE_BY	0x0008
+#define LB_TAG_COMPILE_HOST	0x0009
+#define LB_TAG_COMPILE_DOMAIN	0x000a
+#define LB_TAG_COMPILER		0x000b
+#define LB_TAG_LINKER		0x000c
+#define LB_TAG_ASSEMBLER	0x000d
+struct lb_string {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  string[0];
+};
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+	uint32_t tag;               /* CMOS definitions table type */
+	uint32_t size;               /* size of the entire table */
+	uint32_t header_length;      /* length of header */
+};
+
+/* cmos entry record
+        This record is variable length.  The name field may be
+        shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+        anywhere in the byte, but can not span bytes unless it
+        starts at the beginning of the byte and the length is
+        fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+	uint32_t tag;                /* entry type */
+	uint32_t size;               /* length of this record */
+	uint32_t bit;                /* starting bit from start of image */
+	uint32_t length;             /* length of field in bits */
+	uint32_t config;             /* e=enumeration, h=hex, r=reserved */
+	uint32_t config_id;          /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii, 
+					       variable length int aligned */
+};
+
+
+/* cmos enumerations record
+        This record is variable length.  The text field may be
+        shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+	uint32_t tag;		     /* enumeration type */
+	uint32_t size; 		     /* length of this record */
+	uint32_t config_id;          /* a number identifying the config id */
+	uint32_t value;              /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+	uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii, 
+						variable length int aligned */
+};
+
+/* cmos defaults record
+        This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+	uint32_t tag;                /* default type */
+	uint32_t size;               /* length of this record */
+	uint32_t name_length;        /* length of the following name field */
+	uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 128
+	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct	cmos_checksum {
+	uint32_t tag;
+	uint32_t size;
+	/* In practice everything is byte aligned, but things are measured
+	 * in bits to be consistent.
+	 */
+	uint32_t range_start;	/* First bit that is checksummed (byte aligned) */
+	uint32_t range_end;	/* Last bit that is checksummed (byte aligned) */
+	uint32_t location;	/* First bit of the checksum (byte aligned) */
+	uint32_t type;		/* Checksum algorithm that is used */
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+};
+
+
+
+#endif /* LINUXBIOS_TABLES_H */




From c-d.hailfinger.devel.2006 at gmx.net  Tue Feb  6 22:57:42 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 06 Feb 2007 22:57:42 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070206194821.21747gmx1@mx092.gmx.net>
References: <20070206194821.21747gmx1@mx092.gmx.net>
Message-ID: <45C8F9D6.5060109@gmx.net>

Hi!

svn at openbios.org wrote:
> Signed-off-by: Adam Kaufman <adam.kaufman at pinnacle.com>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
> Acked-by: Adam Kaufman <adam.kaufman at pinnacle.com>

It seems there is still some confusion about Signed-off-by
and Acked-by. The meaning of Acked-by is a real subset of
Signed-off-by. So acking a patch you already signed off
for is totally meaningless and should be avoided. The
Linux kernel guys never ack and sign off the same patch.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From bxshi at msik.com.cn  Wed Feb  7 03:31:15 2007
From: bxshi at msik.com.cn (bxshi at msik.com.cn)
Date: Wed, 7 Feb 2007 10:31:15 +0800
Subject: [LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
Message-ID: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>

Dear all,
This patch is for MSI K9ND Master Series (ms9282) LinuxBIOS support.
Thanks very much for Yinghai's great work for MCP55.

Sign-off-by: Bingxun Shi <bingxunshi at gmail.com>

Description for 9282
Cpu :  AMD socket F
Memory: DDR2 16 DIMMS
Chipset: nVidia MCP55

Detailed information ,
http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632



Index: src/mainboard/msi/ms9282/Config.lb
===================================================================
--- src/mainboard/msi/ms9282/Config.lb  (revision 0)
+++ src/mainboard/msi/ms9282/Config.lb  (revision 0)
@@ -0,0 +1,418 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2006 AMD
+## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+##
+## Copyright (C) 2006 MSI
+## Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+       default ROM_SECTION_SIZE   = FALLBACK_SIZE
+       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+       default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD     = 1
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#dir /drivers/ati/ragexl
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+end
+
+else
+
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
+
+##
+## Romcc output
+##
+makerule ./failover.E
+        depends "$(MAINBOARD)/failover.c ./romcc"
+        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+        depends "$(MAINBOARD)/failover.c ./romcc"
+        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E
+        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+       if CONFIG_USE_INIT
+               ldscript /cpu/x86/32bit/entry32.lds
+       end
+
+       if CONFIG_USE_INIT
+               ldscript      /cpu/amd/car/cache_as_ram.lds
+       end
+end
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+       mainboardinit cpu/x86/16bit/reset16.inc
+       ldscript /cpu/x86/16bit/reset16.lds
+else
+       mainboardinit cpu/x86/32bit/reset32.inc
+       ldscript /cpu/x86/32bit/reset32.lds
+end
+
+if USE_DCACHE_RAM
+else
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit southbridge/nvidia/mcp55/id.inc
+ldscript /southbridge/nvidia/mcp55/id.lds
+
+##
+## ROMSTRAP table for MCP55
+##
+if USE_FALLBACK_IMAGE
+       mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+       ldscript /southbridge/nvidia/mcp55/romstrap.lds
+end
+
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+       mainboardinit ./failover.inc
+end
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+# ROMCC
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+end
+
+##
+## Include the secondary Configuration files
+##
+if CONFIG_CHIP_NAME
+        config chip.h
+end
+
+
+# sample config for msi/ms9282
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+
+       device pci_domain 0 on
+               chip northbridge/amd/amdk8 #mc0
+                       device pci 18.0 on #  northbridge
+                               #  devices on link 0, link 0 == LDT 0
+                               chip southbridge/nvidia/mcp55
+                                       device pci 0.0 on end   # HT
+                                       device pci 1.0 on # LPC
+                                               chip superio/winbond/w83627ehg
+                                                       device pnp 2e.0 on #  Floppy
+                                                               io 0x60 = 0x3f0
+                                                               irq 0x70 = 6
+                                                               drq 0x74 = 2
+                                                       end
+                                                       device pnp 2e.1 off #  Parallel Port
+                                                               io 0x60 = 0x378
+                                                               irq 0x70 = 7
+                                                       end
+                                                       device pnp 2e.2 on #  Com1
+                                                               io 0x60 = 0x3f8
+                                                               irq 0x70 = 4
+                                                       end
+                                                       device pnp 2e.3 off #  Com2
+                                                               io 0x60 = 0x2f8
+                                                               irq 0x70 = 3
+                                                       end
+                                                       device pnp 2e.5 on #  Keyboard
+                                                               io 0x60 = 0x60
+                                                               io 0x62 = 0x64
+                                                               irq 0x70 = 1
+                                                               irq 0x72 = 12
+                                                       end
+                                                       device pnp 2e.6 off #  SERIAL_FALSH
+                                                               io 0x60 = 0x100
+                                                       end
+                                                       device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                                                               io 0x60 = 0x220
+                                                               io 0x62 = 0x300
+                                                               irq 0x70 = 9
+                                                       end
+                                                       device pnp 2e.8 off end #  WDTO_PLED
+                                                       device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
+                                                       device pnp 2e.a off end #  ACPI
+                                                       device pnp 2e.b on #  HW Monitor
+                                                               io 0x60 = 0x290
+                                                               irq 0x70 = 5
+                                                       end
+                                               end
+                                       end
+                                        device pci 1.1 on # SM 0
+                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+                                                       device i2c 70 on  #0 pca9554 1
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                       end
+                                                       device i2c 70 on  #0 pca9554 2
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                       end
+                                               end
+                                       end
+                                       device pci 1.1 on # SM 1
+                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+                                                       device i2c 72 on     #pca9554 channle1
+                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                                       device i2c 72 on     #pca9545 channel 2
+                                                               chip drivers/i2c/adm1027   #HWM ADT7463
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                                       device i2c 72 on end  #pca9545 channel 3
+                                                       device i2c 72 on      #pca9545 channel 4
+                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                               end
+                                       end
+
+                                       device pci 2.0 on end # USB 1.1
+                                       device pci 2.1 on end # USB 2
+                                       device pci 4.0 on  end # IDE
+                                               device pci 5.0 on  end # SATA 0
+                                       device pci 5.1 on  end # SATA 1
+                                       device pci 5.2 on  end # SATA 2
+                                       device pci 6.0 on  #P2P
+                                               chip drivers/pci/onboard
+                                                       device pci 4.0 on end
+                                                       register "rom_address" = "0xfff80000"
+                                               end
+                                       end # P2P
+                                       device pci 7.0 on end # reserve
+                                       device pci 8.0 on end # MAC0
+                                       device pci 9.0 on end # MAC1
+                                       device pci a.0 on
+                                               device pci 0.0 on
+                                                       chip drivers/pci/onboard
+                                                               device pci 4.0 on end  #pci_E lan1
+                                                               device pci 4.1 on end  #pci_E lan2
+                                                       end
+                                               end
+                                       end # 0x376
+                                               device pci b.0 on  end # PCI E 0x374
+                                       device pci c.0 on  end
+                                       device pci d.0 on   #SAS
+                                               chip drivers/pci/onboard
+                                                       device pci 0.0 on end
+                                               end
+                                       end # PCI E 1 0x378
+                                       device pci e.0 on end # PCI E 0 0x375
+                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
+                                       register "ide0_enable" = "1"
+                                       register "ide1_enable" = "1"
+                                       register "sata0_enable" = "1"
+                                       register "sata1_enable" = "1"
+                               end
+                       end #  device pci 18.0
+                       device pci 18.0 on end # Link 1
+                       device pci 18.0 on end
+                       device pci 18.1 on end
+                       device pci 18.2 on end
+                       device pci 18.3 on end
+               end #mc0
+
+       end # pci_domain
+
+#        chip drivers/generic/debug
+#                device pnp 0.0 off end
+#                device pnp 0.1 off end
+#                device pnp 0.2 off end
+#                device pnp 0.3 off end
+#                device pnp 0.4 off end
+#              device pnp 0.5 on end
+#        end
+end # root_complex


Index: src/mainboard/msi/ms9282/mptable.c
===================================================================
--- src/mainboard/msi/ms9282/mptable.c  (revision 0)
+++ src/mainboard/msi/ms9282/mptable.c  (revision 0)
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "MSI    ";
+        static const char productid[12] = "MS9282       ";
+        struct mp_config_table *mc;
+       struct mb_sysconf_t *m;
+       unsigned sbdn;
+
+       int i,j;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+       get_bus_conf();
+       sbdn = sysconf.sbdn;
+       m = sysconf.mb;
+
+/*Bus:         Bus ID  Type*/
+       /* define bus and isa numbers */
+        for(j= 0; j < 256 ; j++) {
+               if(m->bus_type[j])
+                        smp_write_bus(mc, j, "PCI   ");
+        }
+        smp_write_bus(mc, m->bus_isa, "ISA   ");
+
+/*I/O APICs:   APIC ID Version State           Address*/
+        {
+                device_t dev;
+               struct resource *res;
+               uint32_t dword;
+
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                if (dev) {
+                       res = find_resource(dev, PCI_BASE_ADDRESS_1);
+                       if (res) {
+                               smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+                       }
+
+                       dword = 0x43c6c643;
+                       pci_write_config32(dev, 0x7c, dword);
+
+                       dword = 0x81001a00;
+                       pci_write_config32(dev, 0x80, dword);
+
+                       dword = 0xd00002d2;
+                       pci_write_config32(dev, 0x84, dword);
+
+                }
+
+
+       }
+
+                  /*I/O Ints:  Type    Polarity    Trigger                     Bus ID   IRQ    APIC ID PIN# */
+       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
+
+//SMBUS
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
+
+//USB1.1
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
+
+//USB2.0
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+//SATA1
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
+
+//SATA2
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+//SATA3
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
+
+//NIC1
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
+//NIC2
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
+
+       for(j=7; j>=2; j--) {
+               if(!m->bus_mcp55[j]) continue;
+               for(i=0;i<4;i++) {
+                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+               }
+       }
+
+       for(j=0; j<1; j++)
+               for(i=0;i<4;i++) {
+                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
+               }
+
+/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
+       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+       smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+       /* There is no extension information... */
+
+       /* Compute the checksums */
+       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+       printk_debug("Wrote the mp table end at: %p - %p\n",
+               mc, smp_next_mpe_entry(mc));
+       return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+       void *v;
+       v = smp_write_floating_table(addr);
+       return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/msi/ms9282/irq_tables.c
===================================================================
--- src/mainboard/msi/ms9282/irq_tables.c       (revision 0)
+++ src/mainboard/msi/ms9282/irq_tables.c       (revision 0)
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify!
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+#include "mb_sysconf.h"
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+               uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+               uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus;
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+       struct irq_routing_table *pirq;
+       struct irq_info *pirq_info;
+       unsigned slot_num;
+       uint8_t *v;
+       struct mb_sysconf_t *m;
+       unsigned sbdn;
+
+        uint8_t sum=0;
+        int i;
+
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+       sbdn = sysconf.sbdn;
+       m = sysconf.mb;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+       pirq = (void *)(addr);
+       v = (uint8_t *)(addr);
+
+       pirq->signature = PIRQ_SIGNATURE;
+       pirq->version  = PIRQ_VERSION;
+
+       pirq->rtr_bus = m->bus_mcp55[0];
+       pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+
+       pirq->exclusive_irqs = 0;
+
+       pirq->rtr_vendor = 0x10de;
+       pirq->rtr_device = 0x0370;
+
+       pirq->miniport_data = 0;
+
+       memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+       pirq_info = (void *) ( &pirq->checksum + 1);
+       slot_num = 0;
+//pci bridge
+       write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+       pirq_info++; slot_num++;
+
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+                if(!(sysconf.pci1234[i] & 0x1) ) continue;
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned devn = sysconf.hcdn[i] & 0xff;
+
+                write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+                pirq_info++; slot_num++;
+       }
+
+       pirq->size = 32 + 16 * slot_num;
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];
+
+       sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+       printk_info("done.\n");
+
+       return  (unsigned long) pirq_info;
+
+}
Index: src/mainboard/msi/ms9282/resourcemap.c
===================================================================
--- src/mainboard/msi/ms9282/resourcemap.c      (revision 0)
+++ src/mainboard/msi/ms9282/resourcemap.c      (revision 0)
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2003 Stefan Reinauer <stepan at coresystems.de>
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * MSI ms9282 needs a different resource map
+ *
+ */
+
+static void setup_ms9282_resource_map(void)
+{
+       static const unsigned int register_values[] = {
+#if 1
+               /* Careful set limit registers before base registers which contain the enables */
+               /* DRAM Limit i Registers
+                * F1:0x44 i = 0
+                * F1:0x4C i = 1
+                * F1:0x54 i = 2
+                * F1:0x5C i = 3
+                * F1:0x64 i = 4
+                * F1:0x6C i = 5
+                * F1:0x74 i = 6
+                * F1:0x7C i = 7
+                * [ 2: 0] Destination Node ID
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 7: 3] Reserved
+                * [10: 8] Interleave select
+                *         specifies the values of A[14:12] to use with interleave enable.
+                * [15:11] Reserved
+                * [31:16] DRAM Limit Address i Bits 39-24
+                *         This field defines the upper address bits of a 40 bit  address
+                *         that define the end of the DRAM region.
+                */
+               PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+               PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+               PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+               PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+               PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+               PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+               PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+               /* DRAM Base i Registers
+                * F1:0x40 i = 0
+                * F1:0x48 i = 1
+                * F1:0x50 i = 2
+                * F1:0x58 i = 3
+                * F1:0x60 i = 4
+                * F1:0x68 i = 5
+                * F1:0x70 i = 6
+                * F1:0x78 i = 7
+                * [ 0: 0] Read Enable
+                *         0 = Reads Disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes Disabled
+                *         1 = Writes Enabled
+                * [ 7: 2] Reserved
+                * [10: 8] Interleave Enable
+                *         000 = No interleave
+                *         001 = Interleave on A[12] (2 nodes)
+                *         010 = reserved
+                *         011 = Interleave on A[12] and A[14] (4 nodes)
+                *         100 = reserved
+                *         101 = reserved
+                *         110 = reserved
+                *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+                * [15:11] Reserved
+                * [13:16] DRAM Base Address i Bits 39-24
+                *         This field defines the upper address bits of a 40-bit address
+                *         that define the start of the DRAM region.
+                */
+               PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+#endif
+#if 1
+
+               /* Memory-Mapped I/O Limit i Registers
+                * F1:0x84 i = 0
+                * F1:0x8C i = 1
+                * F1:0x94 i = 2
+                * F1:0x9C i = 3
+                * F1:0xA4 i = 4
+                * F1:0xAC i = 5
+                * F1:0xB4 i = 6
+                * F1:0xBC i = 7
+                * [ 2: 0] Destination Node ID
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 3: 3] Reserved
+                * [ 5: 4] Destination Link ID
+                *         00 = Link 0
+                *         01 = Link 1
+                *         10 = Link 2
+                *         11 = Reserved
+                * [ 6: 6] Reserved
+                * [ 7: 7] Non-Posted
+                *         0 = CPU writes may be posted
+                *         1 = CPU writes must be non-posted
+                * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+                *         This field defines the upp adddress bits of a 40-bit address that
+                *         defines the end of a memory-mapped I/O region n
+                */
+               PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+//             PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+               /* Memory-Mapped I/O Base i Registers
+                * F1:0x80 i = 0
+                * F1:0x88 i = 1
+                * F1:0x90 i = 2
+                * F1:0x98 i = 3
+                * F1:0xA0 i = 4
+                * F1:0xA8 i = 5
+                * F1:0xB0 i = 6
+                * F1:0xB8 i = 7
+                * [ 0: 0] Read Enable
+                *         0 = Reads disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes disabled
+                *         1 = Writes Enabled
+                * [ 2: 2] Cpu Disable
+                *         0 = Cpu can use this I/O range
+                *         1 = Cpu requests do not use this I/O range
+                * [ 3: 3] Lock
+                *         0 = base/limit registers i are read/write
+                *         1 = base/limit registers i are read-only
+                * [ 7: 4] Reserved
+                * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+                *         This field defines the upper address bits of a 40bit address
+                *         that defines the start of memory-mapped I/O region i
+                */
+               PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+//             PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+#endif
+#if 1
+
+               /* PCI I/O Limit i Registers
+                * F1:0xC4 i = 0
+                * F1:0xCC i = 1
+                * F1:0xD4 i = 2
+                * F1:0xDC i = 3
+                * [ 2: 0] Destination Node ID
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 3: 3] Reserved
+                * [ 5: 4] Destination Link ID
+                *         00 = Link 0
+                *         01 = Link 1
+                *         10 = Link 2
+                *         11 = reserved
+                * [11: 6] Reserved
+                * [24:12] PCI I/O Limit Address i
+                *         This field defines the end of PCI I/O region n
+                * [31:25] Reserved
+                */
+               PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+               PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+               /* PCI I/O Base i Registers
+                * F1:0xC0 i = 0
+                * F1:0xC8 i = 1
+                * F1:0xD0 i = 2
+                * F1:0xD8 i = 3
+                * [ 0: 0] Read Enable
+                *         0 = Reads Disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes Disabled
+                *         1 = Writes Enabled
+                * [ 3: 2] Reserved
+                * [ 4: 4] VGA Enable
+                *         0 = VGA matches Disabled
+                *         1 = matches all address < 64K and where A[9:0] is in the
+                *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+                * [ 5: 5] ISA Enable
+                *         0 = ISA matches Disabled
+                *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+                *             from matching agains this base/limit pair
+                * [11: 6] Reserved
+                * [24:12] PCI I/O Base i
+                *         This field defines the start of PCI I/O region n
+                * [31:25] Reserved
+                */
+               PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+               PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+#endif
+               /* Config Base and Limit i Registers
+                * F1:0xE0 i = 0
+                * F1:0xE4 i = 1
+                * F1:0xE8 i = 2
+                * F1:0xEC i = 3
+                * [ 0: 0] Read Enable
+                *         0 = Reads Disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes Disabled
+                *         1 = Writes Enabled
+                * [ 2: 2] Device Number Compare Enable
+                *         0 = The ranges are based on bus number
+                *         1 = The ranges are ranges of devices on bus 0
+                * [ 3: 3] Reserved
+                * [ 6: 4] Destination Node
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 7: 7] Reserved
+                * [ 9: 8] Destination Link
+                *         00 = Link 0
+                *         01 = Link 1
+                *         10 = Link 2
+                *         11 - Reserved
+                * [15:10] Reserved
+                * [23:16] Bus Number Base i
+                *         This field defines the lowest bus number in configuration region i
+                * [31:24] Bus Number Limit i
+                *         This field defines the highest bus number in configuration region i
+                */
+#if 1
+//             PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
+//             PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
+               PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+#endif
+
+       };
+
+       int max;
+       max = sizeof(register_values)/sizeof(register_values[0]);
+       setup_resource_map(register_values, max);
+}
+
Index: src/mainboard/msi/ms9282/Options.lb
===================================================================
--- src/mainboard/msi/ms9282/Options.lb (revision 0)
+++ src/mainboard/msi/ms9282/Options.lb (revision 0)
@@ -0,0 +1,309 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2006 AMD
+## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+##
+## Copyright (C) 2006 MSI
+## Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+#bx_b005+
+uses SB_HT_CHAIN_ON_BUS0
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+#512K bytes
+default ROM_SIZE=524288
+
+#1M bytes
+#bx- default ROM_SIZE=1048576
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+#CHIP_NAME ?
+#default CONFIG_CHIP_NAME=1
+
+#1G memory hole
+#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0
+
+#make the SB HT chain on bus 0, default is not (0)
+#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
+
+##bx_b005+ make the SB HT chain on bus 0
+default SB_HT_CHAIN_ON_BUS0=1
+
+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#VGA
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcc000
+default DCACHE_RAM_SIZE=0x4000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
+
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="ms9282"
+default MAINBOARD_VENDOR="MSI"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end

Index: src/mainboard/msi/ms9282/failover.c
===================================================================
--- src/mainboard/msi/ms9282/failover.c (revision 0)
+++ src/mainboard/msi/ms9282/failover.c (revision 0)
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/mc146818rtc_early.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+       uint32_t dword;
+       uint8_t byte;
+
+        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20;
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+
+       dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+       dword |= (1<<0);
+       pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+
+
+}
+
+#if CONFIG_LOGICAL_CPUS==1
+#include "cpu/amd/dualcore/dualcore_id.c"
+#endif
+
+static unsigned long main(unsigned long bist)
+{
+        /* Make cerain my local apic is useable */
+        enable_lapic();
+
+        /* Is this a cpu only reset? */
+        if (early_mtrr_init_detected()) {
+               if (last_boot_normal()) {
+                       goto normal_image;
+               } else {
+                       goto fallback_image;
+               }
+       }
+
+       /* Is this a secondary cpu? */
+       if (!boot_cpu()) {
+               if (last_boot_normal()) {
+                       goto normal_image;
+               } else {
+                       goto fallback_image;
+               }
+       }
+
+       /* Nothing special needs to be done to find bus 0 */
+       /* Allow the HT devices to be found */
+
+       enumerate_ht_chain();
+
+       sio_setup();
+
+       /* Setup the mcp55 */
+       mcp55_enable_rom();
+
+       /* Is this a deliberate reset by the bios */
+       if (bios_reset_detected() && last_boot_normal()) {
+               goto normal_image;
+       }
+       /* This is the primary cpu how should I boot? */
+       else if (do_normal_boot()) {
+               goto normal_image;
+       }
+       else {
+               goto fallback_image;
+       }
+ normal_image:
+       asm volatile ("jmp __normal_image"
+               : /* outputs */
+               : "a" (bist) /* inputs */
+               : /* clobbers */
+               );
+ fallback_image:
+       return bist;
+}
Index: src/mainboard/msi/ms9282/mb_sysconf.h
===================================================================
--- src/mainboard/msi/ms9282/mb_sysconf.h       (revision 0)
+++ src/mainboard/msi/ms9282/mb_sysconf.h       (revision 0)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned apicid_mcp55;
+       unsigned bus_type[256];
+
+};
+
+#endif
+
Index: src/mainboard/msi/ms9282/chip.h
===================================================================
--- src/mainboard/msi/ms9282/chip.h     (revision 0)
+++ src/mainboard/msi/ms9282/chip.h     (revision 0)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_msi_ms9282_ops;
+
+struct mainboard_msi_ms9282_config {
+       int fixup_scsi;
+       int fixup_vga;
+};
Index: src/mainboard/msi/ms9282/cmos.layout
===================================================================
--- src/mainboard/msi/ms9282/cmos.layout        (revision 0)
+++ src/mainboard/msi/ms9282/cmos.layout        (revision 0)
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
Index: src/mainboard/msi/ms9282/mainboard.c
===================================================================
--- src/mainboard/msi/ms9282/mainboard.c        (revision 0)
+++ src/mainboard/msi/ms9282/mainboard.c        (revision 0)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_tyan_ms9282_ops = {
+       CHIP_NAME("MSI ms9282 mainboard")
+};
+#endif
Index: src/mainboard/msi/ms9282/get_bus_conf.c
===================================================================
--- src/mainboard/msi/ms9282/get_bus_conf.c     (revision 0)
+++ src/mainboard/msi/ms9282/get_bus_conf.c     (revision 0)
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+struct mb_sysconf_t mb_sysconf;
+
+unsigned pci1234x[] =
+{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+        //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+        0x0000ff0,
+        0x0000ff0,
+        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0
+};
+unsigned hcdnx[] =
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+       0x20202020,
+       0x20202020,
+        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+};
+
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+static unsigned get_hcid(unsigned i)
+{
+        unsigned id = 0;
+
+        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+
+        unsigned devn = sysconf.hcdn[i] & 0xff;
+
+        device_t dev;
+
+        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+
+        switch (dev->device) {
+        case 0x0369: //IO55
+                id = 4;
+                break;
+        }
+
+        // we may need more way to find out hcid: subsystem id? GPIO read ?
+
+        // we need use id for 1. bus num, 2. mptable, 3. acpi table
+
+        return id;
+}
+
+void get_bus_conf(void)
+{
+
+       unsigned apicid_base;
+       struct mb_sysconf_t *m;
+
+        device_t dev;
+        int i, j;
+
+        if(get_bus_conf_done==1) return; //do it only once
+
+        get_bus_conf_done = 1;
+
+       sysconf.mb = &mb_sysconf;
+
+       m = sysconf.mb;
+       memset(m, 0, sizeof(struct mb_sysconf_t));
+
+        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        for(i=0;i<sysconf.hc_possible_num; i++) {
+                sysconf.pci1234[i] = pci1234x[i];
+                sysconf.hcdn[i] = hcdnx[i];
+        }
+
+        get_sblk_pci1234();
+
+       sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+
+       m->bus_type[0] = 1; //pci
+
+       m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+
+                /* MCP55 */
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+                if (dev) {
+                        m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+                }
+
+               for(i=2; i<8;i++) {
+                       dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+                       if (dev) {
+                               m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                       }
+                       else {
+                               printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+                       }
+               }
+
+       for(i=0; i< sysconf.hc_possible_num; i++) {
+               if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
+               for (j = busn; j <= busn_max; j++)
+                       m->bus_type[j] = 1;
+               if(m->bus_isa <= busn_max)
+                       m->bus_isa = busn_max + 1;
+               printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+       }
+
+
+
+/*I/O APICs:   APIC ID Version State           Address*/
+#if CONFIG_LOGICAL_CPUS==1
+       apicid_base = get_apicid_base(1);
+#else
+       apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+       m->apicid_mcp55 = apicid_base+0;
+
+}
Index: src/mainboard/msi/ms9282/cache_as_ram_auto.c
===================================================================
--- src/mainboard/msi/ms9282/cache_as_ram_auto.c        (revision 0)
+++ src/mainboard/msi/ms9282/cache_as_ram_auto.c        (revision 0)
@@ -0,0 +1,296 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 1
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#define DEBUG_SMBUS 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+       #include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
+
+#include <device/pci_ids.h>
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+#define SMBUS_SWITCH1 0x70
+#define SMBUS_SWITCH2 0x72
+        unsigned device=(ctrl->channel0[0])>>8;
+        smbus_send_byte(SMBUS_SWITCH1, device);
+       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+}
+
+#if 0
+static inline void change_i2c_mux(unsigned device)
+{
+#define SMBUS_SWITCH1 0x70
+#define SMBUS_SWITHC2 0x72
+        smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
+       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+}
+#endif
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+       return smbus_read_byte(device, address);
+}
+
+//#define K8_4RANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+ /* msi does not want the default */
+#include "resourcemap.c"
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define MCP55_NUM 1
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+//set GPIO to input mode
+#define MCP55_MB_SETUP \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+        uint32_t dword;
+        uint8_t byte;
+
+        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20;
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+        dword |= (1<<0);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+
+
+}
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        sio_setup();
+
+        /* Setup the mcp55 */
+        mcp55_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+       ;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
+#define RC0 (2<<8)
+#define RC1 (1<<8)
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+       static const uint16_t spd_addr [] = {
+                       RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
+                       RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+                       RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
+                       RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+#endif
+       };
+
+       unsigned bsp_apicid = 0;
+        int needs_reset;
+       struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+       char *p ;
+
+        if (bist == 0) {
+               //init_cpus(cpu_init_detectedx);
+               bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+       w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
+        setup_ms9282_resource_map();
+
+       setup_coherent_ht_domain();
+
+        wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        start_other_cores();
+        //wait_all_other_cores_started(bsp_apicid);
+#endif
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+       needs_reset = optimize_link_coherent_ht();
+
+       needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+        needs_reset |= mcp55_early_setup_x();
+
+               if (needs_reset) {
+                       print_info("ht reset -\r\n");
+                       soft_reset();
+               }
+
+        //It's the time to set ctrl now;
+        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+       enable_smbus();
+
+#if 0
+        int i;
+        for(i=4;i<8;i++) {
+                change_i2c_mux(i);
+                dump_smbus_registers();
+        }
+#endif
+
+       memreset_setup();
+
+       sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+       post_cache_as_ram();
+
+}


Index: targets/msi/ms9282/Config.lb
===================================================================
--- targets/msi/ms9282/Config.lb        (revision 0)
+++ targets/msi/ms9282/Config.lb        (revision 0)
@@ -0,0 +1,91 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2006 MSI
+## Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target ms9282
+mainboard msi/ms9282
+
+romimage "normal"
+#       48K for SCSI FW
+#        option ROM_SIZE = 475136
+       option ROM_SIZE = 512*1024-36*1024
+#      option ROM_SIZE = 524288
+#       48K for SCSI FW and 48K for ATI ROM
+#       option ROM_SIZE = 425984
+#       64K for Etherboot
+#        option ROM_SIZE = 458752
+       option USE_FALLBACK_IMAGE=0
+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x18800
+       option ROM_IMAGE_SIZE=0x20000
+#      option ROM_IMAGE_SIZE=0x15800
+       option XIP_ROM_SIZE=0x40000
+       option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#      payload ../../../payloads/tg3.zelf
+#      payload ../../../../payloads/tg3_vga.zelf
+#      payload /filo.elf
+       payload /tg3--filo.elf
+#      payload /payload
+#      payload ../../../../payloads/e1000_vga.zelf
+#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#      payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+romimage "fallback"
+       option USE_FALLBACK_IMAGE=1
+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x19800
+       option ROM_IMAGE_SIZE=0x20000
+#      option ROM_IMAGE_SIZE=0x15800
+       option XIP_ROM_SIZE=0x40000
+       option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#      payload ../../../payloads/tg3.zelf
+#      payload ../../../../payloads/tg3_vga.zelf
+#      payload ../../../../payloads/memtest
+#      payload ../../../../payloads/e1000_vga.zelf
+#      payload ../../../../payloads/filo_hda.zelf
+#      payload /filo.elf
+       payload /tg3--filo.elf
+#      payload /payload
+#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#      payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+buildrom ./ms9282.lxb ROM_SIZE "normal" "fallback"




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From luis.f.correia at gmail.com  Wed Feb  7 10:48:45 2007
From: luis.f.correia at gmail.com (Luis Correia)
Date: Wed, 7 Feb 2007 09:48:45 +0000
Subject: [LinuxBIOS] Probable fix for gcc4 builds
Message-ID: <efe7343f0702070148q5d83263bxb3b6963f1e871200@mail.gmail.com>

Hi!

this is completely untested!

I got this hint from the syslinux mailing list regarding building on newer
distros, maybe this helps building linuxbios.

For newer distro's (like ubuntu 6.10, FC5+), syslinux build fails due to gcc
4. Here is a patch to get it to build properly.

The only thing it does is add -fno-stack-protection to CFLAGS in all the
Makefiles.

Source: (Ram Yalamanchili)


Luis
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From michalwan at hotmail.com  Wed Feb  7 11:35:42 2007
From: michalwan at hotmail.com (michal wan)
Date: Wed, 07 Feb 2007 18:35:42 +0800
Subject: [LinuxBIOS] why no mapped APIC
Message-ID: <BAY132-F354E4B6E1234CEF1749BC8B59E0@phx.gbl>

the log is  below:
No local APIC present or hardware disabled
Initializing CPU#0

google searchs something like:
mapped APIC to ffffd000 
or 
Using APIC driver default ACPI

what else step missed or not configured? any hints would be greatly 
appreciated!

_________________________________________________________________
???? MSN Explorer:   http://explorer.msn.com/lccn/  
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From lihao at mprc.pku.edu.cn  Wed Feb  7 13:24:59 2007
From: lihao at mprc.pku.edu.cn (lihao)
Date: Wed, 7 Feb 2007 20:24:59 +0800
Subject: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
In-Reply-To: <200702071156.20315.indrek.kruusa@artecdesign.ee>
Message-ID: <000001c74ab2$fd02ed10$07c8a8c0@dionysus>

Thanks for replying my question.
> All you need in VSA is vsainit and sysmanager (if you don't need graphics 
support).
  I need graphics support. I also have an ATI card, so I think I have two graphics 
card, one on board while another addon.

> In which particular order those init things must happen - look at 
> Geode GX/LX examples in LB tree (our is artecrgoup).
  I do not quite understand what you mean by _particular oder_, you mean 
First loading VSA, and then doing other things like graphic initialize??
  Also I found artecrgoup use Lx and Cs5536, which is not too much different 
from what I am using(gx2 and cs5535, and olpc/rev_a as my porting start) I think. I check the function pci_domain_enable() in src/northbridge/amd/lx/northbridge.c, I do think the code here is more clearly than the code in _gx_, but the order is almost the same.
  Maybe I misunderstand you; could you give me some explanation?

My situation:
I have a 512k flash rom, and I reserve 128k for vsa, 64k for vga, and 128k for payload, the left is for linuxbios.rom.
Now the code runs at device enumeration, and calls XXX_enable function of each 
device. When it comes to vga, it calls vsa to handle this. And then vsa is loaded successfully. After that, cpu generates exception 13, which is general protection. 
I got so confused and don?t know what causes that. Anyone meets this kind of problem before?? Any advice would be well appreciated.

-----????-----
???: Indrek Kruusa [mailto:indrek.kruusa at artecdesign.ee] 
????: 2007?2?7? 17:56
???: lihao
??: Re: ??: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??

?hel kenal p?eval (kolmap?ev 07 veebruar 2007 4:23 am) kirjutasid sa:
> The VSA is definitely loaded okay, I have checked the signature of it.
> At first, my VSA image is not compressed, but the code in LinuxBIOS calls
> Unrv2b() function to uncompress the VSA image.
> After I found this, I use nrv2b to compress the image and it is okay to
> jump into VSA's code.
> By the way, there are some codes which are commented out in loading VSA is
> totally for uncompressed VSA image(simply memory copy).
>
> I didn?t  build VGA bios in my image, may this be the reason why it didn?t
> pass pci_sanity_check functions??


No - you can stay completely without VGA ROM and LB works.

All you need in VSA is vsainit and sysmanager (if you don't need graphics 
support). In which particular order those init things must happen - look at 
Geode GX/LX examples in LB tree (our is artecrgoup).

cheers,
Indrek




> -----????-----
> ???: Indrek Kruusa [mailto:indrek.kruusa at artecdesign.ee]
> ????: 2007?2?6? 23:15
> ???: lihao
> ??: linuxbios at linuxbios.org
> ??: Re: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
>
> ?hel kenal p?eval (teisip?ev 06 veebruar 2007 12:37 am) kirjutas lihao:
> > Hi all,
> >
> >          I have made the codes run into the vsmbios. And it hangs on
> > pci_sanity_check(). Anyone has the same problems?
>
> Can you check that the signature of the loaded VSA is correct (e.g. by
> printing it out)?
> Do you have VSA nrv2b compressed or not?
>
>
> cheers,
> Indrek
>
> > I have 2 questions:
> >
> > 1)      I have downloaded VSA code, and VSA implements a softVG, do I
> > need to make a VGABIOS myself from linux?
> >
> > 2)      If I need a VGABIOS, where should I put it in the image??
> >
> >
> >
> >          Thanks, any advice would be well appreciated.
> >
> >
> >
> >   _____
> >
> > ???: lihao [mailto:lihao at mprc.pku.edu.cn]
> > ????: 2007?2?6? 3:13
> > ???: 'linuxbios at linuxbios.org'
> > ??: questions about VSA on Gx2 plus cs5535??
> >
> >
> >
> > Hi all,
> >
> >          I am running LinuxBIOS on gx2 and cs5535 platform. Now the code
> > begins to enumerate devices in northbridge.
> >
> > And the code hangs just after prints out _do_vsmbios_.
> >
> >          I find the next function called close to that print is
> > _unrv2b((uint8 *)rom, buffer, &ileg)_, and it seems that cpu is in dead
> > loop.
> >
> > I am thinking that maybe my linuxbios image is not correctly built. The
> > step I build image is divided into 2:
> >
> >          Firstly, I build out a _linuxbios.rom_ image;
> >
> >          Secondly, I use _buildrom_ tool from util directory to build
> > vsa2.bin and linuxbios.rom together out as the final image.
> >
> >          My flash is 512KB, so I put vsa2.bin at 0xfff80000, and
> > linuxbios.rom at another side of flash.
> >
> >          Is my step correct??
> >
> >
> >
> >          By the way, after I built out vsa image, it generates some other
> > images, which one should I choose? Including: vsa2.bin, olpcXXX.bin, some
> > vsms and so on?.
> >
> >
> >
> >          Any advice would be well appreciated.




From indrek.kruusa at artecdesign.ee  Wed Feb  7 16:30:33 2007
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Wed, 7 Feb 2007 17:30:33 +0200
Subject: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
In-Reply-To: <000001c74ab2$fd02ed10$07c8a8c0@dionysus>
References: <000001c74ab2$fd02ed10$07c8a8c0@dionysus>
Message-ID: <200702071730.33286.indrek.kruusa@artecdesign.ee>

?hel kenal p?eval (kolmap?ev 07 veebruar 2007 2:24 pm) kirjutas lihao:
> Thanks for replying my question.
>
> > All you need in VSA is vsainit and sysmanager (if you don't need graphics
>
> support).
>   I need graphics support. I also have an ATI card, so I think I have two
> graphics card, one on board while another addon.
>
> > In which particular order those init things must happen - look at
> > Geode GX/LX examples in LB tree (our is artecrgoup).
>
>   I do not quite understand what you mean by _particular oder_, you mean
> First loading VSA, and then doing other things like graphic initialize??

Yes. I'v pointed this out because you should see from existing code that there 
is nothing to do with graphics nor VGA  before VSA. So there can't be a 
question about VSA and VGA conflict in this stage. This is the only reason I 
referred to artecgroup's target.
GX/LX + CS5535/CS5536 = those are still different combinations.  Ideally you 
should start with the target which has gx2 and cs5535.


Indrek


>   Also I found artecrgoup use Lx and Cs5536, which is not too much
> different from what I am using(gx2 and cs5535, and olpc/rev_a as my porting
> start) I think.
> I check the function pci_domain_enable() in 
> src/northbridge/amd/lx/northbridge.c, I do think the code here is more
> clearly than the code in _gx_, but the order is almost the same. Maybe I
> misunderstand you; could you give me some explanation?
>
> My situation:
> I have a 512k flash rom, and I reserve 128k for vsa, 64k for vga, and 128k
> for payload, the left is for linuxbios.rom. Now the code runs at device
> enumeration, and calls XXX_enable function of each device. When it comes to
> vga, it calls vsa to handle this. And then vsa is loaded successfully.
> After that, cpu generates exception 13, which is general protection. I got
> so confused and don?t know what causes that. Anyone meets this kind of
> problem before?? Any advice would be well appreciated.
>
> -----????-----
> ???: Indrek Kruusa [mailto:indrek.kruusa at artecdesign.ee]
> ????: 2007?2?7? 17:56
> ???: lihao
> ??: Re: ??: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
>
> ?hel kenal p?eval (kolmap?ev 07 veebruar 2007 4:23 am) kirjutasid sa:
> > The VSA is definitely loaded okay, I have checked the signature of it.
> > At first, my VSA image is not compressed, but the code in LinuxBIOS calls
> > Unrv2b() function to uncompress the VSA image.
> > After I found this, I use nrv2b to compress the image and it is okay to
> > jump into VSA's code.
> > By the way, there are some codes which are commented out in loading VSA
> > is totally for uncompressed VSA image(simply memory copy).
> >
> > I didn?t  build VGA bios in my image, may this be the reason why it
> > didn?t pass pci_sanity_check functions??
>
> No - you can stay completely without VGA ROM and LB works.
>
> All you need in VSA is vsainit and sysmanager (if you don't need graphics
> support). In which particular order those init things must happen - look at
> Geode GX/LX examples in LB tree (our is artecrgoup).
>
> cheers,
> Indrek
>
> > -----????-----
> > ???: Indrek Kruusa [mailto:indrek.kruusa at artecdesign.ee]
> > ????: 2007?2?6? 23:15
> > ???: lihao
> > ??: linuxbios at linuxbios.org
> > ??: Re: [LinuxBIOS] questions about VSA on Gx2 plus cs5535??
> >
> > ?hel kenal p?eval (teisip?ev 06 veebruar 2007 12:37 am) kirjutas lihao:
> > > Hi all,
> > >
> > >          I have made the codes run into the vsmbios. And it hangs on
> > > pci_sanity_check(). Anyone has the same problems?
> >
> > Can you check that the signature of the loaded VSA is correct (e.g. by
> > printing it out)?
> > Do you have VSA nrv2b compressed or not?
> >
> >
> > cheers,
> > Indrek
> >
> > > I have 2 questions:
> > >
> > > 1)      I have downloaded VSA code, and VSA implements a softVG, do I
> > > need to make a VGABIOS myself from linux?
> > >
> > > 2)      If I need a VGABIOS, where should I put it in the image??
> > >
> > >
> > >
> > >          Thanks, any advice would be well appreciated.
> > >
> > >
> > >
> > >   _____
> > >
> > > ???: lihao [mailto:lihao at mprc.pku.edu.cn]
> > > ????: 2007?2?6? 3:13
> > > ???: 'linuxbios at linuxbios.org'
> > > ??: questions about VSA on Gx2 plus cs5535??
> > >
> > >
> > >
> > > Hi all,
> > >
> > >          I am running LinuxBIOS on gx2 and cs5535 platform. Now the
> > > code begins to enumerate devices in northbridge.
> > >
> > > And the code hangs just after prints out _do_vsmbios_.
> > >
> > >          I find the next function called close to that print is
> > > _unrv2b((uint8 *)rom, buffer, &ileg)_, and it seems that cpu is in dead
> > > loop.
> > >
> > > I am thinking that maybe my linuxbios image is not correctly built. The
> > > step I build image is divided into 2:
> > >
> > >          Firstly, I build out a _linuxbios.rom_ image;
> > >
> > >          Secondly, I use _buildrom_ tool from util directory to build
> > > vsa2.bin and linuxbios.rom together out as the final image.
> > >
> > >          My flash is 512KB, so I put vsa2.bin at 0xfff80000, and
> > > linuxbios.rom at another side of flash.
> > >
> > >          Is my step correct??
> > >
> > >
> > >
> > >          By the way, after I built out vsa image, it generates some
> > > other images, which one should I choose? Including: vsa2.bin,
> > > olpcXXX.bin, some vsms and so on?.
> > >
> > >
> > >
> > >          Any advice would be well appreciated.



From kononov195-lbl at yahoo.com  Wed Feb  7 17:15:36 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Wed, 07 Feb 2007 10:15:36 -0600
Subject: [LinuxBIOS]  ck804 romstrap modification
Message-ID: <45C9FB28.8040301@yahoo.com>

This modification simplifies automation of building ROM
files with correct MAC addresses.

The automation is done by adding the following into
src/mainboard/xxx/xxx/Config.lb

  ##
  ## ROMSTRAP table for CK804
  ##
  if USE_FALLBACK_IMAGE
+   mainboardinit southbridge/../../targets/xxx/xxx/mac_address.h
     mainboardinit southbridge/nvidia/ck804/romstrap.inc
     ldscript /southbridge/nvidia/ck804/romstrap.lds
  end

The location of mac_address.h can be different. The file is
generated by the build process or edited manually.

Signed-off-by: Roman Kononov <kononov195-lbl at yahoo.com>
---

Index: src/southbridge/nvidia/ck804/romstrap.inc
===================================================================
--- src/southbridge/nvidia/ck804/romstrap.inc	(revision 2551)
+++ src/southbridge/nvidia/ck804/romstrap.inc	(working copy)
@@ -24,8 +24,12 @@ linkedlist:
  	.long 0xFFFFFFFF			// 28h
  	.long 0xFFFFFFFF			// 2Ch
  	
+#if defined(MAC_ADDRESS)
+	.quad MAC_ADDRESS			// 30h, MAC address ---> keep it in 0xffffffd0
+#else	
  	.long 0x81543266			// 30h, MAC address low 4 byte ---> keep it in 0xffffffd0
  	.long 0x000000E0			// 34h, MAC address high 4 byte
+#endif

  	.long 0x002309CE			// 38h, UUID low 4 byte
  	.long 0x00E08100			// 3Ch, UUID high 4 byte





From yinghai.lu at amd.com  Wed Feb  7 18:35:21 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Wed, 7 Feb 2007 09:35:21 -0800
Subject: [LinuxBIOS] ck804 romstrap modification
Message-ID: <5986589C150B2F49A46483AC44C7BCA4907420@ssvlexmb2.amd.com>

That is not necessary.

For the cluster, 
1. you need to program mac address for every node at the first time.
2. and for the second time, you need to use scripts to preserve the mac
address.

YH






From kononov195-lbl at yahoo.com  Wed Feb  7 19:01:33 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Wed, 07 Feb 2007 12:01:33 -0600
Subject: [LinuxBIOS] ck804 romstrap modification
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA4907420@ssvlexmb2.amd.com>
References: <5986589C150B2F49A46483AC44C7BCA4907420@ssvlexmb2.amd.com>
Message-ID: <45CA13FD.3050306@yahoo.com>

On 02/07/2007 11:35 AM, Lu, Yinghai wrote:
> That is not necessary.
> 
> For the cluster, 
> 1. you need to program mac address for every node at the first time.
> 2. and for the second time, you need to use scripts to preserve the mac
> address.

Yinghai,

I am not sure that I understand you correctly. I guess, my
patch supposedly makes the step 1 easier.

I have no clusters. I have a number of PCs with original
BIOSes, and I need to flash linuxbios into them. The original
BIOS keeps the MAC address in the BIOS flash.

Another point is that I've spent quite a bit of time figuring
out exactly why my networking is screwed and how it would be
possible to move the MAC address definition from the secret
file closer to the particular target configuration and the
person compiling it. The MAC address is not a property of
ck804, it is a property of the mainboard or the target.

Regards,

Roman



From yinghai.lu at amd.com  Wed Feb  7 19:13:28 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Wed, 7 Feb 2007 10:13:28 -0800
Subject: [LinuxBIOS] ck804 romstrap modification
Message-ID: <5986589C150B2F49A46483AC44C7BCA4907422@ssvlexmb2.amd.com>

So you need to scripts for flash
1. get mac address from the legacy bios from flash
2. flash your linuxbios.
3. reprogram you mac address again.

Or conbine 2/3 to update linuxbios image, and flash it if you like.

Late when you like update linuxbios with linuxbios, just use flash util
with execlude command line to keep the mac address.

Good HW design should use serial EEPROM on smbus to preserve the MAC
address instead like s2895.

YH

-----Original Message-----
From: Roman Kononov [mailto:kononov195-lbl at yahoo.com] 
Sent: Wednesday, February 07, 2007 10:02 AM
To: Lu, Yinghai
Cc: LinuxBIOS
Subject: Re: [LinuxBIOS] ck804 romstrap modification

On 02/07/2007 11:35 AM, Lu, Yinghai wrote:
> That is not necessary.
> 
> For the cluster, 
> 1. you need to program mac address for every node at the first time.
> 2. and for the second time, you need to use scripts to preserve the
mac
> address.

Yinghai,

I am not sure that I understand you correctly. I guess, my
patch supposedly makes the step 1 easier.

I have no clusters. I have a number of PCs with original
BIOSes, and I need to flash linuxbios into them. The original
BIOS keeps the MAC address in the BIOS flash.

Another point is that I've spent quite a bit of time figuring
out exactly why my networking is screwed and how it would be
possible to move the MAC address definition from the secret
file closer to the particular target configuration and the
person compiling it. The MAC address is not a property of
ck804, it is a property of the mainboard or the target.

Regards,

Roman







From kononov195-lbl at yahoo.com  Wed Feb  7 19:46:57 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Wed, 07 Feb 2007 12:46:57 -0600
Subject: [LinuxBIOS] ck804 romstrap modification
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA4907422@ssvlexmb2.amd.com>
References: <5986589C150B2F49A46483AC44C7BCA4907422@ssvlexmb2.amd.com>
Message-ID: <45CA1EA1.6040000@yahoo.com>

On 02/07/2007 12:13 PM, Lu, Yinghai wrote:
> So you need to scripts for flash
> 1. get mac address from the legacy bios from flash
> 2. flash your linuxbios.
> 3. reprogram you mac address again.

Thank you for the clarifications.

> Good HW design should use serial EEPROM on smbus to preserve the MAC
> address instead like s2895.

It is not my case. Sun Ultra40 has AT24C64, which has no MAC in
it. This EEPROM looks smbus-unfriendly for it needs 13-bit data
words. In any case, the original BIOSes contain MACs, serial
numbers and other tags.

> -----Original Message-----
> From: Roman Kononov [mailto:kononov195-lbl at yahoo.com] 

> Another point is that I've spent quite a bit of time figuring
> out exactly why my networking is screwed and how it would be
> possible to move the MAC address definition from the secret
> file closer to the particular target configuration and the
> person compiling it. The MAC address is not a property of
> ck804, it is a property of the mainboard or the target.

What do you think about the above stuff?

I panned to modify romstrap.inc and Sun Ultra40 mainboard's
Config.lb, and put that mac_address.h into the target directory
so that a potential user of linuxbios.org would be aware about
all this.

Roman



From yinghai.lu at amd.com  Wed Feb  7 20:09:19 2007
From: yinghai.lu at amd.com (Lu, Yinghai)
Date: Wed, 7 Feb 2007 11:09:19 -0800
Subject: [LinuxBIOS] ck804 romstrap modification
Message-ID: <5986589C150B2F49A46483AC44C7BCA4907424@ssvlexmb2.amd.com>

-----Original Message-----
From: Roman Kononov [mailto:kononov195-lbl at yahoo.com] 
Sent: Wednesday, February 07, 2007 10:47 AM
To: Lu, Yinghai
Cc: LinuxBIOS
Subject: Re: [LinuxBIOS] ck804 romstrap modification

>I panned to modify romstrap.inc and Sun Ultra40 mainboard's
>Config.lb, and put that mac_address.h into the target directory
>so that a potential user of linuxbios.org would be aware about
>all this.

The romstrap.inc is only want to have the fixed postion for MAC in
flash.

You have own romstrap.inc in your MB dir, and update MB Config.lb to
point to it.

YH






From kononov195-lbl at yahoo.com  Wed Feb  7 20:40:30 2007
From: kononov195-lbl at yahoo.com (Roman Kononov)
Date: Wed, 07 Feb 2007 13:40:30 -0600
Subject: [LinuxBIOS] ck804 romstrap modification
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA4907424@ssvlexmb2.amd.com>
References: <5986589C150B2F49A46483AC44C7BCA4907424@ssvlexmb2.amd.com>
Message-ID: <45CA2B2E.9010808@yahoo.com>

On 02/07/2007 01:09 PM, Lu, Yinghai wrote:
> The romstrap.inc is only want to have the fixed postion for MAC in
> flash.
> 
> You have own romstrap.inc in your MB dir, and update MB Config.lb to
> point to it.

This will work too. My objection is that the other magic things from
romstrap.inc would be in at least two places, which is a potential
difficulty.

Roman



From stefan.reinauer at coresystems.de  Wed Feb  7 23:34:57 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Wed, 07 Feb 2007 23:34:57 +0100
Subject: [LinuxBIOS] ck804 romstrap modification
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA4907422@ssvlexmb2.amd.com>
References: <5986589C150B2F49A46483AC44C7BCA4907422@ssvlexmb2.amd.com>
Message-ID: <45CA5411.9010101@coresystems.de>

Lu, Yinghai wrote:
> So you need to scripts for flash
> 1. get mac address from the legacy bios from flash
> 2. flash your linuxbios.
> 3. reprogram you mac address again.
> 
> Or conbine 2/3 to update linuxbios image, and flash it if you like.

Maybe this is a case where we might want to teach that kind of
information to the flashrom utility?

It could detect the ck804, read the required information, and, when a
specific option is set, change the to-be-flashed image on the fly.

> Late when you like update linuxbios with linuxbios, just use flash util
> with execlude command line to keep the mac address.

Most of the flash drivers do "dummy exclusions" right now. Should we try
to fix them up?

> Good HW design should use serial EEPROM on smbus to preserve the MAC
> address instead like s2895.

Good hardware design also uses SCSI instead of IDE, but that does not
always help ;-)


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Thu Feb  8 01:27:03 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 8 Feb 2007 01:27:03 +0100
Subject: [LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
In-Reply-To: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
References: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
Message-ID: <20070208002703.GA22300@greenwood>

Hi,

On Wed, Feb 07, 2007 at 10:31:15AM +0800, bxshi at msik.com.cn wrote:
> Dear all,
> This patch is for MSI K9ND Master Series (ms9282) LinuxBIOS support.
> Thanks very much for Yinghai's great work for MCP55.
> 
> Sign-off-by: Bingxun Shi <bingxunshi at gmail.com>

Great stuff! Thanks a lot for your work!

After a quick review I cannot see any flaws whatsoever: the patch
applies fine, all license headers are there, sign-off is there,
and the code builds fine.

I cannot test on real hardware (I don't have that board), but otherwise
all seems great. If nobody complains, I'll commit this tomorrow.

Thanks again!


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From peilien at yahoo.com  Thu Feb  8 02:10:37 2007
From: peilien at yahoo.com (Perry Wang)
Date: Wed, 7 Feb 2007 17:10:37 -0800
Subject: [LinuxBIOS] Question about PCI Config Space byte rd/wr in HT
In-Reply-To: <20070208002703.GA22300@greenwood>
Message-ID: <mailman.171.1355071059.16123.coreboot@coreboot.org>

Hi,

If software tries to do a byte rd/wr access to PCI config access, say in
linux or BIOS, how would it show up on the HT bus?

I'm assuming that config space access is initiated through the southbridge.
Anyone know if an HT device will ever have to expect byte access to its
config space?

Thanks much,
Perry




From uwe at hermann-uwe.de  Thu Feb  8 02:30:38 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 8 Feb 2007 02:30:38 +0100
Subject: [LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
In-Reply-To: <20070208002703.GA22300@greenwood>
References: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
	<20070208002703.GA22300@greenwood>
Message-ID: <20070208013038.GA4356@greenwood>

On Thu, Feb 08, 2007 at 01:27:03AM +0100, Uwe Hermann wrote:
> > Sign-off-by: Bingxun Shi <bingxunshi at gmail.com>

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Forgot the ack...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Feb  8 02:43:52 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 8 Feb 2007 02:43:52 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <45C8F9D6.5060109@gmx.net>
References: <20070206194821.21747gmx1@mx092.gmx.net> <45C8F9D6.5060109@gmx.net>
Message-ID: <20070208014352.GB4356@greenwood>

On Tue, Feb 06, 2007 at 10:57:42PM +0100, Carl-Daniel Hailfinger wrote:
> Hi!
> 
> svn at openbios.org wrote:
> > Signed-off-by: Adam Kaufman <adam.kaufman at pinnacle.com>
> > Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> > Acked-by: Stefan Reinauer <stepan at coresystems.de>
> > Acked-by: Adam Kaufman <adam.kaufman at pinnacle.com>
> 
> It seems there is still some confusion about Signed-off-by
> and Acked-by. The meaning of Acked-by is a real subset of
> Signed-off-by. So acking a patch you already signed off
> for is totally meaningless and should be avoided. The
> Linux kernel guys never ack and sign off the same patch.

I was going to reply to this, too, but for another reason.
The last 'Acked-by: Adam Kaufman <adam.kaufman at pinnacle.com>'
was not posted publically by Adam anywhere as far as I can
see, so it should not appear in the commit message.

As for the meaning of Acked-by, I'm not so sure. We currently use
Signed-off-by as a tagging of "I wrote (parts of) this code"
(i.e. is has legal importance), and the Acked-by merely as
"ok, looks fine" indicator (but you didn't write the code).

Not sure how exactly the Linux kernel folks use these...

Sample scenario: Developer A posts a patch with a Signed-off-by,
you (developer B) modify/improve it and add your own Signed-off-by.

Then someone else (developer C) improves the patch even further, and
adds his Signed-off-by. Now you (B) post an Acked-by for this last
revision of the patch, i.e.

Signed-off-by: A
Signed-off-by: B
Signed-off-by: C
Acked-by: B

This makes sense to me. What would probably _not_ make any sense is

Signed-off-by: A
Signed-off-by: B
Acked-by: B

because you ack your own patch here, which defeats our purpose of the
Acked-by tag (enforce review by at least one developer).

Also, I don't think that a Signed-off-by necessarily means that you
ack the patch. It's possible that you just posted an improved version
of the patch (and added your Signed-off-by), but you still think that
it's not good enough to be committed, i.e. you don't want to ack it
at the moment...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stefan.reinauer at coresystems.de  Thu Feb  8 10:18:58 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Thu, 08 Feb 2007 10:18:58 +0100
Subject: [LinuxBIOS] Probable fix for gcc4 builds
In-Reply-To: <efe7343f0702070148q5d83263bxb3b6963f1e871200@mail.gmail.com>
References: <efe7343f0702070148q5d83263bxb3b6963f1e871200@mail.gmail.com>
Message-ID: <45CAEB02.4040905@coresystems.de>

Luis Correia wrote:
> Hi!
> 
> this is completely untested!
> 
> I got this hint from the syslinux mailing list regarding building on
> newer distros, maybe this helps building linuxbios.
> 
> For newer distro's (like ubuntu 6.10, FC5+), syslinux build fails due to
> gcc 4. Here is a patch to get it to build properly.
> 
> The only thing it does is add -fno-stack-protection to CFLAGS in all the
> Makefiles.
> 
> Source: (Ram Yalamanchili)
> 
> 
> Luis


It seems, there is no patch.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From luis.f.correia at gmail.com  Thu Feb  8 10:36:26 2007
From: luis.f.correia at gmail.com (Luis Correia)
Date: Thu, 8 Feb 2007 09:36:26 +0000
Subject: [LinuxBIOS] Probable fix for gcc4 builds
In-Reply-To: <45CAEB02.4040905@coresystems.de>
References: <efe7343f0702070148q5d83263bxb3b6963f1e871200@mail.gmail.com>
	<45CAEB02.4040905@coresystems.de>
Message-ID: <efe7343f0702080136w545d6bb7n97a30673ef527cca@mail.gmail.com>

Yes, you're right, there is no patch.

I'm no expert with messing around with Makefiles, hence the hint to add
"-fno-stack-protection" to CFLAGS in all the Makefiles.

Sorry for that, i'm now busy with other projects. I'll return soon to linux
bios development as I need to finish the NOVA board support.

Luis Correia


On 2/8/07, Stefan Reinauer <stefan.reinauer at coresystems.de> wrote:
>
> Luis Correia wrote:
> > Hi!
> >
> > this is completely untested!
> >
> > I got this hint from the syslinux mailing list regarding building on
> > newer distros, maybe this helps building linuxbios.
> >
> > For newer distro's (like ubuntu 6.10, FC5+), syslinux build fails due to
> > gcc 4. Here is a patch to get it to build properly.
> >
> > The only thing it does is add -fno-stack-protection to CFLAGS in all the
> > Makefiles.
> >
> > Source: (Ram Yalamanchili)
> >
> >
> > Luis
>
>
> It seems, there is no patch.
>
> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
>
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From sayoji at linuxmail.org  Thu Feb  8 12:47:53 2007
From: sayoji at linuxmail.org (Ana Vasan)
Date: Thu, 08 Feb 2007 19:47:53 +0800
Subject: [LinuxBIOS] Error : Payload FILO
Message-ID: <20070208114753.416AD4387B@ws5-1.us4.outblaze.com>

Hi,
  I am newbie to LinuxBIOS. 
Hardware Configuration: 
   Mother Board : Tyan S2882
   BIOS Chip    : American Metagrends
   Hard Drive   : SATA

I am following the steps mentioned in the following link.
      http://linuxbios.org/Tyan_S2882_Build_Tutorial

I am facing an issue in Payload. FILO Version - 0.5. When I changed the Config file and make, i get the following error.

Makefile:63: warning: overriding commands for target `clean'
makerules:46: warning: ignoring old commands for target `clean'
echo '#define PROGRAM_NAME "FILO"' > main/version.h
echo '#define PROGRAM_VERSION "0.5 (root at LinuxBIOS) Thu Feb  8 17:00:48 IST 2007"' >> main/version.h
make -C main
make[1]: Entering directory `/root/filo-0.5/main'
/bin/echo -e '/* GENERATED FILE, DO NOT EDIT */\n' >../config.h
sed -e 's/#.*//' -e '/=/!d' -e 's/\([^[:space:]]*\)[[:space:]]*=[[:space:]]*\(.*\).*/#define \1 \2/' -e 's/^#define \([^ ]*\) 0$/#undef \1/' ../Config >>../config.h
gcc -m32 -Wall -Os -fomit-frame-pointer -fno-common -ffreestanding -fno-strict-aliasing -Wno-pointer-sign -Wno-unused  -nostdinc -imacros ../config.h -I../include -I/usr/lib/gcc/i386-redhat-linux/3.4.5/include -MD -c filo.c -o filo.o
cc1: error: unrecognized command line option "-Wno-pointer-sign"
make[1]: *** [filo.o] Error 1
make[1]: Leaving directory `/root/filo-0.5/main'
make: *** [main/builtin.o] Error 2

Please help me in resolving it.
Sayoji









=
Equipos de Acabado
Royo Machinery supplies an ample range of automatic die cutters, box folder gluers, UV machines, laminators, corrugated board lines, etc.
http://a8-asy.a8ww.net/a8-ads/adftrclick?redirectid=b29bfd1a5db81ff9714b9298c640e606


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From stepan at coresystems.de  Thu Feb  8 12:53:52 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 8 Feb 2007 12:53:52 +0100
Subject: [LinuxBIOS] Error : Payload FILO
In-Reply-To: <20070208114753.416AD4387B@ws5-1.us4.outblaze.com>
References: <20070208114753.416AD4387B@ws5-1.us4.outblaze.com>
Message-ID: <20070208115351.GA18437@coresystems.de>

* Ana Vasan <sayoji at linuxmail.org> [070208 12:47]:
> cc1: error: unrecognized command line option "-Wno-pointer-sign"
> make[1]: *** [filo.o] Error 1
> make[1]: Leaving directory `/root/filo-0.5/main'
> make: *** [main/builtin.o] Error 2
> 
> Please help me in resolving it.
> Sayoji

Please update your gcc or remove "-Wno-pointer-sign" from 
makerules.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Fri Feb  9 01:26:10 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  9 Feb 2007 01:26:10 +0100
Subject: [LinuxBIOS] r2552 - in trunk/LinuxBIOSv2: src/mainboard/msi
	src/mainboard/msi/ms9282 targets/msi targets/msi/ms9282
Message-ID: <mailman.172.1355071059.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-02-09 01:26:10 +0100 (Fri, 09 Feb 2007)
New Revision: 2552

Added:
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/chip.h
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cmos.layout
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/failover.c
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/get_bus_conf.c
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/irq_tables.c
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mainboard.c
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mb_sysconf.h
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mptable.c
   trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/resourcemap.c
   trunk/LinuxBIOSv2/targets/msi/ms9282/
   trunk/LinuxBIOSv2/targets/msi/ms9282/Config.lb
Log:
Add support for the MSI K9ND Master Series (ms9282) board.

Signed-off-by: Bingxun Shi <bingxunshi at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Config.lb	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,418 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2006 AMD
+## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+##
+## Copyright (C) 2006 MSI
+## Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+       default ROM_SECTION_SIZE   = FALLBACK_SIZE
+       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+       default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD     = 1
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#dir /drivers/ati/ragexl
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+end
+
+else
+
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
+
+##
+## Romcc output
+##
+makerule ./failover.E
+        depends "$(MAINBOARD)/failover.c ./romcc"
+        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+        depends "$(MAINBOARD)/failover.c ./romcc"
+        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E
+        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+       if CONFIG_USE_INIT
+               ldscript /cpu/x86/32bit/entry32.lds
+       end
+
+       if CONFIG_USE_INIT
+               ldscript      /cpu/amd/car/cache_as_ram.lds
+       end
+end
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+       mainboardinit cpu/x86/16bit/reset16.inc
+       ldscript /cpu/x86/16bit/reset16.lds
+else
+       mainboardinit cpu/x86/32bit/reset32.inc
+       ldscript /cpu/x86/32bit/reset32.lds
+end
+
+if USE_DCACHE_RAM
+else
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit southbridge/nvidia/mcp55/id.inc
+ldscript /southbridge/nvidia/mcp55/id.lds
+
+##
+## ROMSTRAP table for MCP55
+##
+if USE_FALLBACK_IMAGE
+       mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+       ldscript /southbridge/nvidia/mcp55/romstrap.lds
+end
+
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+       mainboardinit ./failover.inc
+end
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+# ROMCC
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+end
+
+##
+## Include the secondary Configuration files
+##
+if CONFIG_CHIP_NAME
+        config chip.h
+end
+
+
+# sample config for msi/ms9282
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+
+       device pci_domain 0 on
+               chip northbridge/amd/amdk8 #mc0
+                       device pci 18.0 on #  northbridge
+                               #  devices on link 0, link 0 == LDT 0
+                               chip southbridge/nvidia/mcp55
+                                       device pci 0.0 on end   # HT
+                                       device pci 1.0 on # LPC
+                                               chip superio/winbond/w83627ehg
+                                                       device pnp 2e.0 on #  Floppy
+                                                               io 0x60 = 0x3f0
+                                                               irq 0x70 = 6
+                                                               drq 0x74 = 2
+                                                       end
+                                                       device pnp 2e.1 off #  Parallel Port
+                                                               io 0x60 = 0x378
+                                                               irq 0x70 = 7
+                                                       end
+                                                       device pnp 2e.2 on #  Com1
+                                                               io 0x60 = 0x3f8
+                                                               irq 0x70 = 4
+                                                       end
+                                                       device pnp 2e.3 off #  Com2
+                                                               io 0x60 = 0x2f8
+                                                               irq 0x70 = 3
+                                                       end
+                                                       device pnp 2e.5 on #  Keyboard
+                                                               io 0x60 = 0x60
+                                                               io 0x62 = 0x64
+                                                               irq 0x70 = 1
+                                                               irq 0x72 = 12
+                                                       end
+                                                       device pnp 2e.6 off #  SERIAL_FALSH
+                                                               io 0x60 = 0x100
+                                                       end
+                                                       device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                                                               io 0x60 = 0x220
+                                                               io 0x62 = 0x300
+                                                               irq 0x70 = 9
+                                                       end
+                                                       device pnp 2e.8 off end #  WDTO_PLED
+                                                       device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
+                                                       device pnp 2e.a off end #  ACPI
+                                                       device pnp 2e.b on #  HW Monitor
+                                                               io 0x60 = 0x290
+                                                               irq 0x70 = 5
+                                                       end
+                                               end
+                                       end
+                                        device pci 1.1 on # SM 0
+                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+                                                       device i2c 70 on  #0 pca9554 1
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                       end
+                                                       device i2c 70 on  #0 pca9554 2
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                       end
+                                               end
+                                       end
+                                       device pci 1.1 on # SM 1
+                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+                                                       device i2c 72 on     #pca9554 channle1
+                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                                       device i2c 72 on     #pca9545 channel 2
+                                                               chip drivers/i2c/adm1027   #HWM ADT7463
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                                       device i2c 72 on end  #pca9545 channel 3
+                                                       device i2c 72 on      #pca9545 channel 4
+                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                               end
+                                       end
+
+                                       device pci 2.0 on end # USB 1.1
+                                       device pci 2.1 on end # USB 2
+                                       device pci 4.0 on  end # IDE
+                                               device pci 5.0 on  end # SATA 0
+                                       device pci 5.1 on  end # SATA 1
+                                       device pci 5.2 on  end # SATA 2
+                                       device pci 6.0 on  #P2P
+                                               chip drivers/pci/onboard
+                                                       device pci 4.0 on end
+                                                       register "rom_address" = "0xfff80000"
+                                               end
+                                       end # P2P
+                                       device pci 7.0 on end # reserve
+                                       device pci 8.0 on end # MAC0
+                                       device pci 9.0 on end # MAC1
+                                       device pci a.0 on
+                                               device pci 0.0 on
+                                                       chip drivers/pci/onboard
+                                                               device pci 4.0 on end  #pci_E lan1
+                                                               device pci 4.1 on end  #pci_E lan2
+                                                       end
+                                               end
+                                       end # 0x376
+                                               device pci b.0 on  end # PCI E 0x374
+                                       device pci c.0 on  end
+                                       device pci d.0 on   #SAS
+                                               chip drivers/pci/onboard
+                                                       device pci 0.0 on end
+                                               end
+                                       end # PCI E 1 0x378
+                                       device pci e.0 on end # PCI E 0 0x375
+                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
+                                       register "ide0_enable" = "1"
+                                       register "ide1_enable" = "1"
+                                       register "sata0_enable" = "1"
+                                       register "sata1_enable" = "1"
+                               end
+                       end #  device pci 18.0
+                       device pci 18.0 on end # Link 1
+                       device pci 18.0 on end
+                       device pci 18.1 on end
+                       device pci 18.2 on end
+                       device pci 18.3 on end
+               end #mc0
+
+       end # pci_domain
+
+#        chip drivers/generic/debug
+#                device pnp 0.0 off end
+#                device pnp 0.1 off end
+#                device pnp 0.2 off end
+#                device pnp 0.3 off end
+#                device pnp 0.4 off end
+#              device pnp 0.5 on end
+#        end
+end # root_complex

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Options.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/Options.lb	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,309 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2006 AMD
+## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+##
+## Copyright (C) 2006 MSI
+## Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+#bx_b005+
+uses SB_HT_CHAIN_ON_BUS0
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+#512K bytes
+default ROM_SIZE=524288
+
+#1M bytes
+#bx- default ROM_SIZE=1048576
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+#CHIP_NAME ?
+#default CONFIG_CHIP_NAME=1
+
+#1G memory hole
+#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0
+
+#make the SB HT chain on bus 0, default is not (0)
+#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
+
+##bx_b005+ make the SB HT chain on bus 0
+default SB_HT_CHAIN_ON_BUS0=1
+
+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#VGA
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcc000
+default DCACHE_RAM_SIZE=0x4000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
+
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="ms9282"
+default MAINBOARD_VENDOR="MSI"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cache_as_ram_auto.c	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,296 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 1
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#define DEBUG_SMBUS 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+       #include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
+
+#include <device/pci_ids.h>
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+#define SMBUS_SWITCH1 0x70
+#define SMBUS_SWITCH2 0x72
+        unsigned device=(ctrl->channel0[0])>>8;
+        smbus_send_byte(SMBUS_SWITCH1, device);
+       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+}
+
+#if 0
+static inline void change_i2c_mux(unsigned device)
+{
+#define SMBUS_SWITCH1 0x70
+#define SMBUS_SWITHC2 0x72
+        smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
+       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+}
+#endif
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+       return smbus_read_byte(device, address);
+}
+
+//#define K8_4RANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+ /* msi does not want the default */
+#include "resourcemap.c"
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define MCP55_NUM 1
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+//set GPIO to input mode
+#define MCP55_MB_SETUP \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+        uint32_t dword;
+        uint8_t byte;
+
+        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20;
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+        dword |= (1<<0);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+
+
+}
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        sio_setup();
+
+        /* Setup the mcp55 */
+        mcp55_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+       ;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
+#define RC0 (2<<8)
+#define RC1 (1<<8)
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+       static const uint16_t spd_addr [] = {
+                       RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
+                       RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+                       RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
+                       RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+#endif
+       };
+
+       unsigned bsp_apicid = 0;
+        int needs_reset;
+       struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+       char *p ;
+
+        if (bist == 0) {
+               //init_cpus(cpu_init_detectedx);
+               bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+       w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
+        setup_ms9282_resource_map();
+
+       setup_coherent_ht_domain();
+
+        wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        start_other_cores();
+        //wait_all_other_cores_started(bsp_apicid);
+#endif
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+       needs_reset = optimize_link_coherent_ht();
+
+       needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+        needs_reset |= mcp55_early_setup_x();
+
+               if (needs_reset) {
+                       print_info("ht reset -\r\n");
+                       soft_reset();
+               }
+
+        //It's the time to set ctrl now;
+        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+       enable_smbus();
+
+#if 0
+        int i;
+        for(i=4;i<8;i++) {
+                change_i2c_mux(i);
+                dump_smbus_registers();
+        }
+#endif
+
+       memreset_setup();
+
+       sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+       post_cache_as_ram();
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/chip.h	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_msi_ms9282_ops;
+
+struct mainboard_msi_ms9282_config {
+       int fixup_scsi;
+       int fixup_vga;
+};

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cmos.layout
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cmos.layout	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/cmos.layout	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/failover.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/failover.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/failover.c	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/mc146818rtc_early.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+       uint32_t dword;
+       uint8_t byte;
+
+        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20;
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+
+       dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+       dword |= (1<<0);
+       pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+
+
+}
+
+#if CONFIG_LOGICAL_CPUS==1
+#include "cpu/amd/dualcore/dualcore_id.c"
+#endif
+
+static unsigned long main(unsigned long bist)
+{
+        /* Make cerain my local apic is useable */
+        enable_lapic();
+
+        /* Is this a cpu only reset? */
+        if (early_mtrr_init_detected()) {
+               if (last_boot_normal()) {
+                       goto normal_image;
+               } else {
+                       goto fallback_image;
+               }
+       }
+
+       /* Is this a secondary cpu? */
+       if (!boot_cpu()) {
+               if (last_boot_normal()) {
+                       goto normal_image;
+               } else {
+                       goto fallback_image;
+               }
+       }
+
+       /* Nothing special needs to be done to find bus 0 */
+       /* Allow the HT devices to be found */
+
+       enumerate_ht_chain();
+
+       sio_setup();
+
+       /* Setup the mcp55 */
+       mcp55_enable_rom();
+
+       /* Is this a deliberate reset by the bios */
+       if (bios_reset_detected() && last_boot_normal()) {
+               goto normal_image;
+       }
+       /* This is the primary cpu how should I boot? */
+       else if (do_normal_boot()) {
+               goto normal_image;
+       }
+       else {
+               goto fallback_image;
+       }
+ normal_image:
+       asm volatile ("jmp __normal_image"
+               : /* outputs */
+               : "a" (bist) /* inputs */
+               : /* clobbers */
+               );
+ fallback_image:
+       return bist;
+}

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/get_bus_conf.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/get_bus_conf.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/get_bus_conf.c	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+struct mb_sysconf_t mb_sysconf;
+
+unsigned pci1234x[] =
+{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+        //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+        0x0000ff0,
+        0x0000ff0,
+        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0
+};
+unsigned hcdnx[] =
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+       0x20202020,
+       0x20202020,
+        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+};
+
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+static unsigned get_hcid(unsigned i)
+{
+        unsigned id = 0;
+
+        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+
+        unsigned devn = sysconf.hcdn[i] & 0xff;
+
+        device_t dev;
+
+        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+
+        switch (dev->device) {
+        case 0x0369: //IO55
+                id = 4;
+                break;
+        }
+
+        // we may need more way to find out hcid: subsystem id? GPIO read ?
+
+        // we need use id for 1. bus num, 2. mptable, 3. acpi table
+
+        return id;
+}
+
+void get_bus_conf(void)
+{
+
+       unsigned apicid_base;
+       struct mb_sysconf_t *m;
+
+        device_t dev;
+        int i, j;
+
+        if(get_bus_conf_done==1) return; //do it only once
+
+        get_bus_conf_done = 1;
+
+       sysconf.mb = &mb_sysconf;
+
+       m = sysconf.mb;
+       memset(m, 0, sizeof(struct mb_sysconf_t));
+
+        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        for(i=0;i<sysconf.hc_possible_num; i++) {
+                sysconf.pci1234[i] = pci1234x[i];
+                sysconf.hcdn[i] = hcdnx[i];
+        }
+
+        get_sblk_pci1234();
+
+       sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+
+       m->bus_type[0] = 1; //pci
+
+       m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+
+                /* MCP55 */
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+                if (dev) {
+                        m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+                }
+
+               for(i=2; i<8;i++) {
+                       dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+                       if (dev) {
+                               m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                       }
+                       else {
+                               printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+                       }
+               }
+
+       for(i=0; i< sysconf.hc_possible_num; i++) {
+               if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
+               for (j = busn; j <= busn_max; j++)
+                       m->bus_type[j] = 1;
+               if(m->bus_isa <= busn_max)
+                       m->bus_isa = busn_max + 1;
+               printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+       }
+
+
+
+/*I/O APICs:   APIC ID Version State           Address*/
+#if CONFIG_LOGICAL_CPUS==1
+       apicid_base = get_apicid_base(1);
+#else
+       apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+       m->apicid_mcp55 = apicid_base+0;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/irq_tables.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/irq_tables.c	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify!
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+#include "mb_sysconf.h"
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+               uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+               uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus;
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+       struct irq_routing_table *pirq;
+       struct irq_info *pirq_info;
+       unsigned slot_num;
+       uint8_t *v;
+       struct mb_sysconf_t *m;
+       unsigned sbdn;
+
+        uint8_t sum=0;
+        int i;
+
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+       sbdn = sysconf.sbdn;
+       m = sysconf.mb;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+       pirq = (void *)(addr);
+       v = (uint8_t *)(addr);
+
+       pirq->signature = PIRQ_SIGNATURE;
+       pirq->version  = PIRQ_VERSION;
+
+       pirq->rtr_bus = m->bus_mcp55[0];
+       pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+
+       pirq->exclusive_irqs = 0;
+
+       pirq->rtr_vendor = 0x10de;
+       pirq->rtr_device = 0x0370;
+
+       pirq->miniport_data = 0;
+
+       memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+       pirq_info = (void *) ( &pirq->checksum + 1);
+       slot_num = 0;
+//pci bridge
+       write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+       pirq_info++; slot_num++;
+
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+                if(!(sysconf.pci1234[i] & 0x1) ) continue;
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned devn = sysconf.hcdn[i] & 0xff;
+
+                write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+                pirq_info++; slot_num++;
+       }
+
+       pirq->size = 32 + 16 * slot_num;
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];
+
+       sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+       printk_info("done.\n");
+
+       return  (unsigned long) pirq_info;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mainboard.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mainboard.c	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_tyan_ms9282_ops = {
+       CHIP_NAME("MSI ms9282 mainboard")
+};
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mb_sysconf.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mb_sysconf.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mb_sysconf.h	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned apicid_mcp55;
+       unsigned bus_type[256];
+
+};
+
+#endif
+

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mptable.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/mptable.c	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "MSI    ";
+        static const char productid[12] = "MS9282       ";
+        struct mp_config_table *mc;
+       struct mb_sysconf_t *m;
+       unsigned sbdn;
+
+       int i,j;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+       get_bus_conf();
+       sbdn = sysconf.sbdn;
+       m = sysconf.mb;
+
+/*Bus:         Bus ID  Type*/
+       /* define bus and isa numbers */
+        for(j= 0; j < 256 ; j++) {
+               if(m->bus_type[j])
+                        smp_write_bus(mc, j, "PCI   ");
+        }
+        smp_write_bus(mc, m->bus_isa, "ISA   ");
+
+/*I/O APICs:   APIC ID Version State           Address*/
+        {
+                device_t dev;
+               struct resource *res;
+               uint32_t dword;
+
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                if (dev) {
+                       res = find_resource(dev, PCI_BASE_ADDRESS_1);
+                       if (res) {
+                               smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+                       }
+
+                       dword = 0x43c6c643;
+                       pci_write_config32(dev, 0x7c, dword);
+
+                       dword = 0x81001a00;
+                       pci_write_config32(dev, 0x80, dword);
+
+                       dword = 0xd00002d2;
+                       pci_write_config32(dev, 0x84, dword);
+
+                }
+
+
+       }
+
+                  /*I/O Ints:  Type    Polarity    Trigger                     Bus ID   IRQ    APIC ID PIN# */
+       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
+       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
+
+//SMBUS
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
+
+//USB1.1
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
+
+//USB2.0
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+//SATA1
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
+
+//SATA2
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+//SATA3
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
+
+//NIC1
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
+//NIC2
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
+
+       for(j=7; j>=2; j--) {
+               if(!m->bus_mcp55[j]) continue;
+               for(i=0;i<4;i++) {
+                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+               }
+       }
+
+       for(j=0; j<1; j++)
+               for(i=0;i<4;i++) {
+                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
+               }
+
+/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
+       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+       smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+       /* There is no extension information... */
+
+       /* Compute the checksums */
+       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+       printk_debug("Wrote the mp table end at: %p - %p\n",
+               mc, smp_next_mpe_entry(mc));
+       return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+       void *v;
+       v = smp_write_floating_table(addr);
+       return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/resourcemap.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/resourcemap.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms9282/resourcemap.c	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2003 Stefan Reinauer <stepan at coresystems.de>
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * MSI ms9282 needs a different resource map
+ *
+ */
+
+static void setup_ms9282_resource_map(void)
+{
+       static const unsigned int register_values[] = {
+#if 1
+               /* Careful set limit registers before base registers which contain the enables */
+               /* DRAM Limit i Registers
+                * F1:0x44 i = 0
+                * F1:0x4C i = 1
+                * F1:0x54 i = 2
+                * F1:0x5C i = 3
+                * F1:0x64 i = 4
+                * F1:0x6C i = 5
+                * F1:0x74 i = 6
+                * F1:0x7C i = 7
+                * [ 2: 0] Destination Node ID
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 7: 3] Reserved
+                * [10: 8] Interleave select
+                *         specifies the values of A[14:12] to use with interleave enable.
+                * [15:11] Reserved
+                * [31:16] DRAM Limit Address i Bits 39-24
+                *         This field defines the upper address bits of a 40 bit  address
+                *         that define the end of the DRAM region.
+                */
+               PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+               PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+               PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+               PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+               PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+               PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+               PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+               /* DRAM Base i Registers
+                * F1:0x40 i = 0
+                * F1:0x48 i = 1
+                * F1:0x50 i = 2
+                * F1:0x58 i = 3
+                * F1:0x60 i = 4
+                * F1:0x68 i = 5
+                * F1:0x70 i = 6
+                * F1:0x78 i = 7
+                * [ 0: 0] Read Enable
+                *         0 = Reads Disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes Disabled
+                *         1 = Writes Enabled
+                * [ 7: 2] Reserved
+                * [10: 8] Interleave Enable
+                *         000 = No interleave
+                *         001 = Interleave on A[12] (2 nodes)
+                *         010 = reserved
+                *         011 = Interleave on A[12] and A[14] (4 nodes)
+                *         100 = reserved
+                *         101 = reserved
+                *         110 = reserved
+                *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+                * [15:11] Reserved
+                * [13:16] DRAM Base Address i Bits 39-24
+                *         This field defines the upper address bits of a 40-bit address
+                *         that define the start of the DRAM region.
+                */
+               PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+#endif
+#if 1
+
+               /* Memory-Mapped I/O Limit i Registers
+                * F1:0x84 i = 0
+                * F1:0x8C i = 1
+                * F1:0x94 i = 2
+                * F1:0x9C i = 3
+                * F1:0xA4 i = 4
+                * F1:0xAC i = 5
+                * F1:0xB4 i = 6
+                * F1:0xBC i = 7
+                * [ 2: 0] Destination Node ID
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 3: 3] Reserved
+                * [ 5: 4] Destination Link ID
+                *         00 = Link 0
+                *         01 = Link 1
+                *         10 = Link 2
+                *         11 = Reserved
+                * [ 6: 6] Reserved
+                * [ 7: 7] Non-Posted
+                *         0 = CPU writes may be posted
+                *         1 = CPU writes must be non-posted
+                * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+                *         This field defines the upp adddress bits of a 40-bit address that
+                *         defines the end of a memory-mapped I/O region n
+                */
+               PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+//             PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+               /* Memory-Mapped I/O Base i Registers
+                * F1:0x80 i = 0
+                * F1:0x88 i = 1
+                * F1:0x90 i = 2
+                * F1:0x98 i = 3
+                * F1:0xA0 i = 4
+                * F1:0xA8 i = 5
+                * F1:0xB0 i = 6
+                * F1:0xB8 i = 7
+                * [ 0: 0] Read Enable
+                *         0 = Reads disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes disabled
+                *         1 = Writes Enabled
+                * [ 2: 2] Cpu Disable
+                *         0 = Cpu can use this I/O range
+                *         1 = Cpu requests do not use this I/O range
+                * [ 3: 3] Lock
+                *         0 = base/limit registers i are read/write
+                *         1 = base/limit registers i are read-only
+                * [ 7: 4] Reserved
+                * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+                *         This field defines the upper address bits of a 40bit address
+                *         that defines the start of memory-mapped I/O region i
+                */
+               PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+//             PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+#endif
+#if 1
+
+               /* PCI I/O Limit i Registers
+                * F1:0xC4 i = 0
+                * F1:0xCC i = 1
+                * F1:0xD4 i = 2
+                * F1:0xDC i = 3
+                * [ 2: 0] Destination Node ID
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 3: 3] Reserved
+                * [ 5: 4] Destination Link ID
+                *         00 = Link 0
+                *         01 = Link 1
+                *         10 = Link 2
+                *         11 = reserved
+                * [11: 6] Reserved
+                * [24:12] PCI I/O Limit Address i
+                *         This field defines the end of PCI I/O region n
+                * [31:25] Reserved
+                */
+               PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+               PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+               /* PCI I/O Base i Registers
+                * F1:0xC0 i = 0
+                * F1:0xC8 i = 1
+                * F1:0xD0 i = 2
+                * F1:0xD8 i = 3
+                * [ 0: 0] Read Enable
+                *         0 = Reads Disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes Disabled
+                *         1 = Writes Enabled
+                * [ 3: 2] Reserved
+                * [ 4: 4] VGA Enable
+                *         0 = VGA matches Disabled
+                *         1 = matches all address < 64K and where A[9:0] is in the
+                *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+                * [ 5: 5] ISA Enable
+                *         0 = ISA matches Disabled
+                *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+                *             from matching agains this base/limit pair
+                * [11: 6] Reserved
+                * [24:12] PCI I/O Base i
+                *         This field defines the start of PCI I/O region n
+                * [31:25] Reserved
+                */
+               PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+               PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+#endif
+               /* Config Base and Limit i Registers
+                * F1:0xE0 i = 0
+                * F1:0xE4 i = 1
+                * F1:0xE8 i = 2
+                * F1:0xEC i = 3
+                * [ 0: 0] Read Enable
+                *         0 = Reads Disabled
+                *         1 = Reads Enabled
+                * [ 1: 1] Write Enable
+                *         0 = Writes Disabled
+                *         1 = Writes Enabled
+                * [ 2: 2] Device Number Compare Enable
+                *         0 = The ranges are based on bus number
+                *         1 = The ranges are ranges of devices on bus 0
+                * [ 3: 3] Reserved
+                * [ 6: 4] Destination Node
+                *         000 = Node 0
+                *         001 = Node 1
+                *         010 = Node 2
+                *         011 = Node 3
+                *         100 = Node 4
+                *         101 = Node 5
+                *         110 = Node 6
+                *         111 = Node 7
+                * [ 7: 7] Reserved
+                * [ 9: 8] Destination Link
+                *         00 = Link 0
+                *         01 = Link 1
+                *         10 = Link 2
+                *         11 - Reserved
+                * [15:10] Reserved
+                * [23:16] Bus Number Base i
+                *         This field defines the lowest bus number in configuration region i
+                * [31:24] Bus Number Limit i
+                *         This field defines the highest bus number in configuration region i
+                */
+#if 1
+//             PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
+//             PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
+               PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+               PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+#endif
+
+       };
+
+       int max;
+       max = sizeof(register_values)/sizeof(register_values[0]);
+       setup_resource_map(register_values, max);
+}
+

Added: trunk/LinuxBIOSv2/targets/msi/ms9282/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/msi/ms9282/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/msi/ms9282/Config.lb	2007-02-09 00:26:10 UTC (rev 2552)
@@ -0,0 +1,91 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2006 MSI
+## Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target ms9282
+mainboard msi/ms9282
+
+romimage "normal"
+#       48K for SCSI FW
+#        option ROM_SIZE = 475136
+       option ROM_SIZE = 512*1024-36*1024
+#      option ROM_SIZE = 524288
+#       48K for SCSI FW and 48K for ATI ROM
+#       option ROM_SIZE = 425984
+#       64K for Etherboot
+#        option ROM_SIZE = 458752
+       option USE_FALLBACK_IMAGE=0
+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x18800
+       option ROM_IMAGE_SIZE=0x20000
+#      option ROM_IMAGE_SIZE=0x15800
+       option XIP_ROM_SIZE=0x40000
+       option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#      payload ../../../payloads/tg3.zelf
+#      payload ../../../../payloads/tg3_vga.zelf
+#      payload /filo.elf
+       payload /tg3--filo.elf
+#      payload /payload
+#      payload ../../../../payloads/e1000_vga.zelf
+#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#      payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+romimage "fallback"
+       option USE_FALLBACK_IMAGE=1
+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x19800
+       option ROM_IMAGE_SIZE=0x20000
+#      option ROM_IMAGE_SIZE=0x15800
+       option XIP_ROM_SIZE=0x40000
+       option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#      payload ../../../payloads/tg3.zelf
+#      payload ../../../../payloads/tg3_vga.zelf
+#      payload ../../../../payloads/memtest
+#      payload ../../../../payloads/e1000_vga.zelf
+#      payload ../../../../payloads/filo_hda.zelf
+#      payload /filo.elf
+       payload /tg3--filo.elf
+#      payload /payload
+#      payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#      payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#      payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+buildrom ./ms9282.lxb ROM_SIZE "normal" "fallback"




From uwe at hermann-uwe.de  Fri Feb  9 01:27:11 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 9 Feb 2007 01:27:11 +0100
Subject: [LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
In-Reply-To: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
References: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
Message-ID: <20070209002711.GA28072@greenwood>

On Wed, Feb 07, 2007 at 10:31:15AM +0800, bxshi at msik.com.cn wrote:
> This patch is for MSI K9ND Master Series (ms9282) LinuxBIOS support.

Committed, thanks!


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From bxshi at msik.com.cn  Fri Feb  9 01:28:25 2007
From: bxshi at msik.com.cn (bxshi)
Date: Fri, 9 Feb 2007 08:28:25 +0800
Subject: [LinuxBIOS] =?gb2312?b?tPC4tDogIFtQQVRDSF0gTVNJIG1zOTI4MiBMaW51?=
 =?gb2312?b?eEJJT1Mgc3VwcG9ydA==?=
In-Reply-To: <20070209002711.GA28072@greenwood>
Message-ID: <MAIL2003ZFCil5r51sX0000eb0e@mail.msikmail.com>


>Committed, thanks!

Thank you!
bxshi



*****CONFIDENTIAL INFORMATION*****

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From info at coresystems.de  Fri Feb  9 02:05:36 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 09 Feb 2007 02:05:36 +0100
Subject: [LinuxBIOS] r2552 build service
Message-ID: <E1HFKCm-0008T2-8V@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2552 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Add support for the MSI K9ND Master Series (ms9282) board.

Signed-off-by: Bingxun Shi <bingxunshi at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Configuration of msi:ms9282 is still broken


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From sayoji at linuxmail.org  Fri Feb  9 05:10:53 2007
From: sayoji at linuxmail.org (Sayoji Siv)
Date: Fri, 09 Feb 2007 12:10:53 +0800
Subject: [LinuxBIOS] Error : Payload FILO
Message-ID: <20070209041053.BC1657ACFB@ws5-10.us4.outblaze.com>

Hi,
 Thanks. I have removed "-Wno-pointer-sign" and now it is working.
I hav another doubt. I am not yet clear about Disk On Chip.

 The BIOS chip in Tyan s2882 board is AMI BIOS B25 4665 and the Disk On Chip i am having is Transcend 40 pin IDE Flash.

Will the both chips will be compatible or is there any specific Disk On Chip for this board ?
Is BIOS savior is required ? If not, how to swap the chip and proceed.

Thanks for any help,
Sayoji



 

> Please update your gcc or remove "-Wno-pointer-sign" from
> makerules.
> 
> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>        Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/

>


=
Quality Business Cards 250 for $16.99
250 full-color. No photo upload fee. Fast, low-cost shipping. Horizontal or vertical. Raised or flat ink. Second-side printing option.
http://a8-asy.a8ww.net/a8-ads/adftrclick?redirectid=0868388e6ada5d8a3b89b652301fe1f7


-- 
Powered by Outblaze



From segher at kernel.crashing.org  Fri Feb  9 18:26:09 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 9 Feb 2007 18:26:09 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070208014352.GB4356@greenwood>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
Message-ID: <1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>

> As for the meaning of Acked-by, I'm not so sure. We currently use
> Signed-off-by as a tagging of "I wrote (parts of) this code"
> (i.e. is has legal importance), and the Acked-by merely as
> "ok, looks fine" indicator (but you didn't write the code).

Signed-off-by means "I am (in part) responsible for this
ending up in thid repo", i.e., you wrote part of the patch
or you were on the path pushing it in.

> Not sure how exactly the Linux kernel folks use these...

Acked-by is used as a comment "looks fine by me" when not
taking direct action yourself.


Segher




From segher at kernel.crashing.org  Fri Feb  9 18:31:40 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 9 Feb 2007 18:31:40 +0100
Subject: [LinuxBIOS] Probable fix for gcc4 builds
In-Reply-To: <efe7343f0702070148q5d83263bxb3b6963f1e871200@mail.gmail.com>
References: <efe7343f0702070148q5d83263bxb3b6963f1e871200@mail.gmail.com>
Message-ID: <ab97a06a50a441b2f73c09fb4c765c6d@kernel.crashing.org>

> The only thing it does is add -fno-stack-protection to CFLAGS in all 
> the Makefiles.

That doesn't work, older GCC versions complain about
that option.  The option should only be used if the
compiler supports it.


Segher




From stuge-linuxbios at cdy.org  Fri Feb  9 20:42:33 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Fri, 9 Feb 2007 20:42:33 +0100
Subject: [LinuxBIOS] Error : Payload FILO
In-Reply-To: <20070209041053.BC1657ACFB@ws5-10.us4.outblaze.com>
References: <20070209041053.BC1657ACFB@ws5-10.us4.outblaze.com>
Message-ID: <20070209194233.17687.qmail@cdy.org>

Hello,

On Fri, Feb 09, 2007 at 12:10:53PM +0800, Sayoji Siv wrote:
>  Thanks. I have removed "-Wno-pointer-sign" and now it is working.
> I hav another doubt. I am not yet clear about Disk On Chip.
> 
>  The BIOS chip in Tyan s2882 board is AMI BIOS B25 4665

Please see
http://linuxbios.org/FAQ#How_do_I_identify_the_BIOS_chip_on_my_mainboard.3F

The AMI BIOS does not identify the actual chip, only the BIOS
software that was flashed into the chip at the factory.

Peel off the sticker to reveal the real chip make/model info.


> and the Disk On Chip i am having is Transcend 40 pin IDE Flash.
> 
> Will the both chips will be compatible or is there any specific
> Disk On Chip for this board ?
> Is BIOS savior is required ? If not, how to swap the chip and
> proceed.

If you want FILO as payload you don't need a Disk On Chip because
LinuxBIOS+FILO can be made to fit any size BIOS flash ROM.


Anyway, once you identify the flash chip that contains your AMI BIOS
it is a good idea to purchase a few extra flash chips that can be
used for experimenting with LinuxBIOS. Save the original AMI BIOS
chip someplace where it will not disappear.

A BIOS savior is not required, but it is a very handy way of managing
several flash chips and is recommended.


//Peter



From stuge-linuxbios at cdy.org  Fri Feb  9 20:48:33 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Fri, 9 Feb 2007 20:48:33 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
Message-ID: <20070209194833.18517.qmail@cdy.org>

On Fri, Feb 09, 2007 at 06:26:09PM +0100, Segher Boessenkool wrote:
> Signed-off-by means "I am (in part) responsible for this
> ending up in thid repo", i.e., you wrote part of the patch
> or you were on the path pushing it in.
> 
> Acked-by is used as a comment "looks fine by me" when not
> taking direct action yourself.

Does commiting constitute "on the path pushing it in" ?

Ie. if I review and then commit, should I sign off or ack?


//Peter



From ward at gnu.org  Fri Feb  9 21:21:12 2007
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 9 Feb 2007 15:21:12 -0500
Subject: [LinuxBIOS] MCP55 LinuxBIOS with USB debug etc. part 1
In-Reply-To: <5986589C150B2F49A46483AC44C7BCA49073AD@ssvlexmb2.amd.com>
References: <5986589C150B2F49A46483AC44C7BCA49073AD@ssvlexmb2.amd.com>
Message-ID: <20070209202112.GB7317@countzero.vandewege.net>

On Fri, Jan 19, 2007 at 09:44:14AM -0800, Lu, Yinghai wrote:
> Please check the MCP55 support with usbdebug.
> 
> MB included:
> Nvidia l1_2pvv
> Gigabyte m57sli

Has anyone tried LinuxBIOS on such a Gigabyte board? We're looking at buying
some new desktop machines, and the Gigabyte M57SLI-S4
(http://www.newegg.com/product/product.asp?item=N82E16813128014) seems like a
nice choice.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From uwe at hermann-uwe.de  Sat Feb 10 01:39:37 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 10 Feb 2007 01:39:37 +0100
Subject: [LinuxBIOS] [PATCH] Improve ITE IT8716F support.
Message-ID: <20070210003936.GA1772@greenwood>

Improve ITE IT8716F support.

Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

---

This is yet another part of Yinghai's huge patch. I merged and adapted
the code, some minor, mostly cosmetic, changes here and there.

Some more things are still missing from the huge patch...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stefan.reinauer at coresystems.de  Sat Feb 10 14:47:17 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 10 Feb 2007 14:47:17 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070209194833.18517.qmail@cdy.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>	<45C8F9D6.5060109@gmx.net>
	<20070208014352.GB4356@greenwood>	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
Message-ID: <45CDCCE5.30306@coresystems.de>

Peter Stuge wrote:
> On Fri, Feb 09, 2007 at 06:26:09PM +0100, Segher Boessenkool wrote:
>> Signed-off-by means "I am (in part) responsible for this
>> ending up in thid repo", i.e., you wrote part of the patch
>> or you were on the path pushing it in.
>>
>> Acked-by is used as a comment "looks fine by me" when not
>> taking direct action yourself.
> 
> Does commiting constitute "on the path pushing it in" ?
> 
> Ie. if I review and then commit, should I sign off or ack?

Not as a necessary pre-condition.

* If you did not work on the patch, you don't have to sign it off.

* If you don't agree to the patch or have not reviewed it (but check it
in because you trust the other reviewers who acked the patch), you
should not ack it.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From segher at kernel.crashing.org  Sat Feb 10 20:13:54 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Sat, 10 Feb 2007 20:13:54 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070209194833.18517.qmail@cdy.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
Message-ID: <981bf51fa007934a10482168184e86c8@kernel.crashing.org>

>> Signed-off-by means "I am (in part) responsible for this
>> ending up in thid repo", i.e., you wrote part of the patch
>> or you were on the path pushing it in.
>>
>> Acked-by is used as a comment "looks fine by me" when not
>> taking direct action yourself.
>
> Does commiting constitute "on the path pushing it in" ?

Yes.  Read the DCO if you're still unsure :-)

> Ie. if I review and then commit, should I sign off or ack?

Sign off.


Segher




From stepan at coresystems.de  Sat Feb 10 20:58:23 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 10 Feb 2007 20:58:23 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <981bf51fa007934a10482168184e86c8@kernel.crashing.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
Message-ID: <20070210195823.GA447@coresystems.de>

* Segher Boessenkool <segher at kernel.crashing.org> [070210 20:13]:
> >> Signed-off-by means "I am (in part) responsible for this
> >> ending up in thid repo", i.e., you wrote part of the patch
> >> or you were on the path pushing it in.
> >>
> >> Acked-by is used as a comment "looks fine by me" when not
> >> taking direct action yourself.
> >
> > Does commiting constitute "on the path pushing it in" ?
> 
> Yes.  Read the DCO if you're still unsure :-)

DCO? Is that an abbreviation for 
http://www.linuxbios.org/Development_Guidelines?

> > Ie. if I review and then commit, should I sign off or ack?
> 
> Sign off.

I would say ack, but not necessarily sign off. 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stuge-linuxbios at cdy.org  Sat Feb 10 22:48:33 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Sat, 10 Feb 2007 22:48:33 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070210195823.GA447@coresystems.de>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
Message-ID: <20070210214833.12074.qmail@cdy.org>

Thanks for the comments!

On Sat, Feb 10, 2007 at 08:58:23PM +0100, Stefan Reinauer wrote:
> > > Does commiting constitute "on the path pushing it in" ?
> > 
> > Yes.  Read the DCO if you're still unsure :-)
> 
> DCO? Is that an abbreviation for 
> http://www.linuxbios.org/Development_Guidelines?

DCO is Developer's Certificate of Origin, the blurb that
Signed-off-by is shorthand for.

http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html

Speaking of the DCO, we are using the verbatim text of the DCO 1.1
but we have renamed it to "LinuxBIOS Developer's Certificate of
Origin 1.1" on the wiki page. Was that intentional?

The original DCO has the following copyright notice:
"? 2005 Open Source Development Labs, Inc. The Developer's
Certificate of Origin 1.1 is licensed under a Creative Commons
Attribution-ShareAlike 2.5 License. If you modify you must use a name
or title distinguishable from "Developer's Certificate of Origin" or
"DCO" or any confusingly similar name."

I'd like to change the wiki page to make it clear that this is the
OSDL DCO and not some local LinuxBIOS variation with a stolen name.
Is that OK with everyone?


> > > Ie. if I review and then commit, should I sign off or ack?
> > 
> > Sign off.
> 
> I would say ack, but not necessarily sign off. 

I guess Segher's point is that committing a patch sent to the mailing
list falls under (c) in the DCO, so I should sign off. Is the mailing
list really "directly to me" ?

However, I first reviewed the patch, so I should ack it. We want at
least one acked-by before commit.

So should I actually first ack and then sign off?

Or do we just agree to roll the two into one for LinuxBIOS?
That would make whichever one we choose more ambiguous though. :\


//Peter



From segher at kernel.crashing.org  Sun Feb 11 02:42:03 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Sun, 11 Feb 2007 02:42:03 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070210195823.GA447@coresystems.de>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
Message-ID: <bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>

>>> Ie. if I review and then commit, should I sign off or ack?
>>
>> Sign off.
>
> I would say ack, but not necessarily sign off.

If you don't sign off on something, you can't put it
into the public tree -- that's the whole philosophy
behind the DCO, to have all contributions traceable
to their origins, by having a "trail of bread crumbs".


Segher




From segher at kernel.crashing.org  Sun Feb 11 02:46:47 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Sun, 11 Feb 2007 02:46:47 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070210214833.12074.qmail@cdy.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<20070210214833.12074.qmail@cdy.org>
Message-ID: <02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>

>>>> Ie. if I review and then commit, should I sign off or ack?
>>>
>>> Sign off.
>>
>> I would say ack, but not necessarily sign off.
>
> I guess Segher's point is that committing a patch sent to the mailing
> list falls under (c) in the DCO, so I should sign off. Is the mailing
> list really "directly to me" ?

Yes.  You got the code, you passed it on.  You better make
sure that you know what you're signing for though -- i.e.,
you should make reasonably sure that the person who sent
you the patch had the right to do so (whether something is
sent via a mailing list makes no difference at all btw --
conducting your business in the open doesn't change the
business).

> So should I actually first ack and then sign off?
>
> Or do we just agree to roll the two into one for LinuxBIOS?
> That would make whichever one we choose more ambiguous though. :\

Well it would be really weird to sign-off on a patch that
you don't agree with, so acked-by is quite redundant if you
already signed off on a patch.


Segher




From stuge-linuxbios at cdy.org  Sun Feb 11 03:35:27 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Sun, 11 Feb 2007 03:35:27 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
References: <20070210214833.12074.qmail@cdy.org>
	<02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
	<20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
Message-ID: <20070211023527.21759.qmail@cdy.org>

On Sun, Feb 11, 2007 at 02:42:03AM +0100, Segher Boessenkool wrote:
> >>> Ie. if I review and then commit, should I sign off or ack?
> >>
> >> Sign off.
> >
> > I would say ack, but not necessarily sign off.
> 
> If you don't sign off on something, you can't put it
> into the public tree -- that's the whole philosophy
> behind the DCO, to have all contributions traceable
> to their origins, by having a "trail of bread crumbs".

Note I did not write the patch and the original author has of course
signed off, but is unable to commit herself.


On Sun, Feb 11, 2007 at 02:46:47AM +0100, Segher Boessenkool wrote:
> > I guess Segher's point is that committing a patch sent to the
> > mailing list falls under (c) in the DCO, so I should sign off.
> > Is the mailing list really "directly to me" ?
> 
> Yes.  You got the code, you passed it on.  You better make
> sure that you know what you're signing for though -- i.e.,
> you should make reasonably sure that the person who sent
> you the patch had the right to do so (whether something is
> sent via a mailing list makes no difference at all btw --
> conducting your business in the open doesn't change the
> business).

Again, the poster has signed off.


> > So should I actually first ack and then sign off?
> >
> > Or do we just agree to roll the two into one for LinuxBIOS?
> > That would make whichever one we choose more ambiguous though. :\
> 
> Well it would be really weird to sign-off on a patch that
> you don't agree with, so acked-by is quite redundant if you
> already signed off on a patch.

I would first review (ack) and then commit (sign off) ..


It seems neither the sign-off nor the ack fits for just a commit.


//Peter



From segher at kernel.crashing.org  Sun Feb 11 03:42:43 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Sun, 11 Feb 2007 03:42:43 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070211023527.21759.qmail@cdy.org>
References: <20070210214833.12074.qmail@cdy.org>
	<02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
	<20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
	<20070211023527.21759.qmail@cdy.org>
Message-ID: <d48ee679c714e0d07e4b02a696825791@kernel.crashing.org>

>> If you don't sign off on something, you can't put it
>> into the public tree -- that's the whole philosophy
>> behind the DCO, to have all contributions traceable
>> to their origins, by having a "trail of bread crumbs".
>
> Note I did not write the patch and the original author has of course
> signed off, but is unable to commit herself.

[I don't mean you personally of course].

You can only commit a patch to the tree if you take
responsibility for it (at some level), and that means
you'll have to sign off on it.

>> Yes.  You got the code, you passed it on.  You better make
>> sure that you know what you're signing for though -- i.e.,
>> you should make reasonably sure that the person who sent
>> you the patch had the right to do so (whether something is
>> sent via a mailing list makes no difference at all btw --
>> conducting your business in the open doesn't change the
>> business).
>
> Again, the poster has signed off.

When you want to pass the code on (for example, by
committing it to the repo), you have to sign off on
it as well.

>> Well it would be really weird to sign-off on a patch that
>> you don't agree with, so acked-by is quite redundant if you
>> already signed off on a patch.
>
> I would first review (ack) and then commit (sign off) ..
>
>
> It seems neither the sign-off nor the ack fits for just a commit.

You *need* a signed-off for a commit though, that's what the
DCO is all about.

If what you want is keeping track of committers -- that's not
a property of a patch, but a property of the repo; any good
SCM tracks that for you automatically.


Segher




From stuge-linuxbios at cdy.org  Sun Feb 11 05:06:49 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Sun, 11 Feb 2007 05:06:49 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <d48ee679c714e0d07e4b02a696825791@kernel.crashing.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
	<20070211023527.21759.qmail@cdy.org>
	<d48ee679c714e0d07e4b02a696825791@kernel.crashing.org>
Message-ID: <20070211040649.2320.qmail@cdy.org>

On Sun, Feb 11, 2007 at 03:42:43AM +0100, Segher Boessenkool wrote:
> >> If you don't sign off on something, you can't put it
> >> into the public tree -- that's the whole philosophy
> >> behind the DCO, to have all contributions traceable
> >> to their origins, by having a "trail of bread crumbs".
> >
> > Note I did not write the patch and the original author has of course
> > signed off, but is unable to commit herself.
> 
> [I don't mean you personally of course].
> 
> You can only commit a patch to the tree if you take
> responsibility for it (at some level), and that means
> you'll have to sign off on it.

Ok, so our policy is that the committer always adds a sign off?


> > Again, the poster has signed off.
> 
> When you want to pass the code on (for example, by
> committing it to the repo), you have to sign off on
> it as well.

But I also reviewed it, so I should ack, right? Adding my own
Signed-off-by doesn't imply review, or does it?


> > It seems neither the sign-off nor the ack fits for just a commit.
> 
> You *need* a signed-off for a commit though, that's what the
> DCO is all about.

Yes, but does the committer need to sign-off too?
Isn't it enough with the signed-off-by from the author and an ack
from the committer?


> If what you want is keeping track of committers -- that's not
> a property of a patch, but a property of the repo; any good
> SCM tracks that for you automatically.

Yes.

But the policy of sign-off+ack required for commit is incompatible
with the suggested author sign-off+committer sign-off scheme, hence
my questions. :)


//Peter



From psosa_ar at yahoo.com  Sun Feb 11 11:08:52 2007
From: psosa_ar at yahoo.com (Pablo Sosa)
Date: Sun, 11 Feb 2007 02:08:52 -0800 (PST)
Subject: [LinuxBIOS] is this motherboard supported? VIA EPIA-SP13000
Message-ID: <208434.14445.qm@web35607.mail.mud.yahoo.com>

Hi there,

   Hope this is the right forum to ask. I was checking the list of supported motherboards in order to try linuxbios, I could find I can buy one of this motherboards which are similar but not the same to VIA that are mentioned on the page, i.e.




            
               
			
                     

                  
                     VIA EPIA-SP13000 Motherboard, Socket 370Specs according to the vendor are:

Specifications:

 - Processor: VIA C3?/ VIA Eden? EBGA processor
 - Chipset: VIA CN400 North Bridge; VIA VT8237 South Bridge
 - System Memory: 1x DDR266/333/400 DIMM socket supports up to 1GB memory size
 - VGA: Integrated VIA UniChrome?Pro AGP graphics with MPEG-2 decoder /MPEG-4 Accelerator
 - Expansion Slots: 1 PCI
 - Onboard IDE: 2x UltraDMA 133/100 Connector
 - Onboard Serial ATA: 2 SATA Connectors
 - Onboard LAN: VIA VT6103 10/100 Base-T Ethernet PHY
 - Onboard Audio: VIA VT1617A 6channel AC' 97 codec
 - Onboard TV Out: VIA VT1623 TV Encoder
 - Onboard 1394: VIA VT6307S IEEE 1394 Firewire

  On the link that's on the supported motherboards page appears, http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=202, and the specs from the manufacturer are:
VIA EPIA MII. 
Chipset 
              ? VIA CLE266 North Bridge
? VIA VT8235M South Bridge

The North/South bridges in the manufacturer page, are different to the ones in the list of compatible motherboards. specs on the motherboard page are:
 VIA
 EPIA-MII
 VIA VT8623
 VIA VT8235, Ricoh RL5C476
 VIA VT1211
 VIA C3?, VIA EDEN?
 Socket 370
 OK
  So I'm a bit confused and wouldn't like to buy something that's unable to support linuxbios, I'll appreciate if someone can help me, or give me some advice


Cheers,
Pablo Sosa


 
____________________________________________________________________________________
Cheap talk?
Check out Yahoo! Messenger's low PC-to-Phone call rates.
http://voice.yahoo.com



From corey_osgood at verizon.net  Sun Feb 11 11:48:25 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Sun, 11 Feb 2007 05:48:25 -0500
Subject: [LinuxBIOS] A (likely rather stupid) question on Via docs
Message-ID: <45CEF479.1010508@verizon.net>

Hi all,
So, I'm working on the vt694x and getting rather frustrated, and so I
popped open the docs from rom.by, and this caught my eye:

| 1.0 | 9/8/99 | Final document release with ?NDA Required? removed |DH|

Does this mean that there shouldn't be any issue with using these docs?
That would make life so much easier.

-Corey




From uwe at hermann-uwe.de  Sun Feb 11 16:12:17 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 11 Feb 2007 16:12:17 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070210214833.12074.qmail@cdy.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<20070210214833.12074.qmail@cdy.org>
Message-ID: <20070211151217.GA23294@greenwood>

Hi,

On Sat, Feb 10, 2007 at 10:48:33PM +0100, Peter Stuge wrote:
> Speaking of the DCO, we are using the verbatim text of the DCO 1.1
> but we have renamed it to "LinuxBIOS Developer's Certificate of
> Origin 1.1" on the wiki page.

Good point.


> Was that intentional?

Yes, but that was wrong. I renamed it because I misread the 'If you
modify you must use a name or title distinguishable from "Developer's
Certificate of Origin"' below.
If we do _not_ modify the DCO, we can still also keep the name (that's
how I understand it at least).

I reverted my renaming, it's called "Developer's Certificate of Origin 1.1"
again now. Thanks for pointing that out.


> The original DCO has the following copyright notice:
> "? 2005 Open Source Development Labs, Inc. The Developer's
> Certificate of Origin 1.1 is licensed under a Creative Commons
> Attribution-ShareAlike 2.5 License. If you modify you must use a name
> or title distinguishable from "Developer's Certificate of Origin" or
> "DCO" or any confusingly similar name."
 

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Sun Feb 11 16:19:37 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 11 Feb 2007 16:19:37 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<20070210214833.12074.qmail@cdy.org>
	<02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
Message-ID: <20070211151937.GB23294@greenwood>

Hi,

On Sun, Feb 11, 2007 at 02:46:47AM +0100, Segher Boessenkool wrote:
> Well it would be really weird to sign-off on a patch that
> you don't agree with, so acked-by is quite redundant if you
> already signed off on a patch.

I posted an example a few days ago. I see a patch on the list,
take it, modify it to improve _some_ parts of it, but it's still
not "finished" and I'm still don't agree that it should be committed.
But at least it's a bit better now.

In such a case I'd say I should sign-off (as I modified the patch), but
I don't want to Ack it.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Sun Feb 11 16:21:09 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 11 Feb 2007 16:21:09 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070211151937.GB23294@greenwood>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<20070210214833.12074.qmail@cdy.org>
	<02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
	<20070211151937.GB23294@greenwood>
Message-ID: <20070211152108.GA7930@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070211 16:19]:
> I posted an example a few days ago. I see a patch on the list,
> take it, modify it to improve _some_ parts of it, but it's still
> not "finished" and I'm still don't agree that it should be committed.
> But at least it's a bit better now.
> 
> In such a case I'd say I should sign-off (as I modified the patch), but
> I don't want to Ack it.

fully agreed.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From segher at kernel.crashing.org  Mon Feb 12 00:49:32 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Mon, 12 Feb 2007 00:49:32 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070211040649.2320.qmail@cdy.org>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
	<20070211023527.21759.qmail@cdy.org>
	<d48ee679c714e0d07e4b02a696825791@kernel.crashing.org>
	<20070211040649.2320.qmail@cdy.org>
Message-ID: <9600a770222faf0575c47ce438422622@kernel.crashing.org>

>> You can only commit a patch to the tree if you take
>> responsibility for it (at some level), and that means
>> you'll have to sign off on it.
>
> Ok, so our policy is that the committer always adds a sign off?

If not, the whole signed-off-by thing becomes useless,
so it better be policy.

>> When you want to pass the code on (for example, by
>> committing it to the repo), you have to sign off on
>> it as well.
>
> But I also reviewed it, so I should ack, right?

Dunno.  "acked-by" as used in Linux is only an informal
comment; if LinuxBIOS wants to formalise its usage, the
rules should be written down somewhere.

> Adding my own
> Signed-off-by doesn't imply review, or does it?

It doesn't, but it would be silly (and irresponsible)
to sign-off on something you didn't look at first.

>>> It seems neither the sign-off nor the ack fits for just a commit.
>>
>> You *need* a signed-off for a commit though, that's what the
>> DCO is all about.
>
> Yes, but does the committer need to sign-off too?
> Isn't it enough with the signed-off-by from the author and an ack
> from the committer?

No.  Every step in the chain into the repo needs to
be tracked or the "chain of trust" is lost.

>> If what you want is keeping track of committers -- that's not
>> a property of a patch, but a property of the repo; any good
>> SCM tracks that for you automatically.
>
> Yes.
>
> But the policy of sign-off+ack required for commit is incompatible
> with the suggested author sign-off+committer sign-off scheme, hence
> my questions. :)

I don't see the incompatibility?  Unless you mean that
the acked-by tags should be put into the commit; that
is a foolish thing indeed, there are many problems with
it (for example, it is easy to forget to add one of those
when you commit; not the case with signed-off, since
that's in the patch when you send it out for review
already, and a committer will add it automatically if
he has his tools set up for that).


Segher




From segher at kernel.crashing.org  Mon Feb 12 01:34:32 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Mon, 12 Feb 2007 01:34:32 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070211151937.GB23294@greenwood>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<20070210214833.12074.qmail@cdy.org>
	<02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
	<20070211151937.GB23294@greenwood>
Message-ID: <fe0a05aa36c67eec47f382b56059da3b@kernel.crashing.org>

>> Well it would be really weird to sign-off on a patch that
>> you don't agree with, so acked-by is quite redundant if you
>> already signed off on a patch.
>
> I posted an example a few days ago. I see a patch on the list,
> take it, modify it to improve _some_ parts of it, but it's still
> not "finished" and I'm still don't agree that it should be committed.
> But at least it's a bit better now.
>
> In such a case I'd say I should sign-off (as I modified the patch), but
> I don't want to Ack it.

But you don't check it in yet either.  The "ack" that we
require is only for pushing stuff into the repo.


Segher




From segher at kernel.crashing.org  Mon Feb 12 01:36:08 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Mon, 12 Feb 2007 01:36:08 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070211152108.GA7930@coresystems.de>
References: <20070206194821.21747gmx1@mx092.gmx.net>
	<45C8F9D6.5060109@gmx.net> <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<20070210214833.12074.qmail@cdy.org>
	<02a263bd8c2823aa46e76ffbe958b3be@kernel.crashing.org>
	<20070211151937.GB23294@greenwood>
	<20070211152108.GA7930@coresystems.de>
Message-ID: <a1983e7b160368608815c891e89c40ea@kernel.crashing.org>

>> I posted an example a few days ago. I see a patch on the list,
>> take it, modify it to improve _some_ parts of it, but it's still
>> not "finished" and I'm still don't agree that it should be committed.
>> But at least it's a bit better now.
>>
>> In such a case I'd say I should sign-off (as I modified the patch), 
>> but
>> I don't want to Ack it.
>
> fully agreed.

Yeah.  But the only "acked-by"s that have any sense
tracking are those on the final version of the patch,
i.e. the version that gets checked in, so the point
is moot.


Segher




From stuge-linuxbios at cdy.org  Mon Feb 12 01:42:05 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Mon, 12 Feb 2007 01:42:05 +0100
Subject: [LinuxBIOS] is this motherboard supported? VIA EPIA-SP13000
In-Reply-To: <208434.14445.qm@web35607.mail.mud.yahoo.com>
References: <208434.14445.qm@web35607.mail.mud.yahoo.com>
Message-ID: <20070212004205.26105.qmail@cdy.org>

Hi Pablo,

On Sun, Feb 11, 2007 at 02:08:52AM -0800, Pablo Sosa wrote:
> Hope this is the right forum to ask. I was checking the list of
> supported motherboards in order to try linuxbios, I could find I
> can buy one of this motherboards which are similar but not the same
> to VIA that are mentioned on the page, i.e.
> 
> VIA EPIA-SP13000 Motherboard, Socket 370
> Specs according to the vendor are:
> 
> Specifications:
> 
>  - Processor: VIA C3 / VIA Eden  EBGA processor
>  - Chipset: VIA CN400 North Bridge; VIA VT8237 South Bridge

[..]

> So I'm a bit confused and wouldn't like to buy something that's
> unable to support linuxbios, I'll appreciate if someone can help
> me, or give me some advice

Your research is correct. The EPIA-SP boards use a lot of hardware
different from the EPIA-MII and most of it is yet unsupported in
LinuxBIOS.

Given data sheets, time and patience it is certainly possible to
teach LinuxBIOS about the hardware on the SP boards, but they are
already old since the C7 boards have been available for some time.


//Peter



From corey_osgood at verizon.net  Mon Feb 12 03:29:31 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Sun, 11 Feb 2007 21:29:31 -0500
Subject: [LinuxBIOS] A (likely rather stupid) question on Via docs
In-Reply-To: <13426df10702111559o5bf93b7cqc7a37c12c1891828@mail.gmail.com>
References: <45CEF479.1010508@verizon.net>
	<13426df10702111559o5bf93b7cqc7a37c12c1891828@mail.gmail.com>
Message-ID: <45CFD10B.6060300@verizon.net>

ron minnich wrote:
> On 2/11/07, Corey Osgood <corey_osgood at verizon.net> wrote:
>> Hi all,
>> So, I'm working on the vt694x and getting rather frustrated, and so I
>> popped open the docs from rom.by, and this caught my eye:
>>
>> | 1.0 | 9/8/99 | Final document release with "NDA Required" removed |DH|
>>
>> Does this mean that there shouldn't be any issue with using these docs?
>> That would make life so much easier.
> 
> how did you get them? How did rom.by get them?

I honestly don't know how rom.by got them, I found them through a heck
of a lot of searching. rom.by is mainly a site for people who hack
original bioses, it went under for a while due to lack of interest but
is now back up. I've looked through a few of the other via ones, and
some are watermarked as "Confidential - NDA Required", but they're also
very early versions (0.1, etc) of the datasheets. They're all listed
here: http://www.rom.by/doki.htm.

> on the face of it, however, that comment would seem to mean that there
> is no issue.

Thanks for the clarification, that was my thought too, but I didn't want
to submit any code and get burned at the stake later on for using
anything that might create legal issues. The other watermarked docs seem
to confirm that this is a public document, just not widely available.

-Corey

PS: Forgot to send this to the mailing list, oops



From stepan at coresystems.de  Mon Feb 12 12:28:08 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 12 Feb 2007 12:28:08 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <9600a770222faf0575c47ce438422622@kernel.crashing.org>
References: <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
	<20070211023527.21759.qmail@cdy.org>
	<d48ee679c714e0d07e4b02a696825791@kernel.crashing.org>
	<20070211040649.2320.qmail@cdy.org>
	<9600a770222faf0575c47ce438422622@kernel.crashing.org>
Message-ID: <20070212112808.GA398@coresystems.de>

* Segher Boessenkool <segher at kernel.crashing.org> [070212 00:49]:
> >> You can only commit a patch to the tree if you take
> >> responsibility for it (at some level), and that means
> >> you'll have to sign off on it.
> >
> > Ok, so our policy is that the committer always adds a sign off?
> 
> If not, the whole signed-off-by thing becomes useless,
> so it better be policy.

now, why exactly?

> > But I also reviewed it, so I should ack, right?
> 
> Dunno.  "acked-by" as used in Linux is only an informal
> comment; if LinuxBIOS wants to formalise its usage, the
> rules should be written down somewhere.
 
Whats missing in http://www.linuxbios.org/Development_Guidelines?

> > Yes, but does the committer need to sign-off too?
> > Isn't it enough with the signed-off-by from the author and an ack
> > from the committer?
> 
> No.  Every step in the chain into the repo needs to
> be tracked or the "chain of trust" is lost.
 
I dont think the chain of trust goes lost. The repository monitors who 
did the commit, so it will be as easy to find out as grepping for the
Signed-off-by: ?

ie. Are you saying the mails that get sent out to the mailing list
should be filtered to say

    Signed-off-by: Committer

instead of

    Committed by: Committer

? 

> I don't see the incompatibility?  Unless you mean that
> the acked-by tags should be put into the commit; that
> is a foolish thing indeed, there are many problems with
> it (for example, it is easy to forget to add one of those
> when you commit; not the case with signed-off, since
> that's in the patch when you send it out for review
> already, and a committer will add it automatically if
> he has his tools set up for that).

If you think our review process is useless, you are of course not
forced to contribute to it.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From segher at kernel.crashing.org  Mon Feb 12 15:20:45 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Mon, 12 Feb 2007 15:20:45 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <20070212112808.GA398@coresystems.de>
References: <20070208014352.GB4356@greenwood>
	<1ac97d9520dbc29bc551f695631d7c5e@kernel.crashing.org>
	<20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
	<20070211023527.21759.qmail@cdy.org>
	<d48ee679c714e0d07e4b02a696825791@kernel.crashing.org>
	<20070211040649.2320.qmail@cdy.org>
	<9600a770222faf0575c47ce438422622@kernel.crashing.org>
	<20070212112808.GA398@coresystems.de>
Message-ID: <6d666938095343e774b92f08226c9f09@kernel.crashing.org>

>>>> You can only commit a patch to the tree if you take
>>>> responsibility for it (at some level), and that means
>>>> you'll have to sign off on it.
>>>
>>> Ok, so our policy is that the committer always adds a sign off?
>>
>> If not, the whole signed-off-by thing becomes useless,
>> so it better be policy.
>
> now, why exactly?

It's point (c) in the DCO.

If you allow any code to be checked in without the person
doing that stating he has the the right to do that, i.e.
without adding the signed-off, all previous signed-off
statements (by the original developer, etc.) have no
significance as to whether the LinuxBIOS project did check
if it was allowed (for IP or copyright reasons) to use
the code.  Only full chains work; one missing link and
it's broken.

>>> But I also reviewed it, so I should ack, right?
>>
>> Dunno.  "acked-by" as used in Linux is only an informal
>> comment; if LinuxBIOS wants to formalise its usage, the
>> rules should be written down somewhere.
>
> Whats missing in http://www.linuxbios.org/Development_Guidelines?

The doc should be in the repo itself.  Other than that,
it could be formalised a bit ;-)

>>> Yes, but does the committer need to sign-off too?
>>> Isn't it enough with the signed-off-by from the author and an ack
>>> from the committer?
>>
>> No.  Every step in the chain into the repo needs to
>> be tracked or the "chain of trust" is lost.
>
> I dont think the chain of trust goes lost. The repository monitors who
> did the commit, so it will be as easy to find out as grepping for the
> Signed-off-by: ?

The "commit" message the repo gives you only tells you
who did the check in; it doesn't say that the commiter
states that he checked to the best of his knowledge that
he is allowed to (re-)publish that source code.

> ie. Are you saying the mails that get sent out to the mailing list
> should be filtered to say
>
>     Signed-off-by: Committer
>
> instead of
>
>     Committed by: Committer
>
> ?

No.  I'm saying that committers should manually (or at least
consciously) add the signed-off.

>> I don't see the incompatibility?  Unless you mean that
>> the acked-by tags should be put into the commit; that
>> is a foolish thing indeed, there are many problems with
>> it (for example, it is easy to forget to add one of those
>> when you commit; not the case with signed-off, since
>> that's in the patch when you send it out for review
>> already, and a committer will add it automatically if
>> he has his tools set up for that).
>
> If you think our review process is useless, you are of course not
> forced to contribute to it.

I'm not saying the review process is useless; I'm saying
that recording history of who thought what patch was a
good idea, _when those patches never end up being committed_,
is pretty damn useless.  A newer version of the patch
superseded the old one; knowing who approved the final
commit *can* of course be useful.  I wasn't commenting
on the review process at all; just on the acked-by lines
that people add to commit messages.


Segher




From rminnich at gmail.com  Mon Feb 12 23:02:38 2007
From: rminnich at gmail.com (ron minnich)
Date: Mon, 12 Feb 2007 15:02:38 -0700
Subject: [LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
In-Reply-To: <20070208002703.GA22300@greenwood>
References: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
	<20070208002703.GA22300@greenwood>
Message-ID: <13426df10702121402l3de1b906v21cad3ccd190672b@mail.gmail.com>

does anyone want to add a "news" entry to the wiki for MSI and this
new support?

thanks

ron



From uwe at hermann-uwe.de  Tue Feb 13 12:43:35 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 13 Feb 2007 12:43:35 +0100
Subject: [LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
In-Reply-To: <13426df10702121402l3de1b906v21cad3ccd190672b@mail.gmail.com>
References: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
	<20070208002703.GA22300@greenwood>
	<13426df10702121402l3de1b906v21cad3ccd190672b@mail.gmail.com>
Message-ID: <20070213114334.GA30416@greenwood>

On Mon, Feb 12, 2007 at 03:02:38PM -0700, ron minnich wrote:
> does anyone want to add a "news" entry to the wiki for MSI and this
> new support?
> 
> thanks

Good point. Done.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Feb 13 12:53:45 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 13 Feb 2007 12:53:45 +0100
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
Message-ID: <20070213115345.GB30416@greenwood>

Hi,

here's the remainders of Yinghai's MCP55 patch. Let's get this reviewed
and committed ASAP so we can announce yet another bunch of supported
mainboards :)

I tried to clean up some parts of the code which are the results of
the diff being made against a pretty old code base, but not all is yet
cleaned (yh_rest_of_patch.patch needs more work).

The yh_mainboards_targets.patch consists of all-new code, so it can be
safely committed, except for two issues:

 * License headers are mostly missing.

 * I don't know whether the code will actually build or work without
   the changes in yh_rest_of_patch.patch (probably not).


HTH, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Feb 13 13:15:09 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 13 Feb 2007 13:15:09 +0100
Subject: [LinuxBIOS] r2550 - trunk/LinuxBIOSv2/util/flashrom
In-Reply-To: <6d666938095343e774b92f08226c9f09@kernel.crashing.org>
References: <20070209194833.18517.qmail@cdy.org>
	<981bf51fa007934a10482168184e86c8@kernel.crashing.org>
	<20070210195823.GA447@coresystems.de>
	<bac6f2b1cf2c993146a9e49366771b68@kernel.crashing.org>
	<20070211023527.21759.qmail@cdy.org>
	<d48ee679c714e0d07e4b02a696825791@kernel.crashing.org>
	<20070211040649.2320.qmail@cdy.org>
	<9600a770222faf0575c47ce438422622@kernel.crashing.org>
	<20070212112808.GA398@coresystems.de>
	<6d666938095343e774b92f08226c9f09@kernel.crashing.org>
Message-ID: <20070213121509.GC30416@greenwood>

Hi,

On Mon, Feb 12, 2007 at 03:20:45PM +0100, Segher Boessenkool wrote:
> It's point (c) in the DCO.
> 
> If you allow any code to be checked in without the person
> doing that stating he has the the right to do that, i.e.
> without adding the signed-off, all previous signed-off
> statements (by the original developer, etc.) have no
> significance as to whether the LinuxBIOS project did check
> if it was allowed (for IP or copyright reasons) to use
> the code.  Only full chains work; one missing link and
> it's broken.

Hm, good point.

 
> >>> But I also reviewed it, so I should ack, right?
> >>
> >> Dunno.  "acked-by" as used in Linux is only an informal
> >> comment; if LinuxBIOS wants to formalise its usage, the
> >> rules should be written down somewhere.
> >
> > Whats missing in http://www.linuxbios.org/Development_Guidelines?
> 
> The doc should be in the repo itself.

OK, I'll send a patch soon.


> Other than that,
> it could be formalised a bit ;-)

Do you have a patch or specific suggestions for improvements?


> I'm not saying the review process is useless; I'm saying
> that recording history of who thought what patch was a
> good idea, _when those patches never end up being committed_,
> is pretty damn useless.  A newer version of the patch
> superseded the old one; knowing who approved the final
> commit *can* of course be useful.  I wasn't commenting
> on the review process at all; just on the acked-by lines
> that people add to commit messages.

OK, how about this procedure (I don't really care anymore whether
it's compatible with the way it works in Linux, it should only be
legally "bullet-proof"):

* Everyone who creates or modifies a patch adds his Signed-off-by.

* The person who finally commits the patch adds his/her
  Signed-off-by, too (if it's not already there anyway).

* The Acked-by is completely separated from that. You send an Acked-by
  when you think this patch can be committed.
  You don't have to modify a patch for an Acked-by, you can just send
  it to say "I think this patch is ok".

* If a certain version of a patch received two Acked-by's by two
  different people, it can be committed.
  Ergo, every commit message will have 1 or more Signed-off-by lines which
  build a "chain of trust" for legal reasons, _and_ it will have 2 or more
  Acked-by lines which enforce our review process.

* The Acked-by's must be for exactly the same version of the patch.
  Acked-by's for previous versions of the patch are meaningless, they
  are not added to the commit message, only those for the exact
  incarnation of the patch which gets committed.

* So yes, it is possible to post

   - A patch with only a Sign-off-by:
     You modified the code, but don't want it to be committed, yet.
   - A patch with a Signed-off-by and an Acked-by:
     You modified the patch and you think it can be commited.
   - An email with just an Acked-by:
     You didn't touch the patch at all, but you think it can be committed.

Comments?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From demaillists at comcast.net  Tue Feb 13 15:21:32 2007
From: demaillists at comcast.net (dedmons)
Date: Tue, 13 Feb 2007 06:21:32 -0800
Subject: [LinuxBIOS] MSI-K7N2GM-L, Athlon XP, NVidia chipset bootable?
Message-ID: <45D1C96C.5000600@comcast.net>

Hi all,

I looked into LinuxBios many years ago, but never
tried to burn a new BIOS.

Now, given that many appear to be flashable onboard
by the motherboard itself, I decided to give it another
look.

My machines motherboard has the following:

board: MSI-K7N2GM-L, Athlon XP, NVidia chipset
MS-6777/G (v1.x) M-ATC
Socket-462

Inside I found the following numbers:

1) Pheonix Bios D686(?) Bios 18195747
2) Nvidia NForce2 MCP F85055-R4 0348A4
3) WinBond W83627HF-AW

The book also lists these two:
4) Realtek RTL8201bl
5) VIA VT6307
6) nVidia NForce2 400/IGP

The board has an on-board AGP card, but I'm using
a Matrox G450 dual-head.

I have noted that LinuxBios lists the following as being
supported (flashrom):
NVIDIA MCP55 OK

and in V2
Winbond? W83627HF ?

I'll continue researching to see if I'll have to Burn
or Flash the LinuxBios, but the book seems to
indicate it is flashable. Hopefully, LinuxBios will
too.

Thanks.

Dale



From c-d.hailfinger.devel.2006 at gmx.net  Tue Feb 13 16:43:19 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 13 Feb 2007 16:43:19 +0100
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <20070213115345.GB30416@greenwood>
References: <20070213115345.GB30416@greenwood>
Message-ID: <45D1DC97.9070501@gmx.net>

Hi,

Uwe Hermann wrote:
> here's the remainders of Yinghai's MCP55 patch. Let's get this reviewed
> and committed ASAP so we can announce yet another bunch of supported
> mainboards :)
> 
> The yh_mainboards_targets.patch consists of all-new code, so it can be
> safely committed, except for two issues:
> 
>  * License headers are mostly missing.
> 
>  * I don't know whether the code will actually build or work without
>    the changes in yh_rest_of_patch.patch (probably not).

* Tabs vs. spaces
* Missing end-of-lines

> -- targets/supermicro/h8dmr/Config.lb  (Revision 0)
> +++ targets/supermicro/h8dmr/Config.lb  (Revision 0)
> @@ -0,0 +1 @@
> +link Config.lb.payload
> \ Kein Zeilenvorschub am Ende der Datei
> 
> Eigenschafts?nderungen: targets/supermicro/h8dmr/Config.lb
> ___________________________________________________________________
> Name: svn:special
>    + *
> 
> --- targets/gigabyte/m57sli/Config.lb   (Revision 0)
> +++ targets/gigabyte/m57sli/Config.lb   (Revision 0)
> @@ -0,0 +1 @@
> +link Config.lb.payload
> \ Kein Zeilenvorschub am Ende der Datei
> 
> Eigenschafts?nderungen: targets/gigabyte/m57sli/Config.lb
> ___________________________________________________________________
> Name: svn:special
>    + *
> 
> --- targets/tyan/s2912/Config.lb        (Revision 0)
> +++ targets/tyan/s2912/Config.lb        (Revision 0)
> @@ -0,0 +1 @@
> +link Config.lb.payload
> \ Kein Zeilenvorschub am Ende der Datei
> 
> Eigenschafts?nderungen: targets/tyan/s2912/Config.lb
> ___________________________________________________________________
> Name: svn:special
>    + *
> 
> Index: targets/payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
> ===================================================================
> Kann nicht anzeigen: Dateityp ist als bin?r angegeben.
> svn:mime-type = application/octet-stream
> 
> Eigenschafts?nderungen: targets/payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
> ___________________________________________________________________
> Name: svn:executable
>    + *
> Name: svn:mime-type
>    + application/octet-stream
> 
> --- targets/nvidia/l1_2pvv/Config.lb    (Revision 0)
> +++ targets/nvidia/l1_2pvv/Config.lb    (Revision 0)
> @@ -0,0 +1 @@
> +link Config.lb.payload
> \ Kein Zeilenvorschub am Ende der Datei
> 
> Eigenschafts?nderungen: targets/nvidia/l1_2pvv/Config.lb
> ___________________________________________________________________
> Name: svn:special
>    + *
> 

Do we have the right to distribute the PIR tables of the original
BIOS?

> --- src/mainboard/supermicro/h8dmr/irq_tables.c (Revision 0)
> +++ src/mainboard/supermicro/h8dmr/irq_tables.c (Revision 0)
> @@ -0,0 +1,96 @@
> +/* This file was generated by getpir.c, do not modify! 
> +   (but if you do, please run checkpir on it to verify)
> +   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up


Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/



From uwe at hermann-uwe.de  Tue Feb 13 17:03:27 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 13 Feb 2007 17:03:27 +0100
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <45D1DC97.9070501@gmx.net>
References: <20070213115345.GB30416@greenwood> <45D1DC97.9070501@gmx.net>
Message-ID: <20070213160327.GA17782@greenwood>

Hi,

On Tue, Feb 13, 2007 at 04:43:19PM +0100, Carl-Daniel Hailfinger wrote:
> * Tabs vs. spaces
> * Missing end-of-lines

Yes, but I don't consider these blockers. We can commit nevertheless,
and then fix these later with an extra patch.


> > -- targets/supermicro/h8dmr/Config.lb  (Revision 0)
> > +++ targets/supermicro/h8dmr/Config.lb  (Revision 0)
> > @@ -0,0 +1 @@
> > +link Config.lb.payload
> > \ Kein Zeilenvorschub am Ende der Datei
> > 
> > Eigenschafts?nderungen: targets/supermicro/h8dmr/Config.lb
> > ___________________________________________________________________
> > Name: svn:special
> >    + *

These are just indicators that there's a symlink
Config.lb -> Config.lb.payload, if I'm not mistaken.

How should we handle this in the repository?


> Do we have the right to distribute the PIR tables of the original
> BIOS?
> 
> > --- src/mainboard/supermicro/h8dmr/irq_tables.c (Revision 0)
> > +++ src/mainboard/supermicro/h8dmr/irq_tables.c (Revision 0)
> > @@ -0,0 +1,96 @@
> > +/* This file was generated by getpir.c, do not modify! 
> > +   (but if you do, please run checkpir on it to verify)
> > +   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up

I have no idea, but we already distribute multiple of those
getpir.c-outputs in our current code base, I think, so it's probably ok.
Anybody who knows more?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From segher at kernel.crashing.org  Tue Feb 13 21:16:31 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Tue, 13 Feb 2007 21:16:31 +0100
Subject: [LinuxBIOS] [PATCH] MSI ms9282 LinuxBIOS support
In-Reply-To: <20070208002703.GA22300@greenwood>
References: <F6A4CD6D05C8BF4893B3FB22EDCDD57DEFCDD2@ex2000.msik.com.cn>
	<20070208002703.GA22300@greenwood>
Message-ID: <98c3df45d0dded365870163aa2c6acc4@kernel.crashing.org>

>> Sign-off-by: Bingxun Shi <bingxunshi at gmail.com>
>
> Great stuff! Thanks a lot for your work!
>
> After a quick review I cannot see any flaws whatsoever: the patch
> applies fine, all license headers are there, sign-off is there,
> and the code builds fine.

It's spelled Signed-off-by: though.


Segher




From segher at kernel.crashing.org  Tue Feb 13 21:19:51 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Tue, 13 Feb 2007 21:19:51 +0100
Subject: [LinuxBIOS] Question about PCI Config Space byte rd/wr in HT
In-Reply-To: <200702080112.l181CXZ1030005@gate.crashing.org>
References: <200702080112.l181CXZ1030005@gate.crashing.org>
Message-ID: <fc76582a84a71f0ecb3d5dc01b2cddf4@kernel.crashing.org>

[Don't reply to an unrelated post, please start a new
thread instead].

> If software tries to do a byte rd/wr access to PCI config access, say 
> in
> linux or BIOS, how would it show up on the HT bus?

As a byte access to config space -- what else?

Read the HT specification (from hypertransport.org)
if you need to know the details.

> I'm assuming that config space access is initiated through the 
> southbridge.

It's done on the CPU chip (it detects accesses to
legacy I/O address 0xfc8/0xcfc).

> Anyone know if an HT device will ever have to expect byte access to its
> config space?

Yes, some people know.  Yes, they have to expect (and
allow) byte accesses.


Segher




From trappski at gmail.com  Tue Feb 13 16:45:42 2007
From: trappski at gmail.com (Andreas Treppe)
Date: Tue, 13 Feb 2007 16:45:42 +0100
Subject: [LinuxBIOS] Hardware Info from me...
In-Reply-To: <be2b1fbf0702130744x3ea06257t4466d929b437fe59@mail.gmail.com>
References: <be2b1fbf0702130744x3ea06257t4466d929b437fe59@mail.gmail.com>
Message-ID: <be2b1fbf0702130745s79921d95jb9d276ff292383da@mail.gmail.com>

The included files ar in plain text...
Hope this is useful info
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From corey_osgood at verizon.net  Wed Feb 14 03:17:34 2007
From: corey_osgood at verizon.net (Corey Osgood)
Date: Tue, 13 Feb 2007 21:17:34 -0500
Subject: [LinuxBIOS] Hardware Info from me...
In-Reply-To: <be2b1fbf0702130745s79921d95jb9d276ff292383da@mail.gmail.com>
References: <be2b1fbf0702130744x3ea06257t4466d929b437fe59@mail.gmail.com>
	<be2b1fbf0702130745s79921d95jb9d276ff292383da@mail.gmail.com>
Message-ID: <45D2713E.2030507@verizon.net>

Andreas Treppe wrote:
> The included files ar in plain text...
> Hope this is useful info
> 
> 

Sorry, there's no support for NForce 2 at the moment, and I don't
believe anyone's working on it. I don't know if we'll be seeing this in
the future or not.

-Corey



From stuge-linuxbios at cdy.org  Wed Feb 14 04:08:11 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Wed, 14 Feb 2007 04:08:11 +0100
Subject: [LinuxBIOS] Hardware Info from me...
In-Reply-To: <45D2713E.2030507@verizon.net>
References: <be2b1fbf0702130744x3ea06257t4466d929b437fe59@mail.gmail.com>
	<be2b1fbf0702130745s79921d95jb9d276ff292383da@mail.gmail.com>
	<45D2713E.2030507@verizon.net>
Message-ID: <20070214030811.16421.qmail@cdy.org>

On Tue, Feb 13, 2007 at 09:17:34PM -0500, Corey Osgood wrote:
> Andreas Treppe wrote:
> > The included files ar in plain text...
> > Hope this is useful info
> 
> Sorry, there's no support for NForce 2 at the moment, and I don't
> believe anyone's working on it. I don't know if we'll be seeing
> this in the future or not.

Still, thanks for sending the info.


//Peter



From bingxunshi at gmail.com  Wed Feb 14 04:23:49 2007
From: bingxunshi at gmail.com (bxshi)
Date: Wed, 14 Feb 2007 11:23:49 +0800
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <20070213115345.GB30416@greenwood>
References: <20070213115345.GB30416@greenwood>
Message-ID: <dcdcf0740702131923o4616a784h128736bcaec92b6c@mail.gmail.com>

>
>
> * I don't know whether the code will actually build or work without
>   the changes in yh_rest_of_patch.patch (probably not).


It should rename ROM_STREAM to ROM_PAYLOAD in Config.lb and Options.lb of
mainboard directory , otherwise it can't compile.

bxshi
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From a1426z at gawab.com  Wed Feb 14 13:11:56 2007
From: a1426z at gawab.com (Al Boldi)
Date: Wed, 14 Feb 2007 15:11:56 +0300
Subject: [LinuxBIOS] is this motherboard supported? VIA EPIA-SP13000
In-Reply-To: <20070212004205.26105.qmail@cdy.org>
References: <208434.14445.qm@web35607.mail.mud.yahoo.com>
	<20070212004205.26105.qmail@cdy.org>
Message-ID: <200702141511.56291.a1426z@gawab.com>

Peter Stuge wrote:
> On Sun, Feb 11, 2007 at 02:08:52AM -0800, Pablo Sosa wrote:
> > Hope this is the right forum to ask. I was checking the list of
> > supported motherboards in order to try linuxbios, I could find I
> > can buy one of this motherboards which are similar but not the same
> > to VIA that are mentioned on the page, i.e.
> >
> > VIA EPIA-SP13000 Motherboard, Socket 370
> > Specs according to the vendor are:
> >
> > Specifications:
> >
> >  - Processor: VIA C3 / VIA Eden  EBGA processor
> >  - Chipset: VIA CN400 North Bridge; VIA VT8237 South Bridge
>
> [..]
>
> > So I'm a bit confused and wouldn't like to buy something that's
> > unable to support linuxbios, I'll appreciate if someone can help
> > me, or give me some advice
>
> Your research is correct. The EPIA-SP boards use a lot of hardware
> different from the EPIA-MII and most of it is yet unsupported in
> LinuxBIOS.

It seems that this is a recurring problem with many boards.

Would it be possible to reduce dependencies, by having a minimal/blind 
CPU/memory bootstrapper with a kernel payload to discover the rest of the 
system?


Thanks!

--
Al




From roze at roze.mine.nu  Wed Feb 14 09:42:04 2007
From: roze at roze.mine.nu (Jonas Lihnell)
Date: Wed, 14 Feb 2007 09:42:04 +0100
Subject: [LinuxBIOS] dmidecode + lspci output.
Message-ID: <200702140942.05301.roze@roze.mine.nu>

# dmidecode 2.8
SMBIOS 2.3 present.
25 structures occupying 645 bytes.
Table at 0x000F0800.

Handle 0x0000, DMI type 1, 25 bytes
System Information
        Manufacturer:
        Product Name:
        Version:
        Serial Number:
        UUID: Not Present
        Wake-up Type: Power Switch

Handle 0x0001, DMI type 2, 8 bytes
Base Board Information
        Manufacturer:
        Product Name: CN700-8237R
        Version:
        Serial Number:

Handle 0x0002, DMI type 3, 17 bytes
Chassis Information
        Manufacturer:
        Type: Desktop
        Lock: Not Present
        Version:
        Serial Number:
        Asset Tag:
        Boot-up State: Unknown
        Power Supply State: Unknown
        Thermal State: Unknown
        Security Status: Unknown
        OEM Information: 0x00000000

Handle 0x0003, DMI type 4, 35 bytes
Processor Information
        Socket Designation: NanoBGA2
        Type: Central Processor
        Family: Other
        Manufacturer: VIA
        ID: A9 06 00 00 FF BB C9 A7
        Version: VIA Eden
        Voltage: 0.8 V
        External Clock: 100 MHz
        Max Speed: 2000 MHz
        Current Speed: 1200 MHz
        Status: Populated, Enabled
        Upgrade: None
        L1 Cache Handle: 0x0006
        L2 Cache Handle: 0x0007
        L3 Cache Handle: Not Provided
        Serial Number:
        Asset Tag:
        Part Number:

Handle 0x0004, DMI type 5, 18 bytes
Memory Controller Information
        Error Detecting Method: None
        Error Correcting Capabilities:
                None
        Supported Interleave: Eight-way Interleave
        Current Interleave: Four-way Interleave
        Maximum Memory Module Size: 1024 MB
        Maximum Total Memory Size: 1024 MB
        Supported Speeds:
                70 ns
                60 ns
        Supported Memory Types:
                DIMM
                SDRAM
        Memory Module Voltage: 2.9 V
        Associated Memory Slots: 1
                0x0005
        Enabled Error Correcting Capabilities: None

Handle 0x0005, DMI type 6, 12 bytes
Memory Module Information
        Socket Designation: A0
        Bank Connections: 0
        Current Speed: 37 ns
        Type: Other
        Installed Size: 512 MB (Single-bank Connection)
        Enabled Size: 512 MB (Single-bank Connection)
        Error Status: OK

Handle 0x0006, DMI type 7, 19 bytes
Cache Information
        Socket Designation: Internal Cache
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Write Back
        Location: Internal
        Installed Size: 32 KB
        Maximum Size: 32 KB
        Supported SRAM Types:
                Synchronous
        Installed SRAM Type: Synchronous
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Unknown
        Associativity: 4-way Set-associative

Handle 0x0007, DMI type 7, 19 bytes
Cache Information
        Socket Designation: Internal Cache
        Configuration: Enabled, Not Socketed, Level 2
        Operational Mode: Write Back
        Location: External
        Installed Size: 0 KB
        Maximum Size: 0 KB
        Supported SRAM Types:
                Synchronous
        Installed SRAM Type: Synchronous
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Unknown
        Associativity: Unknown

Handle 0x0008, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: PRIMARY IDE
        Internal Connector Type: On Board IDE
        External Reference Designator: Not Specified
        External Connector Type: None
        Port Type: Other

Handle 0x0009, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: SECONDARY IDE
        Internal Connector Type: On Board IDE
        External Reference Designator: Not Specified
        External Connector Type: None
        Port Type: Other

Handle 0x000A, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: FDD
        Internal Connector Type: On Board Floppy
        External Reference Designator: Not Specified
        External Connector Type: None
        Port Type: 8251 FIFO Compatible

Handle 0x000B, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: COM1
        Internal Connector Type: 9 Pin Dual Inline (pin 10 cut)
        External Reference Designator:
        External Connector Type: DB-9 male
        Port Type: Serial Port 16450 Compatible

Handle 0x000C, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: COM2
        Internal Connector Type: 9 Pin Dual Inline (pin 10 cut)
        External Reference Designator:
        External Connector Type: DB-9 male
        Port Type: Serial Port 16450 Compatible

Handle 0x000D, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: LPT1
        Internal Connector Type: DB-25 female
        External Reference Designator:
        External Connector Type: DB-25 female
        Port Type: Parallel Port ECP/EPP

Handle 0x000E, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Keyboard
        Internal Connector Type: PS/2
        External Reference Designator:
        External Connector Type: PS/2
        Port Type: Keyboard Port

Handle 0x000F, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: PS/2 Mouse
        Internal Connector Type: PS/2
        External Reference Designator:
        External Connector Type: PS/2
        Port Type: Mouse Port

Handle 0x0010, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: USB0
        External Connector Type: Other
        Port Type: USB

Handle 0x0011, DMI type 9, 13 bytes
System Slot Information
        Designation: PCI0
        Type: 32-bit PCI
        Current Usage: Available
        Length: Long
        ID: 1
        Characteristics:
                5.0 V is provided
                PME signal is supported

Handle 0x0012, DMI type 13, 22 bytes
BIOS Language Information
        Installable Languages: 3
                n|US|iso8859-1
                r|CA|iso8859-1
                a|JP|unicode
        Currently Installed Language: n|US|iso8859-1

Handle 0x0013, DMI type 16, 15 bytes
Physical Memory Array
        Location: System Board Or Motherboard
        Use: System Memory
        Error Correction Type: None
        Maximum Capacity: 512 MB
        Error Information Handle: Not Provided
        Number Of Devices: 1

Handle 0x0014, DMI type 17, 27 bytes
Memory Device
        Array Handle: 0x0013
        Error Information Handle: Not Provided
        Total Width: Unknown
        Data Width: Unknown
        Size: 512 MB
        Form Factor: DIMM
        Set: None
        Locator: A0
        Bank Locator: Bank0/1
        Type: Unknown
        Type Detail: None
        Speed: Unknown
        Manufacturer: None
        Serial Number: None
        Asset Tag: None
        Part Number: None

Handle 0x0015, DMI type 19, 15 bytes
Memory Array Mapped Address
        Starting Address: 0x00000000000
        Ending Address: 0x0001FFFFFFF
        Range Size: 512 MB
        Physical Array Handle: 0x0013
        Partition Width: 0

Handle 0x0016, DMI type 20, 19 bytes
Memory Device Mapped Address
        Starting Address: 0x00000000000
        Ending Address: 0x0001FFFFFFF
        Range Size: 512 MB
        Physical Device Handle: 0x0014
        Memory Array Mapped Address Handle: 0x0015
        Partition Row Position: 1

Handle 0x0017, DMI type 32, 11 bytes
System Boot Information
        Status: No errors detected

Handle 0x0018, DMI type 127, 4 bytes
End Of Table

MiniNix roze # lspci -n
00:00.0 0600: 1106:0314
00:00.1 0600: 1106:1314
00:00.2 0600: 1106:2314
00:00.3 0600: 1106:3208
00:00.4 0600: 1106:4314
00:00.7 0600: 1106:7314
00:01.0 0604: 1106:b198
00:0d.0 0c00: 1106:3044 (rev 80)
00:0e.0 0200: 1106:3119 (rev 11)
00:0f.0 0104: 1106:3149 (rev 80)
00:0f.1 0101: 1106:0571 (rev 06)
00:10.0 0c03: 1106:3038 (rev 81)
00:10.1 0c03: 1106:3038 (rev 81)
00:10.2 0c03: 1106:3038 (rev 81)
00:10.4 0c03: 1106:3104 (rev 86)
00:11.0 0601: 1106:3227
00:11.5 0401: 1106:3059 (rev 60)
01:00.0 0300: 1106:3344 (rev 01)
MiniNix roze # lspci -v
00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host 
Bridge
        Subsystem: VIA Technologies, Inc. Unknown device aa08
        Flags: bus master, 66MHz, medium devsel, latency 8
        Memory at f0000000 (32-bit, prefetchable) [size=64M]
        Capabilities: [80] AGP version 3.5
        Capabilities: [50] Power Management version 2

00:00.1 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host 
Bridge
        Flags: bus master, medium devsel, latency 0

00:00.2 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host 
Bridge
        Flags: bus master, medium devsel, latency 0

00:00.3 Host bridge: VIA Technologies, Inc. PT890 Host Bridge
        Flags: bus master, medium devsel, latency 0

00:00.4 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host 
Bridge
        Flags: bus master, medium devsel, latency 0

00:00.7 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host 
Bridge
        Flags: bus master, medium devsel, latency 0

00:01.0 PCI bridge: VIA Technologies, Inc. VT8237 PCI Bridge (prog-if 00 
[Normal decode])
        Flags: bus master, 66MHz, medium devsel, latency 0
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
        I/O behind bridge: 0000b000-0000bfff
        Memory behind bridge: fb000000-fcffffff
        Prefetchable memory behind bridge: f4000000-f7ffffff
        Capabilities: [70] Power Management version 2

00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller 
(rev 80) (prog-if 10 [OHCI])
        Subsystem: VIA Technologies, Inc. IEEE 1394 Host Controller
        Flags: bus master, stepping, medium devsel, latency 32, IRQ 17
        Memory at fdfff000 (32-bit, non-prefetchable) [size=2K]
        I/O ports at fc00 [size=128]
        Capabilities: [50] Power Management version 2

00:0e.0 Ethernet controller: VIA Technologies, Inc. VT6120/VT6121/VT6122 
Gigabit Ethernet Adapter (rev 11)
        Subsystem: VIA Technologies, Inc. Unknown device 0110
        Flags: bus master, 66MHz, medium devsel, latency 32, IRQ 18
        I/O ports at f800 [size=256]
        Memory at fdffe000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2

00:0f.0 RAID bus controller: VIA Technologies, Inc. VIA VT6420 SATA RAID 
Controller (rev 80)
        Subsystem: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller
        Flags: bus master, medium devsel, latency 32, IRQ 16
        I/O ports at f400 [size=8]
        I/O ports at f000 [size=4]
        I/O ports at ec00 [size=8]
        I/O ports at e800 [size=4]
        I/O ports at e400 [size=16]
        I/O ports at e000 [size=256]
        Capabilities: [c0] Power Management version 2

00:0f.1 IDE interface: VIA Technologies, Inc. 
VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a 
[Master SecP PriP])
        Subsystem: VIA Technologies, Inc. 
VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE
        Flags: bus master, medium devsel, latency 32, IRQ 16
        [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8]
        [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1]
        [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8]
        [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1]
        I/O ports at dc00 [size=16]
        Capabilities: [c0] Power Management version 2

00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 
Controller (rev 81) (prog-if 00 [UHCI])
        Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
        Flags: bus master, medium devsel, latency 32, IRQ 19
        I/O ports at d800 [size=32]
        Capabilities: [80] Power Management version 2

00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 
Controller (rev 81) (prog-if 00 [UHCI])
        Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
        Flags: bus master, medium devsel, latency 32, IRQ 19
        I/O ports at d400 [size=32]
        Capabilities: [80] Power Management version 2

00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 
Controller (rev 81) (prog-if 00 [UHCI])
        Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
        Flags: bus master, medium devsel, latency 32, IRQ 19
        I/O ports at d000 [size=32]
        Capabilities: [80] Power Management version 2

00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86) (prog-if 20 
[EHCI])
        Subsystem: VIA Technologies, Inc. USB 2.0
        Flags: bus master, medium devsel, latency 32, IRQ 19
        Memory at fdffd000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [80] Power Management version 2

00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge 
[KT600/K8T800/K8T890 South]
        Subsystem: VIA Technologies, Inc. Unknown device aa08
        Flags: bus master, stepping, medium devsel, latency 0
        Capabilities: [c0] Power Management version 2

00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233/A/8235/8237 
AC97 Audio Controller (rev 60)
        Subsystem: VIA Technologies, Inc. Unknown device aa08
        Flags: medium devsel, IRQ 20
        I/O ports at c800 [size=256]
        Capabilities: [c0] Power Management version 2

01:00.0 VGA compatible controller: VIA Technologies, Inc. UniChrome Pro IGP 
(rev 01) (prog-if 00 [VGA])
        Subsystem: VIA Technologies, Inc. UniChrome Pro IGP
        Flags: bus master, 66MHz, medium devsel, latency 32, IRQ 21
        Memory at f4000000 (32-bit, prefetchable) [size=64M]
        Memory at fb000000 (32-bit, non-prefetchable) [size=16M]
        [virtual] Expansion ROM at fc000000 [disabled] [size=64K]
        Capabilities: [60] Power Management version 2
        Capabilities: [70] AGP version 3.0

MiniNix roze # lspci -t
-[0000:00]-+-00.0
           +-00.1
           +-00.2
           +-00.3
           +-00.4
           +-00.7
           +-01.0-[0000:01]----00.0
           +-0d.0
           +-0e.0
           +-0f.0
           +-0f.1
           +-10.0
           +-10.1
           +-10.2
           +-10.4
           +-11.0
           \-11.5



From eswierk at arastra.com  Wed Feb 14 19:41:52 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Wed, 14 Feb 2007 10:41:52 -0800
Subject: [LinuxBIOS] [PATCH] Additional MCP55 LPC PCI IDs for flashrom
Message-ID: <c1bf1cf0702141041idfcdb8fma5be75b25c50f889@mail.gmail.com>

The attached patch adds additional PCI IDs for MCP55 LPC devices to
flashrom. 0x0360 is needed to support the DFI LANParty NF590SLI, and I
am deducing the others based on pci_ids.h in the Linux kernel. Perhaps
Yinghai can confirm that these are correct.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From eswierk at arastra.com  Wed Feb 14 19:45:46 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Wed, 14 Feb 2007 10:45:46 -0800
Subject: [LinuxBIOS] [PATCH] flashrom Makefile message improvements
Message-ID: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>

Currently the flashrom Makefile tries to detect whether pciutils-devel
is installed, but the test also fails if zlib-devel is missing. This
patch changes the error message accordingly.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From peilien at yahoo.com  Wed Feb 14 22:04:23 2007
From: peilien at yahoo.com (Perry Wang)
Date: Wed, 14 Feb 2007 13:04:23 -0800
Subject: [LinuxBIOS] Question about PCI Config Space byte rd/wr in HT
In-Reply-To: <fc76582a84a71f0ecb3d5dc01b2cddf4@kernel.crashing.org>
Message-ID: <mailman.173.1355071059.16123.coreboot@coreboot.org>

Thanks for the clarification.

The reason I had some doubts is that there are devices out there that don't
support byte access in config space (at least one HT IP vendor doesn't seem
to support it) and I've been wondering how people have been able to go get
away with this.

I just read the PCI spec and it says that the address during config cycles
is dword address, but I also saw some byte enable signals so it looks like
it's definitely possible to issue byte access to config space in the PCI
world.  

Regards,
Perry

> -----Original Message-----
> From: Segher Boessenkool [mailto:segher at kernel.crashing.org]
> Sent: Tuesday, February 13, 2007 12:20 PM
> To: Perry Wang
> Cc: linuxbios at linuxbios.org
> Subject: Re: [LinuxBIOS] Question about PCI Config Space byte rd/wr in HT
> 
> [Don't reply to an unrelated post, please start a new
> thread instead].
> 
> > If software tries to do a byte rd/wr access to PCI config access, say
> > in
> > linux or BIOS, how would it show up on the HT bus?
> 
> As a byte access to config space -- what else?
> 
> Read the HT specification (from hypertransport.org)
> if you need to know the details.
> 
> > I'm assuming that config space access is initiated through the
> > southbridge.
> 
> It's done on the CPU chip (it detects accesses to
> legacy I/O address 0xfc8/0xcfc).
> 
> > Anyone know if an HT device will ever have to expect byte access to its
> > config space?
> 
> Yes, some people know.  Yes, they have to expect (and
> allow) byte accesses.
> 
> 
> Segher




From kristoffer.lunden at gmail.com  Thu Feb 15 00:56:00 2007
From: kristoffer.lunden at gmail.com (=?UTF-8?Q?Kristoffer_Lund=C3=A9n?=)
Date: Thu, 15 Feb 2007 00:56:00 +0100
Subject: [LinuxBIOS] dmidecode + lspci
Message-ID: <d1a198ae0702141556g35e94bb4o829daafe5b873aae@mail.gmail.com>

$ dmidecode
# dmidecode 2.8
SMBIOS 2.3 present.
54 structures occupying 2105 bytes.
Table at 0x000FA550.

Handle 0x0000, DMI type 0, 20 bytes
BIOS Information
    Vendor: American Megatrends Inc.
    Version: 1.10C
    Release Date: 10/05/2005
    Address: 0xF0000
    Runtime Size: 64 kB
    ROM Size: 512 kB
    Characteristics:
        ISA is supported
        PCI is supported
        PNP is supported
        APM is supported
        BIOS is upgradeable
        BIOS shadowing is allowed
        ESCD support is available
        Boot from CD is supported
        Selectable boot is supported
        BIOS ROM is socketed
        EDD is supported
        5.25"/1.2 MB floppy services are supported (int 13h)
        3.5"/720 KB floppy services are supported (int 13h)
        3.5"/2.88 MB floppy services are supported (int 13h)
        Print screen service is supported (int 5h)
        8042 keyboard services are supported (int 9h)
        Serial services are supported (int 14h)
        Printer services are supported (int 17h)
        CGA/mono video services are supported (int 10h)
        ACPI is supported
        USB legacy is supported
        LS-120 boot is supported
        ATAPI Zip drive boot is supported
        BIOS boot specification is supported

Handle 0x0001, DMI type 1, 25 bytes
System Information
    Manufacturer: FUJITSU SIEMENS
    Product Name: Amilo M3438 Series
    Version:
    Serial Number: 71EE192B
    UUID: C8991985-74FE-D511-ADC4-DFE4577BD973
    Wake-up Type: Power Switch

Handle 0x0002, DMI type 2, 15 bytes
Base Board Information
    Manufacturer:
    Product Name: P71EN0
    Version:
    Serial Number:
    Asset Tag:
    Features:
        Board is a hosting board
        Board is replaceable
    Location In Chassis:
    Chassis Handle: 0x0003
    Type: Motherboard
    Contained Object Handles: 0

Handle 0x0003, DMI type 3, 21 bytes
Chassis Information
    Manufacturer: FUJITSU SIEMENS
    Type: Notebook
    Lock: Not Present
    Version:
    Serial Number:
    Asset Tag:
    Boot-up State: Safe
    Power Supply State: Safe
    Thermal State: Safe
    Security Status: None
    OEM Information: 0x00000000
    Heigth: Unspecified
    Number Of Power Cords: 1
    Contained Elements: 0

Handle 0x0004, DMI type 4, 35 bytes
Processor Information
    Socket Designation: CPU 1
    Type: Central Processor
    Family: Other
    Manufacturer: Intel
    ID: D8 06 00 00 FF FB E9 AF
    Version: Intel(R) Pentium(R) M processor 740
    Voltage: 3.3 V 2.9 V
    External Clock: 532 MHz
    Max Speed: 1729 MHz
    Current Speed: 1729 MHz
    Status: Populated, Enabled
    Upgrade: Other
    L1 Cache Handle: 0x0005
    L2 Cache Handle: 0x0006
    L3 Cache Handle: 0x0007
    Serial Number: To Be Filled By O.E.M.
    Asset Tag: To Be Filled By O.E.M.
    Part Number: To Be Filled By O.E.M.

Handle 0x0005, DMI type 7, 19 bytes
Cache Information
    Socket Designation: L1-Cache
    Configuration: Enabled, Not Socketed, Level 1
    Operational Mode: Varies With Memory Address
    Location: Internal
    Installed Size: 32 KB
    Maximum Size: 32 KB
    Supported SRAM Types:
        Pipeline Burst
    Installed SRAM Type: Pipeline Burst
    Speed: Unknown
    Error Correction Type: Single-bit ECC
    System Type: Data
    Associativity: 4-way Set-associative

Handle 0x0006, DMI type 7, 19 bytes
Cache Information
    Socket Designation: L2-Cache
    Configuration: Enabled, Not Socketed, Level 2
    Operational Mode: Varies With Memory Address
    Location: Internal
    Installed Size: 2048 KB
    Maximum Size: 2048 KB
    Supported SRAM Types:
        Pipeline Burst
    Installed SRAM Type: Pipeline Burst
    Speed: Unknown
    Error Correction Type: Single-bit ECC
    System Type: Unified
    Associativity: 4-way Set-associative

Handle 0x0007, DMI type 7, 19 bytes
Cache Information
    Socket Designation: L3-Cache
    Configuration: Disabled, Not Socketed, Level 3
    Operational Mode: Unknown
    Location: Internal
    Installed Size: 0 KB
    Maximum Size: 0 KB
    Supported SRAM Types:
        Unknown
    Installed SRAM Type: Unknown
    Speed: Unknown
    Error Correction Type: Unknown
    System Type: Unknown
    Associativity: Unknown

Handle 0x0008, DMI type 5, 24 bytes
Memory Controller Information
    Error Detecting Method: 64-bit ECC
    Error Correcting Capabilities:
        None
    Supported Interleave: One-way Interleave
    Current Interleave: One-way Interleave
    Maximum Memory Module Size: 4096 MB
    Maximum Total Memory Size: 16384 MB
    Supported Speeds:
        Other
    Supported Memory Types:
        DIMM
        SDRAM
    Memory Module Voltage: 3.3 V
    Associated Memory Slots: 4
        0x0009
        0x000A
        0x000B
        0x000C
    Enabled Error Correcting Capabilities:
        None

Handle 0x0009, DMI type 6, 12 bytes
Memory Module Information
    Socket Designation: DIMM0
    Bank Connections: 1 2
    Current Speed: Unknown
    Type: DIMM SDRAM
    Installed Size: 512 MB (Double-bank Connection)
    Enabled Size: 512 MB (Double-bank Connection)
    Error Status: OK

Handle 0x000A, DMI type 6, 12 bytes
Memory Module Information
    Socket Designation: DIMM1
    Bank Connections: None
    Current Speed: Unknown
    Type: DIMM SDRAM
    Installed Size: Not Installed
    Enabled Size: Not Installed
    Error Status: OK

Handle 0x000B, DMI type 6, 12 bytes
Memory Module Information
    Socket Designation: DIMM2
    Bank Connections: 5 6
    Current Speed: Unknown
    Type: DIMM SDRAM
    Installed Size: 512 MB (Double-bank Connection)
    Enabled Size: 512 MB (Double-bank Connection)
    Error Status: OK

Handle 0x000C, DMI type 6, 12 bytes
Memory Module Information
    Socket Designation: DIMM3
    Bank Connections: None
    Current Speed: Unknown
    Type: DIMM SDRAM
    Installed Size: Not Installed
    Enabled Size: Not Installed
    Error Status: OK

Handle 0x000D, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J1A1
    Internal Connector Type: None
    External Reference Designator: PS2Mouse
    External Connector Type: PS/2
    Port Type: Mouse Port

Handle 0x000E, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J1A1
    Internal Connector Type: None
    External Reference Designator: Keyboard
    External Connector Type: PS/2
    Port Type: Keyboard Port

Handle 0x000F, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J2A2
    Internal Connector Type: None
    External Reference Designator: USB1
    External Connector Type: Access Bus (USB)
    Port Type: USB

Handle 0x0010, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J2A2
    Internal Connector Type: None
    External Reference Designator: USB2
    External Connector Type: Access Bus (USB)
    Port Type: USB

Handle 0x0011, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J4A1
    Internal Connector Type: None
    External Reference Designator: LPT 1
    External Connector Type: DB-25 male
    Port Type: Parallel Port ECP/EPP

Handle 0x0012, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J2A1
    Internal Connector Type: None
    External Reference Designator: COM A
    External Connector Type: DB-9 male
    Port Type: Serial Port 16550A Compatible

Handle 0x0013, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J6A1
    Internal Connector Type: None
    External Reference Designator: Audio Mic In
    External Connector Type: Mini Jack (headphones)
    Port Type: Audio Port

Handle 0x0014, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J6A1
    Internal Connector Type: None
    External Reference Designator: Audio Line In
    External Connector Type: Mini Jack (headphones)
    Port Type: Audio Port

Handle 0x0015, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J6B1 - AUX IN
    Internal Connector Type: On Board Sound Input From CD-ROM
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Audio Port

Handle 0x0016, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J6B2 - CDIN
    Internal Connector Type: On Board Sound Input From CD-ROM
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Audio Port

Handle 0x0017, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J6J2 - PRI IDE
    Internal Connector Type: On Board IDE
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0018, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J6J1 - SEC IDE
    Internal Connector Type: On Board IDE
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0019, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J4J1 - FLOPPY
    Internal Connector Type: On Board Floppy
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x001A, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J9H1 - FRONT PNL
    Internal Connector Type: 9 Pin Dual Inline (pin 10 cut)
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x001B, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J1B1 - CHASSIS REAR FAN
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x001C, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J2F1 - CPU FAN
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x001D, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J8B4 - FRONT FAN
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x001E, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J9G2 - FNT USB
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x001F, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J6C3 - FP AUD
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0020, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J9G1 - CONFIG
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0021, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J8C1 - SCSI LED
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0022, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J9J2 - INTRUDER
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0023, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J9G4 - ITP
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0024, DMI type 8, 9 bytes
Port Connector Information
    Internal Reference Designator: J2H1 - MAIN POWER
    Internal Connector Type: Other
    External Reference Designator: Not Specified
    External Connector Type: None
    Port Type: Other

Handle 0x0025, DMI type 9, 13 bytes
System Slot Information
    Designation: AGP
    Type: 32-bit AGP 4x
    Current Usage: In Use
    Length: Short
    ID: 0
    Characteristics:
        3.3 V is provided
        Opening is shared
        PME signal is supported

Handle 0x0026, DMI type 9, 13 bytes
System Slot Information
    Designation: PCI1
    Type: 32-bit PCI
    Current Usage: Available
    Length: Short
    ID: 1
    Characteristics:
        3.3 V is provided
        Opening is shared
        PME signal is supported

Handle 0x0027, DMI type 10, 6 bytes
On Board Device Information
    Type: Video
    Status: Enabled
    Description:   To Be Filled By O.E.M.

Handle 0x0028, DMI type 13, 22 bytes
BIOS Language Information
    Installable Languages: 1
        en|US|iso8859-1
    Currently Installed Language: en|US|iso8859-1

Handle 0x0029, DMI type 15, 55 bytes
System Event Log
    Area Length: 1008 bytes
    Header Start Offset: 0x1810
    Header Length: 16 bytes
    Data Start Offset: 0x1820
    Access Method: General-purpose non-volatile data functions
    Access Address: 0x0002
    Status: Valid, Not Full
    Change Token: 0x00000000
    Header Format: Type 1
    Supported Log Type Descriptors: 9
    Descriptor 1: Single-bit ECC memory error
    Data Format 1: Multiple-event handle
    Descriptor 2: Multi-bit ECC memory error
    Data Format 2: Multiple-event handle
    Descriptor 3: Parity memory error
    Data Format 3: Multiple-event
    Descriptor 4: I/O channel block
    Data Format 4: Multiple-event
    Descriptor 5: POST error
    Data Format 5: POST results bitmap
    Descriptor 6: PCI parity error
    Data Format 6: Multiple-event handle
    Descriptor 7: PCI system error
    Data Format 7: Multiple-event handle
    Descriptor 8: System limit exceeded
    Data Format 8: Multiple-event system management
    Descriptor 9: OEM-specific
    Data Format 9: POST results bitmap

Handle 0x002A, DMI type 16, 15 bytes
Physical Memory Array
    Location: System Board Or Motherboard
    Use: System Memory
    Error Correction Type: None
    Maximum Capacity: 4 GB
    Error Information Handle: Not Provided
    Number Of Devices: 4

Handle 0x002B, DMI type 19, 15 bytes
Memory Array Mapped Address
    Starting Address: 0x00000000000
    Ending Address: 0x000400003FF
    Range Size: 1048577 kB
    Physical Array Handle: 0x002A
    Partition Width: 0

Handle 0x002C, DMI type 17, 27 bytes
Memory Device
    Array Handle: 0x002A
    Error Information Handle: Not Provided
    Total Width: 64 bits
    Data Width: 64 bits
    Size: 512 MB
    Form Factor: DIMM
    Set: None
    Locator: DIMM0
    Bank Locator: BANK0
    Type: DDR
    Type Detail: Synchronous
    Speed: Unknown
    Manufacturer: Manufacturer0
    Serial Number: SerNum0
    Asset Tag: AssetTagNum0
    Part Number: PartNum0

Handle 0x002D, DMI type 20, 19 bytes
Memory Device Mapped Address
    Starting Address: 0x00000000000
    Ending Address: 0x0001FFFFFFF
    Range Size: 512 MB
    Physical Device Handle: 0x002C
    Memory Array Mapped Address Handle: 0x002B
    Partition Row Position: 1
    Interleaved Data Depth: 1

Handle 0x002E, DMI type 17, 27 bytes
Memory Device
    Array Handle: 0x002A
    Error Information Handle: Not Provided
    Total Width: Unknown
    Data Width: 64 bits
    Size: No Module Installed
    Form Factor: DIMM
    Set: None
    Locator: DIMM1
    Bank Locator: BANK1
    Type: Unknown
    Type Detail: Unknown
    Speed: Unknown
    Manufacturer: Manufacturer1
    Serial Number: SerNum1
    Asset Tag: AssetTagNum1
    Part Number: PartNum1

Handle 0x002F, DMI type 126, 19 bytes
Inactive

Handle 0x0030, DMI type 17, 27 bytes
Memory Device
    Array Handle: 0x002A
    Error Information Handle: Not Provided
    Total Width: 64 bits
    Data Width: 64 bits
    Size: 512 MB
    Form Factor: DIMM
    Set: None
    Locator: DIMM2
    Bank Locator: BANK2
    Type: DDR
    Type Detail: Synchronous
    Speed: Unknown
    Manufacturer: Manufacturer2
    Serial Number: SerNum2
    Asset Tag: AssetTagNum2
    Part Number: PartNum2

Handle 0x0031, DMI type 20, 19 bytes
Memory Device Mapped Address
    Starting Address: 0x00020000000
    Ending Address: 0x0003FFFFFFF
    Range Size: 512 MB
    Physical Device Handle: 0x0030
    Memory Array Mapped Address Handle: 0x002B
    Partition Row Position: 1
    Interleaved Data Depth: 1

Handle 0x0032, DMI type 17, 27 bytes
Memory Device
    Array Handle: 0x002A
    Error Information Handle: Not Provided
    Total Width: Unknown
    Data Width: 64 bits
    Size: No Module Installed
    Form Factor: DIMM
    Set: None
    Locator: DIMM3
    Bank Locator: BANK3
    Type: Unknown
    Type Detail: Unknown
    Speed: Unknown
    Manufacturer: Manufacturer3
    Serial Number: SerNum3
    Asset Tag: AssetTagNum3
    Part Number: PartNum3

Handle 0x0033, DMI type 126, 19 bytes
Inactive

Handle 0x0034, DMI type 32, 20 bytes
System Boot Information
    Status: No errors detected

Handle 0x0035, DMI type 127, 4 bytes
End Of Table

$ lspci -n
00:00.0 0600: 8086:2590 (rev 04)
00:01.0 0604: 8086:2591 (rev 04)
00:1b.0 0403: 8086:2668 (rev 04)
00:1c.0 0604: 8086:2660 (rev 04)
00:1d.0 0c03: 8086:2658 (rev 04)
00:1d.1 0c03: 8086:2659 (rev 04)
00:1d.2 0c03: 8086:265a (rev 04)
00:1d.3 0c03: 8086:265b (rev 04)
00:1d.7 0c03: 8086:265c (rev 04)
00:1e.0 0604: 8086:2448 (rev d4)
00:1f.0 0601: 8086:2641 (rev 04)
00:1f.1 0101: 8086:266f (rev 04)
00:1f.3 0c05: 8086:266a (rev 04)
01:03.0 0280: 8086:4220 (rev 05)
01:04.0 0c00: 104c:8023
01:05.0 0200: 10ec:8169 (rev 10)
01:07.0 0104: 1106:3249 (rev 50)
03:00.0 0300: 10de:00c8 (rev a2)

$ lspci -v
00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML
Express Processor to DRAM Controller (rev 04)
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, fast devsel, latency 0
    Capabilities: [e0] Vendor Specific Information

00:01.0 PCI bridge: Intel Corporation Mobile 915GM/PM Express PCI
Express Root Port (rev 04) (prog-if 00 [Normal decode])
    Flags: bus master, fast devsel, latency 0
    Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
    Memory behind bridge: faa00000-feafffff
    Prefetchable memory behind bridge: bfe00000-dfefffff
    Capabilities: [88] #0d [0000]
    Capabilities: [80] Power Management version 2
    Capabilities: [90] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
    Capabilities: [a0] Express Root Port (Slot+) IRQ 0

00:1b.0 Audio device: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) High Definition Audio Controller (rev 04)
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, fast devsel, latency 0, IRQ 169
    Memory at febf8000 (64-bit, non-prefetchable) [size=16K]
    Capabilities: [50] Power Management version 2
    Capabilities: [60] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
    Capabilities: [70] Express Unknown type IRQ 0

00:1c.0 PCI bridge: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) PCI Express Port 1 (rev 04) (prog-if 00 [Normal decode])
    Flags: bus master, fast devsel, latency 0
    Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
    I/O behind bridge: 0000d000-0000dfff
    Memory behind bridge: bfc00000-bfcfffff
    Prefetchable memory behind bridge: 00000000bfd00000-00000000bfd00000
    Capabilities: [40] Express Root Port (Slot+) IRQ 0
    Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
    Capabilities: [90] #0d [0000]
    Capabilities: [a0] Power Management version 2

00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #1 (rev 04) (prog-if 00 [UHCI])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 0, IRQ 209
    I/O ports at e480 [size=32]

00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #2 (rev 04) (prog-if 00 [UHCI])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 0, IRQ 217
    I/O ports at e800 [size=32]

00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #3 (rev 04) (prog-if 00 [UHCI])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 0, IRQ 201
    I/O ports at e880 [size=32]

00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB UHCI #4 (rev 04) (prog-if 00 [UHCI])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 0, IRQ 169
    I/O ports at ec00 [size=32]

00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB2 EHCI Controller (rev 04) (prog-if 20 [EHCI])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 0, IRQ 209
    Memory at febffc00 (32-bit, non-prefetchable) [size=1K]
    Capabilities: [50] Power Management version 2
    Capabilities: [58] Debug port

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d4)
(prog-if 01 [Subtractive decode])
    Flags: bus master, fast devsel, latency 0
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
    I/O behind bridge: 00001000-00001fff
    Memory behind bridge: fa900000-fa9fffff
    Prefetchable memory behind bridge: 0000000050000000-0000000050000000
    Capabilities: [50] #0d [0000]

00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface
Bridge (rev 04)
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 0

00:1f.1 IDE interface: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) IDE Controller (rev 04) (prog-if 8a [Master SecP PriP])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 0, IRQ 201
    I/O ports at <unassigned>
    I/O ports at <unassigned>
    I/O ports at <unassigned>
    I/O ports at <unassigned>
    I/O ports at ffa0 [size=16]

00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family)
SMBus Controller (rev 04)
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: medium devsel, IRQ 10
    I/O ports at 0400 [size=32]

01:03.0 Network controller: Intel Corporation PRO/Wireless 2200BG
Network Connection (rev 05)
    Subsystem: Intel Corporation Unknown device 2702
    Flags: bus master, medium devsel, latency 64, IRQ 217
    Memory at fa9fe000 (32-bit, non-prefetchable) [size=4K]
    Capabilities: [dc] Power Management version 2

01:04.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22/A
IEEE-1394a-2000 Controller (PHY/Link) (prog-if 10 [OHCI])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 64, IRQ 201
    Memory at fa9ff000 (32-bit, non-prefetchable) [size=2K]
    Memory at fa9f8000 (32-bit, non-prefetchable) [size=16K]
    Capabilities: [44] Power Management version 2

01:05.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169
Gigabit Ethernet (rev 10)
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 217
    I/O ports at c800 [size=256]
    Memory at fa9ffc00 (32-bit, non-prefetchable) [size=256]
    Expansion ROM at 50000000 [disabled] [size=128K]
    Capabilities: [dc] Power Management version 2

01:07.0 RAID bus controller: VIA Technologies, Inc. VT6421 IDE RAID
Controller (rev 50)
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, medium devsel, latency 64, IRQ 169
    I/O ports at 1420 [size=16]
    I/O ports at 1430 [size=16]
    I/O ports at 1440 [size=16]
    I/O ports at 1450 [size=16]
    I/O ports at 1400 [size=32]
    I/O ports at 1000 [size=256]
    Capabilities: [e0] Power Management version 2

03:00.0 VGA compatible controller: nVidia Corporation NV41.8 [GeForce
Go 6800] (rev a2) (prog-if 00 [VGA])
    Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107c
    Flags: bus master, fast devsel, latency 0, IRQ 169
    Memory at fd000000 (32-bit, non-prefetchable) [size=16M]
    Memory at c0000000 (64-bit, prefetchable) [size=256M]
    Memory at fc000000 (64-bit, non-prefetchable) [size=16M]
    [virtual] Expansion ROM at feae0000 [disabled] [size=128K]
    Capabilities: [60] Power Management version 2
    Capabilities: [68] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
    Capabilities: [78] Express Endpoint IRQ 0

$ lspci -t
-[0000:00]-+-00.0
           +-01.0-[0000:03]----00.0
           +-1b.0
           +-1c.0-[0000:02]--
           +-1d.0
           +-1d.1
           +-1d.2
           +-1d.3
           +-1d.7
           +-1e.0-[0000:01]--+-03.0
           |                 +-04.0
           |                 +-05.0
           |                 \-07.0
           +-1f.0
           +-1f.1
           \-1f.3



-- 
Kristoffer Lund?n
? kristoffer.lunden at gmail.com
? kristoffer.lunden at gamemaker.nu
http://www.gamemaker.nu/
? 0704 48 98 77

From stuge-linuxbios at cdy.org  Thu Feb 15 03:21:53 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Thu, 15 Feb 2007 03:21:53 +0100
Subject: [LinuxBIOS] is this motherboard supported? VIA EPIA-SP13000
In-Reply-To: <200702141511.56291.a1426z@gawab.com>
References: <208434.14445.qm@web35607.mail.mud.yahoo.com>
	<20070212004205.26105.qmail@cdy.org>
	<200702141511.56291.a1426z@gawab.com>
Message-ID: <20070215022153.24359.qmail@cdy.org>

On Wed, Feb 14, 2007 at 03:11:56PM +0300, Al Boldi wrote:
> > Your research is correct. The EPIA-SP boards use a lot of
> > hardware different from the EPIA-MII and most of it is yet
> > unsupported in LinuxBIOS.
> 
> It seems that this is a recurring problem with many boards.

Yes, it is.


> Would it be possible to reduce dependencies, by having a
> minimal/blind CPU/memory bootstrapper with a kernel payload to
> discover the rest of the system?

This is indeed exactly what LinuxBIOS is.

LinuxBIOS is by definition quite hardware specific. It's task is to
know about all the tweaks and quirks of a certain set of hardware,
and tickle the hardware so that it behaves in a standard way.

We appreciate any help we can get in writing code for unsupported
hardware. This is becoming an increasingly complex task with new
technologies emerging every other month.

That said, I think that the V3 design and structure makes it easier
to structure the code further and have more general code. There has
already been some discussion about how to best generalize RAM
initialization e.g. which would be one good way to make porting a
little bit easiser and faster.

There's also the information problem, it's difficult to impossible
for LinuxBIOS as a group to acquire the neccessary datasheets that
detail how to set up the hardware, meaning many ports depend on
individuals who do have access to the documentation but are allowed
to release code.

And even AMD who support LinuxBIOS and contribute regularly in a
stellar manner have needed a lot of time for their legal department
to approve a code release.

It may sound like a crazy uphill battle, but I think the project is
doing well climbing up the hill, slow as it may be. :)


//Peter



From peilien at yahoo.com  Thu Feb 15 06:06:22 2007
From: peilien at yahoo.com (Perry Wang)
Date: Wed, 14 Feb 2007 21:06:22 -0800
Subject: [LinuxBIOS] HT interrupts
In-Reply-To: <fc76582a84a71f0ecb3d5dc01b2cddf4@kernel.crashing.org>
Message-ID: <mailman.174.1355071059.16123.coreboot@coreboot.org>

Hi,

Sorry to spam again but I couldn't figure out this on my own.  Questions:

1. Does LinuxBIOS actually program the HT interrupt definition registers
based on the interrupt capability and mobo config, or does Linux do this? Or
is it up to the driver?

2. What's the recommended way of doing HT interrupt that will work with both
APIC and 8259?  EOI seems to be APIC only (can be turned off in the
interrupt request) and I guess I can't rely on EOI to always be there?

3. EOI in a way acts as flow control.  So without EOI is it possible that I
can flood the PIC/APIC with too many interrupt packets?  I suppose the
credit based flow control in HT can take care of this...

Thanks again
Perry





From yinghailu at gmail.com  Thu Feb 15 07:18:01 2007
From: yinghailu at gmail.com (yhlu)
Date: Wed, 14 Feb 2007 22:18:01 -0800
Subject: [LinuxBIOS] HT interrupts
In-Reply-To: <45d3ea7d.26bf8bc1.277b.1115SMTPIN_ADDED@mx.google.com>
References: <fc76582a84a71f0ecb3d5dc01b2cddf4@kernel.crashing.org>
	<45d3ea7d.26bf8bc1.277b.1115SMTPIN_ADDED@mx.google.com>
Message-ID: <2ea3fae10702142218k597ac9a3o7ec6c21ee1574f4c@mail.gmail.com>

Eric already added HT int support to Linux kernel from 2.6.19.

you could use HT-MSI if you OS doesn't support HT irq directly.

YH

On 2/14/07, Perry Wang <peilien at yahoo.com> wrote:
> Hi,
>
> Sorry to spam again but I couldn't figure out this on my own.  Questions:
>
> 1. Does LinuxBIOS actually program the HT interrupt definition registers
> based on the interrupt capability and mobo config, or does Linux do this? Or
> is it up to the driver?
>
> 2. What's the recommended way of doing HT interrupt that will work with both
> APIC and 8259?  EOI seems to be APIC only (can be turned off in the
> interrupt request) and I guess I can't rely on EOI to always be there?
>
> 3. EOI in a way acts as flow control.  So without EOI is it possible that I
> can flood the PIC/APIC with too many interrupt packets?  I suppose the
> credit based flow control in HT can take care of this...
>
> Thanks again
> Perry
>
>
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios
>



From segher at kernel.crashing.org  Thu Feb 15 16:07:05 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Thu, 15 Feb 2007 16:07:05 +0100
Subject: [LinuxBIOS] HT interrupts
In-Reply-To: <200702150507.l1F57BKA023146@gate.crashing.org>
References: <200702150507.l1F57BKA023146@gate.crashing.org>
Message-ID: <84681d48d59edbab9018f05125df3049@kernel.crashing.org>

> Sorry to spam again but I couldn't figure out this on my own.  
> Questions:

You again replied to an unrelated message instead of starting
a new thread too, sigh.

> 1. Does LinuxBIOS actually program the HT interrupt definition 
> registers
> based on the interrupt capability and mobo config, or does Linux do 
> this? Or
> is it up to the driver?

LinuxBIOS has to do at least some of the configuration.  It
probably does it all, I didn't check.  Linux will at runtime
change some settings.  Unrelated device drivers do not touch
any of this.

> 2. What's the recommended way of doing HT interrupt that will work 
> with both
> APIC and 8259?  EOI seems to be APIC only (can be turned off in the
> interrupt request) and I guess I can't rely on EOI to always be there?

I have no idea what your question is.  You *have* to do EOI
on level triggered interrupts and you *have* to refrain from
using it on edge triggered interrupts, or things will go
(horribly and/or subtly) wrong.

> 3. EOI in a way acts as flow control.  So without EOI is it possible 
> that I
> can flood the PIC/APIC with too many interrupt packets?

No, only one interrupt packet is sent from the HT APIC over
the HT bus; and only one packet (the EOI packet) is sent
back.

> I suppose the
> credit based flow control in HT can take care of this...

That doesn't prevent flooding, it just prevents losing
packets.


Segher




From eswierk at arastra.com  Thu Feb 15 19:14:00 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 15 Feb 2007 10:14:00 -0800
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <dcdcf0740702131923o4616a784h128736bcaec92b6c@mail.gmail.com>
References: <20070213115345.GB30416@greenwood>
	<dcdcf0740702131923o4616a784h128736bcaec92b6c@mail.gmail.com>
Message-ID: <c1bf1cf0702151014q780b157frea2e3ce4660b3d53@mail.gmail.com>

On 2/13/07, bxshi <bingxunshi at gmail.com> wrote:
> It should rename ROM_STREAM to ROM_PAYLOAD in Config.lb and Options.lb of
> mainboard directory , otherwise it can't compile.

Here are the patches Uwe sent, with the following changes:

- changed STREAM options to PAYLOAD as necessary
- removed parts that would have undone STREAM -> PAYLOAD change
- removed a binary file
(targets/payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf)

I haven't done an abuild yet, but more changes are likely necessary.

--Ed
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From uwe at hermann-uwe.de  Thu Feb 15 20:54:03 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 15 Feb 2007 20:54:03 +0100
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <c1bf1cf0702151014q780b157frea2e3ce4660b3d53@mail.gmail.com>
References: <20070213115345.GB30416@greenwood>
	<dcdcf0740702131923o4616a784h128736bcaec92b6c@mail.gmail.com>
	<c1bf1cf0702151014q780b157frea2e3ce4660b3d53@mail.gmail.com>
Message-ID: <20070215195403.GA11790@greenwood>

Hi,

On Thu, Feb 15, 2007 at 10:14:00AM -0800, Ed Swierk wrote:
> Here are the patches Uwe sent, with the following changes:
> 
> - changed STREAM options to PAYLOAD as necessary
> - removed parts that would have undone STREAM -> PAYLOAD change
> - removed a binary file
> (targets/payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf)

Thanks a lot, but please resend the patch with your sign-off.

As for forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf -- do we need that, do
we have source code for it? Or is it just some test-payload which we can
safely ignore?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From rminnich at gmail.com  Thu Feb 15 21:23:09 2007
From: rminnich at gmail.com (ron minnich)
Date: Thu, 15 Feb 2007 13:23:09 -0700
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <20070215195403.GA11790@greenwood>
References: <20070213115345.GB30416@greenwood>
	<dcdcf0740702131923o4616a784h128736bcaec92b6c@mail.gmail.com>
	<c1bf1cf0702151014q780b157frea2e3ce4660b3d53@mail.gmail.com>
	<20070215195403.GA11790@greenwood>
Message-ID: <13426df10702151223q4cc55715q3fe922a8765b2707@mail.gmail.com>

can somebody get this committed now? The vendor is getting anxious :-)



thanks!

ron



From eswierk at arastra.com  Thu Feb 15 21:37:10 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 15 Feb 2007 12:37:10 -0800
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <c1bf1cf0702151234g2a327728mb66b0d648aa3c6a2@mail.gmail.com>
References: <20070213115345.GB30416@greenwood>
	<dcdcf0740702131923o4616a784h128736bcaec92b6c@mail.gmail.com>
	<c1bf1cf0702151014q780b157frea2e3ce4660b3d53@mail.gmail.com>
	<20070215195403.GA11790@greenwood>
	<c1bf1cf0702151234g2a327728mb66b0d648aa3c6a2@mail.gmail.com>
Message-ID: <c1bf1cf0702151237m4b716a59k1459baac1ec0afcf@mail.gmail.com>

On 2/15/07, Ed Swierk <eswierk at arastra.com> wrote:
> OK, but as I said, the patches haven't received any testing, so I'm
> not asserting that they work.

I should add that the patch may well break mainboards that are
currently working, so caveat emptor.

On the other hand, it will certainly be easier for us to collaborate
on fixing things once the code is committed.

--Ed



From eswierk at arastra.com  Thu Feb 15 21:34:35 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 15 Feb 2007 12:34:35 -0800
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <20070215195403.GA11790@greenwood>
References: <20070213115345.GB30416@greenwood>
	<dcdcf0740702131923o4616a784h128736bcaec92b6c@mail.gmail.com>
	<c1bf1cf0702151014q780b157frea2e3ce4660b3d53@mail.gmail.com>
	<20070215195403.GA11790@greenwood>
Message-ID: <c1bf1cf0702151234g2a327728mb66b0d648aa3c6a2@mail.gmail.com>

On 2/15/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> Thanks a lot, but please resend the patch with your sign-off.

OK, but as I said, the patches haven't received any testing, so I'm
not asserting that they work.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

> As for forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf -- do we need that, do
> we have source code for it? Or is it just some test-payload which we can
> safely ignore?

I'm assuming that it's just a FILO image with the forcedeth driver
from the Etherboot codebase, but only Yinghai would know for sure.

--Ed
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From uwe at hermann-uwe.de  Fri Feb 16 15:31:29 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 16 Feb 2007 15:31:29 +0100
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <20070213115345.GB30416@greenwood>
References: <20070213115345.GB30416@greenwood>
Message-ID: <20070216143129.GA22262@greenwood>

New version of the src/mainboard/ and targets/ contents, with license
headers added.

This can be committed IHMO. It won't build, but it shouldn't break
anything either. So:

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

I'm waiting for one more Ack before I commit.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Fri Feb 16 15:36:12 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri, 16 Feb 2007 15:36:12 +0100
Subject: [LinuxBIOS] r2553 - trunk/LinuxBIOSv2/util/flashrom
Message-ID: <mailman.175.1355071060.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-02-16 15:36:12 +0100 (Fri, 16 Feb 2007)
New Revision: 2553

Modified:
   trunk/LinuxBIOSv2/util/flashrom/Makefile
Log:
Currently the flashrom Makefile tries to detect whether pciutils-devel
is installed, but the test also fails if zlib-devel is missing. This
patch changes the error message accordingly.

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/util/flashrom/Makefile
===================================================================
--- trunk/LinuxBIOSv2/util/flashrom/Makefile	2007-02-09 00:26:10 UTC (rev 2552)
+++ trunk/LinuxBIOSv2/util/flashrom/Makefile	2007-02-16 14:36:12 UTC (rev 2553)
@@ -41,14 +41,14 @@
 	@$(CC) -MM *.c > .dependencies
 
 pciutils:
-	@echo; echo -n "Checking for pciutils... "
+	@echo; echo -n "Checking for pciutils and zlib... "
 	@$(shell ( echo "#include <pci/pci.h>";		   \
 		   echo "struct pci_access *pacc;";	   \
 		   echo "int main(int argc, char **argv)"; \
 		   echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c )
 	@$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null &&	\
 		echo "found." || ( echo "not found."; echo;		\
-		echo "Please install pciutils and pciutils-devel.";	\
+		echo "Please install pciutils-devel and zlib-devel.";	\
 		echo "See README for more information."; echo;		\
 		rm -f .test.c .test; exit 1)
 	@rm -f .test.c .test




From uwe at hermann-uwe.de  Fri Feb 16 15:37:08 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 16 Feb 2007 15:37:08 +0100
Subject: [LinuxBIOS] [PATCH] flashrom Makefile message improvements
In-Reply-To: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>
References: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>
Message-ID: <20070216143708.GB22262@greenwood>

Hi,

On Wed, Feb 14, 2007 at 10:45:46AM -0800, Ed Swierk wrote:
> Currently the flashrom Makefile tries to detect whether pciutils-devel
> is installed, but the test also fails if zlib-devel is missing. This
> patch changes the error message accordingly.

Committed, thanks!


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Feb 16 15:40:07 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 16 Feb 2007 15:40:07 +0100
Subject: [LinuxBIOS] [PATCH] Improve ITE IT8716F support.
In-Reply-To: <20070210003936.GA1772@greenwood>
References: <20070210003936.GA1772@greenwood>
Message-ID: <20070216144007.GC22262@greenwood>

Hi,

On Sat, Feb 10, 2007 at 01:39:37AM +0100, Uwe Hermann wrote:
> Improve ITE IT8716F support.
> 
> Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Can somebody please review/test/ack this? It's one of the last remaining
parts of Yinghai's huge patch.


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From info at coresystems.de  Fri Feb 16 16:16:14 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 16 Feb 2007 16:16:14 +0100
Subject: [LinuxBIOS] r2553 build service
Message-ID: <E1HI4oo-0008Ep-VV@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2553 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Currently the flashrom Makefile tries to detect whether pciutils-devel
is installed, but the test also fails if zlib-devel is missing. This
patch changes the error message accordingly.

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Configuration of msi:ms9282 is still broken


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision will 
be backed out.

   Yours truely,
     LinuxBIOS automatic build system





From rminnich at gmail.com  Fri Feb 16 16:44:54 2007
From: rminnich at gmail.com (ron minnich)
Date: Fri, 16 Feb 2007 08:44:54 -0700
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <20070216143129.GA22262@greenwood>
References: <20070213115345.GB30416@greenwood>
	<20070216143129.GA22262@greenwood>
Message-ID: <13426df10702160744g64c9c77as7333402ba65e1fd9@mail.gmail.com>

On 2/16/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> New version of the src/mainboard/ and targets/ contents, with license
> headers added.
>
> This can be committed IHMO. It won't build, but it shouldn't break
> anything either. So:
>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Please close this thread out witha commit message and version #. This
is a great patch -- 4 new mainboards. Thanks all!

Probably be a good idea to put this news on the wiki too. That's five
new mainboards this month!

Of course, we have to get them to build now :-) -- uwe, what's missing
at this point? This is a huge set of changes.

We should never forget the vendors here. Supermicro, MSI, Nvidia,
Gigabyte, Tyan -- all of them letting this work go forward. And, of
course, AMD, who support the LinuxBIOS project in such fine form by
supporingt Dr. Lu. Let's be glad we have great companies like this to
work with!

Now, go forth and buy their products :-)

ron



From ward at gnu.org  Fri Feb 16 17:01:46 2007
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 16 Feb 2007 11:01:46 -0500
Subject: [LinuxBIOS] [PATCH] Rest of huge MCP55 patch
In-Reply-To: <13426df10702160744g64c9c77as7333402ba65e1fd9@mail.gmail.com>
References: <20070213115345.GB30416@greenwood>
	<20070216143129.GA22262@greenwood>
	<13426df10702160744g64c9c77as7333402ba65e1fd9@mail.gmail.com>
Message-ID: <20070216160146.GA6873@countzero.vandewege.net>

On Fri, Feb 16, 2007 at 08:44:54AM -0700, ron minnich wrote:
> Of course, we have to get them to build now :-) -- uwe, what's missing
> at this point? This is a huge set of changes.
> 
> We should never forget the vendors here. Supermicro, MSI, Nvidia,
> Gigabyte, Tyan -- all of them letting this work go forward. And, of
> course, AMD, who support the LinuxBIOS project in such fine form by
> supporingt Dr. Lu. Let's be glad we have great companies like this to
> work with!
> 
> Now, go forth and buy their products :-)

We've just purchased 2 of the Gigabyte boards; they should arrive sometime
next week. I'm going to be trying to build LB for them, and I'll be sure to
report here. If that goes well, we're going to buy another 5 boards (we're
upgrading desktop machines).

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From johan.palmqvist at home.se  Thu Feb 15 19:26:41 2007
From: johan.palmqvist at home.se (Johan Palmqvist)
Date: Thu, 15 Feb 2007 19:26:41 +0100
Subject: [LinuxBIOS] dmidecode and lspci outputs
Message-ID: <45D4A5E1.1060606@home.se>

Here is a zipped attachment with dmidecode, lspci -v, -n and -t output
of the following boards:

ABit BX6 1.0
ASUS A7V133-C
ASUS A7V333
ASUS A7V600
ASUS A7V600-X
ASUS K8N
ASUS TX97-X
ASUS TX97-XE
Compaq Presario 4118EA
IBM eServer xSeries 220
MSI MS-6119

I can get output from a few more if needed.

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From wertigon at gmail.com  Fri Feb 16 02:25:24 2007
From: wertigon at gmail.com (=?ISO-8859-1?Q?Per_Ekstr=F6m?=)
Date: Fri, 16 Feb 2007 02:25:24 +0100
Subject: [LinuxBIOS] Hardware info
Message-ID: <16726be0702151725w10882516md8fdd6a721942a65@mail.gmail.com>

I don't know how useful laptop hardware is, but here's my hardware specs.

May I suggest a different list for the hardware info though? I kinda feel
bad about spamming a list with my hardware specs... :)

- Per
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# dmidecode 2.8
SMBIOS 2.31 present.
32 structures occupying 1288 bytes.
Table at 0x000DF810.

Handle 0x0000, DMI type 0, 20 bytes
BIOS Information
	Vendor: Phoenix/FUJITSU SIEMENS
	Version: 1.06
	Release Date: 06/16/2005
	Address: 0xE30F0
	Runtime Size: 118544 bytes
	ROM Size: 512 kB
	Characteristics:
		ISA is supported
		PCI is supported
		PC Card (PCMCIA) is supported
		PNP is supported
		APM is supported
		BIOS is upgradeable
		BIOS shadowing is allowed
		ESCD support is available
		Boot from CD is supported
		3.5"/720 KB floppy services are supported (int 13h)
		Print screen service is supported (int 5h)
		8042 keyboard services are supported (int 9h)
		Serial services are supported (int 14h)
		Printer services are supported (int 17h)
		ACPI is supported
		USB legacy is supported
		AGP is supported
		Smart battery is supported
		BIOS boot specification is supported

Handle 0x0001, DMI type 1, 25 bytes
System Information
	Manufacturer: FUJITSU SIEMENS
	Product Name: AMILO PRO V8010                 
	Version: F0                      
	Serial Number: YBDW038435                      
	UUID: 604E4D2F-E01D-B211-8000-00C09FDBDC1C
	Wake-up Type: Power Switch

Handle 0x0002, DMI type 2, 8 bytes
Base Board Information
	Manufacturer: FUJITSU                         
	Product Name: EF6                             
	Version: 05                      
	Serial Number: EF6TFCCYE538035C05              

Handle 0x0003, DMI type 3, 17 bytes
Chassis Information
	Manufacturer: FUJITSU SIEMENS                 
	Type: Notebook
	Lock: Not Present
	Version: A8010                   
	Serial Number: YBDW038435                      
	Asset Tag: No Asset Tag                    
	Boot-up State: Safe
	Power Supply State: Safe
	Thermal State: Safe
	Security Status: None
	OEM Information: 0x00000000

Handle 0x0004, DMI type 4, 35 bytes
Processor Information
	Socket Designation: On Board
	Type: Central Processor
	Family: Unknown
	Manufacturer: Intel Corportion
	ID: D8 06 00 00 FF FB E9 AF
	Version: Intel(R) Pentium(R) M processor
	Voltage: 1.2 V
	External Clock: 533 MHz
	Max Speed: 1733 MHz
	Current Speed: 1733 MHz
	Status: Populated, Enabled
	Upgrade: ZIF Socket
	L1 Cache Handle: 0x0008
	L2 Cache Handle: 0x0009
	L3 Cache Handle: Not Provided
	Serial Number: Not Specified
	Asset Tag: Not Specified
	Part Number: Not Specified

Handle 0x0005, DMI type 5, 20 bytes
Memory Controller Information
	Error Detecting Method: None
	Error Correcting Capabilities:
		None
	Supported Interleave: One-way Interleave
	Current Interleave: One-way Interleave
	Maximum Memory Module Size: 2048 MB
	Maximum Total Memory Size: 4096 MB
	Supported Speeds:
		60 ns
	Supported Memory Types:
		DIMM
	Memory Module Voltage: 3.3 V
	Associated Memory Slots: 2
		0x0006
		0x0007
	Enabled Error Correcting Capabilities:
		Unknown

Handle 0x0006, DMI type 6, 12 bytes
Memory Module Information
	Socket Designation: DIMM 1
	Bank Connections: 0 1
	Current Speed: 75 ns
	Type: DIMM SDRAM
	Installed Size: Not Installed
	Enabled Size: Not Installed
	Error Status: OK

Handle 0x0007, DMI type 6, 12 bytes
Memory Module Information
	Socket Designation: DIMM 2
	Bank Connections: 2 3
	Current Speed: 75 ns
	Type: DIMM SDRAM
	Installed Size: 512 MB (Double-bank Connection)
	Enabled Size: 512 MB (Double-bank Connection)
	Error Status: OK

Handle 0x0008, DMI type 7, 19 bytes
Cache Information
	Socket Designation: L1 Cache
	Configuration: Enabled, Not Socketed, Level 1
	Operational Mode: Write Back
	Location: Internal
	Installed Size: 32 KB
	Maximum Size: 32 KB
	Supported SRAM Types:
		Burst
		Pipeline Burst
		Asynchronous
	Installed SRAM Type: Asynchronous
	Speed: Unknown
	Error Correction Type: Unknown
	System Type: Unknown
	Associativity: Unknown

Handle 0x0009, DMI type 7, 19 bytes
Cache Information
	Socket Designation: L2 Cache
	Configuration: Enabled, Not Socketed, Level 2
	Operational Mode: Write Back
	Location: External
	Installed Size: 2048 KB
	Maximum Size: 2048 KB
	Supported SRAM Types:
		Burst
		Pipeline Burst
		Asynchronous
	Installed SRAM Type: Burst
	Speed: Unknown
	Error Correction Type: Unknown
	System Type: Unknown
	Associativity: Unknown

Handle 0x000A, DMI type 8, 9 bytes
Port Connector Information
	Internal Reference Designator: Not Specified
	Internal Connector Type: None
	External Reference Designator: COM 1
	External Connector Type: DB-9 male
	Port Type: Serial Port 16550A Compatible

Handle 0x000B, DMI type 8, 9 bytes
Port Connector Information
	Internal Reference Designator: CON 4
	Internal Connector Type: None
	External Reference Designator: Parallel
	External Connector Type: DB-25 female
	Port Type: Parallel Port ECP/EPP

Handle 0x000C, DMI type 9, 13 bytes
System Slot Information
	Designation: PCI Slot J20
	Type: 32-bit PCI
	Current Usage: Unknown
	Length: Long
	ID: 0
	Characteristics:
		5.0 V is provided
		3.3 V is provided
		PME signal is supported

Handle 0x000D, DMI type 9, 13 bytes
System Slot Information
	Designation: PCMCIA socket 0
	Type: 32-bit PC Card (PCMCIA)
	Current Usage: Unknown
	Length: Long
	ID: Adapter 0, Socket 0
	Characteristics:
		5.0 V is provided
		3.3 V is provided
		PC Card-16 is supported
		Cardbus is supported
		Modem ring resume is supported
		PME signal is supported
		Hot-plug devices are supported

Handle 0x000E, DMI type 10, 10 bytes
On Board Device 1 Information
	Type: Video
	Status: Disabled
	Description: Intel Alviso Integrated VGA
On Board Device 2 Information
	Type: Sound
	Status: Disabled
	Description: Intel AC97
On Board Device 3 Information
	Type: Other
	Status: Disabled
	Description: TI PCI7411 CardBus Controller

Handle 0x000F, DMI type 11, 5 bytes
OEM Strings
	String 1: SMBIOS 2.3
	String 2: Customer Reference Platform

Handle 0x0010, DMI type 15, 29 bytes
System Event Log
	Area Length: 0 bytes
	Header Start Offset: 0x0000
	Header Length: 16 bytes
	Data Start Offset: 0x0010
	Access Method: Memory-mapped physical 32-bit address
	Access Address: 0x00000000
	Status: Invalid, Not Full
	Change Token: 0x00000000
	Header Format: Type 1
	Supported Log Type Descriptors: 3
	Descriptor 1: POST error
	Data Format 1: POST results bitmap
	Descriptor 2: Single-bit ECC memory error
	Data Format 2: Multiple-event
	Descriptor 3: Multi-bit ECC memory error
	Data Format 3: Multiple-event

Handle 0x0011, DMI type 16, 15 bytes
Physical Memory Array
	Location: System Board Or Motherboard
	Use: System Memory
	Error Correction Type: None
	Maximum Capacity: 3 GB
	Error Information Handle: Not Provided
	Number Of Devices: 2

Handle 0x0012, DMI type 17, 27 bytes
Memory Device
	Array Handle: 0x0011
	Error Information Handle: No Error
	Total Width: Unknown
	Data Width: Unknown
	Size: No Module Installed
	Form Factor: DIMM
	Set: 1
	Locator: DIMM 0
	Bank Locator: Bank 0, 1
	Type: DDR
	Type Detail: Synchronous
	Speed: 333 MHz (3.0 ns)
	Manufacturer: Not Specified
	Serial Number: Not Specified
	Asset Tag: Not Specified
	Part Number: Not Specified

Handle 0x0013, DMI type 17, 27 bytes
Memory Device
	Array Handle: 0x0011
	Error Information Handle: No Error
	Total Width: 64 bits
	Data Width: 64 bits
	Size: 512 MB
	Form Factor: DIMM
	Set: 1
	Locator: DIMM 1
	Bank Locator: Bank 2, 3
	Type: DDR
	Type Detail: Synchronous
	Speed: 333 MHz (3.0 ns)
	Manufacturer: Not Specified
	Serial Number: Not Specified
	Asset Tag: Not Specified
	Part Number: Not Specified

Handle 0x0014, DMI type 19, 15 bytes
Memory Array Mapped Address
	Starting Address: 0x00000000000
	Ending Address: 0x0001FFFFFFF
	Range Size: 512 MB
	Physical Array Handle: 0x0011
	Partition Width: 0

Handle 0x0015, DMI type 20, 19 bytes
Memory Device Mapped Address
	Starting Address: 0x00000000000
	Ending Address: 0x000000003FF
	Range Size: 1 kB
	Physical Device Handle: 0x0012
	Memory Array Mapped Address Handle: 0x0014
	Partition Row Position: 1
	Interleave Position: 1

Handle 0x0016, DMI type 20, 19 bytes
Memory Device Mapped Address
	Starting Address: 0x00000000000
	Ending Address: 0x0001FFFFFFF
	Range Size: 512 MB
	Physical Device Handle: 0x0013
	Memory Array Mapped Address Handle: 0x0014
	Partition Row Position: 1
	Interleave Position: 1

Handle 0x0017, DMI type 22, 26 bytes
Portable Battery
	Location: Internal Battery
	Manufacturer: Fujitsu
	Name: Fujitsu
	Chemistry: Lithium Ion
	Design Capacity: 4600 mWh
	Design Voltage: 14800 mV
	SBDS Version: 00h   
	Maximum Error: Unknown
	SBDS Serial Number: 0000
	SBDS Manufacture Date: 1980-00-00
	OEM-specific Information: 0x00000000

Handle 0x0018, DMI type 32, 20 bytes
System Boot Information
	Status: <OUT OF SPEC>

Handle 0x0019, DMI type 143, 15 bytes
OEM-specific Type
	Header and Data:
		8F 0F 19 00 00 5F 46 4A 5F 4F 45 4D 5F 00 00

Handle 0x001A, DMI type 143, 8 bytes
OEM-specific Type
	Header and Data:
		8F 08 1A 00 01 03 00 00

Handle 0x001B, DMI type 176, 16 bytes
OEM-specific Type
	Header and Data:
		B0 10 1B 00 00 00 00 00 00 00 FF FF FF FF FF FF

Handle 0x001C, DMI type 188, 8 bytes
OEM-specific Type
	Header and Data:
		BC 08 1C 00 39 38 31 24

Handle 0x001D, DMI type 200, 7 bytes
OEM-specific Type
	Header and Data:
		C8 07 1D 00 01 02 03
	Strings:
		152D
		EF6
		Q3B21

Handle 0x001E, DMI type 126, 4 bytes
Inactive

Handle 0x001F, DMI type 127, 4 bytes
End Of Table

00:00.0 0600: 8086:2590 (rev 04)
00:02.0 0300: 8086:2592 (rev 04)
00:02.1 0380: 8086:2792 (rev 04)
00:1c.0 0604: 8086:2660 (rev 04)
00:1c.1 0604: 8086:2662 (rev 04)
00:1d.0 0c03: 8086:2658 (rev 04)
00:1d.1 0c03: 8086:2659 (rev 04)
00:1d.2 0c03: 8086:265a (rev 04)
00:1d.3 0c03: 8086:265b (rev 04)
00:1d.7 0c03: 8086:265c (rev 04)
00:1e.0 0604: 8086:2448 (rev d4)
00:1e.2 0401: 8086:266e (rev 04)
00:1e.3 0703: 8086:266d (rev 04)
00:1f.0 0601: 8086:2641 (rev 04)
00:1f.1 0101: 8086:266f (rev 04)
00:1f.2 0106: 8086:2653 (rev 04)
00:1f.3 0c05: 8086:266a (rev 04)
06:00.0 0200: 10ec:8169 (rev 10)
06:04.0 0280: 8086:4220 (rev 05)
06:09.0 0607: 104c:8031
06:09.2 0c00: 104c:8032
06:09.3 0180: 104c:8033
06:09.4 0805: 104c:8034
00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 04)
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, fast devsel, latency 0
	Capabilities: [e0] Vendor Specific Information

00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04) (prog-if 00 [VGA])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, fast devsel, latency 0, IRQ 177
	Memory at b0080000 (32-bit, non-prefetchable) [size=512K]
	I/O ports at 1800 [size=8]
	Memory at c0000000 (32-bit, prefetchable) [size=256M]
	Memory at b0000000 (32-bit, non-prefetchable) [size=256K]
	Capabilities: [d0] Power Management version 2

00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04)
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: fast devsel
	Memory at 33000000 (32-bit, non-prefetchable) [disabled] [size=512K]
	Capabilities: [d0] Power Management version 2

00:1c.0 PCI bridge: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1 (rev 04) (prog-if 00 [Normal decode])
	Flags: bus master, fast devsel, latency 0
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	Capabilities: [40] Express Root Port (Slot+) IRQ 0
	Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
	Capabilities: [90] #0d [0000]
	Capabilities: [a0] Power Management version 2
	Capabilities: [100] Virtual Channel
	Capabilities: [180] Unknown (5)

00:1c.1 PCI bridge: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2 (rev 04) (prog-if 00 [Normal decode])
	Flags: bus master, fast devsel, latency 0
	Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
	Capabilities: [40] Express Root Port (Slot+) IRQ 0
	Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
	Capabilities: [90] #0d [0000]
	Capabilities: [a0] Power Management version 2
	Capabilities: [100] Virtual Channel
	Capabilities: [180] Unknown (5)

00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0, IRQ 233
	I/O ports at 1820 [size=32]

00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0, IRQ 225
	I/O ports at 1840 [size=32]

00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0, IRQ 217
	I/O ports at 1860 [size=32]

00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0, IRQ 177
	I/O ports at 1880 [size=32]

00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 04) (prog-if 20 [EHCI])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0, IRQ 233
	Memory at b0040000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2
	Capabilities: [58] Debug port

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d4) (prog-if 01 [Subtractive decode])
	Flags: bus master, fast devsel, latency 0
	Bus: primary=00, secondary=06, subordinate=57, sec-latency=216
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: b0100000-b01fffff
	Prefetchable memory behind bridge: 0000000030000000-0000000032f00000
	Capabilities: [50] #0d [0000]

00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller (rev 04)
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0, IRQ 169
	I/O ports at 1c00 [size=256]
	I/O ports at 18c0 [size=64]
	Memory at b0040800 (32-bit, non-prefetchable) [size=512]
	Memory at b0040400 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2

00:1e.3 Modem: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller (rev 04) (prog-if 00 [Generic])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: medium devsel, IRQ 209
	I/O ports at 2400 [size=256]
	I/O ports at 2000 [size=128]
	Capabilities: [50] Power Management version 2

00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge (rev 04)
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0

00:1f.1 IDE interface: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller (rev 04) (prog-if 8a [Master SecP PriP])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 0, IRQ 217
	I/O ports at <unassigned>
	I/O ports at <unassigned>
	I/O ports at <unassigned>
	I/O ports at <unassigned>
	I/O ports at 1810 [size=16]

00:1f.2 SATA controller: Intel Corporation 82801FBM (ICH6M) SATA Controller (rev 04) (prog-if 01 [AHCI 1.0])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 225
	I/O ports at 2088 [size=8]
	I/O ports at 2080 [size=4]
	I/O ports at 18a8 [size=8]
	I/O ports at 180c [size=4]
	I/O ports at 18b0 [size=16]
	Memory at b0040c00 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [70] Power Management version 2

00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller (rev 04)
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: medium devsel, IRQ 11
	I/O ports at 20a0 [size=32]

06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet (rev 10)
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 225
	I/O ports at 3000 [size=256]
	Memory at b0106000 (32-bit, non-prefetchable) [size=256]
	[virtual] Expansion ROM at 32000000 [disabled] [size=128K]
	Capabilities: [dc] Power Management version 2

06:04.0 Network controller: Intel Corporation PRO/Wireless 2200BG Network Connection (rev 05)
	Subsystem: Intel Corporation Unknown device 2702
	Flags: bus master, medium devsel, latency 32, IRQ 169
	Memory at b0107000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [dc] Power Management version 2

06:09.0 CardBus bridge: Texas Instruments PCIxx21/x515 Cardbus Controller
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 168, IRQ 177
	Memory at b0109000 (32-bit, non-prefetchable) [size=4K]
	Bus: primary=06, secondary=07, subordinate=0a, sec-latency=176
	Memory window 0: 30000000-31fff000 (prefetchable)
	Memory window 1: 34000000-35fff000
	I/O window 0: 00003400-000034ff
	I/O window 1: 00003800-000038ff
	16-bit legacy interface ports at 0001

06:09.2 FireWire (IEEE 1394): Texas Instruments OHCI Compliant IEEE 1394 Host Controller (prog-if 10 [OHCI])
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 32, IRQ 217
	Memory at b0106800 (32-bit, non-prefetchable) [size=2K]
	Memory at b0100000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: [44] Power Management version 2

06:09.3 Mass storage controller: Texas Instruments PCIxx21 Integrated FlashMedia Controller
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 64, IRQ 177
	[virtual] Memory at b0104000 (32-bit, non-prefetchable) [size=8K]
	Capabilities: [44] Power Management version 2

06:09.4 Class 0805: Texas Instruments PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Secure Digital (SD) Controller
	Subsystem: Fujitsu Siemens Computer GmbH Unknown device 107d
	Flags: bus master, medium devsel, latency 57, IRQ 177
	Memory at b0108400 (32-bit, non-prefetchable) [size=256]
	Memory at b0108000 (32-bit, non-prefetchable) [size=256]
	Memory at b0106400 (32-bit, non-prefetchable) [size=256]
	Capabilities: [80] Power Management version 2

-[0000:00]-+-00.0
           +-02.0
           +-02.1
           +-1c.0-[0000:02]--
           +-1c.1-[0000:03]--
           +-1d.0
           +-1d.1
           +-1d.2
           +-1d.3
           +-1d.7
           +-1e.0-[0000:06-57]--+-00.0
           |                    +-04.0
           |                    +-09.0
           |                    +-09.2
           |                    +-09.3
           |                    \-09.4
           +-1e.2
           +-1e.3
           +-1f.0
           +-1f.1
           +-1f.2
           \-1f.3

From stepan at coresystems.de  Fri Feb 16 19:36:21 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 16 Feb 2007 19:36:21 +0100
Subject: [LinuxBIOS] [PATCH] flashrom Makefile message improvements
In-Reply-To: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>
References: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>
Message-ID: <20070216183621.GA28040@coresystems.de>

* Ed Swierk <eswierk at arastra.com> [070214 19:45]:
> Currently the flashrom Makefile tries to detect whether pciutils-devel
> is installed, but the test also fails if zlib-devel is missing. This
> patch changes the error message accordingly.

I would generally say this is not a problem in LinuxBIOS but in the
distribution. If building binaries using pciutils requires additional
packages, they should be required by pciutils-devel.

Which distribution is this? 

Glad it is in though, it will reduce questions.

> Signed-off-by: Ed Swierk <eswierk at arastra.com>
> 
> --Ed

> Index: LinuxBIOSv2-2552/util/flashrom/Makefile
> ===================================================================
> --- LinuxBIOSv2-2552.orig/util/flashrom/Makefile
> +++ LinuxBIOSv2-2552/util/flashrom/Makefile
> @@ -41,14 +41,14 @@ dep:
>  	@$(CC) -MM *.c > .dependencies
>  
>  pciutils:
> -	@echo; echo -n "Checking for pciutils... "
> +	@echo; echo -n "Checking for pciutils and zlib... "
>  	@$(shell ( echo "#include <pci/pci.h>";		   \
>  		   echo "struct pci_access *pacc;";	   \
>  		   echo "int main(int argc, char **argv)"; \
>  		   echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c )
>  	@$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null &&	\
>  		echo "found." || ( echo "not found."; echo;		\
> -		echo "Please install pciutils and pciutils-devel.";	\
> +		echo "Please install pciutils-devel and zlib-devel.";	\
>  		echo "See README for more information."; echo;		\
>  		rm -f .test.c .test; exit 1)
>  	@rm -f .test.c .test

> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.openbios.org/mailman/listinfo/linuxbios

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From eswierk at arastra.com  Fri Feb 16 19:52:27 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Fri, 16 Feb 2007 10:52:27 -0800
Subject: [LinuxBIOS] [PATCH] flashrom Makefile message improvements
In-Reply-To: <20070216183621.GA28040@coresystems.de>
References: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>
	<20070216183621.GA28040@coresystems.de>
Message-ID: <c1bf1cf0702161052n3f758883kd3a9c301a5149917@mail.gmail.com>

On 2/16/07, Stefan Reinauer <stepan at coresystems.de> wrote:
> I would generally say this is not a problem in LinuxBIOS but in the
> distribution. If building binaries using pciutils requires additional
> packages, they should be required by pciutils-devel.

I don't think we can blame Fedora--the flashrom Makefile says

  LDFLAGS = -lpci -lz -static

--Ed



From eswierk at arastra.com  Fri Feb 16 20:07:17 2007
From: eswierk at arastra.com (Ed Swierk)
Date: Fri, 16 Feb 2007 11:07:17 -0800
Subject: [LinuxBIOS] [PATCH] Improve ITE IT8716F support.
In-Reply-To: <20070216144007.GC22262@greenwood>
References: <20070210003936.GA1772@greenwood>
	<20070216144007.GC22262@greenwood>
Message-ID: <c1bf1cf0702161107s65536171lf7b5de548c5f501@mail.gmail.com>

On 2/16/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> Can somebody please review/test/ack this? It's one of the last remaining
> parts of Yinghai's huge patch.

I tried it out on my DFI board and it seems to work fine, although I'm
exercising only the serial port.

I had to add #include <arch/io.h> to superio.c to get it to compile.
The modified patch is attached.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
-------------- next part --------------
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From stuge-linuxbios at cdy.org  Fri Feb 16 20:40:06 2007
From: stuge-linuxbios at cdy.org (Peter Stuge)
Date: Fri, 16 Feb 2007 20:40:06 +0100
Subject: [LinuxBIOS] [PATCH] flashrom Makefile message improvements
In-Reply-To: <c1bf1cf0702161052n3f758883kd3a9c301a5149917@mail.gmail.com>
References: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>
	<20070216183621.GA28040@coresystems.de>
	<c1bf1cf0702161052n3f758883kd3a9c301a5149917@mail.gmail.com>
Message-ID: <20070216194006.25322.qmail@cdy.org>

On Fri, Feb 16, 2007 at 10:52:27AM -0800, Ed Swierk wrote:
> I don't think we can blame Fedora--the flashrom Makefile says
> 
>   LDFLAGS = -lpci -lz -static

Is zlib needed because libpci needs it or because some part of
flashrom needs it?


//Peter



From stefan.reinauer at coresystems.de  Fri Feb 16 21:33:57 2007
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Fri, 16 Feb 2007 21:33:57 +0100
Subject: [LinuxBIOS] [PATCH] flashrom Makefile message improvements
In-Reply-To: <20070216194006.25322.qmail@cdy.org>
References: <c1bf1cf0702141045l7732f0b3pbc588d0ef2cb117a@mail.gmail.com>	<20070216183621.GA28040@coresystems.de>	<c1bf1cf0702161052n3f758883kd3a9c301a5149917@mail.gmail.com>
	<20070216194006.25322.qmail@cdy.org>
Message-ID: <45D61535.1010507@coresystems.de>

Peter Stuge wrote:
> On Fri, Feb 16, 2007 at 10:52:27AM -0800, Ed Swierk wrote:
>> I don't think we can blame Fedora--the flashrom Makefile says
>>
>>   LDFLAGS = -lpci -lz -static
> 
> Is zlib needed because libpci needs it or because some part of
> flashrom needs it?

On some distributions, libpci needs it.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Sat Feb 17 15:28:12 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat, 17 Feb 2007 15:28:12 +0100
Subject: [LinuxBIOS] r2554 - in trunk/LinuxBIOSv2: src/mainboard
	src/mainboard/gigabyte src/mainboard/gigabyte/m57sli
	src/mainboard/nvidia src/mainboard/nvidia/l1_2pvv
	src/mainboard/supermicro src/mainboard/supermicro/h8dmr
	src/mainboard/tyan src/mainboard/tyan/s2912 targets
	targets/gigabyte targets/gigabyte/m57sli targets/nvidia
	targets/nvidia/l1_2pvv targets/supermicro
	targets/supermicro/h8dmr targets/tyan targets/tyan/s2912
Message-ID: <mailman.176.1355071060.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-02-17 15:28:11 +0100 (Sat, 17 Feb 2007)
New Revision: 2554

Added:
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/apc_auto.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/chip.h
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cmos.layout
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/get_bus_conf.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/irq_tables.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mainboard.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/resourcemap.c
   trunk/LinuxBIOSv2/src/mainboard/nvidia/
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/apc_auto.c
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/chip.h
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cmos.layout
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/irq_tables.c
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mainboard.c
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mptable.c
   trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/resourcemap.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/apc_auto.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/chip.h
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cmos.layout
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/get_bus_conf.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/irq_tables.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mainboard.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mptable.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/resourcemap.c
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/apc_auto.c
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/chip.h
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cmos.layout
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/get_bus_conf.c
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/irq_tables.c
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mainboard.c
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mb_sysconf.h
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mptable.c
   trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/resourcemap.c
   trunk/LinuxBIOSv2/targets/gigabyte/
   trunk/LinuxBIOSv2/targets/gigabyte/m57sli/
   trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb
   trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb.kernel
   trunk/LinuxBIOSv2/targets/gigabyte/m57sli/VERSION
   trunk/LinuxBIOSv2/targets/nvidia/
   trunk/LinuxBIOSv2/targets/nvidia/l1_2pvv/
   trunk/LinuxBIOSv2/targets/nvidia/l1_2pvv/Config.lb
   trunk/LinuxBIOSv2/targets/nvidia/l1_2pvv/Config.lb.kernel
   trunk/LinuxBIOSv2/targets/nvidia/l1_2pvv/VERSION
   trunk/LinuxBIOSv2/targets/supermicro/
   trunk/LinuxBIOSv2/targets/supermicro/h8dmr/
   trunk/LinuxBIOSv2/targets/supermicro/h8dmr/Config.lb
   trunk/LinuxBIOSv2/targets/supermicro/h8dmr/Config.lb.kernel
   trunk/LinuxBIOSv2/targets/supermicro/h8dmr/VERSION
   trunk/LinuxBIOSv2/targets/tyan/s2912/
   trunk/LinuxBIOSv2/targets/tyan/s2912/Config.lb
   trunk/LinuxBIOSv2/targets/tyan/s2912/Config.lb.kernel
   trunk/LinuxBIOSv2/targets/tyan/s2912/VERSION
Log:
Initial support for the following new mainboards:

* Nvidia l1_2pvv
* Gigabyte m57sli
* Supermicro h8dmr
* Tyan s2912 -- with HTX

The boards will currently _not_ compile, two further patches
from Yinghai Lu are still missing. Please be patient :)

Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,374 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FAILOVER_IMAGE
+	default ROM_SECTION_SIZE   = FAILOVER_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
+else
+    if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+    else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+	default ROM_SECTION_OFFSET = 0
+    end
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+
+if USE_FAILOVER_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+    if USE_FALLBACK_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+    else
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+    end
+end
+
+arch i386 end 
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT	
+		makerule ./cache_as_ram_auto.o
+		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+		end
+	else
+		makerule ./cache_as_ram_auto.inc
+        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+		end
+	end
+
+end
+
+if USE_FAILOVER_IMAGE
+else
+    if CONFIG_AP_CODE_IN_CAR
+        makerule ./apc_auto.o
+                depends "$(MAINBOARD)/apc_auto.c option_table.h"
+                action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+        end
+        ldscript /arch/i386/init/ldscript_apc.lb
+    end
+end
+
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+else
+    if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit southbridge/nvidia/mcp55/id.inc
+ldscript /southbridge/nvidia/mcp55/id.lds
+
+##
+## ROMSTRAP table for MCP55
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+end
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover_failover.lds
+	end
+    end
+else
+    if USE_FALLBACK_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	end
+    end
+end
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject cache_as_ram_auto.o
+	else
+		mainboardinit ./cache_as_ram_auto.inc
+	end
+end
+
+##
+## Include the secondary Configuration files 
+##
+if CONFIG_CHIP_NAME
+	config chip.h
+end
+
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_AM2
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+						chip superio/ite/it8716f
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.2 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.3 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.4 off #  EC
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+							end
+                	        			device pnp 2e.6 on #  Mouse
+                	                			irq 0x70 = 12
+							end
+                	        			device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+                	        			device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+                	        			device pnp 2e.a off end #  CIR
+						end
+					end
+			                device pci 1.1 on # SM 0
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 on end # PCI
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 off end # NIC
+        	       			device pci a.0 on end # PCI E 5
+        	       			device pci b.0 on end # PCI E 4
+                			device pci c.0 on end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 on end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#               device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 off end # io
+#       end  
+end #root_complex

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Options.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Options.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,356 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses ACPI_SSDTX_NUM
+uses USE_FALLBACK_IMAGE
+uses USE_FAILOVER_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_FAILOVER_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses FAILOVER_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_COMPRESSED_ROM_STREAM
+uses CONFIG_COMPRESSED_ROM_STREAM_LZMA
+uses CONFIG_PRECOMPRESSED_ROM_STREAM
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_USBDEBUG_DIRECT
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
+uses HW_MEM_HOLE_SIZE_AUTO_INC
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses SERIAL_CPU_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
+uses CONFIG_LB_MEM_TOPK
+
+uses CONFIG_AP_CODE_IN_CAR
+
+uses MEM_TRAIN_SEQ
+
+uses WAIT_BEFORE_CPUS_INIT
+
+uses CONFIG_USE_PRINTK_IN_CAR
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=524288
+#default ROM_SIZE=0x100000
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=0x40000
+
+#FALLBACK: 256K-4K
+default FALLBACK_SIZE=0x3f000
+#FAILOVER: 4K
+default FAILOVER_SIZE=0x01000
+
+#more 1M for pgtbl
+default CONFIG_LB_MEM_TOPK=2048
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+default HAVE_FAILOVER_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+default HAVE_ACPI_TABLES=0
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_PHYSICAL_CPUS=1
+default CONFIG_LOGICAL_CPUS=1
+
+#default SERIAL_CPU_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=1
+
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
+#2G
+#default HW_MEM_HOLE_SIZEK=0x200000
+#1G
+default HW_MEM_HOLE_SIZEK=0x100000
+#512M
+#default HW_MEM_HOLE_SIZEK=0x80000
+
+#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
+#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+default CONFIG_USBDEBUG_DIRECT=1
+
+#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
+default HT_CHAIN_UNITID_BASE=0
+
+#real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x6
+
+#make the SB HT chain on bus 0, default is not (0)
+default SB_HT_CHAIN_ON_BUS0=2
+
+#only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#allow capable device use that above 4G
+#default CONFIG_PCI_64BIT_PREF_MEM=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc8000
+default DCACHE_RAM_SIZE=0x08000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+default CONFIG_AP_CODE_IN_CAR=0
+default MEM_TRAIN_SEQ=2
+default WAIT_BEFORE_CPUS_INIT=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="m57sli"
+default MAINBOARD_VENDOR="GIGABYTE"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+#default CONFIG_COMPRESSED_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+### 
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+## 
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/apc_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/apc_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/apc_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "arch/i386/lib/console.c"
+
+#if 0 
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+
+#include "lib/delay.c"
+
+//#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+
+#include "cpu/x86/mtrr.h"
+#include "cpu/amd/mtrr.h"
+#include "cpu/x86/tsc.h"
+
+#include "northbridge/amd/amdk8/amdk8_f_pci.c"
+#include "northbridge/amd/amdk8/raminit_f_dqs.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+void hardwaremain(int ret_addr)
+{
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+
+	struct node_core_id id;
+
+	id = get_node_core_id_x();
+
+	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+
+	train_ram(id.nodeid, sysinfo, sysinfox);
+
+	/*
+		go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
+	*/
+
+        __asm__ volatile (
+                "movl  %0, %%edi\n\t"
+                "jmp     *%%edi\n\t"
+                :: "a"(ret_addr)
+        );
+
+
+
+}
+struct eregs {
+        uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
+        uint32_t vector;
+        uint32_t error_code;
+        uint32_t eip;
+        uint32_t cs;
+        uint32_t eflags;
+};
+
+void x86_exception(struct eregs *info)
+{
+        do {
+                hlt();
+        } while(1);
+}
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,367 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+
+
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 1
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#define DBGP_DEFAULT 7
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#if CONFIG_USBDEBUG_DIRECT
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "superio/ite/it8716f/it8716f_early_serial.c"
+#include "superio/ite/it8716f/it8716f_early_init.c"
+
+#if USE_FAILOVER_IMAGE==0
+
+#include "cpu/x86/bist.h"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit_f.c"
+
+#include "sdram/generic_sdram.c"
+
+#include "resourcemap.c" 
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define MCP55_NUM 1
+#define MCP55_USE_NIC 1
+#define MCP55_USE_AZA 1
+
+#define MCP55_PCI_E_X_0 0
+
+#define MCP55_MB_SETUP \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+        uint32_t dword;
+        uint8_t byte;
+
+        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20; 
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+        dword |= (1<<0);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+        dword |= (1<<16);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+}
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        sio_setup();
+
+        /* Setup the mcp55 */
+        mcp55_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
+}
+#endif
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr [] = {
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+#endif
+	};
+
+        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+	pnp_enter_ext_func_mode(SERIAL_DEV);
+        pnp_write_config(SERIAL_DEV, 0x23, 1);
+ 	it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
+	pnp_exit_ext_func_mode(SERIAL_DEV);
+
+        setup_mb_resource_map();
+
+        uart_init();
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+
+#if CONFIG_USBDEBUG_DIRECT
+	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+#endif
+        console_init();
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+        setup_coherent_ht_domain(); // routing table and start other core0
+
+        wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+         * So here need to make sure last core0 is started, esp for two way system,
+         * (there may be apic id conflicts in that case)
+         */
+        start_other_cores();
+        wait_all_other_cores_started(bsp_apicid);
+#endif
+
+        /* it will set up chains and store link pair for optimization later */
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+#if K8_SET_FIDVID == 1
+
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+
+        enable_fid_change();
+
+        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+#endif
+
+        needs_reset |= optimize_link_coherent_ht();
+        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        needs_reset |= mcp55_early_setup_x();
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+              	soft_reset();
+        }
+        allow_all_aps_stop(bsp_apicid);
+
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+        enable_smbus(); 
+
+        memreset_setup();
+
+        //do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+//        init_timer(); // Need to use TMICT to synconize FID/VID
+
+        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+
+}
+
+
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/chip.h	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_gigabyte_m57sli_ops;
+
+struct mainboard_gigabyte_m57sli_config {
+//	int fixup_scsi;
+//	int fixup_vga;
+};

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cmos.layout
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cmos.layout	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cmos.layout	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,119 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/get_bus_conf.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/get_bus_conf.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/get_bus_conf.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned apicid_mcp55;
+
+
+unsigned pci1234x[] = 
+{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0
+};
+unsigned hcdnx[] = 
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+	0x20202020,
+//	0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+};
+unsigned bus_type[256]; 
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+
+	unsigned apicid_base;
+	unsigned sbdn;
+
+        device_t dev;
+        int i, j;
+
+        if(get_bus_conf_done==1) return; //do it only once
+
+        get_bus_conf_done = 1;
+
+        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        for(i=0;i<sysconf.hc_possible_num; i++) {
+                sysconf.pci1234[i] = pci1234x[i];
+                sysconf.hcdn[i] = hcdnx[i];
+        }
+
+        get_sblk_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	sbdn = sysconf.sbdn;
+
+	for(i=0; i<8; i++) {
+		bus_mcp55[i] = 0;
+	}
+	
+	for(i=0;i<256; i++) {
+		bus_type[i] = 0;
+	}
+
+	bus_type[0] = 1; //pci
+	
+	bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+
+	bus_type[bus_mcp55[0]] = 1;
+
+                /* MCP55 */
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0));
+                if (dev) {
+                        bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_mcp55[2]++;
+			for(j=bus_mcp55[1];j<bus_mcp55[2]; j++) bus_type[j] = 1;
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
+
+                        bus_mcp55[1] = 2;
+                        bus_mcp55[2] = 3;
+                }
+
+		for(i=2; i<8;i++) {
+	                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
+        	        if (dev) {
+                	        bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                        bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+        	                bus_isa++;
+				for(j=bus_mcp55[i];j<bus_isa; j++) bus_type[j] = 1;
+	                }
+        	        else {
+                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
+	                        bus_isa = bus_mcp55[i-1]+1;
+        	        }
+		}
+
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else 
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#endif
+	apicid_mcp55 = apicid_base+0;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/irq_tables.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/irq_tables.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+		uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus; 
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	unsigned slot_num;
+	uint8_t *v;
+	unsigned sbdn;
+
+        uint8_t sum=0;
+        int i;
+
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+	sbdn = sysconf.sbdn;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+	pirq = (void *)(addr);
+	v = (uint8_t *)(addr);
+	
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version  = PIRQ_VERSION;
+	
+	pirq->rtr_bus = bus_mcp55[0];
+	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+
+	pirq->exclusive_irqs = 0;
+	
+	pirq->rtr_vendor = 0x10de;
+	pirq->rtr_device = 0x0370;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *) ( &pirq->checksum + 1);
+	slot_num = 0;
+//pci bridge
+	write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+        
+	pirq->size = 32 + 16 * slot_num; 
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];	
+
+	sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+	printk_info("done.\n");
+
+	return	(unsigned long) pirq_info;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mainboard.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mainboard.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_gigabyte_m57sli_ops = {
+	CHIP_NAME("GIGABYTE M575SLI mainboard")
+};
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1
+
+extern unsigned apicid_mcp55;
+
+extern unsigned bus_type[256]; 
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "GIGABYTE";
+        static const char productid[12] = "M57SLI      ";
+        struct mp_config_table *mc;
+	unsigned sbdn;
+
+	int i,j;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
+
+/*Bus:		Bus ID	Type*/
+       /* define bus and isa numbers */
+        for(j= 0; j < 256 ; j++) {
+		if(bus_type[j])
+			 smp_write_bus(mc, j, "PCI   ");
+        }
+        smp_write_bus(mc, bus_isa, "ISA   ");
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+        {
+                device_t dev;
+		struct resource *res;
+		uint32_t dword;
+
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			if (res) {
+				smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+			}
+
+			dword = 0x43c6c643;
+	        	pci_write_config32(dev, 0x7c, dword);
+
+		        dword = 0x81001a00;
+		        pci_write_config32(dev, 0x80, dword);
+
+	        	dword = 0xd0001202;
+		        pci_write_config32(dev, 0x84, dword);
+
+                }
+	}
+  
+/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
+*/	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_mcp55, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_mcp55, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_mcp55, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_mcp55, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_mcp55, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_mcp55, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_mcp55, 0xf);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
+
+	for(j=7; j>=2; j--) {
+		if(!bus_mcp55[j]) continue;
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+        	}
+	}
+
+	for(j=0; j<2; j++) 
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06+j)<<2)|i, apicid_mcp55, 0x10 + (2+i+j)%4);
+	        }
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/resourcemap.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/resourcemap.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/resourcemap.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,283 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n 
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration region i
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+
+	};
+
+	int max;
+	max = sizeof(register_values)/sizeof(register_values[0]);
+	setup_resource_map(register_values, max);
+}
+

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Config.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,436 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FAILOVER_IMAGE
+	default ROM_SECTION_SIZE   = FAILOVER_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
+else
+    if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+    else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+	default ROM_SECTION_OFFSET = 0
+    end
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+
+if USE_FAILOVER_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+    if USE_FALLBACK_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+    else
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+    end
+end
+
+arch i386 end 
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+if HAVE_ACPI_TABLES
+        object acpi_tables.o
+        object fadt.o
+	makerule dsdt.c
+		depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
+		action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+		action  "mv dsdt_lb.hex dsdt.c"
+	end
+        object ./dsdt.o
+
+	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
+	
+        if ACPI_SSDTX_NUM
+            makerule ssdt6.c
+                        depends "$(MAINBOARD)/dx/pci6.asl"
+                        action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
+                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
+                        action  "mv pci6.hex ssdt6.c"
+            end
+            object ./ssdt6.o
+            makerule ssdt5.c
+                        depends "$(MAINBOARD)/dx/pci5.asl"
+                        action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
+                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
+                        action  "mv pci5.hex ssdt5.c"
+            end
+            object ./ssdt5.o
+        end
+end
+
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT	
+		makerule ./cache_as_ram_auto.o
+		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+		end
+	else
+		makerule ./cache_as_ram_auto.inc
+        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+		end
+	end
+
+end
+
+if USE_FAILOVER_IMAGE
+else
+    if CONFIG_AP_CODE_IN_CAR
+        makerule ./apc_auto.o
+                depends "$(MAINBOARD)/apc_auto.c option_table.h"
+                action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+        end
+        ldscript /arch/i386/init/ldscript_apc.lb
+    end
+end
+
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+else
+    if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit southbridge/nvidia/mcp55/id.inc
+ldscript /southbridge/nvidia/mcp55/id.lds
+
+##
+## ROMSTRAP table for MCP55
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+end
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover_failover.lds
+	end
+    end
+else
+    if USE_FALLBACK_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	end
+    end
+end
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject cache_as_ram_auto.o
+	else
+		mainboardinit ./cache_as_ram_auto.inc
+	end
+end
+
+##
+## Include the secondary Configuration files 
+##
+if CONFIG_CHIP_NAME
+	config chip.h
+end
+
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+						chip superio/winbond/w83627ehg
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off  # SFI 
+                	                 			io 0x62 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  WDTO_PLED
+                	        			device pnp 2e.9 off end #  GPIO_SUSLED
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+			                device pci 1.1 on # SM 0
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 on end # PCI
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			device pci a.0 on end # PCI E 5
+        	       			device pci b.0 off end # PCI E 4
+                			device pci c.0 off end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 off end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on
+	                        #  devices on link 2, link 2 == LDT 2
+                        	chip southbridge/nvidia/mcp55
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on end  # LPC
+			                device pci 1.1 on end # SM 0
+	                		device pci 2.0 off end # USB 1.1
+        	        		device pci 2.1 off end # USB 2
+                			device pci 4.0 off end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 off end # PCI
+        	        		device pci 6.1 off end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			device pci a.0 on end # PCI E 5
+        	       			device pci b.0 off end # PCI E 4
+                			device pci c.0 off end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+                        	end
+			end # device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 on end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#               device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 off end # io
+#       end  
+end #root_complex

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Options.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/Options.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,356 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses ACPI_SSDTX_NUM
+uses USE_FALLBACK_IMAGE
+uses USE_FAILOVER_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_FAILOVER_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses FAILOVER_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_COMPRESSED_ROM_STREAM
+uses CONFIG_COMPRESSED_ROM_STREAM_LZMA
+uses CONFIG_PRECOMPRESSED_ROM_STREAM
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_USBDEBUG_DIRECT
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
+uses HW_MEM_HOLE_SIZE_AUTO_INC
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses SERIAL_CPU_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
+uses CONFIG_LB_MEM_TOPK
+
+uses CONFIG_AP_CODE_IN_CAR
+
+uses MEM_TRAIN_SEQ
+
+uses WAIT_BEFORE_CPUS_INIT
+
+uses CONFIG_USE_PRINTK_IN_CAR
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=524288
+#default ROM_SIZE=0x100000
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=0x40000
+
+#FALLBACK: 256K-4K
+default FALLBACK_SIZE=0x3f000
+#FAILOVER: 4K
+default FAILOVER_SIZE=0x01000
+
+#more 1M for pgtbl
+default CONFIG_LB_MEM_TOPK=2048
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+default HAVE_FAILOVER_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+default HAVE_ACPI_TABLES=0
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+#default SERIAL_CPU_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=1
+
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
+#2G
+#default HW_MEM_HOLE_SIZEK=0x200000
+#1G
+default HW_MEM_HOLE_SIZEK=0x100000
+#512M
+#default HW_MEM_HOLE_SIZEK=0x80000
+
+#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
+#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+#default CONFIG_USBDEBUG_DIRECT=1
+
+#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
+default HT_CHAIN_UNITID_BASE=0
+
+#real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x6
+
+#make the SB HT chain on bus 0, default is not (0)
+default SB_HT_CHAIN_ON_BUS0=2
+
+#only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#allow capable device use that above 4G
+#default CONFIG_PCI_64BIT_PREF_MEM=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc8000
+default DCACHE_RAM_SIZE=0x08000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+default CONFIG_AP_CODE_IN_CAR=0
+default MEM_TRAIN_SEQ=1
+default WAIT_BEFORE_CPUS_INIT=1
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="l1_2pvv"
+default MAINBOARD_VENDOR="NVIDIA"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+#default CONFIG_COMPRESSED_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+### 
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+## 
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/apc_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/apc_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/apc_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "arch/i386/lib/console.c"
+
+#if 0 
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+
+#include "lib/delay.c"
+
+//#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+
+#include "cpu/x86/mtrr.h"
+#include "cpu/amd/mtrr.h"
+#include "cpu/x86/tsc.h"
+
+#include "northbridge/amd/amdk8/amdk8_f_pci.c"
+#include "northbridge/amd/amdk8/raminit_f_dqs.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+void hardwaremain(int ret_addr)
+{
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+
+	struct node_core_id id;
+
+	id = get_node_core_id_x();
+
+	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+
+	train_ram(id.nodeid, sysinfo, sysinfox);
+
+	/*
+		go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
+	*/
+
+        __asm__ volatile (
+                "movl  %0, %%edi\n\t"
+                "jmp     *%%edi\n\t"
+                :: "a"(ret_addr)
+        );
+
+
+
+}
+struct eregs {
+        uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
+        uint32_t vector;
+        uint32_t error_code;
+        uint32_t eip;
+        uint32_t cs;
+        uint32_t eflags;
+};
+
+void x86_exception(struct eregs *info)
+{
+        do {
+                hlt();
+        } while(1);
+}
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,369 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+
+
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 0
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#define DBGP_DEFAULT 7
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#if CONFIG_USBDEBUG_DIRECT
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
+
+#if USE_FAILOVER_IMAGE==0
+
+#include "cpu/x86/bist.h"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit_f.c"
+
+#include "sdram/generic_sdram.c"
+
+#include "resourcemap.c" 
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define MCP55_NUM 2
+#define MCP55_USE_NIC 1
+#define MCP55_USE_AZA 1
+
+#define MCP55_PCI_E_X_0 2
+#define MCP55_PCI_E_X_1 4
+
+#define MCP55_MB_SETUP \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+        uint32_t dword;
+        uint8_t byte;
+
+        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20; 
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+        dword |= (1<<0);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+        dword |= (1<<16);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+
+}
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        sio_setup();
+
+        /* Setup the mcp55 */
+        mcp55_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
+}
+#endif
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr [] = {
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+#endif
+	};
+
+        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+	pnp_enter_ext_func_mode(SERIAL_DEV);
+        pnp_write_config(SERIAL_DEV, 0x24, 0);
+ 	w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
+	pnp_exit_ext_func_mode(SERIAL_DEV);
+
+        setup_mb_resource_map();
+
+        uart_init();
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+
+#if CONFIG_USBDEBUG_DIRECT
+	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+#endif
+        console_init();
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+        setup_coherent_ht_domain(); // routing table and start other core0
+
+        wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+         * So here need to make sure last core0 is started, esp for two way system,
+         * (there may be apic id conflicts in that case)
+         */
+        start_other_cores();
+        wait_all_other_cores_started(bsp_apicid);
+#endif
+
+        /* it will set up chains and store link pair for optimization later */
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+#if K8_SET_FIDVID == 1
+
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+
+        enable_fid_change();
+
+        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+#endif
+
+        needs_reset |= optimize_link_coherent_ht();
+        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        needs_reset |= mcp55_early_setup_x();
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+              	soft_reset();
+        }
+        allow_all_aps_stop(bsp_apicid);
+
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+        enable_smbus(); 
+
+        memreset_setup();
+
+        //do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+//        init_timer(); // Need to use TMICT to synconize FID/VID
+
+        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+
+}
+
+
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/chip.h	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_nvidia_l1_2pvv_ops;
+
+struct mainboard_nvidia_l1_2pvv_config {
+//	int fixup_scsi;
+//	int fixup_vga;
+};

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cmos.layout
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cmos.layout	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/cmos.layout	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,119 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,199 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+struct mb_sysconf_t mb_sysconf;
+
+unsigned pci1234x[] = 
+{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+        0x0000ff0,
+        0x0000ff0,
+        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0
+};
+unsigned hcdnx[] = 
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+	0x20202020,
+	0x20202020,
+        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+};
+
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+static unsigned get_hcid(unsigned i)
+{
+        unsigned id = 0;
+
+        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+
+        unsigned devn = sysconf.hcdn[i] & 0xff;
+
+        device_t dev;
+
+        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+
+        switch (dev->device) {
+        case 0x0369: //IO55
+                id = 4;
+                break;
+        }
+
+        // we may need more way to find out hcid: subsystem id? GPIO read ?
+
+        // we need use id for 1. bus num, 2. mptable, 3. acpi table
+
+        return id;
+}
+
+void get_bus_conf(void)
+{
+
+	unsigned apicid_base;
+	struct mb_sysconf_t *m;
+
+        device_t dev;
+        int i, j;
+
+        if(get_bus_conf_done==1) return; //do it only once
+
+        get_bus_conf_done = 1;
+
+	sysconf.mb = &mb_sysconf;
+	
+	m = sysconf.mb;
+	memset(m, 0, sizeof(struct mb_sysconf_t));
+
+        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+
+        for(i=0;i<sysconf.hc_possible_num; i++) {
+                sysconf.pci1234[i] = pci1234x[i];
+                sysconf.hcdn[i] = hcdnx[i];
+        }
+
+        get_sblk_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+
+	m->sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
+
+	m->bus_type[0] = 1; //pci
+	
+	m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+
+                /* MCP55 */
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+                if (dev) {
+                        m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+                }
+
+		for(i=2; i<8;i++) {
+	                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+        	        if (dev) {
+                	        m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                }
+        	        else {
+                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+        	        }
+		}
+
+		if(m->bus_mcp55[2]) {
+			for(i=0;i<2; i++) {
+	                        dev = dev_find_slot(m->bus_mcp55[2], PCI_DEVFN(0, i));
+        	                if(dev) {
+                	                m->bus_pcix[0] = m->bus_mcp55[2];
+                        	        m->bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                        }
+			}
+		}
+		
+	for(i=0; i< sysconf.hc_possible_num; i++) {
+		if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
+		for (j = busn; j <= busn_max; j++) 
+			m->bus_type[j] = 1;
+		if(m->bus_isa <= busn_max) 
+			m->bus_isa = busn_max + 1;
+	        printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+	}
+
+                /* MCP55b */
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+		if (!(sysconf.pci1234[i] & 0x0f) ) continue;
+                // check hcid type here
+                sysconf.hcid[i] = get_hcid(i);
+                if (!sysconf.hcid[i]) continue; //unknown co processor
+
+		m->bus_mcp55b[0] = (sysconf.pci1234[1]>>16) & 0xff;
+		m->bus_mcp55b[1] = m->bus_mcp55b[0]+1; //fake pci
+
+		for(i=2; i<8;i++) {
+	                dev = dev_find_slot(m->bus_mcp55b[0], PCI_DEVFN(m->sbdnb + 0x0a + i - 2 , 0));
+        	        if (dev) {
+                	        m->bus_mcp55b[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                }
+        	        else {
+                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55b[0], m->sbdnb + 0x0a + i - 2 );
+        	        }
+		}
+	}
+
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(2);
+#else 
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#endif
+	m->apicid_mcp55 = apicid_base+0;
+        m->apicid_mcp55b = apicid_base+1;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/irq_tables.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/irq_tables.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+#include "mb_sysconf.h"
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+		uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus; 
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	unsigned slot_num;
+	uint8_t *v;
+	struct mb_sysconf_t *m;
+	unsigned sbdn;
+
+        uint8_t sum=0;
+        int i;
+
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+	sbdn = sysconf.sbdn;
+	m = sysconf.mb;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+	pirq = (void *)(addr);
+	v = (uint8_t *)(addr);
+	
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version  = PIRQ_VERSION;
+	
+	pirq->rtr_bus = m->bus_mcp55[0];
+	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+
+	pirq->exclusive_irqs = 0;
+	
+	pirq->rtr_vendor = 0x10de;
+	pirq->rtr_device = 0x0370;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *) ( &pirq->checksum + 1);
+	slot_num = 0;
+//pci bridge
+	write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+        
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+                if(!(sysconf.pci1234[i] & 0x1) ) continue;
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned devn = sysconf.hcdn[i] & 0xff;
+
+                write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+                pirq_info++; slot_num++;
+	}
+
+	pirq->size = 32 + 16 * slot_num; 
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];	
+
+	sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+	printk_info("done.\n");
+
+	return	(unsigned long) pirq_info;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mainboard.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mainboard.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_nvidia_l1_2pvv_ops = {
+	CHIP_NAME("Nvidia l1_2pvv mainboard")
+};
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned char bus_mcp55b[8];//a
+        unsigned apicid_mcp55;
+        unsigned apicid_mcp55b;
+	unsigned bus_type[256]; 
+	unsigned char bus_pcix[3]; // under bus_mcp55_2
+
+	unsigned sbdnb;
+
+};
+
+#endif
+

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mptable.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/mptable.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,210 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "NVIDIA  ";
+        static const char productid[12] = "L1_2PVV     ";
+        struct mp_config_table *mc;
+	struct mb_sysconf_t *m;
+	unsigned sbdn;
+
+	int i,j;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
+	m = sysconf.mb;
+
+/*Bus:		Bus ID	Type*/
+       /* define bus and isa numbers */
+        for(j= 0; j < 256 ; j++) {
+		if(m->bus_type[j])
+			 smp_write_bus(mc, j, "PCI   ");
+        }
+        smp_write_bus(mc, m->bus_isa, "ISA   ");
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+        {
+                device_t dev;
+		struct resource *res;
+		uint32_t dword;
+
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			if (res) {
+				smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+			}
+
+			dword = 0x43c6c643;
+	        	pci_write_config32(dev, 0x7c, dword);
+
+		        dword = 0x81001a00;
+		        pci_write_config32(dev, 0x80, dword);
+
+	        	dword = 0xd00012d2;
+		        pci_write_config32(dev, 0x84, dword);
+
+                }
+
+	    if(m->bus_mcp55b[0]) {
+                dev = dev_find_slot(m->bus_mcp55b[0], PCI_DEVFN(m->sbdnb + 0x1,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			if (res) {
+				smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base);
+			}
+			dword = 0x43c60000;
+	        	pci_write_config32(dev, 0x7c, dword);
+
+		        dword = 0x81000000;
+		        pci_write_config32(dev, 0x80, dword);
+
+	        	dword = 0xd00002d0;
+		        pci_write_config32(dev, 0x84, dword);
+
+                }
+
+	    }
+
+	}
+  
+		   /*I/O Ints:	Type	Polarity    Trigger			Bus ID	 IRQ	APIC ID	PIN# */	
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
+
+	for(j=7; j>=2; j--) {
+		if(!m->bus_mcp55[j]) continue;
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+        	}
+	}
+
+	for(j=0; j<2; j++) 
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x06+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
+	        }
+
+	if(m->bus_mcp55b[0]) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
+
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
+
+
+		for(j=7; j>=2; j--) {
+			if(!m->bus_mcp55b[j]) continue;
+			for(i=0;i<4;i++) {
+				smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[j], (0x00<<2)|i, m->apicid_mcp55b, 0x10 + (2+j+i+4-m->sbdnb%4)%4);
+			}
+		}
+	}
+#if 1
+
+	if(m->bus_pcix[0]) {	
+
+		for(i=0;i<2;i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[2], (4<<2)|i, m->apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 
+		}
+
+
+		for(i=0;i<4;i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[1], (4<<2)|i, m->apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
+		}
+	}
+#endif
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/resourcemap.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/resourcemap.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/nvidia/l1_2pvv/resourcemap.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,283 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
+//		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset
+		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n 
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+//		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
+		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration region i
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 	*/
+		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+
+	};
+
+	int max;
+	max = sizeof(register_values)/sizeof(register_values[0]);
+	setup_resource_map(register_values, max);
+}
+

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Config.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,390 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FAILOVER_IMAGE
+	default ROM_SECTION_SIZE   = FAILOVER_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
+else
+    if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+    else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+	default ROM_SECTION_OFFSET = 0
+    end
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+
+if USE_FAILOVER_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+    if USE_FALLBACK_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+    else
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+    end
+end
+
+arch i386 end 
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT	
+		makerule ./auto.o
+		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+		end
+	else
+		makerule ./auto.inc
+        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+		end
+	end
+
+end
+
+if USE_FAILOVER_IMAGE
+else
+    if CONFIG_AP_CODE_IN_CAR
+        makerule ./apc_auto.o
+                depends "$(MAINBOARD)/apc_auto.c option_table.h"
+                action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+        end
+        ldscript /arch/i386/init/ldscript_apc.lb
+    end
+end
+
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+else
+    if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit southbridge/nvidia/mcp55/id.inc
+ldscript /southbridge/nvidia/mcp55/id.lds
+
+##
+## ROMSTRAP table for MCP55
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+end
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover_failover.lds
+	end
+    end
+else
+    if USE_FALLBACK_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	end
+    end
+end
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject auto.o
+	else
+		mainboardinit ./auto.inc
+	end
+end
+
+##
+## Include the secondary Configuration files 
+##
+if CONFIG_CHIP_NAME
+	config chip.h
+end
+
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off  # SFI 
+                	                 			io 0x62 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  WDTO_PLED
+                	        			device pnp 2e.9 off end #  GPIO_SUSLED
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+			                device pci 1.1 on # SM 0
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 on  # PCI
+#                                                chip drivers/pci/onboard
+#                                                        device pci 6.0 on end
+#                                                        register "rom_address" = "0xfff80000" #for 512K
+					#		register "rom_address" = "0xfff00000" #for 1M
+ #                                               end
+					end
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			device pci a.0 on  # PCI E 5
+						device pci 0.0 on #nec pci-x
+						end
+						device pci 0.1 on #nec pci-x
+							device pci 4.0 on end #scsi
+							device pci 4.1 on end #scsi
+						end
+					end
+        	       			device pci b.0 on end # PCI E 4
+                			device pci c.0 on end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 on end # io
+#       end  
+end #root_complex

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Options.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/Options.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,353 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses ACPI_SSDTX_NUM
+uses USE_FALLBACK_IMAGE
+uses USE_FAILOVER_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_FAILOVER_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses FAILOVER_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_COMPRESSED_ROM_STREAM
+uses CONFIG_COMPRESSED_ROM_STREAM_LZMA
+uses CONFIG_PRECOMPRESSED_ROM_STREAM
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
+uses HW_MEM_HOLE_SIZE_AUTO_INC
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses SERIAL_CPU_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
+uses CONFIG_LB_MEM_TOPK
+
+uses CONFIG_AP_CODE_IN_CAR
+
+uses MEM_TRAIN_SEQ
+
+uses WAIT_BEFORE_CPUS_INIT
+
+uses CONFIG_USE_PRINTK_IN_CAR
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+#default ROM_SIZE=524288
+default ROM_SIZE=0x100000
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=0x40000
+
+#FALLBACK: 256K-4K
+default FALLBACK_SIZE=0x3f000
+#FAILOVER: 4K
+default FAILOVER_SIZE=0x01000
+
+#more 1M for pgtbl
+default CONFIG_LB_MEM_TOPK=2048
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+default HAVE_FAILOVER_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+default HAVE_ACPI_TABLES=0
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+default SERIAL_CPU_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=1
+
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
+#2G
+#default HW_MEM_HOLE_SIZEK=0x200000
+#1G
+default HW_MEM_HOLE_SIZEK=0x100000
+#512M
+#default HW_MEM_HOLE_SIZEK=0x80000
+
+#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
+#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
+default HT_CHAIN_UNITID_BASE=0
+
+#real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x6
+
+#make the SB HT chain on bus 0, default is not (0)
+default SB_HT_CHAIN_ON_BUS0=2
+
+#only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#allow capable device use that above 4G
+#default CONFIG_PCI_64BIT_PREF_MEM=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc8000
+default DCACHE_RAM_SIZE=0x08000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+default CONFIG_AP_CODE_IN_CAR=0
+default MEM_TRAIN_SEQ=1
+default WAIT_BEFORE_CPUS_INIT=1
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="h8dmr"
+default MAINBOARD_VENDOR="Supermicro"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+#default CONFIG_COMPRESSED_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+### 
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+## 
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+default CONFIG_USE_PRINTK_IN_CAR=0
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/apc_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/apc_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/apc_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "arch/i386/lib/console.c"
+
+#if 0 
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+
+#include "lib/delay.c"
+
+//#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+
+#include "cpu/x86/mtrr.h"
+#include "cpu/amd/mtrr.h"
+#include "cpu/x86/tsc.h"
+
+#include "northbridge/amd/amdk8/amdk8_f_pci.c"
+#include "northbridge/amd/amdk8/raminit_f_dqs.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+void hardwaremain(int ret_addr)
+{
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+
+	struct node_core_id id;
+
+	id = get_node_core_id_x();
+
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+
+	train_ram(id.nodeid, sysinfo, sysinfox);
+
+	/*
+		go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
+	*/
+
+        __asm__ volatile (
+                "movl  %0, %%edi\n\t"
+                "jmp     *%%edi\n\t"
+                :: "a"(ret_addr)
+        );
+
+
+
+}
+struct eregs {
+        uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
+        uint32_t vector;
+        uint32_t error_code;
+        uint32_t eip;
+        uint32_t cs;
+        uint32_t eflags;
+};
+
+void x86_exception(struct eregs *info)
+{
+        do {
+                hlt();
+        } while(1);
+}
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,358 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+
+
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 1
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+// for enable the FAN
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+
+//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+
+#if USE_FAILOVER_IMAGE==0
+
+#include "cpu/x86/bist.h"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit_f.c"
+
+#include "sdram/generic_sdram.c"
+
+#include "resourcemap.c" 
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define MCP55_NUM 1
+#define MCP55_USE_NIC 1
+#define MCP55_USE_AZA 1
+
+#define MCP55_PCI_E_X_0 4
+
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+        uint32_t dword;
+        uint8_t byte;
+        enable_smbus();
+//	smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
+	smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
+
+        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20; 
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+        dword |= (1<<0);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+        dword |= (1<<16);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+
+}
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        sio_setup();
+
+        /* Setup the mcp55 */
+        mcp55_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
+}
+#endif
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr [] = {
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+#endif
+	};
+
+        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+	pnp_enter_ext_func_mode(SERIAL_DEV);
+        pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
+ 	w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE);
+	pnp_exit_ext_func_mode(SERIAL_DEV);
+
+        uart_init();
+        console_init();
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+        setup_mb_resource_map();
+
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+        setup_coherent_ht_domain(); // routing table and start other core0
+
+        wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+         * So here need to make sure last core0 is started, esp for two way system,
+         * (there may be apic id conflicts in that case)
+         */
+        start_other_cores();
+        wait_all_other_cores_started(bsp_apicid);
+#endif
+
+        /* it will set up chains and store link pair for optimization later */
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+#if K8_SET_FIDVID == 1
+
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+
+        enable_fid_change();
+
+        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+#endif
+
+#if 1
+        needs_reset |= optimize_link_coherent_ht();
+        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        needs_reset |= mcp55_early_setup_x();
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+              	soft_reset();
+        }
+#endif
+        allow_all_aps_stop(bsp_apicid);
+
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+//        enable_smbus(); /* enable in sio_setup */
+
+        memreset_setup();
+
+        //do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+//        init_timer(); // Need to use TMICT to synconize FID/VID
+
+        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+
+}
+
+
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/chip.h	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_supermicro_h8dmr_ops;
+
+struct mainboard_supermicro_h8dmr_config {
+};

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cmos.layout
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cmos.layout	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/cmos.layout	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,119 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/get_bus_conf.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/get_bus_conf.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/get_bus_conf.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned apicid_mcp55;
+
+	unsigned char bus_pcix[3]; // under bus_mcp55_2
+
+unsigned pci1234x[] = 
+{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+        0x0000ff0,
+        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0
+};
+unsigned hcdnx[] = 
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+	0x20202020,
+	0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+};
+unsigned sbdnb;
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+
+	unsigned apicid_base;
+	unsigned sbdn;
+
+        device_t dev;
+        int i;
+
+        if(get_bus_conf_done==1) return; //do it only once
+
+        get_bus_conf_done = 1;
+
+        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        for(i=0;i<sysconf.hc_possible_num; i++) {
+                sysconf.pci1234[i] = pci1234x[i];
+                sysconf.hcdn[i] = hcdnx[i];
+        }
+
+        get_sblk_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	sbdn = sysconf.sbdn;
+
+	sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
+
+	for(i=0; i<8; i++) {
+		bus_mcp55[i] = 0;
+	}
+	
+	for(i=0; i<3; i++) {
+		bus_pcix[i] = 0;
+	}
+
+
+	bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+
+                /* MCP55 */
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0));
+                if (dev) {
+                        bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_mcp55[2]++;
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
+
+                        bus_mcp55[1] = 2;
+                        bus_mcp55[2] = 3;
+                }
+
+		for(i=2; i<8;i++) {
+	                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
+        	        if (dev) {
+                	        bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                        bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+        	                bus_isa++;
+	                }
+        	        else {
+                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
+	                        bus_isa = bus_mcp55[i-1]+1;
+        	        }
+		}
+
+		if(bus_mcp55[2]) {
+			for(i=0;i<2; i++) {
+	                        dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i));
+        	                if(dev) {
+                	                bus_pcix[0] = bus_mcp55[2];
+                        	        bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                        }
+			}
+		}
+		
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else 
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#endif
+	apicid_mcp55 = apicid_base+0;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/irq_tables.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/irq_tables.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+		uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus; 
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	unsigned slot_num;
+	uint8_t *v;
+	unsigned sbdn;
+
+        uint8_t sum=0;
+        int i;
+
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+	sbdn = sysconf.sbdn;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+	pirq = (void *)(addr);
+	v = (uint8_t *)(addr);
+	
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version  = PIRQ_VERSION;
+	
+	pirq->rtr_bus = bus_mcp55[0];
+	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+
+	pirq->exclusive_irqs = 0;
+	
+	pirq->rtr_vendor = 0x10de;
+	pirq->rtr_device = 0x0370;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *) ( &pirq->checksum + 1);
+	slot_num = 0;
+//pci bridge
+	write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+        
+	pirq->size = 32 + 16 * slot_num; 
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];	
+
+	sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+	printk_info("done.\n");
+
+	return	(unsigned long) pirq_info;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mainboard.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mainboard.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_supermicro_h8dmr_ops = {
+	CHIP_NAME("Spermicro H8DMR mainboard")
+};
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mptable.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/mptable.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1
+
+extern unsigned apicid_mcp55;
+
+extern unsigned char bus_pcix[3]; // under bus_mcp55_2
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "SUPERMIC";
+        static const char productid[12] = "H8DMR       ";
+        struct mp_config_table *mc;
+	unsigned sbdn;
+
+        unsigned char bus_num;
+	int i,j;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
+
+/*Bus:		Bus ID	Type*/
+       /* define bus and isa numbers */
+        for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+                smp_write_bus(mc, bus_num, "PCI   ");
+        }
+        smp_write_bus(mc, bus_isa, "ISA   ");
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+        {
+                device_t dev;
+		struct resource *res;
+		uint32_t dword;
+
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			if (res) {
+				smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+			}
+
+			dword = 0x43c6c643;
+	        	pci_write_config32(dev, 0x7c, dword);
+
+		        dword = 0x81001a00;
+		        pci_write_config32(dev, 0x80, dword);
+
+	        	dword = 0xd00012d2;
+		        pci_write_config32(dev, 0x84, dword);
+
+                }
+
+
+
+	}
+  
+/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
+*/	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_mcp55, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_mcp55, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_mcp55, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_mcp55, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_mcp55, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_mcp55, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_mcp55, 0xf);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
+
+	for(j=7; j>=2; j--) {
+		if(!bus_mcp55[j]) continue;
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+        	}
+	}
+
+        for(i=0;i<4;i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4);
+        }
+
+
+	if(bus_pcix[0]) {	
+		for(i=0;i<2;i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 
+		}
+
+		for(i=0;i<4;i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
+		}
+	}
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/resourcemap.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/resourcemap.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/h8dmr/resourcemap.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,283 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
+		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n 
+		 * [31:25] Reserved
+		 */
+		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration region i
+		 */
+		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+
+	};
+
+	int max;
+	max = sizeof(register_values)/sizeof(register_values[0]);
+	setup_resource_map(register_values, max);
+}
+

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Config.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,378 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FAILOVER_IMAGE
+	default ROM_SECTION_SIZE   = FAILOVER_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
+else
+    if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+    else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+	default ROM_SECTION_OFFSET = 0
+    end
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+
+if USE_FAILOVER_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+    if USE_FALLBACK_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+    else
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+    end
+end
+
+arch i386 end 
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT	
+		makerule ./cache_as_ram_auto.o
+		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+		end
+	else
+		makerule ./cache_as_ram_auto.inc
+        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+		end
+	end
+
+end
+
+if USE_FAILOVER_IMAGE
+else
+    if CONFIG_AP_CODE_IN_CAR
+        makerule ./apc_auto.o
+                depends "$(MAINBOARD)/apc_auto.c option_table.h"
+                action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+        end
+        ldscript /arch/i386/init/ldscript_apc.lb
+    end
+end
+
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+else
+    if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/entry16.inc
+	ldscript /cpu/x86/16bit/entry16.lds
+    end
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+    else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+    end
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit southbridge/nvidia/mcp55/id.inc
+ldscript /southbridge/nvidia/mcp55/id.lds
+
+##
+## ROMSTRAP table for MCP55
+##
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+else
+    if USE_FALLBACK_IMAGE 
+	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+	ldscript /southbridge/nvidia/mcp55/romstrap.lds
+    end
+end
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if HAVE_FAILOVER_BOOT
+    if USE_FAILOVER_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover_failover.lds
+	end
+    end
+else
+    if USE_FALLBACK_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	end
+    end
+end
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject cache_as_ram_auto.o
+	else
+		mainboardinit ./cache_as_ram_auto.inc
+	end
+end
+
+##
+## Include the secondary Configuration files 
+##
+if CONFIG_CHIP_NAME
+	config chip.h
+end
+
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on end
+			device pci 18.0 on end 
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 on #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off  # SFI 
+                	                 			io 0x62 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  WDTO_PLED
+                	        			device pnp 2e.9 off end #  GPIO_SUSLED
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+			                device pci 1.1 on # SM 0
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 on end # PCI
+        	        		device pci 6.1 off end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			device pci a.0 on end # PCI E 5
+        	       			device pci b.0 off end # PCI E 4
+                			device pci c.0 off end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 off end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 on end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#               device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 off end # io
+#       end  
+end #root_complex

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Options.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/Options.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,358 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses ACPI_SSDTX_NUM
+uses USE_FALLBACK_IMAGE
+uses USE_FAILOVER_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_FAILOVER_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses FAILOVER_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_COMPRESSED_ROM_STREAM
+uses CONFIG_COMPRESSED_ROM_STREAM_LZMA
+uses CONFIG_PRECOMPRESSED_ROM_STREAM
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_USBDEBUG_DIRECT
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
+uses HW_MEM_HOLE_SIZE_AUTO_INC
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses SERIAL_CPU_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
+uses CONFIG_LB_MEM_TOPK
+
+uses CONFIG_AP_CODE_IN_CAR
+
+uses MEM_TRAIN_SEQ
+
+uses WAIT_BEFORE_CPUS_INIT
+
+uses CONFIG_USE_PRINTK_IN_CAR
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=524288
+#default ROM_SIZE=0x100000
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=0x40000
+
+#FALLBACK: 256K-4K
+default FALLBACK_SIZE=0x3f000
+#FAILOVER: 4K
+default FAILOVER_SIZE=0x01000
+
+#more 1M for pgtbl
+default CONFIG_LB_MEM_TOPK=2048
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+default HAVE_FAILOVER_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+default HAVE_ACPI_TABLES=0
+## extra SSDT num
+default ACPI_SSDTX_NUM=3
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+#default SERIAL_CPU_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=1
+
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
+#2G
+#default HW_MEM_HOLE_SIZEK=0x200000
+#1G
+default HW_MEM_HOLE_SIZEK=0x100000
+#512M
+#default HW_MEM_HOLE_SIZEK=0x80000
+
+#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
+#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+#default CONFIG_USBDEBUG_DIRECT=1
+
+#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
+default HT_CHAIN_UNITID_BASE=0
+
+#real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x6
+
+#make the SB HT chain on bus 0, default is not (0)
+default SB_HT_CHAIN_ON_BUS0=2
+
+#only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#allow capable device use that above 4G
+#default CONFIG_PCI_64BIT_PREF_MEM=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc8000
+default DCACHE_RAM_SIZE=0x08000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+default CONFIG_AP_CODE_IN_CAR=0
+default MEM_TRAIN_SEQ=1
+default WAIT_BEFORE_CPUS_INIT=1
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="S2912"
+default MAINBOARD_VENDOR="Tyan"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+#default CONFIG_COMPRESSED_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+### 
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+## 
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/apc_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/apc_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/apc_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "arch/i386/lib/console.c"
+
+#if 0 
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+
+#include "lib/delay.c"
+
+//#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+
+#include "cpu/x86/mtrr.h"
+#include "cpu/amd/mtrr.h"
+#include "cpu/x86/tsc.h"
+
+#include "northbridge/amd/amdk8/amdk8_f_pci.c"
+#include "northbridge/amd/amdk8/raminit_f_dqs.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+void hardwaremain(int ret_addr)
+{
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+
+	struct node_core_id id;
+
+	id = get_node_core_id_x();
+
+	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+
+	train_ram(id.nodeid, sysinfo, sysinfox);
+
+	/*
+		go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
+	*/
+
+        __asm__ volatile (
+                "movl  %0, %%edi\n\t"
+                "jmp     *%%edi\n\t"
+                :: "a"(ret_addr)
+        );
+
+
+
+}
+struct eregs {
+        uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
+        uint32_t vector;
+        uint32_t error_code;
+        uint32_t eip;
+        uint32_t cs;
+        uint32_t eflags;
+};
+
+void x86_exception(struct eregs *info)
+{
+        do {
+                hlt();
+        } while(1);
+}
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cache_as_ram_auto.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,366 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+
+
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 0
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#define DBGP_DEFAULT 7
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#if CONFIG_USBDEBUG_DIRECT
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+
+#if USE_FAILOVER_IMAGE==0
+
+#include "cpu/x86/bist.h"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit_f.c"
+
+#include "sdram/generic_sdram.c"
+
+#include "resourcemap.c" 
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define MCP55_NUM 1
+#define MCP55_USE_NIC 1
+
+#define MCP55_PCI_E_X_0 1
+
+#define MCP55_MB_SETUP \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+        uint32_t dword;
+        uint8_t byte;
+
+        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20; 
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+        /*serial 0 */
+        dword |= (1<<0);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+        dword |= (1<<16);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+
+}
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        sio_setup();
+
+        /* Setup the mcp55 */
+        mcp55_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
+}
+#endif
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr [] = {
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+#endif
+	};
+
+        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset = 0;
+        unsigned bsp_apicid = 0;
+
+        if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+
+        setup_mb_resource_map();
+
+        uart_init();
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+
+#if CONFIG_USBDEBUG_DIRECT
+	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+#endif
+        console_init();
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+        setup_coherent_ht_domain(); // routing table and start other core0
+
+        wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+         * So here need to make sure last core0 is started, esp for two way system,
+         * (there may be apic id conflicts in that case)
+         */
+        start_other_cores();
+        wait_all_other_cores_started(bsp_apicid);
+#endif
+
+        /* it will set up chains and store link pair for optimization later */
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+#if K8_SET_FIDVID == 1
+
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+
+        enable_fid_change();
+
+        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+#endif
+
+        needs_reset |= optimize_link_coherent_ht();
+        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        needs_reset |= mcp55_early_setup_x();
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+              	soft_reset();
+        }
+
+        allow_all_aps_stop(bsp_apicid);
+
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+        enable_smbus(); 
+
+        memreset_setup();
+
+        //do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+//        init_timer(); // Need to use TMICT to synconize FID/VID
+
+        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+
+}
+
+
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/chip.h	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_tyan_s2912_ops;
+
+struct mainboard_tyan_s2912_config {
+//	int fixup_scsi;
+//	int fixup_vga;
+};

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cmos.layout
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cmos.layout	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/cmos.layout	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,119 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/get_bus_conf.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/get_bus_conf.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/get_bus_conf.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+struct mb_sysconf_t mb_sysconf;
+
+unsigned pci1234x[] = 
+{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+        0x0000ff0,
+        0x0000ff0,
+        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0,
+//        0x0000ff0
+};
+unsigned hcdnx[] = 
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+	0x20202020,
+	0x20202020,
+        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+//        0x20202020,
+};
+
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+static unsigned get_hcid(unsigned i)
+{
+        unsigned id = 0;
+
+        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+
+        unsigned devn = sysconf.hcdn[i] & 0xff;
+
+        device_t dev;
+
+        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+
+        switch (dev->device) {
+        case 0x0369: //IO55
+                id = 4;
+                break;
+        }
+
+        // we may need more way to find out hcid: subsystem id? GPIO read ?
+
+        // we need use id for 1. bus num, 2. mptable, 3. acpi table
+
+        return id;
+}
+
+void get_bus_conf(void)
+{
+
+	unsigned apicid_base;
+	struct mb_sysconf_t *m;
+
+        device_t dev;
+        int i, j;
+
+        if(get_bus_conf_done==1) return; //do it only once
+
+        get_bus_conf_done = 1;
+
+	sysconf.mb = &mb_sysconf;
+	
+	m = sysconf.mb;
+	memset(m, 0, sizeof(struct mb_sysconf_t));
+
+        sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+        for(i=0;i<sysconf.hc_possible_num; i++) {
+                sysconf.pci1234[i] = pci1234x[i];
+                sysconf.hcdn[i] = hcdnx[i];
+        }
+
+        get_sblk_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+
+	m->bus_type[0] = 1; //pci
+	
+	m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+
+                /* MCP55 */
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+                if (dev) {
+                        m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                }
+                else {
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+                }
+
+		for(i=2; i<8;i++) {
+	                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+        	        if (dev) {
+                	        m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                }
+        	        else {
+                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+        	        }
+		}
+
+	for(i=0; i< sysconf.hc_possible_num; i++) {
+		if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
+		for (j = busn; j <= busn_max; j++) 
+			m->bus_type[j] = 1;
+		if(m->bus_isa <= busn_max) 
+			m->bus_isa = busn_max + 1;
+	        printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+	}
+
+
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else 
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#endif
+	m->apicid_mcp55 = apicid_base+0;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/irq_tables.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/irq_tables.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+#include "mb_sysconf.h"
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+		uint8_t slot, uint8_t rfu)
+{
+        pirq_info->bus = bus; 
+        pirq_info->devfn = devfn;
+                pirq_info->irq[0].link = link0;
+                pirq_info->irq[0].bitmap = bitmap0;
+                pirq_info->irq[1].link = link1;
+                pirq_info->irq[1].bitmap = bitmap1;
+                pirq_info->irq[2].link = link2;
+                pirq_info->irq[2].bitmap = bitmap2;
+                pirq_info->irq[3].link = link3;
+                pirq_info->irq[3].bitmap = bitmap3;
+        pirq_info->slot = slot;
+        pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	unsigned slot_num;
+	uint8_t *v;
+	struct mb_sysconf_t *m;
+	unsigned sbdn;
+
+        uint8_t sum=0;
+        int i;
+
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+	sbdn = sysconf.sbdn;
+	m = sysconf.mb;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+	pirq = (void *)(addr);
+	v = (uint8_t *)(addr);
+	
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version  = PIRQ_VERSION;
+	
+	pirq->rtr_bus = m->bus_mcp55[0];
+	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+
+	pirq->exclusive_irqs = 0;
+	
+	pirq->rtr_vendor = 0x10de;
+	pirq->rtr_device = 0x0370;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *) ( &pirq->checksum + 1);
+	slot_num = 0;
+//pci bridge
+	write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+        
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+                if(!(sysconf.pci1234[i] & 0x1) ) continue;
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned devn = sysconf.hcdn[i] & 0xff;
+
+                write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+                pirq_info++; slot_num++;
+	}
+
+	pirq->size = 32 + 16 * slot_num; 
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];	
+
+	sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
+
+	printk_info("done.\n");
+
+	return	(unsigned long) pirq_info;
+
+}

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mainboard.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mainboard.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_tyan_s2912_ops = {
+	CHIP_NAME("Tyan S2912 mainboard")
+};
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mb_sysconf.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mb_sysconf.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mb_sysconf.h	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned apicid_mcp55;
+	unsigned bus_type[256]; 
+
+};
+
+#endif
+

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mptable.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/mptable.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "TYAN    ";
+        static const char productid[12] = "S2895       ";
+        struct mp_config_table *mc;
+	struct mb_sysconf_t *m;
+	unsigned sbdn;
+
+	int i,j;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
+	m = sysconf.mb;
+
+/*Bus:		Bus ID	Type*/
+       /* define bus and isa numbers */
+        for(j= 0; j < 256 ; j++) {
+		if(m->bus_type[j])
+			 smp_write_bus(mc, j, "PCI   ");
+        }
+        smp_write_bus(mc, m->bus_isa, "ISA   ");
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+        {
+                device_t dev;
+		struct resource *res;
+		uint32_t dword;
+
+                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			if (res) {
+				smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+			}
+
+			dword = 0x43c6c643;
+	        	pci_write_config32(dev, 0x7c, dword);
+
+		        dword = 0x81001a00;
+		        pci_write_config32(dev, 0x80, dword);
+
+	        	dword = 0xd00002d2;
+		        pci_write_config32(dev, 0x84, dword);
+
+                }
+
+
+	}
+  
+		   /*I/O Ints:	Type	Polarity    Trigger			Bus ID	 IRQ	APIC ID	PIN# */	
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
+
+	for(j=7; j>=2; j--) {
+		if(!m->bus_mcp55[j]) continue;
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+        	}
+	}
+
+	for(j=0; j<1; j++) 
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
+	        }
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/resourcemap.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/resourcemap.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/tyan/s2912/resourcemap.c	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,283 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
+//		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset
+		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n 
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+//		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
+		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration region i
+		 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 	*/
+		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+
+	};
+
+	int max;
+	max = sizeof(register_values)/sizeof(register_values[0]);
+	setup_resource_map(register_values, max);
+}
+

Added: trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,104 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target m57sli
+mainboard gigabyte/m57sli
+
+# serengeti_leopard
+romimage "normal"
+#       48K for SCSI FW
+#        option ROM_SIZE = 475136
+#       48K for SCSI FW and 48K for ATI ROM
+#       option ROM_SIZE = 425984 
+#       64K for Etherboot
+#        option ROM_SIZE = 458752 
+#       44k for atixx.rom
+#        option ROM_SIZE = 479232
+        option USE_FAILOVER_IMAGE=0
+	option USE_FALLBACK_IMAGE=0
+#	option ROM_IMAGE_SIZE=0x13800
+#	option ROM_IMAGE_SIZE=0x18800
+	option ROM_IMAGE_SIZE=0x20000
+#	option ROM_IMAGE_SIZE=0x15800
+	option XIP_ROM_SIZE=0x40000
+	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#	payload ../../../payloads/tg3.zelf
+#	payload ../../../../payloads/tg3_vga.zelf
+#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
+#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
+#	payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+romimage "fallback" 
+        option USE_FAILOVER_IMAGE=0
+	option USE_FALLBACK_IMAGE=1
+#	option ROM_IMAGE_SIZE=0x13800
+#	option ROM_IMAGE_SIZE=0x19800
+	option ROM_IMAGE_SIZE=0x20000
+#	option ROM_IMAGE_SIZE=0x15800
+	option XIP_ROM_SIZE=0x40000
+	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+#       payload ../../../payloads/tg3--ide_disk.zelf
+#        payload ../../../payloads/filo.elf
+#        payload ../../../payloads/filo_mem.elf
+#        payload ../../../payloads/filo.zelf
+#        payload ../../../payloads/tg3--filo_hda2.zelf
+#	payload ../../../payloads/tg3.zelf
+#	payload ../../../../payloads/tg3_vga.zelf
+#	payload ../../../../payloads/memtest
+#	payload ../../../../payloads/e1000_vga.zelf
+#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
+#	payload ../../../../payloads/filo_hda.zelf
+#	payload ../../../../payloads/adlo.elf
+#	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+#	payload ../../../../payloads/forcedeth_mcp55_filo_hda2.zelf
+	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
+#	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+#	payload ../../../payloads/tg3_com2.zelf
+#       payload ../../../payloads/e1000--filo.zelf
+#        payload ../../../payloads/tg3--e1000--filo.zelf
+#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+romimage "failover"
+        option USE_FAILOVER_IMAGE=1
+        option USE_FALLBACK_IMAGE=0
+        option ROM_IMAGE_SIZE=FAILOVER_SIZE
+        option XIP_ROM_SIZE=FAILOVER_SIZE
+        option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+end
+
+#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"

Added: trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb.kernel
===================================================================
--- trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb.kernel	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/gigabyte/m57sli/Config.lb.kernel	2007-02-17 14:28:11 UTC (rev 2554)
@@ -0,0 +1,77 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General