From rminnich at gmail.com  Sun Jul  1 00:00:18 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 30 Jun 2007 15:00:18 -0700
Subject: [LinuxBIOS] [PATCH] v3 - put lar size in the bootblock
In-Reply-To: <20070630215814.GB31719@coresystems.de>
References: <20070630215814.GB31719@coresystems.de>
Message-ID: <13426df10706301500m24138f35r345570a6560bb94d@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From peter at stuge.se  Sun Jul  1 00:01:13 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 00:01:13 +0200
Subject: [LinuxBIOS] r408 - LinuxBIOSv3/include/arch/x86
Message-ID: <20070630220113.18866.qmail@stuge.se>

I've been away on a ferry working since Thursday. Sorry about being
quiet. Am just now catching up on emali.

On Fri, Jun 29, 2007 at 02:22:19AM +0200, svn at openbios.org wrote:
> -	unsigned lo;
> -	unsigned hi;
> +	u32 lo;
> +	u32 hi;
>  };
>  
> -static inline struct msr  rdmsr(unsigned index)
> +static inline struct msr rdmsr(unsigned index)

You missed the parameter index here. Ignore if it's been fixed
already.


//Peter



From svn at openbios.org  Sun Jul  1 00:03:39 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  1 Jul 2007 00:03:39 +0200
Subject: [LinuxBIOS] r427 - in LinuxBIOSv3: arch/x86 util/lar
Message-ID: <mailman.489.1355071127.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-07-01 00:03:39 +0200 (Sun, 01 Jul 2007)
New Revision: 427

Modified:
   LinuxBIOSv3/arch/x86/stage1.c
   LinuxBIOSv3/util/lar/bootblock.c
   LinuxBIOSv3/util/lar/lar.c
Log:
this patch puts the lar size in the bootblock and reads it from there.
Why? This way we don't need to recompile the image when the size of the
LinuxBIOS image changes. This alows building images for 50 motherboards
and equipping each with 10 payloads, resulting in 500 images while you
only have to build each payload once and each motherboard, too.

There's also a small "fix" allowing the compression type to be case
insensitive. Not really relevant I guess.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: LinuxBIOSv3/arch/x86/stage1.c
===================================================================
--- LinuxBIOSv3/arch/x86/stage1.c	2007-06-30 20:57:47 UTC (rev 426)
+++ LinuxBIOSv3/arch/x86/stage1.c	2007-06-30 22:03:39 UTC (rev 427)
@@ -101,8 +101,12 @@
 	// FIXME this should be defined in the VPD area
 	// but NOT IN THE CODE.
 	
-	archive.len=(CONFIG_LINUXBIOS_ROMSIZE_KB)*1024;
-	archive.start=(void *)(0UL-(CONFIG_LINUXBIOS_ROMSIZE_KB*1024)); 
+	/* The len field starts behind the reset vector on x86.
+	 * The start is not correct for all platforms. sc520 will
+	 * need some hands on here. 
+	 */
+	archive.len = *(u32 *)0xfffffff4;
+	archive.start =(void *)(0UL-archive.len); 
 
 	// FIXME check integrity
 

Modified: LinuxBIOSv3/util/lar/bootblock.c
===================================================================
--- LinuxBIOSv3/util/lar/bootblock.c	2007-06-30 20:57:47 UTC (rev 426)
+++ LinuxBIOSv3/util/lar/bootblock.c	2007-06-30 22:03:39 UTC (rev 427)
@@ -74,16 +74,16 @@
 
 int fixup_bootblock(void)
 {
-	/* Per definition the bootblock starts with 256 empty bytes.
-	 * These are utilized to make the bootblock part of a lar file,
-	 * and store the image size.
-	 *
-	 * We will also calculate a checksum here.
-	 */
+	int i;
+	uint32_t *size_pos;
 
-	/* first try. Clear out ugly left-over from ld hack */
-	bootblock_code[bootblock_len - 13] = '\0';
-	bootblock_code[bootblock_len - 12] = '\0';
+	/* This cleans out the area after the reset vector */
+	for(i=13; i>0; i--)
+		bootblock_code[bootblock_len - i] = '\0';
+	
+	/* add lar size to image */
+	size_pos=(uint32_t *)(bootblock_code+bootblock_len-12);
+	size_pos[0] = get_larsize();
 
 	return 0;
 }

Modified: LinuxBIOSv3/util/lar/lar.c
===================================================================
--- LinuxBIOSv3/util/lar/lar.c	2007-06-30 20:57:47 UTC (rev 426)
+++ LinuxBIOSv3/util/lar/lar.c	2007-06-30 22:03:39 UTC (rev 427)
@@ -96,10 +96,10 @@
 			larmode = CREATE;
 			break;
 		case 'C':
-			if (strcmp("lzma", optarg) == 0) {
+			if (strcasecmp("lzma", optarg) == 0) {
 				algo = lzma;
 			}
-			if (strcmp("nrv2b", optarg) == 0) {
+			if (strcasecmp("nrv2b", optarg) == 0) {
 				algo = nrv2b;
 			}
 			break;




From rminnich at gmail.com  Sun Jul  1 00:04:51 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 30 Jun 2007 15:04:51 -0700
Subject: [LinuxBIOS] r408 - LinuxBIOSv3/include/arch/x86
In-Reply-To: <20070630220113.18866.qmail@stuge.se>
References: <20070630220113.18866.qmail@stuge.se>
Message-ID: <13426df10706301504i2c802979xbf3d5af5bd74fa98@mail.gmail.com>

On 6/30/07, Peter Stuge <peter at stuge.se> wrote:
> I've been away on a ferry working

eh? A ferry? Tell us more! Pictures?

ron



From svn at openbios.org  Sun Jul  1 00:09:57 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  1 Jul 2007 00:09:57 +0200
Subject: [LinuxBIOS] r428 - LinuxBIOSv3
Message-ID: <mailman.490.1355071127.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-07-01 00:09:57 +0200 (Sun, 01 Jul 2007)
New Revision: 428

Modified:
   LinuxBIOSv3/
Log:
Set svn:ignore property so temporary files and directories don't show up
in svn status (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>




Property changes on: LinuxBIOSv3
___________________________________________________________________
Name: svn:ignore
   + .kconfig.d
.config
.tmpconfig.h
.xcompile
build
.config.old





From uwe at hermann-uwe.de  Sun Jul  1 00:11:42 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 1 Jul 2007 00:11:42 +0200
Subject: [LinuxBIOS] [PATCH] v3 - put lar size in the bootblock
In-Reply-To: <20070630215814.GB31719@coresystems.de>
References: <20070630215814.GB31719@coresystems.de>
Message-ID: <20070630221141.GD5201@greenwood>

On Sat, Jun 30, 2007 at 11:58:15PM +0200, Stefan Reinauer wrote:
> Hi,
> 
> this patch puts the lar size in the bootblock and reads it from there.
> Why? This way we don't need to recompile the image when the size of the
> LinuxBIOS image changes. This alows building images for 50 motherboards
> and equipping each with 10 payloads, resulting in 500 images while you
> only have to build each payload once and each motherboard, too.

Nice! This will be a very important feature...


> There's also a small "fix" allowing the compression type to be case
> insensitive. Not really relevant I guess.
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> 
> Index: util/lar/bootblock.c
> ===================================================================
> --- util/lar/bootblock.c        (revision 426)
> +++ util/lar/bootblock.c        (working copy)
> @@ -74,16 +74,16 @@
> 
>  int fixup_bootblock(void)
>  {
> -       /* Per definition the bootblock starts with 256 empty bytes.
> -        * These are utilized to make the bootblock part of a lar file,
> -        * and store the image size.
> -        *
> -        * We will also calculate a checksum here.
> -        */
> +       int i;
> +       uint32_t *size_pos;

u32


> -       /* first try. Clear out ugly left-over from ld hack */
> -       bootblock_code[bootblock_len - 13] = '\0';
> -       bootblock_code[bootblock_len - 12] = '\0';
> +       /* This cleans out the area after the reset vector */
> +       for(i=13; i>0; i--)

Coding style is broken (in a few other places, too).


> +               bootblock_code[bootblock_len - i] = '\0';
> +
> +       /* add lar size to image */
> +       size_pos=(uint32_t *)(bootblock_code+bootblock_len-12);

u32


> +       size_pos[0] = get_larsize();
> 
>         return 0;
>  }
> Index: util/lar/lar.c
> ===================================================================
> --- util/lar/lar.c      (revision 426)
> +++ util/lar/lar.c      (working copy)
> @@ -96,10 +96,10 @@
>                         larmode = CREATE;
>                         break;
>                 case 'C':
> -                       if (strcmp("lzma", optarg) == 0) {
> +                       if (strcasecmp("lzma", optarg) == 0) {

OK, I guess, but not all systems might have strcasecmp (I think it's
called stricmp() on some). Not critical right now, though...


>                                 algo = lzma;
>                         }
> -                       if (strcmp("nrv2b", optarg) == 0) {
> +                       if (strcasecmp("nrv2b", optarg) == 0) {
>                                 algo = nrv2b;
>                         }
>                         break;
> Index: arch/x86/stage1.c
> ===================================================================
> --- arch/x86/stage1.c   (revision 426)
> +++ arch/x86/stage1.c   (working copy)
> @@ -101,8 +101,12 @@
>         // FIXME this should be defined in the VPD area
>         // but NOT IN THE CODE.
> 
> -       archive.len=(CONFIG_LINUXBIOS_ROMSIZE_KB)*1024;
> -       archive.start=(void *)(0UL-(CONFIG_LINUXBIOS_ROMSIZE_KB*1024));
> +       /* The len field starts behind the reset vector on x86.
> +        * The start is not correct for all platforms. sc520 will
> +        * need some hands on here.
> +        */
> +       archive.len = *(u32 *)0xfffffff4;
> +       archive.start =(void *)(0UL-archive.len);
 

Something seems wrong with the patch, doesn't apply here (mailer issue?)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From peter at stuge.se  Sun Jul  1 00:11:38 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 00:11:38 +0200
Subject: [LinuxBIOS] r413 - in LinuxBIOSv3: arch/x86 include
	mainboard/artecgroup/dbe61 southbridge/amd/cs5536
	superio/winbond/w83627hf
Message-ID: <20070630221138.20350.qmail@stuge.se>

On Fri, Jun 29, 2007 at 04:36:03PM +0200, svn at openbios.org wrote:
> +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

Need extra () around a or no?

sizeof((a)) / sizeof(((a))[0])) ?


//Peter



From peter at stuge.se  Sun Jul  1 00:30:48 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 00:30:48 +0200
Subject: [LinuxBIOS] r408 - LinuxBIOSv3/include/arch/x86
In-Reply-To: <13426df10706301504i2c802979xbf3d5af5bd74fa98@mail.gmail.com>
References: <20070630220113.18866.qmail@stuge.se>
	<13426df10706301504i2c802979xbf3d5af5bd74fa98@mail.gmail.com>
Message-ID: <20070630223048.23529.qmail@stuge.se>

On Sat, Jun 30, 2007 at 03:04:51PM -0700, ron minnich wrote:
> On 6/30/07, Peter Stuge <peter at stuge.se> wrote:
> > I've been away on a ferry working
> 
> eh? A ferry? Tell us more! Pictures?

Yep, a customer of mine does engine control/fuel saving for ferries.

4x 10000 (yes!) bhp 8-cylinder engines. Each three stories tall and
60 feet long. Cylinders ~2 feet in diameter.

No pictures, sorry. My customer has some, I'll see if I can get
copies.

I'm looking around for an industrial-grade LB-friendly board with
some NAND flash, USB, DVI output (just 2D) and 2GHz+ CPU. Any
suggestions?


//Peter



From uwe at hermann-uwe.de  Sun Jul  1 00:31:18 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 1 Jul 2007 00:31:18 +0200
Subject: [LinuxBIOS] [PATCH] v3: Move htl() into cpu.h
In-Reply-To: <13426df10706301435g4872ebd5yf7b706fe63111d@mail.gmail.com>
References: <20070630202218.GA5201@greenwood>
	<13426df10706301435g4872ebd5yf7b706fe63111d@mail.gmail.com>
Message-ID: <20070630223118.GE5201@greenwood>

On Sat, Jun 30, 2007 at 02:35:04PM -0700, ron minnich wrote:
> On 6/30/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> >See patch.
> >
> >Do we really need or want the "__attribute__((always_inline))"?
> 
> Only rarely.
> 
> Why we would need it for hlt()? So, in case memory is totally not
> working, we don't do a call and try to push stuff on a stack. We want
> it inline.
> 
> There are very few cases where we should apply always_inline.

OK, I see, thanks. Patch updated.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Sun Jul  1 00:38:26 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 1 Jul 2007 00:38:26 +0200
Subject: [LinuxBIOS] r427 - in LinuxBIOSv3: arch/x86 util/lar
Message-ID: <20070630223826.GF5201@greenwood>

On Sun, Jul 01, 2007 at 12:03:39AM +0200, svn at openbios.org wrote:
> Author: stepan
> Date: 2007-07-01 00:03:39 +0200 (Sun, 01 Jul 2007)
> New Revision: 427

Patch sent: Sat, 30 Jun 2007 23:58:15 +0200
ACK:        Sat, 30 Jun 2007 15:00:18 -0700
Commit:     Sun,  1 Jul 2007 00:03:39 +0200

2:03 minutes til ack, 3:21 til commit.

*cough*

My theory: you guys are stuck in a room with lots of kittens and a
terrorist. Every time a patch doesn't get committed in less than
5 minutes the terrorist kills a kitten.


You must love kittens quite a lot :)

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From rminnich at gmail.com  Sun Jul  1 00:42:22 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 30 Jun 2007 15:42:22 -0700
Subject: [LinuxBIOS] r427 - in LinuxBIOSv3: arch/x86 util/lar
In-Reply-To: <20070630223826.GF5201@greenwood>
References: <20070630223826.GF5201@greenwood>
Message-ID: <13426df10706301542j17bee32cp2681aaee1b7a5d1f@mail.gmail.com>

On 6/30/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Sun, Jul 01, 2007 at 12:03:39AM +0200, svn at openbios.org wrote:
> > Author: stepan
> > Date: 2007-07-01 00:03:39 +0200 (Sun, 01 Jul 2007)
> > New Revision: 427
>
> Patch sent: Sat, 30 Jun 2007 23:58:15 +0200
> ACK:        Sat, 30 Jun 2007 15:00:18 -0700
> Commit:     Sun,  1 Jul 2007 00:03:39 +0200
>
> 2:03 minutes til ack, 3:21 til commit.


we're slowing down, I admit.

Actually, we're sitting at a table trying to get this done before I
leave at 4 am tomorrow, or they start serving beer at 8pm in 1:16:33.

:-)

It's almost over ...

ron
p.s. poor kittens!



From stepan at coresystems.de  Sun Jul  1 00:46:04 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 1 Jul 2007 00:46:04 +0200
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
Message-ID: <20070630224604.GA25735@coresystems.de>

* fix copyright headers to v2 only as suggested by Uwe
* drop silly code when not using SMP 
* fix device/device.c
* drop spinlock_t, use struct spinlock instead.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>


Index: include/spinlock.h
===================================================================
--- include/spinlock.h  (revision 427)
+++ include/spinlock.h  (working copy)
@@ -2,11 +2,11 @@
  * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2001 Linux Networx
+ * Copyright (C) 2007 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -22,23 +22,17 @@
 #define SPINLOCK_H

 #if defined(CONFIG_SMP) && CONFIG_SMP == 1
+
 #include <arch/spinlock.h>
+
 #else /* !CONFIG_SMP */

-/* Most GCC versions have a nasty bug with empty initializers */
-#if (__GNUC__ > 2)
-typedef struct { } spinlock_t;
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { }
-#else
-typedef struct { int gcc_is_buggy; } spinlock_t;
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
-#endif
-
 #define barrier()              do {} while(0)
 #define spin_is_locked(lock)   0
 #define spin_unlock_wait(lock) do {} while(0)
 #define spin_lock(lock)                do {} while(0)
 #define spin_unlock(lock)      do {} while(0)
+#define spin_define(lock)       /* empty */
 #endif

 #endif /* SPINLOCK_H */
Index: include/arch/x86/arch/spinlock.h
===================================================================
--- include/arch/x86/arch/spinlock.h    (revision 427)
+++ include/arch/x86/arch/spinlock.h    (working copy)
@@ -2,11 +2,11 @@
  * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2001 Linux Networx
+ * Copyright (C) 2007 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -25,12 +25,12 @@
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */

-typedef struct {
+struct spinlock {
        volatile unsigned int lock;
-} spinlock_t;
+};


-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
+#define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 }

 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -60,18 +60,21 @@
 #define spin_unlock_string \
        "movb $1,%0"

-static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
+static inline __attribute__((always_inline)) void spin_lock(struct spinlock *lock)
 {
        __asm__ __volatile__(
                spin_lock_string
                :"=m" (lock->lock) : : "memory");
 }

-static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
+static inline __attribute__((always_inline)) void spin_unlock(struct spinlock *lock)
 {
        __asm__ __volatile__(
                spin_unlock_string
                :"=m" (lock->lock) : : "memory");
 }

+#define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
+
+
 #endif /* ARCH_SPINLOCK_H */
Index: device/device.c
===================================================================
--- device/device.c     (revision 427)
+++ device/device.c     (working copy)
@@ -183,7 +183,9 @@
  * @return Pointer to the newly created device structure.
  * @see device_path
  */
-// static spinlock_t dev_lock = SPIN_LOCK_UNLOCKED;
+
+spin_define(dev_lock);
+
 struct device *alloc_dev(struct bus *parent, struct device_path *path,
                         struct device_id *devid)
 {



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Sun Jul  1 00:49:05 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 1 Jul 2007 00:49:05 +0200
Subject: [LinuxBIOS] [PATCH] v3 - put lar size in the bootblock
In-Reply-To: <20070630221141.GD5201@greenwood>
References: <20070630215814.GB31719@coresystems.de>
	<20070630221141.GD5201@greenwood>
Message-ID: <20070630224905.GB25735@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070701 00:11]:
> > +       int i;
> > +       uint32_t *size_pos;
> 
> u32
 
No, this is userspace. We don't have u32 here.

 
> > -                       if (strcmp("lzma", optarg) == 0) {
> > +                       if (strcasecmp("lzma", optarg) == 0) {
> 
> OK, I guess, but not all systems might have strcasecmp (I think it's
> called stricmp() on some). Not critical right now, though...
 
ieks. good point. Which are those again?

> > +        */
> > +       archive.len = *(u32 *)0xfffffff4;
> > +       archive.start =(void *)(0UL-archive.len);
>  
> 
> Something seems wrong with the patch, doesn't apply here (mailer issue?)

Yes, whitespaces are broken. I can't get the patches to my mailer except
cut and paste :-((( ssh works, scp does not 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From peter at stuge.se  Sun Jul  1 00:51:38 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 00:51:38 +0200
Subject: [LinuxBIOS] ELF loader in v3
In-Reply-To: <20070629205525.GA30011@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
References: <4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
	<20070629205525.GA30011@coresystems.de>
	<4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
Message-ID: <20070630225138.26958.qmail@stuge.se>

On Fri, Jun 29, 2007 at 10:03:26PM +0200, Patrick Georgi wrote:
> My proposal would be to decompress the ELF image to some location,
> lookk if that location overlaps with the places the data is copied
> to, and if so, determine a large-enough chunk of memory and
> decompress it to there again

Sorry, NAK. I don't like unneccessary work.

If need be, teach elfboot to peek into compressed streams so that it
can tell the decompressor a safe place to decomress to.


On Fri, Jun 29, 2007 at 10:55:25PM +0200, Stefan Reinauer wrote:
> >  Right now, my solution is to mark it nocompress:, before that,
> >  I just decompressed it to a fixed location for experimentation.
> >  It has to be done one way or the other.
> 
> I think the uncompress: marker is fine.

It must be automatic.


> I think we really want to freeze lar in the long or even short run.

Certainly, but let's wait until later.


//Peter



From rminnich at gmail.com  Sun Jul  1 00:51:47 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 30 Jun 2007 15:51:47 -0700
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
In-Reply-To: <20070630224604.GA25735@coresystems.de>
References: <20070630224604.GA25735@coresystems.de>
Message-ID: <13426df10706301551k438f555bjc325d3dbbc91cd3@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

A new record!

ron

On 6/30/07, Stefan Reinauer <stepan at coresystems.de> wrote:
> * fix copyright headers to v2 only as suggested by Uwe
> * drop silly code when not using SMP
> * fix device/device.c
> * drop spinlock_t, use struct spinlock instead.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>
>
> Index: include/spinlock.h
> ===================================================================
> --- include/spinlock.h  (revision 427)
> +++ include/spinlock.h  (working copy)
> @@ -2,11 +2,11 @@
>   * This file is part of the LinuxBIOS project.
>   *
>   * Copyright (C) 2001 Linux Networx
> + * Copyright (C) 2007 coresystems GmbH
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> + * the Free Software Foundation; version 2 of the License.
>   *
>   * This program is distributed in the hope that it will be useful,
>   * but WITHOUT ANY WARRANTY; without even the implied warranty of
> @@ -22,23 +22,17 @@
>  #define SPINLOCK_H
>
>  #if defined(CONFIG_SMP) && CONFIG_SMP == 1
> +
>  #include <arch/spinlock.h>
> +
>  #else /* !CONFIG_SMP */
>
> -/* Most GCC versions have a nasty bug with empty initializers */
> -#if (__GNUC__ > 2)
> -typedef struct { } spinlock_t;
> -#define SPIN_LOCK_UNLOCKED (spinlock_t) { }
> -#else
> -typedef struct { int gcc_is_buggy; } spinlock_t;
> -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
> -#endif
> -
>  #define barrier()              do {} while(0)
>  #define spin_is_locked(lock)   0
>  #define spin_unlock_wait(lock) do {} while(0)
>  #define spin_lock(lock)                do {} while(0)
>  #define spin_unlock(lock)      do {} while(0)
> +#define spin_define(lock)       /* empty */
>  #endif
>
>  #endif /* SPINLOCK_H */
> Index: include/arch/x86/arch/spinlock.h
> ===================================================================
> --- include/arch/x86/arch/spinlock.h    (revision 427)
> +++ include/arch/x86/arch/spinlock.h    (working copy)
> @@ -2,11 +2,11 @@
>   * This file is part of the LinuxBIOS project.
>   *
>   * Copyright (C) 2001 Linux Networx
> + * Copyright (C) 2007 coresystems GmbH
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> + * the Free Software Foundation; version 2 of the License.
>   *
>   * This program is distributed in the hope that it will be useful,
>   * but WITHOUT ANY WARRANTY; without even the implied warranty of
> @@ -25,12 +25,12 @@
>   * Your basic SMP spinlocks, allowing only a single CPU anywhere
>   */
>
> -typedef struct {
> +struct spinlock {
>         volatile unsigned int lock;
> -} spinlock_t;
> +};
>
>
> -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
> +#define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 }
>
>  /*
>   * Simple spin lock operations.  There are two variants, one clears IRQ's
> @@ -60,18 +60,21 @@
>  #define spin_unlock_string \
>         "movb $1,%0"
>
> -static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
> +static inline __attribute__((always_inline)) void spin_lock(struct spinlock *lock)
>  {
>         __asm__ __volatile__(
>                 spin_lock_string
>                 :"=m" (lock->lock) : : "memory");
>  }
>
> -static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
> +static inline __attribute__((always_inline)) void spin_unlock(struct spinlock *lock)
>  {
>         __asm__ __volatile__(
>                 spin_unlock_string
>                 :"=m" (lock->lock) : : "memory");
>  }
>
> +#define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
> +
> +
>  #endif /* ARCH_SPINLOCK_H */
> Index: device/device.c
> ===================================================================
> --- device/device.c     (revision 427)
> +++ device/device.c     (working copy)
> @@ -183,7 +183,9 @@
>   * @return Pointer to the newly created device structure.
>   * @see device_path
>   */
> -// static spinlock_t dev_lock = SPIN_LOCK_UNLOCKED;
> +
> +spin_define(dev_lock);
> +
>  struct device *alloc_dev(struct bus *parent, struct device_path *path,
>                          struct device_id *devid)
>  {
>
>
>
> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios



From svn at openbios.org  Sun Jul  1 00:55:10 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  1 Jul 2007 00:55:10 +0200
Subject: [LinuxBIOS] r429 - in LinuxBIOSv3: device include
	include/arch/x86/arch
Message-ID: <mailman.491.1355071128.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-07-01 00:55:10 +0200 (Sun, 01 Jul 2007)
New Revision: 429

Modified:
   LinuxBIOSv3/device/device.c
   LinuxBIOSv3/include/arch/x86/arch/spinlock.h
   LinuxBIOSv3/include/spinlock.h
Log:
* fix copyright headers to v2 only as suggested by Uwe
* drop silly code when not using SMP
* fix device/device.c
* drop spinlock_t, use struct spinlock instead.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>

one kitten died already! ;-)



Modified: LinuxBIOSv3/device/device.c
===================================================================
--- LinuxBIOSv3/device/device.c	2007-06-30 22:09:57 UTC (rev 428)
+++ LinuxBIOSv3/device/device.c	2007-06-30 22:55:10 UTC (rev 429)
@@ -183,7 +183,9 @@
  * @return Pointer to the newly created device structure.
  * @see device_path
  */
-// static spinlock_t dev_lock = SPIN_LOCK_UNLOCKED;
+
+spin_define(dev_lock);
+
 struct device *alloc_dev(struct bus *parent, struct device_path *path,
 			 struct device_id *devid)
 {

Modified: LinuxBIOSv3/include/arch/x86/arch/spinlock.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-06-30 22:09:57 UTC (rev 428)
+++ LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-06-30 22:55:10 UTC (rev 429)
@@ -2,11 +2,11 @@
  * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2001 Linux Networx
+ * Copyright (C) 2007 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * the Free Software Foundation; version 2 of the License.
  * 
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -25,12 +25,12 @@
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */
 
-typedef struct {
+struct spinlock {
 	volatile unsigned int lock;
-} spinlock_t;
+};
 
 
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
+#define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 }
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -60,18 +60,21 @@
 #define spin_unlock_string \
 	"movb $1,%0"
 
-static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
+static inline __attribute__((always_inline)) void spin_lock(struct spinlock *lock)
 {
 	__asm__ __volatile__(
 		spin_lock_string
 		:"=m" (lock->lock) : : "memory");
 }
 
-static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
+static inline __attribute__((always_inline)) void spin_unlock(struct spinlock *lock)
 {
 	__asm__ __volatile__(
 		spin_unlock_string
 		:"=m" (lock->lock) : : "memory");
 }
 
+#define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
+
+
 #endif /* ARCH_SPINLOCK_H */

Modified: LinuxBIOSv3/include/spinlock.h
===================================================================
--- LinuxBIOSv3/include/spinlock.h	2007-06-30 22:09:57 UTC (rev 428)
+++ LinuxBIOSv3/include/spinlock.h	2007-06-30 22:55:10 UTC (rev 429)
@@ -2,11 +2,11 @@
  * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2001 Linux Networx
+ * Copyright (C) 2007 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * the Free Software Foundation; version 2 of the License.
  * 
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -22,23 +22,17 @@
 #define SPINLOCK_H
 
 #if defined(CONFIG_SMP) && CONFIG_SMP == 1
+
 #include <arch/spinlock.h>
+
 #else /* !CONFIG_SMP */
 
-/* Most GCC versions have a nasty bug with empty initializers */
-#if (__GNUC__ > 2) 
-typedef struct { } spinlock_t;
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { }
-#else
-typedef struct { int gcc_is_buggy; } spinlock_t;
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
-#endif
-
 #define barrier()		do {} while(0)
 #define spin_is_locked(lock)	0
 #define spin_unlock_wait(lock)	do {} while(0)
 #define spin_lock(lock)		do {} while(0)
 #define spin_unlock(lock)	do {} while(0)
+#define spin_define(lock)       /* empty */
 #endif
 
 #endif /* SPINLOCK_H */




From stepan at coresystems.de  Sun Jul  1 00:57:12 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 1 Jul 2007 00:57:12 +0200
Subject: [LinuxBIOS] ELF loader in v3
In-Reply-To: <20070630225138.26958.qmail@stuge.se>
References: <4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
	<20070629205525.GA30011@coresystems.de>
	<4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
	<20070630225138.26958.qmail@stuge.se>
Message-ID: <20070630225712.GA30777@coresystems.de>

* Peter Stuge <peter at stuge.se> [070701 00:51]:
> > >  Right now, my solution is to mark it nocompress:, before that,
> > >  I just decompressed it to a fixed location for experimentation.
> > >  It has to be done one way or the other.
> > 
> > I think the uncompress: marker is fine.
> 
> It must be automatic.
 
How would l ar know which modules must not be compressed? We have to
teach it at some place.

Jordan Crouse has a surprise for us in a couple of days I guess.

> > I think we really want to freeze lar in the long or even short run.
> 
> Certainly, but let's wait until later.

Yes.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Sun Jul  1 00:57:43 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 1 Jul 2007 00:57:43 +0200
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
In-Reply-To: <20070630224604.GA25735@coresystems.de>
References: <20070630224604.GA25735@coresystems.de>
Message-ID: <20070630225743.GG5201@greenwood>

On Sun, Jul 01, 2007 at 12:46:04AM +0200, Stefan Reinauer wrote:
> -/* Most GCC versions have a nasty bug with empty initializers */
> -#if (__GNUC__ > 2)
> -typedef struct { } spinlock_t;
> -#define SPIN_LOCK_UNLOCKED (spinlock_t) { }
> -#else
> -typedef struct { int gcc_is_buggy; } spinlock_t;
> -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
> -#endif
> -

ACK. Sending a similar patch was already on my TODO list. We don't care
about gcc <= 3, I guess.


>  #define barrier()              do {} while(0)
>  #define spin_is_locked(lock)   0
>  #define spin_unlock_wait(lock) do {} while(0)
>  #define spin_lock(lock)                do {} while(0)
>  #define spin_unlock(lock)      do {} while(0)
> +#define spin_define(lock)       /* empty */

Why not this?
#define spin_define(lock) do {} while(0)


> +#define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED

Uh, that looks like an inline function might be better here.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Sun Jul  1 01:01:54 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 1 Jul 2007 01:01:54 +0200
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
In-Reply-To: <20070630225743.GG5201@greenwood>
References: <20070630224604.GA25735@coresystems.de>
	<20070630225743.GG5201@greenwood>
Message-ID: <20070630230154.GA1147@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070701 00:57]:
> On Sun, Jul 01, 2007 at 12:46:04AM +0200, Stefan Reinauer wrote:
> > -/* Most GCC versions have a nasty bug with empty initializers */
> > -#if (__GNUC__ > 2)
> > -typedef struct { } spinlock_t;
> > -#define SPIN_LOCK_UNLOCKED (spinlock_t) { }
> > -#else
> > -typedef struct { int gcc_is_buggy; } spinlock_t;
> > -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
> > -#endif
> > -
> 
> ACK. Sending a similar patch was already on my TODO list. We don't care
> about gcc <= 3, I guess.

Check the code, it will work on pre v3 like a charme. I don't know what
those Linux guys must have been smoking, but I better don't try it.

> >  #define spin_unlock(lock)      do {} while(0)
> > +#define spin_define(lock)       /* empty */
> 
> Why not this?
> #define spin_define(lock) do {} while(0)
 
Haha. I had this first. But a do .. while construct outside a function
scope is nothing gcc (or any other compiler) would handle :-)

> > +#define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
> 
> Uh, that looks like an inline function might be better here.

Not sure I get what you mean.. This one defines a (file) global
variable.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From peter at stuge.se  Sun Jul  1 01:20:22 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 01:20:22 +0200
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <20070630214319.GA31719@coresystems.de>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
Message-ID: <20070630232022.466.qmail@stuge.se>

On Sat, Jun 30, 2007 at 11:43:20PM +0200, Stefan Reinauer wrote:
> So instead of adding enabled; to all device nodes, we should add
> disabled to those that we do not want enabled. What do you think?

We should definately optimize for the common case whatever it is.


//Peter



From peter at stuge.se  Sun Jul  1 01:23:32 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 01:23:32 +0200
Subject: [LinuxBIOS] r418 - in LinuxBIOSv3: arch/x86 device
	include	include/arch/x86 include/arch/x86/arch include/device
	lib util/dtc
In-Reply-To: <20070630193832.GA25213@coresystems.de>
References: <20070630191833.GM10622@greenwood>
	<20070630193832.GA25213@coresystems.de>
Message-ID: <20070630232332.1018.qmail@stuge.se>

On Sat, Jun 30, 2007 at 09:38:32PM +0200, Stefan Reinauer wrote:
> > > +#define barrier() __asm__ __volatile__("": : :"memory")
> > 
> > #define barrier() (__asm__ __volatile__("": : :"memory"))
> 
> this will break code using it. try barrier(); 

#define barier() do { __asm__ .. } while(0)

is common, does it work here?


//Peter



From peter at stuge.se  Sun Jul  1 01:27:05 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 01:27:05 +0200
Subject: [LinuxBIOS] r418 - in LinuxBIOSv3: arch/x86 device include
	include/arch/x86 include/arch/x86/arch include/device lib util/dtc
In-Reply-To: <13426df10706301456n95187e9m6642eade1ca199e3@mail.gmail.com>
References: <20070630191833.GM10622@greenwood>
	<20070630193832.GA25213@coresystems.de>
	<13426df10706301456n95187e9m6642eade1ca199e3@mail.gmail.com>
Message-ID: <20070630232705.1554.qmail@stuge.se>

On Sat, Jun 30, 2007 at 02:56:22PM -0700, ron minnich wrote:
> we need to learn how to use stuff like mb(). Oh joy :-)

Isn't all that bad..

Call wmb() to "commit" writes. Call rmb() to "commit" reads. Call
mb() to "commit" both.

Good thing they have short names.


//Peter



From rminnich at gmail.com  Sun Jul  1 01:27:27 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 30 Jun 2007 16:27:27 -0700
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <20070630232022.466.qmail@stuge.se>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
Message-ID: <13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>

On 6/30/07, Peter Stuge <peter at stuge.se> wrote:
> On Sat, Jun 30, 2007 at 11:43:20PM +0200, Stefan Reinauer wrote:
> > So instead of adding enabled; to all device nodes, we should add
> > disabled to those that we do not want enabled. What do you think?
>
> We should definately optimize for the common case whatever it is.

What I can do is look for a disable property in each node. If it is
NOT found, emit
.enabled = 1;
If it is found,
.enabled = 0;

sound ok?

ron



From peter at stuge.se  Sun Jul  1 01:34:39 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 01:34:39 +0200
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
Message-ID: <20070630233439.2638.qmail@stuge.se>

On Sat, Jun 30, 2007 at 04:27:27PM -0700, ron minnich wrote:
> What I can do is look for a disable property in each node. If it is
> NOT found, emit
> .enabled = 1;
> If it is found,
> .enabled = 0;
> 
> sound ok?

Yes sir! As long as enabled is more common than disabled.


//Peter



From uwe at hermann-uwe.de  Sun Jul  1 02:07:37 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 1 Jul 2007 02:07:37 +0200
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
Message-ID: <20070701000736.GH5201@greenwood>

On Sat, Jun 30, 2007 at 04:27:27PM -0700, ron minnich wrote:
> On 6/30/07, Peter Stuge <peter at stuge.se> wrote:
> > On Sat, Jun 30, 2007 at 11:43:20PM +0200, Stefan Reinauer wrote:
> > > So instead of adding enabled; to all device nodes, we should add
> > > disabled to those that we do not want enabled. What do you think?
> >
> > We should definately optimize for the common case whatever it is.
> 
> What I can do is look for a disable property in each node. If it is
> NOT found, emit
> .enabled = 1;
> If it is found,
> .enabled = 0;
> 
> sound ok?

Why not, instead of 'enabled;', use
  enabled="0"
or 
  enabled="1"
then? That has the benefit that you don't have to know what the default
is (enabled or disabled), you know everything you need just by looking
at the dts itself.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Sun Jul  1 02:14:03 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 1 Jul 2007 02:14:03 +0200
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
In-Reply-To: <20070630230154.GA1147@coresystems.de>
References: <20070630224604.GA25735@coresystems.de>
	<20070630225743.GG5201@greenwood>
	<20070630230154.GA1147@coresystems.de>
Message-ID: <20070701001402.GI5201@greenwood>

On Sun, Jul 01, 2007 at 01:01:54AM +0200, Stefan Reinauer wrote:
> > >  #define spin_unlock(lock)      do {} while(0)
> > > +#define spin_define(lock)       /* empty */
> > 
> > Why not this?
> > #define spin_define(lock) do {} while(0)
>  
> Haha. I had this first. But a do .. while construct outside a function
> scope is nothing gcc (or any other compiler) would handle :-)

Yep.

 
> > > +#define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
> > 
> > Uh, that looks like an inline function might be better here.
> 
> Not sure I get what you mean.. This one defines a (file) global
> variable.

OK, I totally misread what the code is supposed to do.

I'm not sure the spin_define() is such a good idea then. It has a nice
name and all, but it might be obfuscating things more than necessary.
Maybe a simple variable declaration (i.e., drop the #define) would be better?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From c-d.hailfinger.devel.2006 at gmx.net  Sun Jul  1 02:21:04 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 01 Jul 2007 02:21:04 +0200
Subject: [LinuxBIOS] ELF loader in v3
In-Reply-To: <20070630225138.26958.qmail@stuge.se>
References: <4682B253.3020909@georgi-clan.de>	<20070629185641.GA29163@coresystems.de>	<4685658E.6080700@georgi-clan.de>	<20070629205525.GA30011@coresystems.de>	<4682B253.3020909@georgi-clan.de>	<20070629185641.GA29163@coresystems.de>	<4685658E.6080700@georgi-clan.de>
	<20070630225138.26958.qmail@stuge.se>
Message-ID: <4686F370.5020908@gmx.net>

On 01.07.2007 00:51, Peter Stuge wrote:
> On Fri, Jun 29, 2007 at 10:03:26PM +0200, Patrick Georgi wrote:
>> My proposal would be to decompress the ELF image to some location,
>> lookk if that location overlaps with the places the data is copied
>> to, and if so, determine a large-enough chunk of memory and
>> decompress it to there again
> 
> Sorry, NAK. I don't like unneccessary work.
> 
> If need be, teach elfboot to peek into compressed streams so that it
> can tell the decompressor a safe place to decomress to.

Sorry, our implementation of lzma decompression does not decompress
to a stream, only in bulk. Choosing streaming decompression is
possible, but the memory requirements made me decide against it.
Decompression speed is also significantly slower for streaming lzma
decompression.

Regards,
Carl-Daniel



From rminnich at gmail.com  Sun Jul  1 05:46:44 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 30 Jun 2007 20:46:44 -0700
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <20070701000736.GH5201@greenwood>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
	<20070701000736.GH5201@greenwood>
Message-ID: <13426df10706302046s6c6e4732m2d1b9f44824fdde1@mail.gmail.com>

On 6/30/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Sat, Jun 30, 2007 at 04:27:27PM -0700, ron minnich wrote:
> > On 6/30/07, Peter Stuge <peter at stuge.se> wrote:
> > > On Sat, Jun 30, 2007 at 11:43:20PM +0200, Stefan Reinauer wrote:
> > > > So instead of adding enabled; to all device nodes, we should add
> > > > disabled to those that we do not want enabled. What do you think?
> > >
> > > We should definately optimize for the common case whatever it is.
> >
> > What I can do is look for a disable property in each node. If it is
> > NOT found, emit
> > .enabled = 1;
> > If it is found,
> > .enabled = 0;
> >
> > sound ok?
>
> Why not, instead of 'enabled;', use
>   enabled="0"
> or
>   enabled="1"
> then? That has the benefit that you don't have to know what the default
> is (enabled or disabled), you know everything you need just by looking
> at the dts itself.
>
>
> Uwe.
> --
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
>
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.6 (GNU/Linux)
>
> iD8DBQFGhvBIXdVoV3jWIbQRAgQoAJ0dDBxSH2BlcI7u0ldL93XOtM57/gCbB7nD
> 120zDwDQEbqpwuyLjU8xfAE=
> =hPcG
> -----END PGP SIGNATURE-----
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>



From rminnich at gmail.com  Sun Jul  1 05:48:22 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 30 Jun 2007 20:48:22 -0700
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <20070701000736.GH5201@greenwood>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
	<20070701000736.GH5201@greenwood>
Message-ID: <13426df10706302048v330c243qf15befd1daba6371@mail.gmail.com>

Sorry about the lats empty message. Gmail did something, I know not what.


On 6/30/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Sat, Jun 30, 2007 at 04:27:27PM -0700, ron minnich wrote:

> > What I can do is look for a disable property in each node. If it is
> > NOT found, emit
> > .enabled = 1;
> > If it is found,
> > .enabled = 0;
> >
> > sound ok?
>
> Why not, instead of 'enabled;', use
>   enabled="0"
> or
>   enabled="1"
> then? That has the benefit that you don't have to know what the default
> is (enabled or disabled), you know everything you need just by looking
> at the dts itself.

yeah, that works. I will take the magic enabled out of the .y, and
will require that people set that property for each node; I will catch
a missing set at flatten tree time. I think that is reasonable.

This will get done next week, I'm out of time for a bit. Or someone
else can write it, which is fine too.

ron



From libv at skynet.be  Sun Jul  1 20:00:57 2007
From: libv at skynet.be (Luc Verhaegen)
Date: Sun, 1 Jul 2007 20:00:57 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070630190254.GL10622@greenwood>
References: <20070630190254.GL10622@greenwood>
Message-ID: <20070701180057.GA24639@skynet.be>

On Sat, Jun 30, 2007 at 09:02:54PM +0200, Uwe Hermann wrote:
> Hi all,
> 
> please note that we're planning to create a new top-level directory
> 'util' in svn where independant utilities (which are not tied to a
> certain LinuxBIOS version) will reside.
> 
> One of these utilities will be flashrom, but others will follow.
> 
> The new repository layout will look like this:
> 
> - trunk
>   - LinuxBIOSv1
>   - LinuxBIOSv2
>   - LinuxBIOSv3 (later)
>   - util
>     - flashrom
>     - ...
> 
> The current trunk/LinuxBIOSv2/util/flashrom will be moved into
> trunk/util per 'svn mv', so the history will remain intact.
> 
> trunk/LinuxBIOSv2/util/flashrom will then become a svn:externals entry,
> that is, it will still _look_ like it's in the LinuxBIOSv2 tree, but
> it'll actually be checked out from trunk/util/flashrom.
>
> LinuxBIOSv3 will probably also "get" flashrom via svn:externals into
> the util/flashrom directory.

I fully agree with the earlier stuff, but is there any reason to keep
this in the v3 tree? People will not be that unhappy if they're required 
to pull in the flashrom utility seperately, and i'm not sure, but i 
think that in some cases, the likes of uniflash can be used to flash a 
linuxbios too.

I personally don't think there should be a place in the v3 tree for a 
utility like this, as it leads an almost completely independent life.

> The transition should be painless (a simple 'svn up' should do), but
> just in case there are problems, please make sure you save all pending
> flashrom patches/modifications you may have. If there are problems
> please let us know (try a fresh checkout before, though).
> 
> If nobody objects, I'll perform the required actions later this day or
> tomorrow.
> 
> 
> Thanks, Uwe.

Luc Verhaegen.



From segher at kernel.crashing.org  Sun Jul  1 21:12:36 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Sun, 1 Jul 2007 21:12:36 +0200
Subject: [LinuxBIOS] [PATCH] v3 - put lar size in the bootblock
In-Reply-To: <20070630224905.GB25735@coresystems.de>
References: <20070630215814.GB31719@coresystems.de>
	<20070630221141.GD5201@greenwood>
	<20070630224905.GB25735@coresystems.de>
Message-ID: <8df5675b4582f5c80acb95aaba030239@kernel.crashing.org>

>> OK, I guess, but not all systems might have strcasecmp (I think it's
>> called stricmp() on some). Not critical right now, though...
>
> ieks. good point. Which are those again?

Non-POSIX systems.  Do we care?


Segher




From svn at openbios.org  Sun Jul  1 21:41:04 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  1 Jul 2007 21:41:04 +0200
Subject: [LinuxBIOS] r2729 - trunk
Message-ID: <mailman.492.1355071128.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-01 21:41:04 +0200 (Sun, 01 Jul 2007)
New Revision: 2729

Added:
   trunk/util/
Log:
Add directory for various utilities which are not bound to a certain
LinuxBIOS version (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>






From svn at openbios.org  Sun Jul  1 21:42:39 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  1 Jul 2007 21:42:39 +0200
Subject: [LinuxBIOS] r2730 - in trunk: LinuxBIOSv2/util util
Message-ID: <mailman.493.1355071129.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-01 21:42:39 +0200 (Sun, 01 Jul 2007)
New Revision: 2730

Added:
   trunk/util/flashrom/
Removed:
   trunk/LinuxBIOSv2/util/flashrom/
Log:
Move 'flashrom' into global util/flashrom svn directory, as it's not
LinuxBIOSv2-specific (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Copied: trunk/util/flashrom (from rev 2728, trunk/LinuxBIOSv2/util/flashrom)




From svn at openbios.org  Sun Jul  1 21:47:31 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  1 Jul 2007 21:47:31 +0200
Subject: [LinuxBIOS] r2731 - trunk/LinuxBIOSv2/util
Message-ID: <mailman.494.1355071129.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-01 21:47:31 +0200 (Sun, 01 Jul 2007)
New Revision: 2731

Modified:
   trunk/LinuxBIOSv2/util/
Log:
Grab flashrom from the new location via svn:externals (trivial).

Note that this is just a "copy" (sort of), the "real" location of
the flashrom code is now svn://linuxbios.org/repos/trunk/util/flashrom.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>




Property changes on: trunk/LinuxBIOSv2/util
___________________________________________________________________
Name: svn:externals
   + flashrom svn://linuxbios.org/repos/trunk/util/flashrom





From info at coresystems.de  Sun Jul  1 22:26:19 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 01 Jul 2007 22:26:19 +0200
Subject: [LinuxBIOS] r2729 build service
Message-ID: <E1I55zv-0005Ay-55@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "" checked in revision 2729 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:


Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2729&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2729&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2729&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2729&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2729&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2729&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in 's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From info at coresystems.de  Sun Jul  1 23:16:42 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 01 Jul 2007 23:16:42 +0200
Subject: [LinuxBIOS] r2730 build service
Message-ID: <E1I56mg-0001xc-Al@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2730 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Move 'flashrom' into global util/flashrom svn directory, as it's not
LinuxBIOSv2-specific (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2730&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2730&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2730&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2730&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2730&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2730&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From peter at stuge.se  Sun Jul  1 23:57:34 2007
From: peter at stuge.se (Peter Stuge)
Date: Sun, 1 Jul 2007 23:57:34 +0200
Subject: [LinuxBIOS] r2731 - trunk/LinuxBIOSv2/util
Message-ID: <20070701215734.22994.qmail@stuge.se>

On Sun, Jul 01, 2007 at 09:47:31PM +0200, svn at openbios.org wrote:
> Name: svn:externals
>    + flashrom svn://linuxbios.org/repos/trunk/util/flashrom

Do we want a completely new repo for utils?


//Peter



From info at coresystems.de  Mon Jul  2 00:12:46 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Mon, 02 Jul 2007 00:12:46 +0200
Subject: [LinuxBIOS] r2731 build service
Message-ID: <E1I57ew-00014t-8s@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2731 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Grab flashrom from the new location via svn:externals (trivial).

Note that this is just a "copy" (sort of), the "real" location of
the flashrom code is now svn://linuxbios.org/repos/trunk/util/flashrom.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2731&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2731&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2731&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2731&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2731&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2731&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From uwe at hermann-uwe.de  Mon Jul  2 00:30:35 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 2 Jul 2007 00:30:35 +0200
Subject: [LinuxBIOS] r2731 - trunk/LinuxBIOSv2/util
In-Reply-To: <20070701215734.22994.qmail@stuge.se>
References: <20070701215734.22994.qmail@stuge.se>
Message-ID: <20070701223035.GA27613@greenwood>

On Sun, Jul 01, 2007 at 11:57:34PM +0200, Peter Stuge wrote:
> On Sun, Jul 01, 2007 at 09:47:31PM +0200, svn at openbios.org wrote:
> > Name: svn:externals
> >    + flashrom svn://linuxbios.org/repos/trunk/util/flashrom
> 
> Do we want a completely new repo for utils?

No, I don't think so. On the contrary, we want to have LinuxBIOSv3 in
the same repo, too.

Thus:

 - trunk
   - LinuxBIOSv1
   - LinuxBIOSv2
   - LinuxBIOSv3
   - util
     - flashrom
     - ...

The advantage is that all moves are easy and retain the history, and also
that we can use one and the same trac instance to track bugs and
feature requests of _all_ our code, plus common svn code browsers etc, etc.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Mon Jul  2 00:34:51 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 2 Jul 2007 00:34:51 +0200
Subject: [LinuxBIOS] r2731 - trunk/LinuxBIOSv2/util
In-Reply-To: <20070701215734.22994.qmail@stuge.se>
References: <20070701215734.22994.qmail@stuge.se>
Message-ID: <20070701223451.GA8409@coresystems.de>

* Peter Stuge <peter at stuge.se> [070701 23:57]:
> On Sun, Jul 01, 2007 at 09:47:31PM +0200, svn at openbios.org wrote:
> > Name: svn:externals
> >    + flashrom svn://linuxbios.org/repos/trunk/util/flashrom
> 
> Do we want a completely new repo for utils?

Yes we do.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Mon Jul  2 00:38:32 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 2 Jul 2007 00:38:32 +0200
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <13426df10706302048v330c243qf15befd1daba6371@mail.gmail.com>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
	<20070701000736.GH5201@greenwood>
	<13426df10706302048v330c243qf15befd1daba6371@mail.gmail.com>
Message-ID: <20070701223832.GB8409@coresystems.de>

* ron minnich <rminnich at gmail.com> [070701 05:48]:
> > then? That has the benefit that you don't have to know what the default
> > is (enabled or disabled), you know everything you need just by looking
> > at the dts itself.
> 
> yeah, that works. I will take the magic enabled out of the .y, and
> will require that people set that property for each node; I will catch
> a missing set at flatten tree time. I think that is reasonable.
 
Please dont do that. I think it is reasonable to assume that a device
that you specify is enabled. Otherwise why would you specify it? 

I dont like overspecifying completely obvious things in description files.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Mon Jul  2 00:50:04 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 2 Jul 2007 00:50:04 +0200
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
In-Reply-To: <20070701001402.GI5201@greenwood>
References: <20070630224604.GA25735@coresystems.de>
	<20070630225743.GG5201@greenwood>
	<20070630230154.GA1147@coresystems.de>
	<20070701001402.GI5201@greenwood>
Message-ID: <20070701225004.GC8409@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070701 02:14]:
> OK, I totally misread what the code is supposed to do.
> 
> I'm not sure the spin_define() is such a good idea then. It has a nice
> name and all, but it might be obfuscating things more than necessary.
> Maybe a simple variable declaration (i.e., drop the #define) would be better?

I don't see why it would be better, there are no obvious advantages, but
some obvious disadvantages.
Here our principles start clashing. We can't do this for several
reasons:

* The declaration is static, so it has to be surrounded by #if
  defined(CONFIG_SMP) would waste all the places in the code. This is 
  controverse to our goal to make changes as local as possible.
  If we don't, we end up with warnings in the code for almost every
  board

* Since some of us started hating typedefs, we don't have anything to
  declare anymore. You simply can not rely that a spinlock is
  represented by struct spinlock on all possible systems.
  So to get this done right, we would have to go back to spinlock_t,
  in which case I would vote to also go back to device_t and all the
  others, so we stay consistent.


Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From xiongyi04 at gmail.com  Mon Jul  2 20:20:38 2007
From: xiongyi04 at gmail.com (Xiong Yi)
Date: Mon, 2 Jul 2007 11:20:38 -0700
Subject: [LinuxBIOS] EFI Payload help: how to identify the resource types
	and attributes in LB
Message-ID: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>

Hi, all

 

I am developing the EFI payload for LB (see
http://code.google.com/soc/2007/coresystems/appinfo.html?csaid=83B941F46A422
F1A).

And I am unifying the resource management of LB and EFI. In more details, I
am parsing the LB table and converting it to the HOB structures of Tiano
EFI.

I described this idea several days ago.
(http://www.linuxbios.org/pipermail/linuxbios/2007-June/022340.html) 

 

But there is a problem:

 

The Tiano EFI describes the system resources as types and attributes, such
as the following definition:

 //*********************************************************

// EFI_RESOURCE_TYPE (define the resource type)

//*********************************************************

typedef UINT32 EFI_RESOURCE_TYPE;

#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000 (system memory resource)

#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 (memory-mapped IO)

#define EFI_RESOURCE_IO 0x00000002 (Processor IO space)

#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 (Memory-mapped firmware
device)

#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005 (Reserved memory address
space)

#define EFI_RESOURCE_IO_RESERVED 0x00000006 (Reserved IO address space)

 

//**************************************************************************
********

// EFI_RESOURCE_ATTRIBUTE_TYPE(define the resource attributes)

//**************************************************************************
********

 

typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;

// These types can be ORed together as needed.

#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 (the memory region exists)

#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 (the memory region has
been initialized)

#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 (the memory region has been
tested)

 

And there are similar definitions in the LB's /src/include/device/resourch.h
file.

But I can just find 

IORESOURCE_MEM | IORESOURCE_CACHEABLE (system memory) resources types and 

LB_MEM_RAM, LB_MEM_TABLE attributes in the LB tables. 

 

So how to identify other resource types and attributes in LB?

Or the current LB implementation just describes these types and attributes, 

I need to construct the rest resource types and attributes in the payload
itself as the exact requirement?

 

By the way, I built the LB with qemu emulation and just track qemu emulation
LB's source codes.

 

Thanks & Best regards,

 

Xiong Yi

 

 

 

 

 

 

 

 

 

 

 

 

 

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From ebiederman at lnxi.com  Mon Jul  2 06:03:58 2007
From: ebiederman at lnxi.com (Eric W. Biederman)
Date: Sun, 01 Jul 2007 22:03:58 -0600
Subject: [LinuxBIOS] ELF loader in v3
In-Reply-To: <13426df10706291427p39eed310l4bf095eedbd8f47c@mail.gmail.com> (ron
	minnich's message of "Fri, 29 Jun 2007 14:27:12 -0700")
References: <4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
	<20070629205525.GA30011@coresystems.de>
	<13426df10706291427p39eed310l4bf095eedbd8f47c@mail.gmail.com>
Message-ID: <m3hconpi35.fsf@maxwell.lnxi.com>

"ron minnich" <rminnich at gmail.com> writes:

> I think we have a lot of control with the ROM payload, so much so that
> requiring it to locate itself above 512K is a simple thing to do.
> LinuxBIOS does not load general payloads, just ROM payloads, and it is
> reasonable to create some restrictions.

There are a couple of options here.  Ideally linuxbios would execute
from the end of ram instead of the beginning which would mean all
architecturally defined addresses would be free for use for the
payload.  I think I handle this in etherboot by simply running
from the end of memory.

It does sound like this is going to have to be a 2 step process,
decompress and then load.  So really only the code for the final
load step has to get out of the way.

I do know it can be nice to handle something fairly arbitrary and
it really wasn't that much code.

Eric



From peter at stuge.se  Mon Jul  2 08:13:14 2007
From: peter at stuge.se (Peter Stuge)
Date: Mon, 2 Jul 2007 08:13:14 +0200
Subject: [LinuxBIOS] ELF loader in v3
In-Reply-To: <4686F370.5020908@gmx.net>
References: <4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
	<20070629205525.GA30011@coresystems.de>
	<4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
	<20070630225138.26958.qmail@stuge.se> <4686F370.5020908@gmx.net>
Message-ID: <20070702061314.29634.qmail@stuge.se>

On Sun, Jul 01, 2007 at 02:21:04AM +0200, Carl-Daniel Hailfinger wrote:
> > If need be, teach elfboot to peek into compressed streams so that
> > it can tell the decompressor a safe place to decomress to.
> 
> Sorry, our implementation of lzma decompression does not decompress
> to a stream, only in bulk.

So compress only the ELF segments but not the header.

(This is a good reason to have compression built into lar, since
it would constitute crazy weird ELF trickery if done manually.)


//Peter



From darmawan.salihun at gmail.com  Mon Jul  2 11:17:51 2007
From: darmawan.salihun at gmail.com (Darmawan Salihun)
Date: Mon, 02 Jul 2007 16:17:51 +0700
Subject: [LinuxBIOS] Winflashrom -- Current Status
In-Reply-To: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>
References: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>
Message-ID: <4688C2BF.2040600@gmail.com>

Hi all,
     The diff for the latest winflashrom code is attached. There are
still a few issues with this code.

1. I've tested it on ICH-5 board. However, the BIOS binary that it reads
from it is 514KB. It should be only 512KB.
    I'm still trying to find out the bug. Any info from ICH-x code
maintainer?

2. The PCI library is still a "brute force" approach. But, it works so
far. I'll remove it soon enough.

More updates to come.

Cheers,
Darmawan
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From jordan.crouse at amd.com  Mon Jul  2 16:53:58 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 2 Jul 2007 08:53:58 -0600
Subject: [LinuxBIOS] ELF loader in v3
In-Reply-To: <20070630143256.GD10622@greenwood>
References: <4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<4685658E.6080700@georgi-clan.de>
	<20070629205525.GA30011@coresystems.de>
	<20070630143256.GD10622@greenwood>
Message-ID: <20070702145358.GB10819@cosmic.amd.com>

On 30/06/07 16:32 +0200, Uwe Hermann wrote:
> On Fri, Jun 29, 2007 at 10:55:25PM +0200, Stefan Reinauer wrote:
> > I think we really want to freeze lar in the long or even short run. we
> > should get this finished within the next few weeks. Lets not freeze or
> > version the format during development. If early versions stop working at
> > some point, that is not an issue. We dont run on any hardware, yet. 
> > Decompression is the only issue I see with this at the moment. :( It
> > will make us have several copies of the same stuff again :(
> 
> We definately need a version field in the lar header, we probably cannot
> use the same format forever, there _will_ be changes one day.

Agreed. Stefan and I discussed this briefly at OLS.

> I agree that we don't have to worry too much as long as there are no
> external users (yet). But in fact, the 'lar' binary itself will be an
> "external" user. It will be available from /usr/bin/lar or similar,
> as a general utility (_not_ bound to a specific revision of LinuxBIOS).
> 
> We'll use 'lar' to add entries (e.g. payloads) to existing images, remove
> entries, etc. etc., all from user space with the 'lar' tool.
> 
> Thus, this tool must know which version of a lar archives it works on,
> and it must contain backwards compatibility code, to not only handle
> the lar format which was the newest one when the tool was compiled,
> but also all older version (at least those, which were "released" or
> marked as "stable" or something)...
> 
> For now the work required to do this is almost zero, just add a
> 'version' entry to the lar header struct and ignore it's value.
> Later versions will have to read the version field and act accordingly.

I think now is the time to do that - we can easily break any lar users
now without much penalty.   Later, it won't be so easy.

Jordan

-- 
Jordan Crouse
Senior Linux Engineer
Advanced Micro Devices, Inc.
<www.amd.com/embeddedprocessors>





From jordan.crouse at amd.com  Mon Jul  2 16:59:31 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 2 Jul 2007 08:59:31 -0600
Subject: [LinuxBIOS] OLS audio/video/slides?
In-Reply-To: <20070630141830.GC10622@greenwood>
References: <4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<20070630141830.GC10622@greenwood>
Message-ID: <20070702145931.GC10819@cosmic.amd.com>

On 30/06/07 16:18 +0200, Uwe Hermann wrote:
> On Fri, Jun 29, 2007 at 08:56:41PM +0200, Stefan Reinauer wrote:
> > Jordan's talk here at the OLS described how LinuxBIOS relocates itself
> > from the very low space to TOM during the boot process.
> 
> Are there slides, audio recordings or video recordings available?

Slides will be forthcoming when I finish navigating the shark filled
waters of our web site.  Audio and video recordings will eventually be made
available on linuxsymposium.org as soon as they figure out how much it will
cost to produce them.

Also, the paper itself (which is more detailed then the presentation), is
here:  

https://ols2006.108.redhat.com/2007/Reprints/crouse-Reprint.pdf

That will also hopefully be on our website soon enough.  If you have any
questions, let me know.

Jordan

-- 
Jordan Crouse
Senior Linux Engineer
Advanced Micro Devices, Inc.
<www.amd.com/embeddedprocessors>





From jordan.crouse at amd.com  Mon Jul  2 17:24:45 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 2 Jul 2007 09:24:45 -0600
Subject: [LinuxBIOS] r2731 - trunk/LinuxBIOSv2/util
In-Reply-To: <20070701223451.GA8409@coresystems.de>
References: <20070701215734.22994.qmail@stuge.se>
	<20070701223451.GA8409@coresystems.de>
Message-ID: <20070702152445.GC11224@cosmic.amd.com>

On 02/07/07 00:34 +0200, Stefan Reinauer wrote:
> * Peter Stuge <peter at stuge.se> [070701 23:57]:
> > On Sun, Jul 01, 2007 at 09:47:31PM +0200, svn at openbios.org wrote:
> > > Name: svn:externals
> > >    + flashrom svn://linuxbios.org/repos/trunk/util/flashrom
> > 
> > Do we want a completely new repo for utils?
> 
> Yes we do.

I would like to see LAR in there too - it would be very handy to be able
to build LAR without the whole LBv3 tree, especially for buildrom (/me
laughs evilly).

Jordan





From jordan.crouse at amd.com  Mon Jul  2 17:28:21 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 2 Jul 2007 09:28:21 -0600
Subject: [LinuxBIOS] v3 - put lar size in the bootblock
In-Reply-To: <8df5675b4582f5c80acb95aaba030239@kernel.crashing.org>
References: <20070630215814.GB31719@coresystems.de>
	<20070630221141.GD5201@greenwood>
	<20070630224905.GB25735@coresystems.de>
	<8df5675b4582f5c80acb95aaba030239@kernel.crashing.org>
Message-ID: <20070702152821.GD11224@cosmic.amd.com>

On 01/07/07 21:12 +0200, Segher Boessenkool wrote:
> >> OK, I guess, but not all systems might have strcasecmp (I think it's
> >> called stricmp() on some). Not critical right now, though...
> >
> > ieks. good point. Which are those again?
> 
> Non-POSIX systems.  Do we care?

No.

Jordan

-- 
Jordan Crouse
Senior Linux Engineer
Advanced Micro Devices, Inc.
<www.amd.com/embeddedprocessors>





From rminnich at gmail.com  Mon Jul  2 18:08:31 2007
From: rminnich at gmail.com (ron minnich)
Date: Mon, 2 Jul 2007 09:08:31 -0700
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
In-Reply-To: <20070701225004.GC8409@coresystems.de>
References: <20070630224604.GA25735@coresystems.de>
	<20070630225743.GG5201@greenwood>
	<20070630230154.GA1147@coresystems.de>
	<20070701001402.GI5201@greenwood>
	<20070701225004.GC8409@coresystems.de>
Message-ID: <13426df10707020908y75020ebdq29f942844b02404f@mail.gmail.com>

change spinlock_define to spinlock_declare?

ron



From peter at stuge.se  Mon Jul  2 21:37:03 2007
From: peter at stuge.se (Peter Stuge)
Date: Mon, 2 Jul 2007 21:37:03 +0200
Subject: [LinuxBIOS] Winflashrom -- Current Status
In-Reply-To: <4688C2BF.2040600@gmail.com>
References: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>
	<4688C2BF.2040600@gmail.com>
Message-ID: <20070702193703.21913.qmail@stuge.se>

Hi,

On Mon, Jul 02, 2007 at 04:17:51PM +0700, Darmawan Salihun wrote:
> The diff for the latest winflashrom code is attached.

The diff is reversed, so a bit hard to read. Please do svn diff
-r1:HEAD next time.

Also, instead of commenting out non-Windows code and adding new
Windows-only code, please suggest good ways to abstract the code.


> There are still a few issues with this code.
> 
> 1. I've tested it on ICH-5 board. However, the BIOS binary that it
> reads from it is 514KB. It should be only 512KB.
> I'm still trying to find out the bug. Any info from ICH-x code
> maintainer?

This is probably because Win32 does LF->CR+LF translation when the
fopen() mode is "r" or "w" - Win32 introduces "rb" and "wb" for
binary files.


> 2. The PCI library is still a "brute force" approach. But, it works
> so far. I'll remove it soon enough.

Please make this a high priority. Until this is fixed, the driver is
a bluescreen waiting to happen and we can't really responsibly ask
people to test it that way. :\


> More updates to come.

This is good stuff!


On another note, is it possible to load the driver directly from a
resource without writing it out to a file first?


//Peter



From uwe at hermann-uwe.de  Mon Jul  2 21:57:33 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 2 Jul 2007 21:57:33 +0200
Subject: [LinuxBIOS] OLS audio/video/slides?
In-Reply-To: <20070702145931.GC10819@cosmic.amd.com>
References: <4682B253.3020909@georgi-clan.de>
	<20070629185641.GA29163@coresystems.de>
	<20070630141830.GC10622@greenwood>
	<20070702145931.GC10819@cosmic.amd.com>
Message-ID: <20070702195733.GA8232@greenwood>

On Mon, Jul 02, 2007 at 08:59:31AM -0600, Jordan Crouse wrote:
> On 30/06/07 16:18 +0200, Uwe Hermann wrote:
> > On Fri, Jun 29, 2007 at 08:56:41PM +0200, Stefan Reinauer wrote:
> > > Jordan's talk here at the OLS described how LinuxBIOS relocates itself
> > > from the very low space to TOM during the boot process.
> > 
> > Are there slides, audio recordings or video recordings available?
> 
> Slides will be forthcoming when I finish navigating the shark filled
> waters of our web site.  Audio and video recordings will eventually be made
> available on linuxsymposium.org as soon as they figure out how much it will
> cost to produce them.
> 
> Also, the paper itself (which is more detailed then the presentation), is
> here:  
> 
> https://ols2006.108.redhat.com/2007/Reprints/crouse-Reprint.pdf

Great, thanks, added to the wiki.

 
Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Mon Jul  2 22:57:45 2007
From: svn at openbios.org (svn at openbios.org)
Date: Mon,  2 Jul 2007 22:57:45 +0200
Subject: [LinuxBIOS] r430 - LinuxBIOSv3/util/lar
Message-ID: <mailman.495.1355071129.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-02 22:57:45 +0200 (Mon, 02 Jul 2007)
New Revision: 430

Modified:
   LinuxBIOSv3/util/lar/bootblock.c
   LinuxBIOSv3/util/lar/create.c
   LinuxBIOSv3/util/lar/extract.c
Log:
Coding style fixes via 'indent' (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/util/lar/bootblock.c
===================================================================
--- LinuxBIOSv3/util/lar/bootblock.c	2007-06-30 22:55:10 UTC (rev 429)
+++ LinuxBIOSv3/util/lar/bootblock.c	2007-07-02 20:57:45 UTC (rev 430)
@@ -48,11 +48,11 @@
 	 */
 	if (bootblock_len != BOOTBLOCK_SIZE) {
 		printf("Warning: %s does not seem to be a bootblock, "
-				"so ignore it\n", bootblock);
-		bootblock_code=NULL;
-		bootblock_len=0;
+		       "so ignore it\n", bootblock);
+		bootblock_code = NULL;
+		bootblock_len = 0;
 		// Is this an error condition?
-	}	
+	}
 
 	bootblock_code = malloc(bootblock_len);
 	if (!bootblock_code) {
@@ -78,13 +78,12 @@
 	uint32_t *size_pos;
 
 	/* This cleans out the area after the reset vector */
-	for(i=13; i>0; i--)
+	for (i = 13; i > 0; i--)
 		bootblock_code[bootblock_len - i] = '\0';
-	
+
 	/* add lar size to image */
-	size_pos=(uint32_t *)(bootblock_code+bootblock_len-12);
+	size_pos = (uint32_t *) (bootblock_code + bootblock_len - 12);
 	size_pos[0] = get_larsize();
 
 	return 0;
 }
-

Modified: LinuxBIOSv3/util/lar/create.c
===================================================================
--- LinuxBIOSv3/util/lar/create.c	2007-06-30 22:55:10 UTC (rev 429)
+++ LinuxBIOSv3/util/lar/create.c	2007-07-02 20:57:45 UTC (rev 430)
@@ -36,13 +36,15 @@
 
 extern enum compalgo algo;
 
-void compress_impossible(char *in, u32 in_len, char *out, u32 *out_len) {
+void compress_impossible(char *in, u32 in_len, char *out, u32 *out_len)
+{
 	fprintf(stderr,
 		"The selected compression algorithm wasn't compiled in.\n");
 	exit(1);
 }
 
-void do_no_compress(char *in, u32 in_len, char *out, u32 *out_len) {
+void do_no_compress(char *in, u32 in_len, char *out, u32 *out_len)
+{
 	memcpy(out, in, in_len);
 	out_len[0] = in_len;
 }
@@ -116,7 +118,7 @@
 		header = (struct lar_header *)tempmem;
 		pathname = tempmem + sizeof(struct lar_header);
 		pathlen = snprintf(pathname, MAX_PATHLEN - 1, name) + 1;
-		pathlen = (pathlen + 15) & 0xfffffff0;/* Align to 16 bytes. */
+		pathlen = (pathlen + 15) & 0xfffffff0;	/* Align to 16 bytes. */
 
 		/* Read file into memory. */
 		filebuf = malloc(filelen);
@@ -184,15 +186,17 @@
 
 	if (bootblock_len) {
 		if (verbose())
-			printf ("Detected bootblock of %d bytes\n", bootblock_len);
+			printf("Detected bootblock of %d bytes\n",
+			       bootblock_len);
 
 		bb_header_len = sizeof(struct lar_header) +
-			((strlen(basename(get_bootblock()))+15) & 0xfffffff0);
+		    ((strlen(basename(get_bootblock())) + 15) & 0xfffffff0);
 
 		bb_header_len = (bb_header_len + 15) & 0xfffffff0;
 
 		if (verbose())
-			printf ("Required bootblock header of %d bytes\n", bb_header_len);
+			printf("Required bootblock header of %d bytes\n",
+			       bb_header_len);
 
 		diff -= bootblock_len;
 		diff -= bb_header_len;
@@ -239,15 +243,15 @@
 		struct lar_header *bb;
 
 		bootblock_header = malloc(bb_header_len);
-		if(!bootblock_header) {
+		if (!bootblock_header) {
 			fprintf(stderr, "Out of memory.\n");
 			exit(1);
 		}
 
-		memset (bootblock_header, 0, bb_header_len);
+		memset(bootblock_header, 0, bb_header_len);
 
 		/* construct header */
-		bb=(struct lar_header *)bootblock_header;
+		bb = (struct lar_header *)bootblock_header;
 		memcpy(bb->magic, MAGIC, 8);
 		bb->reallen = htonl(bootblock_len);
 		bb->len = htonl(bootblock_len);
@@ -258,8 +262,8 @@
 		/* Write filename. we calculated the buffer size, 
 		 * so no overflow danger here.
 		 */
-		strcpy(bootblock_header+sizeof(struct lar_header), 
-				basename(get_bootblock()) );
+		strcpy(bootblock_header + sizeof(struct lar_header),
+		       basename(get_bootblock()));
 
 		fwrite(bootblock_header, bb_header_len, 1, archive);
 		fwrite(bootblock_code, bootblock_len, 1, archive);

Modified: LinuxBIOSv3/util/lar/extract.c
===================================================================
--- LinuxBIOSv3/util/lar/extract.c	2007-06-30 22:55:10 UTC (rev 429)
+++ LinuxBIOSv3/util/lar/extract.c	2007-07-02 20:57:45 UTC (rev 430)
@@ -33,13 +33,15 @@
 #include "lib.h"
 #include "lar.h"
 
-void uncompress_impossible(char *dst, char *src, u32 len) {
+void uncompress_impossible(char *dst, char *src, u32 len)
+{
 	fprintf(stderr,
 		"Cannot uncompress data (algorithm not compiled in).\n");
 	exit(1);
 }
 
-void do_no_uncompress(char *dst, char *src, u32 len) {
+void do_no_uncompress(char *dst, char *src, u32 len)
+{
 	memcpy(dst, src, len);
 }
 
@@ -117,7 +119,7 @@
 		if (pos) {
 			pos[1] = 0;
 			/* printf("Pathname %s\n",pathname); */
-			mkdirp(pathname,0755);
+			mkdirp(pathname, 0755);
 		}
 		free(pathname);
 
@@ -133,8 +135,7 @@
 		} else {
 			char *buf = malloc(ntohl(header->reallen));
 			uncompress_functions[ntohl(header->compression)](buf,
-				walk + ntohl(header->offset),
-				ntohl(header->len));
+			   walk + ntohl(header->offset), ntohl(header->len));
 			fwrite(buf, ntohl(header->reallen), 1, file_to_extract);
 			free(buf);
 		}




From uwe at hermann-uwe.de  Tue Jul  3 01:26:11 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 3 Jul 2007 01:26:11 +0200
Subject: [LinuxBIOS] [PATCH] v3 - put lar size in the bootblock
In-Reply-To: <20070630224905.GB25735@coresystems.de>
References: <20070630215814.GB31719@coresystems.de>
	<20070630221141.GD5201@greenwood>
	<20070630224905.GB25735@coresystems.de>
Message-ID: <20070702232611.GC8232@greenwood>

On Sun, Jul 01, 2007 at 12:49:05AM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070701 00:11]:
> > > +       int i;
> > > +       uint32_t *size_pos;
> > 
> > u32
>  
> No, this is userspace. We don't have u32 here.

You mean in lar in general? We _do_ use u32 in lar code already, so
maybe that needs fixing?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Jul  3 01:28:14 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 3 Jul 2007 01:28:14 +0200
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <20070701223832.GB8409@coresystems.de>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
	<20070701000736.GH5201@greenwood>
	<13426df10706302048v330c243qf15befd1daba6371@mail.gmail.com>
	<20070701223832.GB8409@coresystems.de>
Message-ID: <20070702232814.GD8232@greenwood>

On Mon, Jul 02, 2007 at 12:38:32AM +0200, Stefan Reinauer wrote:
> * ron minnich <rminnich at gmail.com> [070701 05:48]:
> > > then? That has the benefit that you don't have to know what the default
> > > is (enabled or disabled), you know everything you need just by looking
> > > at the dts itself.
> > 
> > yeah, that works. I will take the magic enabled out of the .y, and
> > will require that people set that property for each node; I will catch
> > a missing set at flatten tree time. I think that is reasonable.
>  
> Please dont do that. I think it is reasonable to assume that a device
> that you specify is enabled. Otherwise why would you specify it? 
> 
> I dont like overspecifying completely obvious things in description files.

Yeah, I think you're right.

So we have two options:

 1. disable="1"
 2. enable="0"

for devices which should be disabled. I think option 1 is a bit
clearer. Thoughts?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Jul  3 01:32:36 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 3 Jul 2007 01:32:36 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070701180057.GA24639@skynet.be>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
Message-ID: <20070702233236.GE8232@greenwood>

On Sun, Jul 01, 2007 at 08:00:57PM +0200, Luc Verhaegen wrote:
> I fully agree with the earlier stuff, but is there any reason to keep
> this in the v3 tree? People will not be that unhappy if they're required 
> to pull in the flashrom utility seperately,

I fully agree, it's not required. Some developers have expressed in the
past that they like to keep all our code together in one 'svn co' bunch.

I don't have a strong opinion either way (as long as we don't have
_forks_ of code for v1 and v2, which is why we now use svn:externals).


> and i'm not sure, but i 
> think that in some cases, the likes of uniflash can be used to flash a 
> linuxbios too.

Definately, not everyone needs flashrom.


> I personally don't think there should be a place in the v3 tree for a 
> utility like this, as it leads an almost completely independent life.

Yes, and it should. The copy in v2/v3 is merely there for convenience.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From jordan.crouse at amd.com  Tue Jul  3 01:38:43 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 2 Jul 2007 17:38:43 -0600
Subject: [LinuxBIOS] [PATCH][v3] Add automagic detection for
	-fno-stack-protector
Message-ID: <20070702233843.GG14253@cosmic.amd.com>

Yay!  You have no idea how happy I am to push this patch up.
No more -fno-stack-protector hacks (at least for v3).  

Jordan
-------------- next part --------------
[PATCH][v3] Add automatic detection for -fno-stack-protector

This borrows the cc-option call from the kernel to check if
-fno-stack-protector is supported by the compiler, and if it is,
then enable it.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>

Index: LinuxBIOSv3/Makefile
===================================================================
--- LinuxBIOSv3.orig/Makefile	2007-07-02 17:21:19.000000000 -0600
+++ LinuxBIOSv3/Makefile	2007-07-02 17:26:32.000000000 -0600
@@ -32,6 +32,19 @@
 obj := $(shell pwd)/build
 export src obj
 
+# These functions are called by the kernel - we use these below
+# to check for -fno-stack-protector
+
+try-run= $(shell set -e; \
+	TMP=".$$$$.tmp"; \
+	if ($(1)) > /dev/null 2>&1; \
+	then echo "$(2)"; \
+	else echo "$(3)"; \
+	fi; rm -rf "$$TMP")
+
+cc-option=$(call try-run,\
+	$(CC) $(1) -S -xc /dev/null -o "$$TMP", $(1), $(2))
+
 # Do not print "Entering directory ...".
 MAKEFLAGS += --no-print-directory
 
@@ -42,6 +55,11 @@
 	      -mpreferred-stack-boundary=2 -mregparm=3 -pipe
 # FIXME: Does stack boundary or regparm break the code on real hardware?
 
+# Add in automagic detection for -fno-stack-protector
+# This is borrowed from the kernel 2.6 scripts
+
+CFLAGS += $(call cc-option, -fno-stack-protector,)
+
 HOSTCC     := gcc
 HOSTCXX    := g++
 HOSTCFLAGS := -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \

From uwe at hermann-uwe.de  Tue Jul  3 01:39:06 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 3 Jul 2007 01:39:06 +0200
Subject: [LinuxBIOS] [PATCH] v3 - spinlock cleanup
In-Reply-To: <20070701225004.GC8409@coresystems.de>
References: <20070630224604.GA25735@coresystems.de>
	<20070630225743.GG5201@greenwood>
	<20070630230154.GA1147@coresystems.de>
	<20070701001402.GI5201@greenwood>
	<20070701225004.GC8409@coresystems.de>
Message-ID: <20070702233906.GF8232@greenwood>

On Mon, Jul 02, 2007 at 12:50:04AM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070701 02:14]:
> > OK, I totally misread what the code is supposed to do.
> > 
> > I'm not sure the spin_define() is such a good idea then. It has a nice
> > name and all, but it might be obfuscating things more than necessary.
> > Maybe a simple variable declaration (i.e., drop the #define) would be better?
> 
> I don't see why it would be better, there are no obvious advantages, but
> some obvious disadvantages.
> Here our principles start clashing. We can't do this for several
> reasons:
> 
> * The declaration is static, so it has to be surrounded by #if
>   defined(CONFIG_SMP) would waste all the places in the code. This is 
>   controverse to our goal to make changes as local as possible.
>   If we don't, we end up with warnings in the code for almost every
>   board
> 
> * Since some of us started hating typedefs, we don't have anything to
>   declare anymore. You simply can not rely that a spinlock is
>   represented by struct spinlock on all possible systems.
>   So to get this done right, we would have to go back to spinlock_t,
>   in which case I would vote to also go back to device_t and all the
>   others, so we stay consistent.

Hm, ok forget what I said.

I think we should go back to using spinlock_t (but not device_t!).

As far as I remember the problem with device_t was that it was not
just a typedef for a struct, but a typedef for a _pointer_to_a_struct_.

That causes many nasty possibilities for bugs to creep in when you
see foo_t and think it's an int or struct where in reality it is
actually a _pointer_ to something.

So I think we should revert back to spinlock_t and use the macro, too.


Sorry for the confusion. Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Jul  3 01:41:00 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 3 Jul 2007 01:41:00 +0200
Subject: [LinuxBIOS] r413 - in LinuxBIOSv3: arch/x86
	include	mainboard/artecgroup/dbe61
	southbridge/amd/cs5536	superio/winbond/w83627hf
In-Reply-To: <20070630221138.20350.qmail@stuge.se>
References: <20070630221138.20350.qmail@stuge.se>
Message-ID: <20070702234100.GG8232@greenwood>

On Sun, Jul 01, 2007 at 12:11:38AM +0200, Peter Stuge wrote:
> On Fri, Jun 29, 2007 at 04:36:03PM +0200, svn at openbios.org wrote:
> > +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
> 
> Need extra () around a or no?
> 
> sizeof((a)) / sizeof(((a))[0])) ?

Hm, good question. I guess not, I've seen many projects use this macro
without that many braces, but maybe they're all wrong ;-)

As long as 'a' is a simple array all should be fine, I guess. Using
ARRAY_SIZE on something other than an array is probably a bug anyway.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From jordan.crouse at amd.com  Tue Jul  3 01:47:05 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 2 Jul 2007 17:47:05 -0600
Subject: [LinuxBIOS] Add automagic detection for -fno-stack-protector
In-Reply-To: <20070702233843.GG14253@cosmic.amd.com>
References: <20070702233843.GG14253@cosmic.amd.com>
Message-ID: <20070702234705.GH14253@cosmic.amd.com>

On 02/07/07 17:38 -0600, Jordan Crouse wrote:
> Yay!  You have no idea how happy I am to push this patch up.
> No more -fno-stack-protector hacks (at least for v3).  
> 
> Jordan

Hmm - whoever checks this in, please change "called by the kernel" to
"from the kernel" in the first blob.   The way it reads now is stupid. :)

Jordan
-- 
Jordan Crouse
Senior Linux Engineer
Advanced Micro Devices, Inc.
<www.amd.com/embeddedprocessors>





From uwe at hermann-uwe.de  Tue Jul  3 01:43:07 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 3 Jul 2007 01:43:07 +0200
Subject: [LinuxBIOS] [PATCH][v3] small fix for nrv2b
In-Reply-To: <4682B285.5020300@georgi-clan.de>
References: <4682B285.5020300@georgi-clan.de>
Message-ID: <20070702234307.GH8232@greenwood>

On Wed, Jun 27, 2007 at 08:55:01PM +0200, Patrick Georgi wrote:
> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

r419.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Jul  3 01:48:36 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 3 Jul 2007 01:48:36 +0200
Subject: [LinuxBIOS] GA-M57SLI
In-Reply-To: <20070627194413.GA19628@coresystems.de>
References: <37367b3a0706251451n7b012fd9n4bedcdd977c89092@mail.gmail.com>
	<46824015.4000206@lotuspond.ca>
	<2ea3fae10706270958o6bdd96fbwa5ff00cae7431371@mail.gmail.com>
	<20070627173753.GA18911@coresystems.de>
	<2ea3fae10706271240r6398d02aq16ee12983e6a9b97@mail.gmail.com>
	<20070627194413.GA19628@coresystems.de>
Message-ID: <20070702234836.GI8232@greenwood>

On Wed, Jun 27, 2007 at 09:44:13PM +0200, Stefan Reinauer wrote:
> * yhlu <yinghailu at gmail.com> [070627 21:40]:
> > > Why is that? Multiboot?
> > >
> > > Can we go the other way round? LinuxBIOS+Xen+DOM0 in the kernel?
> > 
> >  Mulitboot.
>  
> Ok. Grub2 will solve that.
> 
> >  more guys is using SATA disk instead ot PATA ide.
>  
> This should not be an issue if we manage to fit Xen and DOM0 into the
> flash chip.

Anyone willing to try? :) I guess it should be possible with a large
enough chip. It's probably best to try to cook up something for QEMU
first...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From marc.jones at amd.com  Tue Jul  3 01:55:12 2007
From: marc.jones at amd.com (Marc Jones)
Date: Mon, 02 Jul 2007 17:55:12 -0600
Subject: [LinuxBIOS] [PATCH] geode_v3_cleanup.patch - Re: r387 - in
 LinuxBIOSv3/arch/x86: . geodelx
In-Reply-To: <20070627233154.16037.qmail@stuge.se>
References: <20070627233154.16037.qmail@stuge.se>
Message-ID: <46899060.8060500@amd.com>

This patch fixes a number of comments and other issues raised by Peter. 
More comments inline.



Peter Stuge wrote:
> On Wed, Jun 27, 2007 at 11:07:10PM +0200, svn at openbios.org wrote:
>> +++ LinuxBIOSv3/arch/x86/Makefile	2007-06-27 21:07:10 UTC (rev 387)
> ..
> 
> 
>> +$(obj)/arch/x86/geodelx/stage0.o: $(src)/arch/x86/geodelx/stage0.S
>> +	$(Q)mkdir -p $(obj)/arch/x86/geodelx
> 
> Uh? The rule depends on a file in a directory created in the rule?
> 
> 
>> +	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
>> +	$(Q)$(CC) -E $(LINUXBIOSINCLUDE) $< \
>> +		-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
>> +		-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
> 
> Maybe even the svn rev date?
> 
> 
>> +	/* Setup access to the cache for under 640K. Note MC not setup yet. */
>> +	msr.hi = 0x20000000;
>> +	msr.lo = 0xfff80;
>> +	wrmsr(MSR_GLIU0 + 0x20, msr);
>> +
>> +	msr.hi = 0x20000000;
>> +	msr.lo = 0x80fffe0;
>> +	wrmsr(MSR_GLIU0 + 0x21, msr);
>> +
>> +	msr.hi = 0x20000000;
>> +	msr.lo = 0xfff80;
>> +	wrmsr(MSR_GLIU1 + 0x20, msr);
>> +
>> +	msr.hi = 0x20000000;
>> +	msr.lo = 0x80fffe0;
>> +	wrmsr(MSR_GLIU1 + 0x21, msr);
> 
> No nice #defines around for these?
> 
>
added defines for the MSRs and comments for the values.

> 
>> +/** 
>> +  * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure
>> +  * out what these values mean.
>> +  */
>> +void start_timer1(void)
>> +{
>> +	outb(0x56, 0x43);
>> +	outb(0x12, 0x41);
>> +}
> 
> 0x43 is PIT command/control.
> 0x41 is PIT counter 1.
> 
> 0x56 means write counter 1 lower 8 bits in next IO, set the counter
> mode to square wave generator (count down to 0 from programmed value
> twice in a row, alternating the output signal) counting in 16-bit
> binary mode.
> 
> 0x12 is written to the counter.
> 
> Used for RAM refresh on XT/AT but the port 61 reference indicates it
> has to do with the (emulated?) keyboard controller.
> 
> 
> 
Good summary. Added to the function header with slight modifications.

>> +	msr_t msrGlcpSysRstpll;
> 
> This guy could use a better name. At least no caps.
> 
> 
changed to msr_glcp_sys_pll

>> +			msrGlcpSysRstpll.lo &=
>> +			    ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
>> +			msrGlcpSysRstpll.lo |=
>> +			    (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
> 
> Why 0xDE ?
> 
>
Added comment - because AMD recommends setting based on stability testing


>> +		/*      You should never get here..... The chip has reset. */
>> +		printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
>> +		post_code(POST_PLL_RESET_FAIL);
>> +		__asm__ __volatile__("hlt\n");
> 
> How about that hlt() function? Remember we want to put panic room
> code there when we have too much spare time.
> 
> 
I didn't change this. There was still some question about hlt() on the 
list.

>> +/**
>> + * Return the CPU clock rate. Rates in this system are always returned
>> + * as multkiples of 33 Mhz.
>> + *
>> + */
>> +u32 cpu_speed(void)
> 
> Is there a doxygen syntax for the return value? Also please say which
> unit the value is in. MHz?
> 
>

done (I hope, I'm not doxygen guy)

>> +/**
>> + * Return the Geode Link clock rate.  Rates in this system are always
>> + * returned as multkiples of 33 Mhz.
>> + *
>> + */
>> +u32 geode_link_speed(void)
> 
> Ditto.
> 
> 
ditto

>> +	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
>> +	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
> 
> Maybe that 0x1F is a #define?
> 
>
done


>> +/**
>> + * Return the PCI bus clock rate.  Rates in this system are always
>> + * returned as multkiples of 33 Mhz.
>> + *
>> + */
>> +u32 pci_speed(void)
> 
> Doxygen return value comment here too?
> 
>
yup

>> +	msrnum = GLCP_DELAY_CONTROLS;
>> +	msr = rdmsr(msrnum);
>> +	if (msr.lo & ~(0x7C0)) {
>> +		return;
>> +	}
> 
> The juju must stay but 0x7c0 seems like a #define?
> 
> 
yup

>> +	if (spdbyte0 == 0 || spdbyte1 == 0) {
>> +		/* one dimm solution */
>> +		if (spdbyte1 == 0) {
>> +			msr.hi |= 0x000800000;
>> +		}
>> +		spdbyte0 += spdbyte1;
>> +		if (spdbyte0 > 8) {
>> +			/* large dimm */
>> +			if (glspeed < 334) {
>> +				msr.hi |= 0x0837100AA;
>> +				msr.lo |= 0x056960004;
>> +			} else {
>> +				msr.hi |= 0x082710055;
>> +				msr.lo |= 0x056960004;
>> +			}
>> +		} else if (spdbyte0 > 4) {
>> +			/* medium dimm */
>> +			if (glspeed < 334) {
>> +				msr.hi |= 0x0837100AA;
>> +				msr.lo |= 0x056960004;
>> +			} else {
>> +				msr.hi |= 0x0827100AA;
>> +				msr.lo |= 0x056960004;
>> +			}
>> +		} else {
>> +			/* small dimm */
>> +			if (glspeed < 334) {
>> +				msr.hi |= 0x0837100FF;
>> +				msr.lo |= 0x056960004;
>> +			} else {
>> +				msr.hi |= 0x0827100FF;
>> +				msr.lo |= 0x056960004;
>> +			}
>> +		}
>> +	} else {
>> +		/* two dimm solution */
>> +		spdbyte0 += spdbyte1;
>> +		if (spdbyte0 > 24) {
>> +			/* huge dimms */
>> +			if (glspeed < 334) {
>> +				msr.hi |= 0x0B37100A5;
>> +				msr.lo |= 0x056960004;
>> +			} else {
>> +				msr.hi |= 0x0B2710000;
>> +				msr.lo |= 0x056960004;
>> +			}
>> +		} else if (spdbyte0 > 16) {
>> +			/* large dimms */
>> +			if (glspeed < 334) {
>> +				msr.hi |= 0x0B37100A5;
>> +				msr.lo |= 0x056960004;
>> +			} else {
>> +				msr.hi |= 0x0B27100A5;
>> +				msr.lo |= 0x056960004;
>> +			}
>> +		} else if (spdbyte0 >= 8) {
>> +			/* medium dimms */
>> +			if (glspeed < 334) {
>> +				msr.hi |= 0x0937100A5;
>> +				msr.lo |= 0x056960004;
>> +			} else {
>> +				msr.hi |= 0x0C27100A5;
>> +				msr.lo |= 0x056960004;
>> +			}
>> +		} else {
>> +			/* small dimms */
>> +			if (glspeed < 334) {
>> +				msr.hi |= 0x0837100A5;
>> +				msr.lo |= 0x056960004;
>> +			} else {
>> +				msr.hi |= 0x082710000;
>> +				msr.lo |= 0x056960004;
>> +			}
>> +		}
> 
> Each if statements just changes a few bits. Couldn't this be made
> more readable?
> 
>

seemed like it was enough code change that this would get it's own patch 
. I think I can get this done tomorrow

>> +DCacheSetupBad:
>> +	hlt		/* Issues */
>> +	jmp DCacheSetupBad
> 
> Hehe, yes, we have issues. Should we aim for panic room code in
> assembly?
> 
> 
>> +lout:
>> +	/* Restore the BIST result. */
>> +	movl	%ebp, %eax
>> +	/* We need to set ebp? No need. */
>> +	movl	%esp, %ebp
>> +	pushl	%eax		/* BIST */
>> +	call	stage1_main
>> +	/* We will not go back. */
> 
> I remember commenting on this before; please handle a return or
> change it to a jmp. (I like the latter.)
> 
>
fixed in a prior patch

>> +fixed_mtrr_msr:
>> +	.long   0x250, 0x258, 0x259
>> +	.long   0x268, 0x269, 0x26A
>> +	.long   0x26B, 0x26C, 0x26D
>> +	.long   0x26E, 0x26F
>> +var_mtrr_msr:
>> +	.long   0x200, 0x201, 0x202, 0x203
>> +	.long   0x204, 0x205, 0x206, 0x207
> 
> ..or this would be executed on return..
> 
> 
> //Peter
> 

Marc

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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From stepan at coresystems.de  Tue Jul  3 05:01:43 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 3 Jul 2007 05:01:43 +0200
Subject: [LinuxBIOS] [PATCH][v3] Add automagic detection
	for	-fno-stack-protector
In-Reply-To: <20070702233843.GG14253@cosmic.amd.com>
References: <20070702233843.GG14253@cosmic.amd.com>
Message-ID: <20070703030143.GB22459@coresystems.de>

* Jordan Crouse <jordan.crouse at amd.com> [070703 01:38]:
> Yay!  You have no idea how happy I am to push this patch up.
> No more -fno-stack-protector hacks (at least for v3).  
> 
> Jordan

Hi Jordan,

is there some way we can include this in util/xcompile/xcompile
instead?

That script was meant to be an abstraction for stuff like this at some
point.

Comments/flames/ideas of course welcome!

> [PATCH][v3] Add automatic detection for -fno-stack-protector
> 
> This borrows the cc-option call from the kernel to check if
> -fno-stack-protector is supported by the compiler, and if it is,
> then enable it.
> 
> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
> 
> Index: LinuxBIOSv3/Makefile
> ===================================================================
> --- LinuxBIOSv3.orig/Makefile	2007-07-02 17:21:19.000000000 -0600
> +++ LinuxBIOSv3/Makefile	2007-07-02 17:26:32.000000000 -0600
> @@ -32,6 +32,19 @@
>  obj := $(shell pwd)/build
>  export src obj
>  
> +# These functions are called by the kernel - we use these below
> +# to check for -fno-stack-protector
> +
> +try-run= $(shell set -e; \
> +	TMP=".$$$$.tmp"; \
> +	if ($(1)) > /dev/null 2>&1; \
> +	then echo "$(2)"; \
> +	else echo "$(3)"; \
> +	fi; rm -rf "$$TMP")
> +
> +cc-option=$(call try-run,\
> +	$(CC) $(1) -S -xc /dev/null -o "$$TMP", $(1), $(2))
> +
>  # Do not print "Entering directory ...".
>  MAKEFLAGS += --no-print-directory
>  
> @@ -42,6 +55,11 @@
>  	      -mpreferred-stack-boundary=2 -mregparm=3 -pipe
>  # FIXME: Does stack boundary or regparm break the code on real hardware?
>  
> +# Add in automagic detection for -fno-stack-protector
> +# This is borrowed from the kernel 2.6 scripts
> +
> +CFLAGS += $(call cc-option, -fno-stack-protector,)
> +
>  HOSTCC     := gcc
>  HOSTCXX    := g++
>  HOSTCFLAGS := -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \

> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From corey.osgood at gmail.com  Tue Jul  3 05:18:53 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Mon, 02 Jul 2007 23:18:53 -0400
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <20070702232814.GD8232@greenwood>
References: <20070630193805.GN10622@greenwood>	<20070630214319.GA31719@coresystems.de>	<20070630232022.466.qmail@stuge.se>	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>	<20070701000736.GH5201@greenwood>	<13426df10706302048v330c243qf15befd1daba6371@mail.gmail.com>	<20070701223832.GB8409@coresystems.de>
	<20070702232814.GD8232@greenwood>
Message-ID: <4689C01D.7090309@gmail.com>

Uwe Hermann wrote:
> On Mon, Jul 02, 2007 at 12:38:32AM +0200, Stefan Reinauer wrote:
>   
>> * ron minnich <rminnich at gmail.com> [070701 05:48]:
>>     
>>>> then? That has the benefit that you don't have to know what the default
>>>> is (enabled or disabled), you know everything you need just by looking
>>>> at the dts itself.
>>>>         
>>> yeah, that works. I will take the magic enabled out of the .y, and
>>> will require that people set that property for each node; I will catch
>>> a missing set at flatten tree time. I think that is reasonable.
>>>       
>>  
>> Please dont do that. I think it is reasonable to assume that a device
>> that you specify is enabled. Otherwise why would you specify it? 
>>
>> I dont like overspecifying completely obvious things in description files.
>>     
>
> Yeah, I think you're right.
>
> So we have two options:
>
>  1. disable="1"
>  2. enable="0"
>
> for devices which should be disabled. I think option 1 is a bit
> clearer. Thoughts?
>
>
> Uwe.
>   
Agreed. Default to hardware enabled unless explicitly disabled, and
clearly state that somewhere, seems the best route to me.

-Corey



From darmawan.salihun at gmail.com  Tue Jul  3 07:48:48 2007
From: darmawan.salihun at gmail.com (Darmawan Salihun)
Date: Tue, 03 Jul 2007 12:48:48 +0700
Subject: [LinuxBIOS] Winflashrom -- Current Status
In-Reply-To: <20070702193703.21913.qmail@stuge.se>
References: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>	<4688C2BF.2040600@gmail.com>
	<20070702193703.21913.qmail@stuge.se>
Message-ID: <4689E340.4080700@gmail.com>

Hi,
Peter Stuge wrote:
> Hi,
>
> On Mon, Jul 02, 2007 at 04:17:51PM +0700, Darmawan Salihun wrote:
>   
>> The diff for the latest winflashrom code is attached.
>>     
>
> The diff is reversed, so a bit hard to read. Please do svn diff
> -r1:HEAD next time.
>   
ok :)

> Also, instead of commenting out non-Windows code and adding new
> Windows-only code, please suggest good ways to abstract the code.
>
>   
Basically, I'm in the process of designing the abstraction right now
;-). I'll post it when I'm done.
Nonetheless, I need a "working" code as a comparison to know the details
of the "incompatible" parts
between the windows version and the *NIX version.

>> There are still a few issues with this code.
>>
>> 1. I've tested it on ICH-5 board. However, the BIOS binary that it
>> reads from it is 514KB. It should be only 512KB.
>> I'm still trying to find out the bug. Any info from ICH-x code
>> maintainer?
>>     
>
> This is probably because Win32 does LF->CR+LF translation when the
> fopen() mode is "r" or "w" - Win32 introduces "rb" and "wb" for
> binary files.
>   
aha.., I see. I forgot about it :-/. I've fixed such a bug when porting
flashrom version 1.23 back then ;-).
Thanks for the hint.

>> 2. The PCI library is still a "brute force" approach. But, it works
>> so far. I'll remove it soon enough.
>>     
>
> Please make this a high priority. Until this is fixed, the driver is
> a bluescreen waiting to happen and we can't really responsibly ask
> people to test it that way. :\
>   
yes, it's on the top priority list right now.

>   
>> More updates to come.
>>     
>
> This is good stuff!
>
>
> On another note, is it possible to load the driver directly from a
> resource without writing it out to a file first?
>   
I don't know that for sure. But, I'll try to find out. Maybe using
memory-mapped file would allow us to
do such a thing.

Anyway, I'll be off for about 4-5 days. So, updates will come only by
next week.

Cheers,
Darmawan





From joe at smittys.pointclark.net  Tue Jul  3 11:17:14 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Tue, 03 Jul 2007 05:17:14 -0400
Subject: [LinuxBIOS] SDD byte 31
Message-ID: <20070703051714.bsv7t4e28ocw8s8s@www.smittys.pointclark.net>

Hello,
Corey or Uwe, maybe you can help me. Where did you get the SDD byte 31  
values? Is there a chart somewhere? Can you point me in the right  
direction?

Thanks - Joe



From corey.osgood at gmail.com  Tue Jul  3 12:03:17 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Tue, 03 Jul 2007 06:03:17 -0400
Subject: [LinuxBIOS] SDD byte 31
In-Reply-To: <20070703051714.bsv7t4e28ocw8s8s@www.smittys.pointclark.net>
References: <20070703051714.bsv7t4e28ocw8s8s@www.smittys.pointclark.net>
Message-ID: <468A1EE5.3070101@gmail.com>

Joseph Smith wrote:
> Hello,
> Corey or Uwe, maybe you can help me. Where did you get the SDD byte 31
> values? Is there a chart somewhere? Can you point me in the right
> direction?
>
> Thanks - Joe
>
This is a good straighforward translation of the standard:
http://www.simmtester.com/page/news/showpubnews.asp?num=101

And, Intel's version is a pretty easy read as well:
http://www.intel.com/design/chipsets/memory/spdsd12a.pdf

The JEDEC version is the official one, but I hate trampling through
multiple pdfs to try and find one little bit of information, these are
much more concise. Both explain byte 31, and much of the standard is the
same between sdram/ddr/ddr2.

-corey



From libv at skynet.be  Tue Jul  3 13:55:04 2007
From: libv at skynet.be (Luc Verhaegen)
Date: Tue, 3 Jul 2007 13:55:04 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070702233236.GE8232@greenwood>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
Message-ID: <20070703115504.GA5627@skynet.be>

On Tue, Jul 03, 2007 at 01:32:36AM +0200, Uwe Hermann wrote:
> On Sun, Jul 01, 2007 at 08:00:57PM +0200, Luc Verhaegen wrote:
> > I fully agree with the earlier stuff, but is there any reason to keep
> > this in the v3 tree? People will not be that unhappy if they're required 
> > to pull in the flashrom utility seperately,
> 
> I fully agree, it's not required. Some developers have expressed in the
> past that they like to keep all our code together in one 'svn co' bunch.
> 
> I don't have a strong opinion either way (as long as we don't have
> _forks_ of code for v1 and v2, which is why we now use svn:externals).
> 
> 
> > and i'm not sure, but i 
> > think that in some cases, the likes of uniflash can be used to flash a 
> > linuxbios too.
> 
> Definately, not everyone needs flashrom.
> 
> 
> > I personally don't think there should be a place in the v3 tree for a 
> > utility like this, as it leads an almost completely independent life.
> 
> Yes, and it should. The copy in v2/v3 is merely there for convenience.
> 
> 
> Uwe.

I fully understand and support the v2 copy, but for v3 i don't see the 
point myself. Maybe other people have an opinion here.

Luc Verhaegen.



From dhbarr at gozelle.com  Tue Jul  3 14:20:10 2007
From: dhbarr at gozelle.com (David H. Barr)
Date: Tue, 3 Jul 2007 07:20:10 -0500
Subject: [LinuxBIOS] GA-M57SLI
In-Reply-To: <20070702234836.GI8232@greenwood>
References: <37367b3a0706251451n7b012fd9n4bedcdd977c89092@mail.gmail.com>
	<46824015.4000206@lotuspond.ca>
	<2ea3fae10706270958o6bdd96fbwa5ff00cae7431371@mail.gmail.com>
	<20070627173753.GA18911@coresystems.de>
	<2ea3fae10706271240r6398d02aq16ee12983e6a9b97@mail.gmail.com>
	<20070627194413.GA19628@coresystems.de>
	<20070702234836.GI8232@greenwood>
Message-ID: <e8d467740707030520m7dc6cf3u1fe25de6c290f6d@mail.gmail.com>

On 7/2/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Wed, Jun 27, 2007 at 09:44:13PM +0200, Stefan Reinauer wrote:
> > * yhlu <yinghailu at gmail.com> [070627 21:40]:
> > > > Why is that? Multiboot?
> > > >
> > > > Can we go the other way round? LinuxBIOS+Xen+DOM0 in the kernel?
> > >
> > >  Mulitboot.
> >
> > Ok. Grub2 will solve that.
> >
> > >  more guys is using SATA disk instead ot PATA ide.
> >
> > This should not be an issue if we manage to fit Xen and DOM0 into the
> > flash chip.
>
> Anyone willing to try? :) I guess it should be possible with a large
> enough chip.

I've been waiting for this.  Four-socket quad-core (16-way!) with Xen
in the Flash part sends chills up my spine.  A true virtualization
appliance!

-dhbarr.



From george at kami.ru  Tue Jul  3 19:46:12 2007
From: george at kami.ru (George V. Adamov)
Date: Tue, 03 Jul 2007 17:46:12 +0000
Subject: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n platinum)
	motherboard
Message-ID: <468A8B64.7030004@kami.ru>

Porting LinuxBios on MSI ms7250 motherbord
I have a problem - after memory initialization, it goes to soft reset...
So far have no idea why...


LinuxBIOS-2.0.0_Fallback Thu Jun 28 12:26:54 UTC 2007 starting...
core0 started:
SBLink=00
NC node|link=00
mcp55_num:01
Ram1.00
Ram2.00
Unbuffered
333Mhz
Interleaved
RAM: 0x00100000 KB
Ram3
Initializing memory:  done
Setting variable MTRR 02, base: 0000MB, range: 0400MB, type WB
DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=aeDQS 
Training:tsc[00]=000000000ee58519
DQS Training:tsc[01]=000ceea800001000
DQS Training:tsc[02]=000ceea48000c298
DQS Training:tsc[03]=000ceeb0ffff03da
DQS Training:tsc[04]=000000001065ffaf
Ram4
v_esp=000cefe4
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:


INIT detected from  ---- {APICID = 00 NODEID = 00 COREID = 00} ---

Issuing SOFT_RESET...





From rminnich at gmail.com  Tue Jul  3 18:18:06 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 3 Jul 2007 09:18:06 -0700
Subject: [LinuxBIOS] GA-M57SLI
In-Reply-To: <20070702234836.GI8232@greenwood>
References: <37367b3a0706251451n7b012fd9n4bedcdd977c89092@mail.gmail.com>
	<46824015.4000206@lotuspond.ca>
	<2ea3fae10706270958o6bdd96fbwa5ff00cae7431371@mail.gmail.com>
	<20070627173753.GA18911@coresystems.de>
	<2ea3fae10706271240r6398d02aq16ee12983e6a9b97@mail.gmail.com>
	<20070627194413.GA19628@coresystems.de>
	<20070702234836.GI8232@greenwood>
Message-ID: <13426df10707030918j225796c8mceff85f3f6cd6bfe@mail.gmail.com>

we're going to put kvm into flash. Xen is really falling out of favor
and kvm is winning. This was very clear at OLS as I talked to vendors.

ron



From rminnich at gmail.com  Tue Jul  3 18:19:12 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 3 Jul 2007 09:19:12 -0700
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070702233236.GE8232@greenwood>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be> <20070702233236.GE8232@greenwood>
Message-ID: <13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>

I don't care where flashrom is but it is really nice if ONE co is all
that is needed to get all you need.

thanks

ron



From marc.jones at amd.com  Tue Jul  3 18:39:32 2007
From: marc.jones at amd.com (Marc Jones)
Date: Tue, 03 Jul 2007 10:39:32 -0600
Subject: [LinuxBIOS] [Re: [PATCH] geode_v3_cleanup.patch - Re: r387 - in
 LinuxBIOSv3/arch/x86: . geodelx]
Message-ID: <468A7BC4.5090504@amd.com>


-------------- next part --------------
An embedded message was scrubbed...
From: "Marc Jones" <marc.jones at amd.com>
Subject: Re: [LinuxBIOS] [PATCH] geode_v3_cleanup.patch - Re: r387 - in LinuxBIOSv3/arch/x86: . geodelx
Date: Tue, 03 Jul 2007 10:21:06 -0600
Size: 13937
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20070703/33a6c5ff/attachment.mht>

From rminnich at gmail.com  Tue Jul  3 18:41:36 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 3 Jul 2007 09:41:36 -0700
Subject: [LinuxBIOS] [RFC] v3: dts fixes and questions
In-Reply-To: <4689C01D.7090309@gmail.com>
References: <20070630193805.GN10622@greenwood>
	<20070630214319.GA31719@coresystems.de>
	<20070630232022.466.qmail@stuge.se>
	<13426df10706301627s37ffd932jfdfbcb48371ec9b6@mail.gmail.com>
	<20070701000736.GH5201@greenwood>
	<13426df10706302048v330c243qf15befd1daba6371@mail.gmail.com>
	<20070701223832.GB8409@coresystems.de>
	<20070702232814.GD8232@greenwood> <4689C01D.7090309@gmail.com>
Message-ID: <13426df10707030941xeb44a6fn6b88cd6d3d93936d@mail.gmail.com>

On 7/2/07, Corey Osgood <corey.osgood at gmail.com> wrote:

> Agreed. Default to hardware enabled unless explicitly disabled, and
> clearly state that somewhere, seems the best route to me.


Will do. Look for it in a few days.

ron



From yinghailu at gmail.com  Tue Jul  3 18:42:12 2007
From: yinghailu at gmail.com (yhlu)
Date: Tue, 3 Jul 2007 09:42:12 -0700
Subject: [LinuxBIOS] GA-M57SLI
In-Reply-To: <13426df10707030918j225796c8mceff85f3f6cd6bfe@mail.gmail.com>
References: <37367b3a0706251451n7b012fd9n4bedcdd977c89092@mail.gmail.com>
	<46824015.4000206@lotuspond.ca>
	<2ea3fae10706270958o6bdd96fbwa5ff00cae7431371@mail.gmail.com>
	<20070627173753.GA18911@coresystems.de>
	<2ea3fae10706271240r6398d02aq16ee12983e6a9b97@mail.gmail.com>
	<20070627194413.GA19628@coresystems.de>
	<20070702234836.GI8232@greenwood>
	<13426df10707030918j225796c8mceff85f3f6cd6bfe@mail.gmail.com>
Message-ID: <2ea3fae10707030942uf3dfb45hb270feffb61f3a61@mail.gmail.com>

then linuxbios + tiny kernel with kvm could load other os and other linux.

YH

On 7/3/07, ron minnich <rminnich at gmail.com> wrote:
> we're going to put kvm into flash. Xen is really falling out of favor
> and kvm is winning. This was very clear at OLS as I talked to vendors.
>
> ron
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>



From yinghailu at gmail.com  Tue Jul  3 18:46:03 2007
From: yinghailu at gmail.com (yhlu)
Date: Tue, 3 Jul 2007 09:46:03 -0700
Subject: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n platinum)
	motherboard
In-Reply-To: <468A8B64.7030004@kami.ru>
References: <468A8B64.7030004@kami.ru>
Message-ID: <2ea3fae10707030946l41b4e748jc7c4dcb4f73efc1c@mail.gmail.com>

it mean your mem is not initilized properly.

socket AM2 or Socket F? you need to specify that in MB Config.lb

YH



From rminnich at gmail.com  Tue Jul  3 18:46:14 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 3 Jul 2007 09:46:14 -0700
Subject: [LinuxBIOS] GA-M57SLI
In-Reply-To: <2ea3fae10707030942uf3dfb45hb270feffb61f3a61@mail.gmail.com>
References: <37367b3a0706251451n7b012fd9n4bedcdd977c89092@mail.gmail.com>
	<46824015.4000206@lotuspond.ca>
	<2ea3fae10706270958o6bdd96fbwa5ff00cae7431371@mail.gmail.com>
	<20070627173753.GA18911@coresystems.de>
	<2ea3fae10706271240r6398d02aq16ee12983e6a9b97@mail.gmail.com>
	<20070627194413.GA19628@coresystems.de>
	<20070702234836.GI8232@greenwood>
	<13426df10707030918j225796c8mceff85f3f6cd6bfe@mail.gmail.com>
	<2ea3fae10707030942uf3dfb45hb270feffb61f3a61@mail.gmail.com>
Message-ID: <13426df10707030946h5db5c596le66e400bdc63d935@mail.gmail.com>

On 7/3/07, yhlu <yinghailu at gmail.com> wrote:
> then linuxbios + tiny kernel with kvm could load other os and other linux.

yes. Or kvm could *BE* the tiny kernel, with just the right drivers.
And, for other drivers, you leave that on disk. There's a lot of
options here.

ron



From marc.jones at amd.com  Tue Jul  3 18:48:00 2007
From: marc.jones at amd.com (Marc Jones)
Date: Tue, 03 Jul 2007 10:48:00 -0600
Subject: [LinuxBIOS] [Re: [PATCH] geode_v3_cleanup.patch - Re: r387 - in
 LinuxBIOSv3/arch/x86: . geodelx]
In-Reply-To: <468A7BC4.5090504@amd.com>
References: <468A7BC4.5090504@amd.com>
Message-ID: <468A7DC0.7010801@amd.com>

Sorry, I lost my comment and signed-off-by in the patch. This should be 
correct.
Marc


Marc Jones wrote:
> 
> 
> ------------------------------------------------------------------------
> 
> Subject:
> Re: [LinuxBIOS] [PATCH] geode_v3_cleanup.patch - Re: r387 - in 
> LinuxBIOSv3/arch/x86: . geodelx
> From:
> "Marc Jones" <marc.jones at amd.com>
> Date:
> Tue, 03 Jul 2007 10:21:06 -0600
> To:
> "Uwe Hermann" <uwe at hermann-uwe.de>
> 
> To:
> "Uwe Hermann" <uwe at hermann-uwe.de>
> 
> 
> Patch updated and comments inline.
> 
> Uwe Hermann wrote:
>> On Mon, Jul 02, 2007 at 05:55:12PM -0600, Marc Jones wrote:
>>> Clean up comments and #defines in Geode LX code.
>>>
>>> Signed-off-by: Marc Jones <marc.jones at amd.com>
>>>
>>> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
>>> ===================================================================
>>> --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c    2007-07-02 
>>> 11:23:59.000000000 -0600
>>> +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c    2007-07-02 
>>> 16:27:43.000000000 -0600
>>> @@ -40,8 +40,21 @@
>>>    */
>>>  
>>>  /** -  * start_time1 Starts Timer 1 for port 61 use. FIXME try to 
>>> figure
>>> -  * out what these values mean.
>>> +  * start_time1 Starts Timer 1 for port 61 use.
>>
>> You can omit the "start_time1" and other function names in Doxygen
>> comments, they're not required at all. Doxygen knows which function you
>> intend to document.
>>
>>
> done
> 
> 
>>> +  * 0x43 is PIT command/control.
>>> +  * 0x41 is PIT counter 1.
>>
>> These should have #defines too, I think.
>>
>>
> See follow on patch. Requires a change to a core file and should be 
> reviewed separately.
> 
>>> +  *
>>> +  * The command 0x56 means write counter 1 lower 8 bits in next IO,
>>> +  * set the counter mode to square wave generator (count down to 0
>>> +  * from programmed value twice in a row, alternating the output 
>>> signal)
>>> +  * counting in 16-bit binary mode.
>>> +  *
>>> +  * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh
>>> +  * approximately every 15us written to the counter.
>>> +  *
>>> +  * The PIT typically generating 1.19318 MHz
>>> +  * Timer 1 was used for RAM refresh on XT/AT and can be read on 
>>> port61.
>>> +  * Port61 is used by many timing loops for calibration.
>>>    */
>>>  void start_timer1(void)
>>>  {
>>> @@ -134,42 +147,44 @@
>>>   */
>>>  void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
>>>  {
>>> -    struct msr  msrGlcpSysRstpll;
>>> +    struct msr  msr_glcp_sys_pll;
>>>  
>>> -    msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
>>> +    msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL);
>>>  
>>>      printk(BIOS_DEBUG, -        "_MSR GLCP_SYS_RSTPLL (%08x) value 
>>> is: %08x:%08x\n", msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
>>> +        "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", 
>>> msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
>>>      post_code(POST_PLL_INIT);
>>>  
>>> -    if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
>>> +    if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
>>>          printk(BIOS_DEBUG,"Configuring PLL\n");
>>>          if (manualconf) {
>>>              post_code(POST_PLL_MANUAL);
>>>              /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
>>> -            msrGlcpSysRstpll.hi = pll_hi;
>>> +            msr_glcp_sys_pll.hi = pll_hi;
>>>  
>>>              /* Hold Count - how long we will sit in reset */
>>> -            msrGlcpSysRstpll.lo = pll_lo;
>>> +            msr_glcp_sys_pll.lo = pll_lo;
>>>          } else {
>>>              /*automatic configuration (straps) */
>>>              post_code(POST_PLL_STRAP);
>>> -            msrGlcpSysRstpll.lo &=
>>> +            /* Hold 0xDE*16clocks during reset. */
>>                                        ^
>>                                  missing space
>>
>>
> done
> 
>>> +            /* AMD recomended value for proper PLL reset.*/
>>> +            msr_glcp_sys_pll.lo &=
>>>                  ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
>>
>> Please also add the reason why AMD recommends the value (rationale) to
>> the code comment.
>>
>>
> I indicated it was the validated value. The rationale has been lost to 
> time.
> 
>>> -            msrGlcpSysRstpll.lo |=
>>> +            msr_glcp_sys_pll.lo |=
>>>                  (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
>>> -            msrGlcpSysRstpll.lo &=
>>> +            msr_glcp_sys_pll.lo &=
>>>                  ~(RSTPPL_LOWER_COREBYPASS_SET |
>>>                    RSTPPL_LOWER_MBBYPASS_SET);
>>> -            msrGlcpSysRstpll.lo |=
>>> +            msr_glcp_sys_pll.lo |=
>>>                  RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
>>>          }
>>>          /* Use SWFLAGS to remember: "we've already been here"  */
>>> -        msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
>>> +        msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
>>>  
>>>          /* "reset the chip" value */
>>> -        msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
>>> -        wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
>>> +        msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
>>> +        wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll);
>>>  
>>>          /*      You should never get here..... The chip has reset. */
>>>          printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
>>> @@ -183,9 +198,8 @@
>>>  
>>>  
>>>  /**
>>> - * Return the CPU clock rate. Rates in this system are always returned
>>> - * as multkiples of 33 Mhz.
>>> - *
>>> + * Return the CPU clock rate from the PLL MSR.
>>> + *   @return CPU speed in MHz
>>       ^^
>>   no spaces here, please
>>
> done
> 
>> Was the above comment incorrect? Are Mhz returned? Or multiples of 33 
>> MHz?
>>
> yes, the MSR holds setting is in multiples of 33MHz. The function 
> returns that actual MHz.
> 
> 
>>
>>>   */
>>>  u32 cpu_speed(void)
>>>  {
>>> @@ -193,17 +207,16 @@
>>>      struct msr  msr;
>>>  
>>>      msr = rdmsr(GLCP_SYS_RSTPLL);
>>> -    speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 
>>> 333) / 10;
>>> -    if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 
>>> 333) % 10) > 5) {
>>> +    speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 
>>> RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10;
>>> +    if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 
>>> RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) {
>>>          ++speed;
>>>      }
>>>      return (speed);
>>>  }
>>>  
>>>  /**
>>> - * Return the Geode Link clock rate.  Rates in this system are always
>>> - * returned as multkiples of 33 Mhz.
>>> - *
>>> + * Return the GeodeLink clock rate from the PLL MSR.
>>> + *   @return GeodeLink speed in MHz
>>       ^^
>>    no spaces
>>
>>  (also in some other places)
>>
>>
> done
>> Patch looks good, I'd say we commit the next revision.
>>
>>
>> Uwe.
> 
> 
> Marc
> 
> 
> ------------------------------------------------------------------------
> 
> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
> ===================================================================
> --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c	2007-07-02 11:42:59.000000000 -0600
> +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 08:53:38.000000000 -0600
> @@ -40,8 +40,21 @@
>    */
>  
>  /** 
> -  * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure
> -  * out what these values mean.
> +  * Starts Timer 1 for port 61 use.
> +  * 0x43 is PIT command/control.
> +  * 0x41 is PIT counter 1.
> +  *
> +  * The command 0x56 means write counter 1 lower 8 bits in next IO,
> +  * set the counter mode to square wave generator (count down to 0
> +  * from programmed value twice in a row, alternating the output signal)
> +  * counting in 16-bit binary mode.
> +  *
> +  * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh
> +  * approximately every 15us written to the counter.
> +  *
> +  * The PIT typically generating 1.19318 MHz
> +  * Timer 1 was used for RAM refresh on XT/AT and can be read on port61.
> +  * Port61 is used by many timing loops for calibration.
>    */
>  void start_timer1(void)
>  {
> @@ -134,42 +147,44 @@
>   */
>  void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
>  {
> -	struct msr  msrGlcpSysRstpll;
> +	struct msr  msr_glcp_sys_pll;
>  
> -	msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
> +	msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL);
>  
>  	printk(BIOS_DEBUG, 
> -		"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
> +		"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
>  	post_code(POST_PLL_INIT);
>  
> -	if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
> +	if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
>  		printk(BIOS_DEBUG,"Configuring PLL\n");
>  		if (manualconf) {
>  			post_code(POST_PLL_MANUAL);
>  			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
> -			msrGlcpSysRstpll.hi = pll_hi;
> +			msr_glcp_sys_pll.hi = pll_hi;
>  
>  			/* Hold Count - how long we will sit in reset */
> -			msrGlcpSysRstpll.lo = pll_lo;
> +			msr_glcp_sys_pll.lo = pll_lo;
>  		} else {
>  			/*automatic configuration (straps) */
>  			post_code(POST_PLL_STRAP);
> -			msrGlcpSysRstpll.lo &=
> +			/* Hold 0xDE * 16 clocks during reset. */
> +			/* AMD recomended value for PLL reset from silicon validation. */
> +			msr_glcp_sys_pll.lo &=
>  			    ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
> -			msrGlcpSysRstpll.lo |=
> +			msr_glcp_sys_pll.lo |=
>  			    (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
> -			msrGlcpSysRstpll.lo &=
> +			msr_glcp_sys_pll.lo &=
>  			    ~(RSTPPL_LOWER_COREBYPASS_SET |
>  			      RSTPPL_LOWER_MBBYPASS_SET);
> -			msrGlcpSysRstpll.lo |=
> +			msr_glcp_sys_pll.lo |=
>  			    RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
>  		}
>  		/* Use SWFLAGS to remember: "we've already been here"  */
> -		msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
> +		msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
>  
>  		/* "reset the chip" value */
> -		msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
> -		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
> +		msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
> +		wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll);
>  
>  		/*      You should never get here..... The chip has reset. */
>  		printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
> @@ -183,9 +198,8 @@
>  
>  
>  /**
> - * Return the CPU clock rate. Rates in this system are always returned
> - * as multkiples of 33 Mhz.
> - *
> + * Return the CPU clock rate from the PLL MSR.
> + * @return CPU speed in MHz
>   */
>  u32 cpu_speed(void)
>  {
> @@ -193,17 +207,16 @@
>  	struct msr  msr;
>  
>  	msr = rdmsr(GLCP_SYS_RSTPLL);
> -	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
> -	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
> +	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10;
> +	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) {
>  		++speed;
>  	}
>  	return (speed);
>  }
>  
>  /**
> - * Return the Geode Link clock rate.  Rates in this system are always
> - * returned as multkiples of 33 Mhz.
> - *
> + * Return the GeodeLink clock rate from the PLL MSR.
> + * @return GeodeLink speed in MHz
>   */
>  u32 geode_link_speed(void)
>  {
> @@ -211,8 +224,8 @@
>  	struct msr  msr;
>  
>  	msr = rdmsr(GLCP_SYS_RSTPLL);
> -	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
> -	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
> +	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10;
> +	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) {
>  		++speed;
>  	}
>  	return (speed);
> @@ -220,9 +233,8 @@
>  
>  
>  /**
> - * Return the PCI bus clock rate.  Rates in this system are always
> - * returned as multkiples of 33 Mhz.
> - *
> + * Return the PCI bus clock rate from the PLL MSR.
> + * @return PCI speed in MHz
>   */
>  u32 pci_speed(void)
>  {
> @@ -295,7 +307,7 @@
>  	  */
>  	msrnum = GLCP_DELAY_CONTROLS;
>  	msr = rdmsr(msrnum);
> -	if (msr.lo & ~(0x7C0)) {
> +	if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) {
>  		return;
>  	}
>  
> Index: LinuxBIOSv3/arch/x86/geodelx/stage1.c
> ===================================================================
> --- LinuxBIOSv3.orig/arch/x86/geodelx/stage1.c	2007-07-02 11:42:59.000000000 -0600
> +++ LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-02 11:43:04.000000000 -0600
> @@ -52,20 +52,20 @@
>  
>  	/* Setup access to the cache for under 640K. Note MC not setup yet. */
>  	msr.hi = 0x20000000;
> -	msr.lo = 0xfff80;
> -	wrmsr(MSR_GLIU0 + 0x20, msr);
> +	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
> +	wrmsr(MSR_GLIU0_BASE1, msr);
>  
>  	msr.hi = 0x20000000;
> -	msr.lo = 0x80fffe0;
> -	wrmsr(MSR_GLIU0 + 0x21, msr);
> +	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
> +	wrmsr(MSR_GLIU0_BASE2, msr);
>  
>  	msr.hi = 0x20000000;
> -	msr.lo = 0xfff80;
> -	wrmsr(MSR_GLIU1 + 0x20, msr);
> +	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
> +	wrmsr(MSR_GLIU1_BASE1, msr);
>  
>  	msr.hi = 0x20000000;
> -	msr.lo = 0x80fffe0;
> -	wrmsr(MSR_GLIU1 + 0x21, msr);
> +	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
> +	wrmsr(MSR_GLIU0_BASE2, msr);
>  
>  }
>  
> Index: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
> ===================================================================
> --- LinuxBIOSv3.orig/include/arch/x86/amd_geodelx.h	2007-07-02 11:42:59.000000000 -0600
> +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-02 11:43:04.000000000 -0600
> @@ -354,10 +354,13 @@
>  #define GLCP_GLD_MSR_ERROR			(MSR_GLCP + 0x2003)
>  #define GLCP_GLD_MSR_PM				(MSR_GLCP + 0x2004)
>  #define GLCP_DELAY_CONTROLS			(MSR_GLCP + 0x0F)
> +#define DELAY_LOWER_STATUS_MASK		 0x7C0
>  #define GLCP_SYS_RSTPLL				(MSR_GLCP + 0x14)	/* R/W */
>  #define RSTPLL_UPPER_GLMULT_SHIFT		7
> +#define RSTPLL_UPPER_GLMULT_MASK		0x1F
>  #define RSTPLL_UPPER_GLDIV_SHIFT		6
>  #define RSTPLL_UPPER_CPUMULT_SHIFT		1
> +#define RSTPLL_UPPER_CPUMULT_MASK		0x1F
>  #define RSTPLL_UPPER_CPUDIV_SHIFT		0
>  #define RSTPLL_LOWER_SWFLAGS_SHIFT		26
>  #define RSTPLL_LOWER_SWFLAGS_MASK		(0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
> 

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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From marc.jones at amd.com  Tue Jul  3 18:53:23 2007
From: marc.jones at amd.com (Marc Jones)
Date: Tue, 03 Jul 2007 10:53:23 -0600
Subject: [LinuxBIOS] [PATCH] v3: 8254_pit.patch
Message-ID: <468A7F03.1050207@amd.com>

I think that I put the 8254_pit.h in the correct place.
LinuxBIOSv3\include\arch\x86\8254_pit.h

Marc

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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From svn at openbios.org  Tue Jul  3 18:58:16 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue,  3 Jul 2007 18:58:16 +0200
Subject: [LinuxBIOS] r431 - in LinuxBIOSv3: . include include/arch/x86/arch
Message-ID: <mailman.496.1355071129.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-03 18:58:16 +0200 (Tue, 03 Jul 2007)
New Revision: 431

Modified:
   LinuxBIOSv3/HACKING
   LinuxBIOSv3/include/arch/x86/arch/spinlock.h
   LinuxBIOSv3/include/spinlock.h
Log:
Document origin of include/arch/x86/arch/spinlock.h and use proper
header. Some other minor fixes (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/HACKING
===================================================================
--- LinuxBIOSv3/HACKING	2007-07-02 20:57:45 UTC (rev 430)
+++ LinuxBIOSv3/HACKING	2007-07-03 16:58:16 UTC (rev 431)
@@ -95,6 +95,11 @@
   Files: include/asm-i386/processor.h, arch/i386/kernel/cpu/mtrr/state.c
   Current version we use: 297d9c035edd04327fedc0d1da27c2b112b66fcc (06/2007)
 
+* include/arch/x86/arch/spinlock.h: GPLv2
+  Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
+  Files: include/asm-i386/spinlock.h, include/asm-i386/spinlock_types.h
+  Current version we use: 139ec7c416248b9ea227d21839235344edfee1e0 (12/2006)
+
 * include/arch/x86/swab.h: GPLv2
   Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
   Current version we use: ?

Modified: LinuxBIOSv3/include/arch/x86/arch/spinlock.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-07-02 20:57:45 UTC (rev 430)
+++ LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-07-03 16:58:16 UTC (rev 431)
@@ -1,35 +1,26 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
+ * It is based on the Linux kernel file include/asm-i386/spinlock.h.
+ *
+ * Modifications are:
  * Copyright (C) 2001 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
  * Copyright (C) 2007 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 	
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
  */
 
 #ifndef ARCH_SPINLOCK_H
 #define ARCH_SPINLOCK_H
 
 /*
- * Your basic SMP spinlocks, allowing only a single CPU anywhere
+ * Your basic SMP spinlocks, allowing only a single CPU anywhere.
  */
 
 struct spinlock {
 	volatile unsigned int lock;
 };
 
-
 #define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 }
 
 /*
@@ -38,7 +29,7 @@
  *
  * We make no fairness assumptions. They have a cost.
  */
-#define barrier() __asm__ __volatile__("": : :"memory")
+#define barrier()		__asm__ __volatile__("": : :"memory")
 #define spin_is_locked(x)	(*(volatile char *)(&(x)->lock) <= 0)
 #define spin_unlock_wait(x)	do { barrier(); } while(spin_is_locked(x))
 
@@ -76,5 +67,4 @@
 
 #define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
 
-
 #endif /* ARCH_SPINLOCK_H */

Modified: LinuxBIOSv3/include/spinlock.h
===================================================================
--- LinuxBIOSv3/include/spinlock.h	2007-07-02 20:57:45 UTC (rev 430)
+++ LinuxBIOSv3/include/spinlock.h	2007-07-03 16:58:16 UTC (rev 431)
@@ -2,20 +2,22 @@
  * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2001 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
  * Copyright (C) 2007 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 	
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
 #ifndef SPINLOCK_H
@@ -32,7 +34,8 @@
 #define spin_unlock_wait(lock)	do {} while(0)
 #define spin_lock(lock)		do {} while(0)
 #define spin_unlock(lock)	do {} while(0)
-#define spin_define(lock)       /* empty */
+#define spin_define(lock)	/* empty */
+
 #endif
 
 #endif /* SPINLOCK_H */




From c-d.hailfinger.devel.2006 at gmx.net  Tue Jul  3 19:10:34 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 03 Jul 2007 19:10:34 +0200
Subject: [LinuxBIOS] [Re: [PATCH] geode_v3_cleanup.patch - Re: r387 - in
 LinuxBIOSv3/arch/x86: . geodelx]
In-Reply-To: <468A7DC0.7010801@amd.com>
References: <468A7BC4.5090504@amd.com> <468A7DC0.7010801@amd.com>
Message-ID: <468A830A.7060704@gmx.net>

On 03.07.2007 18:48, Marc Jones wrote:
> Clean up comments and #defines in Geode LX code.
> 
> Signed-off-by: Marc Jones <marc.jones at amd.com>
> 
> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
> ===================================================================
> --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c	2007-07-02 11:42:59.000000000 -0600
> +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 08:53:38.000000000 -0600
> @@ -40,8 +40,21 @@
>    */
>  
>  /** 
> -  * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure
> -  * out what these values mean.
> +  * Starts Timer 1 for port 61 use.
> +  * 0x43 is PIT command/control.
> +  * 0x41 is PIT counter 1.
> +  *
> +  * The command 0x56 means write counter 1 lower 8 bits in next IO,
> +  * set the counter mode to square wave generator (count down to 0
> +  * from programmed value twice in a row, alternating the output signal)
> +  * counting in 16-bit binary mode.
> +  *
> +  * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh
> +  * approximately every 15us written to the counter.

"written to the counter" does not seem to belong to the sentence.

> +  *
> +  * The PIT typically generating 1.19318 MHz
                        ^is

> +  * Timer 1 was used for RAM refresh on XT/AT and can be read on port61.
> +  * Port61 is used by many timing loops for calibration.
>    */
>  void start_timer1(void)
>  {
> @@ -134,42 +147,44 @@
>   */
>  void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
>  {
> -	struct msr  msrGlcpSysRstpll;
> +	struct msr  msr_glcp_sys_pll;

An explanation what glcp means would be nice.

>  
> -	msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
> +	msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL);
>  
>  	printk(BIOS_DEBUG, 
> -		"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
> +		"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
>  	post_code(POST_PLL_INIT);
>  
> -	if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
> +	if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
>  		printk(BIOS_DEBUG,"Configuring PLL\n");
>  		if (manualconf) {
>  			post_code(POST_PLL_MANUAL);
>  			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
> -			msrGlcpSysRstpll.hi = pll_hi;
> +			msr_glcp_sys_pll.hi = pll_hi;
>  
>  			/* Hold Count - how long we will sit in reset */
> -			msrGlcpSysRstpll.lo = pll_lo;
> +			msr_glcp_sys_pll.lo = pll_lo;
>  		} else {
>  			/*automatic configuration (straps) */
>  			post_code(POST_PLL_STRAP);
> -			msrGlcpSysRstpll.lo &=
> +			/* Hold 0xDE * 16 clocks during reset. */
> +			/* AMD recomended value for PLL reset from silicon validation. */
> +			msr_glcp_sys_pll.lo &=
>  			    ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
> -			msrGlcpSysRstpll.lo |=
> +			msr_glcp_sys_pll.lo |=
>  			    (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
> -			msrGlcpSysRstpll.lo &=
> +			msr_glcp_sys_pll.lo &=
>  			    ~(RSTPPL_LOWER_COREBYPASS_SET |
>  			      RSTPPL_LOWER_MBBYPASS_SET);
> -			msrGlcpSysRstpll.lo |=
> +			msr_glcp_sys_pll.lo |=
>  			    RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
>  		}
>  		/* Use SWFLAGS to remember: "we've already been here"  */
> -		msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
> +		msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
>  
>  		/* "reset the chip" value */
> -		msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
> -		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
> +		msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
> +		wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll);
>  
>  		/*      You should never get here..... The chip has reset. */
>  		printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
> @@ -183,9 +198,8 @@
>  
>  
>  /**
> - * Return the CPU clock rate. Rates in this system are always returned
> - * as multkiples of 33 Mhz.
> - *
> + * Return the CPU clock rate from the PLL MSR.
> + * @return CPU speed in MHz
>   */
>  u32 cpu_speed(void)
>  {
> @@ -193,17 +207,16 @@
>  	struct msr  msr;
>  
>  	msr = rdmsr(GLCP_SYS_RSTPLL);
> -	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
> -	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
> +	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10;
> +	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) {

80 chars per line please, but OTOH I see no way to split this sensibly
to multiple lines.

>  		++speed;
>  	}
>  	return (speed);
>  }
>  
>  /**
> - * Return the Geode Link clock rate.  Rates in this system are always
> - * returned as multkiples of 33 Mhz.
> - *
> + * Return the GeodeLink clock rate from the PLL MSR.
> + * @return GeodeLink speed in MHz
>   */
>  u32 geode_link_speed(void)
>  {
> @@ -211,8 +224,8 @@
>  	struct msr  msr;
>  
>  	msr = rdmsr(GLCP_SYS_RSTPLL);
> -	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
> -	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
> +	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10;
> +	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) {
>  		++speed;
>  	}
>  	return (speed);
> @@ -220,9 +233,8 @@
>  
>  
>  /**
> - * Return the PCI bus clock rate.  Rates in this system are always
> - * returned as multkiples of 33 Mhz.
> - *
> + * Return the PCI bus clock rate from the PLL MSR.
> + * @return PCI speed in MHz
>   */
>  u32 pci_speed(void)
>  {
> @@ -295,7 +307,7 @@
>  	  */
>  	msrnum = GLCP_DELAY_CONTROLS;
>  	msr = rdmsr(msrnum);
> -	if (msr.lo & ~(0x7C0)) {
> +	if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) {
>  		return;
>  	}
>  
> Index: LinuxBIOSv3/arch/x86/geodelx/stage1.c
> ===================================================================
> --- LinuxBIOSv3.orig/arch/x86/geodelx/stage1.c	2007-07-02 11:42:59.000000000 -0600
> +++ LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-02 11:43:04.000000000 -0600
> @@ -52,20 +52,20 @@
>  
>  	/* Setup access to the cache for under 640K. Note MC not setup yet. */

MC?

>  	msr.hi = 0x20000000;
> -	msr.lo = 0xfff80;
> -	wrmsr(MSR_GLIU0 + 0x20, msr);
> +	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
> +	wrmsr(MSR_GLIU0_BASE1, msr);
>  
>  	msr.hi = 0x20000000;
> -	msr.lo = 0x80fffe0;
> -	wrmsr(MSR_GLIU0 + 0x21, msr);
> +	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
> +	wrmsr(MSR_GLIU0_BASE2, msr);
>  
>  	msr.hi = 0x20000000;
> -	msr.lo = 0xfff80;
> -	wrmsr(MSR_GLIU1 + 0x20, msr);
> +	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
> +	wrmsr(MSR_GLIU1_BASE1, msr);
>  
>  	msr.hi = 0x20000000;
> -	msr.lo = 0x80fffe0;
> -	wrmsr(MSR_GLIU1 + 0x21, msr);
> +	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
> +	wrmsr(MSR_GLIU0_BASE2, msr);
>  
>  }
>  
> Index: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
> ===================================================================
> --- LinuxBIOSv3.orig/include/arch/x86/amd_geodelx.h	2007-07-02 11:42:59.000000000 -0600
> +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-02 11:43:04.000000000 -0600
> @@ -354,10 +354,13 @@
>  #define GLCP_GLD_MSR_ERROR			(MSR_GLCP + 0x2003)
>  #define GLCP_GLD_MSR_PM				(MSR_GLCP + 0x2004)
>  #define GLCP_DELAY_CONTROLS			(MSR_GLCP + 0x0F)
> +#define DELAY_LOWER_STATUS_MASK		 0x7C0
>  #define GLCP_SYS_RSTPLL				(MSR_GLCP + 0x14)	/* R/W */
>  #define RSTPLL_UPPER_GLMULT_SHIFT		7
> +#define RSTPLL_UPPER_GLMULT_MASK		0x1F
>  #define RSTPLL_UPPER_GLDIV_SHIFT		6
>  #define RSTPLL_UPPER_CPUMULT_SHIFT		1
> +#define RSTPLL_UPPER_CPUMULT_MASK		0x1F
>  #define RSTPLL_UPPER_CPUDIV_SHIFT		0
>  #define RSTPLL_LOWER_SWFLAGS_SHIFT		26
>  #define RSTPLL_LOWER_SWFLAGS_MASK		(0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
> 

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



From svn at openbios.org  Tue Jul  3 22:33:33 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue,  3 Jul 2007 22:33:33 +0200
Subject: [LinuxBIOS] r432 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
Message-ID: <mailman.497.1355071129.16123.coreboot@coreboot.org>

Author: mjones
Date: 2007-07-03 22:33:33 +0200 (Tue, 03 Jul 2007)
New Revision: 432

Modified:
   LinuxBIOSv3/arch/x86/geodelx/geodelx.c
   LinuxBIOSv3/arch/x86/geodelx/stage1.c
   LinuxBIOSv3/include/arch/x86/amd_geodelx.h
Log:
Clean up comments and #defines in Geode LX code.
 
Signed-off-by: Marc Jones <marc.jones at amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 16:58:16 UTC (rev 431)
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 20:33:33 UTC (rev 432)
@@ -40,8 +40,21 @@
   */
 
 /** 
-  * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure
-  * out what these values mean.
+  * Starts Timer 1 for port 61 use.
+  * 0x43 is PIT command/control.
+  * 0x41 is PIT counter 1.
+  *
+  * The command 0x56 means write counter 1 lower 8 bits in next IO,
+  * set the counter mode to square wave generator (count down to 0
+  * from programmed value twice in a row, alternating the output signal)
+  * counting in 16-bit binary mode.
+  *
+  * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh
+  * approximately every 15us.
+  *
+  * The PIT typically is generating 1.19318 MHz
+  * Timer 1 was used for RAM refresh on XT/AT and can be read on port61.
+  * Port61 is used by many timing loops for calibration.
   */
 void start_timer1(void)
 {
@@ -134,42 +147,44 @@
  */
 void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
 {
-	struct msr  msrGlcpSysRstpll;
+	struct msr  msr_glcp_sys_pll; /* GeodeLink PLL control MSR */
 
-	msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
+	msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL);
 
 	printk(BIOS_DEBUG, 
-		"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
+		"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
 	post_code(POST_PLL_INIT);
 
-	if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
+	if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
 		printk(BIOS_DEBUG,"Configuring PLL\n");
 		if (manualconf) {
 			post_code(POST_PLL_MANUAL);
 			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
-			msrGlcpSysRstpll.hi = pll_hi;
+			msr_glcp_sys_pll.hi = pll_hi;
 
 			/* Hold Count - how long we will sit in reset */
-			msrGlcpSysRstpll.lo = pll_lo;
+			msr_glcp_sys_pll.lo = pll_lo;
 		} else {
 			/*automatic configuration (straps) */
 			post_code(POST_PLL_STRAP);
-			msrGlcpSysRstpll.lo &=
+			/* Hold 0xDE * 16 clocks during reset. */
+			/* AMD recomended value for PLL reset from silicon validation. */
+			msr_glcp_sys_pll.lo &=
 			    ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
-			msrGlcpSysRstpll.lo |=
+			msr_glcp_sys_pll.lo |=
 			    (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
-			msrGlcpSysRstpll.lo &=
+			msr_glcp_sys_pll.lo &=
 			    ~(RSTPPL_LOWER_COREBYPASS_SET |
 			      RSTPPL_LOWER_MBBYPASS_SET);
-			msrGlcpSysRstpll.lo |=
+			msr_glcp_sys_pll.lo |=
 			    RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
 		}
 		/* Use SWFLAGS to remember: "we've already been here"  */
-		msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
+		msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
 
 		/* "reset the chip" value */
-		msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
-		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
+		msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
+		wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll);
 
 		/*      You should never get here..... The chip has reset. */
 		printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
@@ -183,9 +198,8 @@
 
 
 /**
- * Return the CPU clock rate. Rates in this system are always returned
- * as multkiples of 33 Mhz.
- *
+ * Return the CPU clock rate from the PLL MSR.
+ * @return CPU speed in MHz
  */
 u32 cpu_speed(void)
 {
@@ -193,17 +207,16 @@
 	struct msr  msr;
 
 	msr = rdmsr(GLCP_SYS_RSTPLL);
-	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
-	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
+	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10;
+	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) {
 		++speed;
 	}
 	return (speed);
 }
 
 /**
- * Return the Geode Link clock rate.  Rates in this system are always
- * returned as multkiples of 33 Mhz.
- *
+ * Return the GeodeLink clock rate from the PLL MSR.
+ * @return GeodeLink speed in MHz
  */
 u32 geode_link_speed(void)
 {
@@ -211,8 +224,8 @@
 	struct msr  msr;
 
 	msr = rdmsr(GLCP_SYS_RSTPLL);
-	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
-	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
+	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10;
+	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) {
 		++speed;
 	}
 	return (speed);
@@ -220,9 +233,8 @@
 
 
 /**
- * Return the PCI bus clock rate.  Rates in this system are always
- * returned as multkiples of 33 Mhz.
- *
+ * Return the PCI bus clock rate from the PLL MSR.
+ * @return PCI speed in MHz
  */
 u32 pci_speed(void)
 {
@@ -295,7 +307,7 @@
 	  */
 	msrnum = GLCP_DELAY_CONTROLS;
 	msr = rdmsr(msrnum);
-	if (msr.lo & ~(0x7C0)) {
+	if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) {
 		return;
 	}
 

Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-03 16:58:16 UTC (rev 431)
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-03 20:33:33 UTC (rev 432)
@@ -50,22 +50,23 @@
 	wrmsr(CPU_RCONF_C0_DF, msr);
 	wrmsr(CPU_RCONF_E0_FF, msr);
 
-	/* Setup access to the cache for under 640K. Note MC not setup yet. */
+	/* Setup access to the cache for under 640K. */
+	/* Note memory controler not setup yet. */
 	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU0 + 0x20, msr);
+	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
+	wrmsr(MSR_GLIU0_BASE1, msr);
 
 	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU0 + 0x21, msr);
+	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
+	wrmsr(MSR_GLIU0_BASE2, msr);
 
 	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU1 + 0x20, msr);
+	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
+	wrmsr(MSR_GLIU1_BASE1, msr);
 
 	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU1 + 0x21, msr);
+	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
+	wrmsr(MSR_GLIU0_BASE2, msr);
 
 }
 

Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-03 16:58:16 UTC (rev 431)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-03 20:33:33 UTC (rev 432)
@@ -354,10 +354,13 @@
 #define GLCP_GLD_MSR_ERROR			(MSR_GLCP + 0x2003)
 #define GLCP_GLD_MSR_PM				(MSR_GLCP + 0x2004)
 #define GLCP_DELAY_CONTROLS			(MSR_GLCP + 0x0F)
+#define DELAY_LOWER_STATUS_MASK		 0x7C0
 #define GLCP_SYS_RSTPLL				(MSR_GLCP + 0x14)	/* R/W */
 #define RSTPLL_UPPER_GLMULT_SHIFT		7
+#define RSTPLL_UPPER_GLMULT_MASK		0x1F
 #define RSTPLL_UPPER_GLDIV_SHIFT		6
 #define RSTPLL_UPPER_CPUMULT_SHIFT		1
+#define RSTPLL_UPPER_CPUMULT_MASK		0x1F
 #define RSTPLL_UPPER_CPUDIV_SHIFT		0
 #define RSTPLL_LOWER_SWFLAGS_SHIFT		26
 #define RSTPLL_LOWER_SWFLAGS_MASK		(0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)




From marc.jones at amd.com  Tue Jul  3 22:34:19 2007
From: marc.jones at amd.com (Marc Jones)
Date: Tue, 03 Jul 2007 14:34:19 -0600
Subject: [LinuxBIOS] [Re: [PATCH] geode_v3_cleanup.patch - Re: r387 - in
 LinuxBIOSv3/arch/x86: . geodelx]
In-Reply-To: <468A830A.7060704@gmx.net>
References: <468A7BC4.5090504@amd.com> <468A7DC0.7010801@amd.com>
	<468A830A.7060704@gmx.net>
Message-ID: <468AB2CB.2010607@amd.com>



Carl-Daniel Hailfinger wrote:
> On 03.07.2007 18:48, Marc Jones wrote:
>> Clean up comments and #defines in Geode LX code.
>>
>> Signed-off-by: Marc Jones <marc.jones at amd.com>
>>
....
> 
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> 

r432
-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From uwe at hermann-uwe.de  Wed Jul  4 00:04:59 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 00:04:59 +0200
Subject: [LinuxBIOS] [PATCH] v3: 8254_pit.patch
In-Reply-To: <468A7F03.1050207@amd.com>
References: <468A7F03.1050207@amd.com>
Message-ID: <20070703220459.GA17746@greenwood>

On Tue, Jul 03, 2007 at 10:53:23AM -0600, Marc Jones wrote:
> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
> ===================================================================
> --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c	2007-07-02 10:23:52.000000000 -0600
> +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 09:37:11.000000000 -0600
> @@ -30,6 +30,7 @@
>  #include <io.h>
>  #include <amd_geodelx.h>
>  #include <spd.h>
> +#include <8254_pit.h>
>  
>  /* all these functions used to be in a lot of fiddly little files.  To
>    * make it easier to find functions, we are merging them here. This
> @@ -41,8 +42,6 @@
>  
>  /** 
>    * Starts Timer 1 for port 61 use.
> -  * 0x43 is PIT command/control.
> -  * 0x41 is PIT counter 1.
>    *
>    * The command 0x56 means write counter 1 lower 8 bits in next IO,
>    * set the counter mode to square wave generator (count down to 0
> @@ -58,8 +57,8 @@
>    */
>  void start_timer1(void)
>  {
> -	outb(0x56, 0x43);
> -	outb(0x12, 0x41);
> +	outb(0x56, I82C54_CONTROL_WORD_REGISTER);
> +	outb(0x12, I82C54_COUNTER1);

Yep, but the 0x56 and 0x12 should be #defines (or have comments), too.

>  }
>  
>  /** 
> Index: LinuxBIOSv3/arch/x86/speaker.c
> ===================================================================
> --- LinuxBIOSv3.orig/arch/x86/speaker.c	2007-07-02 10:23:37.000000000 -0600
> +++ LinuxBIOSv3/arch/x86/speaker.c	2007-07-03 09:34:08.000000000 -0600
> @@ -2,6 +2,7 @@
>   * This file is part of the LinuxBIOS project.
>   *
>   * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
> + * Copyright (C) 2007 Advanced Micro Devices, Inc.

Nope, please drop that this time. There's no new code, just shuffling of
existing code in this patch.


>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
> @@ -18,23 +19,9 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>  
> -/*
> - * Datasheet:
> - *  - Name: 82C54 CHMOS Programmable Interval Timer
> - *  - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf
> - *  - Order number: 231244-006
> - */

Please let's keep this here _and_ in 8254_pit.h, it's useful in both
files, IMO.


> -
>  #include <io.h>
>  #include <lib.h>
> -
> -#define I82C54_CONTROL_WORD_REGISTER	0x43	/* Write-only. */
> -
> -#define I82C54_COUNTER0			0x40
> -#define I82C54_COUNTER1			0x41
> -#define I82C54_COUNTER2			0x42
> -
> -#define PC_SPEAKER_PORT			0x61

The PC_SPEAKER_PORT belongs in this file, I think. It's not PIT related,
but speaker related.


> +#include <8254_pit.h>
>  
>  /**
>   * Use the PC speaker to create a tone/sound of the specified frequency.
> Index: LinuxBIOSv3/include/arch/x86/8254_pit.h

Hm, maybe we should make this include/arch/x86/legacy.h and stick other
#defines in there, too. We should avoid too many small almost-empty
files and there will be other "legacy" devices which need #defines.


> ===================================================================
> --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> +++ LinuxBIOSv3/include/arch/x86/8254_pit.h	2007-07-03 09:34:04.000000000 -0600
> @@ -0,0 +1,36 @@
> + * Copyright (C) 2007 Advanced Micro Devices, Inc.

See above, drop this please.


Otherwise patch is ok.

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Wed Jul  4 00:06:34 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 00:06:34 +0200
Subject: [LinuxBIOS] [PATCH][v3] Add automagic detection
	for	-fno-stack-protector
In-Reply-To: <20070703030143.GB22459@coresystems.de>
References: <20070702233843.GG14253@cosmic.amd.com>
	<20070703030143.GB22459@coresystems.de>
Message-ID: <20070703220634.GB17746@greenwood>

On Tue, Jul 03, 2007 at 05:01:43AM +0200, Stefan Reinauer wrote:
> is there some way we can include this in util/xcompile/xcompile
> instead?
> 
> That script was meant to be an abstraction for stuff like this at some
> point.

Ack, would be better in xcompile. Could somebody please test this on
non-Linux platforms, too? E.g. Solaris, FreeBSD, OpenBSD etc. etc.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From jordan.crouse at amd.com  Wed Jul  4 00:09:16 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 3 Jul 2007 16:09:16 -0600
Subject: [LinuxBIOS] Add automagic detection for -fno-stack-protector
In-Reply-To: <20070703220634.GB17746@greenwood>
References: <20070702233843.GG14253@cosmic.amd.com>
	<20070703030143.GB22459@coresystems.de>
	<20070703220634.GB17746@greenwood>
Message-ID: <20070703220916.GA19894@cosmic.amd.com>

On 04/07/07 00:06 +0200, Uwe Hermann wrote:
> On Tue, Jul 03, 2007 at 05:01:43AM +0200, Stefan Reinauer wrote:
> > is there some way we can include this in util/xcompile/xcompile
> > instead?
> > 
> > That script was meant to be an abstraction for stuff like this at some
> > point.
> 
> Ack, would be better in xcompile. Could somebody please test this on
> non-Linux platforms, too? E.g. Solaris, FreeBSD, OpenBSD etc. etc.

Alright - xcompile it is.   i'll do the patch.

> 
> Uwe.
> -- 
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios

-- 
Jordan Crouse
Senior Linux Engineer
Advanced Micro Devices, Inc.
<www.amd.com/embeddedprocessors>





From peter at stuge.se  Wed Jul  4 00:10:29 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 4 Jul 2007 00:10:29 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>
Message-ID: <20070703221029.5251.qmail@stuge.se>

On Tue, Jul 03, 2007 at 09:19:12AM -0700, ron minnich wrote:
> I don't care where flashrom is but it is really nice if ONE co is
> all that is needed to get all you need.

To have that, and get _only_ what you need when you need the
utilities they get their own repo. I think that makes the most
sense logically too.

I am definately for the externals so they are pulled into both v2 and
v3 co:s too.

How does updates and commits work for the external repo-in-the-repo?


//Peter



From jordan.crouse at amd.com  Wed Jul  4 00:36:03 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 3 Jul 2007 16:36:03 -0600
Subject: [LinuxBIOS] Add automagic detection for -fno-stack-protector
In-Reply-To: <20070703220634.GB17746@greenwood>
References: <20070702233843.GG14253@cosmic.amd.com>
	<20070703030143.GB22459@coresystems.de>
	<20070703220634.GB17746@greenwood>
Message-ID: <20070703223603.GA14935@cosmic.amd.com>

On 04/07/07 00:06 +0200, Uwe Hermann wrote:
> On Tue, Jul 03, 2007 at 05:01:43AM +0200, Stefan Reinauer wrote:
> > is there some way we can include this in util/xcompile/xcompile
> > instead?
> > 
> > That script was meant to be an abstraction for stuff like this at some
> > point.
> 
> Ack, would be better in xcompile. Could somebody please test this on
> non-Linux platforms, too? E.g. Solaris, FreeBSD, OpenBSD etc. etc.

Okay then - here goes.   Please test extensively.....

Jordan
-------------- next part --------------
[PATCH][v3]  Add testcc() function to xcompile to check for -fno-stack-protector

enable xcompile to check for various compiler flags and set them in the 
CFLAGS variable if they are located.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>

Index: LinuxBIOSv3/Makefile
===================================================================
--- LinuxBIOSv3.orig/Makefile	2007-07-03 16:29:49.000000000 -0600
+++ LinuxBIOSv3/Makefile	2007-07-03 16:32:01.000000000 -0600
@@ -96,6 +96,7 @@
 AS := $(AS_$(ARCH))
 LD := $(LD_$(ARCH))
 OBJCOPY := $(OBJCOPY_$(ARCH))
+CFLAGS += $(CFLAGS_$(ARCH))
 
 CPPFLAGS := $(LINUXBIOSINCLUDE)
 CFLAGS += $(LINUXBIOSINCLUDE)
Index: LinuxBIOSv3/util/xcompile/xcompile
===================================================================
--- LinuxBIOSv3.orig/util/xcompile/xcompile	2007-07-03 16:32:16.000000000 -0600
+++ LinuxBIOSv3/util/xcompile/xcompile	2007-07-03 16:32:20.000000000 -0600
@@ -25,6 +25,15 @@
 			-e s/s390x/s390/ -e s/parisc64/parisc/ \
 			-e s/ppc.*/powerpc/ -e s/mips.*/mips/`
 
+testcc()
+{
+	TMP=".$$$$.tmp"
+	$1 $2 -S -xc /dev/null -o $TMP > /dev/null 2>&1
+	ret=$?
+	rm -rf $TMP
+	return $ret 
+}
+
 searchgnu()
 {
 	# $1 short name
@@ -45,18 +54,23 @@
 case  "$ARCH" in
 "x86_64")
 	echo "CC_x86 := gcc -m32"
+	CC="gcc -m32"
+
 	searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as) --32"
 	searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld) -b elf32-i386 -melf_i386"
 	searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)"
 	;;
 "x86")
 	echo "CC_x86 := gcc"
+	CC="gcc"
+
 	searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as)"
 	searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld)"
 	searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)"
 	;;
 *)
 	# FIXME: This should be detected.
+	CC="i386-linux-gcc"
 	echo "CC_x86 := i386-linux-gcc"
 	echo "AS_x86 := i386-linux-as"
 	echo "LD_x86 := i386-linux-ld"
@@ -64,6 +78,13 @@
 	;;
 esac
 
+# This is where we test for various flags and other things
+
+CFLAGS=""
+testcc "$CC" "-fno-stack-protector" && CFLAGS="$CFLAGS-fno-stack-protector " 
+
+echo "CFLAGS_x86 := $CFLAGS"
+
 # TODO: The same as above for PowerPC, and other architectures
 #       as soon as they are supported by LinuxBIOSv3.
 

From uwe at hermann-uwe.de  Wed Jul  4 01:28:49 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 01:28:49 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070703221029.5251.qmail@stuge.se>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>
	<20070703221029.5251.qmail@stuge.se>
Message-ID: <20070703232849.GC17746@greenwood>

On Wed, Jul 04, 2007 at 12:10:29AM +0200, Peter Stuge wrote:
> On Tue, Jul 03, 2007 at 09:19:12AM -0700, ron minnich wrote:
> > I don't care where flashrom is but it is really nice if ONE co is
> > all that is needed to get all you need.
> 
> To have that, and get _only_ what you need when you need the
> utilities they get their own repo. I think that makes the most
> sense logically too.

I strongly disagree.

There's absolutely no gain in having different physical repositories.
It's much better to have subdirectories in _one_ common repository.

You can do all you ever need this way:

Get v2:
svn co svn://linuxbios.org/repos/trunk/LinuxBIOSv2

Get only flashrom:
svn co svn://linuxbios.org/repos/trunk/util/flashrom

Get all utilities:
svn co svn://linuxbios.org/repos/trunk/util

Get everything (v2, v1, utilities, even v3 later):
svn co svn://linuxbios.org/repos/trunk


Having _different_ repositories will remove lots of advantages:

 - Common code browser (in trac) for all our code.

 - Common bug tracking system for all code.

   (We'd have to set up a _separate_ trac instance for another
    repository; that's the reason why you can't file bugs against
    LinuxBIOSv3 and why you cannot view the v3 code in trac, currently)

   We would then _not_ be able to move a bug report from one of the
   trac instances to the other, for example.
   We'd have to tell our users "no, not that trac, please report your
   bug in the other trac"...
   
 - Moving code becomes a _lot_ harder if you have different repos.
   Now it's a simple 'svn mv' and you automatically preserve all history.

 - You cannot easily do, say, 'svn log' or 'svn diff -r500:600' over all
   the code, you have to mess with _two_ repos...

The list goes on.


> I am definately for the externals so they are pulled into both v2 and
> v3 co:s too.
> 
> How does updates and commits work for the external repo-in-the-repo?

Think symlinks. If you do 'cd util/flashrom' in v2 and
change+commit things there, it'll be committed in flashrom (which is an
svn:externals), not in v2.

'svn up' in v2 will update v2 _and_ automatically update flashrom, as
it's an svn:external within v2.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From marc.jones at amd.com  Wed Jul  4 02:19:48 2007
From: marc.jones at amd.com (Marc Jones)
Date: Tue, 03 Jul 2007 18:19:48 -0600
Subject: [LinuxBIOS] [PATCH] v3: 8254_pit.patch
In-Reply-To: <20070703220459.GA17746@greenwood>
References: <468A7F03.1050207@amd.com>
 <20070703220459.GA17746@greenwood>
Message-ID: <468AE7A4.2000909@amd.com>

Updated the patch based on comments. Some comments inline below.

Uwe Hermann wrote:
> On Tue, Jul 03, 2007 at 10:53:23AM -0600, Marc Jones wrote:
>> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
>> ===================================================================
>> --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c	2007-07-02 10:23:52.000000000 -0600
>> +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 09:37:11.000000000 -0600
>> @@ -30,6 +30,7 @@
>>  #include <io.h>
>>  #include <amd_geodelx.h>
>>  #include <spd.h>
>> +#include <8254_pit.h>
>>  
>>  /* all these functions used to be in a lot of fiddly little files.  To
>>    * make it easier to find functions, we are merging them here. This
>> @@ -41,8 +42,6 @@
>>  
>>  /** 
>>    * Starts Timer 1 for port 61 use.
>> -  * 0x43 is PIT command/control.
>> -  * 0x41 is PIT counter 1.
>>    *
>>    * The command 0x56 means write counter 1 lower 8 bits in next IO,
>>    * set the counter mode to square wave generator (count down to 0
>> @@ -58,8 +57,8 @@
>>    */
>>  void start_timer1(void)
>>  {
>> -	outb(0x56, 0x43);
>> -	outb(0x12, 0x41);
>> +	outb(0x56, I82C54_CONTROL_WORD_REGISTER);
>> +	outb(0x12, I82C54_COUNTER1);
> 
> Yep, but the 0x56 and 0x12 should be #defines (or have comments), too.
> 
The 0x56 and 0x12 are well commented in the function header.

>>  }
>>  
>>  /** 
>> Index: LinuxBIOSv3/arch/x86/speaker.c
>> ===================================================================
>> --- LinuxBIOSv3.orig/arch/x86/speaker.c	2007-07-02 10:23:37.000000000 -0600
>> +++ LinuxBIOSv3/arch/x86/speaker.c	2007-07-03 09:34:08.000000000 -0600
>> @@ -2,6 +2,7 @@
>>   * This file is part of the LinuxBIOS project.
>>   *
>>   * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
>> + * Copyright (C) 2007 Advanced Micro Devices, Inc.
> 
> Nope, please drop that this time. There's no new code, just shuffling of
> existing code in this patch.
> 
ok
> 
>>   *
>>   * This program is free software; you can redistribute it and/or modify
>>   * it under the terms of the GNU General Public License as published by
>> @@ -18,23 +19,9 @@
>>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>>   */
>>  
>> -/*
>> - * Datasheet:
>> - *  - Name: 82C54 CHMOS Programmable Interval Timer
>> - *  - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf
>> - *  - Order number: 231244-006
>> - */
> 
> Please let's keep this here _and_ in 8254_pit.h, it's useful in both
> files, IMO.
> 
ok

> 
>> -
>>  #include <io.h>
>>  #include <lib.h>
>> -
>> -#define I82C54_CONTROL_WORD_REGISTER	0x43	/* Write-only. */
>> -
>> -#define I82C54_COUNTER0			0x40
>> -#define I82C54_COUNTER1			0x41
>> -#define I82C54_COUNTER2			0x42
>> -
>> -#define PC_SPEAKER_PORT			0x61
> 
> The PC_SPEAKER_PORT belongs in this file, I think. It's not PIT related,
> but speaker related.
>
good point

> 
>> +#include <8254_pit.h>
>>  
>>  /**
>>   * Use the PC speaker to create a tone/sound of the specified frequency.
>> Index: LinuxBIOSv3/include/arch/x86/8254_pit.h
> 
> Hm, maybe we should make this include/arch/x86/legacy.h and stick other
> #defines in there, too. We should avoid too many small almost-empty
> files and there will be other "legacy" devices which need #defines.
> 
> 
I started on this path but since there wasn't a legacy.h i figured 
everything was getting it's own headers. There is a legacy.h now.

>> ===================================================================
>> --- /dev/null	1970-01-01 00:00:00.000000000 +0000
>> +++ LinuxBIOSv3/include/arch/x86/8254_pit.h	2007-07-03 09:34:04.000000000 -0600
>> @@ -0,0 +1,36 @@
>> + * Copyright (C) 2007 Advanced Micro Devices, Inc.
> 
> See above, drop this please.
> 
ok
> 
> Otherwise patch is ok.
> 
> Uwe.
> 

Marc

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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From joe at smittys.pointclark.net  Wed Jul  4 15:22:54 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Wed, 04 Jul 2007 09:22:54 -0400
Subject: [LinuxBIOS] Convert hex to dec
Message-ID: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>

Hello,
Got another silly C newbie question.
If I want to convert a hex value to decimal, would this work?

value = ff /* Hex value */

sscanf(value, %d, &value)

Is the variable "value" now 255??


Thanks - Joe



From libv at skynet.be  Wed Jul  4 16:32:03 2007
From: libv at skynet.be (Luc Verhaegen)
Date: Wed, 4 Jul 2007 16:32:03 +0200
Subject: [LinuxBIOS] [patch] flashrom: add support for tyan tomcat k7m.
Message-ID: <20070704143203.GA12491@skynet.be>

Luc Verhaegen.
-------------- next part --------------
Flashrom: Add support for Tyan Tomcat K7M.

Same board enable as Asus A7V8-MX. Tested by Reinhard Max.

Signed-off-by: Luc Verhaegen <libv at skynet.be>

Index: board_enable.c
===================================================================
--- board_enable.c	(revision 2731)
+++ board_enable.c	(working copy)
@@ -138,8 +138,9 @@
 }
 
 /*
- * Suited for ASUS A7V8X-MX SE and A7V400-MX.
- *
+ * Suited for:
+ *   ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
+ *   Tyan Tomcat K7M: AMD Geode NX + VIA KM400 + VT8237.
  */
 
 static int board_asus_a7v8x_mx(const char *name)
@@ -148,9 +149,11 @@
 	uint8_t val;
 
 	dev = pci_dev_find(0x1106, 0x3177);	/* VT8235 ISA bridge */
+	if (!dev)
+	        dev = pci_dev_find(0x1106, 0x3227);	/* VT8237 ISA bridge */
 	if (!dev) {
-		fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n");
-		return -1;
+		    fprintf(stderr, "\nERROR: VT823x ISA Bridge not found.\n");
+		    return -1;
 	}
 
 	/* This bit is marked reserved actually */
@@ -300,6 +303,8 @@
 	 NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
 	{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
 	 NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx},
+	{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498,
+	 NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx},
 	{0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000,
 	 "asus", "p5a", "ASUS P5A", board_asus_p5a},
 	{0x1166, 0x0205, 0x1014, 0x0347, 0x0000, 0x0000, 0x0000, 0x0000,

From peter at stuge.se  Wed Jul  4 17:29:56 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 4 Jul 2007 17:29:56 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
Message-ID: <20070704152956.30330.qmail@stuge.se>

On Wed, Jul 04, 2007 at 09:22:54AM -0400, Joseph Smith wrote:
> Hello,
> Got another silly C newbie question.
> If I want to convert a hex value to decimal, would this work?
> 
> value = ff /* Hex value */
> 
> sscanf(value, %d, &value)
> 
> Is the variable "value" now 255??

Hexadecimal, decimal and octal are different ways for us humans to
express numbers to computers, but no matter what we use, they are
always stored in binary form in the machine.

Thus, there is no difference between a number in hexadecimal or
decimal. We do however have to tell the computer which formatting we
want when the computer should show us the numbers.

unsigned char value;

value=0xff; /* hexadecimal */

/* %d means print number in decimal */
printf("value in decimal is now %d\n",value);


value=135; /* decimal */

/* %x means print in hex */
printf("value in hexadecimal is now %x\n",value);


value=0254; /* octal */

if(0xac==0254)
  printf("C knows that 0xac == 0254 because they are both == %d\n",value);


Have a look at the printf man page for your nearest C library to
learn about all the good stuff you can put into formatting strings
besides just %d and %x.


//Peter



From stepan at coresystems.de  Wed Jul  4 17:50:09 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 4 Jul 2007 17:50:09 +0200
Subject: [LinuxBIOS] r431 - in LinuxBIOSv3: .
	include	include/arch/x86/arch
Message-ID: <20070704155009.GC7595@coresystems.de>

Please do not remove license headers. 

All files must have a valid license header, also the imported ones.
If we can not determine the license, we can not use the code.

* svn at openbios.org <svn at openbios.org> [070703 18:58]:
> Author: uwe
> Date: 2007-07-03 18:58:16 +0200 (Tue, 03 Jul 2007)
> New Revision: 431
> 
> Modified:
>    LinuxBIOSv3/HACKING
>    LinuxBIOSv3/include/arch/x86/arch/spinlock.h
>    LinuxBIOSv3/include/spinlock.h
> Log:
> Document origin of include/arch/x86/arch/spinlock.h and use proper
> header. Some other minor fixes (trivial).
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> 
> 
> Modified: LinuxBIOSv3/HACKING
> ===================================================================
> --- LinuxBIOSv3/HACKING	2007-07-02 20:57:45 UTC (rev 430)
> +++ LinuxBIOSv3/HACKING	2007-07-03 16:58:16 UTC (rev 431)
> @@ -95,6 +95,11 @@
>    Files: include/asm-i386/processor.h, arch/i386/kernel/cpu/mtrr/state.c
>    Current version we use: 297d9c035edd04327fedc0d1da27c2b112b66fcc (06/2007)
>  
> +* include/arch/x86/arch/spinlock.h: GPLv2
> +  Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
> +  Files: include/asm-i386/spinlock.h, include/asm-i386/spinlock_types.h
> +  Current version we use: 139ec7c416248b9ea227d21839235344edfee1e0 (12/2006)
> +
>  * include/arch/x86/swab.h: GPLv2
>    Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
>    Current version we use: ?
> 
> Modified: LinuxBIOSv3/include/arch/x86/arch/spinlock.h
> ===================================================================
> --- LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-07-02 20:57:45 UTC (rev 430)
> +++ LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-07-03 16:58:16 UTC (rev 431)
> @@ -1,35 +1,26 @@
>  /*
>   * This file is part of the LinuxBIOS project.
>   *
> + * It is based on the Linux kernel file include/asm-i386/spinlock.h.
> + *
> + * Modifications are:
>   * Copyright (C) 2001 Linux Networx
> + * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
>   * Copyright (C) 2007 coresystems GmbH
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; version 2 of the License.
> - * 
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - * 	
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
>   */
>  
>  #ifndef ARCH_SPINLOCK_H
>  #define ARCH_SPINLOCK_H
>  
>  /*
> - * Your basic SMP spinlocks, allowing only a single CPU anywhere
> + * Your basic SMP spinlocks, allowing only a single CPU anywhere.
>   */
>  
>  struct spinlock {
>  	volatile unsigned int lock;
>  };
>  
> -
>  #define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 }
>  
>  /*
> @@ -38,7 +29,7 @@
>   *
>   * We make no fairness assumptions. They have a cost.
>   */
> -#define barrier() __asm__ __volatile__("": : :"memory")
> +#define barrier()		__asm__ __volatile__("": : :"memory")
>  #define spin_is_locked(x)	(*(volatile char *)(&(x)->lock) <= 0)
>  #define spin_unlock_wait(x)	do { barrier(); } while(spin_is_locked(x))
>  
> @@ -76,5 +67,4 @@
>  
>  #define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
>  
> -
>  #endif /* ARCH_SPINLOCK_H */
> 
> Modified: LinuxBIOSv3/include/spinlock.h
> ===================================================================
> --- LinuxBIOSv3/include/spinlock.h	2007-07-02 20:57:45 UTC (rev 430)
> +++ LinuxBIOSv3/include/spinlock.h	2007-07-03 16:58:16 UTC (rev 431)
> @@ -2,20 +2,22 @@
>   * This file is part of the LinuxBIOS project.
>   *
>   * Copyright (C) 2001 Linux Networx
> + * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
>   * Copyright (C) 2007 coresystems GmbH
> + * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
>   * the Free Software Foundation; version 2 of the License.
> - * 
> + *
>   * This program is distributed in the hope that it will be useful,
>   * but WITHOUT ANY WARRANTY; without even the implied warranty of
>   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>   * GNU General Public License for more details.
> - * 	
> + *
>   * You should have received a copy of the GNU General Public License
>   * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>  
>  #ifndef SPINLOCK_H
> @@ -32,7 +34,8 @@
>  #define spin_unlock_wait(lock)	do {} while(0)
>  #define spin_lock(lock)		do {} while(0)
>  #define spin_unlock(lock)	do {} while(0)
> -#define spin_define(lock)       /* empty */
> +#define spin_define(lock)	/* empty */
> +
>  #endif
>  
>  #endif /* SPINLOCK_H */
> 
> 
> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
> 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From uwe at hermann-uwe.de  Wed Jul  4 18:14:25 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 18:14:25 +0200
Subject: [LinuxBIOS] r431 - in LinuxBIOSv3: .
	include	include/arch/x86/arch
In-Reply-To: <20070704155009.GC7595@coresystems.de>
References: <20070704155009.GC7595@coresystems.de>
Message-ID: <20070704161424.GJ17746@greenwood>

On Wed, Jul 04, 2007 at 05:50:09PM +0200, Stefan Reinauer wrote:
> Please do not remove license headers. 
> 
> All files must have a valid license header, also the imported ones.
> If we can not determine the license, we can not use the code.

Yes, I fully agree. But we know the license, it's the GPLv2 for all Linux
code except where noted otherwise (also mentioned in HACKING).

I think the "taken from Linux" mini-header should be enough, but we can also
make it clearer if you want:


Method 1 (mini-header with license mentioned):

/*
 * This file is part of the LinuxBIOS project.
 *
 * It is based on the Linux kernel file include/asm-i386/spinlock.h,
 * and is thus licensed under the terms of the GNU GPL, version 2.
 *
 * Modifications are:
 * Copyright (C) 2001 Linux Networx
 * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
 * Copyright (C) 2007 coresystems GmbH
 * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
 */


Method 2 (full header) - THIS IS WRONG!:

/*
 * This file is part of the LinuxBIOS project.
 *
 * It is based on the Linux kernel file include/asm-i386/spinlock.h.
 *
 * Copyright (C) 2001 Linux Networx
 * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
 * Copyright (C) 2007 coresystems GmbH
 * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

This is _not_ correct, as we only list the copyright lines of our
modifications, but not the copyright lines of the original Linux code
authors (because they're not in the Linux file, and we don't know them).
This looks like the file was written purely by us, which is wrong.

This is the reason why I prefer the mini-header (method 1). We just say
"we took this from Linux", which is ok license-wise, as we know the code
is GPL'd. But we don't have to care about finding/listing the copyright
holders, if somebody wants to know we refer them to the Linux developers
or git history or something...


Method 3 (full header, but only list modifications):

/*
 * This file is part of the LinuxBIOS project.
 *
 * It is based on the Linux kernel file include/asm-i386/spinlock.h.
 *
 * Modifications are:
 * Copyright (C) 2001 Linux Networx
 * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
 * Copyright (C) 2007 coresystems GmbH
 * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

This is probably a good compromise. We list the license explicitly, and
(only) the authors of the modifications.

I think either the current method, or method 1 or 3 are fine.

Comments?



> > Modified: LinuxBIOSv3/HACKING
> > ===================================================================
> > --- LinuxBIOSv3/HACKING	2007-07-02 20:57:45 UTC (rev 430)
> > +++ LinuxBIOSv3/HACKING	2007-07-03 16:58:16 UTC (rev 431)
> > @@ -95,6 +95,11 @@
> >    Files: include/asm-i386/processor.h, arch/i386/kernel/cpu/mtrr/state.c
> >    Current version we use: 297d9c035edd04327fedc0d1da27c2b112b66fcc (06/2007)
> >  
> > +* include/arch/x86/arch/spinlock.h: GPLv2
> > +  Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
> > +  Files: include/asm-i386/spinlock.h, include/asm-i386/spinlock_types.h
> > +  Current version we use: 139ec7c416248b9ea227d21839235344edfee1e0 (12/2006)
> > +
> >  * include/arch/x86/swab.h: GPLv2
> >    Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
> >    Current version we use: ?
> > 
> > Modified: LinuxBIOSv3/include/arch/x86/arch/spinlock.h
> > ===================================================================
> > --- LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-07-02 20:57:45 UTC (rev 430)
> > +++ LinuxBIOSv3/include/arch/x86/arch/spinlock.h	2007-07-03 16:58:16 UTC (rev 431)
> > @@ -1,35 +1,26 @@
> >  /*
> >   * This file is part of the LinuxBIOS project.
> >   *
> > + * It is based on the Linux kernel file include/asm-i386/spinlock.h.
> > + *
> > + * Modifications are:
> >   * Copyright (C) 2001 Linux Networx
> > + * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
> >   * Copyright (C) 2007 coresystems GmbH
> > - *
> > - * This program is free software; you can redistribute it and/or modify
> > - * it under the terms of the GNU General Public License as published by
> > - * the Free Software Foundation; version 2 of the License.
> > - * 
> > - * This program is distributed in the hope that it will be useful,
> > - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > - * GNU General Public License for more details.
> > - * 	
> > - * You should have received a copy of the GNU General Public License
> > - * along with this program; if not, write to the Free Software
> > - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > + * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> >   */
> >  
> >  #ifndef ARCH_SPINLOCK_H
> >  #define ARCH_SPINLOCK_H
> >  
> >  /*
> > - * Your basic SMP spinlocks, allowing only a single CPU anywhere
> > + * Your basic SMP spinlocks, allowing only a single CPU anywhere.
> >   */
> >  
> >  struct spinlock {
> >  	volatile unsigned int lock;
> >  };
> >  
> > -
> >  #define SPIN_LOCK_UNLOCKED (struct spinlock) { 1 }
> >  
> >  /*
> > @@ -38,7 +29,7 @@
> >   *
> >   * We make no fairness assumptions. They have a cost.
> >   */
> > -#define barrier() __asm__ __volatile__("": : :"memory")
> > +#define barrier()		__asm__ __volatile__("": : :"memory")
> >  #define spin_is_locked(x)	(*(volatile char *)(&(x)->lock) <= 0)
> >  #define spin_unlock_wait(x)	do { barrier(); } while(spin_is_locked(x))
> >  
> > @@ -76,5 +67,4 @@
> >  
> >  #define spin_define(spin) static struct spinlock spin = SPIN_LOCK_UNLOCKED
> >  
> > -
> >  #endif /* ARCH_SPINLOCK_H */
> > 
> > Modified: LinuxBIOSv3/include/spinlock.h
> > ===================================================================
> > --- LinuxBIOSv3/include/spinlock.h	2007-07-02 20:57:45 UTC (rev 430)
> > +++ LinuxBIOSv3/include/spinlock.h	2007-07-03 16:58:16 UTC (rev 431)
> > @@ -2,20 +2,22 @@
> >   * This file is part of the LinuxBIOS project.
> >   *
> >   * Copyright (C) 2001 Linux Networx
> > + * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
> >   * Copyright (C) 2007 coresystems GmbH
> > + * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> >   *
> >   * This program is free software; you can redistribute it and/or modify
> >   * it under the terms of the GNU General Public License as published by
> >   * the Free Software Foundation; version 2 of the License.
> > - * 
> > + *
> >   * This program is distributed in the hope that it will be useful,
> >   * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >   * GNU General Public License for more details.
> > - * 	
> > + *
> >   * You should have received a copy of the GNU General Public License
> >   * along with this program; if not, write to the Free Software
> > - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> >   */
> >  
> >  #ifndef SPINLOCK_H
> > @@ -32,7 +34,8 @@
> >  #define spin_unlock_wait(lock)	do {} while(0)
> >  #define spin_lock(lock)		do {} while(0)
> >  #define spin_unlock(lock)	do {} while(0)
> > -#define spin_define(lock)       /* empty */
> > +#define spin_define(lock)	/* empty */
> > +
> >  #endif
> >  
> >  #endif /* SPINLOCK_H */


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Wed Jul  4 18:31:15 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 4 Jul 2007 18:31:15 +0200
Subject: [LinuxBIOS] r431 - in LinuxBIOSv3: .
	include	include/arch/x86/arch
In-Reply-To: <20070704161424.GJ17746@greenwood>
References: <20070704155009.GC7595@coresystems.de>
	<20070704161424.GJ17746@greenwood>
Message-ID: <20070704163115.GA20684@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070704 18:14]:
> Yes, I fully agree. But we know the license, it's the GPLv2 for all Linux
> code except where noted otherwise (also mentioned in HACKING).
 
We do, but do we implicitly expect this from anyone else?

> I think the "taken from Linux" mini-header should be enough, but we can also
> make it clearer if you want:
> 
> This is probably a good compromise. We list the license explicitly, and
> (only) the authors of the modifications.
 
> I think either the current method, or method 1 or 3 are fine.

I think 3 is the best one.. We are already going safe in so many places
(licenses for dts files and Kconfig files), so we should maybe just do
the same here.

Other opinions?

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Wed Jul  4 19:24:52 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 4 Jul 2007 19:24:52 +0200
Subject: [LinuxBIOS] r2731 - trunk/LinuxBIOSv2/util
In-Reply-To: <20070702152445.GC11224@cosmic.amd.com>
References: <20070701215734.22994.qmail@stuge.se>
	<20070701223451.GA8409@coresystems.de>
	<20070702152445.GC11224@cosmic.amd.com>
Message-ID: <20070704172452.GB26224@coresystems.de>

* Jordan Crouse <jordan.crouse at amd.com> [070702 17:24]:
> On 02/07/07 00:34 +0200, Stefan Reinauer wrote:
> > * Peter Stuge <peter at stuge.se> [070701 23:57]:
> > > On Sun, Jul 01, 2007 at 09:47:31PM +0200, svn at openbios.org wrote:
> > > > Name: svn:externals
> > > >    + flashrom svn://linuxbios.org/repos/trunk/util/flashrom
> > > 
> > > Do we want a completely new repo for utils?
> > 
> > Yes we do.
> 
> I would like to see LAR in there too - it would be very handy to be able
> to build LAR without the whole LBv3 tree, especially for buildrom (/me
> laughs evilly).

Hm. What do you use it for, if not with v3?  ;-)

But I agree it should go to the util dir/repo/...

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Wed Jul  4 19:43:36 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 19:43:36 +0200
Subject: [LinuxBIOS] [PATCH] v3: 8254_pit.patch
In-Reply-To: <468AE7A4.2000909@amd.com>
References: <468A7F03.1050207@amd.com> <20070703220459.GA17746@greenwood>
	<468AE7A4.2000909@amd.com>
Message-ID: <20070704174336.GK17746@greenwood>

On Tue, Jul 03, 2007 at 06:19:48PM -0600, Marc Jones wrote:
>> Yep, but the 0x56 and 0x12 should be #defines (or have comments), too.
> The 0x56 and 0x12 are well commented in the function header.

Ah, yes, I should have looked a bit closer.


> Moved some generic 8254 PIT #defines out of the speaker code to legacy.h.
> Use legacy.h PIT defines in Geode code.
> 
> Signed-off-by: Marc Jones <marc.jones at amd.com>

Looks good to me.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Wed Jul  4 19:47:11 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 19:47:11 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070704152956.30330.qmail@stuge.se>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
Message-ID: <20070704174711.GL17746@greenwood>

On Wed, Jul 04, 2007 at 05:29:56PM +0200, Peter Stuge wrote:
> On Wed, Jul 04, 2007 at 09:22:54AM -0400, Joseph Smith wrote:
> > Hello,
> > Got another silly C newbie question.
> > If I want to convert a hex value to decimal, would this work?
> > 
> > value = ff /* Hex value */
> > 
> > sscanf(value, %d, &value)
> > 
> > Is the variable "value" now 255??
> 
> Hexadecimal, decimal and octal are different ways for us humans to
> express numbers to computers, but no matter what we use, they are
> always stored in binary form in the machine.
> 
> Thus, there is no difference between a number in hexadecimal or
> decimal. We do however have to tell the computer which formatting we
> want when the computer should show us the numbers.
> 
> unsigned char value;
> 
> value=0xff; /* hexadecimal */
> 
> /* %d means print number in decimal */
> printf("value in decimal is now %d\n",value);
> 
> 
> value=135; /* decimal */
> 
> /* %x means print in hex */
> printf("value in hexadecimal is now %x\n",value);
> 
> 
> value=0254; /* octal */
> 
> if(0xac==0254)
>   printf("C knows that 0xac == 0254 because they are both == %d\n",value);
> 
> 
> Have a look at the printf man page for your nearest C library to
> learn about all the good stuff you can put into formatting strings
> besides just %d and %x.

I use some aliases in my .bashrc which are pretty handy for converting
HEX or BINARY or DECIMAL:

alias HEX="ruby -e 'printf(\"0x%X\n\", ARGV[0])'"
alias DEC="ruby -e 'printf(\"%d\n\", ARGV[0])'"
alias BIN="ruby -e 'printf(\"%bb\n\", ARGV[0])'"

(You can replace 'ruby' with 'perl' if you want)

Usage:

$ HEX 78
0x4E
$ BIN 0x6a
1101010b
$ DEC 0x72
114


HTH, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Wed Jul  4 19:51:50 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed,  4 Jul 2007 19:51:50 +0200
Subject: [LinuxBIOS] r2732 - trunk/util/flashrom
Message-ID: <mailman.498.1355071130.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-04 19:51:49 +0200 (Wed, 04 Jul 2007)
New Revision: 2732

Modified:
   trunk/util/flashrom/board_enable.c
Log:
Flashrom: Add support for Tyan Tomcat K7M.

Same board enable as Asus A7V8-MX. Tested by Reinhard Max.

Signed-off-by: Luc Verhaegen <libv at skynet.be>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/flashrom/board_enable.c
===================================================================
--- trunk/util/flashrom/board_enable.c	2007-07-01 19:47:31 UTC (rev 2731)
+++ trunk/util/flashrom/board_enable.c	2007-07-04 17:51:49 UTC (rev 2732)
@@ -138,8 +138,9 @@
 }
 
 /*
- * Suited for ASUS A7V8X-MX SE and A7V400-MX.
- *
+ * Suited for:
+ *   ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
+ *   Tyan Tomcat K7M: AMD Geode NX + VIA KM400 + VT8237.
  */
 
 static int board_asus_a7v8x_mx(const char *name)
@@ -148,8 +149,10 @@
 	uint8_t val;
 
 	dev = pci_dev_find(0x1106, 0x3177);	/* VT8235 ISA bridge */
+	if (!dev)
+		dev = pci_dev_find(0x1106, 0x3227);	/* VT8237 ISA bridge */
 	if (!dev) {
-		fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n");
+		fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
 		return -1;
 	}
 
@@ -300,6 +303,8 @@
 	 NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
 	{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
 	 NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx},
+	{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498,
+	 NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx},
 	{0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000,
 	 "asus", "p5a", "ASUS P5A", board_asus_p5a},
 	{0x1166, 0x0205, 0x1014, 0x0347, 0x0000, 0x0000, 0x0000, 0x0000,




From uwe at hermann-uwe.de  Wed Jul  4 19:52:31 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 19:52:31 +0200
Subject: [LinuxBIOS] [patch] flashrom: add support for tyan tomcat k7m.
In-Reply-To: <20070704143203.GA12491@skynet.be>
References: <20070704143203.GA12491@skynet.be>
Message-ID: <20070704175231.GM17746@greenwood>

On Wed, Jul 04, 2007 at 04:32:03PM +0200, Luc Verhaegen wrote:
> Flashrom: Add support for Tyan Tomcat K7M.
> 
> Same board enable as Asus A7V8-MX. Tested by Reinhard Max.
> 
> Signed-off-by: Luc Verhaegen <libv at skynet.be>

Looks good, r2732.


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Wed Jul  4 20:01:54 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 4 Jul 2007 20:01:54 +0200
Subject: [LinuxBIOS] Add automagic detection for -fno-stack-protector
In-Reply-To: <20070703223603.GA14935@cosmic.amd.com>
References: <20070702233843.GG14253@cosmic.amd.com>
	<20070703030143.GB22459@coresystems.de>
	<20070703220634.GB17746@greenwood>
	<20070703223603.GA14935@cosmic.amd.com>
Message-ID: <20070704180154.GN17746@greenwood>

On Tue, Jul 03, 2007 at 04:36:03PM -0600, Jordan Crouse wrote:
> [PATCH][v3]  Add testcc() function to xcompile to check for -fno-stack-protector
> 
> enable xcompile to check for various compiler flags and set them in the 
> CFLAGS variable if they are located.
> 
> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>

Looks good, and works for me (but I cannot test the case where
-fno-stack-protector is actually needed, my setup doesn't require it).

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

 
Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From info at coresystems.de  Wed Jul  4 20:38:32 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Wed, 04 Jul 2007 20:38:32 +0200
Subject: [LinuxBIOS] r2732 build service
Message-ID: <E1I69kG-0001Kg-Rq@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "" checked in revision 2732 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:


Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2732&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in 's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From peter at stuge.se  Wed Jul  4 21:32:02 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 4 Jul 2007 21:32:02 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070704174711.GL17746@greenwood>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
Message-ID: <20070704193203.7640.qmail@stuge.se>

On Wed, Jul 04, 2007 at 07:47:11PM +0200, Uwe Hermann wrote:
> I use some aliases in my .bashrc which are pretty handy for converting
> HEX or BINARY or DECIMAL:
> 
> alias HEX="ruby -e 'printf(\"0x%X\n\", ARGV[0])'"
> alias DEC="ruby -e 'printf(\"%d\n\", ARGV[0])'"
> alias BIN="ruby -e 'printf(\"%bb\n\", ARGV[0])'"
> 
> (You can replace 'ruby' with 'perl' if you want)

bash has printf too; try printf 0x%X\\n 128


//Peter



From acassis at gmail.com  Wed Jul  4 21:59:17 2007
From: acassis at gmail.com (Alan Carvalho de Assis)
Date: Wed, 4 Jul 2007 16:59:17 -0300
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070704193203.7640.qmail@stuge.se>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070704193203.7640.qmail@stuge.se>
Message-ID: <37367b3a0707041259q5eec2bf3k8215078697ff18d5@mail.gmail.com>

2007/7/4, Peter Stuge <peter at stuge.se>:
> On Wed, Jul 04, 2007 at 07:47:11PM +0200, Uwe Hermann wrote:
> > I use some aliases in my .bashrc which are pretty handy for converting
> > HEX or BINARY or DECIMAL:
> >
> > alias HEX="ruby -e 'printf(\"0x%X\n\", ARGV[0])'"
> > alias DEC="ruby -e 'printf(\"%d\n\", ARGV[0])'"
> > alias BIN="ruby -e 'printf(\"%bb\n\", ARGV[0])'"
> >
> > (You can replace 'ruby' with 'perl' if you want)
>
> bash has printf too; try printf 0x%X\\n 128
>

Yes, printf at shell is very useful, I use this command to reset BIOS CMOS:

# printf "\x2E" | dd bs=1 seek=112 of=/dev/port
# printf "\xFF" | dd bs=1 seek=113 of=/dev/port

It sends 0x2E to port 0x70 and 0xFF to port 0x71.

>
> //Peter
>

Alan



From joe at smittys.pointclark.net  Wed Jul  4 22:36:57 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Wed, 04 Jul 2007 16:36:57 -0400
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070704152956.30330.qmail@stuge.se>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
Message-ID: <20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>

Quoting Peter Stuge <peter at stuge.se>:

> On Wed, Jul 04, 2007 at 09:22:54AM -0400, Joseph Smith wrote:
>> Hello,
>> Got another silly C newbie question.
>> If I want to convert a hex value to decimal, would this work?
>>
>> value = ff /* Hex value */
>>
>> sscanf(value, %d, &value)
>>
>> Is the variable "value" now 255??
>
> Hexadecimal, decimal and octal are different ways for us humans to
> express numbers to computers, but no matter what we use, they are
> always stored in binary form in the machine.
>
> Thus, there is no difference between a number in hexadecimal or
> decimal. We do however have to tell the computer which formatting we
> want when the computer should show us the numbers.
>
> unsigned char value;
>
> value=0xff; /* hexadecimal */
>
> /* %d means print number in decimal */
> printf("value in decimal is now %d\n",value);
>
>
> value=135; /* decimal */
>
> /* %x means print in hex */
> printf("value in hexadecimal is now %x\n",value);
>
>
> value=0254; /* octal */
>
> if(0xac==0254)
>   printf("C knows that 0xac == 0254 because they are both == %d\n",value);
>
>
> Have a look at the printf man page for your nearest C library to
> learn about all the good stuff you can put into formatting strings
> besides just %d and %x.
>
>
> //Peter
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>
>

Ok so how would I go about doing this is print_debug than?
Something like:

value=0xff; /* hexadecimal */

/* %d means print number in decimal */
print_debug("value in decimal is now %d\n",value);

Thanks - Joe



From joe at smittys.pointclark.net  Wed Jul  4 22:45:02 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Wed, 04 Jul 2007 16:45:02 -0400
Subject: [LinuxBIOS] i82830 raminit.c
Message-ID: <20070704164502.odgvjvgmscwwg04s@www.smittys.pointclark.net>

Ok, I think I am ready to test my i82830 raminit.c. I started this  
from the i82810 code, but I want it to be able to configure an  
assymetric dimm. If anyone has a few minutes can you check this out,  
and give me some feedback??

Thanks - Joe
-------------- next part --------------
/*
 * This file is part of the LinuxBIOS project.
 *
 * Originally written for the i82810 by:
 * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
 * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
 *
 * Modified for the i82830 by:
 * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <spd.h>
#include <sdram_mode.h>
#include <delay.h>
#include "i82830.h"

/*-----------------------------------------------------------------------------
Macros and definitions.
-----------------------------------------------------------------------------*/

/* Uncomment this to enable debugging output. */
// #define DEBUG_RAM_SETUP 1

/* Debugging macros. */
#if defined(DEBUG_RAM_SETUP)
#define PRINT_DEBUG(x)		print_debug(x)
#define PRINT_DEBUG_HEX8(x)	print_debug_hex8(x)
#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
#define PRINT_DEBUG_HEX32(x)	print_debug_hex32(x)
#define DUMPNORTH()		dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX8(x)
#define PRINT_DEBUG_HEX16(x)
#define PRINT_DEBUG_HEX32(x)
#define DUMPNORTH()
#endif

/* DRC[10:8] - Refresh Mode Select (RMS).
 * 0x1 for Refresh interval 15.6 us for 133MHz
 * 0x2 for Refresh interval 7.8 us for 133MHz
 * 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode)
 */
#define RAM_COMMAND_REFRESH    0x1

/* DRC[6:4] - SDRAM Mode Select (SMS). */
#define RAM_COMMAND_NOP		 0x1
#define RAM_COMMAND_PRECHARGE	 0x2
#define RAM_COMMAND_MRS		 0x3
#define RAM_COMMAND_CBR		 0x6
#define RAM_COMMAND_NORMAL	 0x7

/*-----------------------------------------------------------------------------
SDRAM configuration functions.
-----------------------------------------------------------------------------*/

/**
 * Send the specified RAM command to all DIMMs.
 *
 * @param Memory controller
 * @param TODO
 * @param TODO
 */
static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, uint32_t addr_offset, uint32_t row_offset) {

	uint8_t reg;

	/* TODO: Support for multiple DIMMs. */

	/* Configure the RAM command. */
	reg = pci_read_config32(ctrl->d0, DRC);
	reg &= 0xdffff88f;		/* Clear bits 29, 10-8, 6-4. */
	reg |= command << 4;
      /* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */
	if (command == RAM_COMMAND_NORMAL) {
	reg |= ((RAM_COMMAND_REFRESH << 8) | (1 << 29));
      }
	pci_write_config32(ctrl->d0, DRC, reg);

	/* RAM_COMMAND_NORMAL affects only the memory controller and
	   doesn't need to be "sent" to the DIMMs. */
	/* if (command == RAM_COMMAND_NORMAL) return; */

	PRINT_DEBUG("    Sending RAM command 0x");
	PRINT_DEBUG_HEX32(reg);
	PRINT_DEBUG(" to 0x");
	PRINT_DEBUG_HEX32(0 + addr_offset);	// FIXME
	PRINT_DEBUG("\r\n");

	/* Read from (DIMM start address + addr_offset). */
	read32(0 + addr_offset);	//first offset is always 0
	read32(row_offset + addr_offset);
}

/*-----------------------------------------------------------------------------
DIMM-independant configuration functions.
-----------------------------------------------------------------------------*/

static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
{
	unsigned dimm_mask;
	int i;
	dimm_mask = 0;
	for(i = 0; i < DIMM_SOCKETS; i++) {
		int byte;
		unsigned device;
		device = ctrl->channel0[i];
		if (device) {
			byte = spd_read_byte(device, 2);  /* Type */
			if (byte == 4) {
				dimm_mask |= (1 << i);
			}
		}
		device = ctrl->channel1[i];
		if (device) {
			byte = spd_read_byte(device, 2);
			if (byte == 4) {
				dimm_mask |= (1 << (i + DIMM_SOCKETS));
			}
		}
	}
	return dimm_mask;
}

struct dimm_size {
	unsigned long side1;
	unsigned long side2;
};

static struct dimm_size spd_get_dimm_size(unsigned device)
{
	/* Calculate the log base 2 size of a DIMM in bits */
	struct dimm_size sz;
	int value, low;
	sz.side1 = 0;
	sz.side2 = 0;

	/* test for sdram */
	value = spd_read_byte(device, 2);      /* type */
      if (value < 0) goto hw_err;
	if (value != 4) {
		print_debug("SPD2 DIMM Is Not Compatable\r\n");
		goto val_err;
	}

	/* test for PC133 (i830 only supports PC133) */
	value = spd_read_byte(device, 9);      /* cycle time */
      if (value < 0) goto hw_err;
	if (value != 75) {
		print_debug("SPD9 DIMM Is Not PC133 Compatable\r\n");
		goto val_err;
	}
	value = 0;
	value = spd_read_byte(device, 10);     /* access time */
      if (value < 0) goto hw_err;
	if (value != 54) {
		print_debug("SPD10 DIMM Is Not PC133 Compatable\r\n");
		goto val_err;
	}

	/* Note it might be easier to use byte 31 here, it has the DIMM size as
	 * a multiple of 4MB.  The way we do it now we can size both
	 * sides of an assymetric dimm.
	 */
	value = spd_read_byte(device, 3);	/* rows */
	if (value < 0) goto hw_err;
	if ((value & 0xf) == 0) {
		print_debug("SPD3 Error With Rows\r\n");
		goto val_err;
	}
	sz.side1 += value & 0xf;

	value = spd_read_byte(device, 4);	/* columns */
	if (value < 0) goto hw_err;
	if ((value & 0xf) == 0) {
		print_debug("SPD4 Error With Columns\r\n");
		goto val_err;
	}
	sz.side1 += value & 0xf;

	value = spd_read_byte(device, 17);	/* banks */
	if (value < 0) goto hw_err;
	if ((value & 0xff) == 0) {
		print_debug("SPD17 Error With Banks\r\n");
		goto val_err;
	}
	sz.side1 += log2(value & 0xff);

	/* Get the module data width and convert it to a power of two */
	value = spd_read_byte(device, 7);	/* (high byte) */
	if (value < 0) goto hw_err;
	value &= 0xff;
	value <<= 8;
	
	low = spd_read_byte(device, 6);	/* (low byte) */
	if (low < 0) goto hw_err;
	value = value | (low & 0xff);
	if ((value != 72) && (value != 64)) {
		print_debug("SPD6 Error With Data Width\r\n");
		goto val_err;
	}
	sz.side1 += log2(value);

	/* side 2 */
	value = spd_read_byte(device, 5);	/* number of physical banks */
	if (value < 0) goto hw_err;
	value &= 7;
	if (value == 1) goto out;
	if (value != 2) {
		print_debug("SPD5 Error With Physical Banks\r\n");
		goto val_err;
	}

	/* Start with the symmetrical case */
	sz.side2 = sz.side1;

	value = spd_read_byte(device, 3);	/* rows */
	if (value < 0) goto hw_err;
	if ((value & 0xf0) == 0) goto out;	/* If symmetrical we are done */
	sz.side2 -= (value & 0x0f);		/* Subtract out rows on side 1 */
	sz.side2 += ((value >> 4) & 0x0f);	/* Add in rows on side 2 */

	value = spd_read_byte(device, 4);	/* columns */
	if (value < 0) goto hw_err;
	if ((value & 0xff) == 0) {
		print_debug("SPD4 Error With Side2 Rows\r\n");
		goto val_err;
	}
	sz.side2 -= (value & 0x0f);		/* Subtract out columns on side 1 */
	sz.side2 += ((value >> 4) & 0x0f);	/* Add in columsn on side 2 */
	goto out;

 val_err:
	die("Bad SPD value\r\n");

/* If an hw_error occurs report that I have no memory */
hw_err:
	sz.side1 = 0;
	sz.side2 = 0;
 out:
	return sz;

}

static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
{
	int i;
	int cum;
	
	for(i = cum = 0; i < DIMM_SOCKETS; i++) {
		struct dimm_size sz;
		if (dimm_mask & (1 << i)) {
			sz = spd_get_dimm_size(ctrl->channel0[i]);

			/* WISHLIST: would be nice to display it as decimal? */
			print_debug("DIMM is ");
			print_debug_hex8(sz.side1);
			print_debug(" On Side 1\r\n");
			print_debug("DIMM is ");
			print_debug_hex8(sz.side2);
			print_debug(" On Side 2\r\n");

			/* Set the row offset, in KBytes (should this be
			* Kbits?). Note that this offset is the start of the
			* next row.
			*/
			row_offset = ((sz.side1 + sz.side2) * 1024);

			if (sz.side1 < 29) {
				return -1; /* Report SPD error */
			}
			/* convert bits to multiples of 64MB */
			sz.side1 -= 29;
			cum += (1 << sz.side1);
			/* DRB = 0x60 */
			pci_write_config8(ctrl->d0, DRB + (i*2), cum);
			print_debug("DRB On Side 1 ");
			print_debug_hex8(cum);
			print_debug("\r\n");
			if( sz.side2 > 28) {
				sz.side2 -= 29;
				cum += (1 << sz.side2);
			}
			pci_write_config8(ctrl->d0, DRB+1 + (i*2), cum);
			print_debug("DRB On Side 2 ");
			print_debug_hex8(cum);
			print_debug("\r\n");
		}
		else {
			pci_write_config8(ctrl->d0, DRB + (i*2), cum);
			pci_write_config8(ctrl->d0, DRB+1 + (i*2), cum);
		}
	}
	return 0;
}

static void set_dram_timing(const struct mem_controller *ctrl) {

      /* Set the value for DRAM Timing Register */
      pci_write_config32(ctrl->d0, DRT, 0x00000010);
}

static void set_dram_buffer_strength(const struct mem_controller *ctrl) {

	/* TODO: This needs to be set according to the DRAM tech
	 * (x8, x16, or x32). Argh, Intel provides no docs on this!
	 * Currently, it needs to be pulled from the output of
	 * lspci -xxx Rx92
	 */
      /* Set the value for System Memory Buffer Strength Control Registers */
      pci_write_config32(ctrl->d0, BUFF_SC0, 0x0000491B);
      pci_write_config32(ctrl->d0, BUFF_SC1, 0x00009B49);
      pci_write_config32(ctrl->d0, BUFF_SC2, 0x0000FC9B);
      pci_write_config32(ctrl->d0, BUFF_SC3, 0x000014FC);
}

/*-----------------------------------------------------------------------------
Public interface.
-----------------------------------------------------------------------------*/

/**
 * TODO.
 *
 * @param Memory controller
 */
static void sdram_set_registers(const struct mem_controller *ctrl)
{

	print_debug("Setting Initial Registers....\r\n");

      /* Set the value for PCI Command Register */
      pci_write_config16(ctrl->d0, PCICMD, 0x0006);

      /* Set the value for PCI Status Register */
      pci_write_config16(ctrl->d0, PCISTS, 0x0010);

      /* Set the value for Register Range Base Address Register */
      pci_write_config32(ctrl->d0, RRBAR, 0x00000000);

      /* Set the value for GMCH Control Register #0 */
      pci_write_config16(ctrl->d0, GCC0, 0xA072);

      /* Set the value for GMCH Control Register #1 */
      pci_write_config16(ctrl->d0, GCC1, 0x0000);

      /* Set the value for Fixed DRAM Hole Control Register */
      pci_write_config8(ctrl->d0, FDHC, 0x00);

      /* Set the value for Programable Attribute Map Registers */
	/* Ideally, this should be R/W for as many ranges as possible. */
      pci_write_config8(ctrl->d0, PAM0, 0x30);
      pci_write_config8(ctrl->d0, PAM1, 0x33);
      pci_write_config8(ctrl->d0, PAM2, 0x33);
      pci_write_config8(ctrl->d0, PAM3, 0x33);
      pci_write_config8(ctrl->d0, PAM4, 0x33);
      pci_write_config8(ctrl->d0, PAM5, 0x33);
      pci_write_config8(ctrl->d0, PAM6, 0x33);

      /* Set the value for DRAM Row Attribute Registers */
      pci_write_config8(ctrl->d0, DRA, 0xFF);
      pci_write_config8(ctrl->d0, DRA1, 0xF1);

      /* Set the value for DRAM Throttling Control Register */
      pci_write_config32(ctrl->d0, DTC, 0x00000000);

      /* Set the value for System Management RAM Control Register */
      pci_write_config8(ctrl->d0, SMRAM, 0x02);

      /* Set the value for Extended System Management RAM Control Register */
      pci_write_config8(ctrl->d0, ESMRAMC, 0x38);

      print_debug("Initial registers have been set.\r\n");
}

/**
 * TODO.
 *
 * @param Memory controller
 */
static void sdram_set_spd_registers(const struct mem_controller *ctrl) {

	/* spd_set_dram_size() moved into sdram_enable() to prevent having
	 * to pass a variable between here and there.
	 */
	set_dram_buffer_strength(ctrl);

	set_dram_timing(ctrl);
}

/**
 * Enable SDRAM.
 *
 * @param Number of controllers
 * @param Memory controller
 */
static void sdram_enable(int controllers, const struct mem_controller *ctrl) {

	int i;

	/* Todo: this will currently work with either one dual sided or two
	 * single sided DIMMs. Needs to work with 2 dual sided DIMMs in the
	 * long run.
	 */
	long mask;
	uint32_t row_offset;

	mask = spd_detect_dimms(ctrl);
	spd_set_dram_size(ctrl, mask);

	/* 1. Apply NOP. */
	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
	do_ram_command(ctrl, RAM_COMMAND_NOP, 0, row_offset);
	udelay(200);

	/* 2. Precharge all. Wait tRP. */
	PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0, row_offset);
	udelay(1);

	/* 3. Perform 8 refresh cycles. Wait tRC each time. */
	PRINT_DEBUG("RAM Enable 3: CBR\r\n");
	do_ram_command(ctrl, RAM_COMMAND_CBR, 0, row_offset);
	for (i = 0; i < 8; i++) {
		read32(0);
		read32(row_offset);
		udelay(1);
	}

	/* 4. Mode register set. Wait two memory cycles. */
	PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
	do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0, row_offset);
	udelay(2);

	/* 5. Normal operation (enables refresh) */
	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
	do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0, row_offset);
	udelay(1);

	PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
	DUMPNORTH();
}

From corey.osgood at gmail.com  Thu Jul  5 05:15:47 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 04 Jul 2007 23:15:47 -0400
Subject: [LinuxBIOS] i82830 raminit.c
In-Reply-To: <20070704164502.odgvjvgmscwwg04s@www.smittys.pointclark.net>
References: <20070704164502.odgvjvgmscwwg04s@www.smittys.pointclark.net>
Message-ID: <468C6263.9090807@gmail.com>

Joseph Smith wrote:
> Ok, I think I am ready to test my i82830 raminit.c. I started this
> from the i82810 code, but I want it to be able to configure an
> assymetric dimm. If anyone has a few minutes can you check this out,
> and give me some feedback??
>
> Thanks - Joe
> ------------------------------------------------------------------------
>
> /*
>  * This file is part of the LinuxBIOS project.
>  *
>  * Originally written for the i82810 by:
>  * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
>  * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
>  *
>  * Modified for the i82830 by:
>   

I think you can drop these, perhaps with a comment below stating you're
the one that ported it. Besides, what Uwe wrote was actually for the
i440bx...

> /* Uncomment this to enable debugging output. */
> // #define DEBUG_RAM_SETUP 1
>   

You'll probably want that uncommented before you begin testing.

> /* DRC[6:4] - SDRAM Mode Select (SMS). */
> #define RAM_COMMAND_NOP		 0x1
> #define RAM_COMMAND_PRECHARGE	 0x2
> #define RAM_COMMAND_MRS		 0x3
> #define RAM_COMMAND_CBR		 0x6
> #define RAM_COMMAND_NORMAL	 0x7
>   

Hmm, 0x0 does nothing? Even if you don't use it, just state it for
clarity's sake please.

> static struct dimm_size spd_get_dimm_size(unsigned device)
> {
> 	/* Calculate the log base 2 size of a DIMM in bits */
> 	struct dimm_size sz;
> 	int value, low;
> 	sz.side1 = 0;
> 	sz.side2 = 0;
>
> 	/* test for sdram */
> 	value = spd_read_byte(device, 2);      /* type */
>       if (value < 0) goto hw_err;
> 	if (value != 4) {
> 		print_debug("SPD2 DIMM Is Not Compatable\r\n");
> 		goto val_err;
> 	}
>
> 	/* test for PC133 (i830 only supports PC133) */
> 	value = spd_read_byte(device, 9);      /* cycle time */
>       if (value < 0) goto hw_err;
> 	if (value != 75) {
> 		print_debug("SPD9 DIMM Is Not PC133 Compatable\r\n");
> 		goto val_err;
> 	}
> 	value = 0;
> 	value = spd_read_byte(device, 10);     /* access time */
>       if (value < 0) goto hw_err;
> 	if (value != 54) {
> 		print_debug("SPD10 DIMM Is Not PC133 Compatable\r\n");
> 		goto val_err;
> 	}
>
> 	/* Note it might be easier to use byte 31 here, it has the DIMM size as
> 	 * a multiple of 4MB.  The way we do it now we can size both
> 	 * sides of an assymetric dimm.
> 	 */
> 	value = spd_read_byte(device, 3);	/* rows */
> 	if (value < 0) goto hw_err;
> 	if ((value & 0xf) == 0) {
> 		print_debug("SPD3 Error With Rows\r\n");
> 		goto val_err;
> 	}
> 	sz.side1 += value & 0xf;
>
> 	value = spd_read_byte(device, 4);	/* columns */
> 	if (value < 0) goto hw_err;
> 	if ((value & 0xf) == 0) {
> 		print_debug("SPD4 Error With Columns\r\n");
> 		goto val_err;
> 	}
> 	sz.side1 += value & 0xf;
>
> 	value = spd_read_byte(device, 17);	/* banks */
> 	if (value < 0) goto hw_err;
> 	if ((value & 0xff) == 0) {
> 		print_debug("SPD17 Error With Banks\r\n");
> 		goto val_err;
> 	}
> 	sz.side1 += log2(value & 0xff);
>
> 	/* Get the module data width and convert it to a power of two */
> 	value = spd_read_byte(device, 7);	/* (high byte) */
> 	if (value < 0) goto hw_err;
> 	value &= 0xff;
> 	value <<= 8;
> 	
> 	low = spd_read_byte(device, 6);	/* (low byte) */
> 	if (low < 0) goto hw_err;
> 	value = value | (low & 0xff);
> 	if ((value != 72) && (value != 64)) {
> 		print_debug("SPD6 Error With Data Width\r\n");
> 		goto val_err;
> 	}
> 	sz.side1 += log2(value);
>
> 	/* side 2 */
> 	value = spd_read_byte(device, 5);	/* number of physical banks */
> 	if (value < 0) goto hw_err;
> 	value &= 7;
> 	if (value == 1) goto out;
> 	if (value != 2) {
> 		print_debug("SPD5 Error With Physical Banks\r\n");
> 		goto val_err;
> 	}
>
> 	/* Start with the symmetrical case */
> 	sz.side2 = sz.side1;
>
> 	value = spd_read_byte(device, 3);	/* rows */
> 	if (value < 0) goto hw_err;
> 	if ((value & 0xf0) == 0) goto out;	/* If symmetrical we are done */
> 	sz.side2 -= (value & 0x0f);		/* Subtract out rows on side 1 */
> 	sz.side2 += ((value >> 4) & 0x0f);	/* Add in rows on side 2 */
>
> 	value = spd_read_byte(device, 4);	/* columns */
> 	if (value < 0) goto hw_err;
> 	if ((value & 0xff) == 0) {
> 		print_debug("SPD4 Error With Side2 Rows\r\n");
> 		goto val_err;
> 	}
> 	sz.side2 -= (value & 0x0f);		/* Subtract out columns on side 1 */
> 	sz.side2 += ((value >> 4) & 0x0f);	/* Add in columsn on side 2 */
> 	goto out;
>
>  val_err:
> 	die("Bad SPD value\r\n");
>
> /* If an hw_error occurs report that I have no memory */
> hw_err:
> 	sz.side1 = 0;
> 	sz.side2 = 0;
>  out:
> 	return sz;
>
> }
>   

I really, _REALLY_ don't like this, even if it does work. Reading from
spd byte 31 gives you the bank size, in units of 4mb, for both sides of
an asymetrical dimm. Please look at the spd spec (Intel or Jedec) to see
what you need to do to read it, it's a bit odd. You need to figure out
how many places the 1 is shifted, the number of places * 4mb is the size
of the bank, if the banks are asymetrical the smaller size is side2. And
if you do decide to use it anyways, please add the original copyright
holder, I think this is from e7501?

> static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
> {
> 	int i;
> 	int cum;
> 	
> 	for(i = cum = 0; i < DIMM_SOCKETS; i++) {
> 		struct dimm_size sz;
> 		if (dimm_mask & (1 << i)) {
> 			sz = spd_get_dimm_size(ctrl->channel0[i]);
>
> 			/* WISHLIST: would be nice to display it as decimal? */
> 			print_debug("DIMM is ");
> 			print_debug_hex8(sz.side1);
> 			print_debug(" On Side 1\r\n");
> 			print_debug("DIMM is ");
> 			print_debug_hex8(sz.side2);
> 			print_debug(" On Side 2\r\n");
>
> 			/* Set the row offset, in KBytes (should this be
> 			* Kbits?). Note that this offset is the start of the
> 			* next row.
> 			*/
> 			row_offset = ((sz.side1 + sz.side2) * 1024);
>   

If you're still in the initial testing stages, try to get one
single-sided dimm working first. Also, if you have a dual-sided dimm,
row_offset needs to be the address at the second side (as far as I
know), so only sz.side1 * 1024. This might be chip-dependent,
board-dependent, or I might be completely wrong...

> static void sdram_enable(int controllers, const struct mem_controller *ctrl) {
>
> 	int i;
>
> 	/* Todo: this will currently work with either one dual sided or two
> 	 * single sided DIMMs. Needs to work with 2 dual sided DIMMs in the
> 	 * long run.
> 	 */
> 	long mask;
> 	uint32_t row_offset;
>
> 	mask = spd_detect_dimms(ctrl);
> 	spd_set_dram_size(ctrl, mask);
>
> 	/* 1. Apply NOP. */
> 	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
> 	do_ram_command(ctrl, RAM_COMMAND_NOP, 0, row_offset);
>   

row_offset needs to be passed to spd_set_dram_size and set there, in the
long run. For now, just set row_offset to 0 and don't worry about it,
except possibly during MRS..might want to comment it out in
do_ram_command as well, just to be safe.

Other than that, looks good, so good luck with the testing!

-Corey



From corey.osgood at gmail.com  Thu Jul  5 05:32:51 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 04 Jul 2007 23:32:51 -0400
Subject: [LinuxBIOS] FILO and USB: Out of heap space
Message-ID: <468C6663.70804@gmail.com>

FILO is giving me the error below when using autoboot and attempting to
boot from a usb drive. I think this might be due to this board having 4
USB controllers, but I'm not really sure. The board in question is the
CN700/VT8237R board, booting the factory BIOS and then booting FILO
through grub. USB is enabled in the BIOS, EHCI is disabled, and all USB
controllers are enabled (there's no option to disable some, it's all or
none). BTW, Peter's FILO IDE speedup patch works great on this board!
This error occurs with a fresh checkout as well. I'm hoping someone with
more USB knowledge than me (which doesn't take much) can tell what's
wrong here.

Thanks,
Corey

Error log:

boot:
uda1:/vmlinuz                                                            
malloc_diag: alloc: 416 bytes (3 blocks), free: 15960 bytes (1
blocks)         
malloc_diag: alloc: 432 bytes (4 blocks), free: 15944 bytes (1
blocks)         
file_open: dev=uda1,
path=/vmlinuz                                             
LinuxLabs USB
bootloader                                                       
uhc_init: Found UHCI at
fffffd00                                               
uhc_reset: Resetting
UHCI                                                      
uhc_init: uhc_init setting framelist to:
1ddaa2d0                              
uhc_start: Starting
UHCI                                                       
dump_uhci: HCI at
fffffd00                                                     
uhc_init: Found UHCI at
fffffc00                                               
uhc_reset: Resetting
UHCI                                                      
uhc_init: uhc_init setting framelist to:
1ddaa2d0                              
uhc_start: Starting
UHCI                                                       
dump_uhci: HCI at
fffffc00                                                     
uhc_init: Found UHCI at
fffffb00                                               
uhc_reset: Resetting
UHCI                                                      
uhc_init: uhc_init setting framelist to:
1ddaa2d0                              
uhc_start: Starting
UHCI                                                       
dump_uhci: HCI at
fffffb00                                                     
uhc_init: Found UHCI at
fffffa00                                               
uhc_reset: Resetting
UHCI                                                      
uhc_init: uhc_init setting framelist to:
1ddaa2d0                              
uhc_start: Starting
UHCI                                                       
dump_uhci: HCI at
fffffa00                                                     
malloc_diag: alloc: 8632 bytes (5 blocks), free: 7744 bytes (1
blocks)         
init_framelist: frame_list is at
12e000                                        
dump_link: frame_list_link: addr:
00121db0                                     
dump_link: frame_list_link:  raw addr:
1decc080                                
dump_link: frame_list_link: terminate:
0                                       
dump_link: frame_list_link: queue:
1                                           
dump_link: frame_list_link: depth:
0                                           
Out of heap space



From stepan at coresystems.de  Thu Jul  5 05:58:18 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 5 Jul 2007 05:58:18 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070704174711.GL17746@greenwood>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
Message-ID: <20070705035818.GA310@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070704 19:47]:
> I use some aliases in my .bashrc which are pretty handy for converting
> HEX or BINARY or DECIMAL:
> 
> alias HEX="ruby -e 'printf(\"0x%X\n\", ARGV[0])'"
> alias DEC="ruby -e 'printf(\"%d\n\", ARGV[0])'"
> alias BIN="ruby -e 'printf(\"%bb\n\", ARGV[0])'"
> 
> Usage:
> 
> $ HEX 78
> 0x4E
> $ BIN 0x6a
> 1101010b
> $ DEC 0x72
> 114

cool stuff. Can it easily be fixed to convert  binary into hex or dec,
too?


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul  5 06:41:19 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 5 Jul 2007 06:41:19 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070702233236.GE8232@greenwood>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
Message-ID: <20070705044119.GA5680@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070703 01:32]:
> I don't have a strong opinion either way (as long as we don't have
> _forks_ of code for v1 and v2, which is why we now use svn:externals).
 
I like the way doing the forks as they really allow us to progress with
new code while leaving old code intact. We can still make branches of
the tree to simulate the old behavior, which is what we are going to do,
after all.

> > and i'm not sure, but i 
> > think that in some cases, the likes of uniflash can be used to flash a 
> > linuxbios too.
> 
> Definately, not everyone needs flashrom.
 
util in a seperate repo/directory is a bit hypothetic. It does not
really gain us anything. Everyone does need lar, but should we pack lar
and flashrom in the same repo because it sits in util? 

Why would someone want lar when he attempts to download flashrom?

Why would someone not download flashrom? To save how many seconds? 

> 
> > I personally don't think there should be a place in the v3 tree for a 
> > utility like this, as it leads an almost completely independent life.
> 
> Yes, and it should. The copy in v2/v3 is merely there for convenience.

There is no copy in v3?

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul  5 06:42:07 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 5 Jul 2007 06:42:07 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>
Message-ID: <20070705044207.GB5680@coresystems.de>

* ron minnich <rminnich at gmail.com> [070703 18:19]:
> I don't care where flashrom is but it is really nice if ONE co is all
> that is needed to get all you need.

I do care for flashrom, and I think it should be in v3 (using externals
or not)

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul  5 06:43:57 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 5 Jul 2007 06:43:57 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070703221029.5251.qmail@stuge.se>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>
	<20070703221029.5251.qmail@stuge.se>
Message-ID: <20070705044357.GC5680@coresystems.de>

* Peter Stuge <peter at stuge.se> [070704 00:10]:
> To have that, and get _only_ what you need when you need the
> utilities they get their own repo. I think that makes the most
> sense logically too.
> 
> I am definately for the externals so they are pulled into both v2 and
> v3 co:s too.
> 
> How does updates and commits work for the external repo-in-the-repo?
 
There is no external repository. Its just another directory in the v2
repository we are using for the external. It does not make any more
sense than it did before, except cosmetics.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul  5 06:47:27 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 5 Jul 2007 06:47:27 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070703232849.GC17746@greenwood>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<13426df10707030919r2fd3f402vb10dda92ea3eb28f@mail.gmail.com>
	<20070703221029.5251.qmail@stuge.se>
	<20070703232849.GC17746@greenwood>
Message-ID: <20070705044727.GD5680@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070704 01:28]:
> Get v2:
> svn co svn://linuxbios.org/repos/trunk/LinuxBIOSv2
> 
> Get only flashrom:
> svn co svn://linuxbios.org/repos/trunk/util/flashrom

What was wrong with:

svn co svn://linuxbios.org/repos/trunk/LinuxBIOSv2/util/flashrom

??
 
> Get everything (v2, v1, utilities, even v3 later):
> svn co svn://linuxbios.org/repos/trunk
 
Nobody will ever do that. You need utilities with every version, but not
all versions together.

> Having _different_ repositories will remove lots of advantages:
> 
>  - Common code browser (in trac) for all our code.
 
That could be fixed in trac

>  - Common bug tracking system for all code.

Is that a bug in trac?

>  - You cannot easily do, say, 'svn log' or 'svn diff -r500:600' over all
>    the code, you have to mess with _two_ repos...
> 
> The list goes on.
 
What are the advantages of the move to a different directory though? 


> Think symlinks. If you do 'cd util/flashrom' in v2 and
> change+commit things there, it'll be committed in flashrom (which is an
> svn:externals), not in v2.
 
This is very implicit magic, I hope it wont bite us.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Thu Jul  5 09:18:26 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 5 Jul 2007 09:18:26 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070705035818.GA310@coresystems.de>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070705035818.GA310@coresystems.de>
Message-ID: <20070705071825.GA5920@greenwood>

On Thu, Jul 05, 2007 at 05:58:18AM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070704 19:47]:
> > I use some aliases in my .bashrc which are pretty handy for converting
> > HEX or BINARY or DECIMAL:
> > 
> > alias HEX="ruby -e 'printf(\"0x%X\n\", ARGV[0])'"
> > alias DEC="ruby -e 'printf(\"%d\n\", ARGV[0])'"
> > alias BIN="ruby -e 'printf(\"%bb\n\", ARGV[0])'"
> > 
> > Usage:
> > 
> > $ HEX 78
> > 0x4E
> > $ BIN 0x6a
> > 1101010b
> > $ DEC 0x72
> > 114
> 
> cool stuff. Can it easily be fixed to convert  binary into hex or dec,
> too?

Yes, that works already (the syntax is a bit strange, though):

$ HEX 0b10101010
0xAA
$ DEC 0b10000011
131


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Jul  5 09:36:04 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 5 Jul 2007 09:36:04 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070705044119.GA5680@coresystems.de>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<20070705044119.GA5680@coresystems.de>
Message-ID: <20070705073604.GB5920@greenwood>

On Thu, Jul 05, 2007 at 06:41:19AM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070703 01:32]:
> > I don't have a strong opinion either way (as long as we don't have
> > _forks_ of code for v1 and v2, which is why we now use svn:externals).
>  
> I like the way doing the forks as they really allow us to progress with
> new code while leaving old code intact.

It may make sense for LinuxBIOS to "fork" as in "we don't modify v2 but
start fresh with v3" from time to time when really big changes are needed.

It does not make sense for common, independant utilities such as
flashrom. Flashrom works with v1, v2, and v3. Why should we fork it for
every version?

I'm not saying to put _all_ utilities in there, if a tool is specific to
a certain LinuxBIOS version, we should keep it in that code tree, of
course. So 'newconfig' or 'optionlist' stays in v2. Also, 'kconfig'
stays in v3, as we cannot sensibly use it in other versions (too many
local v3-specific modifications).

But common utilities should be moved to the global util/ directory.


> > > and i'm not sure, but i 
> > > think that in some cases, the likes of uniflash can be used to flash a 
> > > linuxbios too.
> > 
> > Definately, not everyone needs flashrom.
>  
> util in a seperate repo/directory is a bit hypothetic. It does not
> really gain us anything.

Yes, it does. We can put common utilities which are independent of
LinuxBIOS-versions in there.

The alternative, just having another flashrom copy in v3 (for
example), would basically fork flashrom and there's no reason to do that,
only disadvantages.


> Everyone does need lar, but should we pack lar
> and flashrom in the same repo because it sits in util? 
> 
> Why would someone want lar when he attempts to download flashrom?

You don't have that problem, you can easily get flashrom without lar:
svn co svn://linuxbios.org/repos/trunk/util/flashrom


> Why would someone not download flashrom? To save how many seconds? 

That's not the reason to do this stuff; you always get flashrom when you
download v2 as it's an svn:externals.
If we add it to v3, you'll always get flashrom when you checkout v3.


> > > I personally don't think there should be a place in the v3 tree for a 
> > > utility like this, as it leads an almost completely independent life.
> > 
> > Yes, and it should. The copy in v2/v3 is merely there for convenience.
> 
> There is no copy in v3?

Not yet. Shall we add it?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From tiansm at lemote.com  Thu Jul  5 09:59:31 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Thu, 05 Jul 2007 15:59:31 +0800
Subject: [LinuxBIOS] another question for cs5536
Message-ID: <468CA4E3.7070501@lemote.com>

Hi Marc,
    Thanks for you last reply on virtual pci config space, I finally 
find a doc on it at
http://www.amd.com/files/connectivitysolutions/geode/geode_gx/32663C_lx_gx_pciconfig.pdf 
by reading
the paper of <<Breaking the Chains?Using LinuxBIOS to Liberate Embedded 
x86 Processors>>, really thanks.

And I am curious with the irq signal of cs5536. it's said that gpio12 
can be used as a INTR_OUT of pic, I have configure the GPIO as 
out_aux1?but it's seems I have missed something, the output of gpio12 
doesn't change with some rtc interrupt occur(I can see some bit of irr 
of 8259 set).


    Thanks in advanced.

Tian




From libv at skynet.be  Thu Jul  5 11:17:15 2007
From: libv at skynet.be (Luc Verhaegen)
Date: Thu, 5 Jul 2007 11:17:15 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070705073604.GB5920@greenwood>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<20070705044119.GA5680@coresystems.de>
	<20070705073604.GB5920@greenwood>
Message-ID: <20070705091715.GA15217@skynet.be>

On Thu, Jul 05, 2007 at 09:36:04AM +0200, Uwe Hermann wrote:
> On Thu, Jul 05, 2007 at 06:41:19AM +0200, Stefan Reinauer wrote:
> > * Uwe Hermann <uwe at hermann-uwe.de> [070703 01:32]:
> > > I don't have a strong opinion either way (as long as we don't have
> > > _forks_ of code for v1 and v2, which is why we now use svn:externals).
> >  
> > I like the way doing the forks as they really allow us to progress with
> > new code while leaving old code intact.
> 
> It may make sense for LinuxBIOS to "fork" as in "we don't modify v2 but
> start fresh with v3" from time to time when really big changes are needed.
> 
> It does not make sense for common, independant utilities such as
> flashrom. Flashrom works with v1, v2, and v3. Why should we fork it for
> every version?

Plus, flashrom has its uses outside linuxbios too. It's quite a few 
orders of magnitude harder to provide linuxbios support than it is to 
provide flashrom support for any board out there.

Luc Verhaegen.



From polytan at gmail.com  Thu Jul  5 11:48:57 2007
From: polytan at gmail.com (polytan)
Date: Thu, 5 Jul 2007 11:48:57 +0200
Subject: [LinuxBIOS] MS-6391 and intel 845
Message-ID: <741f8c060707050248k64cff937x3a997afbeaf80e1d@mail.gmail.com>

Hi,

I've got a motherboard with a plcc socket and a flashrom not soldered on it.

So I'm going to by a bigger memory and put a LinuxBios on it but...is this
software supported ?

It's a quite old motherboard (it's for 1.3 - 2GHz P4 processors).

Amiti?s,

-- 

  -=( Polytan )=-
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From Libo.Feng at amd.com  Thu Jul  5 12:06:38 2007
From: Libo.Feng at amd.com (Feng, Libo)
Date: Thu, 5 Jul 2007 18:06:38 +0800
Subject: [LinuxBIOS] Machine check panic.
Message-ID: <DD1CC71B621B004FA76856E5129D6B174FECDB@sbjgexmb1.amd.com>

Hi, all,

The system I am using is: Tyan 3992, AMD Athlon64, Redhat enterprise version 4. LinuxBios is based on MSI ms9185. I encountered a Machine check panic. Who can interpret the below information. I think ADDR is a Mci_ADDR register, but what is TSC. Furthermore, I think Athlon64 should have 5 error-reporting banks, there is only 3 showing, maybe the serial port missed something, but what means 4 Bank, and what is the last long number? The attached is the whole log file. The system hung, what should I do next? Thank you.

Loading dm-zero.ko module
Loadi
CPU 0: Machine Check Exception:                4 Bank 0: 947a400000000833
TSC 45a20e904a ADDR 3fb07340

CPU 0: Machine Check Exception:                4 Bank 1: b600200000000853
TSC 45a20e957c ADDR 1d3480

CPU 0: Machine Check Exception:                4 Bank 2: d000400000000863
TSC 45a20e970a
Kernel panic - not syncing: Machine check
 ng dm-snapshot.ko module
 <<TyanLB05.txt>> 
Best Regards

??? Feng Libo @ AMD  Ext: 20906
Mobile Phone: 13683249071
Office Phone: 0086-010-62801406

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From uwe at hermann-uwe.de  Thu Jul  5 12:32:39 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 5 Jul 2007 12:32:39 +0200
Subject: [LinuxBIOS] Machine check panic.
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B174FECDB@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B174FECDB@sbjgexmb1.amd.com>
Message-ID: <20070705103239.GG5920@greenwood>

Hi,

On Thu, Jul 05, 2007 at 06:06:38PM +0800, Feng, Libo wrote:
> Hi, all,
> 
> The system I am using is: Tyan 3992, AMD Athlon64, Redhat enterprise version 4. LinuxBios is based on MSI ms9185. I encountered a Machine check panic. Who can interpret the below information. I think ADDR is a Mci_ADDR register, but what is TSC. Furthermore, I think Athlon64 should have 5 error-reporting banks, there is only 3 showing, maybe the serial port missed something, but what means 4 Bank, and what is the last long number? The attached is the whole log file. The system hung, what should I do next? Thank you.

TSC is the Time Stamp Counter register (or similar), I think.

I cannot help with your specific problem I'm afraid, but you're using a
really old kernel, please try a recent one, e.g. 2.6.21, and see if that
helps. Also, you seem to have some LVM/RAID running, maybe it's easier to
use "plain" disks for testing...

 
HTH, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From tiansm at lemote.com  Thu Jul  5 15:22:51 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Thu, 05 Jul 2007 21:22:51 +0800
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <468CA4E3.7070501@lemote.com>
References: <468CA4E3.7070501@lemote.com>
Message-ID: <468CF0AB.8020304@lemote.com>

done, there's a bug in my software, datebook is right~:)

Songmao Tian wrote:
> Hi Marc,
>     Thanks for you last reply on virtual pci config space, I finally 
> find a doc on it at
> http://www.amd.com/files/connectivitysolutions/geode/geode_gx/32663C_lx_gx_pciconfig.pdf 
> by reading
> the paper of <<Breaking the Chains?Using LinuxBIOS to Liberate Embedded 
> x86 Processors>>, really thanks.
>
> And I am curious with the irq signal of cs5536. it's said that gpio12 
> can be used as a INTR_OUT of pic, I have configure the GPIO as 
> out_aux1?but it's seems I have missed something, the output of gpio12 
> doesn't change with some rtc interrupt occur(I can see some bit of irr 
> of 8259 set).
>
>
>     Thanks in advanced.
>
> Tian
>
>
>   




From george at kami.ru  Thu Jul  5 19:48:01 2007
From: george at kami.ru (George V. Adamov)
Date: Thu, 05 Jul 2007 17:48:01 +0000
Subject: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n
	platinum)	motherboard
Message-ID: <468D2ED1.30401@kami.ru>

I have changed the config for MB.
(Actualy I took the config from Gigabyte as base, then  changed superIO 
chipset to winbond).


George.


yhlu wrote:

> it mean your mem is not initilized properly.
>
> socket AM2 or Socket F? you need to specify that in MB Config.lb
>
> YH
>




From tiansm at lemote.com  Thu Jul  5 16:34:53 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Thu, 05 Jul 2007 22:34:53 +0800
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <468CF0AB.8020304@lemote.com>
References: <468CA4E3.7070501@lemote.com> <468CF0AB.8020304@lemote.com>
Message-ID: <468D018D.7040701@lemote.com>

with regard to interrupt signal, I am still puzzled with the PCI_INTA#, 
it is said that it's a input io. Shouldn't it output the interrupt 
signal to cpu?



Songmao Tian wrote:
> done, there's a bug in my software, datebook is right~:)
>
> Songmao Tian wrote:
>   
>> Hi Marc,
>>     Thanks for you last reply on virtual pci config space, I finally 
>> find a doc on it at
>> http://www.amd.com/files/connectivitysolutions/geode/geode_gx/32663C_lx_gx_pciconfig.pdf 
>> by reading
>> the paper of <<Breaking the Chains?Using LinuxBIOS to Liberate Embedded 
>> x86 Processors>>, really thanks.
>>
>> And I am curious with the irq signal of cs5536. it's said that gpio12 
>> can be used as a INTR_OUT of pic, I have configure the GPIO as 
>> out_aux1?but it's seems I have missed something, the output of gpio12 
>> doesn't change with some rtc interrupt occur(I can see some bit of irr 
>> of 8259 set).
>>
>>
>>     Thanks in advanced.
>>
>> Tian
>>
>>
>>   
>>     
>
>
>   




From peter at stuge.se  Thu Jul  5 16:42:37 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 5 Jul 2007 16:42:37 +0200
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <468D018D.7040701@lemote.com>
References: <468CA4E3.7070501@lemote.com> <468CF0AB.8020304@lemote.com>
	<468D018D.7040701@lemote.com>
Message-ID: <20070705144237.18816.qmail@stuge.se>

On Thu, Jul 05, 2007 at 10:34:53PM +0800, Songmao Tian wrote:
> with regard to interrupt signal, I am still puzzled with the
> PCI_INTA#, it is said that it's a input io. Shouldn't it output
> the interrupt signal to cpu?

I suspect it is the signal facing PCI devices.

The signal facing the CPU is probably inside the GeodeLink somewhere.


//Peter



From joe at smittys.pointclark.net  Thu Jul  5 17:35:32 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Thu, 05 Jul 2007 11:35:32 -0400
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070705071825.GA5920@greenwood>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070705035818.GA310@coresystems.de> <20070705071825.GA5920@greenwood>
Message-ID: <20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>

Quoting Uwe Hermann <uwe at hermann-uwe.de>:

> On Thu, Jul 05, 2007 at 05:58:18AM +0200, Stefan Reinauer wrote:
>> * Uwe Hermann <uwe at hermann-uwe.de> [070704 19:47]:
>> > I use some aliases in my .bashrc which are pretty handy for converting
>> > HEX or BINARY or DECIMAL:
>> >
>> > alias HEX="ruby -e 'printf(\"0x%X\n\", ARGV[0])'"
>> > alias DEC="ruby -e 'printf(\"%d\n\", ARGV[0])'"
>> > alias BIN="ruby -e 'printf(\"%bb\n\", ARGV[0])'"
>> >
>> > Usage:
>> >
>> > $ HEX 78
>> > 0x4E
>> > $ BIN 0x6a
>> > 1101010b
>> > $ DEC 0x72
>> > 114
>>
>> cool stuff. Can it easily be fixed to convert  binary into hex or dec,
>> too?
>
> Yes, that works already (the syntax is a bit strange, though):
>
> $ HEX 0b10101010
> 0xAA
> $ DEC 0b10000011
> 131
>
>
> Uwe.

Ok so how would I go about doing this is print_debug than?
Something like:

value=0xff; /* hexadecimal */

/* %d means print number in decimal */
print_debug("value in decimal is now %d\n",value);


Thanks - Joe



From marc.jones at amd.com  Thu Jul  5 18:05:44 2007
From: marc.jones at amd.com (Marc Jones)
Date: Thu, 05 Jul 2007 10:05:44 -0600
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <20070705144237.18816.qmail@stuge.se>
References: <468CA4E3.7070501@lemote.com> <468CF0AB.8020304@lemote.com>
	<468D018D.7040701@lemote.com> <20070705144237.18816.qmail@stuge.se>
Message-ID: <468D16D8.1020207@amd.com>



Peter Stuge wrote:
> On Thu, Jul 05, 2007 at 10:34:53PM +0800, Songmao Tian wrote:
>> with regard to interrupt signal, I am still puzzled with the
>> PCI_INTA#, it is said that it's a input io. Shouldn't it output
>> the interrupt signal to cpu?
> 
> I suspect it is the signal facing PCI devices.
> 
> The signal facing the CPU is probably inside the GeodeLink somewhere.
> 
> 
> //Peter
> 

Peter is correct. The PCI_INTA# from the CPU(northbridge) to the cs5536 
is for graphics and/or AES egine interrupts. The interrupt signal(INTR#) 
from the cs5536 to the CPU is in the sideband serial packet.  Look for 
"CPU Interface Serial (CIS)" in the 5536 databook for more information.

Marc


-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From joe at smittys.pointclark.net  Thu Jul  5 18:12:38 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Thu, 05 Jul 2007 12:12:38 -0400
Subject: [LinuxBIOS] i82830 raminit.c
In-Reply-To: <468C6263.9090807@gmail.com>
References: <20070704164502.odgvjvgmscwwg04s@www.smittys.pointclark.net>
	<468C6263.9090807@gmail.com>
Message-ID: <20070705121238.nzex9ztjsc04cc0s@www.smittys.pointclark.net>

Thanks for the feedback Corey. I have a few questions / comments.
>
>
>> /* DRC[6:4] - SDRAM Mode Select (SMS). */
>> #define RAM_COMMAND_NOP		 0x1
>> #define RAM_COMMAND_PRECHARGE	 0x2
>> #define RAM_COMMAND_MRS		 0x3
>> #define RAM_COMMAND_CBR		 0x6
>> #define RAM_COMMAND_NORMAL	 0x7
>>
>
> Hmm, 0x0 does nothing? Even if you don't use it, just state it for
> clarity's sake please.

What would I define 0x0 as?


>
>> static struct dimm_size spd_get_dimm_size(unsigned device)
>> {
>> 	/* Calculate the log base 2 size of a DIMM in bits */
>> 	struct dimm_size sz;
>> 	int value, low;
>> 	sz.side1 = 0;
>> 	sz.side2 = 0;
>>
>> 	/* test for sdram */
>> 	value = spd_read_byte(device, 2);      /* type */
>>       if (value < 0) goto hw_err;
>> 	if (value != 4) {
>> 		print_debug("SPD2 DIMM Is Not Compatable\r\n");
>> 		goto val_err;
>> 	}
>>
>> 	/* test for PC133 (i830 only supports PC133) */
>> 	value = spd_read_byte(device, 9);      /* cycle time */
>>       if (value < 0) goto hw_err;
>> 	if (value != 75) {
>> 		print_debug("SPD9 DIMM Is Not PC133 Compatable\r\n");
>> 		goto val_err;
>> 	}
>> 	value = 0;
>> 	value = spd_read_byte(device, 10);     /* access time */
>>       if (value < 0) goto hw_err;
>> 	if (value != 54) {
>> 		print_debug("SPD10 DIMM Is Not PC133 Compatable\r\n");
>> 		goto val_err;
>> 	}
>>
>> 	/* Note it might be easier to use byte 31 here, it has the DIMM size as
>> 	 * a multiple of 4MB.  The way we do it now we can size both
>> 	 * sides of an assymetric dimm.
>> 	 */
>> 	value = spd_read_byte(device, 3);	/* rows */
>> 	if (value < 0) goto hw_err;
>> 	if ((value & 0xf) == 0) {
>> 		print_debug("SPD3 Error With Rows\r\n");
>> 		goto val_err;
>> 	}
>> 	sz.side1 += value & 0xf;
>>
>> 	value = spd_read_byte(device, 4);	/* columns */
>> 	if (value < 0) goto hw_err;
>> 	if ((value & 0xf) == 0) {
>> 		print_debug("SPD4 Error With Columns\r\n");
>> 		goto val_err;
>> 	}
>> 	sz.side1 += value & 0xf;
>>
>> 	value = spd_read_byte(device, 17);	/* banks */
>> 	if (value < 0) goto hw_err;
>> 	if ((value & 0xff) == 0) {
>> 		print_debug("SPD17 Error With Banks\r\n");
>> 		goto val_err;
>> 	}
>> 	sz.side1 += log2(value & 0xff);
>>
>> 	/* Get the module data width and convert it to a power of two */
>> 	value = spd_read_byte(device, 7);	/* (high byte) */
>> 	if (value < 0) goto hw_err;
>> 	value &= 0xff;
>> 	value <<= 8;
>>
>> 	low = spd_read_byte(device, 6);	/* (low byte) */
>> 	if (low < 0) goto hw_err;
>> 	value = value | (low & 0xff);
>> 	if ((value != 72) && (value != 64)) {
>> 		print_debug("SPD6 Error With Data Width\r\n");
>> 		goto val_err;
>> 	}
>> 	sz.side1 += log2(value);
>>
>> 	/* side 2 */
>> 	value = spd_read_byte(device, 5);	/* number of physical banks */
>> 	if (value < 0) goto hw_err;
>> 	value &= 7;
>> 	if (value == 1) goto out;
>> 	if (value != 2) {
>> 		print_debug("SPD5 Error With Physical Banks\r\n");
>> 		goto val_err;
>> 	}
>>
>> 	/* Start with the symmetrical case */
>> 	sz.side2 = sz.side1;
>>
>> 	value = spd_read_byte(device, 3);	/* rows */
>> 	if (value < 0) goto hw_err;
>> 	if ((value & 0xf0) == 0) goto out;	/* If symmetrical we are done */
>> 	sz.side2 -= (value & 0x0f);		/* Subtract out rows on side 1 */
>> 	sz.side2 += ((value >> 4) & 0x0f);	/* Add in rows on side 2 */
>>
>> 	value = spd_read_byte(device, 4);	/* columns */
>> 	if (value < 0) goto hw_err;
>> 	if ((value & 0xff) == 0) {
>> 		print_debug("SPD4 Error With Side2 Rows\r\n");
>> 		goto val_err;
>> 	}
>> 	sz.side2 -= (value & 0x0f);		/* Subtract out columns on side 1 */
>> 	sz.side2 += ((value >> 4) & 0x0f);	/* Add in columsn on side 2 */
>> 	goto out;
>>
>>  val_err:
>> 	die("Bad SPD value\r\n");
>>
>> /* If an hw_error occurs report that I have no memory */
>> hw_err:
>> 	sz.side1 = 0;
>> 	sz.side2 = 0;
>>  out:
>> 	return sz;
>>
>> }
>>
>
> I really, _REALLY_ don't like this, even if it does work. Reading from
> spd byte 31 gives you the bank size, in units of 4mb, for both sides of
> an asymetrical dimm. Please look at the spd spec (Intel or Jedec) to see
> what you need to do to read it, it's a bit odd. You need to figure out
> how many places the 1 is shifted, the number of places * 4mb is the size
> of the bank, if the banks are asymetrical the smaller size is side2. And
> if you do decide to use it anyways, please add the original copyright
> holder, I think this is from e7501?
>
Your right, I don't really feel the above method is necessary. The  
only problem is this with Byte 31:

# Banks Density of Bank 1 Density of bank 2 Byte 31 contents
1       32MByte           N/A               0000 1000
2       32MByte           32MBbyte          0000 1000
2       32MByte           16MByte           0000 1100

You can see Byte 31 contents are going to be the same when the density  
is the same no matter how many banks it has. Could this pottentially  
give a false reading?? You could also use Byte 5 to determine the  
banks. Could we say something like; if byte 5 has 1 bank than byte 31  
is correct and if byte 5 has 2 banks to muliply byte 31 by 2?? But  
what about the third example above when you have more than 1 bank and  
the densities are different??

>> static long spd_set_ram_size(const struct mem_controller *ctrl,   
>> long dimm_mask)
>> {
>> 	int i;
>> 	int cum;
>>
>> 	for(i = cum = 0; i < DIMM_SOCKETS; i++) {
>> 		struct dimm_size sz;
>> 		if (dimm_mask & (1 << i)) {
>> 			sz = spd_get_dimm_size(ctrl->channel0[i]);
>>
>> 			/* WISHLIST: would be nice to display it as decimal? */
>> 			print_debug("DIMM is ");
>> 			print_debug_hex8(sz.side1);
>> 			print_debug(" On Side 1\r\n");
>> 			print_debug("DIMM is ");
>> 			print_debug_hex8(sz.side2);
>> 			print_debug(" On Side 2\r\n");
>>
>> 			/* Set the row offset, in KBytes (should this be
>> 			* Kbits?). Note that this offset is the start of the
>> 			* next row.
>> 			*/
>> 			row_offset = ((sz.side1 + sz.side2) * 1024);
>>
>
> If you're still in the initial testing stages, try to get one
> single-sided dimm working first. Also, if you have a dual-sided dimm,
> row_offset needs to be the address at the second side (as far as I
> know), so only sz.side1 * 1024. This might be chip-dependent,
> board-dependent, or I might be completely wrong...
>
My test board has 128MB on-board, Remember this is a set-top-box. To  
the registry, with the stock bios it shows up as a sindle sided  
so-dimm in socket 2. Initially I could just hardcode alot of this but  
I would like to make it versitial and have the ability to use socket 1  
also. Alot of Laptops use this chip also, so this could open up  
LinuxBios to that front.

Thanks Again - Joe



From tsylla at gmail.com  Thu Jul  5 18:14:55 2007
From: tsylla at gmail.com (Tom Sylla)
Date: Thu, 5 Jul 2007 09:14:55 -0700
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <468D018D.7040701@lemote.com>
References: <468CA4E3.7070501@lemote.com> <468CF0AB.8020304@lemote.com>
	<468D018D.7040701@lemote.com>
Message-ID: <57947bf80707050914l61b6c96cybb031f952c7a1abc@mail.gmail.com>

On 7/5/07, Songmao Tian <tiansm at lemote.com> wrote:
> with regard to interrupt signal, I am still puzzled with the PCI_INTA#,
> it is said that it's a input io. Shouldn't it output the interrupt
> signal to cpu?

On 5536, the PCI_INT{A,B,C,D}# signals are usually configured as
inputs. (they are all just part of the GPIO block). Those signals then
get mapped into the interrupt logic through the various IRQ mapping
MSRs.

Interrupt delivery to the processor is done on the "CIS" pin that is
an output from 5536 to the GX or LX processor. The CIS pin delivers
IRQ, SMI, NMI, etc in a serial stream to the CPU. (the CPU
de-serializes it, and has internal versions of those signals)

Your goal seems to be to mux 5536's internal INTR signal out onto a
GPIO. There are some hints about that in the datasheet, but that is
not an official way to do it. Normal Geode systems all use the serial
packet. You will probably not get any support from AMD to do it that
way, that path is not tested. (though I have seen it work)



From svn at openbios.org  Thu Jul  5 18:58:10 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  5 Jul 2007 18:58:10 +0200
Subject: [LinuxBIOS] r433 - in LinuxBIOSv3: arch/x86 arch/x86/geodelx
	include/arch/x86
Message-ID: <mailman.499.1355071130.16123.coreboot@coreboot.org>

Author: mjones
Date: 2007-07-05 18:58:10 +0200 (Thu, 05 Jul 2007)
New Revision: 433

Added:
   LinuxBIOSv3/include/arch/x86/legacy.h
Modified:
   LinuxBIOSv3/arch/x86/geodelx/geodelx.c
   LinuxBIOSv3/arch/x86/speaker.c
Log:
Moved some generic 8254 PIT #defines out of the speaker code to legacy.h.
Use legacy.h PIT defines in Geode code.

Signed-off-by: Marc Jones <marc.jones at amd.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 20:33:33 UTC (rev 432)
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-05 16:58:10 UTC (rev 433)
@@ -30,6 +30,7 @@
 #include <io.h>
 #include <amd_geodelx.h>
 #include <spd.h>
+#include <legacy.h>
 
 /* all these functions used to be in a lot of fiddly little files.  To
   * make it easier to find functions, we are merging them here. This
@@ -41,8 +42,6 @@
 
 /** 
   * Starts Timer 1 for port 61 use.
-  * 0x43 is PIT command/control.
-  * 0x41 is PIT counter 1.
   *
   * The command 0x56 means write counter 1 lower 8 bits in next IO,
   * set the counter mode to square wave generator (count down to 0
@@ -58,8 +57,8 @@
   */
 void start_timer1(void)
 {
-	outb(0x56, 0x43);
-	outb(0x12, 0x41);
+	outb(0x56, I82C54_CONTROL_WORD_REGISTER);
+	outb(0x12, I82C54_COUNTER1);
 }
 
 /** 

Modified: LinuxBIOSv3/arch/x86/speaker.c
===================================================================
--- LinuxBIOSv3/arch/x86/speaker.c	2007-07-03 20:33:33 UTC (rev 432)
+++ LinuxBIOSv3/arch/x86/speaker.c	2007-07-05 16:58:10 UTC (rev 433)
@@ -27,13 +27,8 @@
 
 #include <io.h>
 #include <lib.h>
+#include <legacy.h>
 
-#define I82C54_CONTROL_WORD_REGISTER	0x43	/* Write-only. */
-
-#define I82C54_COUNTER0			0x40
-#define I82C54_COUNTER1			0x41
-#define I82C54_COUNTER2			0x42
-
 #define PC_SPEAKER_PORT			0x61
 
 /**

Added: LinuxBIOSv3/include/arch/x86/legacy.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/legacy.h	                        (rev 0)
+++ LinuxBIOSv3/include/arch/x86/legacy.h	2007-07-05 16:58:10 UTC (rev 433)
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Datasheet:
+ *  - Name: 82C54 CHMOS Programmable Interval Timer
+ *  - PDF: http://www.intel.com/design/archives/periphrl/docs/23124406.pdf
+ *  - Order number: 231244-006
+ *
+ * See also:
+ *  - http://en.wikipedia.org/wiki/Intel_8253
+ */
+
+#define I82C54_CONTROL_WORD_REGISTER	0x43	/* Write-only. */
+#define I82C54_COUNTER0			0x40
+#define I82C54_COUNTER1			0x41
+#define I82C54_COUNTER2			0x42




From marc.jones at amd.com  Thu Jul  5 19:12:11 2007
From: marc.jones at amd.com (Marc Jones)
Date: Thu, 05 Jul 2007 11:12:11 -0600
Subject: [LinuxBIOS] [Fwd: Re:  [PATCH] v3: 8254_pit.patch]
Message-ID: <468D266B.80303@amd.com>

An embedded message was scrubbed...
From: "Marc Jones" <marc.jones at amd.com>
Subject: Re: [LinuxBIOS] [PATCH] v3: 8254_pit.patch
Date: Thu, 05 Jul 2007 10:58:36 -0600
Size: 1282
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20070705/04da7c7a/attachment.mht>

From yinghailu at gmail.com  Thu Jul  5 19:13:46 2007
From: yinghailu at gmail.com (yhlu)
Date: Thu, 5 Jul 2007 10:13:46 -0700
Subject: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n platinum)
	motherboard
In-Reply-To: <468D2ED1.30401@kami.ru>
References: <468D2ED1.30401@kami.ru>
Message-ID: <2ea3fae10707051013j63888d14n729d65cc8bcd9016@mail.gmail.com>

On 7/5/07, George V. Adamov <george at kami.ru> wrote:
> I have changed the config for MB.
> (Actualy I took the config from Gigabyte as base, then  changed superIO
> chipset to winbond).

are you using tar ball i sent or from public tree?

YH



From svn at openbios.org  Thu Jul  5 19:27:24 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  5 Jul 2007 19:27:24 +0200
Subject: [LinuxBIOS] r434 - in LinuxBIOSv3: . util/xcompile
Message-ID: <mailman.500.1355071130.16123.coreboot@coreboot.org>

Author: mjones
Date: 2007-07-05 19:27:23 +0200 (Thu, 05 Jul 2007)
New Revision: 434

Modified:
   LinuxBIOSv3/Makefile
   LinuxBIOSv3/util/xcompile/xcompile
Log:
Add testcc() function to xcompile to check for various compiler flags and set them in the CFLAGS variable if they are located.
Added check for -fno-stack-protector flag.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Marc Jones <marc.jones at amd.com>



Modified: LinuxBIOSv3/Makefile
===================================================================
--- LinuxBIOSv3/Makefile	2007-07-05 16:58:10 UTC (rev 433)
+++ LinuxBIOSv3/Makefile	2007-07-05 17:27:23 UTC (rev 434)
@@ -96,6 +96,7 @@
 AS := $(AS_$(ARCH))
 LD := $(LD_$(ARCH))
 OBJCOPY := $(OBJCOPY_$(ARCH))
+CFLAGS += $(CFLAGS_$(ARCH))
 
 CPPFLAGS := $(LINUXBIOSINCLUDE)
 CFLAGS += $(LINUXBIOSINCLUDE)

Modified: LinuxBIOSv3/util/xcompile/xcompile
===================================================================
--- LinuxBIOSv3/util/xcompile/xcompile	2007-07-05 16:58:10 UTC (rev 433)
+++ LinuxBIOSv3/util/xcompile/xcompile	2007-07-05 17:27:23 UTC (rev 434)
@@ -25,6 +25,15 @@
 			-e s/s390x/s390/ -e s/parisc64/parisc/ \
 			-e s/ppc.*/powerpc/ -e s/mips.*/mips/`
 
+testcc()
+{
+	TMP=".$$$$.tmp"
+	$1 $2 -S -xc /dev/null -o $TMP > /dev/null 2>&1
+	ret=$?
+	rm -rf $TMP
+	return $ret 
+}
+
 searchgnu()
 {
 	# $1 short name
@@ -45,18 +54,23 @@
 case  "$ARCH" in
 "x86_64")
 	echo "CC_x86 := gcc -m32"
+	CC="gcc -m32"
+
 	searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as) --32"
 	searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld) -b elf32-i386 -melf_i386"
 	searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)"
 	;;
 "x86")
 	echo "CC_x86 := gcc"
+	CC="gcc"
+
 	searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as)"
 	searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld)"
 	searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)"
 	;;
 *)
 	# FIXME: This should be detected.
+	CC="i386-linux-gcc"
 	echo "CC_x86 := i386-linux-gcc"
 	echo "AS_x86 := i386-linux-as"
 	echo "LD_x86 := i386-linux-ld"
@@ -64,6 +78,13 @@
 	;;
 esac
 
+# This is where we test for various flags and other things
+
+CFLAGS=""
+testcc "$CC" "-fno-stack-protector" && CFLAGS="$CFLAGS-fno-stack-protector " 
+
+echo "CFLAGS_x86 := $CFLAGS"
+
 # TODO: The same as above for PowerPC, and other architectures
 #       as soon as they are supported by LinuxBIOSv3.
 




From marc.jones at amd.com  Thu Jul  5 19:30:04 2007
From: marc.jones at amd.com (Marc Jones)
Date: Thu, 05 Jul 2007 11:30:04 -0600
Subject: [LinuxBIOS] Add automagic detection for -fno-stack-protector
In-Reply-To: <20070704180154.GN17746@greenwood>
References: <20070702233843.GG14253@cosmic.amd.com>
	<20070703030143.GB22459@coresystems.de>
	<20070703220634.GB17746@greenwood>
	<20070703223603.GA14935@cosmic.amd.com>
	<20070704180154.GN17746@greenwood>
Message-ID: <468D2A9C.2070909@amd.com>



Uwe Hermann wrote:
> On Tue, Jul 03, 2007 at 04:36:03PM -0600, Jordan Crouse wrote:
>> [PATCH][v3]  Add testcc() function to xcompile to check for -fno-stack-protector
>>
>> enable xcompile to check for various compiler flags and set them in the 
>> CFLAGS variable if they are located.
>>
>> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
> 
> Looks good, and works for me (but I cannot test the case where
> -fno-stack-protector is actually needed, my setup doesn't require it).
> 
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
>  
> Uwe.
> 
Acked-by: Marc Jones <marc.jones at amd.com>

r434

Thanks,
Marc

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From marc.jones at amd.com  Thu Jul  5 22:21:25 2007
From: marc.jones at amd.com (Marc Jones)
Date: Thu, 05 Jul 2007 14:21:25 -0600
Subject: [LinuxBIOS] Geode delay control setting cleanup
Message-ID: <468D52C5.1020105@amd.com>

Last week Peter commented that the delay control setting code should be 
made clearer. Here is what I came up with. I think that it makes more 
sense now.

Marc

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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From yinghailu at gmail.com  Thu Jul  5 22:48:00 2007
From: yinghailu at gmail.com (yhlu)
Date: Thu, 5 Jul 2007 13:48:00 -0700
Subject: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n platinum)
	motherboard
In-Reply-To: <468D2ED1.30401@kami.ru>
References: <468D2ED1.30401@kami.ru>
Message-ID: <2ea3fae10707051348o5676e858i438adfef51f5a1e1@mail.gmail.com>

gcc version?
try 4.0.2 or 4.1.2 please.

YH



From peter at stuge.se  Thu Jul  5 23:48:13 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 5 Jul 2007 23:48:13 +0200
Subject: [LinuxBIOS] Geode delay control setting cleanup
In-Reply-To: <468D52C5.1020105@amd.com>
References: <468D52C5.1020105@amd.com>
Message-ID: <20070705214813.20663.qmail@stuge.se>

On Thu, Jul 05, 2007 at 02:21:25PM -0600, Marc Jones wrote:
> Rework the Geode delay control setup to table driven and much more
> readable.

Wow, what a difference!


> Signed-off-by: Marc Jones <marc.jones at amd.com>

Acked-by: Peter Stuge <peter at stuge.se>



From uwe at hermann-uwe.de  Fri Jul  6 02:05:47 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 6 Jul 2007 02:05:47 +0200
Subject: [LinuxBIOS] [PATCH][v3] Spinlock fixes
Message-ID: <20070706000547.GD13756@greenwood>

See patch.

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Jul  6 02:27:34 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 6 Jul 2007 02:27:34 +0200
Subject: [LinuxBIOS] Geode delay control setting cleanup
In-Reply-To: <468D52C5.1020105@amd.com>
References: <468D52C5.1020105@amd.com>
Message-ID: <20070706002732.GE13756@greenwood>

On Thu, Jul 05, 2007 at 02:21:25PM -0600, Marc Jones wrote:
> Last week Peter commented that the delay control setting code should be 
> made clearer. Here is what I came up with. I think that it makes more sense 
> now.

Yep, great stuff! We need more patches of this type!


> Index: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
> ===================================================================
> --- LinuxBIOSv3.orig/arch/x86/geodelx/geodelx.c	2007-07-03 18:20:19.000000000 -0600
> +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-03 17:40:27.000000000 -0600
> @@ -247,6 +247,54 @@
>  	}
>  }
>  
> +
> +/**
> + * Delay Control Settings Table from AMD (MCP 0x4C00000F)
> + * DIMMs	devices	  Slow (<=333MHz)         Fast (>334MHz)
> + * -----	-------	 ----------------------	 ----------------------
> + *  1		4		 0x83*100FF 0x56960004	 0x82*100FF 0x56960004
> + *  1		8		 0x83*100AA 0x56960004	 0x82*100AA 0x56960004
> + *  1		16		 0x83*100AA 0x56960004	 0x82*10055 0x56960004
                                             ^
                                     Why "*" here?

This table is mostly identical to the struct/table below. If it's really
intended to be the same, I'd rather drop it (no duplication of
information if we can avoid it). If there's something important in
there, rather add a comment to the struct below...


> + *
> + *  2		8		 0x837100A5 0x56960004	 0x82710000 0x56960004
> + *  2		16		 0x937100A5 0x56960004	 0xC27100A5 0x56960004
> + *  2		20		 0xB37100A5 0x56960004	 0xB27100A5 0x56960004
> + *  2		24		 0xB37100A5 0x56960004	 0xB27100A5 0x56960004
> + *  2		32		 0xB37100A5 0x56960004	 0xB2710000 0x56960004
> + *
> + * =========================================================================
> + * - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
> + *     in slot 0, but it should be clear for all 2 DIMM settings and if a
> + *     single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
> + *
> + * Settings for single DIMM and no VTT termination (Like db800 platform)
> + *   0xF2F100FF 0x56960004
> + * -------------------------------------
> + * ADDR/CTL have 22 ohm series R
> + * DQ/DQM/DQS have 33 ohm series R
> +*/
> +
> +struct delay_controls {
> +	u8 dimms;
> +	u8 devices;
> +	u32 slow_hi;
> +	u32 slow_low;
> +	u32 fast_hi;
> +	u32 fast_low;
> +};
> +
> +const struct delay_controls delay_control_table [] = {
> +/* DIMMs	devices	Slow (<=333MHz)				Fast (>334MHz)*/
> +{	1,		4,		0x0837100FF, 0x056960004,	0x0827100FF, 0x056960004},
> +{	1,		8,		0x0837100AA, 0x056960004,	0x0827100AA, 0x056960004},
> +{	1,		16,		0x0837100AA, 0x056960004,	0x082710055, 0x056960004},
> +{	2,		8,		0x0837100A5, 0x056960004,	0x082710000, 0x056960004},
> +{	2,		16,		0x0937100A5, 0x056960004,	0x0C27100A5, 0x056960004},
> +{	2,		20,		0x0B37100A5, 0x056960004,	0x0B27100A5, 0x056960004},
> +{	2,		24,		0x0B37100A5, 0x056960004,	0x0B27100A5, 0x056960004},
> +{	2,		32,		0x0B37100A5, 0x056960004,	0x0B2710000, 0x056960004}
> +};

As the stuct is only used once, you can do something like this, I think:

const struct delay_controls {
	u8 dimms;
	u8 devices;
	u32 slow_hi;
	u32 slow_low;
	u32 fast_hi;
	u32 fast_low;
} delay_control_table [] = {
	/* DIMMs Devs Slow (<=333MHz)            Fast (>334MHz) */
	{ 1,     4,   0x0837100FF, 0x056960004,  0x0827100FF, 0x056960004 },
	{ 1,     8,   0x0837100AA, 0x056960004,  0x0827100AA, 0x056960004 },
	{ 1,     16,  0x0837100AA, 0x056960004,  0x082710055, 0x056960004 },
	{ 2,     8,   0x0837100A5, 0x056960004,  0x082710000, 0x056960004 },
	{ 2,     16,  0x0937100A5, 0x056960004,  0x0C27100A5, 0x056960004 },
	{ 2,     20,  0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
	{ 2,     24,  0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
	{ 2,     32,  0x0B37100A5, 0x056960004,  0x0B2710000, 0x056960004 },
};

(note that I reformatted the table (mostly by using spaces for alignment) to
fit in 79 chars/line)

You may have to drop the 'const', not sure (this is untested).


> +
>  /**
>   * set_delay_control. This is Black Magic DRAM timing
>   * juju(http://www.thefreedictionary.com/juju) Dram delay depends on
> @@ -263,12 +311,10 @@
>   * @param dimm1 DIMM 1 SMBus address
>   * @param sram_width Data width of the SDRAM
>   */
> -
>  void set_delay_control(u8 dimm0, u8 dimm1)
>  {
>  	u32 msrnum, glspeed;
> -	u8 spdbyte0, spdbyte1;
> -	int numdimms = 0;
> +	u8 spdbyte0, spdbyte1, dimms, i;

Is this safe? The 'dimms' variable is not set to zero anymore?


> +	/* save some power, disable clock to second DIMM if it is empty */
> +	if (spdbyte1 == 0) {
> +		msr.hi |= 0x000800000;

Not critical, but maybe it makes sense to make this a #define, too?


> +	}
> +
> +	spdbyte0 += spdbyte1;
> +
> +	for(i = 0; i < ARRAY_SIZE(delay_control_table); i++){
           ^                                                ^
         space                                            space

> +		if((dimms == delay_control_table[i].dimms) &&
                  ^
                 space

> +				(spdbyte0 <= delay_control_table[i].devices)) {
>  			if (glspeed < 334) {
> -				msr.hi |= 0x0837100A5;
> -				msr.lo |= 0x056960004;
> +				msr.hi |= delay_control_table[i].slow_hi;
> +				msr.lo |= delay_control_table[i].slow_low;
>  			} else {
> -				msr.hi |= 0x082710000;
> -				msr.lo |= 0x056960004;
> +				msr.hi |= delay_control_table[i].fast_hi;
> +				msr.lo |= delay_control_table[i].fast_low;


Great patch!

With the above issues fixed:

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From tiansm at lemote.com  Fri Jul  6 02:37:20 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Fri, 06 Jul 2007 08:37:20 +0800
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <468D16D8.1020207@amd.com>
References: <468CA4E3.7070501@lemote.com>
	<468CF0AB.8020304@lemote.com>	<468D018D.7040701@lemote.com>
	<20070705144237.18816.qmail@stuge.se> <468D16D8.1020207@amd.com>
Message-ID: <468D8EC0.6060402@lemote.com>

Marc Jones wrote:
> Peter Stuge wrote:
>   
>> On Thu, Jul 05, 2007 at 10:34:53PM +0800, Songmao Tian wrote:
>>     
>>> with regard to interrupt signal, I am still puzzled with the
>>> PCI_INTA#, it is said that it's a input io. Shouldn't it output
>>> the interrupt signal to cpu?
>>>       
>> I suspect it is the signal facing PCI devices.
>>
>> The signal facing the CPU is probably inside the GeodeLink somewhere.
>>
>>
>> //Peter
>>
>>     
>
> Peter is correct. The PCI_INTA# from the CPU(northbridge) to the cs5536 
> is for graphics and/or AES egine interrupts. The interrupt signal(INTR#) 
> from the cs5536 to the CPU is in the sideband serial packet.  Look for 
> "CPU Interface Serial (CIS)" in the 5536 databook for more information.
>
> Marc
>
>
>   

I got it:), I suspect that, but I haven't notice the that there's pci 
devices in northbridge.
thanks Marc, thanks Peter.





From uwe at hermann-uwe.de  Fri Jul  6 02:46:44 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 6 Jul 2007 02:46:44 +0200
Subject: [LinuxBIOS] i82830 raminit.c
In-Reply-To: <20070705121238.nzex9ztjsc04cc0s@www.smittys.pointclark.net>
References: <20070704164502.odgvjvgmscwwg04s@www.smittys.pointclark.net>
	<468C6263.9090807@gmail.com>
	<20070705121238.nzex9ztjsc04cc0s@www.smittys.pointclark.net>
Message-ID: <20070706004644.GF13756@greenwood>

On Thu, Jul 05, 2007 at 12:12:38PM -0400, Joseph Smith wrote:
> >> /* DRC[6:4] - SDRAM Mode Select (SMS). */
> >> #define RAM_COMMAND_NOP		 0x1
> >> #define RAM_COMMAND_PRECHARGE	 0x2
> >> #define RAM_COMMAND_MRS		 0x3
> >> #define RAM_COMMAND_CBR		 0x6
> >> #define RAM_COMMAND_NORMAL	 0x7
> >
> > Hmm, 0x0 does nothing? Even if you don't use it, just state it for
> > clarity's sake please.
> 
> What would I define 0x0 as?

Check the datasheet (is it publically available?). The description
should be where the DRC register is described, I guess.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From tiansm at lemote.com  Fri Jul  6 02:55:37 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Fri, 06 Jul 2007 08:55:37 +0800
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <57947bf80707050914l61b6c96cybb031f952c7a1abc@mail.gmail.com>
References: <468CA4E3.7070501@lemote.com> <468CF0AB.8020304@lemote.com>	
	<468D018D.7040701@lemote.com>
	<57947bf80707050914l61b6c96cybb031f952c7a1abc@mail.gmail.com>
Message-ID: <468D9309.70200@lemote.com>

Tom Sylla wrote:
> On 7/5/07, Songmao Tian <tiansm at lemote.com> wrote:
>> with regard to interrupt signal, I am still puzzled with the PCI_INTA#,
>> it is said that it's a input io. Shouldn't it output the interrupt
>> signal to cpu?
>
> On 5536, the PCI_INT{A,B,C,D}# signals are usually configured as
> inputs. (they are all just part of the GPIO block). Those signals then
> get mapped into the interrupt logic through the various IRQ mapping
> MSRs.
>
> Interrupt delivery to the processor is done on the "CIS" pin that is
> an output from 5536 to the GX or LX processor. The CIS pin delivers
> IRQ, SMI, NMI, etc in a serial stream to the CPU. (the CPU
> de-serializes it, and has internal versions of those signals)
>
> Your goal seems to be to mux 5536's internal INTR signal out onto a
> GPIO. There are some hints about that in the datasheet, but that is
> not an official way to do it. Normal Geode systems all use the serial
> packet. You will probably not get any support from AMD to do it that
> way, that path is not tested. (though I have seen it work)
>
>
Actually, we are using a non-Geode CPU(in fact it's a mips varient). I 
understand the situation, luckily I got
helps from all of you:), thanks again.

Perhaps I will try to port the LinuxBIOS, but if so, I have to port 
another payload(I am looking into grub2, any other sugguestion?)

and u-boot is another good option.







From corey.osgood at gmail.com  Fri Jul  6 03:57:25 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 05 Jul 2007 21:57:25 -0400
Subject: [LinuxBIOS] i82830 raminit.c
In-Reply-To: <20070705121238.nzex9ztjsc04cc0s@www.smittys.pointclark.net>
References: <20070704164502.odgvjvgmscwwg04s@www.smittys.pointclark.net>	<468C6263.9090807@gmail.com>
	<20070705121238.nzex9ztjsc04cc0s@www.smittys.pointclark.net>
Message-ID: <468DA185.5060206@gmail.com>

Joseph Smith wrote:

<snip>
>> I really, _REALLY_ don't like this, even if it does work. Reading from
>> spd byte 31 gives you the bank size, in units of 4mb, for both sides of
>> an asymetrical dimm. Please look at the spd spec (Intel or Jedec) to see
>> what you need to do to read it, it's a bit odd. You need to figure out
>> how many places the 1 is shifted, the number of places * 4mb is the size
>> of the bank, if the banks are asymetrical the smaller size is side2. And
>> if you do decide to use it anyways, please add the original copyright
>> holder, I think this is from e7501?
>
> Your right, I don't really feel the above method is necessary. The
> only problem is this with Byte 31:
>
> # Banks Density of Bank 1 Density of bank 2 Byte 31 contents
> 1       32MByte           N/A               0000 1000
> 2       32MByte           32MBbyte          0000 1000
> 2       32MByte           16MByte           0000 1100
>
> You can see Byte 31 contents are going to be the same when the density
> is the same no matter how many banks it has. Could this potentially
> give a false reading?? You could also use Byte 5 to determine the
> banks. Could we say something like; if byte 5 has 1 bank than byte 31
> is correct and if byte 5 has 2 banks to muliply byte 31 by 2?? But
> what about the third example above when you have more than 1 bank and
> the densities are different??

Below is a simple example. There are better/faster ways to do it, but
this should just work. Also, coding style is probably very broken, blame
that on Thunderbird.

int i, spd_byte_31, spd_byte_5;
spd_byte_31 = smbus_read_byte(device, 31); //please rename device to dimm
spd_byte_5 = smbus_read_byte(device, 5);

for (i = 8; i >= 0; i--) {
    /* Find the larger value. The larger side is always side1 */
    if (spd_byte_31 & (1 << i) == (1 << i)) {
        sz.side1 = i;
        break;
    }
}

/* Set to 0 in case it's single sided */
sz.side2 = 0;

/* Test if it's a dual-sided dimm */
if (spd_byte_5 > 1) {
    /* Test to see if there's a second value, if so it's asymmetrical */
    if (spd_byte_31 != (1 << i)) {
        /* Find the second value, picking up where we left off */
        /* i-- done initially to make sure we don't get the same value
again */
        for (i--; i >= 0; i--) {
          if (spd_byte_31 == (1 << i) {
             sz.side2 = i;
             break;
          }
    }
    /* If not, it's symmetrical */
    else {
        sz.side2 = sz.side1;
    }
    return sz; //sizes are now in units of 4mb, so 1 = 4mb, 2 = 8mb, etc.
}

BTW, this has finally made me see the correlation that the i810 uses!
Expect a patch sometime for some major cleanup.

>>> static long spd_set_ram_size(const struct mem_controller *ctrl, 
>>> long dimm_mask)
>>> {
>>>     int i;
>>>     int cum;
>>>
>>>     for(i = cum = 0; i < DIMM_SOCKETS; i++) {
>>>         struct dimm_size sz;
>>>         if (dimm_mask & (1 << i)) {
>>>             sz = spd_get_dimm_size(ctrl->channel0[i]);
>>>
>>>             /* WISHLIST: would be nice to display it as decimal? */
>>>             print_debug("DIMM is ");
>>>             print_debug_hex8(sz.side1);
>>>             print_debug(" On Side 1\r\n");
>>>             print_debug("DIMM is ");
>>>             print_debug_hex8(sz.side2);
>>>             print_debug(" On Side 2\r\n");
>>>
>>>             /* Set the row offset, in KBytes (should this be
>>>             * Kbits?). Note that this offset is the start of the
>>>             * next row.
>>>             */
>>>             row_offset = ((sz.side1 + sz.side2) * 1024);
>>>
>>
>> If you're still in the initial testing stages, try to get one
>> single-sided dimm working first. Also, if you have a dual-sided dimm,
>> row_offset needs to be the address at the second side (as far as I
>> know), so only sz.side1 * 1024. This might be chip-dependent,
>> board-dependent, or I might be completely wrong...
> My test board has 128MB on-board, Remember this is a set-top-box. To
> the registry, with the stock bios it shows up as a sindle sided
> so-dimm in socket 2. Initially I could just hardcode alot of this but
> I would like to make it versitial and have the ability to use socket 1
> also. Alot of Laptops use this chip also, so this could open up
> LinuxBios to that front.

Does that dimm provide spd data? lm-sensors dimms-detect.pl should tell
you from userspace, or else dump_spd_data from linuxbios. If not, ignore
it completely for now, just act like it doesn't exist and hardcode it in
later. If so, use that as your test dimm/slot. I suspect it's probably
the former. Once you have one dimm working, try for another. Going for
both the first time through would take a lot of luck.

-Corey



From corey.osgood at gmail.com  Fri Jul  6 04:20:29 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 05 Jul 2007 22:20:29 -0400
Subject: [LinuxBIOS] i82830 raminit.c
In-Reply-To: <468DA185.5060206@gmail.com>
References: <20070704164502.odgvjvgmscwwg04s@www.smittys.pointclark.net>	<468C6263.9090807@gmail.com>
	<20070705121238.nzex9ztjsc04cc0s@www.smittys.pointclark.net>
	<468DA185.5060206@gmail.com>
Message-ID: <468DA6ED.6080300@gmail.com>

My bad, missed a closing bracket (possibly more, very tired right how):

>     if (spd_byte_31 != (1 << i)) {
>         /* Find the second value, picking up where we left off */
>         /* i-- done initially to make sure we don't get the same value
> again */
>         for (i--; i >= 0; i--) {
>           if (spd_byte_31 == (1 << i) {
>              sz.side2 = i;
>              break;
>           }
>   
         }
>     }
>     /* If not, it's symmetrical */




From stepan at coresystems.de  Fri Jul  6 08:22:59 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 6 Jul 2007 08:22:59 +0200
Subject: [LinuxBIOS] [PATCH][v3] Spinlock fixes
In-Reply-To: <20070706000547.GD13756@greenwood>
References: <20070706000547.GD13756@greenwood>
Message-ID: <20070706062259.GA985@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070706 02:05]:
> Various spinlock-related cleanups:
> 
>  - Revert back to spinlock_t (instead of struct spinlock). This is fine
>    in this special case, as the contents of spinlock_t are not meant to
>    ever be accessed directly (only by "accessor" functions).
 
NACK.

Why would that be required? The code in svn needs no fixing. Let's not
invent typedefs without any need for them

>  - Drop the spin_lock_string and spin_unlock_string macros, they're pretty
>    useless as they're only used in a single place and a macro doesn't make
>    this code any more readable, IMO.

NACK.

They are not useless at all as they are _the_ (one and only) spinlock
implementation on x86. The "only single place" is the declaration of the
x86 specific spin_lock and spin_unlock functions. 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Fri Jul  6 08:58:37 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 6 Jul 2007 08:58:37 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070705073604.GB5920@greenwood>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<20070705044119.GA5680@coresystems.de>
	<20070705073604.GB5920@greenwood>
Message-ID: <20070706065837.GA8751@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070705 09:36]:
> > > > I personally don't think there should be a place in the v3 tree for a 
> > > > utility like this, as it leads an almost completely independent life.
> > > 
> > > Yes, and it should. The copy in v2/v3 is merely there for convenience.
> > 
> > There is no copy in v3?
> 
> Not yet. Shall we add it?
 
Yes, please.

Acked-by: Stefan Reinauer <stepan at coresystems.de>



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From george at kami.ru  Fri Jul  6 13:51:17 2007
From: george at kami.ru (George V. Adamov)
Date: Fri, 06 Jul 2007 11:51:17 +0000
Subject: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n
	platinum)	motherboard
In-Reply-To: <2ea3fae10707051013j63888d14n729d65cc8bcd9016@mail.gmail.com>
References: <468D2ED1.30401@kami.ru>
	<2ea3fae10707051013j63888d14n729d65cc8bcd9016@mail.gmail.com>
Message-ID: <468E2CB5.6070400@kami.ru>

I am using linuxbios from public tree (snapshot downloaded from 
linuxbios.org)
Thank you for idea about gcc, I really using an old one, will upgrade 
and try.

yhlu wrote:

>On 7/5/07, George V. Adamov <george at kami.ru> wrote:
>  
>
>>I have changed the config for MB.
>>(Actualy I took the config from Gigabyte as base, then  changed superIO
>>chipset to winbond).
>>    
>>
>
>are you using tar ball i sent or from public tree?
>
>YH
>
>  
>




From george at kami.ru  Fri Jul  6 17:40:32 2007
From: george at kami.ru (George V. Adamov)
Date: Fri, 06 Jul 2007 15:40:32 +0000
Subject: [LinuxBIOS] Porting Linux BIOS to MSI ms7250 (k9n
	platinum)	motherboard
In-Reply-To: <2ea3fae10707051348o5676e858i438adfef51f5a1e1@mail.gmail.com>
References: <468D2ED1.30401@kami.ru>
	<2ea3fae10707051348o5676e858i438adfef51f5a1e1@mail.gmail.com>
Message-ID: <468E6270.80203@kami.ru>

It seems to be the same with 4.1.2 as with 3.3.4

yhlu wrote:

>gcc version?
>try 4.0.2 or 4.1.2 please.
>
>YH
>
>  
>




From peter at stuge.se  Fri Jul  6 16:28:01 2007
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Jul 2007 16:28:01 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070705035818.GA310@coresystems.de>
	<20070705071825.GA5920@greenwood>
	<20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
Message-ID: <20070706142801.31265.qmail@stuge.se>

On Wed, Jul 04, 2007 at 04:36:57PM -0400, Joseph Smith wrote:
> > printf("value in hexadecimal is now %x\n",value);
> 
> Ok so how would I go about doing this is print_debug than?

Sorry.

print_debug() in v2 doesn't support variable number of arguments
(varargs) but maybe you could backport printk() from v3 lib/console.c ?


//Peter



From uwe at hermann-uwe.de  Fri Jul  6 16:34:41 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 6 Jul 2007 16:34:41 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop superfluous round()
Message-ID: <20070706143440.GA8383@greenwood>

See patch.

Do we want align_up()/align_down() in lib.c maybe?

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Jul  6 17:07:54 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 6 Jul 2007 17:07:54 +0200
Subject: [LinuxBIOS] [PATCH][v3] Spinlock fixes
In-Reply-To: <20070706062259.GA985@coresystems.de>
References: <20070706000547.GD13756@greenwood>
	<20070706062259.GA985@coresystems.de>
Message-ID: <20070706150754.GB8383@greenwood>

On Fri, Jul 06, 2007 at 08:22:59AM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070706 02:05]:
> > Various spinlock-related cleanups:
> > 
> >  - Revert back to spinlock_t (instead of struct spinlock). This is fine
> >    in this special case, as the contents of spinlock_t are not meant to
> >    ever be accessed directly (only by "accessor" functions).
>  
> NACK.
> 
> Why would that be required? The code in svn needs no fixing. Let's not
> invent typedefs without any need for them

It's not strictly required, but as the original code had a spinlock_t
(which we removed because I made some stupid comments before actually
thinking), I thought we could add it back.

It makes sense in this case, as we'll never access anything in the
struct directly. spinlock_t could probably be implemented differently,
and that's the whole point of the typedef in this case -- we don't care
how it's implemented, we only ever access the variables via
spin_lock(foo) and spin_unlock(foo), never via foo->lock directly.

 
> >  - Drop the spin_lock_string and spin_unlock_string macros, they're pretty
> >    useless as they're only used in a single place and a macro doesn't make
> >    this code any more readable, IMO.
> 
> NACK.
> 
> They are not useless at all as they are _the_ (one and only) spinlock
> implementation on x86. The "only single place" is the declaration of the
> x86 specific spin_lock and spin_unlock functions. 

Huh? I don't understand.

My remark was meant to say the following: version a) is not more
readable than b), so let's use b).


a)

#define spin_lock_string \
        "\n1:\t" \
        "lock ; decb %0\n\t" \
        "js 2f\n" \
        ".section .text.lock,\"ax\"\n" \
        "2:\t" \
        "cmpb $0,%0\n\t" \
        "rep;nop\n\t" \
        "jle 2b\n\t" \
        "jmp 1b\n" \
        ".previous"

static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
{
        __asm__ __volatile__(
                spin_lock_string
                :"=m" (lock->lock) : : "memory");
}


b)

static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
{
      __asm__ __volatile__("\n1:\t"
                           "lock ; decb %0\n\t"
                           "js 2f\n"
                           ".section .text.lock,\"ax\"\n"
                           "2:\t"
                           "cmpb $0,%0\n\t"
                           "rep;nop\n\t"
                           "jle 2b\n\t"
                           "jmp 1b\n"
                           ".previous"
                           :"=m" (lock->lock) : : "memory");
}

Are there any drawbacks if we use version b)? I think not. This is
indeed x86 specific, a spinlock implementation for PowerPC for example
would be in a different file (arch/powerpc/arch/spinlock.h) and would
implement spin_lock() from scratch anyway.

It's not like we define another spin_lock_string for PowerPC and use it
in a generic spin_lock() function. If we do that, then the spin_lock()
should not be in include/arch/x86/arch/spinlock.h (x86-specific), but rather
in include/spinlock.h (generic, arch-independent), correct?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From joe at smittys.pointclark.net  Fri Jul  6 17:41:51 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Fri, 06 Jul 2007 11:41:51 -0400
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706142801.31265.qmail@stuge.se>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070705035818.GA310@coresystems.de> <20070705071825.GA5920@greenwood>
	<20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
	<20070706142801.31265.qmail@stuge.se>
Message-ID: <20070706114151.gekpxulz4wcw0cw0@www.smittys.pointclark.net>

Quoting Peter Stuge <peter at stuge.se>:

> On Wed, Jul 04, 2007 at 04:36:57PM -0400, Joseph Smith wrote:
>> > printf("value in hexadecimal is now %x\n",value);
>>
>> Ok so how would I go about doing this is print_debug than?
>
> Sorry.
>
> print_debug() in v2 doesn't support variable number of arguments
> (varargs) but maybe you could backport printk() from v3 lib/console.c ?
>
>
> //Peter
>
Maybe V3 at a later date, I'm still working on porting my board to V2.

Ok, if the computer sees everthing in binary, than maybe I can try  
something like this?

#define PRINT_DEBUG_DEC(d)

value=0xff; /* hexadecimal */

print_debug("value in decimal is now ");
PRINT_DEBUG_DEC(value);
print_debug(" Is this working?\r\n");


What do you think?


Thanks - Joe



From stepan at coresystems.de  Fri Jul  6 19:39:46 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 6 Jul 2007 19:39:46 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706142801.31265.qmail@stuge.se>
References: <20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070705035818.GA310@coresystems.de>
	<20070705071825.GA5920@greenwood>
	<20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
	<20070706142801.31265.qmail@stuge.se>
Message-ID: <20070706173945.GB3605@coresystems.de>

* Peter Stuge <peter at stuge.se> [070706 16:28]:
> On Wed, Jul 04, 2007 at 04:36:57PM -0400, Joseph Smith wrote:
> > > printf("value in hexadecimal is now %x\n",value);
> > 
> > Ok so how would I go about doing this is print_debug than?
> 
> Sorry.
> 
> print_debug() in v2 doesn't support variable number of arguments
> (varargs) but maybe you could backport printk() from v3 lib/console.c ?

There are already 6 printk/f variants in v2. So one could assume this
has been tried 5 times already ;)

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Fri Jul  6 19:41:20 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 6 Jul 2007 19:41:20 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706114151.gekpxulz4wcw0cw0@www.smittys.pointclark.net>
References: <20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070705035818.GA310@coresystems.de>
	<20070705071825.GA5920@greenwood>
	<20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
	<20070706142801.31265.qmail@stuge.se>
	<20070706114151.gekpxulz4wcw0cw0@www.smittys.pointclark.net>
Message-ID: <20070706174120.GC3605@coresystems.de>

* Joseph Smith <joe at smittys.pointclark.net> [070706 17:41]:
> #define PRINT_DEBUG_DEC(d)
> 
> value=0xff; /* hexadecimal */
> 
> print_debug("value in decimal is now ");
> PRINT_DEBUG_DEC(value);
> print_debug(" Is this working?\r\n");
 
Since it seems to be for debug only, you can also use
print_debug_hex8
print_debug_hex16
print_debug_hex32

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Fri Jul  6 19:44:12 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 6 Jul 2007 19:44:12 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop superfluous round()
In-Reply-To: <20070706143440.GA8383@greenwood>
References: <20070706143440.GA8383@greenwood>
Message-ID: <20070706174412.GD3605@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070706 16:34]:
> See patch.
> 
> Do we want align_up()/align_down() in lib.c maybe?

Since it operates on resources, I think no.

> Drop the round() function, as it is an exact copy of align_up().
> 
> Also, make align_up()/align_down() non-static as they are useful
> even outside of device/device_util.c.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
 
-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From svn at openbios.org  Fri Jul  6 20:03:43 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  6 Jul 2007 20:03:43 +0200
Subject: [LinuxBIOS] r435 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
Message-ID: <mailman.501.1355071131.16123.coreboot@coreboot.org>

Author: mjones
Date: 2007-07-06 20:03:43 +0200 (Fri, 06 Jul 2007)
New Revision: 435

Modified:
   LinuxBIOSv3/arch/x86/geodelx/geodelx.c
   LinuxBIOSv3/include/arch/x86/amd_geodelx.h
Log:
Rework the Geode delay control setup to table driven and much more readable.

Signed-off-by: Marc Jones <marc.jones at amd.com>
Acked-by: Peter Stuge <peter at stuge.se>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-05 17:27:23 UTC (rev 434)
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-06 18:03:43 UTC (rev 435)
@@ -247,7 +247,43 @@
 	}
 }
 
+
 /**
+ * Delay Control Settings Table from AMD (MCP 0x4C00000F)
+ * =========================================================================
+ */
+const struct delay_controls {
+	u8 dimms;
+	u8 devices;
+	u32 slow_hi;
+	u32 slow_low;
+	u32 fast_hi;
+	u32 fast_low;
+} delay_control_table [] = {
+	/* DIMMs Devs Slow (<=333MHz)            Fast (>334MHz) */
+	{ 1,     4,   0x0837100FF, 0x056960004,  0x0827100FF, 0x056960004 },
+	{ 1,     8,   0x0837100AA, 0x056960004,  0x0827100AA, 0x056960004 },
+	{ 1,     16,  0x0837100AA, 0x056960004,  0x082710055, 0x056960004 },
+	{ 2,     8,   0x0837100A5, 0x056960004,  0x082710000, 0x056960004 },
+	{ 2,     16,  0x0937100A5, 0x056960004,  0x0C27100A5, 0x056960004 },
+	{ 2,     20,  0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
+	{ 2,     24,  0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
+	{ 2,     32,  0x0B37100A5, 0x056960004,  0x0B2710000, 0x056960004 },
+};
+/**
+ *  - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
+ *    in slot 0, but it should be clear for all 2 DIMM settings and if a
+ *    single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
+ *
+ *    Settings for single DIMM and no VTT termination (Like db800 platform)
+ *     0xF2F100FF 0x56960004
+ *     -------------------------------------
+ *    ADDR/CTL have 22 ohm series R
+ *    DQ/DQM/DQS have 33 ohm series R
+ */
+
+
+/**
  * set_delay_control. This is Black Magic DRAM timing
  * juju(http://www.thefreedictionary.com/juju) Dram delay depends on
  * cpu clock, memory bus clock, memory bus loading, memory bus
@@ -263,12 +299,10 @@
  * @param dimm1 DIMM 1 SMBus address
  * @param sram_width Data width of the SDRAM
  */
-
 void set_delay_control(u8 dimm0, u8 dimm1)
 {
 	u32 msrnum, glspeed;
-	u8 spdbyte0, spdbyte1;
-	int numdimms = 0;
+	u8 spdbyte0, spdbyte1, dimms, i;
 	struct msr  msr;
 
 	glspeed = geode_link_speed();
@@ -315,9 +349,10 @@
 	 * # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
 	 * Note - We only support module width of 64.
 	 */
+	dimms = 0;
 	spdbyte0 = smbus_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH);
 	if (spdbyte0 != 0xFF) {
-		numdimms++;
+		dimms++;
 		spdbyte0 = (unsigned char)64 / spdbyte0 *
 		    (unsigned char)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS));
 	} else {
@@ -326,136 +361,34 @@
 
 	spdbyte1 = smbus_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH);
 	if (spdbyte1 != 0xFF) {
-		numdimms++;
+		dimms++;
 		spdbyte1 = (unsigned char)64 / spdbyte1 *
 		    (unsigned char)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS));
 	} else {
 		spdbyte1 = 0;
 	}
 
-/* The current thinking. Subject to change...
+	/* zero GLCP_DELAY_CONTROLS MSR */
+	msr.hi = msr.lo = 0;
 
-;								   "FUTURE ROBUSTNESS" PROPOSAL
-;								   ----------------------------
-;		DIMM	 Max MBUS					   MC 0x2000001A bits 26:24
-;DIMMs	devices	 Frequency	 MCP 0x4C00000F Setting		 vvv
-;-----	-------	 ---------	 ----------------------	 ----------
-;1		 4		 400MHz		 0x82*100FF 0x56960004		  4
-;1		 8		 400MHz		 0x82*100AA 0x56960004		  4
-;1		 16		 400MHz		 0x82*10055 0x56960004		  4
-;
-;2		 4,4	 400MHz		 0x82710000 0x56960004		  4
-;2		 8,8	 400MHz		 0xC27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
-;
-;2		16,4	 >333		 0xB27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
-;2		16,8	 >333		 0xB27100A5 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
-;2		16,16	 >333		 0xB2710000 0x56960004		  4	*** OUT OF PUBLISHED ENVELOPE ***
-;
-;1		 4		 <=333MHz	 0x83*100FF 0x56960004		  3
-;1		 8		 <=333MHz	 0x83*100AA 0x56960004		  3
-;1		 16		 <=333MHz	 0x83*100AA 0x56960004		  3
-;
-;2		 4,4	 <=333MHz	 0x837100A5 0x56960004		  3
-;2		 8,8	 <=333MHz	 0x937100A5 0x56960004		  3
-;
-;2		16,4	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
-;2		16,8	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
-;2		16,16	 <=333MHz	 0xB37100A5 0x56960004		  3	*** OUT OF PUBLISHED ENVELOPE ***
-;=========================================================================
-;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
-;	 but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
-;	 Bits 54:52 should always be set to '111'.
+	/* save some power, disable clock to second DIMM if it is empty */
+	if (spdbyte1 == 0) {
+		msr.hi |= DELAY_UPPER_DISABLE_CLK135;
+	}
 
-;No VTT termination
-;-------------------------------------
-;ADDR/CTL have 22 ohm series R
-;DQ/DQM/DQS have 33 ohm series R
-;
-;		DIMM	 Max MBUS
-;DIMMs	devices	 Frequency	 MCP 0x4C00000F Setting
-;-----	-------	 ---------	 ----------------------
-;1		 4		 400MHz		 0xF2F100FF 0x56960004		  4			The MC changes improve Salsa.
-;1		 8		 400MHz		 0xF2F100FF 0x56960004		  4			Delay controls no real change,
-;1		 4		 <=333MHz	 0xF2F100FF 0x56960004		  3			just fixing typo in left side.
-;1		 8		 <=333MHz	 0xF2F100FF 0x56960004		  3
-;1		 16		 <=333MHz	 0xF2F100FF 0x56960004		  3
-*/
-	msr.hi = msr.lo = 0;
+	spdbyte0 += spdbyte1;
 
-	if (spdbyte0 == 0 || spdbyte1 == 0) {
-		/* one dimm solution */
-		if (spdbyte1 == 0) {
-			msr.hi |= 0x000800000;
-		}
-		spdbyte0 += spdbyte1;
-		if (spdbyte0 > 8) {
-			/* large dimm */
+	for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
+		if ((dimms == delay_control_table[i].dimms) &&
+				(spdbyte0 <= delay_control_table[i].devices)) {
 			if (glspeed < 334) {
-				msr.hi |= 0x0837100AA;
-				msr.lo |= 0x056960004;
+				msr.hi |= delay_control_table[i].slow_hi;
+				msr.lo |= delay_control_table[i].slow_low;
 			} else {
-				msr.hi |= 0x082710055;
-				msr.lo |= 0x056960004;
+				msr.hi |= delay_control_table[i].fast_hi;
+				msr.lo |= delay_control_table[i].fast_low;
 			}
-		} else if (spdbyte0 > 4) {
-			/* medium dimm */
-			if (glspeed < 334) {
-				msr.hi |= 0x0837100AA;
-				msr.lo |= 0x056960004;
-			} else {
-				msr.hi |= 0x0827100AA;
-				msr.lo |= 0x056960004;
-			}
-		} else {
-			/* small dimm */
-			if (glspeed < 334) {
-				msr.hi |= 0x0837100FF;
-				msr.lo |= 0x056960004;
-			} else {
-				msr.hi |= 0x0827100FF;
-				msr.lo |= 0x056960004;
-			}
 		}
-	} else {
-		/* two dimm solution */
-		spdbyte0 += spdbyte1;
-		if (spdbyte0 > 24) {
-			/* huge dimms */
-			if (glspeed < 334) {
-				msr.hi |= 0x0B37100A5;
-				msr.lo |= 0x056960004;
-			} else {
-				msr.hi |= 0x0B2710000;
-				msr.lo |= 0x056960004;
-			}
-		} else if (spdbyte0 > 16) {
-			/* large dimms */
-			if (glspeed < 334) {
-				msr.hi |= 0x0B37100A5;
-				msr.lo |= 0x056960004;
-			} else {
-				msr.hi |= 0x0B27100A5;
-				msr.lo |= 0x056960004;
-			}
-		} else if (spdbyte0 >= 8) {
-			/* medium dimms */
-			if (glspeed < 334) {
-				msr.hi |= 0x0937100A5;
-				msr.lo |= 0x056960004;
-			} else {
-				msr.hi |= 0x0C27100A5;
-				msr.lo |= 0x056960004;
-			}
-		} else {
-			/* small dimms */
-			if (glspeed < 334) {
-				msr.hi |= 0x0837100A5;
-				msr.lo |= 0x056960004;
-			} else {
-				msr.hi |= 0x082710000;
-				msr.lo |= 0x056960004;
-			}
-		}
 	}
 	wrmsr(GLCP_DELAY_CONTROLS, msr);
 	return;

Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-05 17:27:23 UTC (rev 434)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-06 18:03:43 UTC (rev 435)
@@ -354,7 +354,8 @@
 #define GLCP_GLD_MSR_ERROR			(MSR_GLCP + 0x2003)
 #define GLCP_GLD_MSR_PM				(MSR_GLCP + 0x2004)
 #define GLCP_DELAY_CONTROLS			(MSR_GLCP + 0x0F)
-#define DELAY_LOWER_STATUS_MASK		 0x7C0
+#define DELAY_UPPER_DISABLE_CLK135	(1 << 23)
+#define DELAY_LOWER_STATUS_MASK		0x7C0
 #define GLCP_SYS_RSTPLL				(MSR_GLCP + 0x14)	/* R/W */
 #define RSTPLL_UPPER_GLMULT_SHIFT		7
 #define RSTPLL_UPPER_GLMULT_MASK		0x1F




From marc.jones at amd.com  Fri Jul  6 20:05:11 2007
From: marc.jones at amd.com (Marc Jones)
Date: Fri, 06 Jul 2007 12:05:11 -0600
Subject: [LinuxBIOS] Geode delay control setting cleanup
In-Reply-To: <20070706002732.GE13756@greenwood>
References: <468D52C5.1020105@amd.com>
 <20070706002732.GE13756@greenwood>
Message-ID: <468E8457.8090703@amd.com>




> With the above issues fixed:
> 
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> 
> Uwe.

Issues fixed.

r435

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From jtmettala at gmail.com  Fri Jul  6 22:40:54 2007
From: jtmettala at gmail.com (=?UTF-8?Q?Jouni_Mett=C3=A4l=C3=A4?=)
Date: Fri, 6 Jul 2007 23:40:54 +0300
Subject: [LinuxBIOS] ticket 7 (flashing ICH-x mainboard)
Message-ID: <63e824e50707061340x5d514b27me5bfb2d550c189b0@mail.gmail.com>

Based on intel 82802ab/82802ac datasheet. There is Top Block Lock. TBL# pin
disables writing of highest addressable block when it is low.

When #TBL pin was desoldered and connected to Vcc (Is it right way to put it
high?) Flashing with flashrom was succesful. Verify was ok.

It wasn't possible to write that chip with flashrom or uniflash before that.

There is also WP# pin to enable or disable writing other blocks.

Datasheet is http://download.intel.com/design/chipsets/datashts/29065804.pdf
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From a1426z at gawab.com  Fri Jul  6 23:28:31 2007
From: a1426z at gawab.com (Al Boldi)
Date: Sat, 7 Jul 2007 00:28:31 +0300
Subject: [LinuxBIOS] FILO and USB: Out of heap space
In-Reply-To: <468C6663.70804@gmail.com>
References: <468C6663.70804@gmail.com>
Message-ID: <200707070028.31652.a1426z@gawab.com>

Corey Osgood wrote:
> FILO is giving me the error below when using autoboot and attempting to
> boot from a usb drive. I think this might be due to this board having 4
> USB controllers, but I'm not really sure. The board in question is the
> CN700/VT8237R board, booting the factory BIOS and then booting FILO
> through grub. USB is enabled in the BIOS, EHCI is disabled, and all USB
> controllers are enabled (there's no option to disable some, it's all or
> none). BTW, Peter's FILO IDE speedup patch works great on this board!
> This error occurs with a fresh checkout as well. I'm hoping someone with
> more USB knowledge than me (which doesn't take much) can tell what's
> wrong here.


Check your config according to http://www.linuxbios.org/index.php/Etherboot

The following flags in src/arch/i386/Config are critical for a normal bios:
CFLAGS+= -DPCBIOS
#CFLAGS+= -DLINUXBIOS
CFLAGS+= -DCONFIG_PCI_DIRECT
CFLAGS+= -DCONSOLE_DIRECT_VGA
#filo is for some reason dependent on serial; will hang otherwise
CFLAGS+= -DCONSOLE_SERIAL -DCOMCONSOLE=0x3f8
#don't uncomment this one; will slow down display on fast machines (P4)
#CFLAGS+= -DCOMPRESERVE


Thanks!

--
Al




From joe at smittys.pointclark.net  Sat Jul  7 00:59:32 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Fri, 06 Jul 2007 18:59:32 -0400
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706174120.GC3605@coresystems.de>
References: <20070704152956.30330.qmail@stuge.se>
	<20070704174711.GL17746@greenwood>
	<20070705035818.GA310@coresystems.de>
	<20070705071825.GA5920@greenwood>
	<20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
	<20070706142801.31265.qmail@stuge.se>
	<20070706114151.gekpxulz4wcw0cw0@www.smittys.pointclark.net>
	<20070706174120.GC3605@coresystems.de>
Message-ID: <20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>

Quoting Stefan Reinauer <stepan at coresystems.de>:

> * Joseph Smith <joe at smittys.pointclark.net> [070706 17:41]:
>> #define PRINT_DEBUG_DEC(d)
>>
>> value=0xff; /* hexadecimal */
>>
>> print_debug("value in decimal is now ");
>> PRINT_DEBUG_DEC(value);
>> print_debug(" Is this working?\r\n");
>
> Since it seems to be for debug only, you can also use
> print_debug_hex8
> print_debug_hex16
> print_debug_hex32
>
> Stefan
>

But that is the whole problem. I already says "print_debug_hex8". I  
want it to display decimal not hex.....


Thanks - Joe



From stepan at coresystems.de  Sat Jul  7 01:32:01 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 7 Jul 2007 01:32:01 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
References: <20070705035818.GA310@coresystems.de>
	<20070705071825.GA5920@greenwood>
	<20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
	<20070706142801.31265.qmail@stuge.se>
	<20070706114151.gekpxulz4wcw0cw0@www.smittys.pointclark.net>
	<20070706174120.GC3605@coresystems.de>
	<20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
Message-ID: <20070706233201.GC25864@coresystems.de>

* Joseph Smith <joe at smittys.pointclark.net> [070707 00:59]:
>  But that is the whole problem. I already says "print_debug_hex8". I want it 
>  to display decimal not hex.....

You could look at print_debug_hex8 and implement the _dec8 functions.

I don't think it's worth the effort though. What's wrong with hex?

It's all debug anyways.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Sat Jul  7 01:42:26 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 7 Jul 2007 01:42:26 +0200
Subject: [LinuxBIOS] FILO and USB: Out of heap space
In-Reply-To: <468C6663.70804@gmail.com>
References: <468C6663.70804@gmail.com>
Message-ID: <20070706234226.GE25864@coresystems.de>

* Corey Osgood <corey.osgood at gmail.com> [070705 05:32]:
> FILO is giving me the error below when using autoboot and attempting to
> boot from a usb drive. I think this might be due to this board having 4
> USB controllers, but I'm not really sure. The board in question is the
> CN700/VT8237R board, booting the factory BIOS and then booting FILO
> through grub. USB is enabled in the BIOS, EHCI is disabled, and all USB
> controllers are enabled (there's no option to disable some, it's all or
> none). BTW, Peter's FILO IDE speedup patch works great on this board!
> This error occurs with a fresh checkout as well. I'm hoping someone with
> more USB knowledge than me (which doesn't take much) can tell what's
> wrong here.
 
> dump_link: frame_list_link: depth:
> 0                                           
> Out of heap space

You can increase the memory that the FILO memory allocator is able to
use. probably a good idea. If this fixes your problem, please send a
patch.

it can be adjusted in i386/ldscript around line 12

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From joe at smittys.pointclark.net  Sat Jul  7 02:29:54 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Fri, 06 Jul 2007 20:29:54 -0400
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706233201.GC25864@coresystems.de>
References: <20070705035818.GA310@coresystems.de>
	<20070705071825.GA5920@greenwood>
	<20070705113532.cvfxknvzkos880k0@www.smittys.pointclark.net>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
	<20070706142801.31265.qmail@stuge.se>
	<20070706114151.gekpxulz4wcw0cw0@www.smittys.pointclark.net>
	<20070706174120.GC3605@coresystems.de>
	<20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
	<20070706233201.GC25864@coresystems.de>
Message-ID: <20070706202954.u7vcguld2cckk88g@www.smittys.pointclark.net>

Quoting Stefan Reinauer <stepan at coresystems.de>:

> * Joseph Smith <joe at smittys.pointclark.net> [070707 00:59]:
>>  But that is the whole problem. I already says "print_debug_hex8". I want it
>>  to display decimal not hex.....
>
> You could look at print_debug_hex8 and implement the _dec8 functions.
>
> I don't think it's worth the effort though. What's wrong with hex?
>
> It's all debug anyways.
>
I kow it is just for aesthetics but, If it is an easy implimentation,  
I will check it out. What file is print_debug_hex8 in anyways?

Thanks Again - Joe



From rminnich at gmail.com  Sat Jul  7 02:52:59 2007
From: rminnich at gmail.com (ron minnich)
Date: Fri, 6 Jul 2007 17:52:59 -0700
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706202954.u7vcguld2cckk88g@www.smittys.pointclark.net>
References: <20070705035818.GA310@coresystems.de>
	<20070704092254.jzmps3qdc0gg0wok@www.smittys.pointclark.net>
	<20070704152956.30330.qmail@stuge.se>
	<20070704163657.yxqp2qg6osk0k8s8@www.smittys.pointclark.net>
	<20070706142801.31265.qmail@stuge.se>
	<20070706114151.gekpxulz4wcw0cw0@www.smittys.pointclark.net>
	<20070706174120.GC3605@coresystems.de>
	<20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
	<20070706233201.GC25864@coresystems.de>
	<20070706202954.u7vcguld2cckk88g@www.smittys.pointclark.net>
Message-ID: <13426df10707061752j7a52f193ja084cf4f2ce40daf@mail.gmail.com>

joe, print in hex is trivial.

In the limit, it's this simple:
putc(hexarray((a>>4)&0xf); putc(hexarray(a&0xf));

decimal is harder, and, in romcc, not worth the effort.

I think this whole decimal escapade is not a good use of time.

ron



From todthgie at hotmail.com  Sat Jul  7 10:12:40 2007
From: todthgie at hotmail.com (todthgie)
Date: Sat, 7 Jul 2007 10:12:40 +0200
Subject: [LinuxBIOS] ticket 7 (flashing ICH-x mainboard)
References: <63e824e50707061340x5d514b27me5bfb2d550c189b0@mail.gmail.com>
Message-ID: <BAY132-DAV17D86C1FDC3D81EA1E303EC7000@phx.gbl>

Hello,

Soldering #TBL to Vcc seems aceptable to me. i always use a resistor of 
1k..10k in series but that is just to be on the extrem safe side...

next step is finding out to what the original #TBL pad is connected .. if 
#WP is comming from some chip #TBL might be near it on that chip....

greetings,
todthgie


----- Original Message ----- 
From: Jouni Mett?l?
To: linuxbios at linuxbios.org
Sent: Friday, July 06, 2007 22:40
Subject: [LinuxBIOS] ticket 7 (flashing ICH-x mainboard)


Based on intel 82802ab/82802ac datasheet. There is Top Block Lock. TBL# pin 
disables writing of highest addressable block when it is low.

When #TBL pin was desoldered and connected to Vcc (Is it right way to put it 
high?) Flashing with flashrom was succesful. Verify was ok.

It wasn't possible to write that chip with flashrom or uniflash before that.

There is also WP# pin to enable or disable writing other blocks.

Datasheet is http://download.intel.com/design/chipsets/datashts/29065804.pdf




-- 
linuxbios mailing list
linuxbios at linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios 




From svn at openbios.org  Sat Jul  7 11:34:56 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  7 Jul 2007 11:34:56 +0200
Subject: [LinuxBIOS] r436 - in LinuxBIOSv3: arch/x86 northbridge/amd/geodelx
	northbridge/intel/i440bxemulation southbridge/intel/i82371eb
	superio/winbond/w83627hf
Message-ID: <mailman.502.1355071131.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-07-07 11:34:56 +0200 (Sat, 07 Jul 2007)
New Revision: 436

Modified:
   LinuxBIOSv3/arch/x86/Makefile
   LinuxBIOSv3/northbridge/amd/geodelx/Makefile
   LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile
   LinuxBIOSv3/southbridge/intel/i82371eb/Makefile
   LinuxBIOSv3/superio/winbond/w83627hf/Makefile
Log:
trivial: fix some dependencies (for make -j)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: LinuxBIOSv3/arch/x86/Makefile
===================================================================
--- LinuxBIOSv3/arch/x86/Makefile	2007-07-06 18:03:43 UTC (rev 435)
+++ LinuxBIOSv3/arch/x86/Makefile	2007-07-07 09:34:56 UTC (rev 436)
@@ -95,7 +95,7 @@
 	      $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \
 		$(STAGE0_MAINBOARD_OBJ)
 
-$(obj)/stage0.init: $(STAGE0_OBJ)
+$(obj)/stage0.o $(obj)/stage0.init: $(STAGE0_OBJ)
 	$(Q)# We need to be careful. If stage0.o gets bigger than
 	$(Q)# 0x4000 - 0x100, we will end up with a 4 gig file.
 	$(Q)# I wonder if that behavior is on purpose.

Modified: LinuxBIOSv3/northbridge/amd/geodelx/Makefile
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/Makefile	2007-07-06 18:03:43 UTC (rev 435)
+++ LinuxBIOSv3/northbridge/amd/geodelx/Makefile	2007-07-07 09:34:56 UTC (rev 436)
@@ -21,7 +21,7 @@
 
 STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o $(obj)/northbridge/amd/geodelx/geodelxinit.o
 
-$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c
+$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/northbridge/amd/geodelx
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@

Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile	2007-07-06 18:03:43 UTC (rev 435)
+++ LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile	2007-07-07 09:34:56 UTC (rev 436)
@@ -21,7 +21,7 @@
 
 STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
 
-$(obj)/northbridge/intel/i440bxemulation/%.o: $(src)/northbridge/intel/i440bxemulation/%.c
+$(obj)/northbridge/intel/i440bxemulation/%.o: $(src)/northbridge/intel/i440bxemulation/%.c $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/northbridge/intel/i440bxemulation
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@

Modified: LinuxBIOSv3/southbridge/intel/i82371eb/Makefile
===================================================================
--- LinuxBIOSv3/southbridge/intel/i82371eb/Makefile	2007-07-06 18:03:43 UTC (rev 435)
+++ LinuxBIOSv3/southbridge/intel/i82371eb/Makefile	2007-07-07 09:34:56 UTC (rev 436)
@@ -20,7 +20,7 @@
 
 STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
 
-$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c
+$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/southbridge/intel/i82371eb/
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@

Modified: LinuxBIOSv3/superio/winbond/w83627hf/Makefile
===================================================================
--- LinuxBIOSv3/superio/winbond/w83627hf/Makefile	2007-07-06 18:03:43 UTC (rev 435)
+++ LinuxBIOSv3/superio/winbond/w83627hf/Makefile	2007-07-07 09:34:56 UTC (rev 436)
@@ -22,7 +22,7 @@
 # Always add to variables, as there could be more than one Super I/O.
 STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
 
-$(obj)/superio/winbond/w83627hf/%.o: $(src)/superio/winbond/w83627hf/%.c
+$(obj)/superio/winbond/w83627hf/%.o: $(src)/superio/winbond/w83627hf/%.c $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/superio/winbond/w83627hf/
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@




From uwe at hermann-uwe.de  Sat Jul  7 21:18:14 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 7 Jul 2007 21:18:14 +0200
Subject: [LinuxBIOS] [PATCH] Add support for 17 new SMSC Super I/O devices
Message-ID: <20070707191814.GA5859@greenwood>

Hi,

here's a new generic driver for SMSC Super I/O chips which should put an
end to the copy+paste style of development when it comes to Super I/O
code in LinuxBIOS and massively reduce the amount of duplicated code.

This single piece of code should be able to (currently) handle 17
different SMSC Super I/O chips, more can be added with minimal amount
of work (two lines of code).

This patch replaces a bunch of v2 Super I/Os, basically "ports" some of
the yet unported v1 Super I/Os, and adds support for a bunch of totally
new Super I/Os, all in one.

The following devices may or may not be (fully) supported by the driver:

 - FDC37b80x
 - FDC37m70x
 - FDC37b78x
 - FDC37b72x
 - FDC37m81x
 - FDC37m60x
 - LPC47b27x
 - LPC47m10x
 - LPC47m112
 - LPC47m13x
 - LPC47m15x
 - LPC47m192
 - LPC47s45x
 - LPC47b397
 - A8000
 - DME1737
 - SCH5307

The floppy disk controller, the parallel port, the serial ports, and the
keyboard controller should work with all the chips. For the more advanced
stuff (e.g. HWM, ACPI, SMBus) more work is probably required.

So far only the ASUS A8000 has been tested on real hardware (and it works :)

The current lpc47b272 and lpc47m10x in v2 can probably be dropped
immediately, AFAICS my driver handles everything those two did. Some
other devices in v2 do a bit more at the moment and cannot be dropped, yet.

As I cannot test all of this on hardware, it would be nice if somebody
with a supported board using one of these Super I/Os could replace the
respective driver with this new 'smscsuperio' driver and test whether
everything works ok.


I'm planning similar patches for all other Super I/O vendors, I think we
can easily handle 95% of all Super I/Os of each vendor with one such
generic driver.

I also plan to use the same technique in v3, so we only need very few,
generic drivers there, too.

Open issues: I don't know if or how we can handle boards with multiple
Super I/Os on them. Ideas welcome!


Technically the driver reads the device ID of the Super I/O and then
initializes only those devices which are supported by that Super I/O.

The code is a bit clumsy in parts, suggestions for improvements are welcome!


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Sat Jul  7 21:19:44 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  7 Jul 2007 21:19:44 +0200
Subject: [LinuxBIOS] r437 - in LinuxBIOSv3: device include/device
Message-ID: <mailman.503.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-07 21:19:44 +0200 (Sat, 07 Jul 2007)
New Revision: 437

Modified:
   LinuxBIOSv3/device/device.c
   LinuxBIOSv3/device/device_util.c
   LinuxBIOSv3/include/device/device.h
Log:
Drop the round() function, as it is an exact copy of align_up().

Also, make align_up()/align_down() non-static as they are useful
even outside of device/device_util.c.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: LinuxBIOSv3/device/device.c
===================================================================
--- LinuxBIOSv3/device/device.c	2007-07-07 09:34:56 UTC (rev 436)
+++ LinuxBIOSv3/device/device.c	2007-07-07 19:19:44 UTC (rev 437)
@@ -244,22 +244,6 @@
 }
 
 /**
- * Round a number up to an alignment.
- *
- * @param val The starting value.
- * @param roundup Alignment as a power of two.
- * @returns Rounded up number.
- */
-static resource_t round(resource_t val, unsigned long pow)
-{
-	resource_t mask;
-	mask = (1ULL << pow) - 1ULL;
-	val += mask;
-	val &= ~mask;
-	return val;
-}
-
-/**
  * Read the resources on all devices of a given bus.
  *
  * @param bus Bus to read the resources on.
@@ -492,9 +476,9 @@
 				base = 0x3e0;
 			}
 		}
-		if (((round(base, align) + size) - 1) <= resource->limit) {
+		if (((align_up(base, align) + size) - 1) <= resource->limit) {
 			/* Base must be aligned to size. */
-			base = round(base, align);
+			base = align_up(base, align);
 			resource->base = base;
 			resource->flags |= IORESOURCE_ASSIGNED;
 			resource->flags &= ~IORESOURCE_STORED;
@@ -517,7 +501,7 @@
 	 * minimum granularity so we know not to place something else at an
 	 * address positively decoded by the bridge.
 	 */
-	bridge->size = round(base, bridge->gran) - bridge->base;
+	bridge->size = align_up(base, bridge->gran) - bridge->base;
 
 	printk(BIOS_SPEW, "%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d done\n", dev_path(bus->dev), (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", base, bridge->size, bridge->align, bridge->gran);
 }

Modified: LinuxBIOSv3/device/device_util.c
===================================================================
--- LinuxBIOSv3/device/device_util.c	2007-07-07 09:34:56 UTC (rev 436)
+++ LinuxBIOSv3/device/device_util.c	2007-07-07 19:19:44 UTC (rev 437)
@@ -496,7 +496,7 @@
  * @param gran Granularity we are aligning the number to.
  * @returns The aligned value.
  */
-static resource_t align_up(resource_t val, unsigned long gran)
+resource_t align_up(resource_t val, unsigned long gran)
 {
 	resource_t mask;
 	mask = (1ULL << gran) - 1ULL;
@@ -512,7 +512,7 @@
  * @param gran Granularity we are aligning the number to.
  * @returns The aligned value.
  */
-static resource_t align_down(resource_t val, unsigned long gran)
+resource_t align_down(resource_t val, unsigned long gran)
 {
 	resource_t mask;
 	mask = (1ULL << gran) - 1ULL;

Modified: LinuxBIOSv3/include/device/device.h
===================================================================
--- LinuxBIOSv3/include/device/device.h	2007-07-07 09:34:56 UTC (rev 436)
+++ LinuxBIOSv3/include/device/device.h	2007-07-07 19:19:44 UTC (rev 437)
@@ -257,6 +257,9 @@
 #define DEVICE_IO_ALIGN 16 
 #define DEVICE_MEM_ALIGN 4096
 
+resource_t align_up(resource_t val, unsigned long gran);
+resource_t align_down(resource_t val, unsigned long gran);
+
 extern struct device_operations default_dev_ops_root;
 
 extern int id_eq(struct device_id *id1, struct device_id *id2);




From uwe at hermann-uwe.de  Sat Jul  7 21:21:18 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 7 Jul 2007 21:21:18 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop superfluous round()
In-Reply-To: <20070706174412.GD3605@coresystems.de>
References: <20070706143440.GA8383@greenwood>
	<20070706174412.GD3605@coresystems.de>
Message-ID: <20070707192117.GB5859@greenwood>

On Fri, Jul 06, 2007 at 07:44:12PM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070706 16:34]:
> > See patch.
> > 
> > Do we want align_up()/align_down() in lib.c maybe?
> 
> Since it operates on resources, I think no.

It's not specific to resources, though. We could change it to operate
on u64 variables, I think that should work fine. I'll see if I can
make a patch.


> Acked-by: Stefan Reinauer <stepan at coresystems.de>

Thanks, r437.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Sat Jul  7 21:26:28 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 7 Jul 2007 21:26:28 +0200
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <468D9309.70200@lemote.com>
References: <468CA4E3.7070501@lemote.com> <468CF0AB.8020304@lemote.com>
	<468D018D.7040701@lemote.com>
	<57947bf80707050914l61b6c96cybb031f952c7a1abc@mail.gmail.com>
	<468D9309.70200@lemote.com>
Message-ID: <20070707192628.GC5859@greenwood>

On Fri, Jul 06, 2007 at 08:55:37AM +0800, Songmao Tian wrote:
> Actually, we are using a non-Geode CPU(in fact it's a mips varient). I 
> understand the situation, luckily I got
> helps from all of you:), thanks again.
> 
> Perhaps I will try to port the LinuxBIOS, but if so, I have to port 
> another payload(I am looking into grub2, any other sugguestion?)

GRUB2 is being worked on as part of Google Summer of Code, so that
should work soonish...

If you want to port LinuxBIOS to MIPS (which would be great!), please
start with LinuxBIOSv3, which is still in early development stages but
is a _lot_ better and easier to handle from a development (and user!)
point of view.

Other than that, the "typical" payloads in LinuxBIOS are FILO (to boot
from disk, for example) or memtest86 (for testing the RAM setup while
developing). I don't know whether either of them support MIPS (guess not).


> and u-boot is another good option.

Yeah, I've been wondering about this, too. But doesn't u-boot do pretty
much the same we do in LinuxBIOS (just for other, mainly embedded boards)?

Or can it be configured to basically _not_ init the system (and leave
that part to LinuxBIOS), but only provide a "shell" of some sort for
configuration stuff (sorry, I haven't yet played much with u-boot).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Sat Jul  7 23:18:47 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  7 Jul 2007 23:18:47 +0200
Subject: [LinuxBIOS] r438 - LinuxBIOSv3/arch/x86/geodelx
Message-ID: <mailman.504.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-07 23:18:47 +0200 (Sat, 07 Jul 2007)
New Revision: 438

Modified:
   LinuxBIOSv3/arch/x86/geodelx/cpu.c
   LinuxBIOSv3/arch/x86/geodelx/geodelx.c
   LinuxBIOSv3/arch/x86/geodelx/stage0.S
   LinuxBIOSv3/arch/x86/geodelx/stage1.c
Log:
Various coding style fixes, typo fixes, and other cosmetic changes (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/arch/x86/geodelx/cpu.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/cpu.c	2007-07-07 19:19:44 UTC (rev 437)
+++ LinuxBIOSv3/arch/x86/geodelx/cpu.c	2007-07-07 21:18:47 UTC (rev 438)
@@ -22,10 +22,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This is a test for the idea of a cpu device. There is only ever
- * going to be one CPU device, the bootstrap processor or BP; other
- * processors will go through a different path.  on Geode it is
- * really simple, so we start with that. Later, it gets harder.
+/* This is a test for the idea of a CPU device. There is only ever going to
+ * be one CPU device, the bootstrap processor or BP; other processors will
+ * go through a different path. On Geode it is really simple, so we start
+ * with that. Later, it gets harder.
  */
 
 #include <console.h>
@@ -35,35 +35,38 @@
 #include <io.h>
 #include <cpu.h>
 
-/* TODO: better comment on vsm_end_post_smi, and define 0x05a2 down below */
-/** 
+/* TODO: Better comment on vsm_end_post_smi, and define 0x05a2 down below. */
+
+/**
  * This is a call to the VSM.
- * We need to know what it does. 
+ *
+ * TODO: We need to know what it does.
  */
 static void vsm_end_post_smi(void)
 {
-	__asm__ volatile ("push %ax\n"
-			  "mov $0x5000, %ax\n"
-			  ".byte 0x0f, 0x38\n" "pop %ax\n");
+	__asm__ volatile("push %ax\n"
+			 "mov $0x5000, %ax\n"
+			 ".byte 0x0f, 0x38\n"
+			 "pop %ax\n");
 }
 
 /**
- * The very last steps in lx init. Turn on caching, 
- * tell vsm that we are done. Turn A20 back on in 
- * case VSM turned it off. 
- * @param dev struct device pointer
+ * The very last steps in LX init. Turn on caching, tell VSM that we are
+ * done. Turn A20 back on in case VSM turned it off.
+ *
+ * @param dev The device to use.
  */
 static void lx_init(struct device *dev)
 {
-	printk(BIOS_SPEW, "lx_init\n");
+	printk(BIOS_SPEW, "CPU lx_init\n");
 
-	/* Turn on caching if we haven't already */
+	/* Turn on caching if we haven't already. */
 	enable_cache();
 
-	// do VSA late init
+	/* Do VSA late init. */
 	vsm_end_post_smi();
 
-	// Set gate A20 (legacy vsm disables it in late init)
+	/* Set gate A20 (legacy VSM disables it in late init). */
 	printk(BIOS_SPEW, "A20 (0x92): %d\n", inb(0x92));
 	outb(0x02, 0x92);
 	printk(BIOS_SPEW, "A20 (0x92): %d\n", inb(0x92));
@@ -71,30 +74,34 @@
 	printk(BIOS_SPEW, "CPU lx_init DONE\n");
 };
 
-/* The only operations currently set up are the phase 6. We might,
- * however, set up an op in phase3_scan to get the cpuinfo into a
- * struct for all to see.  On SMP, it would not be hard to have
- * phase3 scan set up an array of such structs.  Further, for systems
- * which have multiple types of CPUs, you can compile in multiple CPU
- * files and use the device id, at scan time, to pick which one is
- * used. There is a lot of flexibility here!
+/**
+ * The only operations currently set up are the phase 6. We might, however,
+ * set up an op in phase3_scan to get the cpuinfo into a struct for all to
+ * see. On SMP, it would not be hard to have phase3_scan set up an array of
+ * such structs.
+ *
+ * Further, for systems which have multiple types of CPUs, you can compile
+ * in multiple CPU files and use the device ID, at scan time, to pick which
+ * one is used. There is a lot of flexibility here!
  */
 struct device_operations geodelx_cpuops = {
-	.constructor		 = default_device_constructor,
-	.phase3_scan		 = NULL,
-	.phase6_init		 = lx_init,
+	.constructor	= default_device_constructor,
+	.phase3_scan	= NULL,
+	.phase6_init	= lx_init,
 };
 
-/* This is a constructor for a cpu. the PCI id works for now. 
-  * Later, we might need to change it to use a different phase3 scan, 
-  * and match on a cpu id. However, CPU IDs are known to be kind
-  * of weird, depending on date manufactured they can be all 
-  * over the place (the Geode alone has had 3 vendors!) so
-  * we will have to be careful
-  */
+/**
+ * This is a constructor for a CPU.
+ *
+ * Later, we might need to change it to use a different phase3_scan, and
+ * match on a CPU ID. However, CPU IDs are known to be kind of weird,
+ * depending on date manufactured they can be all over the place (the Geode
+ * alone has had 3 vendors!) so we will have to be careful.
+ */
 struct constructor geodelx_constructors[] = {
-  {.id = {.type = DEVICE_ID_PCI,
-	  .u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},
-   .ops = &geodelx_cpuops},
-  {.ops = 0},
+	{.id = {.type = DEVICE_ID_PCI,
+		/* TODO: This is incorrect, these are _not_ PCI IDs! */
+		.u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},
+	 .ops = &geodelx_cpuops},
+	{.ops = 0},
 };

Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-07 19:19:44 UTC (rev 437)
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-07 21:18:47 UTC (rev 438)
@@ -28,71 +28,73 @@
 #include <string.h>
 #include <msr.h>
 #include <io.h>
+#include <hlt.h>
 #include <amd_geodelx.h>
 #include <spd.h>
 #include <legacy.h>
 
-/* all these functions used to be in a lot of fiddly little files.  To
-  * make it easier to find functions, we are merging them here. This
-  * file is our first real cpu-specific support file and should serve
-  * as a model for v3 cpu-specific support. So, warning, you might
-  * think it makes sense to split this file up, but we've tried that,
-  * and it sucks.
-  */
+/* All these functions used to be in a lot of fiddly little files. To make it
+ * easier to find functions, we are merging them here. This file is our first
+ * real CPU-specific support file and should serve as a model for v3
+ * CPU-specific support.
+ *
+ * So, warning, you might think it makes sense to split this file up, but
+ * we've tried that, and it sucks.
+ */
 
-/** 
-  * Starts Timer 1 for port 61 use.
-  *
-  * The command 0x56 means write counter 1 lower 8 bits in next IO,
-  * set the counter mode to square wave generator (count down to 0
-  * from programmed value twice in a row, alternating the output signal)
-  * counting in 16-bit binary mode.
-  *
-  * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh
-  * approximately every 15us.
-  *
-  * The PIT typically is generating 1.19318 MHz
-  * Timer 1 was used for RAM refresh on XT/AT and can be read on port61.
-  * Port61 is used by many timing loops for calibration.
-  */
+/**
+ * Starts Timer 1 for port 61 use.
+ *
+ * The command 0x56 means write counter 1 lower 8 bits in next I/O, set the
+ * counter mode to square wave generator (count down to 0 from programmed
+ * value twice in a row, alternating the output signal) counting in 16-bit
+ * binary mode.
+ *
+ * 0x12 is counter/timer 1 and signals the PIT to do a RAM refresh
+ * approximately every 15us.
+ *
+ * The PIT typically is generating 1.19318 MHz.
+ *
+ * Timer 1 was used for RAM refresh on XT/AT and can be read on port 61.
+ * Port 61 is used by many timing loops for calibration.
+ */
 void start_timer1(void)
 {
 	outb(0x56, I82C54_CONTROL_WORD_REGISTER);
 	outb(0x12, I82C54_COUNTER1);
 }
 
-/** 
-  * system_preinit Very early initialization needed for almost
-  * everything else.  Currently, all we do is start timer1.
-  */
+/**
+ * Very early initialization needed for almost everything else.
+ * Currently, all we do is start timer1.
+ */
 void system_preinit(void)
 {
 	start_timer1();
 }
 
+/* CPU bug management */
 
-/* cpu bug management */
 /**
+ * Bugtool #465 and #609 PCI cache deadlock.
+ * TODO: URL?
  *
- *	pci_deadlock Bugtool #465 and #609 PCI cache deadlock There is
- *	also fix code in cache and PCI functions. This bug is very is
- *	pervasive.
- *
+ * There is also fix code in cache and PCI functions. This bug is very is
+ * pervasive.
  */
 static void pci_deadlock(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
-	/*
-	 * forces serialization of all load misses. Setting this bit prevents the 
-	 * DM pipe from backing up if a read request has to be held up waiting 
-	 * for PCI writes to complete.
+	/* Forces serialization of all load misses. Setting this bit prevents
+	 * the DM pipe from backing up if a read request has to be held up
+	 * waiting for PCI writes to complete.
 	 */
 	msr = rdmsr(CPU_DM_CONFIG0);
 	msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
 	wrmsr(CPU_DM_CONFIG0, msr);
 
-	/* write serialize memory hole to PCI. Need to unWS when something is 
+	/* Write serialize memory hole to PCI. Need to unWS when something is
 	 * shadowed regardless of cachablility.
 	 */
 	msr.lo = 0x021212121;
@@ -102,16 +104,16 @@
 	wrmsr(CPU_RCONF_E0_FF, msr);
 }
 
-/**	disable_memory_reorder PBZ 3659: The MC reordered transactions
-  *	incorrectly and breaks coherency.  Disable reording and take a
-  *	potential performance hit.  This is safe to do here and not in
-  *	MC init since there is nothing to maintain coherency with and
-  *	the cache is not enabled yet.
-  */
-/****************************************************************************/
+/**
+ * PBZ 3659: The MC reordered transactions incorrectly and breaks coherency.
+ *
+ * Disable reording and take a potential performance hit. This is safe to do
+ * here and not in MC init, since there is nothing to maintain coherency with
+ * and the cache is not enabled yet.
+ */
 static void disable_memory_reorder(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	msr = rdmsr(MC_CF8F_DATA);
 	msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
@@ -119,55 +121,61 @@
 }
 
 /**
-  * Fix up register settings to manage known CPU bugs.  For cpu
-  * version C3. Should be the only released version
-  */
+ * Fix up register settings to manage known CPU bugs.
+ *
+ * For CPU version C3. Should be the only released version.
+ */
 void cpu_bug(void)
 {
 	pci_deadlock();
 	disable_memory_reorder();
-	printk(BIOS_DEBUG, "Done cpubug fixes \n");
+	printk(BIOS_DEBUG, "Done cpubug fixes\n");
 }
 
 /**
- * Reset the phase locked loop hardware. After power on as part of
- * this operation, we have to set the clock hardware and reboot. Thus,
- * we have to know if we have been here before. To do this, we use the
- * RSTPLL_LOWER_SWFLAGS_SHIFT flag in the msrGlcpSysRstpll. Also, the
- * clocks can either be configured via passed-in parameters or
- * hardware straps. Once set, we yank the hardware reset line and
- * hlt. We should never reach the hlt, but one never knows.
+ * Reset the phase locked loop (PLL) hardware.
  *
- * @param manualconf If non-zero, use passed-in parameters to
- * determine how to configure pll -- manual or automagic. 
- * If manual, use passed-in parameters pll_hi and pll_lo
- * @param pll_hi value to use for the high 32 bits of the pll msr
- * @param pll_lo value to use for the low 32 bits of the pll msr
+ * After power on as part of this operation, we have to set the clock
+ * hardware and reboot. Thus, we have to know if we have been here before.
+ *
+ * To do this, we use the RSTPLL_LOWER_SWFLAGS_SHIFT flag in the
+ * msrGlcpSysRstpll. Also, the clocks can either be configured via passed-in
+ * parameters or hardware straps. Once set, we yank the hardware reset line
+ * and hlt. We should never reach the hlt, but one never knows.
+ *
+ * @param manualconf If non-zero, use passed-in parameters to determine how
+ *                   to configure PLL -- manual or automagic. If manual, use
+ *                   passed-in parameters pll_hi and pll_lo.
+ * @param pll_hi Value to use for the high 32 bits of the PLL msr.
+ * @param pll_lo Value to use for the low 32 bits of the PLL msr.
  */
 void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
 {
-	struct msr  msr_glcp_sys_pll; /* GeodeLink PLL control MSR */
+	struct msr msr_glcp_sys_pll;	/* GeodeLink PLL control MSR */
 
 	msr_glcp_sys_pll = rdmsr(GLCP_SYS_RSTPLL);
 
-	printk(BIOS_DEBUG, 
-		"_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
+	printk(BIOS_DEBUG,
+	       "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n",
+	       msr_glcp_sys_pll.hi, msr_glcp_sys_pll.lo);
 	post_code(POST_PLL_INIT);
 
 	if (!(msr_glcp_sys_pll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
-		printk(BIOS_DEBUG,"Configuring PLL\n");
+		printk(BIOS_DEBUG, "Configuring PLL\n");
 		if (manualconf) {
 			post_code(POST_PLL_MANUAL);
-			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
+			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
 			msr_glcp_sys_pll.hi = pll_hi;
 
 			/* Hold Count - how long we will sit in reset */
 			msr_glcp_sys_pll.lo = pll_lo;
 		} else {
-			/*automatic configuration (straps) */
+			/* Automatic configuration (straps) */
 			post_code(POST_PLL_STRAP);
-			/* Hold 0xDE * 16 clocks during reset. */
-			/* AMD recomended value for PLL reset from silicon validation. */
+
+			/* Hold 0xDE * 16 clocks during reset. AMD recomended
+			 * value for PLL reset from silicon validation.
+			 */
 			msr_glcp_sys_pll.lo &=
 			    ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
 			msr_glcp_sys_pll.lo |=
@@ -178,79 +186,81 @@
 			msr_glcp_sys_pll.lo |=
 			    RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
 		}
-		/* Use SWFLAGS to remember: "we've already been here"  */
+
+		/* Use SWFLAGS to remember: "we've already been here". */
 		msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
 
-		/* "reset the chip" value */
+		/* "Reset the chip" value */
 		msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
 		wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll);
 
-		/*      You should never get here..... The chip has reset. */
-		printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n");
+		/* You should never get here... the chip has reset. */
+		printk(BIOS_EMERG, "CONFIGURING PLL FAILURE -- HALT\n");
 		post_code(POST_PLL_RESET_FAIL);
-		__asm__ __volatile__("hlt\n");
+		hlt();
+	}
 
-	}
 	printk(BIOS_DEBUG, "Done pll_reset\n");
 	return;
 }
 
-
 /**
  * Return the CPU clock rate from the PLL MSR.
- * @return CPU speed in MHz
+ *
+ * @return CPU speed in MHz.
  */
 u32 cpu_speed(void)
 {
 	u32 speed;
-	struct msr  msr;
+	struct msr msr;
 
 	msr = rdmsr(GLCP_SYS_RSTPLL);
-	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10;
-	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) {
+	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT)
+		  & RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) / 10;
+	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT)
+		& RSTPLL_UPPER_CPUMULT_MASK) + 1) * 333) % 10) > 5) {
 		++speed;
 	}
-	return (speed);
+	return speed;
 }
 
 /**
  * Return the GeodeLink clock rate from the PLL MSR.
- * @return GeodeLink speed in MHz
+ *
+ * @return GeodeLink speed in MHz.
  */
 u32 geode_link_speed(void)
 {
-	unsigned int speed;
-	struct msr  msr;
+	u32 speed;
+	struct msr msr;
 
 	msr = rdmsr(GLCP_SYS_RSTPLL);
-	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10;
-	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) {
+	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT)
+		   & RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) / 10;
+	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT)
+		& RSTPLL_UPPER_GLMULT_MASK) + 1) * 333) % 10) > 5) {
 		++speed;
 	}
-	return (speed);
+	return speed;
 }
 
-
 /**
  * Return the PCI bus clock rate from the PLL MSR.
- * @return PCI speed in MHz
+ *
+ * @return PCI speed in MHz.
  */
 u32 pci_speed(void)
 {
-	struct msr  msr;
+	struct msr msr = rdmsr(GLCP_SYS_RSTPLL);
 
-	msr = rdmsr(GLCP_SYS_RSTPLL);
-	if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {
-		return (66);
-	} else {
-		return (33);
-	}
+	if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT))
+		return 66;
+	else
+		return 33;
 }
 
-
 /**
- * Delay Control Settings Table from AMD (MCP 0x4C00000F)
- * =========================================================================
+ * Delay Control Settings table from AMD (MCP 0x4C00000F).
  */
 const struct delay_controls {
 	u8 dimms;
@@ -259,55 +269,56 @@
 	u32 slow_low;
 	u32 fast_hi;
 	u32 fast_low;
-} delay_control_table [] = {
+} delay_control_table[] = {
 	/* DIMMs Devs Slow (<=333MHz)            Fast (>334MHz) */
-	{ 1,     4,   0x0837100FF, 0x056960004,  0x0827100FF, 0x056960004 },
-	{ 1,     8,   0x0837100AA, 0x056960004,  0x0827100AA, 0x056960004 },
-	{ 1,     16,  0x0837100AA, 0x056960004,  0x082710055, 0x056960004 },
-	{ 2,     8,   0x0837100A5, 0x056960004,  0x082710000, 0x056960004 },
-	{ 2,     16,  0x0937100A5, 0x056960004,  0x0C27100A5, 0x056960004 },
-	{ 2,     20,  0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
-	{ 2,     24,  0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
-	{ 2,     32,  0x0B37100A5, 0x056960004,  0x0B2710000, 0x056960004 },
+	{   1,     4, 0x0837100FF, 0x056960004,  0x0827100FF, 0x056960004 },
+	{   1,     8, 0x0837100AA, 0x056960004,  0x0827100AA, 0x056960004 },
+	{   1,    16, 0x0837100AA, 0x056960004,  0x082710055, 0x056960004 },
+	{   2,     8, 0x0837100A5, 0x056960004,  0x082710000, 0x056960004 },
+	{   2,    16, 0x0937100A5, 0x056960004,  0x0C27100A5, 0x056960004 },
+	{   2,    20, 0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
+	{   2,    24, 0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
+	{   2,    32, 0x0B37100A5, 0x056960004,  0x0B2710000, 0x056960004 },
 };
-/**
- *  - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
- *    in slot 0, but it should be clear for all 2 DIMM settings and if a
- *    single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
+
+/*
+ * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
+ * in slot 0, but it should be clear for all 2 DIMM settings and if a
+ * single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
  *
- *    Settings for single DIMM and no VTT termination (Like db800 platform)
- *     0xF2F100FF 0x56960004
- *     -------------------------------------
- *    ADDR/CTL have 22 ohm series R
- *    DQ/DQM/DQS have 33 ohm series R
+ * Settings for single DIMM and no VTT termination (like DB800 platform)
+ * 0xF2F100FF 0x56960004
+ * -------------------------------------
+ * ADDR/CTL have 22 ohm series R
+ * DQ/DQM/DQS have 33 ohm series R
  */
 
-
 /**
- * set_delay_control. This is Black Magic DRAM timing
- * juju(http://www.thefreedictionary.com/juju) Dram delay depends on
- * cpu clock, memory bus clock, memory bus loading, memory bus
- * termination, your middle initial (ha! caught you!), Geode Link
- * clock rate, and dram timing specifications. From this the code
- * computes a number which is "known to work". No, hardware is not an
- * exact science. And, finally, if an FS2 (jtag debugger) is hooked
- * up, then just don't to anything. This code was written by a master
+ * This is Black Magic DRAM timing juju[1].
+ *
+ * DRAM delay depends on CPU clock, memory bus clock, memory bus loading,
+ * memory bus termination, your middle initial (ha! caught you!), GeodeLink
+ * clock rate, and DRAM timing specifications.
+ *
+ * From this the code computes a number which is "known to work". No,
+ * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
+ * is hooked up, then just don't do anything. This code was written by a master
  * of the Dark Arts at AMD and should not be modified in any way.
  * 
- * @param num_banks How many banks of DRAM there are
- * @param dimm0 DIMM 0 SMBus address
- * @param dimm1 DIMM 1 SMBus address
- * @param sram_width Data width of the SDRAM
+ * [1] (http://www.thefreedictionary.com/juju)
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent).
  */
 void set_delay_control(u8 dimm0, u8 dimm1)
 {
 	u32 msrnum, glspeed;
 	u8 spdbyte0, spdbyte1, dimms, i;
-	struct msr  msr;
+	struct msr msr;
 
 	glspeed = geode_link_speed();
 
-	/* fix delay controls for DM and IM arrays */
+	/* Fix delay controls for DM and IM arrays. */
 	msrnum = CPU_BC_MSS_ARRAY_CTL0;
 	msr.hi = 0;
 	msr.lo = 0x2814D352;
@@ -328,33 +339,32 @@
 	msr.hi = 0x00000005;
 	wrmsr(msrnum, msr);
 
-	/* Enable setting */
+	/* Enable setting. */
 	msrnum = CPU_BC_MSS_ARRAY_CTL_ENA;
 	msr.hi = 0;
 	msr.lo = 0x00000001;
 	wrmsr(msrnum, msr);
 
-	/* Debug Delay Control Setup Check
-	  * 
-	  *  Leave it alone if it has been setup. FS2 or something is here. 
-	  */
+	/* Debug Delay Control setup check.
+	 * Leave it alone if it has been setup. FS2 or something is here.
+	 */
 	msrnum = GLCP_DELAY_CONTROLS;
 	msr = rdmsr(msrnum);
-	if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) {
+	if (msr.lo & ~(DELAY_LOWER_STATUS_MASK))
 		return;
-	}
 
-	/*
-	 * Delay Controls based on DIMM loading. UGH!
-	 * # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
-	 * Note - We only support module width of 64.
+	/* Delay Controls based on DIMM loading. UGH!
+	 * Number of devices = module width (SPD 6) / device width (SPD 13)
+	 *                     * physical banks (SPD 5)
+	 *
+	 * Note: We only support a module width of 64.
 	 */
 	dimms = 0;
 	spdbyte0 = smbus_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH);
 	if (spdbyte0 != 0xFF) {
 		dimms++;
-		spdbyte0 = (unsigned char)64 / spdbyte0 *
-		    (unsigned char)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS));
+		spdbyte0 = (u8)64 / spdbyte0 *
+			   (u8)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS));
 	} else {
 		spdbyte0 = 0;
 	}
@@ -362,25 +372,24 @@
 	spdbyte1 = smbus_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH);
 	if (spdbyte1 != 0xFF) {
 		dimms++;
-		spdbyte1 = (unsigned char)64 / spdbyte1 *
-		    (unsigned char)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS));
+		spdbyte1 = (u8)64 / spdbyte1 *
+			   (u8)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS));
 	} else {
 		spdbyte1 = 0;
 	}
 
-	/* zero GLCP_DELAY_CONTROLS MSR */
+	/* Zero GLCP_DELAY_CONTROLS MSR */
 	msr.hi = msr.lo = 0;
 
-	/* save some power, disable clock to second DIMM if it is empty */
-	if (spdbyte1 == 0) {
+	/* Save some power, disable clock to second DIMM if it is empty. */
+	if (spdbyte1 == 0)
 		msr.hi |= DELAY_UPPER_DISABLE_CLK135;
-	}
 
 	spdbyte0 += spdbyte1;
 
 	for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
 		if ((dimms == delay_control_table[i].dimms) &&
-				(spdbyte0 <= delay_control_table[i].devices)) {
+		    (spdbyte0 <= delay_control_table[i].devices)) {
 			if (glspeed < 334) {
 				msr.hi |= delay_control_table[i].slow_hi;
 				msr.lo |= delay_control_table[i].slow_low;
@@ -395,29 +404,28 @@
 }
 
 /**
- * cpu_reg_init. All cpu register settings, here in one place, and
- * done in the proper order.
+ * All CPU register settings, here in one place, and done in the proper order.
  *
- * @param debug_clock_disable Disable the debug clock to save power. Currently ignored, but we need to 
- * pick this up from a CMOS setting in future. 
- * @param dimm0 SMBus address of dimm0 (mainboard dependent)
- * @param dimm1 SMBus address of dimm1 (mainboard dependent)
+ * @param debug_clock_disable Disable the debug clock to save power. Currently
+ *                            ignored, but we need to pick this up from a CMOS
+ *                            setting in future.
+ * @param dimm0 SMBus address of DIMM 0 (mainboard dependent).
+ * @param dimm1 SMBus address of DIMM 1 (mainboard dependent).
  */
 void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1)
 {
 	int msrnum;
-	struct msr  msr;
+	struct msr msr;
 
 	/* Castle 2.0 BTM periodic sync period. */
-	/*      [40:37] 1 sync record per 256 bytes */
+	/* [40:37] 1 sync record per 256 bytes. */
 	msrnum = CPU_PF_CONF;
 	msr = rdmsr(msrnum);
 	msr.hi |= (0x8 << 5);
 	wrmsr(msrnum, msr);
 
-	/*
-	   ; Castle performance setting.
-	   ; Enable Quack for fewer re-RAS on the MC
+	/* Castle performance setting.
+	 * Enable Quack for fewer re-RAS on the MC.
 	 */
 	msrnum = GLIU0_ARB;
 	msr = rdmsr(msrnum);
@@ -431,45 +439,49 @@
 	msr.hi |= ARB_UPPER_QUACK_EN_SET;
 	wrmsr(msrnum, msr);
 
-	/*      GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
+	/* GLIU port active enable, limit south pole masters (AES and PCI) to
+	 * one outstanding transaction.
+	 */
 	msrnum = GLIU1_PORT_ACTIVE;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0x880;
 	wrmsr(msrnum, msr);
 
-	/* Set the Delay Control in GLCP */
+	/* Set the Delay Control in GLCP. */
 	set_delay_control(dimm0, dimm1);
 
-	/*  Enable RSDC */
+	/* Enable RSDC. */
 	msrnum = CPU_AC_SMM_CTL;
 	msr = rdmsr(msrnum);
 	msr.lo |= SMM_INST_EN_SET;
 	wrmsr(msrnum, msr);
 
-	/* FPU imprecise exceptions bit */
+	/* FPU imprecise exceptions bit. */
 	msrnum = CPU_FPU_MSR_MODE;
 	msr = rdmsr(msrnum);
 	msr.lo |= FPU_IE_SET;
 	wrmsr(msrnum, msr);
 
-	/* Power Savers (Do after BIST) */
-	/* Enable Suspend on HLT & PAUSE instructions */
+	/* Power savers (do after BIST). */
+	/* Enable Suspend on HLT & PAUSE instructions. */
 	msrnum = CPU_XC_CONFIG;
 	msr = rdmsr(msrnum);
 	msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
 	wrmsr(msrnum, msr);
 
-	/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
+	/* Enable SUSP and allow TSC to run in Suspend (keep speed
+	 * detection happy).
+	 */
 	msrnum = CPU_BC_CONF_0;
 	msr = rdmsr(msrnum);
 	msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
 	msr.lo &= 0x0F0FFFFFF;
-	msr.lo |= 0x002000000;	/* PBZ213: Set PAUSEDLY = 2 */
+	msr.lo |= 0x002000000;	/* PBZ213: Set PAUSEDLY = 2. */
 	wrmsr(msrnum, msr);
 
 	/* Disable the debug clock to save power. */
-	/* NOTE: leave it enabled for fs2 debug */
-	if (debug_clock_disable && 0){
+	/* Note: Leave it enabled for FS2 debug. */
+	if (debug_clock_disable && 0) {
 		msrnum = GLCP_DBGCLKCTL;
 		msr.hi = 0;
 		msr.lo = 0;
@@ -481,7 +493,8 @@
 	msr.hi = 0;
 	msr.lo = 0x00000603C;
 	wrmsr(msrnum, msr);
-	/* fix cpu bugs */
+
+	/* Fix CPU bugs. */
 #warning testing fixing bugs in initram
 	cpu_bug();
 }

Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/stage0.S	2007-07-07 19:19:44 UTC (rev 437)
+++ LinuxBIOSv3/arch/x86/geodelx/stage0.S	2007-07-07 21:18:47 UTC (rev 438)
@@ -1,29 +1,29 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
-## Copyright (C) 2005 Eswar Nallusamy, LANL
-## Copyright (C) 2005 Tyan
-## (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2005 Eswar Nallusamy, LANL
+ * Copyright (C) 2005 Tyan
+ * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
+ * Copyright (C) 2007 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
-/* Init code - Switch CPU to protected mode and enable Cache-as-Ram. */
+/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
 
 #include "../macros.h"
 #include <amd_geodelx.h>
@@ -31,20 +31,20 @@
 /* This is where the DCache will be mapped and be used as stack. It would be
  * cool if it was the same base as LinuxBIOS normal stack.
  */
-#define	LX_STACK_BASE		DCACHE_RAM_BASE
-#define	LX_STACK_END		LX_STACK_BASE+(DCACHE_RAM_SIZE-4)
+#define LX_STACK_BASE		DCACHE_RAM_BASE
+#define LX_STACK_END		LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
 
-#define	LX_NUM_CACHELINES	0x080	/* There are 128 lines per way. */
-#define	LX_CACHELINE_SIZE	0x020	/* There are 32 bytes per line. */
-#define	LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
-#define	CR0_CD			0x40000000 /* Bit 30 = Cache Disable */
-#define	CR0_NW			0x20000000 /* Bit 29 = Not Write Through */
+#define LX_NUM_CACHELINES	0x080	/* There are 128 lines per way. */
+#define LX_CACHELINE_SIZE	0x020	/* There are 32 bytes per line. */
+#define LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
+#define CR0_CD			0x40000000 /* Bit 30 = Cache Disable */
+#define CR0_NW			0x20000000 /* Bit 29 = Not Write Through */
 
-#define ROM_CODE_SEG 0x08
-#define ROM_DATA_SEG 0x10
+#define ROM_CODE_SEG		0x08
+#define ROM_DATA_SEG		0x10
 
-#define CACHE_RAM_CODE_SEG 0x18
-#define CACHE_RAM_DATA_SEG 0x20
+#define CACHE_RAM_CODE_SEG	0x18
+#define CACHE_RAM_DATA_SEG	0x20
 
 	.code16
 	.globl _stage0
@@ -54,21 +54,19 @@
 	/* Save the BIST result. */
 	movl	%eax, %ebp;
 
-	/* Thanks to kmliu at sis.com.tw for this TLB fix. */
-	/* IMMEDIATELY invalidate the translation lookaside buffer before
+	/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
 	 * executing any further code. Even though paging is disabled we
 	 * could still get false address translations due to the TLB if we
 	 * didn't invalidate it.
 	 */
-
 	xorl	%eax, %eax
-	movl	%eax, %cr3	/* Invalidate TLB */
+	movl	%eax, %cr3	/* Invalidate TLB. */
 
 	/* Switch to protected mode. */
 
 	/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
 	 * using BFD version 2.15.94.0.2.2 20041220 this works fine without
-	 * all the ld hackery and so on. So leave it as is with this comment. 
+	 * all the ld hackery and so on. So leave it as is with this comment.
 	 */
 
 	data32	lgdt %cs:gdtptr
@@ -84,18 +82,19 @@
 	// port80_post(0x23)
 
 	/* Now we are in protected mode. Jump to a 32 bit code segment. */
-	data32 ljmp    $ROM_CODE_SEG, $protected_stage0
+	data32	ljmp $ROM_CODE_SEG, $protected_stage0
+
 	/* I am leaving this weird jump in here in the event that future gas
 	 * bugs force it to be used.
 	 */
-	#.byte 0x66
+	/* .byte 0x66 */
 	.code32
-	#ljmp    $ROM_CODE_SEG, $protected_stage0
+	/* ljmp	$ROM_CODE_SEG, $protected_stage0 */
 
-	#.code16
-	.align  4
+	/* .code16 */
+	.align 4
 	.globl gdt16
-gdt16 = . - _stage0 
+gdt16 = . - _stage0
 gdt16x:
 	.word	gdt16xend - gdt16x -1	/* Compute the table limit. */
 	.long	gdt16x
@@ -118,22 +117,22 @@
 	 * Let's not worry about this -- optimizing gdt is pointless since
 	 * we're only in it for a little bit.
 	 *
-	 * BTW note the trick below: The GDT points to ITSELF, and the first
+	 * Btw. note the trick below: The GDT points to ITSELF, and the first
 	 * good descriptor is at offset 8. So you word-align the table, and
 	 * then because you chose 8, you get a nice 64-bit aligned GDT entry,
 	 * which is good as this is the size of the entry.
 	 *
-	 * Just in case you ever wonder why people do this. 
+	 * Just in case you ever wonder why people do this.
 	 */
-	.align  4
+	.align 4
 	.globl gdtptr
 	.globl gdt_limit
-gdt_limit = gdt_end - gdt - 1   /* Compute the table limit. */
+gdt_limit = gdt_end - gdt - 1		/* Compute the table limit. */
 
 gdt:
 gdtptr:
-	.word	gdt_end - gdt -1 /* Compute the table limit. */
-	.long	gdt              /* We know the offset. */
+	.word	gdt_end - gdt -1	/* Compute the table limit. */
+	.long	gdt			/* We know the offset. */
 	.word	0
 
 	/* selgdt 0x08, flat code segment */
@@ -153,21 +152,20 @@
 	.byte	0x00, 0x93, 0xcf, 0x00
 gdt_end:
 
-	/*
-	 * When we come here we are in protected mode. We expand the stack
+	/* When we come here we are in protected mode. We expand the stack
 	 * and copy the data segment from ROM to the memory.
 	 *
 	 * After that, we call the chipset bootstrap routine that
 	 * does what is left of the chipset initialization.
 	 *
-	 * NOTE: Aligned to 4 so that we are sure that the prefetch
+	 * Note: Aligned to 4 so that we are sure that the prefetch
 	 * cache will be reloaded.
 	 */
 
 	.align  4
 	.globl protected_stage0
 protected_stage0:
-	// This code was used by v2. TODO
+	/* This code was used by v2. TODO. */
 	lgdt	%cs:gdtptr
 	ljmp	$ROM_CODE_SEG, $__protected_stage0
 
@@ -188,17 +186,18 @@
 	/* Restore the BIST value to %eax. */
 	movl	%ebp, %eax
 
-.align 4
+	.align 4
 	/* Here begins CAR support. */
-	/* This particular code is straight from LinuxBIOS V2. */
+	/* This particular code is straight from LinuxBIOS v2. */
 
 	/* DCacheSetup: Setup data cache for use as RAM for a stack. */
 DCacheSetup:
+	invd
 
-	invd
 	/* Set cache properties. */
 	movl	$CPU_RCONF_DEFAULT, %ecx
 	rdmsr
+
 	/* 1MB system memory in write back 1|00100|00. */
 	movl	$0x010010000, %eax
 	wrmsr
@@ -208,6 +207,7 @@
 	 */
 	movl	CPU_DM_CONFIG0,%ecx
 	rdmsr
+
 	/* TODO: Make consistent with i$ init, either whole reg = 0, or just
 	 * this bit...
 	 */
@@ -258,17 +258,18 @@
 	movl	$CPU_DC_INDEX, %ecx
 	wrmsr
 
-	/* Startaddress for tag of Way0: ebp will hold the incrementing
-	 * address. dont destroy!
+	/* Start address for tag of Way0: ebp will hold the incrementing
+	 * address. Don't destroy!
 	 */
 	movl	$LX_STACK_BASE, %ebp	/* Init to start address. */
-	/* Set valid bit and tag for this Way (B[31:12] : Cache tag value for
+
+	/* Set valid bit and tag for this Way (B[31:12]: Cache tag value for
 	 * line/way curr. selected by CPU_DC_INDEX.
 	 */
 	orl	$1, %ebp
 
 	/* Start tag Ways 0 with 128 lines with 32 bytes each: edi will hold
-	 * the line counter. dont destroy!
+	 * the line counter. Don't destroy!
 	 */
 	movl	$LX_NUM_CACHELINES, %edi
 
@@ -298,12 +299,13 @@
 	movl	$CPU_DC_TAG, %ecx
 	wrmsr
 
-	/* Switch to next line. Lines are in Bits10:4. */
+	/* Switch to next line. Lines are in bits 10:4. */
 	/* When index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is
 	 * not a valid CL anymore!
 	 */
 	movl	$CPU_DC_INDEX, %ecx
 	rdmsr
+
 	/* TODO: Probably would be more elegant to calculate this from
 	 * counter var edi...
 	 */
@@ -325,7 +327,8 @@
 	movl	$CPU_DC_INDEX, %ecx
 	rdmsr
 	addl	$0x01, %eax
-	/* Let's be sure: reset line index Bits10:4. */
+
+	/* Let's be sure: reset line index bits 10:4. */
 	andl	$0xFFFFF80F, %eax
 	wrmsr
 
@@ -371,6 +374,7 @@
 	 */
 	/* Clear the cache, the following code from crt0.S.lb will setup
 	 * a new stack.
+	 * TODO: There is no crt0.S.lb (anymore?).
 	 */
 	wbinvd
 
@@ -387,6 +391,7 @@
 lout:
 	/* Restore the BIST result. */
 	movl	%ebp, %eax
+
 	/* We need to set ebp? No need. */
 	movl	%esp, %ebp
 	pushl	%eax		/* BIST */
@@ -394,40 +399,43 @@
 	/* We will not go back. */
 
 fixed_mtrr_msr:
-	.long   0x250, 0x258, 0x259
-	.long   0x268, 0x269, 0x26A
-	.long   0x26B, 0x26C, 0x26D
-	.long   0x26E, 0x26F
+	.long	0x250, 0x258, 0x259
+	.long	0x268, 0x269, 0x26A
+	.long	0x26B, 0x26C, 0x26D
+	.long	0x26E, 0x26F
 var_mtrr_msr:
-	.long   0x200, 0x201, 0x202, 0x203
-	.long   0x204, 0x205, 0x206, 0x207
-	.long   0x208, 0x209, 0x20A, 0x20B
-	.long   0x20C, 0x20D, 0x20E, 0x20F
-	.long   0x000 /* NULL, end of table */
+	.long	0x200, 0x201, 0x202, 0x203
+	.long	0x204, 0x205, 0x206, 0x207
+	.long	0x208, 0x209, 0x20A, 0x20B
+	.long	0x20C, 0x20D, 0x20E, 0x20F
+	.long	0x000 /* NULL, end of table */
 
-# Reset vector.
+/* Reset vector. */
 
 /*
- * RVECTOR: size of reset vector, default is 0x10
- * RESRVED: size of vpd code, default is 0xf0
- * BOOTBLK: size of bootblock code, default is 0x1f00 (8k-256b)
+ * RVECTOR: Size of reset vector, default is 0x10.
+ * RESRVED: Size of vpd code, default is 0xf0.
+ * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b).
  */
 
 SEGMENT_SIZE = 0x10000
 RVECTOR      = 0x00010
 
-# Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
-# I think we should leave it this way forever, as the bugs come and
-# go -- and come again.
-#	.code16
-#	.section ".rom.text"
+/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
+ * I think we should leave it this way forever, as the bugs come and
+ * go -- and come again.
+ *
+ *	.code16
+ *	.section ".rom.text"
+ */
 .section ".reset", "ax"
 	.globl _resetjump
 _resetjump:
 	/* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
-#	jmp _stage0
-	.byte  0xe9
-	.int   _stage0 - ( . + 2 )
+	/* jmp _stage0 */
+	.byte	0xe9
+	.int	_stage0 - ( . + 2 )
+
 	/* Note: The above jump is hand coded to work around bugs in binutils.
 	 * 5 bytes are used for a 3 byte instruction. This works because x86
 	 * is little endian and allows us to use supported 32 bit relocations
@@ -436,8 +444,8 @@
 	 */
 .byte	0
 
-# Date? ID string? We might want to put something else in here.
+/* Date? ID string? We might want to put something else in here. */
 .ascii DATE
 
-# Checksum.
-#.word	0
+/* Checksum. */
+/* .word 0 */

Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-07 19:19:44 UTC (rev 437)
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-07 21:18:47 UTC (rev 438)
@@ -32,13 +32,15 @@
 #include <spd.h>
 
 /**
-  * geodelx_msr_init Set up Geode LX registers for sane behaviour. Set
-  * all low memory (under 1MB) to write back.  Do some setup for cache
-  * as ram as well.
-  */
+ * Set up Geode LX registers for sane behaviour.
+ *
+ * Set all low memory (under 1MB) to write back. Do some setup for Cache
+ * as Ram (CAR) as well.
+ */
 void geodelx_msr_init(void)
 {
-	struct msr  msr;
+	struct msr msr;
+
 	/* Setup access to the cache for under 1MB. */
 	msr.hi = 0x24fffc02;
 	msr.lo = 0x1000A000;	/* 0-A0000 write back */
@@ -51,7 +53,7 @@
 	wrmsr(CPU_RCONF_E0_FF, msr);
 
 	/* Setup access to the cache for under 640K. */
-	/* Note memory controler not setup yet. */
+	/* Note: Memory controller not setup yet. */
 	msr.hi = 0x20000000;
 	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
 	wrmsr(MSR_GLIU0_BASE1, msr);
@@ -67,6 +69,4 @@
 	msr.hi = 0x20000000;
 	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
 	wrmsr(MSR_GLIU0_BASE2, msr);
-
 }
-




From svn at openbios.org  Sun Jul  8 02:19:27 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  8 Jul 2007 02:19:27 +0200
Subject: [LinuxBIOS] r439 - LinuxBIOSv3/northbridge/amd/geodelx
Message-ID: <mailman.505.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-08 02:19:26 +0200 (Sun, 08 Jul 2007)
New Revision: 439

Modified:
   LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c
   LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c
   LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
Log:
Even more coding style fixes and other cosmetic fixes (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c	2007-07-07 21:18:47 UTC (rev 438)
+++ LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c	2007-07-08 00:19:26 UTC (rev 439)
@@ -30,54 +30,74 @@
 #include <io.h>
 #include <amd_geodelx.h>
 
-/* here is programming for the various MSRs.*/
+/* Here is programming for the various MSRs. */
 #define IM_QWAIT 0x100000
 
-/* set in high nibl */
-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */
+/* Set in high nibble. */
+#define DMCF_WRITE_SERIALIZE_REQUEST	(2 << 12)	/* 2 outstanding */
 
-#define DMCF_SERIAL_LOAD_MISSES  (2)	/* enabled */
+#define DMCF_SERIAL_LOAD_MISSES		2		/* Enabled */
 
-/* these are the 8-bit attributes for controlling RCONF registers
- * RCONF is Region CONFiguraiton, and controls caching and other
- * attributes of a region.  Just like MTRRs, only different.
-  */
-#define CACHE_DISABLE (1<<0)
-#define WRITE_ALLOCATE (1<<1)
-#define WRITE_PROTECT (1<<2)
-#define WRITE_THROUGH (1<<3)
-#define WRITE_COMBINE (1<<4)
-#define WRITE_SERIALIZE (1<<5)
+/* These are the 8-bit attributes for controlling RCONF registers.
+ *
+ * RCONF is Region CONFiguration, and controls caching and other
+ * attributes of a region. Just like MTRRs, only different.
+ */
+#define CACHE_DISABLE		(1 << 0)
+#define WRITE_ALLOCATE		(1 << 1)
+#define WRITE_PROTECT		(1 << 2)
+#define WRITE_THROUGH		(1 << 3)
+#define WRITE_COMBINE		(1 << 4)
+#define WRITE_SERIALIZE		(1 << 5)
 
-/* ram has none of this stuff */
-#define RAM_PROPERTIES (0)
-#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
-#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
-#define MSR_WS_CD_DEFAULT (0x21212121)
+/* RAM has none of this stuff. */
+#define RAM_PROPERTIES		0
+#define DEVICE_PROPERTIES	(WRITE_SERIALIZE|CACHE_DISABLE)
+#define ROM_PROPERTIES		(WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
+#define MSR_WS_CD_DEFAULT	0x21212121
 
 /* RCONF registers 1810-1817 give you 8 registers with which to
  * program protection regions the are region configuration range
  * registers, or RRCF in msr terms, the are a straight base, top
  * address assign, since they are 4k aligned.
  */
-/* so no left-shift needed for top or base */
-#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
-#define RRCF_LOW_CD(base)	RRCF_LOW(base, CACHE_DISABLE)
+/* So no left-shift needed for top or base. */
+#define RRCF_LOW(base, properties)	(base | (1 << 8) | properties)
+#define RRCF_LOW_CD(base)		RRCF_LOW(base, CACHE_DISABLE)
 
-/* build initializer for P2D MSR */
-/* this is complex enough that you are going to need to RTFM if you
- *    really want to understand it.
+/* Build initializer for P2D MSR.
+ *
+ * This is complex enough that you are going to need to RTFM if you
+ * really want to understand it.
  */
-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
+#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \
+		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pbase >> 24), \
+		       .lo = (pbase << 8) | pmask}}
+#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \
+		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \
+			     (poffset << 8) | (pbase >> 24), \
+		       .lo = (pbase << 8) | pmask}}
+#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \
+		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pmax >> 12), \
+		       .lo = (pmax << 20) | pmin}}
+#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \
+		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \
+			     (poffset << 8) | (pmax >> 12), \
+		       .lo = (pmax << 20) | pmin}}
+#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \
+		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (wen), \
+		       .lo = (ren << 16) | (pscbase >> 18)}}
+#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \
+		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (ibase >> 12), \
+		       .lo = (ibase << 20) | imask}}
+#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \
+		{msr, {.hi = (pdid1 << 29) | (bizarro << 28), \
+		       .lo = (en << 24) | (wen << 21) | \
+			     (ren << 20) | (ibase << 3)}}
 
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 
+/* TODO: Should be in some header file? */
 extern void graphics_init(void);
 extern void cpu_bug(void);
 extern void chipsetinit(void);
@@ -90,195 +110,213 @@
 
 struct msr_defaults {
 	int msr_no;
-	struct msr  msr;
+	struct msr msr;
 } msr_defaults[] = {
-	{0x1700, {.hi = 0,.lo = IM_QWAIT}}, 
-	{0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST,
-		  .lo = DMCF_SERIAL_LOAD_MISSES}},
+	{ 0x1700, {.hi = 0,.lo = IM_QWAIT}},
+	{ 0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST,
+		   .lo = DMCF_SERIAL_LOAD_MISSES}},
+
 	/* 1808 will be done down below, so we have to do 180a->1817
-	 * (well, 1813 really) 
+	 * (well, 1813 really).
 	 */
-	/* for 180a, for now, we assume VSM will configure it */
-	/* 180b is left at reset value,a0000-bffff is non-cacheable */
-	/* 180c, c0000-dffff is set to write serialize and non-cachable */
-	/* oops, 180c will be set by cpu bug handling in cpubug.c */
-	//{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
-	/* 180d is left at default, e0000-fffff is non-cached */
-	/* we will assume 180e, the ssm region configuration, is left
-	 * at default or set by VSM */
-	/* we will not set 0x180f, the DMM,yet 
+	/* For 180a, for now, we assume VSM will configure it. */
+	/* 180b is left at reset value, a0000-bffff is non-cacheable. */
+	/* 180c, c0000-dffff is set to write serialize and non-cachable. */
+	/* Oops, 180c will be set by CPU bug handling in cpubug.c. */
+	/* TODO: There's no cpubug.c. */
+	// {0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
+	/* 180d is left at default, e0000-fffff is non-cached. */
+	/* We will assume 180e, the ssm region configuration, is left
+	 * at default or set by VSM.
 	 */
-	//{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
-	//{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
-	//{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
-	//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
-	/* now for GLPCI routing */
+	/* We will not set 0x180f, the DMM, yet. */
+
+	// {0x1810, {.hi = 0xee7ff000,
+	// 	     .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
+	// {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
+	// {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
+	// {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
+
+	/* Now for GLPCI routing. */
+
 	/* GLIU0 */
-	P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),
-	P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
+	P2D_BM(MSR_GLIU0_BASE1,  0x1, 0x0, 0x0, 0xfff80),
+	P2D_BM(MSR_GLIU0_BASE2,  0x1, 0x0, 0x80000, 0xfffe0),
 	P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
+
 	/* GLIU1 */
-	P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
-	P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
-	P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), 
-	{0}
+	P2D_BM(MSR_GLIU1_BASE1,  0x1, 0x0, 0x0, 0xfff80),
+	P2D_BM(MSR_GLIU1_BASE2,  0x1, 0x0, 0x80000, 0xfffe0),
+	P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
+
+	{0},
 };
 
-/** 
-  * Size up ram. All we need to here is read the MSR for DRAM and grab
-  * out the sizing bits.  Note that this code depends on initram
-  * having run. It uses the MSRs, not the SPDs, and the MSRs of course
-  * are set up by initram.
-  */
+/**
+ * Size up ram.
+ *
+ * All we need to do here is read the MSR for DRAM and grab out the sizing
+ * bits. Note that this code depends on initram having run. It uses the MSRs,
+ * not the SPDs, and the MSRs of course are set up by initram.
+ *
+ * @return TODO
+ */
 int sizeram(void)
 {
-	struct msr  msr;
+	struct msr msr;
 	int sizem = 0;
 	unsigned short dimm;
 
 	/* Get the RAM size from the memory controller as calculated
-	 * and set by auto_size_dimm() 
+	 * and set by auto_size_dimm().
 	 */
 	msr = rdmsr(MC_CF07_DATA);
-	printk(BIOS_DEBUG,"sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
-	
-	/* dimm 0 */
+	printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi,
+	       msr.lo);
+
+	/* DIMM 0 */
 	dimm = msr.hi;
-	/* installed? */
+	/* Installed? */
 	if ((dimm & 7) != 7) {
 		/* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
-		sizem = 4 << ((dimm >> 12) & 0x0F);	}
-	
-	/* dimm 1 */
+		sizem = 4 << ((dimm >> 12) & 0x0F);
+	}
+
+	/* DIMM 1 */
 	dimm = msr.hi >> 16;
-	/* installed? */
+	/* Installed? */
 	if ((dimm & 7) != 7) {
 		/* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
 		sizem += 4 << ((dimm >> 12) & 0x0F);
 	}
 
-	printk(BIOS_DEBUG,"sizeram: sizem 0x%xMB\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
+
 	return sizem;
 }
 
-/** 
-  * enable_shadow. Currently not set up. 
-  * @param dev The nortbridge device. 
-  */
-static void enable_shadow(struct device * dev)
+/**
+ * Currently not set up.
+ *
+ * @param dev The nortbridge device.
+ */
+static void enable_shadow(struct device *dev)
 {
 }
 
 /**
-  * init the northbridge pci device. Right now this a no op. We leave
-  * it here as a hook for later use.  
-  * @param dev The nortbridge device.
-  */
-static void geodelx_northbridge_init(struct device * dev)
+ * Initialize the northbridge PCI device.
+ * Right now this a no op. We leave it here as a hook for later use.
+ *
+ * @param dev The nortbridge device.
+ */
+static void geodelx_northbridge_init(struct device *dev)
 {
-	//struct msr  msr;
+	/* struct msr msr; */
 
-	printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
 	enable_shadow(dev);
-	/*
-	 * Swiss cheese
-	 */
-	//msr = rdmsr(MSR_GLIU0_SHADOW);
 
-	//msr.hi |= 0x3;
-	//msr.lo |= 0x30000;
+#if 0
+	/* Swiss cheese */
+	msr = rdmsr(MSR_GLIU0_SHADOW);
 
-	//printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	//printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+	msr.hi |= 0x3;
+	msr.lo |= 0x30000;
+
+	printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+	printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+#endif
 }
 
-/** 
-  * Set resources for the PCI northbridge device. This function is
-  * required due to VSA interactions.
-  * @param dev The nortbridge device. 
-  */
+/**
+ * Set resources for the PCI northbridge device.
+ * This function is required due to VSA interactions.
+ *
+ * @param dev The nortbridge device.
+ */
 void geodelx_northbridge_set_resources(struct device *dev)
 {
 	struct resource *resource, *last;
-	unsigned link;
+	unsigned int link;
 	u8 line;
 
 	last = &dev->resource[dev->resources];
 
 	for (resource = &dev->resource[0]; resource < last; resource++) {
-
-		/* 
-		 * from AMD: do not change the base address, it will
-		 * make the VSA virtual registers unusable
+		/* From AMD: do not change the base address, it will
+		 * make the VSA virtual registers unusable.
 		 */
-		//pci_set_resource(dev, resource);
-		// FIXME: static allocation may conflict with dynamic mappings!
+		// pci_set_resource(dev, resource);
+		// FIXME: Static allocation may conflict with dynamic mappings!
 	}
-	
+
 	for (link = 0; link < dev->links; link++) {
 		struct bus *bus;
 		bus = &dev->link[link];
 		if (bus->children) {
-			printk(BIOS_DEBUG, 
-			       "my_dev_set_resources: phase4_assign_resources %d\n", bus);
+			printk(BIOS_DEBUG,
+			       "my_dev_set_resources: phase4_assign_resources %d\n",
+			       bus);
 			phase4_assign_resources(bus);
 		}
 	}
-	
-	/* set a default latency timer */
+
+	/* Set a default latency timer. */
 	pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
-	
-	/* set a default secondary latency timer */
-	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+
+	/* Set a default secondary latency timer. */
+	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
 		pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
-	}
 
-	/* zero the irq settings */
+	/* Zero the IRQ settings. */
 	line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
-	if (line) {
+	if (line)
 		pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
-	}
 
-	/* set the cache line size, so far 64 bytes is good for everyone */
+	/* Set the cache line size, so far 64 bytes is good for everyone. */
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
 
-
-
-/** 
-  * Set resources for the PCI domain. Just set up basic global ranges
-  * for IO and memory Allocation of sub-resources draws on these
-  * top-level resources in the usual hierarchical manner.
-  * @param dev The nortbridge device. 
-  */
-static void geodelx_pci_domain_read_resources(struct device * dev)
+/**
+ * Set resources for the PCI domain.
+ *
+ * Just set up basic global ranges for I/O and memory. Allocation of
+ * sub-resources draws on these top-level resources in the usual
+ * hierarchical manner.
+ *
+ * @param dev The nortbridge device.
+ */
+static void geodelx_pci_domain_read_resources(struct device *dev)
 {
 	struct resource *resource;
-	printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__);
 
-	/* Initialize the system wide io space constraints */
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
+
+	/* Initialize the system wide I/O space constraints. */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 	resource->limit = 0xffffUL;
 	resource->flags =
-		IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
-	/* Initialize the system wide memory resources constraints */
+	/* Initialize the system wide memory resources constraints. */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 	resource->limit = 0xffffffffULL;
 	resource->flags =
-		IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
-/** 
-  * Create a ram resource, by taking the passed-in size and createing
-  * a resource record.
-  * @param dev the device
-  * @param index a resource index
-  * @param basek base memory address in k
-  * @param sizek size of memory in k
-  */
-static void ram_resource(struct device * dev, unsigned long index,
+/**
+ * Create a RAM resource, by taking the passed-in size and creating
+ * a resource record.
+ *
+ * @param dev The device.
+ * @param index A resource index.
+ * @param basek Base memory address in KB.
+ * @param sizek Size of memory in KB.
+ */
+static void ram_resource(struct device *dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
 	struct resource *resource;
@@ -290,159 +328,169 @@
 	resource->base = ((resource_t) basek) << 10;
 	resource->size = ((resource_t) sizek) << 10;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
-		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
-/** 
-  * Set resources in the pci domain. Also, as a side effect, create a
-  * ram resource in the child which, interestingly enough, is the
-  * north bridge pci device, for later allocation of address space.
-  * @param dev the device
-  */
- static void geodelx_pci_domain_set_resources(struct device * dev)
+/**
+ * Set resources in the PCI domain.
+ *
+ * Also, as a side effect, create a RAM resource in the child which,
+ * interestingly enough, is the northbridge PCI device, for later
+ * allocation of address space.
+ *
+ * @param dev The device.
+ */
+static void geodelx_pci_domain_set_resources(struct device *dev)
 {
 	int idx;
-	struct device * mc_dev;
+	struct device *mc_dev;
 
-	printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
-		/* Report the memory regions */
+		/* Report the memory regions. */
 		idx = 10;
+		/* 0 .. 640 KB */
 		ram_resource(dev, idx++, 0, 640);
-		/* Systop - 1 MB -> KB*/
-		ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024);
+		/* 1 MB .. (Systop - 1 MB) (converted to KB) */
+		ram_resource(dev, idx++, 1024,
+			     (get_systop() - (1 * 1024 * 1024)) / 1024);
 	}
 
 	phase4_assign_resources(&dev->link[0]);
 }
 
 /**
-  * enable the pci domain. A littly tricky on this chipset due to the
-  * VSA interactions.  This must happen before any PCI scans happen.
-  * we do early northbridge init to make sure pci scans will work, but
-  * the weird part is we actually have to run some code in x86 mode to
-  * get the VSM installed, since the VSM actually handles some PCI bus
-  * scan tasks via the System Management Interrupt.  Yes, it gets
-  * tricky ...
-  * @param dev the device
-  */
-static void geodelx_pci_domain_phase2(struct device * dev)
+ * Enable the PCI domain.
+ *
+ * A littly tricky on this chipset due to the VSA interactions. This must
+ * happen before any PCI scans happen. We do early northbridge init to make
+ * sure PCI scans will work, but the weird part is we actually have to run
+ * some code in x86 mode to get the VSM installed, since the VSM actually
+ * handles some PCI bus scan tasks via the System Management Interrupt.
+ * Yes, it gets tricky...
+ *
+ * @param dev The device.
+ */
+static void geodelx_pci_domain_phase2(struct device *dev)
 {
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
-	printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__);
-
 	northbridge_init_early();
 #warning cpu bug has been moved to initram stage
-//	cpu_bug();
+	/* cpu_bug(); */
 	chipsetinit();
 
 	setup_realmode_idt();
 
-	printk(BIOS_DEBUG,"Before VSA:\n");
-	// print_conf();
-#warning Not doing vsm bios -- linux will fail. 
-//	do_vsmbios();		// do the magic stuff here, so prepare your tambourine ;)
+	printk(BIOS_DEBUG, "Before VSA:\n");
+	/* print_conf(); */
+#warning Not doing vsm bios -- linux will fail.
+	/* Do the magic stuff here, so prepare your tambourine ;) */
+	/* do_vsmbios(); */
+	printk(BIOS_DEBUG, "After VSA:\n");
+	/* print_conf(); */
 
-	printk(BIOS_DEBUG,"After VSA:\n");
-	// print_conf();
-
-#warning graphics_init is disabled. 
-//	graphics_init();
+#warning graphics_init is disabled.
+	/* graphics_init(); */
 	pci_set_method(dev);
 }
 
 /**
-  * Support for scan bus from the "tippy top" -- i.e. the pci domain,
-  * not the 0:0.0 device.
-  * @param dev The pci domain device
-  * @param max max number of devices to scan. 
-  */
-static unsigned int geodelx_pci_domain_scan_bus(struct device * dev, unsigned int max)
+ * Support for scan bus from the "tippy top" -- i.e. the PCI domain,
+ * not the 0:0.0 device.
+ *
+ * @param dev The PCI domain device.
+ * @param max Maximum number of devices to scan.
+ */
+static unsigned int geodelx_pci_domain_scan_bus(struct device *dev,
+						unsigned int max)
 {
-	printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
 	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 	return max;
 }
 
-
 /**
-  * Support for apic cluster init. TODO should we do this in phase 2?
-  * It is now done in phase 6
-  * @param dev The pci domain device
-  */
-static void cpu_bus_init(struct device * dev)
+ * Support for APIC cluster init.
+ *
+ * TODO: Should we do this in phase 2? It is now done in phase 6.
+ *
+ * @param dev The PCI domain device.
+ */
+static void cpu_bus_init(struct device *dev)
 {
-	printk(BIOS_SPEW,">> Entering northbridge.c: %s\n", __FUNCTION__);
-	printk(BIOS_SPEW,">> Exiting northbridge.c: %s\n", __FUNCTION__);
-
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
+	printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__);
 }
 
-static void cpu_bus_noop(struct device * dev)
+static void cpu_bus_noop(struct device *dev)
 {
 }
 
-/* the same hardware, being multifunction, has several roles. In this
-  * case, the north is a pci domain controller, apic cluster, and the
-  * traditional 0:0.0 device
-  */
+/* The same hardware, being multifunction, has several roles. In this case,
+ * the northbridge is a PCI domain controller, APIC cluster, and the
+ * traditional 0:0.0 device.
+ */
 
-/* Here are the operations for when the northbridge is running a PCI
- *    domain.
- */
+/** Operations for when the northbridge is running a PCI domain. */
 struct device_operations geodelx_pcidomainops = {
-	.constructor		 = default_device_constructor,
-	.phase2_setup_scan_bus	= geodelx_pci_domain_phase2,
-	.phase3_scan		 = geodelx_pci_domain_scan_bus,
-	.phase4_read_resources	 = geodelx_pci_domain_read_resources,
-	.phase4_set_resources	 = geodelx_pci_domain_set_resources,
-	.phase5_enable_resources = enable_childrens_resources,
-	.phase6_init		 = 0,
-	.ops_pci_bus		 = &pci_cf8_conf1,
-
+	.constructor			= default_device_constructor,
+	.phase2_setup_scan_bus		= geodelx_pci_domain_phase2,
+	.phase3_scan			= geodelx_pci_domain_scan_bus,
+	.phase4_read_resources		= geodelx_pci_domain_read_resources,
+	.phase4_set_resources		= geodelx_pci_domain_set_resources,
+	.phase5_enable_resources	= enable_childrens_resources,
+	.phase6_init			= 0,
+	.ops_pci_bus			= &pci_cf8_conf1,
 };
 
-/* Here are the operations for when the northbridge is running an APIC
- *   cluster.
- */
+/** Operations for when the northbridge is running an APIC cluster. */
 struct device_operations geodelx_apicops = {
-	.constructor		 = default_device_constructor,
-	.phase3_scan		 = 0,
-	.phase4_read_resources	 = cpu_bus_noop,
-	.phase4_set_resources	 = cpu_bus_noop,
-	.phase5_enable_resources = cpu_bus_noop,
-	.phase6_init		 = cpu_bus_init,
-	.ops_pci_bus		 = &pci_cf8_conf1,
+	.constructor			= default_device_constructor,
+	.phase3_scan			= 0,
+	.phase4_read_resources		= cpu_bus_noop,
+	.phase4_set_resources		= cpu_bus_noop,
+	.phase5_enable_resources	= cpu_bus_noop,
+	.phase6_init			= cpu_bus_init,
+	.ops_pci_bus			= &pci_cf8_conf1,
 };
 
-/* Here are the operations for when the northbridge is running a PCI
- * device.
- */
+/** Operations for when the northbridge is running a PCI device. */
 struct device_operations geodelx_pci_ops = {
-	.constructor		 = default_device_constructor,
-	.phase3_scan		 = geodelx_pci_domain_scan_bus,
-	.phase4_read_resources	 = geodelx_pci_domain_read_resources,
-	.phase4_set_resources	 = geodelx_northbridge_set_resources,
-	.phase5_enable_resources = enable_childrens_resources,
-	.phase6_init		 = geodelx_northbridge_init,
-	.ops_pci_bus		 = &pci_cf8_conf1,
-
+	.constructor			= default_device_constructor,
+	.phase3_scan			= geodelx_pci_domain_scan_bus,
+	.phase4_read_resources		= geodelx_pci_domain_read_resources,
+	.phase4_set_resources		= geodelx_northbridge_set_resources,
+	.phase5_enable_resources	= enable_childrens_resources,
+	.phase6_init			= geodelx_northbridge_init,
+	.ops_pci_bus			= &pci_cf8_conf1,
 };
 
+/**
+ * The constructor for the device.
+ * Domain ops and APIC cluster ops and PCI device ops are different.
+ */
+struct constructor geodelx_north_constructors[] = {
+	/* Northbridge running a PCI domain. */
+	{.id = {.type = DEVICE_ID_PCI_DOMAIN,
+		.u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
+				     .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
+	 .ops = &geodelx_pcidomainops},
 
-/* The constructor for the device. */
-/* Domain ops and apic cluster ops and pci device ops are different */
-struct constructor geodelx_north_constructors[] = {
-  {.id = {.type = DEVICE_ID_PCI_DOMAIN,
-	  .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
-   &geodelx_pcidomainops},
-  {.id = {.type = DEVICE_ID_APIC_CLUSTER,
-	  .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
-   &geodelx_apicops},
-  {.id = {.type = DEVICE_ID_PCI,
-	  .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
-   &geodelx_pci_ops},
-  {.ops = 0},
+	/* Northbridge running an APIC cluster. */
+	{.id = {.type = DEVICE_ID_APIC_CLUSTER,
+		.u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,
+				       .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
+	 .ops = &geodelx_apicops},
+
+	/* Northbridge running a PCI device. */
+	{.id = {.type = DEVICE_ID_PCI,
+		.u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+			      .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
+	 .ops = &geodelx_pci_ops},
+
+	{.ops = 0},
 };

Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c	2007-07-07 21:18:47 UTC (rev 438)
+++ LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c	2007-07-08 00:19:26 UTC (rev 439)
@@ -37,21 +37,21 @@
 };
 
 struct gliutable gliu0table[] = {
-	/*  0-7FFFF to MC */
+	/* 0-7FFFF to MC */
 	{.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,
 	 .lo = 0x0FFF80},
-	/*  80000-9ffff to Mc */
+	/* 80000-9FFFF to MC */
 	{.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,
 	 .lo = (0x80 << 20) + 0x0FFFE0},
-	/*  C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff
-	 * handled by SoftVideo 
+	/* C0000-FFFFF split to MC and PCI (sub decode) A0000-BFFFF
+	 * handled by SoftVideo.
 	 */
 	{.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,
 	 .hi = MSR_MC + 0x0,.lo = 0x03},
-	/*  Catch and fix dynamicly. */
+	/* Catch and fix dynamically. */
 	{.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,
 	 .hi = MSR_MC,.lo = 0x0},
-	/*  Catch and fix dynamicly. */
+	/* Catch and fix dynamically. */
 	{.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,
 	 .hi = MSR_MC,.lo = 0x0},
 	{.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,
@@ -60,24 +60,24 @@
 };
 
 struct gliutable gliu1table[] = {
-	/*  0-7FFFF to MC */
+	/* 0-7FFFF to MC */
 	{.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,
 	 .lo = 0x0FFF80},
-	/*  80000-9ffff to Mc */
+	/* 80000-9FFFF to MC */
 	{.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,
 	 .lo = (0x80 << 20) + 0x0FFFE0},
-	/*  C0000-Fffff split to MC and PCI (sub decode) */
+	/* C0000-Fffff split to MC and PCI (sub decode) */
 	{.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,
 	 .hi = MSR_GL0 + 0x0,.lo = 0x03},
-	/*      Catch and fix dynamicly. */
+	/* Catch and fix dynamically. */
 	{.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,
 	 .hi = MSR_GL0,.lo = 0x0},
-	/*      Catch and fix dynamicly. */
+	/* Catch and fix dynamically. */
 	{.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,
 	 .hi = MSR_GL0,.lo = 0x0},
 	{.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,
 	 .hi = 0x0,.lo = GL1_GLIU0},
-	/*  FooGlue FPU 0xF0 */
+	/* FooGlue FPU 0xF0 */
 	{.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,
 	 .hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0},
 	{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
@@ -87,121 +87,116 @@
 
 struct msrinit {
 	unsigned long msrnum;
-	struct msr  msr;
+	struct msr msr;
 };
 
 struct msrinit clock_gating_default[] = {
-	{GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
-	{MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
-	{VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
-	{GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
-	{DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}},
-	{GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
-	{GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}},
-	{GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
-	{VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
-	{AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
-	{CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}},
-	{0xffffffff, {0xffffffff, 0xffffffff}},
+	{GLIU0_GLD_MSR_PM,	{.hi = 0x00,.lo = 0x0005}},
+	{MC_GLD_MSR_PM,		{.hi = 0x00,.lo = 0x0001}},
+	{VG_GLD_MSR_PM,		{.hi = 0x00,.lo = 0x0015}},
+	{GP_GLD_MSR_PM,		{.hi = 0x00,.lo = 0x0001}},
+	{DF_GLD_MSR_PM,		{.hi = 0x00,.lo = 0x0555}},
+	{GLIU1_GLD_MSR_PM,	{.hi = 0x00,.lo = 0x0005}},
+	{GLCP_GLD_MSR_PM,	{.hi = 0x00,.lo = 0x0014}},
+	{GLPCI_GLD_MSR_PM,	{.hi = 0x00,.lo = 0x0015}},
+	{VIP_GLD_MSR_PM,	{.hi = 0x00,.lo = 0x0005}},
+	{AES_GLD_MSR_PM,	{.hi = 0x00,.lo = 0x0015}},
+	{CPU_BC_PMODE_MSR,	{.hi = 0x00,.lo = 0x70303}}, // TODO: Correct?
+	{0xffffffff,		{0xffffffff, 0xffffffff}},
 };
 
-/* */
-/*  SET GeodeLink PRIORITY*/
-/* */
+/** GeodeLink priority table. */
 struct msrinit geode_link_priority_table[] = {
-	{CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}},
-	{DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}},
-	{VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}},
-	{GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}},
-	{GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}},
-	{GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}},
-	{VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}},
-	{AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}},
-	{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}},	/*  END */
+	{CPU_GLD_MSR_CONFIG,		{.hi = 0x00,.lo = 0x0220}},
+	{DF_GLD_MSR_MASTER_CONF,	{.hi = 0x00,.lo = 0x0000}},
+	{VG_GLD_MSR_CONFIG,		{.hi = 0x00,.lo = 0x0720}},
+	{GP_GLD_MSR_CONFIG,		{.hi = 0x00,.lo = 0x0010}},
+	{GLPCI_GLD_MSR_CONFIG,		{.hi = 0x00,.lo = 0x0017}},
+	{GLCP_GLD_MSR_CONF,		{.hi = 0x00,.lo = 0x0001}},
+	{VIP_GLD_MSR_CONFIG,		{.hi = 0x00,.lo = 0x0622}},
+	{AES_GLD_MSR_CONFIG,		{.hi = 0x00,.lo = 0x0013}},
+	{0x0FFFFFFFF,			{0x0FFFFFFFF, 0x0FFFFFFFF}},
 };
 
 extern int sizeram(void);
 
 /**
-  * Write a GeodeLink MSR. 
-  * @param gl A Geode Link table descriptor
-  */
+ * Write a GeodeLink MSR.
+ *
+ * @param gl A GeodeLink table descriptor.
+ */
 static void writeglmsr(struct gliutable *gl)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
-	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk(BIOS_SPEW, 
-		"%s: MSR 0x%08x, val 0x%08x:0x%08x\n", 
-		__FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+	wrmsr(gl->desc_name, msr);	/* MSR - see table above. */
+	printk(BIOS_SPEW,
+	       "%s: MSR 0x%08x, val 0x%08x:0x%08x\n",
+	       __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
 }
 
 /**
-  * Read the MSR specified in the gl struct. If the low 32 bits is zero, 
-  * indicating
-  * it has not been set, set it.
-  * @param gl A Geode Link table descriptor
-  */
+ * Read the MSR specified in the gl struct. If the low 32 bits are zero,
+ * indicating it has not been set, set it.
+ *
+ * @param gl A GeodeLink table descriptor.
+ */
 static void ShadowInit(struct gliutable *gl)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	msr = rdmsr(gl->desc_name);
-
-	if (msr.lo == 0) {
+	if (msr.lo == 0)
 		writeglmsr(gl);
-	}
 }
 
-extern int sizeram(void);
-
 /**
-  * Set up the system memory registers, i.e. memory that can be used
-  * for non-VSM (or SMM) purposes. 
-  * @param gl A Geode Link table descriptor
-  */
-
+ * Set up the system memory registers, i.e. memory that can be used
+ * for non-VSM (or SMM) purposes. 
+ *
+ * @param gl A GeodeLink table descriptor.
+ */
 static void sysmem_init(struct gliutable *gl)
 {
-	struct msr  msr;
+	struct msr msr;
 	int sizembytes, sizebytes;
 
-	/*
-	 * Figure out how much RAM is in the machine and alocate all to the
+	/* Figure out how much RAM is in the machine and allocate all to the
 	 * system. We will adjust for SMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", 
+	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n",
 	       __FUNCTION__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= ((SMM_SIZE * 1024) + 1);
-	printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);
+	printk(BIOS_DEBUG, "Usable RAM: %d bytes\n", sizebytes);
 
-	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
-	   The top 8 bits go into 0-7 of msr.hi. */
+	/* 20 bit address. The bottom 12 bits go into bits 20-31 in msr.lo.
+	 * The top 8 bits go into 0-7 of msr.hi.
+	 */
 	sizebytes--;
 	msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
-	sizebytes <<= 8;	/* move bits 23:12 in bits 31:20. */
+	sizebytes <<= 8;	/* Move bits 23:12 in bits 31:20. */
 	sizebytes &= 0xfff00000;
-	sizebytes |= 0x100;	/* start at 1MB */
+	sizebytes |= 0x100;	/* Start at 1 MB. */
 	msr.lo = sizebytes;
 
-	wrmsr(gl->desc_name, msr);	// MSR - see table above
+	wrmsr(gl->desc_name, msr);	/* MSR - see table above. */
 	printk(BIOS_DEBUG, "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
-		     gl->desc_name, msr.hi, msr.lo);
+	       gl->desc_name, msr.hi, msr.lo);
 }
 
 /**
-  * Set up GL0 memory mapping. Again, SMM memory is subtracted. 
-  * @param gl A Geode Link table descriptor
-  */
-
+ * Set up GL0 memory mapping. Again, SMM memory is subtracted. 
+ *
+ * @param gl A GeodeLink table descriptor.
+ */
 static void SMMGL0Init(struct gliutable *gl)
 {
-	struct msr  msr;
+	struct msr msr;
 	int sizebytes = sizeram() << 20;
 	long offset;
 
@@ -209,7 +204,7 @@
 
 	printk(BIOS_DEBUG, "%s: %d bytes\n", __FUNCTION__, sizebytes);
 
-	/* calculate the Two's complement offset */
+	/* Calculate the "two's complement" offset. */
 	offset = sizebytes - SMM_OFFSET;
 	offset = (offset >> 12) & 0x000fffff;
 	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __FUNCTION__, SMM_OFFSET);
@@ -220,94 +215,89 @@
 	msr.lo = SMM_OFFSET << 8;
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	wrmsr(gl->desc_name, msr);	/* MSR - See table above. */
 	printk(BIOS_DEBUG, "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
-		     gl->desc_name, msr.hi, msr.lo);
+	       gl->desc_name, msr.hi, msr.lo);
 }
 
 /**
-  * Set up GL1 memory mapping. Again, SMM memory is subtracted. 
-  * @param gl A Geode Link table descriptor
-  */
-
+ * Set up GL1 memory mapping. Again, SMM memory is subtracted. 
+ *
+ * @param gl A GeodeLink table descriptor.
+ */
 static void SMMGL1Init(struct gliutable *gl)
 {
-	struct msr  msr;
+	struct msr msr;
 	printk(BIOS_DEBUG, "%s:\n", __FUNCTION__);
 
 	msr.hi = gl->hi;
-	/* I don't think this is needed */
+	/* I don't think this is needed. */
 	msr.hi &= 0xffffff00;
 	msr.hi |= (SMM_OFFSET >> 24);
 	msr.lo = (SMM_OFFSET << 8) & 0xFFF00000;
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	wrmsr(gl->desc_name, msr);	/* MSR - See table above. */
 	printk(BIOS_DEBUG, "%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
-		     gl->desc_name, msr.hi, msr.lo);
+	       gl->desc_name, msr.hi, msr.lo);
 }
 
 /**
-  * Set up all Geode Link Interfaces. Iterate over the table until done. 
-  * Case out on the link type, and call the appropriate function. 
-  * @param gl A Geode Link table descriptor
-  */
-
+ * Set up all GeodeLink interfaces. Iterate over the table until done.
+ *
+ * Case out on the link type, and call the appropriate function.
+ *
+ * @param gl A GeodeLink table descriptor.
+ */
 static void GLIUInit(struct gliutable *gl)
 {
-
 	while (gl->desc_type != GL_END) {
 		switch (gl->desc_type) {
 		default:
-			/* For Unknown types: Write then read MSR */
+			/* For unknown types: Write then read MSR. */
 			writeglmsr(gl);
-		case SC_SHADOW:	/*  Check for a Shadow entry */
+		case SC_SHADOW:	/* Check for a Shadow entry. */
 			ShadowInit(gl);
 			break;
-
-		case R_SYSMEM:	/*  check for a SYSMEM entry */
+		case R_SYSMEM:	/* Check for a SYSMEM entry. */
 			sysmem_init(gl);
 			break;
-
-		case BMO_SMM:	/*  check for a SMM entry */
+		case BMO_SMM:	/* Check for a SMM entry. */
 			SMMGL0Init(gl);
 			break;
-
-		case BM_SMM:	/*  check for a SMM entry */
+		case BM_SMM:	/* Check for a SMM entry. */
 			SMMGL1Init(gl);
 			break;
 		}
 		gl++;
 	}
-
 }
 
 /**
-  * Set up the region config registers for the Geode Link PCI interface. 
-  *    R0:  0-640KB,
-  *    R1:  1MB - Top of System Memory
-  *    R2: SMM Memory
-  *    R3: Framebuffer? - not set up yet
-  */
+ * Set up the region config registers for the GeodeLink PCI interface.
+ *
+ * R0: 0 - 640 KB
+ * R1: 1 MB - Top of System Memory
+ * R2: SMM Memory
+ * R3: Framebuffer? - not set up yet.
+ */
 static void GLPCI_init(void)
 {
-	struct gliutable *gl = 0;
-	int i;
-	struct msr  msr;
-	int msrnum, enable_preempt, enable_cpu_override;
+	struct gliutable *gl = NULL;
+	struct msr msr;
+	int i, msrnum, enable_preempt, enable_cpu_override;
 	int nic_grants_control, enable_bus_parking;
 
-	/*  R0 - GLPCI settings for Conventional Memory space. */
+	/* R0 - GLPCI settings for Conventional Memory space. */
 	msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;	/* 640 */
-	msr.lo = 0;		/* 0 */
-	msr.lo |=
-	    GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET +
-	    GLPCI_RC_LOWER_WC_SET;
+	msr.lo = 0;						/* 0 */
+	msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET +
+		  GLPCI_RC_LOWER_WC_SET;
 	msrnum = GLPCI_RC0;
 	wrmsr(msrnum, msr);
 
-	/*  R1 - GLPCI settings for SysMem space. */
-	/*  Get systop from GLIU0 SYSTOP Descriptor */
+	/* R1 - GLPCI settings for SysMem space. */
+	/* Get systop from GLIU0 SYSTOP Descriptor. */
 	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
@@ -318,51 +308,52 @@
 		unsigned long pah, pal;
 		msrnum = gl->desc_name;
 		msr = rdmsr(msrnum);
-		/* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
+
+		/* Example: R_SYSMEM value 20:00:00:0f:fb:f0:01:00
 		 * translates to a base of 0x00100000 and top of 0xffbf0000
-		 * base of 1M and top of around 256M
+		 * base of 1M and top of around 256M.
 		 */
 		/* we have to create a page-aligned (4KB page) address
-		 * for base and top */
-		/* So we need a high page aligned addresss (pah) and
+		 * for base and top.
+		 * So we need a high page aligned addresss (pah) and
 		 * low page aligned address (pal) pah is from msr.hi
 		 * << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
 		pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);
-		/* we have the page address. Now make it a
-		 * page-aligned address */
+
+		/* We have the page address. Now make it page-aligned. */
 		pah <<= 12;
 
 		pal = msr.lo << 12;
 		msr.hi = pah;
 		msr.lo = pal;
-		msr.lo |=
-		    GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
-		    GLPCI_RC_LOWER_WC_SET;
-		printk(BIOS_DEBUG, 
+		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
+			  GLPCI_RC_LOWER_WC_SET;
+		printk(BIOS_DEBUG,
 		       "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
-			     msr.lo, msr.hi);
+		       msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
 	}
 
-	/*      R2 - GLPCI settings for SMM space */
-	msr.hi =
-	    ((SMM_OFFSET +
-	      (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
+	/* R2 - GLPCI settings for SMM space. */
+	msr.hi = ((SMM_OFFSET +
+		 (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
 	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
-	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", 
+	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n",
 	       msr.lo, msr.hi);
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
 
-	/* this is done elsewhere already, but it does no harm to do
-	 * it more than once */
-	/*  write serialize memory hole to PCI. Need to to unWS when
-	 *  something is shadowed regardless of cachablility. */
-	msr.lo = 0x021212121;	/* cache disabled and write serialized */
-	msr.hi = 0x021212121;	/* cache disabled and write serialized */
+	/* This is done elsewhere already, but it does no harm to do
+	 * it more than once.
+	 */
+	/* Write serialize memory hole to PCI. Need to to unWS when
+	 * something is shadowed regardless of cachablility.
+	 */
+	msr.lo = 0x021212121;	/* Cache disabled and write serialized. */
+	msr.hi = 0x021212121;	/* Cache disabled and write serialized. */
 
 	msrnum = CPU_RCONF_A0_BF;
 	wrmsr(msrnum, msr);
@@ -373,8 +364,9 @@
 	msrnum = CPU_RCONF_E0_FF;
 	wrmsr(msrnum, msr);
 
-	/*  Set Non-Cacheable Read Only for NorthBound Transactions to
-	 *  Memory. The Enable bit is handled in the Shadow setup. */
+	/* Set Non-Cacheable Read Only for NorthBound Transactions to
+	 * Memory. The Enable bit is handled in the Shadow setup.
+	 */
 	msrnum = GLPCI_A0_BF;
 	msr.hi = 0x35353535;
 	msr.lo = 0x35353535;
@@ -390,20 +382,19 @@
 	msr.lo = 0x35353535;
 	wrmsr(msrnum, msr);
 
-	/*  Set WSREQ */
+	/* Set WSREQ. */
 	msrnum = CPU_DM_CONFIG0;
 	msr = rdmsr(msrnum);
 	msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
-	/* reduce to 1 for safe mode */
+	/* Reduce to 1 for safe mode. */
 	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT;
 	wrmsr(msrnum, msr);
 
-	/* The following settings will not work with a CS5530 southbridge */
-	/* we are ignoring the 5530 case for now, and perhaps forever. */
+	/* The following settings will not work with a CS5530 southbridge.
+	 * We are ignoring the CS5530 case for now, and perhaps forever.
+	 */
 
-	/* */
 	/* 553x NB Init */
-	/* */
 
 	/* Arbiter setup */
 	enable_preempt =
@@ -424,9 +415,9 @@
 
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
-	/*   (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
-	msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET 
-		| GLPCI_CTRL_LOWER_PCD_SET;
+	/* Out will be disabled in CPUBUG649 for < 2.0 parts. */
+	msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET |
+		  GLPCI_CTRL_LOWER_PCD_SET;
 	msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
 
 	msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
@@ -454,11 +445,11 @@
 	/* Set GLPCI Latency Timer */
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
-	/* Change once 1.x is gone */
+	/* Change once 1.x is gone. */
 	msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT;
 	wrmsr(msrnum, msr);
 
-	/*  GLPCI_SPARE */
+	/* GLPCI_SPARE */
 	msrnum = GLPCI_SPARE;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0x7;
@@ -470,11 +461,11 @@
 }
 
 /**
-  *    Enable Clock Gating in ALL MSRs which relate to clocks. 
-  */
+ * Enable Clock Gating in ALL MSRs which relate to clocks.
+ */
 static void clock_gating_init(void)
 {
-	struct msr  msr;
+	struct msr msr;
 	struct msrinit *gating = clock_gating_default;
 	int i;
 
@@ -482,18 +473,17 @@
 		msr = rdmsr(gating->msrnum);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		wrmsr(gating->msrnum, msr);	// MSR - See the table above
+		wrmsr(gating->msrnum, msr);	/* MSR - See table above. */
 		gating += 1;
 	}
-
 }
 
 /**
-  * Set all Geode Link Priority register as determined by the 
-  */
+ * Set all GeodeLink priority registers as determined by the TODO.
+ */
 static void geode_link_priority(void)
 {
-	struct msr  msr;
+	struct msr msr;
 	struct msrinit *prio = geode_link_priority_table;
 	int i;
 
@@ -502,74 +492,78 @@
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		wrmsr(prio->msrnum, msr);	// MSR - See the table above
+		wrmsr(prio->msrnum, msr);	/* MSR - See table above. */
 		prio += 1;
 	}
 }
 
 /**
- *	Get the GLIU0 shadow register settings
- *	If the set_shadow function is used then all shadow descriptors
- *	  will stay sync'ed.
+ * Get the GLIU0 shadow register settings.
+ *
+ * If the set_shadow() function is used then all shadow descriptors
+ * will stay sync'ed.
+ *
+ * @return TODO
  */
 static u64 get_shadow(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	msr = rdmsr(MSR_GLIU0_SHADOW);
 	return (((u64) msr.hi) << 32) | msr.lo;
 }
 
 /**
- *	Set the cache RConf registers for the memory hole.
- *	Keeps all cache shadow descriptors sync'ed.
- *	This is part of the PCI lockup solution
- * @param Hi the high 32 bits of the msr setting
- * @param lo The low 32 bits of the msr setting
+ * Set the cache RConf registers for the memory hole.
+ *
+ * Keeps all cache shadow descriptors sync'ed.
+ * This is part of the PCI lockup solution.
+ *
+ * @param shadowHi The high 32 bits of the msr setting.
+ * @param shadowLo The low 32 bits of the msr setting.
  */
 static void set_shadowRCONF(u32 shadowHi, u32 shadowLo)
 {
-
-	// ok this is whacky bit translation time.
+	/* Ok, this is whacky bit translation time. */
 	int bit;
 	u8 shadowByte;
-	struct msr  msr = { 0, 0 };
+	struct msr msr = { 0, 0 };
 	shadowByte = (u8) (shadowLo >> 16);
 
-	// load up D000 settings in edx.
+	/* Load up D000 settings in edx. */
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
-		msr.hi |= 1;	// cache disable PCI/Shadow memory
+		msr.hi |= 1;	/* Cache disable PCI/Shadow memory. */
 		if (shadowByte && (1 << bit))
-			msr.hi |= 0x20;	// write serialize PCI memory
+			msr.hi |= 0x20;	/* Write serialize PCI memory. */
 	}
 
-	// load up C000 settings in eax.
-	for (; bit; bit--) {
+	/* Load up C000 settings in eax. */
+	for (/* Nothing */; bit; bit--) {
 		msr.lo <<= 8;
-		msr.lo |= 1;	// cache disable PCI/Shadow memory
+		msr.lo |= 1;	/* Cache disable PCI/Shadow memory. */
 		if (shadowByte && (1 << bit))
-			msr.lo |= 0x20;	// write serialize PCI memory
+			msr.lo |= 0x20;	/* Write serialize PCI memory. */
 	}
 
 	wrmsr(CPU_RCONF_C0_DF, msr);
 
 	shadowByte = (u8) (shadowLo >> 24);
 
-	// load up F000 settings in edx.
+	/* Load up F000 settings in edx. */
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
-		msr.hi |= 1;	// cache disable PCI/Shadow memory
+		msr.hi |= 1;	/* Cache disable PCI/Shadow memory. */
 		if (shadowByte && (1 << bit))
-			msr.hi |= 0x20;	// write serialize PCI memory
+			msr.hi |= 0x20;	/* Write serialize PCI memory. */
 	}
 
-	// load up E000 settings in eax.
-	for (; bit; bit--) {
+	/* Load up E000 settings in eax. */
+	for (/* Nothing */; bit; bit--) {
 		msr.lo <<= 8;
-		msr.lo |= 1;	// cache disable PCI/Shadow memory
+		msr.lo |= 1;	/* Cache disable PCI/Shadow memory. */
 		if (shadowByte && (1 << bit))
-			msr.lo |= 0x20;	// write serialize PCI memory
+			msr.lo |= 0x20;	/* write serialize PCI memory. */
 	}
 
 	wrmsr(CPU_RCONF_E0_FF, msr);
@@ -577,15 +571,17 @@
 
 /**
  * Set the GLPCI registers for the memory hole.
+ *
  * Keeps all cache shadow descriptors sync'ed.
- * @param shadowhi the high 32 bits of the msr setting
- * @param shadowlo The low 32 bits of the msr setting
-  */
+ *
+ * @param shadowhi The high 32 bits of the msr setting.
+ * @param shadowlo The low 32 bits of the msr setting.
+ */
 static void set_shadowGLPCI(u32 shadowhi, u32 shadowlo)
 {
-	struct msr  msr;
+	struct msr msr;
 
-// Set the Enable Register.
+	/* Set the Enable register. */
 	msr = rdmsr(GLPCI_REN);
 	msr.lo &= 0xFFFF00FF;
 	msr.lo |= ((shadowlo & 0xFFFF0000) >> 8);
@@ -593,14 +589,17 @@
 }
 
 /**
- * Set the GLIU SC register settings. Scans descriptor tables for
- * SC_SHADOW.  Keeps all shadow descriptors sync'ed.  
- * @param shadowSettings Shadow register settings
+ * Set the GLIU SC register settings.
+ *
+ * Scans descriptor tables for SC_SHADOW.
+ * Keeps all shadow descriptors sync'ed.
+ *
+ * @param shadowSettings Shadow register settings.
  */
 static void set_shadow(u64 shadowSettings)
 {
 	int i;
-	struct msr  msr;
+	struct msr msr;
 	struct gliutable *pTable;
 	u32 shadowLo, shadowHi;
 
@@ -609,66 +608,70 @@
 
 	set_shadowRCONF(shadowHi, shadowLo);
 	set_shadowGLPCI(shadowHi, shadowLo);
-	
+
 	for (i = 0; gliutables[i]; i++) {
 		for (pTable = gliutables[i]; pTable->desc_type != GL_END;
 		     pTable++) {
 			if (pTable->desc_type == SC_SHADOW) {
-				
 				msr = rdmsr(pTable->desc_name);
 				msr.lo = (u32) shadowSettings;
-				/* maintain PDID in upper EDX*/
-				msr.hi &= 0xFFFF0000;	
+				/* Maintain PDID in upper EDX. */
+				msr.hi &= 0xFFFF0000;
 				msr.hi |=
-				    ((u32) (shadowSettings >> 32)) &
-				    0x0000FFFF;
-				// MSR - See the table above
+				    ((u32) (shadowSettings >> 32)) & 0x0000FFFF;
+				/* MSR - See the table above. */
 				wrmsr(pTable->desc_name, msr);
 			}
 		}
 	}
 }
 
+/**
+ * TODO.
+ */
 static void rom_shadow_settings(void)
 {
+	u64 shadowSettings = get_shadow();
 
-	u64 shadowSettings = get_shadow();
-	// Disable read & writes
+	/* Disable read & writes. */
 	shadowSettings &= (u64) 0xFFFF00000000FFFFULL;
-	// Enable reads for F0000-FFFFF
+
+	/* Enable reads for F0000-FFFFF. */
 	shadowSettings |= (u64) 0x00000000F0000000ULL;
-	// Enable rw for C0000-CFFFF
+
+	/* Enable read & writes for C0000-CFFFF. */
 	shadowSettings |= (u64) 0x0000FFFFFFFF0000ULL;
+
 	set_shadow(shadowSettings);
 }
 
 /**
+ * Set up RCONF_DEFAULT and any other RCONF registers needed.
  *
- *
- * Set up RCONF_DEFAULT and any other RCONF registers needed
- *
- *  DEVRC_RCONF_DEFAULT:
- *  ROMRC(63:56) = 04h	 write protect ROMBASE
- *  ROMBASE(36:55) = 0FFFC0h Top of PCI/bottom of rom chipselect area
- *  DEVRC(35:28) =  39h	 cache disabled in PCI memory + WS bit on 
- +                       Write Combine + write burst.
- *  SYSTOP(27:8) = top of system memory
- *  SYSRC(7:0) = 0 writeback, can set to 08h to make writethrough
- *
-  */
-#define SYSMEM_RCONF_WRITETHROUGH 8
-#define DEVRC_RCONF_DEFAULT 0x21
-#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
-#define ROMRC_RCONF_DEFAULT 0x25
+ * DEVRC_RCONF_DEFAULT:
+ * ROMRC(63:56)   = 0x04     Write protect ROMBASE
+ * ROMBASE(36:55) = 0x0FFFC0 Top of PCI/bottom of ROM chipselect area
+ * DEVRC(35:28)   = 0x39     Cache disabled in PCI memory + WS bit on
+ *                           Write Combine + write burst.
+ * SYSTOP(27:8)   = top of system memory
+ * SYSRC(7:0)     = 0        Writeback, can set to 0x08 to make writethrough
+ */
+#define SYSMEM_RCONF_WRITETHROUGH	8
+#define DEVRC_RCONF_DEFAULT		0x21
+#define ROMBASE_RCONF_DEFAULT		0xFFFC0000
+#define ROMRC_RCONF_DEFAULT		0x25
 
+/**
+ * TODO.
+ */
 static void enable_L1_cache(void)
 {
-	struct gliutable *gl = 0;
+	struct gliutable *gl = NULL;
 	int i;
-	struct msr  msr;
+	struct msr msr;
 	u8 SysMemCacheProp;
 
-	/* Locate SYSMEM entry in GLIU0table */
+	/* Locate SYSMEM entry in GLIU0table. */
 	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
@@ -676,43 +679,46 @@
 		}
 	}
 	if (gl == 0) {
-		post_code(0xCE);	/* POST_RCONFInitError */
-		while (1) ;
+		post_code(POST_RCONFInitError);
+		while (1);	/* TODO: Should be hlt()? */
 	}
+
 // sysdescfound:
 	msr = rdmsr(gl->desc_name);
 
-	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the
+	/* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the
 	 * top 8 bits go into 0-7 of edx.
 	 */
 	msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
 	msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
 	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	// 8
 
-	// Set Default SYSMEM region properties
-	// NOT writethrough == writeback 8 (or ~8)
+	/* Set Default SYSMEM region properties.
+	 * NOT writethrough == writeback 8 (or ~8)
+	 */
 	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;
 
-	// Set PCI space cache properties
-	// setting is split betwwen hi and lo...
+	/* Set PCI space cache properties.
+	 * Setting is split between hi and lo...
+	 */
 	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);
 	msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
 
-	// Set the ROMBASE. This is usually FFFC0000h
+	/* Set the ROMBASE. This is usually 0xFFFC0000. */
 	msr.hi |=
 	    (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
 
-	// Set ROMBASE cache properties.
+	/* Set ROMBASE cache properties. */
 	msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
 
-	// now program RCONF_DEFAULT
+	/* Now program RCONF_DEFAULT. */
 	wrmsr(CPU_RCONF_DEFAULT, msr);
 	printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
-		     msr.lo);
+	       msr.lo);
 
-	// RCONF_BYPASS: Cache tablewalk properties and 
-	// SMM/DMM header access properties.
-	// Set to match system memory cache properties.
+	/* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access
+	 * properties. Set to match system memory cache properties.
+	 */
 	msr = rdmsr(CPU_RCONF_DEFAULT);
 	SysMemCacheProp = (u8) (msr.lo & 0xFF);
 	msr = rdmsr(CPU_RCONF_BYPASS);
@@ -720,37 +726,37 @@
 	    (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
 	wrmsr(CPU_RCONF_BYPASS, msr);
 
-	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", 
+	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n",
 	       msr.hi, msr.lo);
 }
 
-/** 
-  * Enable the L2 cache MSRs.
-  */
+/**
+ * Enable the L2 cache MSRs.
+ */
 static void enable_L2_cache(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	/* Instruction Memory Configuration register
-	 * set EBE bit, required when L2 cache is enabled
+	 * set EBE bit, required when L2 cache is enabled.
 	 */
 	msr = rdmsr(CPU_IM_CONFIG);
 	msr.lo |= 0x400;
 	wrmsr(CPU_IM_CONFIG, msr);
 
-	/* Data Memory Subsystem Configuration register
-	 * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
+	/* Data Memory Subsystem Configuration register. Set EVCTONRPL bit,
+	 * required when L2 cache is enabled in victim mode.
 	 */
 	msr = rdmsr(CPU_DM_CONFIG0);
 	msr.lo |= 0x4000;
 	wrmsr(CPU_DM_CONFIG0, msr);
 
-	/* invalidate L2 cache */
+	/* Invalidate L2 cache. */
 	msr.hi = 0x00;
 	msr.lo = 0x10;
 	wrmsr(CPU_BC_L2_CONF, msr);
 
-	/* Enable L2 cache */
+	/* Enable L2 cache. */
 	msr.hi = 0x00;
 	msr.lo = 0x0f;
 	wrmsr(CPU_BC_L2_CONF, msr);
@@ -763,31 +769,37 @@
 #define CONFIG_VIDEO_MB 8
 #endif
 
-/** 
-  * set up all LX cache registers, L1, L2, and x86. 
-  */
+/**
+ * Set up all LX cache registers, L1, L2, and x86.
+ */
 static void setup_lx_cache(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	enable_L1_cache();
 	enable_L2_cache();
 
-	// Make sure all INVD instructions are treated as WBINVD.  We do this
-	// because we've found some programs which require this behavior.
+	/* Make sure all INVD instructions are treated as WBINVD. We do this
+	 * because we've found some programs which require this behavior.
+	 */
 	msr = rdmsr(CPU_DM_CONFIG0);
 	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
 	wrmsr(CPU_DM_CONFIG0, msr);
 
 	enable_cache();
-	__asm__("wbinvd\n");
+	__asm__("wbinvd\n");	/* TODO: Use wbinvd() function? */
 }
 
+/**
+ * TODO.
+ *
+ * @return TODO.
+ */
 u32 get_systop(void)
 {
-	struct gliutable *gl = 0;
+	struct gliutable *gl = NULL;
 	u32 systop;
-	struct msr  msr;
+	struct msr msr;
 	int i;
 
 	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
@@ -798,45 +810,44 @@
 	}
 	if (gl) {
 		msr = rdmsr(gl->desc_name);
-		systop = ((msr.hi & 0xFF) << 24) | 
-			((msr.lo & 0xFFF00000) >> 8);
+		systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
 		systop += 0x1000;	/* 4K */
 	} else {
 		systop =
 		    ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024;
 	}
+
 	return systop;
 }
 
-/** northbridge_init_early Do all the Nasty Bits that have to
-  * happen. These can be done once memory is up, but before much else
-  * is done. So we do them in Phase 2.
-  */
+/**
+ * Do all the Nasty Bits that have to happen.
+ *
+ * These can be done once memory is up, but before much else is done.
+ * So we do them in phase 2.
+ */
 void northbridge_init_early(void)
 {
-	struct msr  msr;
 	int i;
+	struct msr msr;
+
 	printk(BIOS_DEBUG, "Enter %s\n", __FUNCTION__);
 
 	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
 
-	/*  Now that the descriptor to memory is set up. */
-	/*  The memory controller needs one read to synch its lines
-	 *  before it can be used. 
+	/* Now that the descriptor to memory is set up, the memory controller
+	 * needs one read to synch it's lines before it can be used.
 	 */
 	i = *(int *)0;
 
 	geode_link_priority();
-
 	setup_lx_cache();
-
 	rom_shadow_settings();
-
 	GLPCI_init();
-
 	clock_gating_init();
 
-	__asm__ __volatile__("FINIT\n");
+	__asm__ __volatile__("FINIT\n"); /* TODO: Create finit() function? */
+
 	printk(BIOS_DEBUG, "Exit %s\n", __FUNCTION__);
 }

Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-07 21:18:47 UTC (rev 438)
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-08 00:19:26 UTC (rev 439)
@@ -32,16 +32,19 @@
 #include <amd_geodelx.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 
-static const u8 num_col_addr[] = { 
-	0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, 
-	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F 
+static const u8 num_col_addr[] = {
+	0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
+	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 };
 
 /**
-  * Auto-detect, using SPD, the DIMM size. It's the usual magic, with
-  * all the usual failiure points that can happen.
-  * @param dimm -- The SMBus address of the DIMM
-  */
+ * Auto-detect, using SPD, the DIMM size. It's the usual magic, with
+ * all the usual failure points that can happen.
+ *
+ * @param dimm TODO
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
 {
 	u32 dimm_setting;
@@ -51,13 +54,10 @@
 
 	dimm_setting = 0;
 
-	/* Check that we have a dimm */
-	if (smbus_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
+	/* Check that we have a DIMM. */
+	if (smbus_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF)
 		return;
-	}
 
-	/* Field: Module Banks per DIMM */
-	/* EEPROM byte usage: (5) Number of DIMM Banks */
 	spd_byte = smbus_read_byte(dimm, SPD_NUM_DIMM_BANKS);
 	if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
 		printk(BIOS_EMERG, "Number of module banks not compatible\n");
@@ -66,8 +66,6 @@
 	}
 	dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
 
-	/* Field: Banks per SDRAM device */
-	/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
 	spd_byte = smbus_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
 	if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
 		printk(BIOS_EMERG, "Number of device banks not compatible\n");
@@ -76,59 +74,58 @@
 	}
 	dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
 
-	/* Field: DIMM size
-	 *; EEPROM byte usage: (3)  Number or Row Addresses
-	 *;                                       (4)  Number of Column Addresses
-	 *;                                       (5)  Number of DIMM Banks
-	 *;                                       (31) Module Bank Density
-	 *; Size = Module Density * Module Banks
-	 */
 	if ((smbus_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
 	    || (smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
-		printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");
+		printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hlt();
 	}
 
+	/* Size = Module Density * Module Banks */
 	dimm_size = smbus_read_byte(dimm, SPD_BANK_DENSITY);
-	/* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
+	/* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc
+	 * to not optimize this out.
+	 */
 	dimm_size |= (dimm_size << 8);
-	/* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
+	/* And off 2 GB DIMM size: not supported and the 1 GB size we just
+	 * moved up to bit 8 as well as all the extra on top.
+	 */
 	dimm_size &= 0x01FC;
-	/*       Module Density * Module Banks */
-	/* shift to multiply by # DIMM banks */
+	/* Module Density * Module Banks */
+	/* Shift to multiply by the number of DIMM banks. */
 	dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;
 	dimm_size = __builtin_ctz(dimm_size);
-	if (dimm_size > 8) {	/* 8 is 1GB only support 1GB per DIMM */
+	if (dimm_size > 8) {	/* 8 is 1 GB only support 1 GB per DIMM */
 		printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
 		post_code(ERROR_DENSITY_DIMM);
 		hlt();
 	}
 	dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
 
-	/* Field: PAGE size
-	  * EEPROM byte usage: (4)  Number of Column Addresses
-	  * PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
-	  *
-	  * But this really works by magic.
-	  *If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address
-	  *that MC generates, here is how the MC assigns the pa onto the ma pins:
-	  *
-	  *ma  12 11 10 09 08 07 06 05 04 03 02 01 00
-	  *-------------------------------------------
-	  *pa					09 08 07 06 05 04 03	(7 col addr bits = 1K page size)
-	  *pa				 10 09 08 07 06 05 04 03	(8 col addr bits = 2K page size)
-	  *pa			  11 10 09 08 07 06 05 04 03	(9 col addr bits = 4K page size)
-	  *pa		   12 11 10 09 08 07 06 05 04 03	(10 col addr bits = 8K page size)
-	  *pa	 13 AP 12 11 10 09 08 07 06 05 04 03	(11 col addr bits = 16K page size)
-	  *pa  14 13 AP 12 11 10 09 08 07 06 05 04 03	(12 col addr bits = 32K page size)
-	  * *AP=autoprecharge bit
-	  *
-	  *Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
-	  *so lower 3 address bits are dont_cares.So from the table above,
-	  *it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
-	  *it adds 3 to get 10, then does 2^10=1K.  Get it?
-	*/
+	/* PageSize = 2 ^ (number of column addresses) * data width in bytes
+	 * (should be 8 bytes for a normal DIMM)
+	 *
+	 * If ma[12:0] is the memory address pins, and pa[12:0] is the
+	 * physical column address that the memory controller (MC) generates,
+	 * here is how the MC assigns the pa onto the ma pins:
+	 * 
+	 * ma  12 11 10 09 08 07 06 05 04 03 02 01 00
+	 * -------------------------------------------
+	 * pa					09 08 07 06 05 04 03	(7 col addr bits = 1K page size)
+	 * pa				 10 09 08 07 06 05 04 03	(8 col addr bits = 2K page size)
+	 * pa			  11 10 09 08 07 06 05 04 03	(9 col addr bits = 4K page size)
+	 * pa		   12 11 10 09 08 07 06 05 04 03	(10 col addr bits = 8K page size)
+	 * pa	 13 AP 12 11 10 09 08 07 06 05 04 03	(11 col addr bits = 16K page size)
+	 * pa  14 13 AP 12 11 10 09 08 07 06 05 04 03	(12 col addr bits = 32K page size)
+	 *
+	 * (AP = autoprecharge bit)
+	 * 
+	 * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus
+	 * (8 bytes), so lower 3 address bits are dont_cares. So from the
+	 * table above, it's easier to see what the old code is doing: if for
+	 * example, #col_addr_bits = 7 (06h), it adds 3 to get 10, then does
+	 * 2^10=1K. Get it?
+	 */
 
 	spd_byte = num_col_addr[smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
 	if (spd_byte > MAX_COL_ADDR) {
@@ -137,10 +134,12 @@
 		hlt();
 	}
 	spd_byte -= 7;
-	if (spd_byte > 5) {	/* if the value is above 6 it means >12 address lines */
-		spd_byte = 7;	/* which means >32k so set to disabled */
+	/* If the value is above 6 it means >12 address lines... */
+	if (spd_byte > 5) {
+		spd_byte = 7;	/* ...which means >32k so set to disabled. */
 	}
-	dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT;	/* 0=1k,1=2k,2=4k,etc */
+	/* 0 = 1k, 1 = 2k, 2 = 4k, etc. */
+	dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT;
 
 	msr = rdmsr(MC_CF07_DATA);
 	if (dimm == dimm0) {
@@ -153,11 +152,15 @@
 	wrmsr(MC_CF07_DATA, msr);
 }
 
-/** Try to compute the max DDR clock rate. The only bad news here is that  if you have got a geode link 
-  * speed that is too fast, you are going to pay for it: the system will hlt!
-  * @param dimm0 dimm0 SMBus address
-  * @param dimm1 dimm1 SMBus address
-  */
+/**
+ * Try to compute the max. DDR clock rate.
+ *
+ * The only bad news here is that if you have got a GeodeLink speed that is
+ * too fast, you are going to pay for it: the system will hlt!
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 static void check_ddr_max(u8 dimm0, u8 dimm1)
 {
 	u8 spd_byte0, spd_byte1;
@@ -165,32 +168,32 @@
 
 	/* PC133 identifier */
 	spd_byte0 = smbus_read_byte(dimm0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
-	if (spd_byte0 == 0xFF) {
+	if (spd_byte0 == 0xFF)
 		spd_byte0 = 0;
-	}
 	spd_byte1 = smbus_read_byte(dimm1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
-	if (spd_byte1 == 0xFF) {
+	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
+
+	/* I don't think you need this check. */
+#if 0
+	if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0) {
+		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
+		post_code(POST_PLL_MEM_FAIL);
+		hlt();
 	}
+#endif
 
-	/* I don't think you need this check.
-	   if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){
-	   printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
-	   post_code(POST_PLL_MEM_FAIL);
-	   hlt();
-	   } */
-
-	/* Use the slowest DIMM */
+	/* Use the slowest DIMM. */
 	if (spd_byte0 < spd_byte1) {
 		spd_byte0 = spd_byte1;
 	}
 
-	/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+	/* Turn SPD ns time into MHz. Check what the asm does to this math. */
 	speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
 
-	/* current speed > max speed? */
+	/* Current speed > max speed? */
 	if (geode_link_speed() > speed) {
-		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
+		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
 		post_code(POST_PLL_MEM_FAIL);
 		hlt();
 	}
@@ -198,11 +201,14 @@
 
 const u16 REFRESH_RATE[] = { 15, 3, 7, 31, 62, 125 };	/* ns */
 
-/** 
-  * compute a refresh rate. You have to read both dimms and take the one that requires a faster rate. 
-  * @param dimm0 dimm0 SMBus address
-  * @param dimm1 dimm1 SMBus address
-   */
+/**
+ * Compute a refresh rate.
+ *
+ * You have to read both DIMMs and take the one that requires a faster rate.
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 static void set_refresh_rate(u8 dimm0, u8 dimm1)
 {
 	u8 spd_byte0, spd_byte1;
@@ -223,40 +229,41 @@
 	}
 	rate1 = REFRESH_RATE[spd_byte1];
 
-	/* Use the faster rate (lowest number) */
+	/* Use the faster rate (lowest number). */
 	if (rate0 > rate1) {
 		rate0 = rate1;
 	}
 
 	msr = rdmsr(MC_CF07_DATA);
-	msr.lo |= ((rate0 * (geode_link_speed() / 2)) / 16) 
-			<< CF07_LOWER_REF_INT_SHIFT;
+	msr.lo |= ((rate0 * (geode_link_speed() / 2)) / 16)
+		   << CF07_LOWER_REF_INT_SHIFT;
 	wrmsr(MC_CF07_DATA, msr);
 }
 
-const u8 CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 };	/* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
+/* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
+const u8 CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 };
 
 /**
-  * Compute the CAS rate. 
-  *	EEPROM byte usage: (18) SDRAM device attributes - CAS latency
-  *	EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
-  *	EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
-  *
-  *	The CAS setting is based on the information provided in each DIMMs SPD.
-  *	 The speed at which a DIMM can run is described relative to the slowest
-  *	 CAS the DIMM supports. Each speed for the relative CAS settings is
-  *	 checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
-  *	 speed, the CAS setting	 is removed from the list of good settings for
-  *	 the DIMM. This is done for both DIMMs and the lists are compared to
-  *	 find the lowest common CAS latency setting. If there are no CAS settings
-  *	 in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
-  *	Result is that we will set fastest CAS Latency based on GeodeLink speed 
-  *	and SPD information.
-  *
-  * @param dimm0 dimm0 SMBus address
-  * @param dimm1 dimm1 SMBus address
-  *
-  */
+ * Compute the CAS rate.
+ *
+ * The CAS setting is based on the information provided in each DIMMs SPD.
+ *
+ * The speed at which a DIMM can run is described relative to the slowest
+ * CAS the DIMM supports. Each speed for the relative CAS settings is
+ * checked that it is within the GeodeLink speed. If it isn't within the
+ * GeodeLink speed, the CAS setting is removed from the list of good settings
+ * for the DIMM.
+ *
+ * This is done for both DIMMs and the lists are compared to find the lowest
+ * common CAS latency setting. If there are no CAS settings
+ * in common we output a ERROR_DIFF_DIMMS (0x78) POST code and halt.
+ *
+ * Result is that we will set fastest CAS latency based on GeodeLink speed 
+ * and SPD information.
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 static void set_cas(u8 dimm0, u8 dimm1)
 {
 	u16 glspeed, dimm_speed;
@@ -265,72 +272,78 @@
 
 	glspeed = geode_link_speed();
 
-	/**************************	 dimm0	**********************************/
+	/* DIMM 0 */
 	casmap0 = smbus_read_byte(dimm0, SPD_ACCEPTABLE_CAS_LATENCIES);
 	if (casmap0 != 0xFF) {
-		/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
+		/* If -.5 timing is supported, check -.5 timing > GeodeLink. */
+		/* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */
 		spd_byte = smbus_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_2ND);
 		if (spd_byte != 0) {
-			/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+			/* Turn SPD ns time into MHz. Check what the asm does
+			 * to this math.
+			 */
 			dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) +
 						(spd_byte & 0x0F)));
 			if (dimm_speed >= glspeed) {
-				/* IF -1 timing is supported, check -1 timing > GeodeLink */
+				/* If -1 timing is supported, check -1 timing > GeodeLink. */
+				/* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */
 				spd_byte = smbus_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD);
 				if (spd_byte != 0) {
-					/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+					/* Turn SPD ns time into MHz. Check what the asm does to this math. */
 					dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
 					if (dimm_speed <= glspeed) {
-						/* set we can use -.5 timing but not -1 */
+						/* Set we can use -.5 timing but not -1. */
 						spd_byte = 31 - __builtin_clz((u32) casmap0);
-						/* just want bits in the lower byte since we have to cast to a 32 */
+						/* Just want bits in the lower byte since we have to cast to a 32. */
 						casmap0 &= 0xFF << (--spd_byte);
 					}
-				}	/*MIN_CYCLE_10 !=0 */
+				}	/* MIN_CYCLE_10 != 0 */
 			} else {
-				/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
+				/* Timing_05 < GLspeed, can't use -.5 or -1 timing. */
 				spd_byte = 31 - __builtin_clz((u32) casmap0);
-				/* just want bits in the lower byte since we have to cast to a 32 */
+				/* Just want bits in the lower byte since we have to cast to a 32. */
 				casmap0 &= 0xFF << (spd_byte);
 			}
-		}		/*MIN_CYCLE_05 !=0 */
+		}		/* MIN_CYCLE_05 != 0 */
 	} else {		/* No DIMM */
 		casmap0 = 0;
 	}
 
-	/**************************	 dimm1	**********************************/
+	/* DIMM 1 */
 	casmap1 = smbus_read_byte(dimm1, SPD_ACCEPTABLE_CAS_LATENCIES);
 	if (casmap1 != 0xFF) {
-		/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
+		/* If -.5 timing is supported, check -.5 timing > GeodeLink. */
+		/* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */
 		spd_byte = smbus_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_2ND);
 		if (spd_byte != 0) {
-			/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+			/* Turn SPD ns time into MHz. Check what the asm does to this math. */
 			dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
 			if (dimm_speed >= glspeed) {
-				/* IF -1 timing is supported, check -1 timing > GeodeLink */
+				/* If -1 timing is supported, check -1 timing > GeodeLink. */
+				/* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */
 				spd_byte = smbus_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_3RD);
 				if (spd_byte != 0) {
-					/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+					/* Turn SPD ns time into MHz. Check what the asm does to this math. */
 					dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
 					if (dimm_speed <= glspeed) {
-						/* set we can use -.5 timing but not -1 */
+						/* Set we can use -.5 timing but not -1. */
 						spd_byte = 31 - __builtin_clz((u32) casmap1);
-						/* just want bits in the lower byte since we have to cast to a 32 */
+						/* Just want bits in the lower byte since we have to cast to a 32. */
 						casmap1 &= 0xFF << (--spd_byte);
 					}
-				}	/*MIN_CYCLE_10 !=0 */
+				}	/* MIN_CYCLE_10 != 0 */
 			} else {
-				/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
+				/* Timing_05 < GLspeed, can't use -.5 or -1 timing. */
 				spd_byte = 31 - __builtin_clz((u32) casmap1);
-				/* just want bits in the lower byte since we have to cast to a 32 */
+				/* Just want bits in the lower byte since we have to cast to a 32. */
 				casmap1 &= 0xFF << (spd_byte);
 			}
-		}		/*MIN_CYCLE_05 !=0 */
+		}		/* MIN_CYCLE_05 != 0 */
 	} else {		/* No DIMM */
 		casmap1 = 0;
 	}
 
-	/*********************	CAS_LAT MAP COMPARE	***************************/
+	/* Compare CAS latencies. */
 	if (casmap0 == 0) {
 		spd_byte = CASDDR[__builtin_ctz((u32) casmap1)];
 	} else if (casmap1 == 0) {
@@ -338,7 +351,7 @@
 	} else if ((casmap0 &= casmap1)) {
 		spd_byte = CASDDR[__builtin_ctz((u32) casmap0)];
 	} else {
-		printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
+		printk(BIOS_EMERG, "DIMM CAS latencies not compatible\n");
 		post_code(ERROR_DIFF_DIMMS);
 		hlt();
 	}
@@ -349,12 +362,15 @@
 	wrmsr(MC_CF8F_DATA, msr);
 }
 
-/** 
-  * set latencies for DRAM. These are the famed ras and cas latencies. 
-  * Take the one with the tightest requirements, and use that for both. 
-  * @param dimm0 dimm0 SMBus address
-  * @param dimm1 dimm1 SMBus address
-  */
+/**
+ * Set latencies for DRAM.
+ *
+ * These are the famed RAS and CAS latencies. Take the one with the tightest
+ * requirements, and use that for both.
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 static void set_latencies(u8 dimm0, u8 dimm1)
 {
 	u32 memspeed, dimm_setting;
@@ -367,36 +383,29 @@
 	/* MC_CF8F setup */
 	/* tRAS */
 	spd_byte0 = smbus_read_byte(dimm0, SPD_tRAS);
-	if (spd_byte0 == 0xFF) {
+	if (spd_byte0 == 0xFF)
 		spd_byte0 = 0;
-	}
 	spd_byte1 = smbus_read_byte(dimm1, SPD_tRAS);
-	if (spd_byte1 == 0xFF) {
+	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
+	if (spd_byte0 < spd_byte1)
 		spd_byte0 = spd_byte1;
-	}
 
 	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = (spd_byte0 * memspeed) / 1000;
-	if (((spd_byte0 * memspeed) % 1000)) {
+	if (((spd_byte0 * memspeed) % 1000))
 		++spd_byte1;
-	}
 	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
 
 	/* tRP */
 	spd_byte0 = smbus_read_byte(dimm0, SPD_tRP);
-	if (spd_byte0 == 0xFF) {
+	if (spd_byte0 == 0xFF)
 		spd_byte0 = 0;
-	}
 	spd_byte1 = smbus_read_byte(dimm1, SPD_tRP);
-	if (spd_byte1 == 0xFF) {
+	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
+	if (spd_byte0 < spd_byte1)
 		spd_byte0 = spd_byte1;
-	}
 
 	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
@@ -407,16 +416,13 @@
 
 	/* tRCD */
 	spd_byte0 = smbus_read_byte(dimm0, SPD_tRCD);
-	if (spd_byte0 == 0xFF) {
+	if (spd_byte0 == 0xFF)
 		spd_byte0 = 0;
-	}
 	spd_byte1 = smbus_read_byte(dimm1, SPD_tRCD);
-	if (spd_byte1 == 0xFF) {
+	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
+	if (spd_byte0 < spd_byte1)
 		spd_byte0 = spd_byte1;
-	}
 
 	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
@@ -427,16 +433,13 @@
 
 	/* tRRD */
 	spd_byte0 = smbus_read_byte(dimm0, SPD_tRRD);
-	if (spd_byte0 == 0xFF) {
+	if (spd_byte0 == 0xFF)
 		spd_byte0 = 0;
-	}
 	spd_byte1 = smbus_read_byte(dimm1, SPD_tRRD);
-	if (spd_byte1 == 0xFF) {
+	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
+	if (spd_byte0 < spd_byte1)
 		spd_byte0 = spd_byte1;
-	}
 
 	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
@@ -447,8 +450,8 @@
 
 	/* tRC = tRP + tRAS */
 	dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
-	     		((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
-	    			<< CF8F_LOWER_ACT2ACTREF_SHIFT;
+			((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
+				<< CF8F_LOWER_ACT2ACTREF_SHIFT;
 
 	msr = rdmsr(MC_CF8F_DATA);
 	msr.lo &= 0xF00000FF;
@@ -459,33 +462,36 @@
 	/* MC_CF1017 setup */
 	/* tRFC */
 	spd_byte0 = smbus_read_byte(dimm0, SPD_tRFC);
-	if (spd_byte0 == 0xFF) {
+	if (spd_byte0 == 0xFF)
 		spd_byte0 = 0;
-	}
 	spd_byte1 = smbus_read_byte(dimm1, SPD_tRFC);
-	if (spd_byte1 == 0xFF) {
+	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
+	if (spd_byte0 < spd_byte1)
 		spd_byte0 = spd_byte1;
-	}
 
 	if (spd_byte0) {
 		/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
 		spd_byte1 = (spd_byte0 * memspeed) / 1000;
-		if (((spd_byte0 * memspeed) % 1000)) {
+		if (((spd_byte0 * memspeed) % 1000))
 			++spd_byte1;
-		}
-	} else {		/* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
+	} else {
+		/* Not all SPDs have tRFC setting.
+		 * Use this formula: tRFC = tRC + 1 clk.
+		 */
 		spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
 	}
-	dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT;	/* note this clears the cf8f dimm setting */
+
+	/* Note: This clears the cf8f DIMM setting. */
+	dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT;
 	msr = rdmsr(MC_CF1017_DATA);
 	msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
 	msr.lo |= dimm_setting;
 	wrmsr(MC_CF1017_DATA, msr);
 
-	/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */
+	/* tWTR: Set tWTR to 2 for 400 MHz and above GLBUS (200 Mhz mem)
+	 * otherwise it stay default (1).
+	 */
 	if (memspeed > 198) {
 		msr = rdmsr(MC_CF1017_DATA);
 		msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
@@ -494,44 +500,46 @@
 	}
 }
 
-/** 
-  * Set the registers for drive,  namely drive and fet strength. 
-  * @param dimm0 dimm0 SMBus address
-  * @param dimm1 dimm1 SMBus address
-  */
+/**
+ * Set the registers for drive, namely drive and fet strength.
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 static void set_extended_mode_registers(u8 dimm0, u8 dimm1)
 {
 	u8 spd_byte0, spd_byte1;
 	struct msr msr;
+
 	spd_byte0 = smbus_read_byte(dimm0, SPD_DEVICE_ATTRIBUTES_GENERAL);
-	if (spd_byte0 == 0xFF) {
+	if (spd_byte0 == 0xFF)
 		spd_byte0 = 0;
-	}
 	spd_byte1 = smbus_read_byte(dimm1, SPD_DEVICE_ATTRIBUTES_GENERAL);
-	if (spd_byte1 == 0xFF) {
+	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
-	}
 	spd_byte1 &= spd_byte0;
 
 	msr = rdmsr(MC_CF07_DATA);
-	if (spd_byte1 & 1) {	/* Drive Strength Control */
+	if (spd_byte1 & 1) {
+		/* Drive Strength Control */
 		msr.lo |= CF07_LOWER_EMR_DRV_SET;
 	}
-	if (spd_byte1 & 2) {	/* FET Control */
+	if (spd_byte1 & 2) {
+		/* FET Control */
 		msr.lo |= CF07_LOWER_EMR_QFC_SET;
 	}
 	wrmsr(MC_CF07_DATA, msr);
 }
 
 /**
-  * Debug function. Only used when test hardware is connected. 
-  */
+ * Debug function. Only used when test hardware is connected.
+ */
 static void EnableMTest(void)
 {
 	struct msr msr;
 
 	msr = rdmsr(GLCP_DELAY_CONTROLS);
-	msr.hi &= ~(7 << 20);	/* clear bits 54:52 */
+	msr.hi &= ~(7 << 20);	/* Clear bits 54:52. */
 	if (geode_link_speed() < 200) {
 		msr.hi |= 2 << 20;
 	}
@@ -547,9 +555,10 @@
 	printk(BIOS_DEBUG, "Enabled MTest for TLA debug\n");
 }
 
-/** Set SDRAM registers that need to be set independent of SPD or even presence or absence of DIMMs
-  * in a slot.  Parameters are ignored. 
-  */
+/**
+ * Set SDRAM registers that need to be set independent of SPD or even
+ * presence or absence of DIMMs in a slot. Parameters are ignored.
+ */
 void sdram_set_registers(void)
 {
 	struct msr msr;
@@ -570,20 +579,24 @@
 	msrnum = MC_CF07_DATA;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0xF0;
-	msr.lo |= 0x40;		/* set refresh to 4SDRAM clocks */
+	msr.lo |= 0x40;		/* Set refresh to 4 SDRAM clocks. */
 	wrmsr(msrnum, msr);
 
-	/* Memory Interleave: Set HOI here otherwise default is LOI */
-	/* msrnum = MC_CF8F_DATA;
-	   msr = rdmsr(msrnum);
-	   msr.hi |= CF8F_UPPER_HOI_LOI_SET;
-	   wrmsr(msrnum, msr); */
+	/* Memory Interleave: Set HOI here otherwise default is LOI. */
+#if 0
+	msrnum = MC_CF8F_DATA;
+	msr = rdmsr(msrnum);
+	msr.hi |= CF8F_UPPER_HOI_LOI_SET;
+	wrmsr(msrnum, msr);
+#endif
 }
 
-/** Set SDRAM registers that need to are determined by SPD.
-  * @param dimm0 dimm0 SMBus address
-  * @param dimm1 dimm1 SMBus address
-  */
+/**
+ * Set SDRAM registers that need to be determined by SPD.
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 void sdram_set_spd_registers(u8 dimm0, u8 dimm1)
 {
 	u8 spd_byte;
@@ -591,15 +604,16 @@
 	post_code(POST_MEM_SETUP);
 
 	spd_byte = smbus_read_byte(dimm0, SPD_MODULE_ATTRIBUTES);
-	/* Check DIMM is not Register and not Buffered DIMMs. */
+
+	/* Check DIMM is not Registered and not Buffered DIMMs. */
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		printk(BIOS_EMERG, "dimm0 NOT COMPATIBLE\n");
+		printk(BIOS_EMERG, "DIMM 0 NOT COMPATIBLE!\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hlt();
 	}
 	spd_byte = smbus_read_byte(dimm1, SPD_MODULE_ATTRIBUTES);
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		printk(BIOS_EMERG, "dimm1 NOT COMPATIBLE\n");
+		printk(BIOS_EMERG, "DIMM 1 NOT COMPATIBLE!\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hlt();
 	}
@@ -609,79 +623,85 @@
 	/* Check that the memory is not overclocked. */
 	check_ddr_max(dimm0, dimm1);
 
-	/* Size the DIMMS */
-	/* this is gross. It is an artifact of our move to parametes instead of #defines. FIX ME */
-	/* the fix is trivial but I want to see it work first. */
+	/* Size the DIMMS.
+	 * This is gross. It is an artifact of our move to parametes instead of
+	 * #defines. FIXME! The fix is trivial but I want to see it work first.
+	 */
 	post_code(POST_MEM_SETUP3);
 	auto_size_dimm(dimm0, dimm0, dimm1);
 	post_code(POST_MEM_SETUP4);
 	auto_size_dimm(dimm1, dimm0, dimm1);
 
-	/* Set CAS latency */
+	/* Set CAS latency. */
 	post_code(POST_MEM_SETUP5);
 	set_cas(dimm0, dimm1);
 
-	/* Set all the other latencies here (tRAS, tRP....) */
+	/* Set all the other latencies here (tRAS, tRP...). */
 	set_latencies(dimm0, dimm1);
 
-	/* Set Extended Mode Registers */
+	/* Set Extended Mode Registers. */
 	set_extended_mode_registers(dimm0, dimm1);
 
-	/* Set Memory Refresh Rate */
+	/* Set Memory Refresh Rate. */
 	set_refresh_rate(dimm0, dimm1);
-
 }
 
 /**
-  * enable the DRAMs.
-  * Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
-  * Section 4.1.4, GX/CS5535 GeodeROM Porting guide 
-  * Turn on MC/DIMM interface per JEDEC
-  * 1) Clock stabilizes > 200us
-  * 2) Assert CKE
-  * 3) Precharge All to put all banks into an idles state
-  * 4) EMRS to enable DLL
-  * 6) MRS w/ memory config & reset DLL set
-  * 7) Wait 200 clocks (2us)
-  * 8) Precharge All and 2 Auto refresh
-  * 9) MRS w/ memory config & reset DLL clear
-  * 8) DDR SDRAM ready for normal operation
-  *
-  * @param dimm0 dimm0 SMBus address
-  * @param dimm1 dimm1 SMBus address
-   */
+ * Enable the DRAMs.
+ *
+ * Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
+ * Section 4.1.4, GX/CS5535 GeodeROM Porting guide
+ *
+ * Turn on MC/DIMM interface per JEDEC:
+ *   1) Clock stabilizes > 200us
+ *   2) Assert CKE
+ *   3) Precharge All to put all banks into an idle state
+ *   4) EMRS to enable DLL
+ *   6) MRS w/ memory config & reset DLL set
+ *   7) Wait 200 clocks (2us)
+ *   8) Precharge All and 2 Auto refresh
+ *   9) MRS w/ memory config & reset DLL clear
+ *   8) DDR SDRAM ready for normal operation
+ *
+ * @param dimm0 The SMBus address of DIMM 0 (mainboard-dependent).
+ * @param dimm1 The SMBus address of DIMM 1 (mainboard-dependent).
+ */
 void sdram_enable(u8 dimm0, u8 dimm1)
 {
 	u32 i, msrnum;
 	struct msr msr;
 
-	post_code(POST_MEM_ENABLE);	// post_76h
+	post_code(POST_MEM_ENABLE);
 
-	/* Only enable MTest for TLA memory debug */
-	/*EnableMTest(); */
+	/* Only enable MTest for TLA memory debug. */
+	/* EnableMTest(); */
 
-	/* If both Page Size = "Not Installed" we have a problems and should halt. */
+	/* If both Page Size = "Not Installed" we have a problem and
+	 * should halt.
+	 */
 	msr = rdmsr(MC_CF07_DATA);
-	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == 
-			((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
+	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) |
+			(7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
+			((7 << CF07_UPPER_D1_PSZ_SHIFT) |
+			(7 << CF07_UPPER_D0_PSZ_SHIFT))) {
 		printk(BIOS_EMERG, "No memory in the system\n");
 		post_code(ERROR_NO_DIMMS);
 		hlt();
 	}
 
-	/*      Set CKEs */
+	/* Set CKEs. */
 	msrnum = MC_CFCLK_DBUG;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
 	wrmsr(msrnum, msr);
 
-	/* Force Precharge All on next command, EMRS */
+	/* Force Precharge All on next command, EMRS. */
 	msrnum = MC_CFCLK_DBUG;
 	msr = rdmsr(msrnum);
 	msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
 	wrmsr(msrnum, msr);
 
-	/* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
+	/* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters). */
 	msrnum = MC_CF07_DATA;
 	msr = rdmsr(msrnum);
 	msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
@@ -689,13 +709,13 @@
 	msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
 	wrmsr(msrnum, msr);
 
-	/* Clear Force Precharge All */
+	/* Clear Force Precharge All. */
 	msrnum = MC_CFCLK_DBUG;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
 	wrmsr(msrnum, msr);
 
-	/* MRS Reset DLL - set */
+	/* MRS Reset DLL - set. */
 	msrnum = MC_CF07_DATA;
 	msr = rdmsr(msrnum);
 	msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
@@ -703,23 +723,23 @@
 	msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
 	wrmsr(msrnum, msr);
 
-	/* 2us delay (200 clocks @ 200Mhz). We probably really don't
-	 * need this but....  better safe.
+	/* 2us delay (200 clocks @ 200Mhz). We probably really don't need
+	 * this but... better safe.
+	 *
+	 * Wait two 'port 61 ticks' (between 15us and 30us).
+	 * This would be endless if the timer is stuck.
 	 */
-	/* Wait 2 PORT61 ticks. between 15us and 30us */
-	/* This would be endless if the timer is stuck. */
-	while ((inb(0x61))) ;	/* find the first edge */
-	while (!(~inb(0x61))) ;
+	while ((inb(0x61)));	/* Find the first edge. */
+	while (!(~inb(0x61)));
 
-	/* Force Precharge All on the next command, auto-refresh */
+	/* Force Precharge All on the next command, auto-refresh. */
 	msrnum = MC_CFCLK_DBUG;
 	msr = rdmsr(msrnum);
 	msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
 	wrmsr(msrnum, msr);
 
-	/* Manually AUTO refresh #1 */
-	/* If auto refresh was not enabled above we would need to do 8
-	 * refreshes to prime the pump before these 2.
+	/* Manually AUTO refresh #1. If auto refresh was not enabled above we
+	 * would need to do 8 refreshes to prime the pump before these 2.
 	 */
 	msrnum = MC_CF07_DATA;
 	msr = rdmsr(msrnum);
@@ -728,14 +748,15 @@
 	msr.lo &= ~CF07_LOWER_REF_TEST_SET;
 	wrmsr(msrnum, msr);
 
-	/* Clear Force Precharge All */
+	/* Clear Force Precharge All. */
 	msrnum = MC_CFCLK_DBUG;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
 	wrmsr(msrnum, msr);
 
-	/* Manually AUTO refresh */
-	/* The MC should insert the right delay between the refreshes */
+	/* Manually AUTO refresh.
+	 * The MC should insert the right delay between the refreshes.
+	 */
 	msrnum = MC_CF07_DATA;
 	msr = rdmsr(msrnum);
 	msr.lo |= CF07_LOWER_REF_TEST_SET;
@@ -743,7 +764,7 @@
 	msr.lo &= ~CF07_LOWER_REF_TEST_SET;
 	wrmsr(msrnum, msr);
 
-	/* MRS Reset DLL - clear */
+	/* MRS Reset DLL - clear. */
 	msrnum = MC_CF07_DATA;
 	msr = rdmsr(msrnum);
 	msr.lo |= CF07_LOWER_PROG_DRAM_SET;
@@ -751,13 +772,13 @@
 	msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
 	wrmsr(msrnum, msr);
 
-	/* Allow MC to tristate during idle cycles with MTEST OFF */
+	/* Allow MC to tristate during idle cycles with MTEST OFF. */
 	msrnum = MC_CFCLK_DBUG;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
 	wrmsr(msrnum, msr);
 
-	/* Disable SDCLK dimm1 slot if no DIMM installed to save power. */
+	/* Disable SDCLK DIMM 1 slot if no DIMM installed (to save power). */
 	msr = rdmsr(MC_CF07_DATA);
 	if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
 	    (7 << CF07_UPPER_D1_PSZ_SHIFT)) {
@@ -767,53 +788,54 @@
 		wrmsr(msrnum, msr);
 	}
 
-	/* Set PMode0 Sensitivity Counter */
+	/* Set PMode0 Sensitivity Counter. */
 	msr.lo = 0;		/* pmode 0=0 most aggressive */
 	msr.hi = 0x200;		/* pmode 1=200h */
 	wrmsr(MC_CF_PMCTR, msr);
 
-	/* Set PMode1 Up delay enable */
+	/* Set PMode1 Up delay enable. */
 	msrnum = MC_CF1017_DATA;
 	msr = rdmsr(msrnum);
 	msr.lo |= (209 << 8);	/* bits[15:8] = 209 */
 	wrmsr(msrnum, msr);
 
 	printk(BIOS_DEBUG, "DRAM controller init done.\n");
-	post_code(POST_MEM_SETUP_GOOD);	//0x7E
+	post_code(POST_MEM_SETUP_GOOD);
 
-	/* make sure there is nothing stale in the cache */
+	/* Make sure there is nothing stale in the cache. */
 	/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
 
-	/* The RAM dll needs a write to lock on so generate a few dummy writes */
-	/* Note: The descriptor needs to be enabled to point at memory */
+	/* The RAM dll needs a write to lock on so generate a few dummy
+	 * writes. Note: The descriptor needs to be enabled to point at memory.
+	 */
 	volatile unsigned long *ptr;
 	for (i = 0; i < 5; i++) {
 		ptr = (void *)i;
 		*ptr = (unsigned long)i;
 	}
-	/* SWAPSiF for PBZ 4112 (Errata 34) */
-	/* check for failed DLL settings now that we have done a memory write. */
+
+	/* SWAPSiF for PBZ 4112 (Errata 34)
+	 * Check for failed DLL settings now that we have done a
+	 * memory write.
+	 */
 	msrnum = GLCP_DELAY_CONTROLS;
 	msr = rdmsr(msrnum);
 	if ((msr.lo & 0x7FF) == 0x104) {
+		/* If you had it you would need to clear out the fail boot
+		 * count flag (depending on where it counts from etc).
+		 */
 
-		/* If you had it you would need to clear out the fail
-		 * boot count flag (depending on where it counts from
-		 * etc).
-		  */
-
 		/* The we are about to perform clears the PM_SSC
-		 * register in the 5536 so will need to store the S3
-		 * resume *flag in NVRAM otherwise it would do a
-		 * normal boot
+		 * register in the CS5536 so will need to store the S3
+		 * resume flag in NVRAM otherwise it would do a normal boot.
 		 */
 
-		/* Reset the system */
+		/* Reset the system. */
 		msrnum = MDD_SOFT_RESET;
 		msr = rdmsr(msrnum);
 		msr.lo |= 1;
 		wrmsr(msrnum, msr);
 	}
+
 	printk(BIOS_DEBUG, "RAM DLL lock\n");
-
 }




From tiansm at lemote.com  Sun Jul  8 04:25:44 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Sun, 08 Jul 2007 10:25:44 +0800
Subject: [LinuxBIOS] another question for cs5536
In-Reply-To: <20070707192628.GC5859@greenwood>
References: <468CA4E3.7070501@lemote.com> <468CF0AB.8020304@lemote.com>
	<468D018D.7040701@lemote.com>
	<57947bf80707050914l61b6c96cybb031f952c7a1abc@mail.gmail.com>
	<468D9309.70200@lemote.com> <20070707192628.GC5859@greenwood>
Message-ID: <46904B28.20005@lemote.com>

Uwe Hermann wrote:
> On Fri, Jul 06, 2007 at 08:55:37AM +0800, Songmao Tian wrote:
>   
>> Actually, we are using a non-Geode CPU(in fact it's a mips varient). I 
>> understand the situation, luckily I got
>> helps from all of you:), thanks again.
>>
>> Perhaps I will try to port the LinuxBIOS, but if so, I have to port 
>> another payload(I am looking into grub2, any other sugguestion?)
>>     
>
> GRUB2 is being worked on as part of Google Summer of Code, so that
> should work soonish...
>   
I see you on the list:)
> If you want to port LinuxBIOS to MIPS (which would be great!), please
> start with LinuxBIOSv3, which is still in early development stages but
> is a _lot_ better and easier to handle from a development (and user!)
> point of view.
>   
I am under the way of clean up the start.S code, which is the common 
work of every thing,
also some cache and basic configuration work. after that porting will be 
much easier.
> Other than that, the "typical" payloads in LinuxBIOS are FILO (to boot
> from disk, for example) or memtest86 (for testing the RAM setup while
> developing). I don't know whether either of them support MIPS (guess not).
>
>   

>   
>> and u-boot is another good option.
>>     
>
> Yeah, I've been wondering about this, too. But doesn't u-boot do pretty
> much the same we do in LinuxBIOS (just for other, mainly embedded boards)?
>
> Or can it be configured to basically _not_ init the system (and leave
> that part to LinuxBIOS), but only provide a "shell" of some sort for
> configuration stuff (sorry, I haven't yet played much with u-boot).
>
>   
u-boot trys to be versatile and small, and some tricky relocation is 
done to place itself on the top of the available ram (which I think I 
don't need). but I think with some modification u-boot can be a payload 
of LinuxBIOS:)

> Uwe.
>   




From indrek.kruusa at artecdesign.ee  Mon Jul  9 08:43:49 2007
From: indrek.kruusa at artecdesign.ee (Indrek Kruusa)
Date: Mon, 9 Jul 2007 09:43:49 +0300
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
References: <20070704152956.30330.qmail@stuge.se>
	<20070706174120.GC3605@coresystems.de>
	<20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
Message-ID: <200707090943.49170.indrek.kruusa@artecdesign.ee>

?hel kenal p?eval (laup?ev 07 juuli 2007 1:59 am) kirjutas Joseph Smith:
> Quoting Stefan Reinauer <stepan at coresystems.de>:
> > * Joseph Smith <joe at smittys.pointclark.net> [070706 17:41]:
> >> #define PRINT_DEBUG_DEC(d)
> >>
> >> value=0xff; /* hexadecimal */
> >>
> >> print_debug("value in decimal is now ");
> >> PRINT_DEBUG_DEC(value);
> >> print_debug(" Is this working?\r\n");
> >
> > Since it seems to be for debug only, you can also use
> > print_debug_hex8
> > print_debug_hex16
> > print_debug_hex32
> >
> > Stefan
>
> But that is the whole problem. I already says "print_debug_hex8". I
> want it to display decimal not hex.....

/* Print CPU clock */

        p3 = cpu_clk / 100;
        p2 = (cpu_clk - p3 * 100)/10;
        p1 = cpu_clk - p3 * 100 - p2*10;

        print_info("CPU ");
        print_info_char(48+p3);
        print_info_char(48+p2);
        print_info_char(48+p1);
        print_info(" MHz\r\n");

:)

cheers,
Indrek



From peter at stuge.se  Mon Jul  9 14:32:16 2007
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 Jul 2007 14:32:16 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <200707090943.49170.indrek.kruusa@artecdesign.ee>
References: <20070704152956.30330.qmail@stuge.se>
	<20070706174120.GC3605@coresystems.de>
	<20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
	<200707090943.49170.indrek.kruusa@artecdesign.ee>
Message-ID: <20070709123216.17869.qmail@stuge.se>

inline void print_info_dec(unsigned long value,unsigned long res) {
  for(;res;res/=10)
    print_info_char('0'+value/res%10);
}

On Mon, Jul 09, 2007 at 09:43:49AM +0300, Indrek Kruusa wrote:
>         print_info("CPU ");

print_info_dec(cpu_clk,100);

>         print_info(" MHz\r\n");

Note this only prints the modulus while Indrek's code indicates that
the value does not fit in 3 positions by printing a non-digit
hundreds character.

Multiply the resoluton by 10 to get more digits. 1000=4, 10000=5 etc.

Omitting leading 0:s would need some state to be kept and cost one
more register.


//Peter



From uwe at hermann-uwe.de  Mon Jul  9 21:58:06 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 9 Jul 2007 21:58:06 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop useless Makefiles
Message-ID: <20070709195806.GA11614@greenwood>

See patch (based on original idea from Juergen Beisert).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From joe at smittys.pointclark.net  Mon Jul  9 23:04:43 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Mon, 09 Jul 2007 17:04:43 -0400
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070709123216.17869.qmail@stuge.se>
References: <20070704152956.30330.qmail@stuge.se>
	<20070706174120.GC3605@coresystems.de>
	<20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
	<200707090943.49170.indrek.kruusa@artecdesign.ee>
	<20070709123216.17869.qmail@stuge.se>
Message-ID: <20070709170443.qa55xzn6m8woccos@www.smittys.pointclark.net>

Quoting Peter Stuge <peter at stuge.se>:

> inline void print_info_dec(unsigned long value,unsigned long res) {
>   for(;res;res/=10)
>     print_info_char('0'+value/res%10);
> }
>
> On Mon, Jul 09, 2007 at 09:43:49AM +0300, Indrek Kruusa wrote:
>>         print_info("CPU ");
>
> print_info_dec(cpu_clk,100);
>
>>         print_info(" MHz\r\n");
>
> Note this only prints the modulus while Indrek's code indicates that
> the value does not fit in 3 positions by printing a non-digit
> hundreds character.
>
> Multiply the resoluton by 10 to get more digits. 1000=4, 10000=5 etc.
>
> Omitting leading 0:s would need some state to be kept and cost one
> more register.
>
>
> //Peter
>
Actually, I found this in one of the scripts:

printk_debug("Setting RAM size to %d\n", tomk);

Thanks - Joe



From uwe at hermann-uwe.de  Tue Jul 10 01:26:01 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 10 Jul 2007 01:26:01 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop useless Kconfig files
Message-ID: <20070709232600.GB11614@greenwood>

See patch. Similar approach as with the Makefiles...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Tue Jul 10 04:34:26 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 10 Jul 2007 04:34:26 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop useless Makefiles
In-Reply-To: <20070709195806.GA11614@greenwood>
References: <20070709195806.GA11614@greenwood>
Message-ID: <20070710023425.GC4498@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070709 21:58]:
> Drop a bunch of almost-empty Makefiles which are of no real use.
> 
> Instead unconditionally include _all_ northbridge/southbridge/superio
> Makefiles, but put 'ifeq's in each of them to guard against including
> unwanted contents.
> 
> This may sound like it's very slow when there are many Makefiles, but in
> practice the speed difference is neglectable. A few ad hoc tests I did
> showed no measurable speed differences at all (I used 30 or 40 sample
> Makefiles).
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Tue Jul 10 06:08:19 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 10 Jul 2007 06:08:19 +0200
Subject: [LinuxBIOS] Convert hex to dec
In-Reply-To: <20070709170443.qa55xzn6m8woccos@www.smittys.pointclark.net>
References: <20070704152956.30330.qmail@stuge.se>
	<20070706174120.GC3605@coresystems.de>
	<20070706185932.78aukvd3wwg8ow80@www.smittys.pointclark.net>
	<200707090943.49170.indrek.kruusa@artecdesign.ee>
	<20070709123216.17869.qmail@stuge.se>
	<20070709170443.qa55xzn6m8woccos@www.smittys.pointclark.net>
Message-ID: <20070710040819.GC27459@coresystems.de>

* Joseph Smith <joe at smittys.pointclark.net> [070709 23:04]:
> Actually, I found this in one of the scripts:
> 
> printk_debug("Setting RAM size to %d\n", tomk);
 
print_debug only works in preram stage

printk_debug only works in ram stage

with some exceptions. :-)

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From svn at openbios.org  Tue Jul 10 07:10:30 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 05:10:30 -0000
Subject: [LinuxBIOS] #78: Implement larfs to handle GRUB2 modules in flash
 easily.
Message-ID: <043.7a8969ad7de3bf70e577ae9aab36ad77@openbios.org>

#78: Implement larfs to handle GRUB2 modules in flash easily.
---------------------------------+------------------------------------------
   Reporter:  stepan             |          Owner:  somebody               
       Type:  defect             |         Status:  new                    
   Priority:  major              |      Milestone:  Port GRUB2 to LinuxBIOS
  Component:  code               |        Version:  v3                     
   Keywords:                     |   Dependencies:                         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 Implement a (simple) larfs driver in grub. Besides making it
 easy to solve the module loading itself, it would also help us

 - with copyright issues: if we port over the usb stack from FILO, it
   would not have to be part of the grub2 tree with all the efforts of
   getting it in there

 - with using grub2 as a 1st stage bootloader to load other payloads
   directly from flash, ie payloads that are in multiboot format rather
   than pure ELF. (I have XEN in mind)

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/78>
LinuxBIOS <http://www.linuxbios.org/>

From stepan at coresystems.de  Tue Jul 10 09:21:14 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 10 Jul 2007 09:21:14 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop useless Kconfig files
In-Reply-To: <20070709232600.GB11614@greenwood>
References: <20070709232600.GB11614@greenwood>
Message-ID: <20070710072114.GA17199@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070710 01:26]:
> Index: Kconfig
> ===================================================================
> --- Kconfig	(Revision 439)
> +++ Kconfig	(Arbeitskopie)
> @@ -67,11 +67,27 @@
>  source lib/Kconfig
>  source device/Kconfig
>  
> -# These are used for internal purposes only.
> -source northbridge/Kconfig
> -source southbridge/Kconfig
> -source superio/Kconfig
> +# These are used for internal purposes only:
>  
> +# Northbridges:
> +config NORTHBRIDGE_AMD_GEODELX
> +	boolean
> +config NORTHBRIDGE_INTEL_I440BXEMULATION
> +	boolean
> +
> +# Southbridges:
> +config SOUTHBRIDGE_AMD_CS5536
> +	boolean
> +config SOUTHBRIDGE_INTEL_I82371EB
> +	boolean
> +
> +# Super I/Os:
> +config SUPERIO_WINBOND_W83627HF
> +	boolean
> +
> +# Source all northbridge/southbridge/superio Kconfig files:
> +source northbridge/intel/i440bxemulation/Kconfig
> +
>  menu "Payload"
>  
>  choice

I like the patch. But should we have a Kconfig.components for the above,
as we are going to have many of them at some point.

Otherwise Acked-by: Stefan Reinauer <stepan at coresystems.de>
 
Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Tue Jul 10 09:28:06 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 07:28:06 -0000
Subject: [LinuxBIOS] #79: grub2 loads and executes as payload of the Qemu
 target
Message-ID: <044.a6b58101ab47e4cd7f414f91b1c794be@openbios.org>

#79: grub2 loads and executes as payload of the Qemu target
---------------------------------+------------------------------------------
   Reporter:  oxygene            |          Owner:  oxygene                
       Type:  defect             |         Status:  new                    
   Priority:  major              |      Milestone:  Port GRUB2 to LinuxBIOS
  Component:  code               |        Version:  v3                     
   Keywords:                     |   Dependencies:                         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 For this issue to be done, grub2 should:
  - be able to load modules that are brought in via grub-mkimage
  - be able to use the LinuxBIOSv3 memory map

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/79>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Tue Jul 10 09:30:06 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 07:30:06 -0000
Subject: [LinuxBIOS]  #80: serial console in grub2 works
Message-ID: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>

#80: serial console in grub2 works
---------------------------------+------------------------------------------
   Reporter:  oxygene            |          Owner:  oxygene                
       Type:  enhancement        |         Status:  new                    
   Priority:  major              |      Milestone:  Port GRUB2 to LinuxBIOS
  Component:  code               |        Version:  v3                     
   Keywords:                     |   Dependencies:                         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 grub2 should be capable of using the serial console, just like lbv3 is

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/80>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Tue Jul 10 09:31:01 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 07:31:01 -0000
Subject: [LinuxBIOS]  #81: grub2 vga + keyboard works (text mode)
Message-ID: <044.42d3b2959bb629e9751a77953af832ce@openbios.org>

#81: grub2 vga + keyboard works (text mode)
---------------------------------+------------------------------------------
   Reporter:  oxygene            |          Owner:  oxygene                
       Type:  enhancement        |         Status:  new                    
   Priority:  major              |      Milestone:  Port GRUB2 to LinuxBIOS
  Component:  code               |        Version:  v3                     
   Keywords:                     |   Dependencies:                         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 grub2 should be usable at the console

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/81>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Tue Jul 10 09:32:53 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 07:32:53 -0000
Subject: [LinuxBIOS]  #82: Fix the memory map in LinuxBIOSv3
Message-ID: <044.5bd066a381eb531ec19afe3cb7793c4d@openbios.org>

#82: Fix the memory map in LinuxBIOSv3
---------------------------------+------------------------------------------
   Reporter:  oxygene            |          Owner:  oxygene                
       Type:  defect             |         Status:  new                    
   Priority:  major              |      Milestone:  Setting up LinuxBIOS v3
  Component:  code               |        Version:  v3                     
   Keywords:                     |   Dependencies:                         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 Right now, the memory map in lbv3 is mostly a dummy. Make it represent the
 situation correctly (ie. exclude the areas taken by the ELF image, the lb
 tables, ...)

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/82>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Tue Jul 10 09:35:00 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 07:35:00 -0000
Subject: [LinuxBIOS] #83: grub2 needs to generate its memory map from
 LinuxBIOS
Message-ID: <044.2586510260f6e152c12e60cadf17fdb8@openbios.org>

#83: grub2 needs to generate its memory map from LinuxBIOS
---------------------------------+------------------------------------------
   Reporter:  oxygene            |          Owner:  oxygene                
       Type:  enhancement        |         Status:  new                    
   Priority:  major              |      Milestone:  Port GRUB2 to LinuxBIOS
  Component:  code               |        Version:  v2                     
   Keywords:                     |   Dependencies:  #82                    
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 Grub2 needs to know which memory areas are usable. LinuxBIOSv3 has this
 information, use it.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/83>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Tue Jul 10 09:37:34 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 07:37:34 -0000
Subject: [LinuxBIOS]  #84: grub2 can boot linux from IDE disk
Message-ID: <044.b70ec6a25142eed67ff6f8f078bde54f@openbios.org>

#84: grub2 can boot linux from IDE disk
---------------------------------+------------------------------------------
   Reporter:  oxygene            |          Owner:  oxygene                
       Type:  enhancement        |         Status:  new                    
   Priority:  major              |      Milestone:  Port GRUB2 to LinuxBIOS
  Component:  code               |        Version:  v3                     
   Keywords:                     |   Dependencies:                         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 Grub2 uses BIOS calls right now for access to disk. Replace this with a
 driver that accesses ATA disks directly.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/84>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Tue Jul 10 09:39:38 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 10 Jul 2007 07:39:38 -0000
Subject: [LinuxBIOS] #83: grub2 needs to generate its memory map from
 LinuxBIOS
In-Reply-To: <044.2586510260f6e152c12e60cadf17fdb8@openbios.org>
References: <044.2586510260f6e152c12e60cadf17fdb8@openbios.org>
Message-ID: <053.b5ae9696c8d6f0501facabb3e3271af7@openbios.org>

#83: grub2 needs to generate its memory map from LinuxBIOS
----------------------------+-----------------------------------------------
    Reporter:  oxygene      |         Owner:  oxygene                
        Type:  enhancement  |        Status:  new                    
    Priority:  major        |     Milestone:  Port GRUB2 to LinuxBIOS
   Component:  code         |       Version:  v3                     
  Resolution:               |      Keywords:                         
Dependencies:  #82          |   Patchstatus:  there is no patch      
----------------------------+-----------------------------------------------
Changes (by oxygene):

  * version:  v2 => v3

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/83#comment:1>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Tue Jul 10 14:14:36 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 10 Jul 2007 14:14:36 +0200
Subject: [LinuxBIOS] r440 - in LinuxBIOSv3: . northbridge northbridge/amd
	northbridge/amd/geodelx northbridge/intel
	northbridge/intel/i440bxemulation southbridge southbridge/amd
	southbridge/amd/cs5536 southbridge/intel
	southbridge/intel/i82371eb superio superio/winbond
	superio/winbond/w83627hf
Message-ID: <mailman.506.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-10 14:14:36 +0200 (Tue, 10 Jul 2007)
New Revision: 440

Removed:
   LinuxBIOSv3/northbridge/Makefile
   LinuxBIOSv3/northbridge/amd/Makefile
   LinuxBIOSv3/northbridge/intel/Makefile
   LinuxBIOSv3/southbridge/Makefile
   LinuxBIOSv3/southbridge/amd/Makefile
   LinuxBIOSv3/southbridge/intel/Makefile
   LinuxBIOSv3/superio/Makefile
   LinuxBIOSv3/superio/winbond/Makefile
Modified:
   LinuxBIOSv3/Makefile
   LinuxBIOSv3/northbridge/amd/geodelx/Makefile
   LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile
   LinuxBIOSv3/southbridge/amd/cs5536/Makefile
   LinuxBIOSv3/southbridge/intel/i82371eb/Makefile
   LinuxBIOSv3/superio/winbond/w83627hf/Makefile
Log:
Drop a bunch of almost-empty Makefiles which are of no real use.

Instead unconditionally include _all_ northbridge/southbridge/superio
Makefiles, but put 'ifeq's in each of them to guard against including
unwanted contents.

This may sound like it's very slow when there are many Makefiles, but in
practice the speed difference is neglectable. A few ad hoc tests I did
showed no measurable speed differences at all (I used 30 or 40 sample
Makefiles).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: LinuxBIOSv3/Makefile
===================================================================
--- LinuxBIOSv3/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -109,9 +109,9 @@
 include lib/Makefile
 include device/Makefile
 include mainboard/$(MAINBOARDDIR)/Makefile
-include northbridge/Makefile
-include southbridge/Makefile
-include superio/Makefile
+include northbridge/*/*/Makefile
+include southbridge/*/*/Makefile
+include superio/*/*/Makefile
 include arch/$(ARCH)/Makefile
 
 endif

Deleted: LinuxBIOSv3/northbridge/Makefile
===================================================================
--- LinuxBIOSv3/northbridge/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/northbridge/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,24 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-include $(src)/northbridge/amd/Makefile
-include $(src)/northbridge/intel/Makefile
-

Deleted: LinuxBIOSv3/northbridge/amd/Makefile
===================================================================
--- LinuxBIOSv3/northbridge/amd/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/northbridge/amd/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,25 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
-	include $(src)/northbridge/amd/geodelx/Makefile
-endif
-

Modified: LinuxBIOSv3/northbridge/amd/geodelx/Makefile
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/northbridge/amd/geodelx/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -19,10 +19,15 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o $(obj)/northbridge/amd/geodelx/geodelxinit.o
+ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
 
-$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c $(obj)/statictree.h
+STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
+		      $(obj)/northbridge/amd/geodelx/geodelxinit.o
+
+$(obj)/northbridge/amd/geodelx/%.o: $(src)/northbridge/amd/geodelx/%.c \
+				    $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/northbridge/amd/geodelx
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
+endif

Deleted: LinuxBIOSv3/northbridge/intel/Makefile
===================================================================
--- LinuxBIOSv3/northbridge/intel/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/northbridge/intel/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,25 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
-	include $(src)/northbridge/intel/i440bxemulation/Makefile
-endif
-

Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/northbridge/intel/i440bxemulation/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -19,6 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
+
 STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
 
 $(obj)/northbridge/intel/i440bxemulation/%.o: $(src)/northbridge/intel/i440bxemulation/%.c $(obj)/statictree.h
@@ -26,3 +28,4 @@
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
+endif

Deleted: LinuxBIOSv3/southbridge/Makefile
===================================================================
--- LinuxBIOSv3/southbridge/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/southbridge/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,24 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-include $(src)/southbridge/amd/Makefile
-include $(src)/southbridge/intel/Makefile
-

Deleted: LinuxBIOSv3/southbridge/amd/Makefile
===================================================================
--- LinuxBIOSv3/southbridge/amd/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/southbridge/amd/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,26 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# One entry like the below for each supported AMD southbridge.
-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
-	include $(src)/southbridge/amd/cs5536/Makefile
-endif
-

Modified: LinuxBIOSv3/southbridge/amd/cs5536/Makefile
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/southbridge/amd/cs5536/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -19,10 +19,14 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
+
 STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
 
-$(obj)/southbridge/amd/cs5536/%.o: $(src)/southbridge/amd/cs5536/%.c $(obj)/statictree.h
+$(obj)/southbridge/amd/cs5536/%.o: $(src)/southbridge/amd/cs5536/%.c \
+				   $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/southbridge/amd/cs5536/
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
+endif

Deleted: LinuxBIOSv3/southbridge/intel/Makefile
===================================================================
--- LinuxBIOSv3/southbridge/intel/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/southbridge/intel/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,26 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# One entry like the below for each supported Intel southbridge.
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
-	include $(src)/southbridge/intel/i82371eb/Makefile
-endif
-

Modified: LinuxBIOSv3/southbridge/intel/i82371eb/Makefile
===================================================================
--- LinuxBIOSv3/southbridge/intel/i82371eb/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/southbridge/intel/i82371eb/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -18,10 +18,14 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
+
 STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
 
-$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c $(obj)/statictree.h
+$(obj)/southbridge/intel/i82371eb/%.o: $(src)/southbridge/intel/i82371eb/%.c \
+				       $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/southbridge/intel/i82371eb/
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
+endif

Deleted: LinuxBIOSv3/superio/Makefile
===================================================================
--- LinuxBIOSv3/superio/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/superio/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,23 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-include $(src)/superio/winbond/Makefile
-

Deleted: LinuxBIOSv3/superio/winbond/Makefile
===================================================================
--- LinuxBIOSv3/superio/winbond/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/superio/winbond/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -1,25 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y)
-	include $(src)/superio/winbond/w83627hf/Makefile
-endif
-

Modified: LinuxBIOSv3/superio/winbond/w83627hf/Makefile
===================================================================
--- LinuxBIOSv3/superio/winbond/w83627hf/Makefile	2007-07-08 00:19:26 UTC (rev 439)
+++ LinuxBIOSv3/superio/winbond/w83627hf/Makefile	2007-07-10 12:14:36 UTC (rev 440)
@@ -19,6 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y)
+
 # Always add to variables, as there could be more than one Super I/O.
 STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
 
@@ -27,3 +29,4 @@
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
+endif




From svn at openbios.org  Tue Jul 10 14:30:07 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 10 Jul 2007 14:30:07 +0200
Subject: [LinuxBIOS] r441 - in LinuxBIOSv3: . northbridge northbridge/amd
	northbridge/intel southbridge southbridge/amd
	southbridge/intel superio superio/winbond
Message-ID: <mailman.507.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-10 14:30:07 +0200 (Tue, 10 Jul 2007)
New Revision: 441

Removed:
   LinuxBIOSv3/northbridge/Kconfig
   LinuxBIOSv3/northbridge/amd/Kconfig
   LinuxBIOSv3/northbridge/intel/Kconfig
   LinuxBIOSv3/southbridge/Kconfig
   LinuxBIOSv3/southbridge/amd/Kconfig
   LinuxBIOSv3/southbridge/intel/Kconfig
   LinuxBIOSv3/superio/Kconfig
   LinuxBIOSv3/superio/winbond/Kconfig
Modified:
   LinuxBIOSv3/Kconfig
Log:
Drop a bunch of useless Kconfig files.

Instead of having lots of almost-empty Kconfig files all over the place,
we now collect all the "book-keeping" information (as opposed to real
LinuxBIOS configuration stuff) in one Kconfig file. The benefits are obvious.

Say we have (at some point in the future) 30 supported northbridges, 30
southbridges, and 30 Super I/O chips. That would make 90 useless Kconfig
files with just one or two lines in them, spread all over the place.

With this new approach we would instead have no additional Kconfig
files, just a list of all 90 supported chip(set)s in one Kconfig file.

For "real" config options we would still use Kconfig files in
(e.g.) southbridge/foo/bar/Kconfig, of course, which are manually "hooked"
into the config system in the top-level Kconfig file.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: LinuxBIOSv3/Kconfig
===================================================================
--- LinuxBIOSv3/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -67,11 +67,27 @@
 source lib/Kconfig
 source device/Kconfig
 
-# These are used for internal purposes only.
-source northbridge/Kconfig
-source southbridge/Kconfig
-source superio/Kconfig
+# These are used for internal purposes only:
 
+# Northbridges:
+config NORTHBRIDGE_AMD_GEODELX
+	boolean
+config NORTHBRIDGE_INTEL_I440BXEMULATION
+	boolean
+
+# Southbridges:
+config SOUTHBRIDGE_AMD_CS5536
+	boolean
+config SOUTHBRIDGE_INTEL_I82371EB
+	boolean
+
+# Super I/Os:
+config SUPERIO_WINBOND_W83627HF
+	boolean
+
+# Source all northbridge/southbridge/superio Kconfig files:
+source northbridge/intel/i440bxemulation/Kconfig
+
 menu "Payload"
 
 choice

Deleted: LinuxBIOSv3/northbridge/Kconfig
===================================================================
--- LinuxBIOSv3/northbridge/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/northbridge/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,24 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-source northbridge/amd/Kconfig
-source northbridge/intel/Kconfig
-

Deleted: LinuxBIOSv3/northbridge/amd/Kconfig
===================================================================
--- LinuxBIOSv3/northbridge/amd/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/northbridge/amd/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,27 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config NORTHBRIDGE_AMD_GEODELX
-	boolean
-	help
-	  This option is internally used to decide which northbridge code to
-	  use. It is set in the mainboard Kconfig file.
-

Deleted: LinuxBIOSv3/northbridge/intel/Kconfig
===================================================================
--- LinuxBIOSv3/northbridge/intel/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/northbridge/intel/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,29 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config NORTHBRIDGE_INTEL_I440BXEMULATION
-	boolean
-	help
-	  This option is internally used to decide which northbridge code to
-	  use. It is set in the mainboard Kconfig file.
-
-source northbridge/intel/i440bxemulation/Kconfig
-

Deleted: LinuxBIOSv3/southbridge/Kconfig
===================================================================
--- LinuxBIOSv3/southbridge/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/southbridge/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,24 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-source southbridge/amd/Kconfig
-source southbridge/intel/Kconfig
-

Deleted: LinuxBIOSv3/southbridge/amd/Kconfig
===================================================================
--- LinuxBIOSv3/southbridge/amd/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/southbridge/amd/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,27 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config SOUTHBRIDGE_AMD_CS5536
-	boolean
-	help
-	  This option is internally used to decide which southbridge code to
-	  use. It is set in the mainboard Kconfig file.
-

Deleted: LinuxBIOSv3/southbridge/intel/Kconfig
===================================================================
--- LinuxBIOSv3/southbridge/intel/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/southbridge/intel/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,27 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config SOUTHBRIDGE_INTEL_I82371EB
-	boolean
-	help
-	  This option is internally used to decide which southbridge code to
-	  use. It is set in the mainboard Kconfig file.
-

Deleted: LinuxBIOSv3/superio/Kconfig
===================================================================
--- LinuxBIOSv3/superio/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/superio/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,23 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-source superio/winbond/Kconfig
-

Deleted: LinuxBIOSv3/superio/winbond/Kconfig
===================================================================
--- LinuxBIOSv3/superio/winbond/Kconfig	2007-07-10 12:14:36 UTC (rev 440)
+++ LinuxBIOSv3/superio/winbond/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
@@ -1,27 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config SUPERIO_WINBOND_W83627HF
-	boolean
-	help
-	  This option is internally used to decide which Super I/O code to
-	  use. It is set in the mainboard Kconfig file.
-




From george at kami.ru  Tue Jul 10 19:29:13 2007
From: george at kami.ru (George V. Adamov)
Date: Tue, 10 Jul 2007 17:29:13 +0000
Subject: [LinuxBIOS] Porting linux bios to MSI ms7250
Message-ID: <4693C1E9.7000202@kami.ru>

Finally RAM is up ), but have another problem:


-------------------------------------------------------------
LinuxBIOS-2.0.0_Fallback Tue Jul 10 16:09:10 UTC 2007 starting...
bist==0 cpus inited
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
core0 started:
setup_coherent_ht_domain()started ap apicid:  01
start_other_cores()SBLink=00
NC node|link=00
begin msr fid, vid 310c12120c0c0202
end   msr fid, vid 310c120c0c0c020c
mcp55_num:01
ht reset -


LinuxBIOS-2.0.0_Fallback Tue Jul 10 16:09:10 UTC 2007 starting...
bist==0 cpus inited
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
core0 started:
setup_coherent_ht_domain()started ap apicid:  01
start_other_cores()SBLink=00
NC node|link=00
begin msr fid, vid 310c120c0c0c020c
end   msr fid, vid 310c120c0c0c020c
mcp55_num:01
allow_all_aps_stopfill_mem_ctrlenable_smbus()memreset_setup()sdram_initialize 
- started
Ram1.00
setting up CPU00Ram2.00
sdram_set_spd_registers: starting
activate_spd_rom: nothing needs to be done
DDR2 DIMM FOUND CH0
DDR2 DIMM FOUND CH1
spd_enable_2channels
Enabling dual channel memory
Unbuffered
333Mhz
RAM: 0x00100000 KB
Ram3
\0x09dimm_mask = 00000011
\0x09x4_mask = 00000000
\0x09x16_mask = 00000000
\0x09single_rank_mask = 00000001
\0x09ODC = 00111222
\0x09Addr Timing= 00202220
clock started
Initializing memory:  done
Setting variable MTRR 02, base: 0000MB, range: 0400MB, type WB
DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1a done
DQS Training:DQSPos: 00 done
DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=34 done
DQS Training:tsc[00]=000000003f0c3502
DQS Training:tsc[01]=0000000040c5316e
DQS Training:tsc[02]=0000000040c53177
DQS Training:tsc[03]=00000000807d1167
DQS Training:tsc[04]=00000000822ed6d9
Ram4
sdram_initialize - finished
sdram_initialize
/*source must be here... but only 0xff */

 dump_mem:
fffe0000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dump_mem:

/*I wrote 0x12345678 to 0x00100000 to test RAM - and it clearly can be 
seen that it is ok*/

00100000: 78 56 34 12 21 43 65 87 89 67 45 23 32 54 76 98
00100010: 24 58 38 59 24 67 49 30 95 07 49 24 33 87 93 99
00100020: 42 56 38 40 45 52 46 38 63 21 43 29 94 78 06 05
00100030: 45 90 34 12 67 34 72 98 34 76 38 12 23 76 58 34
00100040: 00 00 00 00 00 00 00 00 24 29 00 00 00 60 bd fd
00100050: ff ff ff ff ff ff ff ff 00 00 00 08 00 00 00 00
00100060: 00 00 00 00 00 00 00 00 67 23 00 00 00 20 bd ff
00100070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100080: fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe
00100090: 01 01 01 01 01 01 01 01 c5 fe 01 01 00 f4 fc c1
001000a0: fe fe fe fe fe fe fe fe 00 00 10 fe 12 00 00 10
001000b0: 01 01 01 01 01 01 01 01 c5 fe 01 01 00 fc fc c1
001000c0: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
001000d0: fe fe fe fe fe fe fe fe 00 00 00 68 00 00 00 00
001000e0: fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe
001000f0: 01 01 01 01 01 01 01 01 c5 fe 01 01 00 fc fc d9


12345678v_esp=000ceddc

testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... G 
versionDone
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Copying LinuxBIOS to RAM. -AMD
src=fffe0000
dst=00100000
dump_mem:
fffe0000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dump_mem:
/*after it has bee zeroed*/
00100000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

-----------------------------------------------------------------------------------

I opened linuxbios_ram.nrv2b, checked it?s location in linuxbios.rom 
(file I flash to ram), calculated the offset and got 0xfffe0000, so the 
offset seems to be ok, but in the memory only 0xff...
any ideas?



From svn at openbios.org  Tue Jul 10 16:38:01 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 10 Jul 2007 16:38:01 +0200
Subject: [LinuxBIOS] r442 - in LinuxBIOSv3: . arch mainboard/emulation
Message-ID: <mailman.508.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-10 16:38:01 +0200 (Tue, 10 Jul 2007)
New Revision: 442

Removed:
   LinuxBIOSv3/arch/Kconfig
   LinuxBIOSv3/arch/powerpc/
Modified:
   LinuxBIOSv3/Kconfig
   LinuxBIOSv3/mainboard/emulation/Kconfig
Log:
Drop unused and non-working PowerPC stubs for now (trivial).
Will be re-added as soon as we support PowerPC in v3, of course.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/Kconfig
===================================================================
--- LinuxBIOSv3/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
+++ LinuxBIOSv3/Kconfig	2007-07-10 14:38:01 UTC (rev 442)
@@ -63,7 +63,7 @@
 endmenu
 
 source mainboard/Kconfig
-source arch/Kconfig
+source arch/x86/Kconfig
 source lib/Kconfig
 source device/Kconfig
 

Deleted: LinuxBIOSv3/arch/Kconfig
===================================================================
--- LinuxBIOSv3/arch/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
+++ LinuxBIOSv3/arch/Kconfig	2007-07-10 14:38:01 UTC (rev 442)
@@ -1,25 +0,0 @@
-##
-## This file is part of the LinuxBIOS project.
-##
-## Copyright (C) 2006 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-# Source all architectures.
-source arch/x86/Kconfig
-source arch/powerpc/Kconfig
-

Modified: LinuxBIOSv3/mainboard/emulation/Kconfig
===================================================================
--- LinuxBIOSv3/mainboard/emulation/Kconfig	2007-07-10 12:30:07 UTC (rev 441)
+++ LinuxBIOSv3/mainboard/emulation/Kconfig	2007-07-10 14:38:01 UTC (rev 442)
@@ -35,13 +35,6 @@
 	help
 	  x86 QEMU variant.
 
-config BOARD_EMULATION_QEMU_POWERPC
-	bool "PowerPC QEMU (EXPERIMENTAL)"
-	depends on EXPERIMENTAL
-	select ARCH_POWERPC
-	help
-	  PowerPC QEMU variant.
-
 endchoice
 
 source "mainboard/emulation/qemu-x86/Kconfig"




From stepan at coresystems.de  Tue Jul 10 18:20:06 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 10 Jul 2007 18:20:06 +0200
Subject: [LinuxBIOS] r442 - in LinuxBIOSv3: . arch mainboard/emulation
Message-ID: <20070710162006.GC30240@coresystems.de>

* svn at openbios.org <svn at openbios.org> [070710 16:38]:
> Author: uwe
> Date: 2007-07-10 16:38:01 +0200 (Tue, 10 Jul 2007)
> New Revision: 442
> 
> Removed:
>    LinuxBIOSv3/arch/Kconfig
>    LinuxBIOSv3/arch/powerpc/
> Modified:
>    LinuxBIOSv3/Kconfig
>    LinuxBIOSv3/mainboard/emulation/Kconfig
> Log:
> Drop unused and non-working PowerPC stubs for now (trivial).
> Will be re-added as soon as we support PowerPC in v3, of course.

Please don't drop stuff arbitrarily. Dropping stuff like this is never
trivial. :-(

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From uwe at hermann-uwe.de  Tue Jul 10 19:25:51 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 10 Jul 2007 19:25:51 +0200
Subject: [LinuxBIOS] r442 - in LinuxBIOSv3: . arch mainboard/emulation
In-Reply-To: <20070710162006.GC30240@coresystems.de>
References: <20070710162006.GC30240@coresystems.de>
Message-ID: <20070710172551.GA12003@greenwood>

On Tue, Jul 10, 2007 at 06:20:06PM +0200, Stefan Reinauer wrote:
> * svn at openbios.org <svn at openbios.org> [070710 16:38]:
> > Author: uwe
> > Date: 2007-07-10 16:38:01 +0200 (Tue, 10 Jul 2007)
> > New Revision: 442
> > 
> > Removed:
> >    LinuxBIOSv3/arch/Kconfig
> >    LinuxBIOSv3/arch/powerpc/
> > Modified:
> >    LinuxBIOSv3/Kconfig
> >    LinuxBIOSv3/mainboard/emulation/Kconfig
> > Log:
> > Drop unused and non-working PowerPC stubs for now (trivial).
> > Will be re-added as soon as we support PowerPC in v3, of course.
> 
> Please don't drop stuff arbitrarily. Dropping stuff like this is never
> trivial. :-(

Yeah, I was a bit too enthusiastic maybe. Dropping stuff is a lot of fun, after
all :) I'll send a patch next time. But it sure makes sense to drop the
PowerPC dummy files as long as we don't really have PowerPC support, IMO.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Jul 10 19:26:37 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 10 Jul 2007 19:26:37 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop useless Makefiles
In-Reply-To: <20070710023425.GC4498@coresystems.de>
References: <20070709195806.GA11614@greenwood>
	<20070710023425.GC4498@coresystems.de>
Message-ID: <20070710172637.GB12003@greenwood>

On Tue, Jul 10, 2007 at 04:34:26AM +0200, Stefan Reinauer wrote:
> Acked-by: Stefan Reinauer <stepan at coresystems.de>

r440.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Tue Jul 10 19:28:07 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 10 Jul 2007 19:28:07 +0200
Subject: [LinuxBIOS] [PATCH][v3] Drop useless Kconfig files
In-Reply-To: <20070710072114.GA17199@coresystems.de>
References: <20070709232600.GB11614@greenwood>
	<20070710072114.GA17199@coresystems.de>
Message-ID: <20070710172807.GC12003@greenwood>

On Tue, Jul 10, 2007 at 09:21:14AM +0200, Stefan Reinauer wrote:
> I like the patch. But should we have a Kconfig.components for the above,
> as we are going to have many of them at some point.
> 
> Otherwise Acked-by: Stefan Reinauer <stepan at coresystems.de>

r441.

Yeah, I think a Kconfig.components or similar makes sense on the long
run. I'd say we postpone adding the file until we have a lot
more components in v3, though.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Tue Jul 10 19:29:31 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 10 Jul 2007 19:29:31 +0200
Subject: [LinuxBIOS] r442 - in LinuxBIOSv3: . arch mainboard/emulation
In-Reply-To: <20070710172551.GA12003@greenwood>
References: <20070710162006.GC30240@coresystems.de>
	<20070710172551.GA12003@greenwood>
Message-ID: <20070710172931.GA20223@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070710 19:25]:
> Yeah, I was a bit too enthusiastic maybe. Dropping stuff is a lot of fun, after
> all :) I'll send a patch next time. But it sure makes sense to drop the
> PowerPC dummy files as long as we don't really have PowerPC support, IMO.

I'd rather consider it a skeleton for someone who wants to start porting
but does not know where to go, or as a start of moving things over from
v2, lacking a hw platform.

It was almost nothing, really, so it probably doesnt matter.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From svn at openbios.org  Tue Jul 10 21:44:22 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 10 Jul 2007 21:44:22 +0200
Subject: [LinuxBIOS] r443 - LinuxBIOSv3/southbridge/amd/cs5536
Message-ID: <mailman.509.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-10 21:44:22 +0200 (Tue, 10 Jul 2007)
New Revision: 443

Modified:
   LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c
   LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h
   LinuxBIOSv3/southbridge/amd/cs5536/dts
   LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c
   LinuxBIOSv3/southbridge/amd/cs5536/stage1.c
Log:
Various coding style fixes and cosmetics (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c	2007-07-10 14:38:01 UTC (rev 442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c	2007-07-10 19:44:22 UTC (rev 443)
@@ -36,10 +36,10 @@
 
 struct msrinit {
 	u32 msrnum;
-	struct msr  msr;
+	struct msr msr;
 };
 
-/*	Master Configuration Register for Bus Masters.*/
+/* Master configuration register for bus masters */
 struct msrinit SB_MASTER_CONF_TABLE[] = {
 	{USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
 	{ATA_SB_GLD_MSR_CONF,  {.hi = 0,.lo = 0x00048f000}},
@@ -48,9 +48,9 @@
 	{0, {0, 0}}
 };
 
-/*	5536 Clock Gating*/
+/* CS5536 clock gating */
 struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
-	/* MSR		  Setting*/
+	/* MSR                Setting */
 	{GLIU_SB_GLD_MSR_PM,  {.hi = 0,.lo = 0x000000004}},
 	{GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
 	{GLCP_SB_GLD_MSR_PM,  {.hi = 0,.lo = 0x000000004}},
@@ -67,23 +67,23 @@
 
 struct acpiinit acpi_init_table[] = {
 	{ACPI_IO_BASE + 0x00, 0x01000000},
-	{ACPI_IO_BASE + 0x08, 0},
-	{ACPI_IO_BASE + 0x0C, 0},
-	{ACPI_IO_BASE + 0x1C, 0},
-	{ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},
+	{ACPI_IO_BASE + 0x08, 0x00000000},
+	{ACPI_IO_BASE + 0x0C, 0x00000000},
+	{ACPI_IO_BASE + 0x1C, 0x00000000},
+	{ACPI_IO_BASE + 0x18, 0xFFFFFFFF},
 	{ACPI_IO_BASE + 0x00, 0x0000FFFF},
 	{PMS_IO_BASE + PM_SCLK, 0x000000E00},
-	{PMS_IO_BASE + PM_SED, 0x000004601},
+	{PMS_IO_BASE + PM_SED,  0x000004601},
 	{PMS_IO_BASE + PM_SIDD, 0x000008C02},
-	{PMS_IO_BASE + PM_WKD, 0x0000000A0},
+	{PMS_IO_BASE + PM_WKD,  0x0000000A0},
 	{PMS_IO_BASE + PM_WKXD, 0x0000000A0},
 	{0, 0}
 };
 
 struct FLASH_DEVICE {
-	unsigned char fType;	/* Flash type: NOR or NAND */
-	unsigned char fInterface;	/* Flash interface: I/O or Memory */
-	unsigned long fMask;	/* Flash size/mask */
+	unsigned char fType;		/* Flash type: NOR or NAND */
+	unsigned char fInterface;	/* Flash interface: I/O or memory */
+	unsigned long fMask;		/* Flash size/mask */
 };
 
 struct FLASH_DEVICE FlashInitTable[] = {
@@ -101,8 +101,8 @@
 };
 
 /**
-  *	Program ACPI LBAR and initialize ACPI registers. 
-  */
+ * Program ACPI LBAR and initialize ACPI registers.
+ */
 static void pm_chipset_init(void)
 {
 	u32 val = 0;
@@ -112,47 +112,45 @@
 	val = 0x0E00;		/*  1ms */
 	outl(val, port);
 
-	/*      PM_WKXD */
-	/*      Make sure bits[3:0]=0000b to clear the */
-	/*      saved Sx state */
+	/* PM_WKXD */
+	/* Make sure bits[3:0]=0000b to clear the saved Sx state. */
 	port = (PMS_IO_BASE + PM_WKXD);
 	val = 0x0A0;		/*  5ms */
 	outl(val, port);
 
-	/*      PM_WKD */
+	/* PM_WKD */
 	port = (PMS_IO_BASE + PM_WKD);
 	outl(val, port);
 
-	/*      PM_SED */
+	/* PM_SED */
 	port = (PMS_IO_BASE + PM_SED);
 	val = 0x04601;		/*  5ms, # of 3.57954MHz clock edges */
 	outl(val, port);
 
-	/*      PM_SIDD */
+	/* PM_SIDD */
 	port = (PMS_IO_BASE + PM_SIDD);
 	val = 0x08C02;		/*  10ms, # of 3.57954MHz clock edges */
 	outl(val, port);
 }
 
-/**	
-  * Flash LBARs need to be setup before VSA init so the PCI BARs have
-  *	correct size info.	Call this routine only if flash needs to be
-  *	configured (don't call it if you want IDE).
-  *
-  */
+/**
+ * Flash LBARs need to be setup before VSA init so the PCI BARs have
+ * correct size info. Call this routine only if flash needs to be
+ * configured (don't call it if you want IDE).
+ */
 static void chipset_flash_setup(void)
 {
-	struct msr  msr;
 	int i;
+	struct msr msr;
 	int numEnabled = 0;
 
 	printk(BIOS_DEBUG, "chipset_flash_setup: Start\n");
 	for (i = 0; i < ARRAY_SIZE(FlashInitTable); i++) {
 		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
 			printk(BIOS_DEBUG, "Enable CS%d\n", i);
-			/* we need to configure the memory/IO mask */
+			/* We need to configure the memory/IO mask. */
 			msr = rdmsr(FlashPort[i]);
-			msr.hi = 0;	/* start with the "enabled" bit clear */
+			msr.hi = 0;	/* Start with "enabled" bit clear. */
 			if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
 				msr.hi |= 0x00000002;
 			else
@@ -162,30 +160,28 @@
 			else
 				msr.hi &= ~0x00000004;
 			msr.hi |= FlashInitTable[i].fMask;
-			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
-				     msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n",
+			       FlashPort[i], msr.hi, msr.lo);
 			wrmsr(FlashPort[i], msr);
 
-			/* now write-enable the device */
+			/* Now write-enable the device. */
 			msr = rdmsr(MDD_NORF_CNTRL);
 			msr.lo |= (1 << i);
-			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
-				     msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n",
+			       MDD_NORF_CNTRL, msr.hi, msr.lo);
 			wrmsr(MDD_NORF_CNTRL, msr);
 
-			/* update the number enabled */
+			/* Update the number enabled. */
 			numEnabled++;
 		}
 	}
-
 	printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n");
-
 }
 
 /**
-  * Use this in the event that you have a FLASH part instead of an IDE drive. 
-  *Run after VSA init to enable the flash PCI device header
-  */
+ * Use this in the event that you have a FLASH part instead of an IDE drive.
+ * Run after VSA init to enable the flash PCI device header.
+ */
 static void enable_ide_nand_flash_header(void)
 {
 	/* Tell VSA to use FLASH PCI header. Not IDE header. */
@@ -193,19 +189,22 @@
 	outl(0xDEADBEEF, 0xCFC);
 }
 
-#define RTC_CENTURY 0x32
+#define RTC_CENTURY	0x32
 #define RTC_DOMA	0x3D
 #define RTC_MONA	0x3E
 
 /**
-  * standard init function for the lpc bus. Sets up the "serial irq" interrupt, 
-  * which is NOT the same as serial interrupt, and also enables DMA from 
-  * the LPC bus. Configures the PC clock, enables rtc and ISA DMA. 
-  * @param southbridge config structure 
-  */
+ * Standard init function for the LPC bus.
+ *
+ * Sets up the "serial irq" interrupt, which is NOT the same as serial
+ * interrupt, and also enables DMA from the LPC bus. Configures the PC clock,
+ * enables RTC and ISA DMA.
+ *
+ * @param sb Southbridge config structure.
+ */
 static void lpc_init(struct southbridge_amd_cs5536_config *sb)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	if (sb->lpc_serirq_enable) {
 		msr.lo = sb->lpc_serirq_enable;
@@ -213,23 +212,23 @@
 		wrmsr(MDD_IRQM_LPC, msr);
 		if (sb->lpc_serirq_polarity) {
 			msr.lo = sb->lpc_serirq_polarity << 16;
-			msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7);	/* enable */
+			msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7);	/* Enable */
 			msr.hi = 0;
 			wrmsr(MDD_LPC_SIRQ, msr);
 		}
 	}
 
-	/* Allow DMA from LPC */
+	/* Allow DMA from LPC. */
 	msr = rdmsr(MDD_DMA_MAP);
 	msr.lo = 0x7777;
 	wrmsr(MDD_DMA_MAP, msr);
 
-	/* enable the RTC/CMOS century byte at address 32h */
+	/* Enable the RTC/CMOS century byte at address 0x32. */
 	msr = rdmsr(MDD_RTC_CENTURY_OFFSET);
 	msr.lo = RTC_CENTURY;
 	wrmsr(MDD_RTC_CENTURY_OFFSET, msr);
 
-	/* enable the RTC/CMOS day of month and month alarms */
+	/* Enable the RTC/CMOS day of month and month alarms. */
 	msr = rdmsr(MDD_RTC_DOMA_IND);
 	msr.lo = RTC_DOMA;
 	wrmsr(MDD_RTC_DOMA_IND, msr);
@@ -243,43 +242,42 @@
 	isa_dma_init();
 }
 
-/** 
- * Depending on settings in the config struct, enable COM1 or COM2 or both. 
- * If the enable is NOT set, the UARTS are explicitly disabled, which is required 
- * if (e.g.) there is a superio attached that does COM1 or COM2.
-  * @param southbridge config structure 
-  */
+/**
+ * Depending on settings in the config struct, enable COM1 or COM2 or both.
+ *
+ * If the enable is NOT set, the UARTs are explicitly disabled, which is
+ * required if (e.g.) there is a Super I/O attached that does COM1 or COM2.
+ *
+ * @param sb Southbridge config structure.
+ */
 static void uarts_init(struct southbridge_amd_cs5536_config *sb)
 {
-	struct msr  msr;
+	struct msr msr;
 	u16 addr = 0;
 	u32 gpio_addr;
 	struct device *dev;
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-			PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
+			      PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
 	gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
-	gpio_addr &= ~1;	/* clear IO bit */
+	gpio_addr &= ~1;	/* Clear I/O bit */
 	printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
 
-	/* This could be extended to support IR modes */
+	/* This could be extended to support IR modes. */
 
 	/* COM1 */
 	if (sb->com1_enable) {
-		/* Set the address */
+		/* Set the address. */
 		switch (sb->com1_address) {
 		case 0x3F8:
 			addr = 7;
 			break;
-
 		case 0x3E8:
 			addr = 6;
 			break;
-
 		case 0x2F8:
 			addr = 5;
 			break;
-
 		case 0x2E8:
 			addr = 4;
 			break;
@@ -288,42 +286,44 @@
 		msr.lo |= addr << 16;
 		wrmsr(MDD_LEG_IO, msr);
 
-		/* Set the IRQ */
+		/* Set the IRQ. */
 		msr = rdmsr(MDD_IRQM_YHIGH);
 		msr.lo |= sb->com1_irq << 24;
 		wrmsr(MDD_IRQM_YHIGH, msr);
 
 		/* GPIO8 - UART1_TX */
-		/* Set: Output Enable  (0x4) */
+		/* Set: Output Enable (0x4) */
 		outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
 		/* Set: OUTAUX1 Select (0x10) */
 		outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
 
 		/* GPIO8 - UART1_RX */
-		/* Set: Input Enable   (0x20) */
+		/* Set: Input Enable (0x20) */
 		outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);
-		/* Set: INAUX1 Select  (0x34) */
+		/* Set: INAUX1 Select (0x34) */
 		outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
 
-		/* Set: GPIO 8 + 9 Pull Up         (0x18) */
+		/* Set: GPIO 8 + 9 Pull Up (0x18) */
 		outl(GPIOL_8_SET | GPIOL_9_SET,
 		     gpio_addr + GPIOL_PULLUP_ENABLE);
 
-		/* enable COM1 */
-		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
+		/* Enable COM1.
+		 *
+		 * Bit 1 = device enable
+		 * Bit 4 = allow access to the upper banks
+		 */
 		msr.lo = (1 << 4) | (1 << 1);
 		msr.hi = 0;
 		wrmsr(MDD_UART1_CONF, msr);
-
 	} else {
-		/* Reset and disable COM1 */
+		/* Reset and disable COM1. */
 		msr = rdmsr(MDD_UART1_CONF);
-		msr.lo = 1;	// reset
+		msr.lo = 1;			/* Reset */
 		wrmsr(MDD_UART1_CONF, msr);
-		msr.lo = 0;	// disabled
+		msr.lo = 0;			/* Disabled */
 		wrmsr(MDD_UART1_CONF, msr);
 
-		/* Disable the IRQ */
+		/* Disable the IRQ. */
 		msr = rdmsr(MDD_LEG_IO);
 		msr.lo &= ~(0xF << 16);
 		wrmsr(MDD_LEG_IO, msr);
@@ -335,15 +335,12 @@
 		case 0x3F8:
 			addr = 7;
 			break;
-
 		case 0x3E8:
 			addr = 6;
 			break;
-
 		case 0x2F8:
 			addr = 5;
 			break;
-
 		case 0x2E8:
 			addr = 4;
 			break;
@@ -352,42 +349,44 @@
 		msr.lo |= addr << 20;
 		wrmsr(MDD_LEG_IO, msr);
 
-		/* Set the IRQ */
+		/* Set the IRQ. */
 		msr = rdmsr(MDD_IRQM_YHIGH);
 		msr.lo |= sb->com2_irq << 28;
 		wrmsr(MDD_IRQM_YHIGH, msr);
 
 		/* GPIO3 - UART2_RX */
-		/* Set: Output Enable  (0x4) */
+		/* Set: Output Enable (0x4) */
 		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
 		/* Set: OUTAUX1 Select (0x10) */
 		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
 
 		/* GPIO4 - UART2_TX */
-		/* Set: Input Enable   (0x20) */
+		/* Set: Input Enable (0x20) */
 		outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
-		/* Set: INAUX1 Select  (0x34) */
+		/* Set: INAUX1 Select (0x34) */
 		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
 
-		/* Set: GPIO 3 + 3 Pull Up         (0x18) */
+		/* Set: GPIO 3 + 3 Pull Up (0x18) */
 		outl(GPIOL_3_SET | GPIOL_4_SET,
 		     gpio_addr + GPIOL_PULLUP_ENABLE);
 
-		/* enable COM2 */
-		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
+		/* Enable COM2.
+		 *
+		 * Bit 1 = device enable
+		 * Bit 4 = allow access to the upper banks
+		 */
 		msr.lo = (1 << 4) | (1 << 1);
 		msr.hi = 0;
 		wrmsr(MDD_UART2_CONF, msr);
-
 	} else {
-		/* Reset and disable COM2 */
+		/* Reset and disable COM2. */
 		msr = rdmsr(MDD_UART2_CONF);
-		msr.lo = 1;	// reset
+		msr.lo = 1;			/* Reset */
 		wrmsr(MDD_UART2_CONF, msr);
-		msr.lo = 0;	// disabled
+		msr.lo = 0;			/* Disabled */
 		wrmsr(MDD_UART2_CONF, msr);
 
-		/* Disable the IRQ */
+		/* Disable the IRQ. */
 		msr = rdmsr(MDD_LEG_IO);
 		msr.lo &= ~(0xF << 20);
 		wrmsr(MDD_LEG_IO, msr);
@@ -396,51 +395,51 @@
 
 #define HCCPARAMS		0x08
 #define IPREG04			0xA0
-	#define USB_HCCPW_SET	(1 << 1)
+#define USB_HCCPW_SET		(1 << 1)
 #define UOCCAP			0x00
-	#define APU_SET			(1 << 15)
+#define APU_SET			(1 << 15)
 #define UOCMUX			0x04
 #define PMUX_HOST		0x02
 #define PMUX_DEVICE		0x03
-	#define PUEN_SET		(1 << 2)
+#define PUEN_SET		(1 << 2)
 #define UDCDEVCTL		0x404
-	#define UDC_SD_SET		(1 << 10)
+#define UDC_SD_SET		(1 << 10)
 #define UOCCTL			0x0C
-	#define PADEN_SET		(1 << 7)
+#define PADEN_SET		(1 << 7)
 
-/** 
- * Depending on settings in the config struct, manage USB setup.  
-  * @param southbridge config structure 
-  */
+/**
+ * Depending on settings in the config struct, manage USB setup.
+ *
+ * @param sb Southbridge config structure.
+ */
 static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 {
 	u32 *bar;
-	struct msr  msr;
+	struct msr msr;
 	struct device *dev;
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-			PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
+			      PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
 	if (dev) {
-
-		/* Serial Short Detect Enable */
+		/* Serial short detect enable */
 		msr = rdmsr(USB2_SB_GLD_MSR_CONF);
 		msr.hi |= USB2_UPPER_SSDEN_SET;
 		wrmsr(USB2_SB_GLD_MSR_CONF, msr);
 
-		/* write to clear diag register */
+		/* Write to clear diag register. */
 		wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
 
 		bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
-		/* Make HCCPARAMS writeable */
+		/* Make HCCPARAMS writable. */
 		*(bar + IPREG04) |= USB_HCCPW_SET;
 
-		/* ; EECP=50h, IST=01h, ASPC=1 */
+		/* EECP=50h, IST=01h, ASPC=1 */
 		*(bar + HCCPARAMS) = 0x00005012;
 	}
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
+			      PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
 		bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
@@ -459,155 +458,155 @@
 		}
 	}
 
-	/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,
-	 *      then perform the following sequence:
-	 *
-	 * - set SD bit in DEVCTRL udc register
-	 * - set PADEN (former OTGPADEN) bit in uoc register
-	 * - set APU bit in uoc register */
+	/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a
+	 * device, then perform the following sequence:
+	 *  - Set SD bit in DEVCTRL udc register
+	 *  - Set PADEN (former OTGPADEN) bit in uoc register
+	 *  - Set APU bit in uoc register
+	 */
 	if (sb->enable_USBP4_device) {
-		dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-				PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+		dev = dev_find_device(PCI_VENDOR_ID_AMD,
+				      PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 		if (dev) {
-			bar = (u32 *) pci_read_config32(dev, 
-					PCI_BASE_ADDRESS_0);
+			bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			*(bar + UDCDEVCTL) |= UDC_SD_SET;
-
 		}
 
 		dev = dev_find_device(PCI_VENDOR_ID_AMD,
-				PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+				      PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 		if (dev) {
-			bar = (u32 *) pci_read_config32(dev,
-					PCI_BASE_ADDRESS_0);
+			bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			*(bar + UOCCTL) |= PADEN_SET;
 			*(bar + UOCCAP) |= APU_SET;
 		}
 	}
 
-	/* Disable virtual PCI UDC and OTG headers */
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-			PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+	/* Disable virtual PCI UDC and OTG headers. */
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
+			      PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 	if (dev) {
 		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
 	}
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
+			      PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
 		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
 	}
 }
 
 /** 
-  * This function is in an odd place. We need to see about moving to it geodelx.c
-  * But for now, let's get things working and put a #warning in. This function 
-  * initializes a lot of nasty bits needed for phase 2. Can this function run
-  * before vsm is set up, or is it required for vsm? The order here is a little hard to 
-  * figure out. 
-  */
+ * This function initializes a lot of nasty bits needed for phase 2.
+ *
+ * Can this function run before vsm is set up, or is it required for vsm?
+ * The order here is a little hard to figure out.
+ *
+ * This function is in an odd place. We need to see about moving it to
+ * geodelx.c. But for now, let's get things working and put a #warning in.
+ */
 void chipsetinit(void)
 {
 	struct device *dev;
-	struct msr  msr;
+	struct msr msr;
 	u32 msrnum;
 	struct southbridge_amd_cs5536_config *sb;
 	struct msrinit *csi;
 
 	post_code(P80_CHIPSET_INIT);
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
-	if (! dev) {
-		printk(BIOS_ERR, "%s: Could not find the south bridge!\n", __FUNCTION__);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
+			      PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+	if (!dev) {
+		printk(BIOS_ERR, "%s: Could not find the south bridge!\n",
+		       __FUNCTION__);
 		return;
 	}
 	sb = (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+
 #if 0
-	   if (! IsS3Resume()) */
+	if (!IsS3Resume())
 	{
 		struct acpiinit *aci = acpi_init_table;
 		for (; aci->ioreg; aci++) {
 			outl(aci->regdata, aci->ioreg);
 			inl(aci->ioreg);
 		}
-
 		pm_chipset_init();
 	}
 #endif
 
-	/* set hd IRQ */
+	/* Set HD IRQ. */
 	outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
 	outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
 
-	/* Allow IO read and writes during a ATA DMA operation.
-	 * This could be done in the HD rom but 
-	 * do it here for easier debugging.
+	/* Allow I/O reads and writes during a ATA DMA operation. This could
+	 * be done in the HD ROM but do it here for easier debugging.
 	 */
 	msrnum = ATA_SB_GLD_MSR_ERR;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0x100;
 	wrmsr(msrnum, msr);
 
-	/*      Enable Post Primary IDE. */
+	/* Enable post primary IDE. */
 	msrnum = GLPCI_SB_CTRL;
 	msr = rdmsr(msrnum);
 	msr.lo |= GLPCI_CRTL_PPIDE_SET;
 	wrmsr(msrnum, msr);
 
 	csi = SB_MASTER_CONF_TABLE;
-	for (; csi->msrnum; csi++) {
+	for (/* Nothing */; csi->msrnum; csi++) {
 		msr.lo = csi->msr.lo;
 		msr.hi = csi->msr.hi;
-		wrmsr(csi->msrnum, msr);	// MSR - see table above
+		wrmsr(csi->msrnum, msr);	/* MSR - see table above */
 	}
 
-	/*      Flash BAR size Setup */
+	/* Flash BAR size setup. */
 	printk(BIOS_ERR, "%sDoing chipset_flash_setup()\n",
-		   sb->enable_ide_nand_flash == 1 ? "" : "Not ");
+	       sb->enable_ide_nand_flash == 1 ? "" : "Not ");
 	if (sb->enable_ide_nand_flash == 1)
 		chipset_flash_setup();
 
-	/* */
-	/*      Set up Hardware Clock Gating */
-	/* */
+	/* Set up hardware clock gating. */
+	/* TODO: Why the extra block here? Can it be removed? */
 	{
 		csi = CS5536_CLOCK_GATING_TABLE;
-		for (; csi->msrnum; csi++) {
+		for (/* Nothing */; csi->msrnum; csi++) {
 			msr.lo = csi->msr.lo;
 			msr.hi = csi->msr.hi;
-			wrmsr(csi->msrnum, msr);	// MSR - see table above
+			wrmsr(csi->msrnum, msr); /* MSR - see table above */
 		}
 	}
 }
 
-/** 
- * Depending on settings in the config struct, enable COM1 or COM2 or both. 
- * If the enable is NOT set, the UARTS are explicitly disabled, which is required 
- * if (e.g.) there is a superio attached that does COM1 or COM2.
-  * @param southbridge config structure 
-  */
+/**
+ * TODO.
+ *
+ * @param dev The device to use.
+ */
 static void southbridge_init(struct device *dev)
 {
 	struct southbridge_amd_cs5536_config *sb =
 	    (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+
 	/*
 	 * struct device *gpiodev;
 	 * unsigned short gpiobase = MDD_GPIO;
 	 */
 
 	printk(BIOS_ERR, "cs5536: %s\n", __FUNCTION__);
+
 	setup_i8259();
 	lpc_init(sb);
 	uarts_init(sb);
 
 	if (sb->enable_gpio_int_route) {
 		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
-			(sb->enable_gpio_int_route & 0xFFFF));
+			 (sb->enable_gpio_int_route & 0xFFFF));
 		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
-			(sb->enable_gpio_int_route >> 16));
+			 (sb->enable_gpio_int_route >> 16));
 	}
 
-	printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__,
-		   sb->enable_ide_nand_flash);
+	printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
+	       __FUNCTION__, sb->enable_ide_nand_flash);
 	if (sb->enable_ide_nand_flash == 1) {
 		enable_ide_nand_flash_header();
 	}
@@ -616,10 +615,10 @@
 
 #warning Add back in unwanted VPCI support
 #if 0
-	/* disable unwanted virtual PCI devices */
+	/* Disable unwanted virtual PCI devices. */
 	for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
 		printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n",
-			     sb->unwanted_vpci[i]);
+		       sb->unwanted_vpci[i]);
 		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
 		outl(0xDEADBEEF, 0xCFC);
 	}
@@ -630,32 +629,35 @@
 {
 	printk(BIOS_ERR, "cs5536: Enter %s: dev is %p\n", __FUNCTION__, dev);
 	printk(BIOS_ERR, "cs5536: Exit %s: dev is %p\n", __FUNCTION__, dev);
-
 }
 
-/** 
-  * A slightly different enable resources than the standard. 
-  * We grab control here as VSA has played in this chip as well. 
-  * @param southbridge config structure 
-  */
+/**
+ * A slightly different enable resources than the standard.
+ * We grab control here as VSA has played in this chip as well.
+ *
+ * @param dev The device to use.
+ */
 static void cs5536_pci_dev_enable_resources(struct device *dev)
 {
+	/* TODO: Shouldn't this be BIOS_SPEW? */
 	printk(BIOS_ERR, "cs5536: %s()\n", __FUNCTION__);
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
 }
 
 static struct device_operations southbridge_ops = {
-	.phase3_scan = scan_static_bus,
-	.phase4_read_resources = pci_dev_read_resources,
-	.phase4_set_resources = pci_dev_set_resources,
-	.phase5_enable_resources = cs5536_pci_dev_enable_resources,
-	.phase6_init = southbridge_init,
+	.phase3_scan			= scan_static_bus,
+	.phase4_read_resources		= pci_dev_read_resources,
+	.phase4_set_resources		= pci_dev_set_resources,
+	.phase5_enable_resources	= cs5536_pci_dev_enable_resources,
+	.phase6_init			= southbridge_init,
 };
 
 struct constructor cs5536_constructors[] = {
-  {.id = {.type = DEVICE_ID_PCI,
-	  .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
-   	.ops = &southbridge_ops},
-  {.ops = 0},
+	{.id = {.type = DEVICE_ID_PCI,
+		.u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+			      .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
+	 .ops = &southbridge_ops},
+
+	{.ops = 0},
 };

Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h	2007-07-10 14:38:01 UTC (rev 442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h	2007-07-10 19:44:22 UTC (rev 443)
@@ -441,7 +441,7 @@
 #define FLASH_IO_128B			0x0000FF80
 #define FLASH_IO_256B			0x0000FF00
 
-/* function prototypes */
+/* Function prototypes */
 void cs5536_setup_extmsr(void);
 void cs5536_setup_idsel(void);
 void cs5536_usb_swapsif(void);
@@ -453,5 +453,4 @@
 void cs5536_setup_onchipuart(void);
 void cs5536_stage1(void);
 
-
-#endif				/* SOUTHBRIDGE_AMD_CS5536_CS5536_H */
+#endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */

Modified: LinuxBIOSv3/southbridge/amd/cs5536/dts
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/dts	2007-07-10 14:38:01 UTC (rev 442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/dts	2007-07-10 19:44:22 UTC (rev 443)
@@ -27,7 +27,7 @@
 	/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
 	lpc_serirq_polarity = "0";
 
-	/* 0:Continuous 1:Quiet */
+	/* 0:continuous 1:quiet */
 	lpc_serirq_mode = "0";
 
 	/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */

Modified: LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c	2007-07-10 14:38:01 UTC (rev 442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c	2007-07-10 19:44:22 UTC (rev 443)
@@ -333,10 +333,10 @@
 /**
  * Read a byte from the SPD. 
  *
- * For this chip, that is really just saying 'read a byte from smbus'.
- * So we use smbus_read_byte. Nota Bene: leave this here as a function 
+ * For this chip, that is really just saying 'read a byte from SMBus'.
+ * So we use smbus_read_byte(). Nota Bene: leave this here as a function 
  * rather than a #define in an obscure location. This function is called 
- * only a few dozen times, and it not performance critical. 
+ * only a few dozen times, and it's not performance critical. 
  *
  * @param device The device.
  * @param address The address.

Modified: LinuxBIOSv3/southbridge/amd/cs5536/stage1.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/stage1.c	2007-07-10 14:38:01 UTC (rev 442)
+++ LinuxBIOSv3/southbridge/amd/cs5536/stage1.c	2007-07-10 19:44:22 UTC (rev 443)
@@ -41,11 +41,12 @@
  */
 void cs5536_setup_extmsr(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	/* Forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM. */
 	msr.hi = msr.lo = 0x00000000;
 
+	/* TODO: unsigned char -> u8? */
 #if CS5536_GLINK_PORT_NUM <= 4
 	msr.lo = CS5536_DEV_NUM <<
 	    (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
@@ -74,7 +75,7 @@
  */
 void cs5536_usb_swapsif(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
 
@@ -97,7 +98,7 @@
  */
 void cs5536_setup_iobase(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	/* Setup LBAR for SMBus controller. */
 	msr.hi = 0x0000f001;
@@ -126,16 +127,17 @@
 }
 
 /**
- * Power Button Setup.
+ * Power button setup.
  *
  * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
- * controls all voltage rails except Vstandby & Vmem. We need to enable,
+ * controls all voltage rails except Vstandby & Vmem. We need to enable
  * OUT_AUX1 and OUTPUT_ENABLE in this order.
  *
  * If GPIO24 is not enabled then soft-off will not work.
  */
 void cs5536_setup_power_button(void)
 {
+	/* TODO: Should be a #define? */
 	outl(0x40020000, PMS_IO_BASE + 0x40);
 	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
 	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
@@ -154,16 +156,12 @@
 	/* Setup GPIO pins 14/15 for SDA/SCL. */
 	val = GPIOL_15_SET | GPIOL_14_SET;
 
-	/* Output Enable */
+	/* Output AUX1 + enable */
 	outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
-
-	/* Output AUX1 */
 	outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
 
-	/* Input Enable */
+	/* Input AUX1 + enable */
 	outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
-
-	/* Input AUX1 */
 	outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
 }
 
@@ -174,21 +172,21 @@
  */
 void cs5536_disable_internal_uart(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	/* The UARTs default to enabled.
 	 * Disable and reset them and configure them later (SIO init).
 	 */
 	msr = rdmsr(MDD_UART1_CONF);
-	msr.lo = 1;		// reset
+	msr.lo = 1;			/* Reset */
 	wrmsr(MDD_UART1_CONF, msr);
-	msr.lo = 0;		// disabled
+	msr.lo = 0;			/* Disable */
 	wrmsr(MDD_UART1_CONF, msr);
 
 	msr = rdmsr(MDD_UART2_CONF);
-	msr.lo = 1;		// reset
+	msr.lo = 1;			/* Reset */
 	wrmsr(MDD_UART2_CONF, msr);
-	msr.lo = 0;		// disabled
+	msr.lo = 0;			/* Disable */
 	wrmsr(MDD_UART2_CONF, msr);
 }
 
@@ -201,7 +199,7 @@
  */
 void cs5536_setup_cis_mode(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	/* Setup CPU interface serial to mode B to match CPU. */
 	msr = rdmsr(GLPCI_SB_CTRL);
@@ -211,16 +209,16 @@
 }
 
 /**
- * Enable the on chip UART.
+ * Enable the on-chip UART.
  *
  * See page 412 of the AMD Geode CS5536 Companion Device data book.
  */
 void cs5536_setup_onchipuart(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	/* Setup early for polling only mode.
-	 * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
+	 * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
 	 *        GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
 	 * 2. Enable UART I/O space in MDD.
 	 *        MSR 0x51400014 bit 18:16
@@ -258,7 +256,7 @@
 /**
  * Board setup.
  *
- * Known to work on the AMD Norwich and DIGITIAL-LOGIC boards.
+ * Known to work on the AMD Norwich and Advanced Digital Logic boards.
  *
  * The extmsr and cis_mode are common for sure. The RSTPLL check is mandatory.
  * IDSEL of course is required, so the chip appears in PCI config space,
@@ -276,7 +274,7 @@
  */
 void cs5536_stage1(void)
 {
-	struct msr  msr;
+	struct msr msr;
 
 	/* Note: you can't do prints in here in most cases, and we don't want
 	 * to hang on serial, so they are commented out.




From uwe at hermann-uwe.de  Tue Jul 10 22:19:36 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 10 Jul 2007 22:19:36 +0200
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Simplify RAM init code a bit
Message-ID: <20070710201936.GD12003@greenwood>

See patch.

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Tue Jul 10 22:26:32 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue, 10 Jul 2007 22:26:32 +0200
Subject: [LinuxBIOS] r444 - LinuxBIOSv3/util
Message-ID: <mailman.510.1355071131.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-10 22:26:32 +0200 (Tue, 10 Jul 2007)
New Revision: 444

Modified:
   LinuxBIOSv3/util/
Log:
Get flashrom into v3, too (via svn:externals).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>




Property changes on: LinuxBIOSv3/util
___________________________________________________________________
Name: svn:externals
   + flashrom svn://linuxbios.org/repos/trunk/util/flashrom





From uwe at hermann-uwe.de  Tue Jul 10 22:27:22 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 10 Jul 2007 22:27:22 +0200
Subject: [LinuxBIOS] Flashrom move into global util/ directory
In-Reply-To: <20070706065837.GA8751@coresystems.de>
References: <20070630190254.GL10622@greenwood>
	<20070701180057.GA24639@skynet.be>
	<20070702233236.GE8232@greenwood>
	<20070705044119.GA5680@coresystems.de>
	<20070705073604.GB5920@greenwood>
	<20070706065837.GA8751@coresystems.de>
Message-ID: <20070710202722.GE12003@greenwood>

On Fri, Jul 06, 2007 at 08:58:37AM +0200, Stefan Reinauer wrote:
> > > There is no copy in v3?
> > 
> > Not yet. Shall we add it?
>  
> Yes, please.
> 
> Acked-by: Stefan Reinauer <stepan at coresystems.de>

Done, r444.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From marc.jones at amd.com  Wed Jul 11 00:29:51 2007
From: marc.jones at amd.com (Marc Jones)
Date: Tue, 10 Jul 2007 16:29:51 -0600
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Simplify RAM init code a bit
In-Reply-To: <20070710201936.GD12003@greenwood>
References: <20070710201936.GD12003@greenwood>
Message-ID: <4694085F.8020307@amd.com>



Uwe Hermann wrote:
> See patch.
> 
> Uwe.
> 
> 
> ------------------------------------------------------------------------
> 
> Simplify the Geode LX RAM init code a bit by using (inline'd) helper
> functions. Untested on real hardware, but it still compiles.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

I can't test it yet either but it builds and looks correct to me. (I'm 
almost into memory init with V3.)

Acked-by: Marc Jones <marc.jones at amd.com>

-- 
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From r.marek at assembler.cz  Wed Jul 11 01:12:27 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 11 Jul 2007 01:12:27 +0200
Subject: [LinuxBIOS] status update - K8T890/VT8237
Message-ID: <4694125B.6030507@assembler.cz>

Hello all,

I just got four words for you: It boots now yeah!

Yes it boots my standard Linux kernel (2.6.22) SATA/IDE/USB/soundcard/gigabiteth 
  and my Radeon seems to work. My MB is Asus A8V-E SE. Which might be compatible 
with A8V-E Duluxe... So someone wants to play too?

However there are some problems left:

1) dualchannel on K8 with unbuffered dimms

Has someone in plan to fix this?

2) something wrong with PCI/RAM resources

LinuxBIOS is telling FILO and FILO tells linux this memmap:

00001000-0009ffff : System RAM
000c0000-000effff : System RAM
00100000-1fffffff : System RAM

But if I use my K8 resource dumper:

MMIO map: #0 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
MMIO map: #1 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
MMIO map: #2 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
MMIO map: #3 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
MMIO map: #4 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
MMIO map: #5 0x00000a0000 - 0x00000cffff Access: R/W     Dstnode:0 DstLink 0
MMIO map: #6 0x00fc000000 - 0x00fc2fffff Access: R/W     Dstnode:0 DstLink 0
MMIO map: #7 0x00e0000000 - 0x00f7ffffff Access: R/W     Dstnode:0 DstLink 0

There is MMIO region up to cffff.

I could not long time  catch this bug - the system hung disk IO when the disk 
buffers hit this region. I thought there is something wrong with V-Link or PCI 
master. But once I spot this I solved it by passing my own memmap to Linux Kernel.

Question is: any idea why this happened? I'm using default resource map and 
reasonably old SVN. This seems to be completely undocumented in K8 code...

Perhaps there is something wrong my my memory resource??

3) ROM strapping of some registers does not work properly

   I will try to solve it.

4) Fine tuning of some VIA registers.

   I will try to solve it.

5) ACPI off, GPIO in SIO, Reset button does not work. PCIe regs tune.


Thanks,
Rudolf





From peter at stuge.se  Wed Jul 11 02:51:46 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 11 Jul 2007 02:51:46 +0200
Subject: [LinuxBIOS] status update - K8T890/VT8237
In-Reply-To: <4694125B.6030507@assembler.cz>
References: <4694125B.6030507@assembler.cz>
Message-ID: <20070711005146.27625.qmail@stuge.se>

On Wed, Jul 11, 2007 at 01:12:27AM +0200, Rudolf Marek wrote:
> I just got four words for you: It boots now yeah!

Great news!


//Peter



From joe at smittys.pointclark.net  Wed Jul 11 10:36:32 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Wed, 11 Jul 2007 04:36:32 -0400
Subject: [LinuxBIOS] DIMM Page Size
Message-ID: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net>

Anyone know what the mathmatical calculation is to determine a Dimms  
"Page Size"?? I found this but it does not seem to work:

Page size = (2^col)*bus_width
where,
col = number of column address lines (SPD byte 4: Number of Column Addresses)
bus_width = number of data(DQ) lines (???SPD byte 13: SDRAM Device Width???)

Thanks - Joe



From gerhard.gappmeier at ascolab.com  Wed Jul 11 10:37:18 2007
From: gerhard.gappmeier at ascolab.com (Gerhard Gappmeier)
Date: Wed, 11 Jul 2007 10:37:18 +0200
Subject: [LinuxBIOS] Acer TravelMate 660
Message-ID: <200707111037.18127.gerhard.gappmeier@ascolab.com>

Hi,

has anyone LinuxBIOS running on an Acer TravelMate 660 laptop?
Or can tell me if it will work?
I'm a LinuxBIOS newbie, but I hope the following information can help.

cat /proc/cpuinfo: 
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 9
model name	: Intel(R) Pentium(R) M processor 1400MHz
stepping	: 5
cpu MHz		: 1400.000
cache size	: 1024 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr mce cx8 sep mtrr pge mca cmov pat clflush dts 
acpi mmx fxsr sse sse2 tm pbe est tm2
bogomips	: 2791.77
clflush size	: 64

lspci -v:
00:00.0 Host bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to 
I/O Controller (rev 02)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, fast devsel, latency 0
	Memory at <unassigned> (32-bit, prefetchable)
	Capabilities: [40] Vendor Specific Information

00:00.1 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV 
Processor to I/O Controller (rev 02)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, fast devsel, latency 0

00:00.3 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV 
Processor to I/O Controller (rev 02)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, fast devsel, latency 0

00:02.0 VGA compatible controller: Intel Corporation 82852/855GM Integrated 
Graphics Device (rev 02) (prog-if 00 [VGA])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, fast devsel, latency 0, IRQ 11
	Memory at e8000000 (32-bit, prefetchable) [size=128M]
	Memory at e0000000 (32-bit, non-prefetchable) [size=512K]
	I/O ports at 1800 [size=8]
	Capabilities: [d0] Power Management version 1

00:02.1 Display controller: Intel Corporation 82852/855GM Integrated Graphics 
Device (rev 02)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, fast devsel, latency 0
	Memory at f0000000 (32-bit, prefetchable) [disabled] [size=128M]
	Memory at e0080000 (32-bit, non-prefetchable) [disabled] [size=512K]
	Capabilities: [d0] Power Management version 1

00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) 
USB UHCI Controller #1 (rev 03) (prog-if 00 [UHCI])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, medium devsel, latency 0, IRQ 11
	I/O ports at 1820 [size=32]

00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) 
USB UHCI Controller #2 (rev 03) (prog-if 00 [UHCI])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, medium devsel, latency 0, IRQ 11
	I/O ports at 1840 [size=32]

00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) 
USB UHCI Controller #3 (rev 03) (prog-if 00 [UHCI])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, medium devsel, latency 0, IRQ 10
	I/O ports at 1860 [size=32]

00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI 
Controller (rev 03) (prog-if 20 [EHCI])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, medium devsel, latency 0, IRQ 10
	Memory at e0100000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2
	Capabilities: [58] Debug port

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev 83) 
(prog-if 00 [Normal decode])
	Flags: bus master, fast devsel, latency 0
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=64
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: e0200000-e07fffff
	Prefetchable memory behind bridge: 30000000-37ffffff

00:1f.0 ISA bridge: Intel Corporation 82801DBM (ICH4-M) LPC Interface Bridge 
(rev 03)
	Flags: bus master, medium devsel, latency 0

00:1f.1 IDE interface: Intel Corporation 82801DBM (ICH4-M) IDE Controller (rev 
03) (prog-if 8a [Master SecP PriP])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, medium devsel, latency 0, IRQ 10
	I/O ports at 01f0 [size=8]
	I/O ports at 03f4 [size=1]
	I/O ports at 0170 [size=8]
	I/O ports at 0374 [size=1]
	I/O ports at 1810 [size=16]
	Memory at 38000000 (32-bit, non-prefetchable) [size=1K]

00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus 
Controller (rev 03)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: medium devsel, IRQ 10
	I/O ports at 1880 [size=32]

00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM 
(ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 03)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, medium devsel, latency 0, IRQ 10
	I/O ports at 1c00 [size=256]
	I/O ports at 18c0 [size=64]
	Memory at e0100c00 (32-bit, non-prefetchable) [size=512]
	Memory at e0100800 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2

00:1f.6 Modem: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 
Modem Controller (rev 03) (prog-if 00 [Generic])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: medium devsel, IRQ 10
	I/O ports at 2400 [size=256]
	I/O ports at 2000 [size=128]
	Capabilities: [50] Power Management version 2

02:02.0 Ethernet controller: Broadcom Corporation BCM4401 100Base-T (rev 01)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, fast devsel, latency 64, IRQ 11
	Memory at e0204000 (32-bit, non-prefetchable) [size=8K]
	Capabilities: [40] Power Management version 2

02:04.0 Network controller: Intel Corporation PRO/Wireless LAN 2100 3B Mini 
PCI Adapter (rev 04)
	Subsystem: Intel Corporation MIM2000/Centrino
	Flags: bus master, medium devsel, latency 64, IRQ 11
	Memory at e0206000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [dc] Power Management version 2

02:06.0 CardBus bridge: O2 Micro, Inc. OZ711EC1 SmartCardBus Controller (rev 
20)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, stepping, slow devsel, latency 64, IRQ 10
	Memory at e0207000 (32-bit, non-prefetchable) [size=4K]
	Bus: primary=02, secondary=03, subordinate=06, sec-latency=176
	Memory window 0: 30000000-33fff000 (prefetchable)
	Memory window 1: 3c000000-3ffff000 (prefetchable)
	I/O window 0: 00003000-000030ff
	I/O window 1: 00003400-000034ff
	16-bit legacy interface ports at 0001

02:06.1 CardBus bridge: O2 Micro, Inc. OZ711EC1 SmartCardBus Controller (rev 
20)
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, slow devsel, latency 64, IRQ 10
	Memory at e0208000 (32-bit, non-prefetchable) [size=4K]
	Bus: primary=02, secondary=07, subordinate=0a, sec-latency=176
	Memory window 0: 34000000-37fff000 (prefetchable)
	Memory window 1: 40000000-43fff000
	I/O window 0: 00003800-000038ff
	I/O window 1: 00003c00-00003cff
	16-bit legacy interface ports at 0001

02:07.0 FireWire (IEEE 1394): Texas Instruments TSB43AB21 IEEE-1394a-2000 
Controller (PHY/Link) (prog-if 10 [OHCI])
	Subsystem: Acer Incorporated [ALI] Unknown device 0035
	Flags: bus master, medium devsel, latency 64, IRQ 10
	Memory at e0209000 (32-bit, non-prefetchable) [size=2K]
	Memory at e0200000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: [44] Power Management version 2


BIOS: Phoenix
VGA-BIOS: Montara-GM 2965 (displayed in the info section of Phoenix BIOS, I 
don't know if this is important)

The display has a special resoltion of 1400x1050 and there is a known problem 
of the BIOS to not support this resolution. So I have to use the 
i915resolution tool on linux to be able to use this resolution.

Can LinuxBIOS initialize the VGA controller?
Or can the original VGA BIOS be used in any way for that?
I have seen something mentioned in other artices.

On the Acer site there is also a flash tool available. But only for windows. 
(WinPhlash). Maybe this can help if the LinuxBIOS flash tool doesn't work.
http://support.acer-euro.com/drivers/notebook/tm_660.html

I understand why initialization of chipset, pci bus, etc is important.
Otherwise the OS could not be started.
But how important is the initialization of other peripherie like modems, USB 
controller, VGA, etc.?
Isn't this done by the OS driver anyway after LinuxBIOS has started the 
kernel?

regards,
Gerhard.



From corey.osgood at gmail.com  Wed Jul 11 11:13:00 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 11 Jul 2007 05:13:00 -0400
Subject: [LinuxBIOS] Does MA map type effect MRS values?
Message-ID: <46949F1C.7020204@gmail.com>

Simple question that I can't seem to find the answer to _anywhere_. From
JEDEC's docs, it sounds like it should, but I can't figure out what the
relationship is. Any info would be greatly appreciated ;)

-Corey



From tiansm at lemote.com  Wed Jul 11 11:36:21 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Wed, 11 Jul 2007 17:36:21 +0800
Subject: [LinuxBIOS] about cs5536 interrupt ack
Message-ID: <4694A495.1050006@lemote.com>

Hi,
    I am trying to use a mips cpu the cs5536. I have some problem with 
the 8259 of cs5536.  The  databook said,

"Control Logic
The INT output goes directly to the CPU interrupt input.
When an INT signal is activated, the CPU responds with an
Interrupt Acknowledge access that is translated to two
pulses on the INTA input of the PIC. At the first INTA pulse,
the highest priority IRR bit is loaded into the corresponding
ISR bit, and that IRR bit is reset. The second INTA pulse
instructs the PIC to present the 8-bit vector of the interrupt
handler onto the data bus."

Is it the responsibility of north bridge to reponse to intr with a PCI 
Interrupt Ack cycle?
it's a problem that my northbridge didn't implement that! Fortunately we 
use a fpga as a northbridge.

it seem it's no way to fix this by software, for OCW3 didn't implemnt 
Poll command:(

so I guess the the process is:
1) 8259 receive a int, a bit irr got set.
2) 8259 assert intr.
3) northbrige generate a int ack cycle.
4) cs5536 translate the ack into two INTA pulse, and the reponse 
northbridge with a interrupt vector.
5) then my program can get the vector from northbridge?

Is that right?

Without int ack, generic linux-mips 8259 code can't work.

Greetings,
Tian






From corey.osgood at gmail.com  Wed Jul 11 12:23:24 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 11 Jul 2007 06:23:24 -0400
Subject: [LinuxBIOS] Acer TravelMate 660
In-Reply-To: <200707111037.18127.gerhard.gappmeier@ascolab.com>
References: <200707111037.18127.gerhard.gappmeier@ascolab.com>
Message-ID: <4694AF9C.9090608@gmail.com>

Gerhard Gappmeier wrote:
> Hi,
>
> has anyone LinuxBIOS running on an Acer TravelMate 660 laptop?
> Or can tell me if it will work?
> I'm a LinuxBIOS newbie, but I hope the following information can help.

LinuxBIOS on laptops is a mess that we're only beginning to jump into.
Laptops have an embedded controller, sometimes referred to as an EC,
that can control everything from power to LCD control, etc, etc. The
docs on these are usually covered by an NDA, with one real exception:
the part used by OLPC's XO. See also http://www.linuxbios.org/Laptop

As for the rest of your hardware, I think some work was being done on
the i855, but I don't know what the outcome of it was. The i82801dbm
should work, either through the regular or generic implementation. You
haven't listed the Super IO, so I can't tell if that would work or not,
but there's a list of supported hardware on the LinuxBIOS wiki. The rest
of the hardware can be dealt with later, although in a perfect world it
should Just Work.

-Corey



From gerhard.gappmeier at ascolab.com  Wed Jul 11 13:23:28 2007
From: gerhard.gappmeier at ascolab.com (Gerhard Gappmeier)
Date: Wed, 11 Jul 2007 13:23:28 +0200
Subject: [LinuxBIOS] Acer TravelMate 660
In-Reply-To: <4694AF9C.9090608@gmail.com>
References: <200707111037.18127.gerhard.gappmeier@ascolab.com>
	<4694AF9C.9090608@gmail.com>
Message-ID: <4694BDB0.3030309@ascolab.com>

Thanks for the info.
> LinuxBIOS on laptops is a mess that we're only beginning to jump into.
> Laptops have an embedded controller, sometimes referred to as an EC,
> that can control everything from power to LCD control, etc, etc. The
> docs on these are usually covered by an NDA, with one real exception:
> the part used by OLPC's XO. See also http://www.linuxbios.org/Laptop
>   
Sounds not ver optimistic for me.
> As for the rest of your hardware, I think some work was being done on
> the i855, but I don't know what the outcome of it was. The i82801dbm
> should work, either through the regular or generic implementation. You
> haven't listed the Super IO, so I can't tell if that would work or not,
>   
Actually I don't know what this Super IO is and where I can get this
information from.
Is there a tool like lspci available, or do I need to open my laptop?
> but there's a list of supported hardware on the LinuxBIOS wiki. The rest
> of the hardware can be dealt with later, although in a perfect world it
> should Just Work.
>
> -Corey
>
>   
Gerhard.



From segher at kernel.crashing.org  Wed Jul 11 13:48:32 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Wed, 11 Jul 2007 13:48:32 +0200
Subject: [LinuxBIOS] DIMM Page Size
In-Reply-To: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net>
References: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net>
Message-ID: <4E7A3EDF-B1C5-4C51-A9FB-495F0B4CFDC4@kernel.crashing.org>

> Anyone know what the mathmatical calculation is to determine a Dimms
> "Page Size"?? I found this but it does not seem to work:
>
> Page size = (2^col)*bus_width
> where,
> col = number of column address lines (SPD byte 4: Number of Column  
> Addresses)
> bus_width = number of data(DQ) lines (???SPD byte 13: SDRAM Device  
> Width???)

"device width" is the number of data lines per DRAM chip on
your DIMM.  This isn't the same as the number of data lines
on the DIMM itself; that is 64 usually (not counting the ECC
bits).  This info is in the SPD as well.


Segher




From segher at kernel.crashing.org  Wed Jul 11 14:06:52 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Wed, 11 Jul 2007 14:06:52 +0200
Subject: [LinuxBIOS] Does MA map type effect MRS values?
In-Reply-To: <46949F1C.7020204@gmail.com>
References: <46949F1C.7020204@gmail.com>
Message-ID: <2EEB4E92-C563-4858-A50A-164F1A636074@kernel.crashing.org>

> Simple question that I can't seem to find the answer to _anywhere_.  
> From
> JEDEC's docs, it sounds like it should, but I can't figure out what  
> the
> relationship is. Any info would be greatly appreciated ;)

What is "MA map type"?  Are you talking about DDR1, DDR2,
DDR3, some GDDR, or what else, anyway?  :-)


Segher




From corey.osgood at gmail.com  Wed Jul 11 14:16:48 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 11 Jul 2007 08:16:48 -0400
Subject: [LinuxBIOS] Does MA map type effect MRS values?
In-Reply-To: <2EEB4E92-C563-4858-A50A-164F1A636074@kernel.crashing.org>
References: <46949F1C.7020204@gmail.com>
	<2EEB4E92-C563-4858-A50A-164F1A636074@kernel.crashing.org>
Message-ID: <4694CA30.30001@gmail.com>

Segher Boessenkool wrote:
>> Simple question that I can't seem to find the answer to _anywhere_. From
>> JEDEC's docs, it sounds like it should, but I can't figure out what the
>> relationship is. Any info would be greatly appreciated ;)
>
> What is "MA map type"?  Are you talking about DDR1, DDR2,
> DDR3, some GDDR, or what else, anyway?  :-)
>
>
> Segher

Sorry, Memory Address map type, in relation to the via cn700 (or any via
northbridge) and ddr2 ram. And the answer appears to be that it doesn't,
since the system is now working with either of two different MA map type
settings (yay!).

-Corey



From lemenkov at gmail.com  Wed Jul 11 15:21:12 2007
From: lemenkov at gmail.com (Peter Lemenkov)
Date: Wed, 11 Jul 2007 17:21:12 +0400
Subject: [LinuxBIOS] Does my MoBo supported?
Message-ID: <adf480660707110621l20783bf8v67e7d652defde993@mail.gmail.com>

Hello All!
I've got a small number of motherboards on which I would like to
install LinuxBIOS instead of proprietary BLOBs.

One of that cars identified as Gigabyte 7VT880-RZ (based on VIA KT880 + VT8237R)

Here is output from lspci and dmidecode respectively:

http://lemenkov.googlepages.com/lspci.txt
http://lemenkov.googlepages.com/dmidecode.txt

Can I do something with this M/b? I don't mean bulking it, actually :)
-- 
With best regards!



From joe at smittys.pointclark.net  Wed Jul 11 15:41:00 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Wed, 11 Jul 2007 09:41:00 -0400
Subject: [LinuxBIOS] DIMM Page Size
In-Reply-To: <4E7A3EDF-B1C5-4C51-A9FB-495F0B4CFDC4@kernel.crashing.org>
References: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net>
	<4E7A3EDF-B1C5-4C51-A9FB-495F0B4CFDC4@kernel.crashing.org>
Message-ID: <20070711094100.pt4t4pyrfac0og8s@www.smittys.pointclark.net>

Quoting Segher Boessenkool <segher at kernel.crashing.org>:

>> Anyone know what the mathmatical calculation is to determine a Dimms
>> "Page Size"?? I found this but it does not seem to work:
>>
>> Page size = (2^col)*bus_width
>> where,
>> col = number of column address lines (SPD byte 4: Number of Column   
>> Addresses)
>> bus_width = number of data(DQ) lines (???SPD byte 13: SDRAM Device Width???)
>
> "device width" is the number of data lines per DRAM chip on
> your DIMM.  This isn't the same as the number of data lines
> on the DIMM itself; that is 64 usually (not counting the ECC
> bits).  This info is in the SPD as well.
>
>
> Segher

Ok, so that must be byte 6: Data Width of Assembly.
It still does not seem to compute though.

col = 9 /* SPD byte 4: Number of Column Addresses */
bus_width = 64 /* SPD byte 6: Data Width of Assembly */

page_size = (2^col)*bus_width

5184 = 81 * 64

Which is not correct because the DIMM has a 4k page size.
(According to it's datasheet).

Please Help.

Thanks - Joe



From myles at pel.cs.byu.edu  Wed Jul 11 16:50:22 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 11 Jul 2007 08:50:22 -0600
Subject: [LinuxBIOS] DIMM Page Size
In-Reply-To: <20070711094100.pt4t4pyrfac0og8s@www.smittys.pointclark.net>
References: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net><4E7A3EDF-B1C5-4C51-A9FB-495F0B4CFDC4@kernel.crashing.org>
	<20070711094100.pt4t4pyrfac0og8s@www.smittys.pointclark.net>
Message-ID: <030001c7c3ca$cef0b4c0$184e040a@chimp>



> Quoting Segher Boessenkool <segher at kernel.crashing.org>:
> 
> >> Anyone know what the mathmatical calculation is to determine a Dimms
> >> "Page Size"?? I found this but it does not seem to work:
> >>
> >> Page size = (2^col)*bus_width
> >> where,
> >> col = number of column address lines (SPD byte 4: Number of Column
> >> Addresses)
> >> bus_width = number of data(DQ) lines (???SPD byte 13: SDRAM Device
> Width???)
> >
> > "device width" is the number of data lines per DRAM chip on
> > your DIMM.  This isn't the same as the number of data lines
> > on the DIMM itself; that is 64 usually (not counting the ECC
> > bits).  This info is in the SPD as well.
> >
> >
> > Segher
> 
> Ok, so that must be byte 6: Data Width of Assembly.
> It still does not seem to compute though.
> 
> col = 9 /* SPD byte 4: Number of Column Addresses */
> bus_width = 64 /* SPD byte 6: Data Width of Assembly */
> 
> page_size = (2^col)*bus_width

2^9 = 512

> 5184 = 81 * 64

512 * 64 = 32K

Myles 

> 
> Which is not correct because the DIMM has a 4k page size.
> (According to it's datasheet).
> 
> Please Help.
> 





From myles at pel.cs.byu.edu  Wed Jul 11 16:54:54 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 11 Jul 2007 08:54:54 -0600
Subject: [LinuxBIOS] DIMM Page Size
In-Reply-To: <030001c7c3ca$cef0b4c0$184e040a@chimp>
References: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net><4E7A3EDF-B1C5-4C51-A9FB-495F0B4CFDC4@kernel.crashing.org><20070711094100.pt4t4pyrfac0og8s@www.smittys.pointclark.net>
	<030001c7c3ca$cef0b4c0$184e040a@chimp>
Message-ID: <030101c7c3cb$714dccd0$184e040a@chimp>



> > col = 9 /* SPD byte 4: Number of Column Addresses */
> > bus_width = 64 /* SPD byte 6: Data Width of Assembly */
> >
> > page_size = (2^col)*bus_width
> 
> 2^9 = 512
> 
> > 5184 = 81 * 64
> 
> 512 * 64 = 32K
> 
> Myles

Sorry, that should have been 32K bits, since you are multiplying by 64 bits.
Then dividing by 8 bits/byte = 4 KB.

Myles

> 
> >
> > Which is not correct because the DIMM has a 4k page size.
> > (According to it's datasheet).





From svn at openbios.org  Wed Jul 11 16:58:58 2007
From: svn at openbios.org (LinuxBIOS)
Date: Wed, 11 Jul 2007 14:58:58 -0000
Subject: [LinuxBIOS] #79: grub2 loads and executes as payload of the
 Qemu target
In-Reply-To: <044.a6b58101ab47e4cd7f414f91b1c794be@openbios.org>
References: <044.a6b58101ab47e4cd7f414f91b1c794be@openbios.org>
Message-ID: <053.c121a9eb769a2df5d038ca4ed92a94af@openbios.org>

#79: grub2 loads and executes as payload of the Qemu target
----------------------------+-----------------------------------------------
    Reporter:  oxygene      |         Owner:  oxygene                
        Type:  enhancement  |        Status:  assigned               
    Priority:  major        |     Milestone:  Port GRUB2 to LinuxBIOS
   Component:  code         |       Version:  v3                     
  Resolution:               |      Keywords:                         
Dependencies:               |   Patchstatus:  patch needs work       
----------------------------+-----------------------------------------------
Changes (by oxygene):

  * status:  new => assigned
  * patchstatus:  there is no patch => patch needs work
  * type:  defect => enhancement

Comment:

 patch-20070711-1-lbgrub2-draft provides a basic vgatext output and ps/2
 keyboard input driver. it also provides the makefiles and grub-mkimage
 variant to generate a build suitable as payload to LinuxBIOSv3

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/79#comment:1>
LinuxBIOS <http://www.linuxbios.org/>

From tiansm at lemote.com  Wed Jul 11 17:19:07 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Wed, 11 Jul 2007 23:19:07 +0800
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
References: <4694A495.1050006@lemote.com>
	<Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
Message-ID: <4694F4EB.8040000@lemote.com>

Before I post the mail, I think you will reply, and haha you did:), 
Thanks that.

Maciej W. Rozycki wrote:
> On Wed, 11 Jul 2007, Songmao Tian wrote:
>
>   
>> "Control Logic
>> The INT output goes directly to the CPU interrupt input.
>> When an INT signal is activated, the CPU responds with an
>> Interrupt Acknowledge access that is translated to two
>> pulses on the INTA input of the PIC. At the first INTA pulse,
>> the highest priority IRR bit is loaded into the corresponding
>> ISR bit, and that IRR bit is reset. The second INTA pulse
>> instructs the PIC to present the 8-bit vector of the interrupt
>> handler onto the data bus."
>>
>> Is it the responsibility of north bridge to reponse to intr with a PCI
>> Interrupt Ack cycle?
>>     
>
>  With an i386 system such a pair of INTA cycles would be generated by the 
> CPU itself and translated by the north bridge to a PCI Interrupt 
> Acknowledge cycle (see the PCI spec for a more elaborate description).
>
>  If the CPU does not generate INTA cycles, it is a common practice to let 
> it ask the north bridge for a PCI Interrupt Acknowledge in some other way, 
> typically by issuing a read cycle that returns the vector reported by the 
> interrupt controller.
>
>   
>> it's a problem that my northbridge didn't implement that! Fortunately we use a
>> fpga as a northbridge.
>>
>> it seem it's no way to fix this by software, for OCW3 didn't implemnt Poll
>> command:(
>>     
>
>  Huh?  Have you managed to find an 8259A clone *that* broken?  So what 
> does it return if you write 0xc to the address 0x20 in the I/O port space 
> and then read back from that location?  You should complain to the 
>   

It's the value of IRR, so guess IRR. AMD has well documented cs5536, I 
appreciate that.

> manufacturer -- they may be able to fix the problem in a later revision.
>
>  BTW, I have just found a bug (OK, a misfeature, perhaps) in 
> include/asm-mips/i8259.h. ;-)  I'll cook a patch.
>
>   
>> so I guess the the process is:
>> 1) 8259 receive a int, a bit irr got set.
>> 2) 8259 assert intr.
>> 3) northbrige generate a int ack cycle.
>> 4) cs5536 translate the ack into two INTA pulse, and the reponse northbridge
>> with a interrupt vector.
>> 5) then my program can get the vector from northbridge?
>>
>> Is that right?
>>     
>
>  More or less -- 3-5 should probably be the outcome of a single read 
> transaction from the north bridge.  I.e. you issue a read to a "magic" 
> location, 3-5 happen, and the data value returned is the vector presented 
> by the interrupt controller on the PCI bus.
>   
yeah, we can implement a register in north bridge.
>   
>> Without int ack, generic linux-mips 8259 code can't work.
>>     
>
>  You can still dispatch interrupts manually by examining the IRR register, 
> but having a way to ask the 8259A's prioritiser would be nice.  Although 
> given such a lethal erratum you report I would not count on the 
> prioritiser to provide any useful flexibility...
>   
yeah, that's a straight thought, tried but failed:(, patch followed.

>   Maciej
>
>
>   
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
index e88a016..38628af 100644
--- a/include/asm-mips/i8259.h
+++ b/include/asm-mips/i8259.h
@@ -42,6 +42,37 @@ extern void enable_8259A_irq(unsigned int irq);
 extern void disable_8259A_irq(unsigned int irq);
 
 extern void init_i8259_irqs(void);
+#define CONFIG_NO_INTERRUPT_ACK
+#ifdef CONFIG_NO_INTERRUPT_ACK
+static inline int _byte_ffs(u8 word)
+{
+    int num = 0;
+    if ((word & 0xf) == 0) {
+        num += 4;
+        word >>= 4;
+    }
+    if ((word & 0x3) == 0) {
+        num += 2;
+        word >>= 2;
+    }
+    if ((word & 0x1) == 0)
+        num += 1;
+    return num;
+}
+
+static inline int read_irq(int port)
+{
+    outb(0x0A, port);
+    return _byte_ffs(inb(port));
+}
+#else
+static inline int read_irq(int port)
+{
+    /* Perform an interrupt acknowledge cycle on controller 1. */
+    outb(0x0C, port);        /* prepare for poll */
+    return inb(port) & 7;
+}
+#endif
 
 /*
  * Do the traditional i8259 interrupt polling thing.  This is for the few
@@ -54,18 +85,16 @@ static inline int i8259_irq(void)
 
     spin_lock(&i8259A_lock);
 
-    /* Perform an interrupt acknowledge cycle on controller 1. */
-    outb(0x0C, PIC_MASTER_CMD);        /* prepare for poll */
-    irq = inb(PIC_MASTER_CMD) & 7;
+    irq = read_irq(PIC_MASTER_CMD);
+
     if (irq == PIC_CASCADE_IR) {
         /*
          * Interrupt is cascaded so perform interrupt
          * acknowledge on controller 2.
          */
-        outb(0x0C, PIC_SLAVE_CMD);        /* prepare for poll */
-        irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
-    }
-
+        irq = read_irq(PIC_SLAVE_CMD) + 8;
+    }
+#ifndef CONFIG_NO_INTERRUPT_ACK
     if (unlikely(irq == 7)) {
         /*
          * This may be a spurious interrupt.
@@ -78,7 +107,7 @@ static inline int i8259_irq(void)
         if(~inb(PIC_MASTER_ISR) & 0x80)
             irq = -1;
     }
-
+#endif
     spin_unlock(&i8259A_lock);
 
     return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;



From tiansm at lemote.com  Wed Jul 11 17:35:46 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Wed, 11 Jul 2007 23:35:46 +0800
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <4694F7CD.8040606@ru.mvista.com>
References: <4694A495.1050006@lemote.com> <4694F5B8.50009@ru.mvista.com>
	<4694F7CD.8040606@ru.mvista.com>
Message-ID: <4694F8D2.3010404@lemote.com>

Sergei Shtylyov wrote:
> Hello, I wrote:
>
>>> it's a problem that my northbridge didn't implement that! 
>>> Fortunately we use a fpga as a northbridge.
>
>>    Wait, CS5536 is a nortbridge itself!
>
>    Apparently, it's only a south bridge. I must've mixed it with Geode 
> itself.
>
> WBR, Sergei
>
>

that's fine:)



From tiansm at lemote.com  Wed Jul 11 17:38:40 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Wed, 11 Jul 2007 23:38:40 +0800
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <4694F4EB.8040000@lemote.com>
References: <4694A495.1050006@lemote.com>
	<Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
	<4694F4EB.8040000@lemote.com>
Message-ID: <4694F980.6060500@lemote.com>

Songmao Tian wrote:
> Before I post the mail, I think you will reply, and haha you did:), 
> Thanks that.
>
> Maciej W. Rozycki wrote:
>> On Wed, 11 Jul 2007, Songmao Tian wrote:
>>
>>  
>>> "Control Logic
>>> The INT output goes directly to the CPU interrupt input.
>>> When an INT signal is activated, the CPU responds with an
>>> Interrupt Acknowledge access that is translated to two
>>> pulses on the INTA input of the PIC. At the first INTA pulse,
>>> the highest priority IRR bit is loaded into the corresponding
>>> ISR bit, and that IRR bit is reset. The second INTA pulse
>>> instructs the PIC to present the 8-bit vector of the interrupt
>>> handler onto the data bus."
>>>
>>> Is it the responsibility of north bridge to reponse to intr with a PCI
>>> Interrupt Ack cycle?
>>>     
>>
>>  With an i386 system such a pair of INTA cycles would be generated by 
>> the CPU itself and translated by the north bridge to a PCI Interrupt 
>> Acknowledge cycle (see the PCI spec for a more elaborate description).
>>
>>  If the CPU does not generate INTA cycles, it is a common practice to 
>> let it ask the north bridge for a PCI Interrupt Acknowledge in some 
>> other way, typically by issuing a read cycle that returns the vector 
>> reported by the interrupt controller.
>>
>>  
>>> it's a problem that my northbridge didn't implement that! 
>>> Fortunately we use a
>>> fpga as a northbridge.
>>>
>>> it seem it's no way to fix this by software, for OCW3 didn't 
>>> implemnt Poll
>>> command:(
>>>     
>>
>>  Huh?  Have you managed to find an 8259A clone *that* broken?  So 
>> what does it return if you write 0xc to the address 0x20 in the I/O 
>> port space and then read back from that location?  You should 
>> complain to the   
>
> It's the value of IRR, so guess IRR. AMD has well documented cs5536, I 
> appreciate that.
>
>> manufacturer -- they may be able to fix the problem in a later revision.
>>
>>  BTW, I have just found a bug (OK, a misfeature, perhaps) in 
>> include/asm-mips/i8259.h. ;-)  I'll cook a patch.
>>
>>  
>>> so I guess the the process is:
>>> 1) 8259 receive a int, a bit irr got set.
>>> 2) 8259 assert intr.
>>> 3) northbrige generate a int ack cycle.
>>> 4) cs5536 translate the ack into two INTA pulse, and the reponse 
>>> northbridge
>>> with a interrupt vector.
>>> 5) then my program can get the vector from northbridge?
>>>
>>> Is that right?
>>>     
>>
>>  More or less -- 3-5 should probably be the outcome of a single read 
>> transaction from the north bridge.  I.e. you issue a read to a 
>> "magic" location, 3-5 happen, and the data value returned is the 
>> vector presented by the interrupt controller on the PCI bus.
>>   
> yeah, we can implement a register in north bridge.
>>  
>>> Without int ack, generic linux-mips 8259 code can't work.
>>>     
>>
>>  You can still dispatch interrupts manually by examining the IRR 
>> register, but having a way to ask the 8259A's prioritiser would be 
>> nice.  Although given such a lethal erratum you report I would not 
>> count on the prioritiser to provide any useful flexibility...
>>   
> yeah, that's a straight thought, tried but failed:(, patch followed.
>
>>   Maciej
>>
>>
>>   
> diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
> index e88a016..38628af 100644
> --- a/include/asm-mips/i8259.h
> +++ b/include/asm-mips/i8259.h
> @@ -42,6 +42,37 @@ extern void enable_8259A_irq(unsigned int irq);
> extern void disable_8259A_irq(unsigned int irq);
>
> extern void init_i8259_irqs(void);
> +#define CONFIG_NO_INTERRUPT_ACK
> +#ifdef CONFIG_NO_INTERRUPT_ACK
> +static inline int _byte_ffs(u8 word)
> +{
> +    int num = 0;
> +    if ((word & 0xf) == 0) {
> +        num += 4;
> +        word >>= 4;
> +    }
> +    if ((word & 0x3) == 0) {
> +        num += 2;
> +        word >>= 2;
> +    }
> +    if ((word & 0x1) == 0)
> +        num += 1;
> +    return num;
> +}
> +
> +static inline int read_irq(int port)
> +{
> +    outb(0x0A, port);
> +    return _byte_ffs(inb(port));
> +}
> +#else
> +static inline int read_irq(int port)
> +{
> +    /* Perform an interrupt acknowledge cycle on controller 1. */
> +    outb(0x0C, port);        /* prepare for poll */
> +    return inb(port) & 7;
> +}
> +#endif
>
> /*
>  * Do the traditional i8259 interrupt polling thing.  This is for the few
> @@ -54,18 +85,16 @@ static inline int i8259_irq(void)
>
>     spin_lock(&i8259A_lock);
>
> -    /* Perform an interrupt acknowledge cycle on controller 1. */
> -    outb(0x0C, PIC_MASTER_CMD);        /* prepare for poll */
> -    irq = inb(PIC_MASTER_CMD) & 7;
> +    irq = read_irq(PIC_MASTER_CMD);
> +
>     if (irq == PIC_CASCADE_IR) {
>         /*
>          * Interrupt is cascaded so perform interrupt
>          * acknowledge on controller 2.
>          */
> -        outb(0x0C, PIC_SLAVE_CMD);        /* prepare for poll */
> -        irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
> -    }
> -
> +        irq = read_irq(PIC_SLAVE_CMD) + 8;
> +    }
> +#ifndef CONFIG_NO_INTERRUPT_ACK
>     if (unlikely(irq == 7)) {
>         /*
>          * This may be a spurious interrupt.
> @@ -78,7 +107,7 @@ static inline int i8259_irq(void)
>         if(~inb(PIC_MASTER_ISR) & 0x80)
>             irq = -1;
>     }
> -
> +#endif
>     spin_unlock(&i8259A_lock);
>
>     return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
>
>
>
after applying this patch, system hung when probing ide, seems reading 
harddisk continuously, since the led is on all the time.



From macro at linux-mips.org  Wed Jul 11 15:24:41 2007
From: macro at linux-mips.org (Maciej W. Rozycki)
Date: Wed, 11 Jul 2007 14:24:41 +0100 (BST)
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <4694A495.1050006@lemote.com>
References: <4694A495.1050006@lemote.com>
Message-ID: <Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>

On Wed, 11 Jul 2007, Songmao Tian wrote:

> "Control Logic
> The INT output goes directly to the CPU interrupt input.
> When an INT signal is activated, the CPU responds with an
> Interrupt Acknowledge access that is translated to two
> pulses on the INTA input of the PIC. At the first INTA pulse,
> the highest priority IRR bit is loaded into the corresponding
> ISR bit, and that IRR bit is reset. The second INTA pulse
> instructs the PIC to present the 8-bit vector of the interrupt
> handler onto the data bus."
> 
> Is it the responsibility of north bridge to reponse to intr with a PCI
> Interrupt Ack cycle?

 With an i386 system such a pair of INTA cycles would be generated by the 
CPU itself and translated by the north bridge to a PCI Interrupt 
Acknowledge cycle (see the PCI spec for a more elaborate description).

 If the CPU does not generate INTA cycles, it is a common practice to let 
it ask the north bridge for a PCI Interrupt Acknowledge in some other way, 
typically by issuing a read cycle that returns the vector reported by the 
interrupt controller.

> it's a problem that my northbridge didn't implement that! Fortunately we use a
> fpga as a northbridge.
> 
> it seem it's no way to fix this by software, for OCW3 didn't implemnt Poll
> command:(

 Huh?  Have you managed to find an 8259A clone *that* broken?  So what 
does it return if you write 0xc to the address 0x20 in the I/O port space 
and then read back from that location?  You should complain to the 
manufacturer -- they may be able to fix the problem in a later revision.

 BTW, I have just found a bug (OK, a misfeature, perhaps) in 
include/asm-mips/i8259.h. ;-)  I'll cook a patch.

> so I guess the the process is:
> 1) 8259 receive a int, a bit irr got set.
> 2) 8259 assert intr.
> 3) northbrige generate a int ack cycle.
> 4) cs5536 translate the ack into two INTA pulse, and the reponse northbridge
> with a interrupt vector.
> 5) then my program can get the vector from northbridge?
> 
> Is that right?

 More or less -- 3-5 should probably be the outcome of a single read 
transaction from the north bridge.  I.e. you issue a read to a "magic" 
location, 3-5 happen, and the data value returned is the vector presented 
by the interrupt controller on the PCI bus.

> Without int ack, generic linux-mips 8259 code can't work.

 You can still dispatch interrupts manually by examining the IRR register, 
but having a way to ask the 8259A's prioritiser would be nice.  Although 
given such a lethal erratum you report I would not count on the 
prioritiser to provide any useful flexibility...

  Maciej



From sshtylyov at ru.mvista.com  Wed Jul 11 17:22:32 2007
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Wed, 11 Jul 2007 19:22:32 +0400
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <4694A495.1050006@lemote.com>
References: <4694A495.1050006@lemote.com>
Message-ID: <4694F5B8.50009@ru.mvista.com>

Songmao Tian wrote:
> Hi,

>    I am trying to use a mips cpu the cs5536. I have some problem with 
> the 8259 of cs5536.  The  databook said,

    Which databook?

> "Control Logic
> The INT output goes directly to the CPU interrupt input.
> When an INT signal is activated, the CPU responds with an
> Interrupt Acknowledge access that is translated to two
> pulses on the INTA input of the PIC. At the first INTA pulse,
> the highest priority IRR bit is loaded into the corresponding
> ISR bit, and that IRR bit is reset. The second INTA pulse
> instructs the PIC to present the 8-bit vector of the interrupt
> handler onto the data bus."

> Is it the responsibility of north bridge to reponse to intr with a PCI 
> Interrupt Ack cycle?



> it's a problem that my northbridge didn't implement that! Fortunately we 
> use a fpga as a northbridge.

    Wait, CS5536 is a nortbridge itself!

> it seem it's no way to fix this by software, for OCW3 didn't implemnt 
> Poll command:(

    Quite a few 8259 clones don't.

> so I guess the the process is:
> 1) 8259 receive a int, a bit irr got set.
> 2) 8259 assert intr.
> 3) northbrige generate a int ack cycle.

    To what, PCI?

> 4) cs5536 translate the ack into two INTA pulse, and the reponse 

    Nonsense. It would only make sense to translate INTA cycles from CPU bus 
to the PCI bus, not the other way around.

> northbridge with a interrupt vector.

    As I said, CS5536 is northbridge in itself.

> 5) then my program can get the vector from northbridge?

    It's CPU that gets the vector, your program could only do this using poll 
comand which as

> Is that right?

    No.

> Without int ack, generic linux-mips 8259 code can't work.

   I'm compleetly lost here -- what does CS5536 has to do with MIPS?

> Greetings,
> Tian

WBR, Sergei



From sshtylyov at ru.mvista.com  Wed Jul 11 17:31:25 2007
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Wed, 11 Jul 2007 19:31:25 +0400
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <4694F5B8.50009@ru.mvista.com>
References: <4694A495.1050006@lemote.com> <4694F5B8.50009@ru.mvista.com>
Message-ID: <4694F7CD.8040606@ru.mvista.com>

Hello, I wrote:

>> it's a problem that my northbridge didn't implement that! Fortunately 
>> we use a fpga as a northbridge.

>    Wait, CS5536 is a nortbridge itself!

    Apparently, it's only a south bridge. I must've mixed it with Geode itself.

WBR, Sergei



From sshtylyov at ru.mvista.com  Wed Jul 11 17:42:51 2007
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Wed, 11 Jul 2007 19:42:51 +0400
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
References: <4694A495.1050006@lemote.com>
	<Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
Message-ID: <4694FA7B.6030409@ru.mvista.com>

Hello.

Maciej W. Rozycki wrote:

>>"Control Logic
>>The INT output goes directly to the CPU interrupt input.
>>When an INT signal is activated, the CPU responds with an
>>Interrupt Acknowledge access that is translated to two
>>pulses on the INTA input of the PIC. At the first INTA pulse,
>>the highest priority IRR bit is loaded into the corresponding
>>ISR bit, and that IRR bit is reset. The second INTA pulse
>>instructs the PIC to present the 8-bit vector of the interrupt
>>handler onto the data bus."

>>Is it the responsibility of north bridge to reponse to intr with a PCI
>>Interrupt Ack cycle?

>  With an i386 system such a pair of INTA cycles would be generated by the 
> CPU itself and translated by the north bridge to a PCI Interrupt 
> Acknowledge cycle (see the PCI spec for a more elaborate description).

>  If the CPU does not generate INTA cycles, it is a common practice to let 
> it ask the north bridge for a PCI Interrupt Acknowledge in some other way, 
> typically by issuing a read cycle that returns the vector reported by the 
> interrupt controller.

>>it's a problem that my northbridge didn't implement that! Fortunately we use a
>>fpga as a northbridge.

>>it seem it's no way to fix this by software, for OCW3 didn't implemnt Poll
>>command:(

>  Huh?  Have you managed to find an 8259A clone *that* broken?  So what 

    It's not such a problem, believe me. ;-)
    Some PPC boards use such clones -- you can see the comment in 
arch/powerpc/sysdev/i8259.c.

> does it return if you write 0xc to the address 0x20 in the I/O port space 
> and then read back from that location?  You should complain to the 
> manufacturer -- they may be able to fix the problem in a later revision.

    Haha, here's an excerpt form CS5535 spec. update:

96. PIC does not support Polling mode

[...]

Implications: This mode is not normally used in x86 systems.
Resolution: None.

>>so I guess the the process is:
>>1) 8259 receive a int, a bit irr got set.
>>2) 8259 assert intr.
>>3) northbrige generate a int ack cycle.
>>4) cs5536 translate the ack into two INTA pulse, and the reponse northbridge
>>with a interrupt vector.
>>5) then my program can get the vector from northbridge?

>>Is that right?

    Indeed, this would seem right but one step skipped -- where CPU tells 
northbridge that it's accepted an interrupt (via INTA).

>  More or less -- 3-5 should probably be the outcome of a single read 
> transaction from the north bridge.  I.e. you issue a read to a "magic" 
> location, 3-5 happen, and the data value returned is the vector presented 
> by the interrupt controller on the PCI bus.

    Yeah, another way of doing the missed step.

>>Without int ack, generic linux-mips 8259 code can't work.

>  You can still dispatch interrupts manually by examining the IRR register, 
> but having a way to ask the 8259A's prioritiser would be nice.  Although 
> given such a lethal erratum you report I would not count on the 
> prioritiser to provide any useful flexibility...

    Why not? AMD just decided not to implement poll mode, that's all.

>   Maciej

WBR, Sergei



From macro at linux-mips.org  Wed Jul 11 17:48:35 2007
From: macro at linux-mips.org (Maciej W. Rozycki)
Date: Wed, 11 Jul 2007 16:48:35 +0100 (BST)
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <4694F4EB.8040000@lemote.com>
References: <4694A495.1050006@lemote.com>
	<Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
	<4694F4EB.8040000@lemote.com>
Message-ID: <Pine.LNX.4.64N.0707111634430.26459@blysk.ds.pg.gda.pl>

On Wed, 11 Jul 2007, Songmao Tian wrote:

> > Huh?  Have you managed to find an 8259A clone *that* broken?  So what does
> > it return if you write 0xc to the address 0x20 in the I/O port space and
> > then read back from that location?  You should complain to the 
> >   
> 
> It's the value of IRR, so guess IRR. AMD has well documented cs5536, I
> appreciate that.

 Indeed.  I am surprised they have decided to drop the poll command -- it 
surely does not require much logic as it mostly reuses what's used to 
produce the vector anyway and it is commonly used when 8259A 
implementations are interfaced to non-i386 processors.  PPC is another 
example.

> > More or less -- 3-5 should probably be the outcome of a single read
> > transaction from the north bridge.  I.e. you issue a read to a "magic"
> > location, 3-5 happen, and the data value returned is the vector presented by
> > the interrupt controller on the PCI bus.
> >   
> yeah, we can implement a register in north bridge.

 Strictly speaking it would not be a register, but a "PCI INTA address 
space" much like PCI memory or I/O port address spaces.  Though as the 
former ignores addresses driven on the bus, the space occupied does not 
have to be extensive -- I would assume whatever slot size is available 
with the address decoder you have implemented would do.

> > You can still dispatch interrupts manually by examining the IRR register,
> > but having a way to ask the 8259A's prioritiser would be nice.  Although
> > given such a lethal erratum you report I would not count on the prioritiser
> > to provide any useful flexibility...
> >   
> yeah, that's a straight thought, tried but failed:(, patch followed.

 You may have to modify other functions from arch/mips/kernel/i8259.c; 
yes, this makes the whole experience not as pretty as one would hope...

  Maciej



From macro at linux-mips.org  Wed Jul 11 18:05:26 2007
From: macro at linux-mips.org (Maciej W. Rozycki)
Date: Wed, 11 Jul 2007 17:05:26 +0100 (BST)
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <4694FA7B.6030409@ru.mvista.com>
References: <4694A495.1050006@lemote.com>
	<Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
	<4694FA7B.6030409@ru.mvista.com>
Message-ID: <Pine.LNX.4.64N.0707111653130.26459@blysk.ds.pg.gda.pl>

Hi,

> > does it return if you write 0xc to the address 0x20 in the I/O port space
> > and then read back from that location?  You should complain to the
> > manufacturer -- they may be able to fix the problem in a later revision.
> 
>    Haha, here's an excerpt form CS5535 spec. update:
> 
> 96. PIC does not support Polling mode
> 
> [...]
> 
> Implications: This mode is not normally used in x86 systems.
> Resolution: None.

 Yes, of course:

$ grep OCW3 arch/i386/kernel/*.c
arch/i386/kernel/time.c:		outb(0x0c, PIC_MASTER_OCW3);

not at all, indeed!

> > You can still dispatch interrupts manually by examining the IRR register,
> > but having a way to ask the 8259A's prioritiser would be nice.  Although
> > given such a lethal erratum you report I would not count on the prioritiser
> > to provide any useful flexibility...
> 
>    Why not? AMD just decided not to implement poll mode, that's all.

 If they have decided to skip such an "unimportant" bit of logic, they 
could have skipped more, only providing support for the basic FNM 
INT/INTA/EOI scheme -- the only one "architecturally" supported from the 
original IBM PC on.  And indeed, a brief look at the datasheed reveals 
they claim to have removed the SFNM too (which IMO provides a more 
reasonable nesting resolution and should be the default for setups where 
nesting is used, such as the environment as set up at the bootstrap by the 
PC BIOS).

  Maciej



From segher at kernel.crashing.org  Wed Jul 11 18:29:12 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Wed, 11 Jul 2007 18:29:12 +0200
Subject: [LinuxBIOS] Does MA map type effect MRS values?
In-Reply-To: <4694CA30.30001@gmail.com>
References: <46949F1C.7020204@gmail.com>
	<2EEB4E92-C563-4858-A50A-164F1A636074@kernel.crashing.org>
	<4694CA30.30001@gmail.com>
Message-ID: <6F641CFD-07D8-4A80-B22F-BFC877E1DC86@kernel.crashing.org>

>>> Simple question that I can't seem to find the answer to  
>>> _anywhere_. From
>>> JEDEC's docs, it sounds like it should, but I can't figure out  
>>> what the
>>> relationship is. Any info would be greatly appreciated ;)
>>
>> What is "MA map type"?  Are you talking about DDR1, DDR2,
>> DDR3, some GDDR, or what else, anyway?  :-)

> Sorry, Memory Address map type, in relation to the via cn700 (or  
> any via
> northbridge) and ddr2 ram. And the answer appears to be that it  
> doesn't,
> since the system is now working with either of two different MA map  
> type
> settings (yay!).

Ah, sounds like it just selects between two different kinds
of address interleaving.  Typically, one is best for random
access, and the other is best for accessing big blocks of
data.

In the (E)MRS regs, you only need to set things like CL, AL,
and termination settings.  It's quite important to get those
right of course ;-)


Segher




From rminnich at gmail.com  Wed Jul 11 18:36:31 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 11 Jul 2007 09:36:31 -0700
Subject: [LinuxBIOS] Does MA map type effect MRS values?
In-Reply-To: <6F641CFD-07D8-4A80-B22F-BFC877E1DC86@kernel.crashing.org>
References: <46949F1C.7020204@gmail.com>
	<2EEB4E92-C563-4858-A50A-164F1A636074@kernel.crashing.org>
	<4694CA30.30001@gmail.com>
	<6F641CFD-07D8-4A80-B22F-BFC877E1DC86@kernel.crashing.org>
Message-ID: <13426df10707110936k19326c05m95eb1670d8ab2b57@mail.gmail.com>

I think segher got it right, IIRC MA is for interleaving. It is
somewhat dependent on how the DIMM is wired in older systems IIRC ...

ron



From segher at kernel.crashing.org  Wed Jul 11 18:42:35 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Wed, 11 Jul 2007 18:42:35 +0200
Subject: [LinuxBIOS] DIMM Page Size
In-Reply-To: <20070711094100.pt4t4pyrfac0og8s@www.smittys.pointclark.net>
References: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net>
	<4E7A3EDF-B1C5-4C51-A9FB-495F0B4CFDC4@kernel.crashing.org>
	<20070711094100.pt4t4pyrfac0og8s@www.smittys.pointclark.net>
Message-ID: <962E2F98-BDB2-40CB-9B77-6BE660676FCE@kernel.crashing.org>

>>> Anyone know what the mathmatical calculation is to determine a Dimms
>>> "Page Size"?? I found this but it does not seem to work:
>>>
>>> Page size = (2^col)*bus_width
>>> where,
>>> col = number of column address lines (SPD byte 4: Number of  
>>> Column  Addresses)
>>> bus_width = number of data(DQ) lines (???SPD byte 13: SDRAM  
>>> Device Width???)
>>
>> "device width" is the number of data lines per DRAM chip on
>> your DIMM.  This isn't the same as the number of data lines
>> on the DIMM itself; that is 64 usually (not counting the ECC
>> bits).  This info is in the SPD as well.
>
> Ok, so that must be byte 6: Data Width of Assembly.

Yes.

> It still does not seem to compute though.
>
> col = 9 /* SPD byte 4: Number of Column Addresses */
> bus_width = 64 /* SPD byte 6: Data Width of Assembly */
>
> page_size = (2^col)*bus_width
>
> 5184 = 81 * 64
>
> Which is not correct because the DIMM has a 4k page size.

2**9 * 64 = 512 * 64 = 32k bits = 4kB.


Segher




From macro at linux-mips.org  Wed Jul 11 18:51:05 2007
From: macro at linux-mips.org (Maciej W. Rozycki)
Date: Wed, 11 Jul 2007 17:51:05 +0100 (BST)
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <Pine.LNX.4.64N.0707111634430.26459@blysk.ds.pg.gda.pl>
References: <4694A495.1050006@lemote.com>
	<Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
	<4694F4EB.8040000@lemote.com>
	<Pine.LNX.4.64N.0707111634430.26459@blysk.ds.pg.gda.pl>
Message-ID: <Pine.LNX.4.64N.0707111729310.26459@blysk.ds.pg.gda.pl>

On Wed, 11 Jul 2007, Maciej W. Rozycki wrote:

> > > You can still dispatch interrupts manually by examining the IRR register,
> > > but having a way to ask the 8259A's prioritiser would be nice.  Although
> > > given such a lethal erratum you report I would not count on the prioritiser
> > > to provide any useful flexibility...
> > >   
> > yeah, that's a straight thought, tried but failed:(, patch followed.
> 
>  You may have to modify other functions from arch/mips/kernel/i8259.c; 
> yes, this makes the whole experience not as pretty as one would hope...

 BTW, have you considered skipping the whole 8259A legacy burden and using 
the interrupt mapper directly?  From a brief look at the datasheet I 
conclude you should be able to OR all the interrupt lines to a single 
8259A input (say IRQ0 for the sake of this consideration -- it does not 
matter), set it to the level triggered mode, mask all the 8259A inputs but 
this one and ignore the device from then on.

 It would work as a "virtual wire", using the Intel's terminology, with 
its INT output simply following its IR0 input.  You can type:

$ grep '8259A Virtual Wire' arch/i386/kernel/io_apic.c

for a reference; ;-) you can skip the AEOI setup as in a system based on a 
MIPS processor an INTA cycle will be unlikely to reach the 8259A by 
accident (which may happen in the wild world of broken PCs) -- which you 
have learnt the hard way by now already.

 You can then dispatch interrupts based on the interrupt mapper registers 
which has this nice side effect of much of the sharing having been 
removed.  It will not work with edge-triggered interrupts, but you do not 
need that 8254 timer, do you?

  Maciej



From jordan.crouse at amd.com  Wed Jul 11 20:05:41 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 12:05:41 -0600
Subject: [LinuxBIOS] Fun with LAR....
Message-ID: <20070711180541.GB20885@cosmic.amd.com>

Hey all - 

I've been working on modifying buildROM to understand LinuxBIOSv3.  Part
of that effort is being able to add payload and arbitrary blobs of binary
(VSA, VGA BIOSen, etc) to existing LARs.  So, needless to say, I've been
hacking away on LAR over the last few days, and the following patches
are the result of that.  I'll try to explain a little bit more about
each patch as it comes.

Please keep in mind that these are not set in stone - I expect heavy
criticism and thought about whats gong on here, and I know you won't let
me down. :)

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From jordan.crouse at amd.com  Wed Jul 11 20:07:47 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 12:07:47 -0600
Subject: [LinuxBIOS] [PATCH][LAR] Add a top level target for LAR
Message-ID: <20070711180747.GC20885@cosmic.amd.com>

This is the easiest patch.. :)  Add a top level 'lar' target to v3, 
so I can build the utility by itself.  Until LAR gets seperated out
into its own repository, I'm going to have to figure out a way to make
buildROM build lar independently of the rest of the v3 code, and this is
probably the best way.

Jordan
-------------- next part --------------
[PATCH][LAR] Add a top level target for LAR

Add a top level target to the LAR makefile so it can be built by itself
in the LBv3 tree.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Index: LinuxBIOSv3/util/lar/Makefile
===================================================================
--- LinuxBIOSv3.orig/util/lar/Makefile	2007-07-09 11:47:18.000000000 -0600
+++ LinuxBIOSv3/util/lar/Makefile	2007-07-09 11:47:33.000000000 -0600
@@ -47,6 +47,8 @@
 	$(Q)$(HOSTCC) $(HOSTCFLAGS) -c $< -o $@
 
 
+lar: $(obj)/util/lar/lar
+
 # -----------------------------------------------------------------------------
 # Stuff below this line is for debugging purposes only.
 

From peter at stuge.se  Wed Jul 11 20:12:04 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 11 Jul 2007 20:12:04 +0200
Subject: [LinuxBIOS] [PATCH][LAR] Add a top level target for LAR
In-Reply-To: <20070711180747.GC20885@cosmic.amd.com>
References: <20070711180747.GC20885@cosmic.amd.com>
Message-ID: <20070711181204.22915.qmail@stuge.se>

On Wed, Jul 11, 2007 at 12:07:47PM -0600, Jordan Crouse wrote:
> Until LAR gets seperated out into its own repository, I'm going to
> have to figure out a way to make buildROM build lar independently
> of the rest of the v3 code, and this is probably the best way.

Sorry, I disagree. :)

I would expect lar to be a target in util/


//Peter



From jordan.crouse at amd.com  Wed Jul 11 20:15:17 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 12:15:17 -0600
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
Message-ID: <20070711181517.GD20885@cosmic.amd.com>

Okay, here we go.  This patch is the meat and potatoes of the whole
operation.  This takes the code previous in create.c, extract.c, list.c
and bootblock.c, and consolidates them into one file.  We use the concept
of a "stream" of sorts here - we create or open a lar, apply operations to
it, and then close it when we are done.  This allows us to mmap the LAR
for speed and simplicity.  This has the slight side effect of requiring that
the user specify a size for the LAR when they create it, but I don't think
thats really a bad thing.

One thing you might miss is that I've turned the path name of the bootblock
into a constant name 'bootblock'.  I did this for a number of reasons -
mainly because its easier to partition off the "bootblock area", and keep
the other blobs from infringing on it - but also because I can't grok an
good reason to have arbitrary bootblock names.

BTW - There isn't anything in this patch precluding a 'lar_delete_files"
function.  If deleting things from a LAR is interesting, then it should be
pretty easy to get that in here too.

Jordan
-------------- next part --------------
[PATCH][LAR] New LAR access functions

In preparation for adding new LAR functionality - this patch consolidates
creating and accessing the LAR into new code utilizing mmap which
facilitates moving about within the archive. 

This code also turns the bootblock path name as a constant value.
It also requires that the user specify a size when the LAR is
created.

Signed-off-by: Jordan crouse <jordan.crouse at amd.com>
Index: LinuxBIOSv3/util/lar/Makefile
===================================================================
--- LinuxBIOSv3.orig/util/lar/Makefile	2007-07-11 11:40:37.000000000 -0600
+++ LinuxBIOSv3/util/lar/Makefile	2007-07-11 11:41:37.000000000 -0600
@@ -18,7 +18,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
 ##
 
-LAROBJ := lar.o create.o extract.o list.o lib.o bootblock.o
+LAROBJ := lar.o stream.o lib.o
 
 LARDIR := lardir
 
Index: LinuxBIOSv3/util/lar/lar.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/lar.c	2007-07-11 11:40:29.000000000 -0600
+++ LinuxBIOSv3/util/lar/lar.c	2007-07-11 11:41:37.000000000 -0600
@@ -62,6 +62,64 @@
 	return bootblock;
 }
 
+int create_lar(const char *archivename, struct file *files)
+{
+	struct lar *lar = lar_new_archive(archivename, larsize);
+
+	if (lar == NULL) {
+		fprintf(stderr, "Unable to create %s as a LAR archive.\n",
+			archivename);
+		exit(1);
+	}
+
+	for( ; files; files = files->next) {
+		if (lar_add_file(lar, files->name)) {
+			fprintf(stderr, "Error adding %s to the LAR.\n", files->name);
+			lar_close_archive(lar);
+			exit(1);
+		}
+	}
+
+	if (lar_add_bootblock(lar, bootblock)) {
+		fprintf(stderr, "Error adding the bootblock to the LAR.\n");
+		lar_close_archive(lar);
+		exit(1);
+	}
+
+	lar_close_archive(lar);
+	return 0;
+}
+
+int list_lar(const char *archivename, struct file *files)
+{
+	struct lar *lar = lar_open_archive(archivename);
+
+	if (lar == NULL) {
+		fprintf(stderr, "Unable to open LAR archive %s\n", archivename);
+		exit(1);
+	}
+
+	lar_list_files(lar, files);
+	lar_close_archive(lar);
+	return 0;
+}
+
+int extract_lar(const char *archivename, struct file *files)
+{
+	int ret;
+
+	struct lar *lar = lar_open_archive(archivename);
+
+	if (lar == NULL) {
+		fprintf(stderr, "Unable to open LAR archive %s\n", archivename);
+		exit(1);
+	}
+
+	ret = lar_extract_files(lar, files);
+	lar_close_archive(lar);
+	return ret;
+}
+
 int main(int argc, char *argv[])
 {
 	int opt;
@@ -173,16 +231,9 @@
 
 		/* adding a bootblock only makes sense when creating a lar */
 		if (!larsize) {
-			printf("Warning: When specifying a bootblock "
-			       "you should also set an archive size.\n");
-		}
-
-		/* load the bootblock */
-		if (larmode == CREATE) {
-			load_bootblock(bootblock);
-			fixup_bootblock();
+			printf("When creating a LAR archive, you must specify an archive size.\n");
+			exit(1);
 		}
-
 	}
 
 	if (optind < argc) {
Index: LinuxBIOSv3/util/lar/lar.h
===================================================================
--- LinuxBIOSv3.orig/util/lar/lar.h	2007-07-11 11:40:29.000000000 -0600
+++ LinuxBIOSv3/util/lar/lar.h	2007-07-11 11:41:37.000000000 -0600
@@ -55,6 +55,9 @@
 #define MAX_PATHLEN 1024
 #define BOOTBLOCK_SIZE 16384
 
+#define BOOTBLOCK_NAME "bootblock"
+#define BOOTBLOCK_NAME_LEN 16
+
 typedef uint32_t u32;
 
 struct lar_header {
@@ -72,6 +75,12 @@
 	u32 compression;
 };
 
+struct lar {
+	int fd;
+	unsigned char *map;
+	int size;
+};
+
 enum compalgo { none = 0, lzma = 1, nrv2b = 2 };
 
 typedef void (*compress_func) (char *, u32, char *, u32 *);
Index: LinuxBIOSv3/util/lar/stream.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv3/util/lar/stream.c	2007-07-11 11:48:23.000000000 -0600
@@ -0,0 +1,555 @@
+/*
+ * lar - LinuxBIOS archiver
+ *
+ * This includes code from previous versions of the LAR utility,
+ * including create.c, list.c, extract.c and bootblock.c
+ *
+ * Copyright (C) 2006-2007 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+ * Copyright (C) 2007 Patrick Georgi <patrick at georgi-clan.de>
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <netinet/in.h>
+#include <libgen.h>
+
+#include "lib.h"
+#include "lar.h"
+
+#define err(fmt,args...) fprintf(stderr, fmt, ##args)
+
+extern enum compalgo algo;
+
+static inline int get_bootblock_offset(int size)
+{
+	return size - (BOOTBLOCK_SIZE + sizeof(struct lar_header) + BOOTBLOCK_NAME_LEN);
+}
+
+static int lar_read_size(struct lar *lar, int filelen)
+{
+	unsigned int *ptr = (unsigned int *) (lar->map + (filelen - 12));
+	return ptr[0];
+}
+
+static void annotate_bootblock(unsigned char *ptr, unsigned int size)
+{
+	int i;
+	unsigned int *p;
+
+	for(i = 13; i > 0; i--)
+		ptr[BOOTBLOCK_SIZE - i] = '\0';
+
+	p = (unsigned int *) (ptr + BOOTBLOCK_SIZE - 12);
+	p[0] = size;
+}
+
+int lar_add_bootblock(struct lar *lar, char *bootblock)
+{
+	unsigned char *offset;
+	struct lar_header *header;
+	int ret;
+
+	if (bootblock != NULL) {
+		struct stat s;
+
+	        ret = stat(bootblock, &s);
+
+		if (ret == -1) {
+			err("Unable to stat %s\n", bootblock);
+			return -1;
+		}
+
+		if (s.st_size != BOOTBLOCK_SIZE) {
+			err("Bootblock %s does not appear to be a bootblock.\n",
+			    bootblock);
+
+			return -1;
+		}
+	}
+
+	offset = lar->map + get_bootblock_offset(lar->size);
+	header = (struct lar_header *) offset;
+
+	memcpy(header->magic, MAGIC, 8);
+	header->reallen = htonl(BOOTBLOCK_SIZE);
+	header->len = htonl(BOOTBLOCK_SIZE);
+	header->offset = htonl(sizeof(struct lar_header) + BOOTBLOCK_NAME_LEN);
+
+	offset += sizeof(struct lar_header);
+	strcpy((char *) offset, BOOTBLOCK_NAME);
+
+	offset += BOOTBLOCK_NAME_LEN;
+
+	/* If a file waas specified, then load it, and read it directly into place */
+
+	if (bootblock != NULL) {
+
+		int fd = open(bootblock, O_RDONLY);
+
+		if (fd == -1) {
+			err("Unable to read bootblock file %s\n", bootblock);
+			return -1;
+		}
+
+		ret = read(fd, offset, BOOTBLOCK_SIZE);
+
+		close(fd);
+
+		if (ret != BOOTBLOCK_SIZE) {
+			err("Unable to read all the bytes in the bootblock file.\n");
+			return -1;
+		}
+	}
+
+	annotate_bootblock(offset, lar->size);
+	return 0;
+}
+
+static struct lar * _open_lar(const char *archive, unsigned int size, int flags)
+{
+	struct lar *lar = calloc(sizeof(*lar), 1);
+
+	if (lar == NULL) {
+		err("Unable to allocate memory.\n");
+		return NULL;
+	}
+
+	lar->fd = open(archive, flags, S_IRUSR | S_IWUSR);
+
+	if (lar->fd == -1) {
+		err("Couldn't open the archive %s\n", archive);
+		goto err;
+	}
+
+	/* Expand the file to the correct size */
+
+	if (lseek(lar->fd, size - 1, SEEK_SET) == -1) {
+	  err("Unable to write the archive %s\n", archive);
+	  goto err;
+	}
+
+	if (write(lar->fd, "", 1) != 1) {
+	  err("Unable to write the file %s\n", archive);
+	  goto err;
+	}
+
+	lar->map = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED,
+		lar->fd, 0);
+
+	lar->size = size;
+
+	if (lar->map == MAP_FAILED) {
+		err("Unable to map the archive %s\n", archive);
+		goto err;
+	}
+
+	return lar;
+
+ err:
+	if (lar->fd >= 0)
+		close(lar->fd);
+
+	unlink(archive);
+
+	if (lar)
+		free(lar);
+
+	return NULL;
+}
+
+static void _close_lar(struct lar *lar)
+{
+	munmap(lar->map, lar->size);
+	close(lar->fd);
+
+	free(lar);
+}
+
+void lar_close_archive(struct lar *lar)
+{
+	_close_lar(lar);
+}
+
+struct lar * lar_new_archive(const char *archive, unsigned int size)
+{
+	struct lar *lar;
+	int i;
+
+	if (!access(archive, F_OK)) {
+		err("Archive file %s already exists\n", archive);
+		return NULL;
+	}
+
+	lar = _open_lar(archive, size, O_RDWR | O_CREAT);
+
+	if (lar == NULL)
+		return NULL;
+
+	/* Fill the whole thing with flash friendly 0xFFs */
+	memset(lar->map, 0xFF, lar->size);
+
+	/* Make a dummy bootblock */
+
+	if (lar_add_bootblock(lar, NULL)) {
+		_close_lar(lar);
+		return NULL;
+	}
+
+	return lar;
+}
+
+struct lar * lar_open_archive(const char *archive)
+{
+	struct lar *lar;
+	int ret, romlen;
+	struct stat s;
+
+	ret = stat(archive, &s);
+
+	if (ret == -1) {
+		err("Unable to stat %s\n", archive);
+		return NULL;
+	}
+
+	lar =  _open_lar(archive, s.st_size, O_RDWR);
+
+	/* Sanity check - make sure the bootblock header is the same length as the LAR archive */
+
+	romlen = lar_read_size(lar, s.st_size);
+
+	if (romlen != s.st_size) {
+		err("Size mismatch - the header says %d but the file is %d bytes long.\n",
+		    romlen, (int) s.st_size);
+		_close_lar(lar);
+		return NULL;
+	}
+
+	return lar;
+}
+
+/* return the offset of the empty space in the LAR */
+
+static int lar_empty_offset(struct lar *lar)
+{
+	int offset = 0;
+	struct lar_header *header;
+
+	while (offset < get_bootblock_offset(lar->size)) {
+		header = (struct lar_header *) (lar->map + offset);
+
+		/* We interpet the absence of the magic as empty space */
+
+		if (strncmp(header->magic, MAGIC, 8))
+			break;
+
+		offset += (ntohl(header->len) + ntohl(header->offset) - 1)
+			& 0xfffffff0;
+	}
+
+	if (offset >= get_bootblock_offset(lar->size))
+		return -1;
+
+	return offset;
+}
+
+static int file_in_list(struct file *files, char *filename)
+{
+	struct file *p;
+
+	if (files == NULL)
+		return 1;
+
+	for(p = files ; p; p = p->next) {
+		if (!strcmp(p->name, filename))
+			return 1;
+	}
+
+	return 0;
+}
+
+void lar_list_files(struct lar *lar, struct file *files)
+{
+	unsigned char *ptr = lar->map;
+	char *filename;
+
+	struct lar_header *header;
+	struct file *fp;
+
+	while (ptr < (lar->map + get_bootblock_offset(lar->size))) {
+		header = (struct lar_header *) ptr;
+
+		/* We interpet the absence of the magic as empty space */
+
+		if (strncmp(header->magic, MAGIC, 8))
+			break;
+
+		filename = (char *) (ptr + sizeof(struct lar_header));
+
+		if (file_in_list(files, filename)) {
+			printf("  %s ", filename);
+
+			if (ntohl(header->compression) == none) {
+				printf("(%d bytes @0x%lx)\n",
+				       ntohl(header->len),
+				       (unsigned long)(ptr - lar->map) +
+				       ntohl(header->offset));
+			} else {
+				printf("(%d bytes, %s compressed to %d bytes "
+				       "@0x%lx)\n",
+				       ntohl(header->reallen),
+				       algo_name[ntohl(header->compression)],
+				       ntohl(header->len),
+				       (unsigned long)(ptr - lar->map) +
+				       ntohl(header->offset));
+			}
+		}
+
+		ptr += (ntohl(header->len) + ntohl(header->offset) - 1)
+			& 0xfffffff0;
+	}
+
+	/* Show the bootblock */
+
+	if (file_in_list(files, BOOTBLOCK_NAME)) {
+		header = (struct lar_header *)
+			(lar->map + get_bootblock_offset(lar->size));
+
+		printf("  bootblock (%d bytes @0x%x)\n",
+		       ntohl(header->len),
+		       get_bootblock_offset(lar->size) +
+		       ntohl(header->offset));
+	}
+}
+
+static int _write_file(char *filename, unsigned char *buffer, int len)
+{
+	char *path = strdup(filename);
+	int fd, ret;
+
+	if (path == NULL) {
+		err("Out of memory.\n");
+		return -1;
+	}
+
+	mkdirp((const char *) dirname(path), 0755);
+	free(path);
+
+	fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644);
+
+	if (fd == -1) {
+		err("Error creating file %s\n", filename);
+		return -1;
+	}
+
+	ret = write(fd, buffer, len);
+
+	if (ret != len)
+		err("Error writingthe file %s\n", filename);
+
+	close(fd);
+	return (ret == len) ? 0 : -1;
+}
+
+int lar_extract_files(struct lar *lar, struct file *files)
+{
+	unsigned char *ptr = lar->map;
+	char *filename;
+	struct lar_header *header;
+	int ret = 0;
+
+	while (ptr < (lar->map + get_bootblock_offset(lar->size))) {
+
+		header = (struct lar_header *) ptr;
+
+		if (strncmp(header->magic, MAGIC, 8))
+			break;
+
+		filename = (char *) (ptr + sizeof(struct lar_header));
+
+		if (file_in_list(files, filename)) {
+
+			if (ntohl(header->compression) == none) {
+				ret = _write_file(filename,
+						  ptr + ntohl(header->offset),
+						  ntohl(header->len));
+			}
+			else {
+				unsigned char *buf =
+					malloc(ntohl(header->reallen));
+
+				if (buf == NULL) {
+					err("Out of memory.\n");
+					return -1;
+				}
+
+				uncompress_functions[ntohl(header->compression)](
+					(char*) buf,
+					(char *) ptr + ntohl(header->offset),
+					ntohl(header->len));
+
+				ret = _write_file(filename, buf,
+					ntohl(header->reallen));
+
+				free(buf);
+			}
+
+			if (ret == -1)
+				return -1;
+		}
+
+		ptr += (ntohl(header->len) + ntohl(header->offset) - 1)
+			& 0xfffffff0;
+	}
+
+	if (file_in_list(files, BOOTBLOCK_NAME)) {
+		header = (struct lar_header *)
+			(lar->map + get_bootblock_offset(lar->size));
+
+		ret = _write_file((char *) BOOTBLOCK_NAME,
+				  lar->map + (get_bootblock_offset(lar->size) + ntohl(header->offset)),
+				  BOOTBLOCK_SIZE);
+	}
+
+	return ret;
+}
+
+int lar_add_file(struct lar *lar, char *name)
+{
+	char *filename, *ptr, *temp;
+	enum compalgo thisalgo;
+	struct lar_header *header;
+	int offset, ret, fd, hlen;
+	u32 complen;
+	int pathlen;
+	struct stat s;
+	u32 *walk,  csum;
+
+	/* Find the beginning of the available space in the LAR */
+	offset = lar_empty_offset(lar);
+
+	thisalgo = algo;
+
+	filename = name;
+
+	if (strstr(name, "nocompress:") == name) {
+		filename += 11;
+		thisalgo = none;
+	}
+
+	if (filename[0] == '.' && filename[1] == '/')
+		filename += 2;
+
+	ret = stat (filename, &s);
+
+	if (ret) {
+		err("Unable to stat %s\n", filename);
+		return -1;
+	}
+
+	/* Allocate a temporary buffer to compress into - this is unavoidable,
+	   because we need to make sure that the compressed data will fit in
+	   the LAR, and we won't know the size of the compressed data until
+	   we actually compress it */
+
+	temp = calloc(s.st_size, 1);
+
+	if (temp == NULL) {
+		err("Out of memory.\n");
+		return -1;
+	}
+
+	/* Open the file */
+	fd = open(filename, O_RDONLY);
+
+	if (fd == -1) {
+		err("Unable to open %s\n", filename);
+		free(temp);
+		return -1;
+	}
+
+	ptr = mmap(0, s.st_size, PROT_READ, MAP_SHARED, fd, 0);
+
+	if (ptr == MAP_FAILED) {
+		err("Unable to map %s\n", filename);
+		close(fd);
+		free(temp);
+		return -1;
+	}
+
+
+	/* Do the compression step */
+	compress_functions[thisalgo](ptr, s.st_size, temp, &complen);
+
+	if (complen >= s.st_size && (thisalgo != none)) {
+		thisalgo = none;
+		compress_functions[thisalgo](ptr, s.st_size, temp, &complen);
+	}
+
+	munmap(ptr, s.st_size);
+	close(fd);
+
+	pathlen = strlen(filename) + 1 > MAX_PATHLEN ? MAX_PATHLEN : strlen(filename) + 1;
+
+	/* Figure out how big our header will be */
+	hlen = sizeof(struct lar_header) + pathlen;
+	hlen = (hlen + 15) & 0xFFFFFFF0;
+
+	if (offset + hlen + complen >= get_bootblock_offset(lar->size)) {
+		err("Not enough room in the LAR to add the file.\n");
+		free(temp);
+		return -1;
+	}
+
+	/* Lets do this thing */
+
+	/* Zero out the header area */
+	memset(lar->map + offset, 0, hlen);
+
+	header = (struct lar_header *) (lar->map + offset);
+
+	memcpy(header, MAGIC, 8);
+	header->compression = htonl(thisalgo);
+	header->reallen = htonl(s.st_size);
+	header->len = htonl(complen);
+	header->offset = htonl(hlen);
+
+	/* Copy the path name */
+	strncpy((char *) (lar->map + offset + sizeof(struct lar_header)),
+		filename, pathlen - 1);
+
+	/* Copy in the data */
+	memcpy(lar->map + (offset + hlen), temp, complen);
+
+	/* Figure out the checksum */
+
+	csum = 0;
+	for (walk = (u32 *) (lar->map + offset);
+	     walk < (u32 *) (temp + complen + hlen);
+	     walk++) {
+		csum += ntohl(*walk);
+	}
+	header->checksum = htonl(csum);
+
+	free(temp);
+	return 0;
+}

From jordan.crouse at amd.com  Wed Jul 11 20:16:19 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 12:16:19 -0600
Subject: [LinuxBIOS] [PATCH][LAR]  Remove old files
Message-ID: <20070711181619.GE20885@cosmic.amd.com>

Simple patch - this removes the files that were obsoleted by the previous
patch.

Jordan
-------------- next part --------------
[PATCH][LAR]  Remove old files

Remove create.c, list.c, extract.c and bootblock.c since their functionality
has been integrated into stream.c.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Index: LinuxBIOSv3/util/lar/create.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/create.c	2007-07-11 11:40:29.000000000 -0600
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,278 +0,0 @@
-/*
- * lar - LinuxBIOS archiver
- *
- * Copyright (C) 2006-2007 coresystems GmbH
- * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
- * Copyright (C) 2007 Patrick Georgi <patrick at georgi-clan.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <netinet/in.h>
-#include <libgen.h>
-
-#include "lib.h"
-#include "lar.h"
-
-extern enum compalgo algo;
-
-void compress_impossible(char *in, u32 in_len, char *out, u32 *out_len)
-{
-	fprintf(stderr,
-		"The selected compression algorithm wasn't compiled in.\n");
-	exit(1);
-}
-
-void do_no_compress(char *in, u32 in_len, char *out, u32 *out_len)
-{
-	memcpy(out, in, in_len);
-	out_len[0] = in_len;
-}
-
-int create_lar(const char *archivename, struct file *files)
-{
-	int i, ret;
-	int diff = 0;
-	int bb_header_len = 0;
-	FILE *archive, *source;
-	char *tempmem;
-	char *filebuf, *filetarget;
-	char *pathname;
-	u32 *walk;
-	u32 csum;
-	int pathlen, entrylen, filelen;
-	u32 compfilelen;
-	long currentsize = 0;
-	struct lar_header *header;
-	struct stat statbuf;
-	enum compalgo thisalgo;
-
-	if (!files) {
-		fprintf(stderr, "No files for archive %s\n", archivename);
-		exit(1);
-	}
-
-	if (verbose())
-		printf("Opening %s\n", archivename);
-
-	archive = fopen(archivename, "w");
-	if (!archive) {
-		fprintf(stderr, "Could not open archive %s for writing\n",
-			archivename);
-		exit(1);
-	}
-
-	while (files) {
-		char *name = files->name;
-
-		thisalgo = algo;
-
-		if (strstr(name, "nocompress:") == name) {
-			name += 11;
-			thisalgo = none;
-		}
-
-		/* skip ./ if available */
-		if (name[0] == '.' && name[1] == '/')
-			name += 2;
-
-		if (verbose())
-			printf("  Adding %s to archive\n", name);
-
-		ret = stat(name, &statbuf);
-		if (ret) {
-			fprintf(stderr, "No such file %s\n", name);
-			exit(1);
-		}
-		filelen = statbuf.st_size;
-
-		tempmem = malloc(sizeof(struct lar_header) + MAX_PATHLEN
-				 + filelen + 16);
-		if (!tempmem) {
-			fprintf(stderr, "Out of memory.\n");
-			return (1);
-		}
-		memset(tempmem, 0, sizeof(struct lar_header) + MAX_PATHLEN
-		       + filelen + 16);
-
-		header = (struct lar_header *)tempmem;
-		pathname = tempmem + sizeof(struct lar_header);
-		pathlen = snprintf(pathname, MAX_PATHLEN - 1, name) + 1;
-		pathlen = (pathlen + 15) & 0xfffffff0;	/* Align to 16 bytes. */
-
-		/* Read file into memory. */
-		filebuf = malloc(filelen);
-		filetarget = pathname + pathlen;
-		source = fopen(name, "r");
-		if (!source) {
-			fprintf(stderr, "No such file %s\n", name);
-			exit(1);
-		}
-		fread(filebuf, filelen, 1, source);
-		fclose(source);
-		compress_functions[thisalgo](filebuf, filelen, filetarget,
-					     &compfilelen);
-		if ((compfilelen >= filelen) && (thisalgo != none)) {
-			thisalgo = none;
-			compress_functions[thisalgo](filebuf, filelen,
-						     filetarget, &compfilelen);
-		}
-		free(filebuf);
-
-		/* Create correct header. */
-		memcpy(header, MAGIC, 8);
-		header->compression = htonl(thisalgo);
-		header->reallen = htonl(filelen);
-		header->len = htonl(compfilelen);
-		header->offset = htonl(sizeof(struct lar_header) + pathlen);
-
-		/* Calculate checksum. */
-		csum = 0;
-		for (walk = (u32 *) tempmem;
-		     walk < (u32 *) (tempmem + compfilelen +
-				     sizeof(struct lar_header) + pathlen);
-		     walk++) {
-			csum += ntohl(*walk);
-		}
-		header->checksum = htonl(csum);
-
-		/* Write out entry to archive. */
-		entrylen = (compfilelen + pathlen + sizeof(struct lar_header) +
-			    15) & 0xfffffff0;
-
-		fwrite(tempmem, entrylen, 1, archive);
-
-		free(tempmem);
-
-		/* size counter */
-		currentsize += entrylen;
-
-		files = files->next;
-	}
-
-	/* Calculate difference, if a size has been specified.
-	 * If diff is below zero, the size has been exceeded.
-	 * If diff is above zero, it specifies the number of 
-	 * padding bytes required for the image.
-	 * Otherwise diff stays 0 and no action is taken below.
-	 */
-	if (get_larsize())
-		diff = get_larsize() - currentsize;
-
-	/* If there's a bootblock loaded, some space is required
-	 * _after_ the padding. 
-	 * Calculate this size here, but write the bootblock later.
-	 */
-
-	if (bootblock_len) {
-		if (verbose())
-			printf("Detected bootblock of %d bytes\n",
-			       bootblock_len);
-
-		bb_header_len = sizeof(struct lar_header) +
-		    ((strlen(basename(get_bootblock())) + 15) & 0xfffffff0);
-
-		bb_header_len = (bb_header_len + 15) & 0xfffffff0;
-
-		if (verbose())
-			printf("Required bootblock header of %d bytes\n",
-			       bb_header_len);
-
-		diff -= bootblock_len;
-		diff -= bb_header_len;
-	}
-
-	/* The image became too big. Print an error message and exit,
-	 * deleting the file. So nobody used an invalid image by accident.
-	 *
-	 * Don't delete the image in "Out of memory" situations. If memory
-	 * is _that_ tight that a few bytes don't fit anymore, everything 
-	 * else will fail as well, so just print an error and exit the 
-	 * program as soon as possible.
-	 */
-
-	if (diff < 0) {
-		fprintf(stderr,
-			"Error: LAR archive exceeded size (%ld > %ld)\n",
-			currentsize, get_larsize());
-
-		/* Open files can not be deleted. */
-		fclose(archive);
-		/* File is too big, delete it. */
-		unlink(archivename);
-		return -1;
-	}
-
-	/* Pad the image. */
-
-	if (diff > 0) {
-		char *padding;
-		/* generate padding (0xff is flash friendly) */
-		padding = malloc(diff);
-		if (!padding) {
-			fprintf(stderr, "Out of memory.\n");
-			exit(1);
-		}
-		memset(padding, 0xff, diff);
-		fwrite(padding, diff, 1, archive);
-		free(padding);
-	}
-
-	if (bootblock_len) {
-		char *bootblock_header;
-		struct lar_header *bb;
-
-		bootblock_header = malloc(bb_header_len);
-		if (!bootblock_header) {
-			fprintf(stderr, "Out of memory.\n");
-			exit(1);
-		}
-
-		memset(bootblock_header, 0, bb_header_len);
-
-		/* construct header */
-		bb = (struct lar_header *)bootblock_header;
-		memcpy(bb->magic, MAGIC, 8);
-		bb->reallen = htonl(bootblock_len);
-		bb->len = htonl(bootblock_len);
-		bb->offset = htonl(bb_header_len);
-
-		/* TODO checksum */
-
-		/* Write filename. we calculated the buffer size, 
-		 * so no overflow danger here.
-		 */
-		strcpy(bootblock_header + sizeof(struct lar_header),
-		       basename(get_bootblock()));
-
-		fwrite(bootblock_header, bb_header_len, 1, archive);
-		fwrite(bootblock_code, bootblock_len, 1, archive);
-	}
-
-	fclose(archive);
-
-	if (verbose())
-		printf("done.\n");
-
-	return 0;
-}
Index: LinuxBIOSv3/util/lar/list.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/list.c	2007-07-11 11:40:29.000000000 -0600
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,121 +0,0 @@
-/*
- * lar - LinuxBIOS archiver
- *
- * Copyright (C) 2006-2007 coresystems GmbH
- * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
- * Copyright (C) 2007 Patrick Georgi <patrick at georgi-clan.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <netinet/in.h>
-
-#include "lib.h"
-#include "lar.h"
-
-int list_lar(const char *archivename, struct file *files)
-{
-	int archivefile;
-	char *inmap;
-	char *walk;
-	char *fullname;
-	struct lar_header *header;
-	struct stat statbuf;
-	int archivelen;
-	int do_extract;
-	int i;
-
-	if (stat(archivename, &statbuf) != 0) {
-		fprintf(stderr, "Error opening %s: %s\n",
-			archivename, strerror(errno));
-		exit(1);
-	}
-
-	if (verbose())
-		printf("Opening %s\n", archivename);
-
-	archivefile = open(archivename, O_RDONLY);
-	if (archivefile == -1) {
-		printf("Error while opening %s: %s\n",
-		       archivename, strerror(errno));
-		exit(1);
-	}
-	archivelen = statbuf.st_size;
-
-	inmap = mmap(NULL, statbuf.st_size, PROT_READ,
-		     MAP_SHARED, archivefile, 0);
-
-	for (walk = inmap; walk < inmap + statbuf.st_size; walk += 16) {
-		if (strcmp(walk, MAGIC) != 0)
-			continue;
-
-		header = (struct lar_header *)walk;
-		fullname = walk + sizeof(struct lar_header);
-
-		do_extract = 1;
-		if (files) {
-			struct file *fwalk = files;
-			do_extract = 0;
-			while (fwalk) {
-				if (strcmp(fullname, fwalk->name) == 0) {
-					do_extract = 1;
-					break;
-				}
-				fwalk = fwalk->next;
-			}
-		}
-
-		/* Don't extract this one, skip it. */
-		if (!do_extract) {
-			continue;
-		}
-
-		printf("  %s ", walk + sizeof(struct lar_header));
-
-		if (ntohl(header->compression) == none) {
-			printf("(%d bytes @0x%lx)\n",
-			       ntohl(header->len),
-			       (unsigned long)(walk - inmap) +
-			       ntohl(header->offset));
-		} else {
-			printf("(%d bytes, %s compressed to %d bytes "
-			       "@0x%lx)\n",
-			       ntohl(header->reallen),
-			       algo_name[ntohl(header->compression)],
-			       ntohl(header->len),
-			       (unsigned long)(walk - inmap) +
-			       ntohl(header->offset));
-		}
-
-		walk += (ntohl(header->len) + ntohl(header->offset)
-			 - 1) & 0xfffffff0;
-	}
-
-	munmap(inmap, statbuf.st_size);
-	close(archivefile);
-
-	if (verbose())
-		printf("done.\n");
-
-	return 0;
-}
Index: LinuxBIOSv3/util/lar/lib.h
===================================================================
--- LinuxBIOSv3.orig/util/lar/lib.h	2007-07-11 11:40:29.000000000 -0600
+++ LinuxBIOSv3/util/lar/lib.h	2007-07-11 11:45:41.000000000 -0600
@@ -62,16 +62,4 @@
 /* prototypes for extract.c functions */
 int extract_lar(const char *archivename, struct file *files);
 
-/* prototypes for list.c functions */
-int list_lar(const char *archivename, struct file *files);
-
-/* prototypes for create.c functions */
-int create_lar(const char *archivename, struct file *files);
-
-/* prototypes for bootblock.c functions */
-extern char *bootblock_code;
-extern int bootblock_len;
-
-int load_bootblock(const char *bootblock);
-int fixup_bootblock(void);
 #endif
Index: LinuxBIOSv3/util/lar/bootblock.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/bootblock.c	2007-07-11 11:40:29.000000000 -0600
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,89 +0,0 @@
-/*
- * lar - LinuxBIOS archiver
- *
- * Copyright (C) 2007 coresystems GmbH
- * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#include "lar.h"
-#include "lib.h"
-
-char *bootblock_code;
-int bootblock_len;
-
-int load_bootblock(const char *bootblock)
-{
-	struct stat statbuf;
-	int ret, filelen;
-	FILE *fh;
-
-	ret = stat(bootblock, &statbuf);
-	if (ret) {
-		fprintf(stderr, "No such file %s\n", bootblock);
-		exit(1);
-	}
-	bootblock_len = statbuf.st_size;
-
-	/* We might want to find additional criteria
-	 * for identifying a bootblock file
-	 */
-	if (bootblock_len != BOOTBLOCK_SIZE) {
-		printf("Warning: %s does not seem to be a bootblock, "
-		       "so ignore it\n", bootblock);
-		bootblock_code = NULL;
-		bootblock_len = 0;
-		// Is this an error condition?
-	}
-
-	bootblock_code = malloc(bootblock_len);
-	if (!bootblock_code) {
-		fprintf(stderr, "Out of memory.\n");
-		exit(1);
-	}
-
-	fh = fopen(bootblock, "r");
-	if (!fh) {
-		fprintf(stderr, "Error while reading file %s\n", bootblock);
-		exit(1);
-	}
-
-	fread(bootblock_code, bootblock_len, 1, fh);
-	fclose(fh);
-
-	return ret;
-}
-
-int fixup_bootblock(void)
-{
-	int i;
-	uint32_t *size_pos;
-
-	/* This cleans out the area after the reset vector */
-	for (i = 13; i > 0; i--)
-		bootblock_code[bootblock_len - i] = '\0';
-
-	/* add lar size to image */
-	size_pos = (uint32_t *) (bootblock_code + bootblock_len - 12);
-	size_pos[0] = get_larsize();
-
-	return 0;
-}
Index: LinuxBIOSv3/util/lar/extract.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/extract.c	2007-07-11 11:40:29.000000000 -0600
+++ /dev/null	1970-01-01 00:00:00.000000000 +0000
@@ -1,155 +0,0 @@
-/*
- * lar - LinuxBIOS archiver
- *
- * Copyright (C) 2006-2007 coresystems GmbH
- * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
- * Copyright (C) 2007 Patrick Georgi <patrick at georgi-clan.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <netinet/in.h>
-
-#include "lib.h"
-#include "lar.h"
-
-void uncompress_impossible(char *dst, char *src, u32 len)
-{
-	fprintf(stderr,
-		"Cannot uncompress data (algorithm not compiled in).\n");
-	exit(1);
-}
-
-void do_no_uncompress(char *dst, char *src, u32 len)
-{
-	memcpy(dst, src, len);
-}
-
-int extract_lar(const char *archivename, struct file *files)
-{
-	int archivefile;
-	char *inmap;
-	char *walk;
-	char *fullname, *pathname, *pos;
-	struct lar_header *header;
-	struct stat statbuf;
-	int archivelen;
-	int do_extract;
-	int i;
-
-	if (stat(archivename, &statbuf) != 0) {
-		printf("Error opening %s: %s\n", archivename, strerror(errno));
-		exit(1);
-	}
-
-	if (verbose())
-		printf("Opening %s\n", archivename);
-
-	archivefile = open(archivename, O_RDONLY);
-	if (archivefile == -1) {
-		printf("Error while opening %s: %s\n",
-		       archivename, strerror(errno));
-		exit(1);
-	}
-	archivelen = statbuf.st_size;
-
-	inmap = mmap(NULL, statbuf.st_size, PROT_READ,
-		     MAP_SHARED, archivefile, 0);
-
-	for (walk = inmap; walk < inmap + statbuf.st_size; walk += 16) {
-		FILE *file_to_extract;
-
-		if (strcmp(walk, MAGIC) != 0)
-			continue;
-
-		header = (struct lar_header *)walk;
-		fullname = walk + sizeof(struct lar_header);
-
-		/* FIXME: check checksum. */
-
-		do_extract = 1;
-		if (files) {
-			struct file *fwalk = files;
-			do_extract = 0;
-			while (fwalk) {
-				if (strcmp(fullname, fwalk->name) == 0) {
-					do_extract = 1;
-					break;
-				}
-				fwalk = fwalk->next;
-			}
-		}
-
-		/* Don't extract this one, skip it. */
-		if (!do_extract)
-			continue;
-
-		if (verbose())
-			printf("  Extracting file %s\n",
-			       walk + sizeof(struct lar_header));
-
-		/* Create the directory if it does not exist. */
-		pathname = strdup(fullname);
-		if (!pathname) {
-			fprintf(stderr, "Out of memory.\n");
-			exit(1);
-		}
-
-		pos = strrchr(pathname, '/');
-		if (pos) {
-			pos[1] = 0;
-			/* printf("Pathname %s\n",pathname); */
-			mkdirp(pathname, 0755);
-		}
-		free(pathname);
-
-		file_to_extract = fopen(fullname, "w");
-		if (!file_to_extract) {
-			fprintf(stderr, "error creating file %s.\n", fullname);
-			exit(1);
-		}
-
-		if (ntohl(header->compression) == none) {
-			fwrite(walk + ntohl(header->offset),
-			       ntohl(header->len), 1, file_to_extract);
-		} else {
-			char *buf = malloc(ntohl(header->reallen));
-			uncompress_functions[ntohl(header->compression)](buf,
-			   walk + ntohl(header->offset), ntohl(header->len));
-			fwrite(buf, ntohl(header->reallen), 1, file_to_extract);
-			free(buf);
-		}
-		fclose(file_to_extract);
-
-		walk += (ntohl(header->offset) + ntohl(header->len)
-			 - 1) & 0xfffffff0;
-	}
-
-	munmap(inmap, statbuf.st_size);
-	close(archivefile);
-
-	if (verbose())
-		printf("done.\n");
-
-	return 0;
-}

From rminnich at gmail.com  Wed Jul 11 20:15:42 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 11 Jul 2007 11:15:42 -0700
Subject: [LinuxBIOS] [PATCH][LAR] Add a top level target for LAR
In-Reply-To: <20070711181204.22915.qmail@stuge.se>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070711181204.22915.qmail@stuge.se>
Message-ID: <13426df10707111115q55ec4ecfk7070c6386a290167@mail.gmail.com>

On 7/11/07, Peter Stuge <peter at stuge.se> wrote:
> On Wed, Jul 11, 2007 at 12:07:47PM -0600, Jordan Crouse wrote:
> > Until LAR gets seperated out into its own repository, I'm going to
> > have to figure out a way to make buildROM build lar independently
> > of the rest of the v3 code, and this is probably the best way.
>
> Sorry, I disagree. :)
>
> I would expect lar to be a target in util/


As Jordan says: "Please keep in mind that these are not set in stone -
I expect heavy
criticism and thought about whats gong on here, and I know you won't let
me down. :)"


Well, *that* didn't take too long :-)

ron



From jordan.crouse at amd.com  Wed Jul 11 20:22:27 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 12:22:27 -0600
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames for create
	and add
Message-ID: <20070711182227.GF20885@cosmic.amd.com>

We we get around to adding blobs to a LAR from within buildROM, we have
an interesting situation, best described with an example.

For Geode we need a VSA blob to operate correctly.  BuildROM wants to
download this blob from a website, and insert it into the the LAR
with a well known name, lets use 'vsa' for giggles.

This patch allows you to specify an arbitrary filename as well as a 
pathname for files in create & add mode in the following manner:

[flags]:[filename]:[pathname]

So instead of copying the  VSA binary into a local directory and renaming
it 'vsa' before adding it o a LAR, instead we use something like this:

./lar -a my.lar ../sources/vsa.bin:vsa

This puts the blob into the LAR, and names it 'vsa'.

(the -a functionality is coming in the next patch).

Jordan
-------------- next part --------------
[PATCH][LAR] Allow user to specify pathnames for create and add

Add another field to the filename specified for create and add operations
to specify the intended pathname for the blob.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Index: LinuxBIOSv3/util/lar/stream.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/stream.c	2007-07-11 11:48:23.000000000 -0600
+++ LinuxBIOSv3/util/lar/stream.c	2007-07-11 11:48:51.000000000 -0600
@@ -436,6 +436,8 @@
 int lar_add_file(struct lar *lar, char *name)
 {
 	char *filename, *ptr, *temp;
+	char *pathname;
+
 	enum compalgo thisalgo;
 	struct lar_header *header;
 	int offset, ret, fd, hlen;
@@ -456,6 +458,18 @@
 		thisalgo = none;
 	}
 
+	pathname = strchr(filename, ':');
+
+	if (pathname != NULL) {
+	  *pathname = '\0';
+	  pathname++;
+
+	  if (!strlen(pathname)) {
+	    err("Invalid pathname specified.\n");
+	    return -1;
+	  }
+	}
+
 	if (filename[0] == '.' && filename[1] == '/')
 		filename += 2;
 
@@ -508,7 +522,7 @@
 	munmap(ptr, s.st_size);
 	close(fd);
 
-	pathlen = strlen(filename) + 1 > MAX_PATHLEN ? MAX_PATHLEN : strlen(filename) + 1;
+	pathlen = strlen(pathname) + 1 > MAX_PATHLEN ? MAX_PATHLEN : strlen(pathname) + 1;
 
 	/* Figure out how big our header will be */
 	hlen = sizeof(struct lar_header) + pathlen;
@@ -535,7 +549,7 @@
 
 	/* Copy the path name */
 	strncpy((char *) (lar->map + offset + sizeof(struct lar_header)),
-		filename, pathlen - 1);
+		pathname, pathlen - 1);
 
 	/* Copy in the data */
 	memcpy(lar->map + (offset + hlen), temp, complen);
Index: LinuxBIOSv3/util/lar/lib.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/lib.c	2007-07-11 11:40:29.000000000 -0600
+++ LinuxBIOSv3/util/lar/lib.c	2007-07-11 11:49:00.000000000 -0600
@@ -148,16 +148,29 @@
 {
 	struct stat filestat;
 	int ret = -1;
-	const char *realname;
+	char *realname;
+	char *c;
+
+	realname = strdup(name);
+
+	if (realname == NULL) {
+	  fprintf(stderr, "Out of memory.\n");
+	  exit(1);
+	}
 
-	realname = name;
 	if (strstr(name, "nocompress:") == name) {
-		realname = name + 11;
+		realname += 11;
 	}
 
+	c = strchr(realname, ':');
+
+	if (c != NULL)
+	  *c = '\0';
+
 	/* printf("... add_files %s\n", name); */
 	if (stat(realname, &filestat) == -1) {
 		fprintf(stderr, "Error getting file attributes of %s\n", name);
+		free(realname);
 		return -1;
 	}
 
@@ -202,6 +215,7 @@
 		ret = 0;
 	}
 
+	free(realname);
 	return ret;
 }
 

From joe at smittys.pointclark.net  Wed Jul 11 20:24:26 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Wed, 11 Jul 2007 14:24:26 -0400
Subject: [LinuxBIOS] DIMM Page Size
In-Reply-To: <030101c7c3cb$714dccd0$184e040a@chimp>
References: <20070711043632.ugnomx5j4wg8ggw4@www.smittys.pointclark.net><4E7A3EDF-B1C5-4C51-A9FB-495F0B4CFDC4@kernel.crashing.org><20070711094100.pt4t4pyrfac0og8s@www.smittys.pointclark.net>
	<030001c7c3ca$cef0b4c0$184e040a@chimp>
	<030101c7c3cb$714dccd0$184e040a@chimp>
Message-ID: <20070711142426.56mxz9oao0k8wggk@www.smittys.pointclark.net>

Quoting Myles Watson <myles at pel.cs.byu.edu>:

>
>
>> > col = 9 /* SPD byte 4: Number of Column Addresses */
>> > bus_width = 64 /* SPD byte 6: Data Width of Assembly */
>> >
>> > page_size = (2^col)*bus_width
>>
>> 2^9 = 512
>>
>> > 5184 = 81 * 64
>>
>> 512 * 64 = 32K
>>
>> Myles
>
> Sorry, that should have been 32K bits, since you are multiplying by 64 bits.
> Then dividing by 8 bits/byte = 4 KB.
>
> Myles
>
>>
>> >
>> > Which is not correct because the DIMM has a 4k page size.
>> > (According to it's datasheet).
>
>
>
>
Your right, Duh I was doing 9^2 = 81 :-)

col = 9 /* SPD byte 4: Number of Column Addresses */
bus_width = 64 /* SPD byte 6: Data Width of Assembly */

bit_page_size = ((2^col) * bus_width)

*/ convert to KB */
page_size = ((bit_page_size / 8) >> 10)

= 4KB

Sweet, this is a much easier way to calculate the DRA ? DRAM Row  
Attribute Register!! One last question, A normal SDRAM DIMM should  
always have SPD byte 6 = 64 and ECC should have SPD byte 6 = 72. Is  
this correct??

Thanks for all the help - Joe



From uwe at hermann-uwe.de  Wed Jul 11 20:24:26 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 11 Jul 2007 20:24:26 +0200
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Simplify geodelx_msr_init() and
	fix a bug (?)
Message-ID: <20070711182426.GA8025@greenwood>

See patch.

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
-------------- next part --------------
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From jordan.crouse at amd.com  Wed Jul 11 20:26:16 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 12:26:16 -0600
Subject: [LinuxBIOS] [PATCH][LAR] Allow human friendly suffixes for the size
	option
Message-ID: <20070711182616.GH20885@cosmic.amd.com>

Last one. :)  This one doesn't follow with any of the previous patches,
but its fun. This allows a modifier suffix on the end of the -s [size]
option to make it more human friendly.  So now instead of -s 32768,
you can use -s 32k instead.   Both 'k' (size * 1024) and 'm' (size * 1024 *
1024) are supported.

Jordan
-------------- next part --------------
[PATCH][LAR]  Allow human friendly suffixes for the size option

Enable 'k' and 'm' suffixes to modify the size in a human friendly
way - s 32k is much easier on the brain then -s 32768.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Index: LinuxBIOSv3/util/lar/lar.c
===================================================================
--- LinuxBIOSv3.orig/util/lar/lar.c	2007-07-11 11:51:57.000000000 -0600
+++ LinuxBIOSv3/util/lar/lar.c	2007-07-11 11:52:01.000000000 -0600
@@ -46,7 +46,7 @@
 	printf("\nLAR - the LinuxBIOS Archiver " VERSION "\n" COPYRIGHT "\n\n"
 	       "Usage: %s [-cxal] archive.lar [[[file1] file2] ...]\n\n", name);
 	printf("Examples:\n");
-	printf("  lar -c -s 32768 -b bootblock myrom.lar foo nocompress:bar\n");
+	printf("  lar -c -s 32k -b bootblock myrom.lar foo nocompress:bar\n");
 	printf("  lar -a myrom.lar foo blob:baz\n");
 	printf("  lar -l myrom.lar\n\n");
 
@@ -61,7 +61,9 @@
 	printf("     * Pathname is the name to use in the LAR header.\n\n");
 
 	printf("Create options:\n");
-	printf("  -s [size]\tSpecify the size of the archive (in bytes)\n");
+	printf("  -s [size]     \tSpecify the size of the archive.\n");
+	printf("                \tUse a 'k' suffix to multiply the size by 1K or\n");
+	printf("                \ta 'm' suffix to multiple the size by 1M.\n");
 	printf("  -b [bootblock]\tSpecify the bootblock blob\n");
 	printf("  -C [lzma|nrv2b]\tSpecify the compression method to use\n\n");
 
@@ -73,6 +75,29 @@
 
 }
 
+/* Add a human touch to the LAR size by allowing suffixes:
+   XX[KkMm] where k = XX * 1024 and m or M = xx * 1024 * 1024
+*/
+
+static void parse_larsize(char *str)
+{
+  char *p = NULL;
+  unsigned int size = strtoul(str, &p, 0);
+
+  if (p != NULL) {
+    if (*p == 'k' || *p == 'K')
+      size *= 1024;
+    else if (*p == 'm' || *p == 'M')
+      size *= (1024 * 1024);
+    else {
+      fprintf(stderr, "Unknown LAR size suffix %c\n", *p);
+      exit(1);
+    }
+  }
+
+  larsize = size;
+}
+
 int verbose(void)
 {
 	return isverbose;
@@ -219,7 +244,7 @@
 			larmode = EXTRACT;
 			break;
 		case 's':
-			larsize = strtol(optarg, (char **)NULL, 10);
+			parse_larsize(optarg);
 			break;
 		case 'b':
 			bootblock = strdup(optarg);

From rminnich at gmail.com  Wed Jul 11 20:26:35 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 11 Jul 2007 11:26:35 -0700
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Simplify geodelx_msr_init()
	and fix a bug (?)
In-Reply-To: <20070711182426.GA8025@greenwood>
References: <20070711182426.GA8025@greenwood>
Message-ID: <13426df10707111126h57e2ce2ava2bc2af978629900@mail.gmail.com>

Excellent patch, I think we'd better let the AMD guys ack it, since I
sometimes miss important details. But I like it.

ron

On 7/11/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> See patch.
>
> Uwe.
> --
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
>
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.6 (GNU/Linux)
>
> iD8DBQFGlSBaXdVoV3jWIbQRAoEMAJ9ICj0tshjxo4ugMJJwmNeuAHci1wCgnofU
> gYBjfsERQwOHu5XWwhcfhwM=
> =uiFw
> -----END PGP SIGNATURE-----
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>
>



From rminnich at gmail.com  Wed Jul 11 20:27:53 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 11 Jul 2007 11:27:53 -0700
Subject: [LinuxBIOS] [PATCH][LAR] Allow human friendly suffixes for the
	size option
In-Reply-To: <20070711182616.GH20885@cosmic.amd.com>
References: <20070711182616.GH20885@cosmic.amd.com>
Message-ID: <13426df10707111127l547a2b01k7615a959b412622a@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>


On 7/11/07, Jordan Crouse <jordan.crouse at amd.com> wrote:
> Last one. :)  This one doesn't follow with any of the previous patches,
> but its fun. This allows a modifier suffix on the end of the -s [size]
> option to make it more human friendly.  So now instead of -s 32768,
> you can use -s 32k instead.   Both 'k' (size * 1024) and 'm' (size * 1024 *
> 1024) are supported.
>
> Jordan
>
> [PATCH][LAR]  Allow human friendly suffixes for the size option
>
> Enable 'k' and 'm' suffixes to modify the size in a human friendly
> way - s 32k is much easier on the brain then -s 32768.
>
> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
> Index: LinuxBIOSv3/util/lar/lar.c
> ===================================================================
> --- LinuxBIOSv3.orig/util/lar/lar.c     2007-07-11 11:51:57.000000000 -0600
> +++ LinuxBIOSv3/util/lar/lar.c  2007-07-11 11:52:01.000000000 -0600
> @@ -46,7 +46,7 @@
>         printf("\nLAR - the LinuxBIOS Archiver " VERSION "\n" COPYRIGHT "\n\n"
>                "Usage: %s [-cxal] archive.lar [[[file1] file2] ...]\n\n", name);
>         printf("Examples:\n");
> -       printf("  lar -c -s 32768 -b bootblock myrom.lar foo nocompress:bar\n");
> +       printf("  lar -c -s 32k -b bootblock myrom.lar foo nocompress:bar\n");
>         printf("  lar -a myrom.lar foo blob:baz\n");
>         printf("  lar -l myrom.lar\n\n");
>
> @@ -61,7 +61,9 @@
>         printf("     * Pathname is the name to use in the LAR header.\n\n");
>
>         printf("Create options:\n");
> -       printf("  -s [size]\tSpecify the size of the archive (in bytes)\n");
> +       printf("  -s [size]     \tSpecify the size of the archive.\n");
> +       printf("                \tUse a 'k' suffix to multiply the size by 1K or\n");
> +       printf("                \ta 'm' suffix to multiple the size by 1M.\n");
>         printf("  -b [bootblock]\tSpecify the bootblock blob\n");
>         printf("  -C [lzma|nrv2b]\tSpecify the compression method to use\n\n");
>
> @@ -73,6 +75,29 @@
>
>  }
>
> +/* Add a human touch to the LAR size by allowing suffixes:
> +   XX[KkMm] where k = XX * 1024 and m or M = xx * 1024 * 1024
> +*/
> +
> +static void parse_larsize(char *str)
> +{
> +  char *p = NULL;
> +  unsigned int size = strtoul(str, &p, 0);
> +
> +  if (p != NULL) {
> +    if (*p == 'k' || *p == 'K')
> +      size *= 1024;
> +    else if (*p == 'm' || *p == 'M')
> +      size *= (1024 * 1024);
> +    else {
> +      fprintf(stderr, "Unknown LAR size suffix %c\n", *p);
> +      exit(1);
> +    }
> +  }
> +
> +  larsize = size;
> +}
> +
>  int verbose(void)
>  {
>         return isverbose;
> @@ -219,7 +244,7 @@
>                         larmode = EXTRACT;
>                         break;
>                 case 's':
> -                       larsize = strtol(optarg, (char **)NULL, 10);
> +                       parse_larsize(optarg);
>                         break;
>                 case 'b':
>                         bootblock = strdup(optarg);
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>



From jordan.crouse at amd.com  Wed Jul 11 20:30:09 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 12:30:09 -0600
Subject: [LinuxBIOS] Add a top level target for LAR
In-Reply-To: <20070711181204.22915.qmail@stuge.se>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070711181204.22915.qmail@stuge.se>
Message-ID: <20070711183009.GI20885@cosmic.amd.com>

On 11/07/07 20:12 +0200, Peter Stuge wrote:
> On Wed, Jul 11, 2007 at 12:07:47PM -0600, Jordan Crouse wrote:
> > Until LAR gets seperated out into its own repository, I'm going to
> > have to figure out a way to make buildROM build lar independently
> > of the rest of the v3 code, and this is probably the best way.
> 
> Sorry, I disagree. :)
> 
> I would expect lar to be a target in util/

I agree.  But as its written right now, the makefiles depend on
the rules in the toplevel directory - so no matter where we define
the target, it can only be called from the toplevel.

Now, if we moved the rules to a seperate rules file, and included _that_
from util/, then I'm with you... :)

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From rminnich at gmail.com  Wed Jul 11 20:44:26 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 11 Jul 2007 11:44:26 -0700
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames for
	create and add
In-Reply-To: <20070711182227.GF20885@cosmic.amd.com>
References: <20070711182227.GF20885@cosmic.amd.com>
Message-ID: <13426df10707111144r216494b5ga7b1e24a186732a4@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnnich at gmail.com>

On 7/11/07, Jordan Crouse <jordan.crouse at amd.com> wrote:
> We we get around to adding blobs to a LAR from within buildROM, we have
> an interesting situation, best described with an example.
>
> For Geode we need a VSA blob to operate correctly.  BuildROM wants to
> download this blob from a website, and insert it into the the LAR
> with a well known name, lets use 'vsa' for giggles.
>
> This patch allows you to specify an arbitrary filename as well as a
> pathname for files in create & add mode in the following manner:
>
> [flags]:[filename]:[pathname]
>
> So instead of copying the  VSA binary into a local directory and renaming
> it 'vsa' before adding it o a LAR, instead we use something like this:
>
> ./lar -a my.lar ../sources/vsa.bin:vsa
>
> This puts the blob into the LAR, and names it 'vsa'.
>
> (the -a functionality is coming in the next patch).
>
> Jordan
>
> [PATCH][LAR] Allow user to specify pathnames for create and add
>
> Add another field to the filename specified for create and add operations
> to specify the intended pathname for the blob.
>
> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
> Index: LinuxBIOSv3/util/lar/stream.c
> ===================================================================
> --- LinuxBIOSv3.orig/util/lar/stream.c  2007-07-11 11:48:23.000000000 -0600
> +++ LinuxBIOSv3/util/lar/stream.c       2007-07-11 11:48:51.000000000 -0600
> @@ -436,6 +436,8 @@
>  int lar_add_file(struct lar *lar, char *name)
>  {
>         char *filename, *ptr, *temp;
> +       char *pathname;
> +
>         enum compalgo thisalgo;
>         struct lar_header *header;
>         int offset, ret, fd, hlen;
> @@ -456,6 +458,18 @@
>                 thisalgo = none;
>         }
>
> +       pathname = strchr(filename, ':');
> +
> +       if (pathname != NULL) {
> +         *pathname = '\0';
> +         pathname++;
> +
> +         if (!strlen(pathname)) {
> +           err("Invalid pathname specified.\n");
> +           return -1;
> +         }
> +       }
> +
>         if (filename[0] == '.' && filename[1] == '/')
>                 filename += 2;
>
> @@ -508,7 +522,7 @@
>         munmap(ptr, s.st_size);
>         close(fd);
>
> -       pathlen = strlen(filename) + 1 > MAX_PATHLEN ? MAX_PATHLEN : strlen(filename) + 1;
> +       pathlen = strlen(pathname) + 1 > MAX_PATHLEN ? MAX_PATHLEN : strlen(pathname) + 1;
>
>         /* Figure out how big our header will be */
>         hlen = sizeof(struct lar_header) + pathlen;
> @@ -535,7 +549,7 @@
>
>         /* Copy the path name */
>         strncpy((char *) (lar->map + offset + sizeof(struct lar_header)),
> -               filename, pathlen - 1);
> +               pathname, pathlen - 1);
>
>         /* Copy in the data */
>         memcpy(lar->map + (offset + hlen), temp, complen);
> Index: LinuxBIOSv3/util/lar/lib.c
> ===================================================================
> --- LinuxBIOSv3.orig/util/lar/lib.c     2007-07-11 11:40:29.000000000 -0600
> +++ LinuxBIOSv3/util/lar/lib.c  2007-07-11 11:49:00.000000000 -0600
> @@ -148,16 +148,29 @@
>  {
>         struct stat filestat;
>         int ret = -1;
> -       const char *realname;
> +       char *realname;
> +       char *c;
> +
> +       realname = strdup(name);
> +
> +       if (realname == NULL) {
> +         fprintf(stderr, "Out of memory.\n");
> +         exit(1);
> +       }
>
> -       realname = name;
>         if (strstr(name, "nocompress:") == name) {
> -               realname = name + 11;
> +               realname += 11;
>         }
>
> +       c = strchr(realname, ':');
> +
> +       if (c != NULL)
> +         *c = '\0';
> +
>         /* printf("... add_files %s\n", name); */
>         if (stat(realname, &filestat) == -1) {
>                 fprintf(stderr, "Error getting file attributes of %s\n", name);
> +               free(realname);
>                 return -1;
>         }
>
> @@ -202,6 +215,7 @@
>                 ret = 0;
>         }
>
> +       free(realname);
>         return ret;
>  }
>
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>



From Marc.Jones at amd.com  Wed Jul 11 20:47:47 2007
From: Marc.Jones at amd.com (Marc Jones)
Date: Wed, 11 Jul 2007 12:47:47 -0600
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Simplify geodelx_msr_init()
 and fix a bug (?)
In-Reply-To: <20070711182426.GA8025@greenwood>
References: <20070711182426.GA8025@greenwood>
Message-ID: <469525D3.7000002@AMD.com>

More good stuff!
Acked-by: Marc Jones <marc.jones at amd.com>

Uwe Hermann wrote:

>See patch.
>
>Uwe.
>  
>
>------------------------------------------------------------------------
>
>Simplify the geodelx_msr_init() function by looping over a table.
>
>Also, drop all copyright lines except (C) 2007 AMD, as this code is
>a straight copy of msr_init() in the v2 Norwich target, and that file
>only contains the (C) 2007 AMD line.
>
>Finally, I think this patch also fixes a (copy+paste) bug, the MSRs
>written should not be
>   MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU1_BASE1, MSR_GLIU0_BASE2
>but rather
>   MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU1_BASE1, MSR_GLIU1_BASE2
>(note MSR_GLIU0_BASE2 vs. MSR_GLIU1_BASE2)
>
>Untested on real hardware, of course.
>
>Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
>
>Index: stage1.c
>===================================================================
>--- stage1.c	(Revision 444)
>+++ stage1.c	(Arbeitskopie)
>@@ -1,8 +1,6 @@
> /*
>  * This file is part of the LinuxBIOS project.
>  *
>- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa at artecdesign.ee>
>- * Copyright (C) 2006 Ronald G. Minnich <rminnich at gmail.com>
>  * Copyright (C) 2007 Advanced Micro Devices, Inc.
>  *
>  * This program is free software; you can redistribute it and/or modify
>@@ -31,42 +29,33 @@
> #include <amd_geodelx.h>
> #include <spd.h>
> 
>+static struct msrinit {
>+	u32 msrnum;
>+	struct msr msr;
>+} msr_table[] = {
>+  /* Setup access to the cache for under 1MB. */
>+  {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, // 0x00000-0xA0000
>+  {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, // 0xA0000-0xBFFFF
>+  {CPU_RCONF_C0_DF,   {.hi = 0x00000000,.lo = 0x00000000}}, // 0xC0000-0xDFFFF
>+  {CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, // 0xE0000-0xFFFFF
>+
>+  /* Setup access to the cache for under 640KB. */
>+  {MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
>+  {MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
>+  {MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
>+  {MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
>+};
>+
> /**
>  * Set up Geode LX registers for sane behaviour.
>  *
>- * Set all low memory (under 1MB) to write back. Do some setup for Cache
>- * as Ram (CAR) as well.
>+ * Set all low memory (under 1MB) to write-back cacheable. Do some setup for
>+ * Cache-as-RAM (CAR) as well. Note: The memory controller is not set up, yet.
>  */
> void geodelx_msr_init(void)
> {
>-	struct msr msr;
>+	int i;
> 
>-	/* Setup access to the cache for under 1MB. */
>-	msr.hi = 0x24fffc02;
>-	msr.lo = 0x1000A000;	/* 0-A0000 write back */
>-	wrmsr(CPU_RCONF_DEFAULT, msr);
>-
>-	msr.hi = 0x0;		/* write back */
>-	msr.lo = 0x0;
>-	wrmsr(CPU_RCONF_A0_BF, msr);
>-	wrmsr(CPU_RCONF_C0_DF, msr);
>-	wrmsr(CPU_RCONF_E0_FF, msr);
>-
>-	/* Setup access to the cache for under 640K. */
>-	/* Note: Memory controller not setup yet. */
>-	msr.hi = 0x20000000;
>-	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
>-	wrmsr(MSR_GLIU0_BASE1, msr);
>-
>-	msr.hi = 0x20000000;
>-	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
>-	wrmsr(MSR_GLIU0_BASE2, msr);
>-
>-	msr.hi = 0x20000000;
>-	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
>-	wrmsr(MSR_GLIU1_BASE1, msr);
>-
>-	msr.hi = 0x20000000;
>-	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
>-	wrmsr(MSR_GLIU0_BASE2, msr);
>+	for (i = 0; i < ARRAY_SIZE(msr_table); i++)
>+		wrmsr(msr_table[i].msrnum, msr_table[i].msr);
> }
>  
>






From uwe at hermann-uwe.de  Wed Jul 11 21:37:23 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 11 Jul 2007 21:37:23 +0200
Subject: [LinuxBIOS] [PATCH][LAR] Allow human friendly suffixes for
	the	size option
In-Reply-To: <13426df10707111127l547a2b01k7615a959b412622a@mail.gmail.com>
References: <20070711182616.GH20885@cosmic.amd.com>
	<13426df10707111127l547a2b01k7615a959b412622a@mail.gmail.com>
Message-ID: <20070711193723.GB8025@greenwood>

On Wed, Jul 11, 2007 at 11:27:53AM -0700, ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Yep,

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

But some small issues:


> > +/* Add a human touch to the LAR size by allowing suffixes:
> > +   XX[KkMm] where k = XX * 1024 and m or M = xx * 1024 * 1024
> > +*/

/* Add a human touch to the LAR size by allowing suffixes:
 * XX[KkMm] where k = XX * 1024 and m or M = xx * 1024 * 1024
 */


> > +
> > +static void parse_larsize(char *str)

static void parse_larsize(const char *str)


> > +{
> > +  char *p = NULL;
> > +  unsigned int size = strtoul(str, &p, 0);
> > +
> > +  if (p != NULL) {
> > +    if (*p == 'k' || *p == 'K')
> > +      size *= 1024;
> > +    else if (*p == 'm' || *p == 'M')
> > +      size *= (1024 * 1024);
> > +    else {
> > +      fprintf(stderr, "Unknown LAR size suffix %c\n", *p);
> > +      exit(1);
> > +    }
> > +  }
> > +
> > +  larsize = size;
> > +}

Please fix the coding style (TABs instead of spaces, for example).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Wed Jul 11 21:42:21 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 11 Jul 2007 21:42:21 +0200
Subject: [LinuxBIOS] r445 - LinuxBIOSv3/arch/x86/geodelx
Message-ID: <mailman.511.1355071132.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-11 21:42:21 +0200 (Wed, 11 Jul 2007)
New Revision: 445

Modified:
   LinuxBIOSv3/arch/x86/geodelx/stage1.c
Log:
Simplify the geodelx_msr_init() function by looping over a table.

Also, drop all copyright lines except (C) 2007 AMD, as this code is
a straight copy of msr_init() in the v2 Norwich target, and that file
only contains the (C) 2007 AMD line.

Finally, I think this patch also fixes a (copy+paste) bug, the MSRs
written should not be
   MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU1_BASE1, MSR_GLIU0_BASE2
but rather
   MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU1_BASE1, MSR_GLIU1_BASE2
(note MSR_GLIU0_BASE2 vs. MSR_GLIU1_BASE2)

Untested on real hardware, of course.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Marc Jones <marc.jones at amd.com>



Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-10 20:26:32 UTC (rev 444)
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-11 19:42:21 UTC (rev 445)
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa at artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich at gmail.com>
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -31,42 +29,33 @@
 #include <amd_geodelx.h>
 #include <spd.h>
 
+static struct msrinit {
+	u32 msrnum;
+	struct msr msr;
+} msr_table[] = {
+  /* Setup access to the cache for under 1MB. */
+  {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, // 0x00000-0xA0000
+  {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, // 0xA0000-0xBFFFF
+  {CPU_RCONF_C0_DF,   {.hi = 0x00000000,.lo = 0x00000000}}, // 0xC0000-0xDFFFF
+  {CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, // 0xE0000-0xFFFFF
+
+  /* Setup access to the cache for under 640KB. */
+  {MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
+  {MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
+  {MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
+  {MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
+};
+
 /**
  * Set up Geode LX registers for sane behaviour.
  *
- * Set all low memory (under 1MB) to write back. Do some setup for Cache
- * as Ram (CAR) as well.
+ * Set all low memory (under 1MB) to write-back cacheable. Do some setup for
+ * Cache-as-RAM (CAR) as well. Note: The memory controller is not set up, yet.
  */
 void geodelx_msr_init(void)
 {
-	struct msr msr;
+	int i;
 
-	/* Setup access to the cache for under 1MB. */
-	msr.hi = 0x24fffc02;
-	msr.lo = 0x1000A000;	/* 0-A0000 write back */
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	msr.hi = 0x0;		/* write back */
-	msr.lo = 0x0;
-	wrmsr(CPU_RCONF_A0_BF, msr);
-	wrmsr(CPU_RCONF_C0_DF, msr);
-	wrmsr(CPU_RCONF_E0_FF, msr);
-
-	/* Setup access to the cache for under 640K. */
-	/* Note: Memory controller not setup yet. */
-	msr.hi = 0x20000000;
-	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
-	wrmsr(MSR_GLIU0_BASE1, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
-	wrmsr(MSR_GLIU0_BASE2, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
-	wrmsr(MSR_GLIU1_BASE1, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
-	wrmsr(MSR_GLIU0_BASE2, msr);
+	for (i = 0; i < ARRAY_SIZE(msr_table); i++)
+		wrmsr(msr_table[i].msrnum, msr_table[i].msr);
 }




From svn at openbios.org  Wed Jul 11 21:47:36 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed, 11 Jul 2007 21:47:36 +0200
Subject: [LinuxBIOS] r446 - LinuxBIOSv3/northbridge/amd/geodelx
Message-ID: <mailman.512.1355071132.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-11 21:47:36 +0200 (Wed, 11 Jul 2007)
New Revision: 446

Modified:
   LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
Log:
Simplify the Geode LX RAM init code a bit by using (inline'd) helper
functions. Untested on real hardware, but it still compiles.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Marc Jones <marc.jones at amd.com>



Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-11 19:42:21 UTC (rev 445)
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-11 19:47:36 UTC (rev 446)
@@ -362,6 +362,27 @@
 	wrmsr(MC_CF8F_DATA, msr);
 }
 
+static inline void helper_spd(u8 dimm0, u8 dimm1, u8 addr, u8 *spd0, u8 *spd1)
+{
+	*spd0 = smbus_read_byte(dimm0, addr);
+	if (*spd0 == 0xFF)
+		*spd0 = 0;
+	*spd1 = smbus_read_byte(dimm1, addr);
+	if (*spd1 == 0xFF)
+		*spd1 = 0;
+	if (*spd0 < *spd1)
+		*spd0 = *spd1;
+}
+
+static inline void helper_calc(u8 *spd0, u8 *spd1, u32 memspeed)
+{
+	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	*spd1 = ((*spd0 >> 2) * memspeed) / 1000;
+	if ((((*spd0 >> 2) * memspeed) % 1000)) {
+		++(*spd1);
+	}
+}
+
 /**
  * Set latencies for DRAM.
  *
@@ -382,70 +403,27 @@
 
 	/* MC_CF8F setup */
 	/* tRAS */
-	spd_byte0 = smbus_read_byte(dimm0, SPD_tRAS);
-	if (spd_byte0 == 0xFF)
-		spd_byte0 = 0;
-	spd_byte1 = smbus_read_byte(dimm1, SPD_tRAS);
-	if (spd_byte1 == 0xFF)
-		spd_byte1 = 0;
-	if (spd_byte0 < spd_byte1)
-		spd_byte0 = spd_byte1;
-
+	helper_spd(dimm0, dimm1, SPD_tRAS, &spd_byte0, &spd_byte1);
 	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	/* TODO: This calculation is a bit different. On purpose or bug? */
 	spd_byte1 = (spd_byte0 * memspeed) / 1000;
 	if (((spd_byte0 * memspeed) % 1000))
 		++spd_byte1;
 	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
 
 	/* tRP */
-	spd_byte0 = smbus_read_byte(dimm0, SPD_tRP);
-	if (spd_byte0 == 0xFF)
-		spd_byte0 = 0;
-	spd_byte1 = smbus_read_byte(dimm1, SPD_tRP);
-	if (spd_byte1 == 0xFF)
-		spd_byte1 = 0;
-	if (spd_byte0 < spd_byte1)
-		spd_byte0 = spd_byte1;
-
-	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
-	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
-	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
-		++spd_byte1;
-	}
+	helper_spd(dimm0, dimm1, SPD_tRP, &spd_byte0, &spd_byte1);
+	helper_calc(&spd_byte0, &spd_byte1, memspeed);
 	dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
 
 	/* tRCD */
-	spd_byte0 = smbus_read_byte(dimm0, SPD_tRCD);
-	if (spd_byte0 == 0xFF)
-		spd_byte0 = 0;
-	spd_byte1 = smbus_read_byte(dimm1, SPD_tRCD);
-	if (spd_byte1 == 0xFF)
-		spd_byte1 = 0;
-	if (spd_byte0 < spd_byte1)
-		spd_byte0 = spd_byte1;
-
-	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
-	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
-	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
-		++spd_byte1;
-	}
+	helper_spd(dimm0, dimm1, SPD_tRCD, &spd_byte0, &spd_byte1);
+	helper_calc(&spd_byte0, &spd_byte1, memspeed);
 	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
 
 	/* tRRD */
-	spd_byte0 = smbus_read_byte(dimm0, SPD_tRRD);
-	if (spd_byte0 == 0xFF)
-		spd_byte0 = 0;
-	spd_byte1 = smbus_read_byte(dimm1, SPD_tRRD);
-	if (spd_byte1 == 0xFF)
-		spd_byte1 = 0;
-	if (spd_byte0 < spd_byte1)
-		spd_byte0 = spd_byte1;
-
-	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
-	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
-	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
-		++spd_byte1;
-	}
+	helper_spd(dimm0, dimm1, SPD_tRRD, &spd_byte0, &spd_byte1);
+	helper_calc(&spd_byte0, &spd_byte1, memspeed);
 	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
 
 	/* tRC = tRP + tRAS */
@@ -461,14 +439,7 @@
 
 	/* MC_CF1017 setup */
 	/* tRFC */
-	spd_byte0 = smbus_read_byte(dimm0, SPD_tRFC);
-	if (spd_byte0 == 0xFF)
-		spd_byte0 = 0;
-	spd_byte1 = smbus_read_byte(dimm1, SPD_tRFC);
-	if (spd_byte1 == 0xFF)
-		spd_byte1 = 0;
-	if (spd_byte0 < spd_byte1)
-		spd_byte0 = spd_byte1;
+	helper_spd(dimm0, dimm1, SPD_tRFC, &spd_byte0, &spd_byte1);
 
 	if (spd_byte0) {
 		/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */




From uwe at hermann-uwe.de  Wed Jul 11 21:49:17 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 11 Jul 2007 21:49:17 +0200
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Simplify RAM init code a bit
In-Reply-To: <4694085F.8020307@amd.com>
References: <20070710201936.GD12003@greenwood> <4694085F.8020307@amd.com>
Message-ID: <20070711194917.GC8025@greenwood>

On Tue, Jul 10, 2007 at 04:29:51PM -0600, Marc Jones wrote:
> I can't test it yet either but it builds and looks correct to me. (I'm 
> almost into memory init with V3.)
>
> Acked-by: Marc Jones <marc.jones at amd.com>

r446, thanks!


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Wed Jul 11 21:50:48 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 11 Jul 2007 21:50:48 +0200
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Simplify
	geodelx_msr_init()	and fix a bug (?)
In-Reply-To: <469525D3.7000002@AMD.com>
References: <20070711182426.GA8025@greenwood> <469525D3.7000002@AMD.com>
Message-ID: <20070711195048.GD8025@greenwood>

On Wed, Jul 11, 2007 at 12:47:47PM -0600, Marc Jones wrote:
> More good stuff!
> Acked-by: Marc Jones <marc.jones at amd.com>

r445.


>> -	msr.hi = 0x20000000;
>> -	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
>> -	wrmsr(MSR_GLIU0_BASE2, msr);
>> -
>> -	msr.hi = 0x20000000;
>> -	msr.lo = 0x000fff80;	/* 0-0x7FFFF */
>> -	wrmsr(MSR_GLIU1_BASE1, msr);
>> -
>> -	msr.hi = 0x20000000;
>> -	msr.lo = 0x080fffe0;	/* 0x80000-0x9FFFF */
>> -	wrmsr(MSR_GLIU0_BASE2, msr);

Can you confirm that this should have been MSR_GLIU1_BASE2
(not MSR_GLIU0_BASE2)?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Wed Jul 11 22:20:29 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 11 Jul 2007 22:20:29 +0200
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Remove useless includes
Message-ID: <20070711202029.GE8025@greenwood>

See patch.

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Wed Jul 11 22:24:52 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 11 Jul 2007 22:24:52 +0200
Subject: [LinuxBIOS] [PATCH][v3] Move lar into global util/ directory +
	svn:externals
Message-ID: <20070711202452.GF8025@greenwood>

OK, not really a patch, but I think we can move lar into the global
util/ directory and suck it into v3 via svn:externals.

That's a first step to make it independent of v3 (and to allow Jordan
to use it in buildrom).

I'm waiting for comments or ACKs before doing this, though.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From jordan.crouse at amd.com  Wed Jul 11 22:33:14 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 14:33:14 -0600
Subject: [LinuxBIOS] Move lar into global util/ directory + svn:externals
In-Reply-To: <20070711202452.GF8025@greenwood>
References: <20070711202452.GF8025@greenwood>
Message-ID: <20070711203314.GJ20885@cosmic.amd.com>

On 11/07/07 22:24 +0200, Uwe Hermann wrote:
> OK, not really a patch, but I think we can move lar into the global
> util/ directory and suck it into v3 via svn:externals.
> 
> That's a first step to make it independent of v3 (and to allow Jordan
> to use it in buildrom).

> I'm waiting for comments or ACKs before doing this, though.

No argument here... :)

> 
> 
> Uwe.
> -- 
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From peter at stuge.se  Thu Jul 12 00:11:33 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 00:11:33 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <20070711181517.GD20885@cosmic.amd.com>
References: <20070711181517.GD20885@cosmic.amd.com>
Message-ID: <20070711221134.27245.qmail@stuge.se>

First some general discussion. More concrete patch comments will
follow.


On Wed, Jul 11, 2007 at 12:15:17PM -0600, Jordan Crouse wrote:
> This has the slight side effect of requiring that the user specify
> a size for the LAR when they create it, but I don't think thats
> really a bad thing.
> 
> One thing you might miss is that I've turned the path name of the
> bootblock into a constant name 'bootblock'.

Some ideas have been tossed around;

1. teach lar about flash chip sector sizes
2. bootblock at top or at bottom


1 means combining flashrom and lar somehow.. Thoughts?

Unfortunately this isn't as easy as a straight modulus operation
because not all flash chips have uniform sector sizes across the
entire chip.

The only way I can see it working is to create a lar for a flash chip
rather than for a size. The flash chip id could be at the end of the
lar (we have a few bytes left right?) and lars could also be generic,
ie. not yet adapted to any chip. This generic lar is what we do right
now, with a fixed 8k-or-so sector size and a fixed total size.

We would also want a flag for each file indicating whether it can be
moved or if it must remain at it's current offset. This flag limits
which lar files can be reflashed independently by flashrom.

And we'd need to add some lar knowledge to flashrom, but only enough
to pick files out of lars.


2 depends on the target architecture. If we can autodetect we should
not make it an option, just stick with assuming top for now and fix
when it's needed.


> It also requires that the user specify a size when the LAR is
> created.

So we're approaching the flash chip. Can we do something more clever
than just specify the size already? I'm not sure. I think a fixed
size is fine for now.


//Peter



From peter at stuge.se  Thu Jul 12 00:49:20 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 00:49:20 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <20070711181517.GD20885@cosmic.amd.com>
References: <20070711181517.GD20885@cosmic.amd.com>
Message-ID: <20070711224920.761.qmail@stuge.se>

Really good ideas! But some comments on implementation..


On Wed, Jul 11, 2007 at 12:15:17PM -0600, Jordan Crouse wrote:
> +struct lar {
> +	int fd;
> +	unsigned char *map;
> +	int size;
> +};

u32 size maybe?


> +static inline int get_bootblock_offset(int size)
> +{
> +	return size - (BOOTBLOCK_SIZE + sizeof(struct lar_header) + BOOTBLOCK_NAME_LEN);
> +}

Same here, u32 for sizes.


> +static int lar_read_size(struct lar *lar, int filelen)
> +{
> +	unsigned int *ptr = (unsigned int *) (lar->map + (filelen - 12));
> +	return ptr[0];
> +}

What about all this pointer arithmetic? Is it really correct?

Doesn't adding 1 to a pointer actually add sizeof pointed-to-type to
the address? Ie. this code isn't portable?


> +static void annotate_bootblock(unsigned char *ptr, unsigned int size)
> +{
> +	int i;
> +	unsigned int *p;
> +
> +	for(i = 13; i > 0; i--)
> +		ptr[BOOTBLOCK_SIZE - i] = '\0';

I think a memset() call here would be nicer..


> +	p = (unsigned int *) (ptr + BOOTBLOCK_SIZE - 12);
> +	p[0] = size;
> +}

Then there's the matter of the pointer arithmetic again. Since ptr is
uchar * this will work, but then writing size to p[0] will write a
different number of bytes on different archs, right?


> + err:
> +	if (lar->fd >= 0)
> +		close(lar->fd);
> +
> +	unlink(archive);
> +
> +	if (lar)
> +		free(lar);

If lar can be 0 at err: then the fd deref is a segfault waiting to
happen.


> +static void _close_lar(struct lar *lar)
> +{
> +	munmap(lar->map, lar->size);
> +	close(lar->fd);
> +
> +	free(lar);
> +}

Maybe add if(!lar) return; ? Maybe even complain with a warning.


> +	/* Make a dummy bootblock */
> +
> +	if (lar_add_bootblock(lar, NULL)) {
> +		_close_lar(lar);
> +		return NULL;
> +	}

This will leave a half-baked lar file hanging if adding the bootblock
fails. Perhaps unlink() too in case of error?


> +struct lar * lar_open_archive(const char *archive)
> +{
> +	struct lar *lar;
> +	int ret, romlen;
> +	struct stat s;
> +
> +	ret = stat(archive, &s);
> +
> +	if (ret == -1) {
> +		err("Unable to stat %s\n", archive);
> +		return NULL;
> +	}
> +
> +	lar =  _open_lar(archive, s.st_size, O_RDWR);

Race conditions. First open() then fstat() to get the size.

Also, the file size can change even though we've opened the file.

Since the size is a rather important variable throughout lar we
want to be able to handle it changing under our feet, but I don't
know what the best way would be?


> +static int file_in_list(struct file *files, char *filename)
> +{
> +	struct file *p;
> +
> +	if (files == NULL)
> +		return 1;

Shouldn't this if just be removed so that a NULL list falls through
the for and returns 0?


> +	for(p = files ; p; p = p->next) {
> +		if (!strcmp(p->name, filename))
> +			return 1;
> +	}
> +
> +	return 0;

..since return 1 is used to indicate the file is actually in the
list?


> +		ptr += (ntohl(header->len) + ntohl(header->offset) - 1)
> +			& 0xfffffff0;

We want this piece of code in a single place before it's in 1000
places. Could you make a function of it?


> +static int _write_file(char *filename, unsigned char *buffer, int len)
> +{
> +	char *path = strdup(filename);
> +	int fd, ret;
> +
> +	if (path == NULL) {
> +		err("Out of memory.\n");
> +		return -1;
> +	}
> +
> +	mkdirp((const char *) dirname(path), 0755);
> +	free(path);
> +
> +	fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644);
> +
> +	if (fd == -1) {
> +		err("Error creating file %s\n", filename);
> +		return -1;
> +	}

I don't think lar should mkdir -p implicitly. Just open() and
perror() or print strerror(errno) in case of failure.


> +	ret = write(fd, buffer, len);
> +
> +	if (ret != len)
> +		err("Error writingthe file %s\n", filename);

Again perror() or strerror(errno) would be nice. Goes for the entire
patch of course. :)


> +		if (strncmp(header->magic, MAGIC, 8))
> +			break;

Is strncmp() good for MAGIC ? Maybe memcmp() ?


> +			if (ntohl(header->compression) == none) {

This ntohl() everywhere is tedious and a bit error prone. Perhaps it
would be better to convert all data to machine byte order only when
it's read rather than every time it's used?


> +	if (strstr(name, "nocompress:") == name) {
> +		filename += 11;
> +		thisalgo = none;
> +	}

strncmp() ?


> +	if (filename[0] == '.' && filename[1] == '/')
> +		filename += 2;

realpath() ?


> +	ret = stat (filename, &s);
> +
> +	if (ret) {
> +		err("Unable to stat %s\n", filename);
> +		return -1;
> +	}
> +
> +	/* Allocate a temporary buffer to compress into - this is unavoidable,
> +	   because we need to make sure that the compressed data will fit in
> +	   the LAR, and we won't know the size of the compressed data until
> +	   we actually compress it */
> +
> +	temp = calloc(s.st_size, 1);
> +
> +	if (temp == NULL) {
> +		err("Out of memory.\n");
> +		return -1;
> +	}
> +
> +	/* Open the file */
> +	fd = open(filename, O_RDONLY);

Race again.


> +	/* Do the compression step */
> +	compress_functions[thisalgo](ptr, s.st_size, temp, &complen);
> +
> +	if (complen >= s.st_size && (thisalgo != none)) {
> +		thisalgo = none;
> +		compress_functions[thisalgo](ptr, s.st_size, temp, &complen);
> +	}

?! Is the compressor function required even with algo none?


//Peter



From peter at stuge.se  Thu Jul 12 00:58:41 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 00:58:41 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <20070711224920.761.qmail@stuge.se>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711224920.761.qmail@stuge.se>
Message-ID: <20070711225841.2044.qmail@stuge.se>

On Thu, Jul 12, 2007 at 12:49:20AM +0200, Peter Stuge wrote:
> > +	mkdirp((const char *) dirname(path), 0755);

> I don't think lar should mkdir -p implicitly. Just open() and
> perror() or print strerror(errno) in case of failure.

Sorry. Since we don't store directories in lar it should indeed mkdir
-p implicitly. But I think a bit of sanity would be nice here since a
lar could otherwise be used to overwrite arbitrary system files.

I'll make a patch for mkdirp() that ensures the directory to be
created is actually below the current directory (and also improve the
return-to-cwd code in mkdir() a bit while at it) if there's interest.
Would that be the right place to put it?


//Peter



From peter at stuge.se  Thu Jul 12 01:05:41 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 01:05:41 +0200
Subject: [LinuxBIOS] [PATCH][LAR]  Remove old files
In-Reply-To: <20070711181619.GE20885@cosmic.amd.com>
References: <20070711181619.GE20885@cosmic.amd.com>
Message-ID: <20070711230541.3127.qmail@stuge.se>

On Wed, Jul 11, 2007 at 12:16:19PM -0600, Jordan Crouse wrote:
> Simple patch - this removes the files that were obsoleted by the
> previous patch.

For the next iteration please add these two patches together since
they belong together IMHO.


//Peter



From peter at stuge.se  Thu Jul 12 01:08:47 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 01:08:47 +0200
Subject: [LinuxBIOS] Add a top level target for LAR
In-Reply-To: <20070711183009.GI20885@cosmic.amd.com>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070711181204.22915.qmail@stuge.se>
	<20070711183009.GI20885@cosmic.amd.com>
Message-ID: <20070711230847.3685.qmail@stuge.se>

On Wed, Jul 11, 2007 at 12:30:09PM -0600, Jordan Crouse wrote:
> > I would expect lar to be a target in util/
> 
> I agree.  But as its written right now, the makefiles depend on
> the rules in the toplevel directory

Ah. I see.

This is another reason to move util/ out to it's own home.

What was decided? I'm not religious about a separate repo but I
do think it's appropriate since it's not really a part of LB.


//Peter



From peter at stuge.se  Thu Jul 12 01:19:53 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 01:19:53 +0200
Subject: [LinuxBIOS] [PATCH][LAR] Allow human friendly suffixes for the
	size option
In-Reply-To: <20070711182616.GH20885@cosmic.amd.com>
References: <20070711182616.GH20885@cosmic.amd.com>
Message-ID: <20070711231953.5324.qmail@stuge.se>

Great idea.


On Wed, Jul 11, 2007 at 12:26:16PM -0600, Jordan Crouse wrote:
> +	printf("                \tUse a 'k' suffix to multiply the size by 1K or\n");
> +	printf("                \ta 'm' suffix to multiple the size by 1M.\n");

I would prefer 1024 rather than 1K and 1048576 or 1024*1024 rather
than 1M.


> +static void parse_larsize(char *str)

static u32 ..


> +  larsize = size;

.. and return size ?

May it's useful somewhere else too? Ie. move to lib.c?


//Peter



From peter at stuge.se  Thu Jul 12 01:23:21 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 01:23:21 +0200
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Remove useless includes
In-Reply-To: <20070711202029.GE8025@greenwood>
References: <20070711202029.GE8025@greenwood>
Message-ID: <20070711232321.5931.qmail@stuge.se>

On Wed, Jul 11, 2007 at 10:20:29PM +0200, Uwe Hermann wrote:
> Remove some include files which are not required (and add some which are).
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Thu Jul 12 01:25:23 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 01:25:23 +0200
Subject: [LinuxBIOS] [PATCH][v3] Move lar into global util/ directory +
	svn:externals
In-Reply-To: <20070711202452.GF8025@greenwood>
References: <20070711202452.GF8025@greenwood>
Message-ID: <20070711232523.6270.qmail@stuge.se>

On Wed, Jul 11, 2007 at 10:24:52PM +0200, Uwe Hermann wrote:
> OK, not really a patch, but I think we can move lar into the global
> util/ directory and suck it into v3 via svn:externals.

Yes. Is it a separate repo yet ? Or is it in the v2 repo? It is
distinct from LB. No need to run abuild after util changes etc.


//Peter



From peter at stuge.se  Thu Jul 12 01:36:10 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 01:36:10 +0200
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames for
	create and add
In-Reply-To: <20070711182227.GF20885@cosmic.amd.com>
References: <20070711182227.GF20885@cosmic.amd.com>
Message-ID: <20070711233610.7951.qmail@stuge.se>

On Wed, Jul 11, 2007 at 12:22:27PM -0600, Jordan Crouse wrote:
> This patch allows you to specify an arbitrary filename as well as a 
> pathname for files in create & add mode in the following manner:

Another great idea!


> ./lar -a my.lar ../sources/vsa.bin:vsa

I don't like having all this information (algo too) in-band with the
filename.. I don't know a nice way to do it for when adding many
files at once though. :\ I was thinking about a "lar script" that
would say what goes where with what algo but it would be nice to not
have to go there.


//Peter



From jordan.crouse at amd.com  Thu Jul 12 01:38:41 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 17:38:41 -0600
Subject: [LinuxBIOS] New LAR access functions
In-Reply-To: <20070711224920.761.qmail@stuge.se>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711224920.761.qmail@stuge.se>
Message-ID: <20070711233841.GB3127@cosmic.amd.com>

On 12/07/07 00:49 +0200, Peter Stuge wrote:
> Really good ideas! But some comments on implementation..
> 
> 
> On Wed, Jul 11, 2007 at 12:15:17PM -0600, Jordan Crouse wrote:
> > +struct lar {
> > +	int fd;
> > +	unsigned char *map;
> > +	int size;
> > +};
> 
> u32 size maybe?

I guess, though I'll bet this code doesn't survive long enough to
see those 2G ROM chips.. :)
> 
> > +static int lar_read_size(struct lar *lar, int filelen)
> > +{
> > +	unsigned int *ptr = (unsigned int *) (lar->map + (filelen - 12));
> > +	return ptr[0];
> > +}
> 
> What about all this pointer arithmetic? Is it really correct?
> 
> Doesn't adding 1 to a pointer actually add sizeof pointed-to-type to
> the address? Ie. this code isn't portable?

lar->map is a uchar, which is a size of 1, so the math works.   I think
by convention, sizeof(uchar) is 1 everywhere, so there shouldn't be a
portability issue here.  If there is, then we'll have to do some very ugly
casting in about 30 places in the code, and I'm hoping it doesn't come
to that.

> 
> > +static void annotate_bootblock(unsigned char *ptr, unsigned int size)
> > +{
> > +	int i;
> > +	unsigned int *p;
> > +
> > +	for(i = 13; i > 0; i--)
> > +		ptr[BOOTBLOCK_SIZE - i] = '\0';
> 
> I think a memset() call here would be nicer..

Oops - I copied that without thinking.  Yeah - memset best.

 
> > +	p = (unsigned int *) (ptr + BOOTBLOCK_SIZE - 12);
> > +	p[0] = size;
> > +}
> 
> Then there's the matter of the pointer arithmetic again. Since ptr is
> uchar * this will work, but then writing size to p[0] will write a
> different number of bytes on different archs, right?

sizeof(unsigned int) is 4 on all the platforms we care about.  I guess I 
could use u32 instead - but thats just going to end up decoding back down
to unsigned int.    If we used an unsigned long, then we would be in trouble,
but I've made very sure we didn't do something like that.

> 
> > + err:
> > +	if (lar->fd >= 0)
> > +		close(lar->fd);
> > +
> > +	unlink(archive);
> > +
> > +	if (lar)
> > +		free(lar);
> 
> If lar can be 0 at err: then the fd deref is a segfault waiting to
> happen.

Lar can't be 0 at err - failure to malloc lar: on line 132 will immediately
return.  err: is there specifically to cleanup lar->fd.

> 
> > +static void _close_lar(struct lar *lar)
> > +{
> > +	munmap(lar->map, lar->size);
> > +	close(lar->fd);
> > +
> > +	free(lar);
> > +}
> 
> Maybe add if(!lar) return; ? Maybe even complain with a warning.

Thats a good idea.

> 
> > +	/* Make a dummy bootblock */
> > +
> > +	if (lar_add_bootblock(lar, NULL)) {
> > +		_close_lar(lar);
> > +		return NULL;
> > +	}
> 
> This will leave a half-baked lar file hanging if adding the bootblock
> fails. Perhaps unlink() too in case of error?

Hmm - sure.  

> 
> > +struct lar * lar_open_archive(const char *archive)
> > +{
> > +	struct lar *lar;
> > +	int ret, romlen;
> > +	struct stat s;
> > +
> > +	ret = stat(archive, &s);
> > +
> > +	if (ret == -1) {
> > +		err("Unable to stat %s\n", archive);
> > +		return NULL;
> > +	}
> > +
> > +	lar =  _open_lar(archive, s.st_size, O_RDWR);
> 
> Race conditions. First open() then fstat() to get the size.

Okay, I agree.  It will be a little bit more complex, but its probably
better.

> Also, the file size can change even though we've opened the file.
> 
> Since the size is a rather important variable throughout lar we
> want to be able to handle it changing under our feet, but I don't
> know what the best way would be?

Do we care?   We're not designing LAR to be able to handle 
concurent processes changing the file at the same time - if it
happens, it will be just pure, unmigitaged bad luck - same as if you
happen to change a file while you 'cat' or 'dd' it.  Is this something
thats realistic enough to worry about?

> 
> > +static int file_in_list(struct file *files, char *filename)
> > +{
> > +	struct file *p;
> > +
> > +	if (files == NULL)
> > +		return 1;
> 
> Shouldn't this if just be removed so that a NULL list falls through
> the for and returns 0?

No - it should return a 1, because by design, files==NULL means 
"show all files".

> > +		ptr += (ntohl(header->len) + ntohl(header->offset) - 1)
> > +			& 0xfffffff0;
> 
> We want this piece of code in a single place before it's in 1000
> places. Could you make a function of it?

Sure.

> 
> > +static int _write_file(char *filename, unsigned char *buffer, int len)
> > +{
> > +	char *path = strdup(filename);
> > +	int fd, ret;
> > +
> > +	if (path == NULL) {
> > +		err("Out of memory.\n");
> > +		return -1;
> > +	}
> > +
> > +	mkdirp((const char *) dirname(path), 0755);
> > +	free(path);
> > +
> > +	fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644);
> > +
> > +	if (fd == -1) {
> > +		err("Error creating file %s\n", filename);
> > +		return -1;
> > +	}
> 
> I don't think lar should mkdir -p implicitly. Just open() and
> perror() or print strerror(errno) in case of failure.

This came from the original code - I think that Stefan and Patrick were
going for the same behavior as tar - and tar definately does implicitly
use mkdir -p on extract.

> 
> > +	ret = write(fd, buffer, len);
> > +
> > +	if (ret != len)
> > +		err("Error writingthe file %s\n", filename);
> 
> Again perror() or strerror(errno) would be nice. Goes for the entire
> patch of course. :)

Most of these were pretty quick and dirty.  I was thinking while I was
writing this that we should go through and standardize all the error and
warning messages.  This would be one of those things to do.

> 
> > +		if (strncmp(header->magic, MAGIC, 8))
> > +			break;
> 
> Is strncmp() good for MAGIC ? Maybe memcmp() ?

Yes - memcmp is better.

> 
> > +			if (ntohl(header->compression) == none) {
> 
> This ntohl() everywhere is tedious and a bit error prone. Perhaps it
> would be better to convert all data to machine byte order only when
> it's read rather than every time it's used?

The file is mmaped, so thats really impossible.  It is tedious, but its
the only way to ensure compatability with big endian machines.

> 
> > +	if (strstr(name, "nocompress:") == name) {
> > +		filename += 11;
> > +		thisalgo = none;
> > +	}
> 
> strncmp() ?

Yeah - I guess either one would be ok.  Should go with
strncmp - its probably faster.

> 
> > +	if (filename[0] == '.' && filename[1] == '/')
> > +		filename += 2;
> 
> realpath() ?

I don't know if realpath is the right one here - because it returns the
absolute path, which I don't think is the goal here.  I tried to squeeze
the filename : pathname stuff in here without making too many changes - 
perhaps we should revisit that.

> > +	ret = stat (filename, &s);
> > +
> > +	if (ret) {
> > +		err("Unable to stat %s\n", filename);
> > +		return -1;
> > +	}
> > +
> > +	/* Allocate a temporary buffer to compress into - this is unavoidable,
> > +	   because we need to make sure that the compressed data will fit in
> > +	   the LAR, and we won't know the size of the compressed data until
> > +	   we actually compress it */
> > +
> > +	temp = calloc(s.st_size, 1);
> > +
> > +	if (temp == NULL) {
> > +		err("Out of memory.\n");
> > +		return -1;
> > +	}
> > +
> > +	/* Open the file */
> > +	fd = open(filename, O_RDONLY);
> 
> Race again.

Got it.

> > +	/* Do the compression step */
> > +	compress_functions[thisalgo](ptr, s.st_size, temp, &complen);
> > +
> > +	if (complen >= s.st_size && (thisalgo != none)) {
> > +		thisalgo = none;
> > +		compress_functions[thisalgo](ptr, s.st_size, temp, &complen);
> > +	}
> 
> ?! Is the compressor function required even with algo none?

I think it does it to avoid complex logic - but we can look at this 
again - there's probably cleanup that can happen here.

Thanks for your comments.
Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From peter at stuge.se  Thu Jul 12 01:39:13 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 01:39:13 +0200
Subject: [LinuxBIOS] Porting linux bios to MSI ms7250
In-Reply-To: <4693C1E9.7000202@kami.ru>
References: <4693C1E9.7000202@kami.ru>
Message-ID: <20070711233913.8455.qmail@stuge.se>

On Tue, Jul 10, 2007 at 05:29:13PM +0000, George V. Adamov wrote:
> I opened linuxbios_ram.nrv2b, checked it?s location in
> linuxbios.rom (file I flash to ram), calculated the offset and
> got 0xfffe0000, so the offset seems to be ok, but in the memory
> only 0xff...
> any ideas?

It looks just like there is RAM shadowing the flash here..


//Peter



From jordan.crouse at amd.com  Thu Jul 12 01:41:21 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 17:41:21 -0600
Subject: [LinuxBIOS] Allow human friendly suffixes for the size option
In-Reply-To: <20070711231953.5324.qmail@stuge.se>
References: <20070711182616.GH20885@cosmic.amd.com>
	<20070711231953.5324.qmail@stuge.se>
Message-ID: <20070711234121.GC3127@cosmic.amd.com>

On 12/07/07 01:19 +0200, Peter Stuge wrote:
> Great idea.
> 
> 
> On Wed, Jul 11, 2007 at 12:26:16PM -0600, Jordan Crouse wrote:
> > +	printf("                \tUse a 'k' suffix to multiply the size by 1K or\n");
> > +	printf("                \ta 'm' suffix to multiple the size by 1M.\n");
> 
> I would prefer 1024 rather than 1K and 1048576 or 1024*1024 rather
> than 1M.

Good idea.  I think 'dd' does the same thing.

> 
> > +static void parse_larsize(char *str)
> 
> static u32 ..
> 
> 
> > +  larsize = size;
> 
> .. and return size ?
> 
> May it's useful somewhere else too? Ie. move to lib.c?

I don't know - this is the only place we do this sort of thing - 
in fact, its probably overkill to have a function - we could do it
right in the switch statement if we wanted to.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From jordan.crouse at amd.com  Thu Jul 12 01:50:10 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 11 Jul 2007 17:50:10 -0600
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames for
 create and add
In-Reply-To: <20070711233610.7951.qmail@stuge.se>
References: <20070711182227.GF20885@cosmic.amd.com>
	<20070711233610.7951.qmail@stuge.se>
Message-ID: <20070711235010.GD3127@cosmic.amd.com>

On 12/07/07 01:36 +0200, Peter Stuge wrote:
> On Wed, Jul 11, 2007 at 12:22:27PM -0600, Jordan Crouse wrote:
> > This patch allows you to specify an arbitrary filename as well as a 
> > pathname for files in create & add mode in the following manner:
> 
> Another great idea!
> 
> 
> > ./lar -a my.lar ../sources/vsa.bin:vsa
> 
> I don't like having all this information (algo too) in-band with the
> filename.. I don't know a nice way to do it for when adding many
> files at once though. :\ I was thinking about a "lar script" that
> would say what goes where with what algo but it would be nice to not
> have to go there.

I was definately thinking about going that direction.  In fact, I talked
to Stefan about it at OLS.  It wouldn't really have to be a script - 
Stefan has been thinking about creating a MANIFEST file when we extract
the LAR that lists the blobs and where they are located - we could use
the exact same format on the input side too:

--------------------------------------------
# MANIFEST
# Filename	    pathname		algorithm
/root/my.payload    normal/payload	lzma
...
bootblock	    bootblock		-
---------------------------------------------

(As an example).  This might actually be better for buildROM - then each
target that builds a blob for the LAR would just echo the line into this
file - thats probably cleaner then something ugly like

LAR_BLOBS += $(SOURCE_DIR)/$(GEODE_VSA):vsa 

Which is what I'm doing now.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From peter at stuge.se  Thu Jul 12 02:05:48 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 02:05:48 +0200
Subject: [LinuxBIOS] Allow human friendly suffixes for the size option
In-Reply-To: <20070711234121.GC3127@cosmic.amd.com>
References: <20070711182616.GH20885@cosmic.amd.com>
	<20070711231953.5324.qmail@stuge.se>
	<20070711234121.GC3127@cosmic.amd.com>
Message-ID: <20070712000548.12695.qmail@stuge.se>

On Wed, Jul 11, 2007 at 05:41:21PM -0600, Jordan Crouse wrote:
> > I would prefer 1024 rather than 1K and 1048576 or 1024*1024
> > rather than 1M.
> 
> Good idea.  I think 'dd' does the same thing.

--8<--
$ dd --help
..
BLOCKS and BYTES may be followed by the following multiplicative
suffixes:
xM M, c 1, w 2, b 512, kB 1000, K 1024, MB 1000*1000, M 1024*1024,
GB 1000*1000*1000, G 1024*1024*1024, and so on for T, P, E, Z, Y.
-->8--

I think we should just stay with [kK]=1024 and [mM]=1024*1024 though.

But the point was that lar should print the numbers rather than the
suffixes in the help output.


> > > +static void parse_larsize(char *str)
> > 
> > May it's useful somewhere else too? Ie. move to lib.c?
> 
> I don't know - this is the only place we do this sort of thing - 
> in fact, its probably overkill to have a function - we could do it
> right in the switch statement if we wanted to.

Sounds good to me.


//Peter



From segher at kernel.crashing.org  Thu Jul 12 02:16:21 2007
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Thu, 12 Jul 2007 02:16:21 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <20070711221134.27245.qmail@stuge.se>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711221134.27245.qmail@stuge.se>
Message-ID: <429EB3D7-44E4-447D-931C-2B83D73F9163@kernel.crashing.org>

> Some ideas have been tossed around;
>
> 1. teach lar about flash chip sector sizes
> 2. bootblock at top or at bottom
>
>
> 1 means combining flashrom and lar somehow.. Thoughts?

I think the boot block should be outside of the LAR completely.
A normal LinuxBIOS upgrade shouldn't touch the bootblock; that
way, recovery code in there can help the user load a working
image into flash after some screw-up, over a serial port or
whatever.

This also handily solves the current problem :-)


Segher




From peter at stuge.se  Thu Jul 12 02:46:06 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 02:46:06 +0200
Subject: [LinuxBIOS] New LAR access functions
In-Reply-To: <20070711233841.GB3127@cosmic.amd.com>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711224920.761.qmail@stuge.se>
	<20070711233841.GB3127@cosmic.amd.com>
Message-ID: <20070712004606.19095.qmail@stuge.se>

On Wed, Jul 11, 2007 at 05:38:41PM -0600, Jordan Crouse wrote:
> > > +	int size;
> > 
> > u32 size maybe?
> 
> I guess, though I'll bet this code doesn't survive long enough to
> see those 2G ROM chips.. :)

I won't take that bet.

But it is nice to show that we have thought about it by being
explicit. Eliminating potential portability problems is another plus.


> > > +	unsigned int *ptr = (unsigned int *) (lar->map + (filelen - 12));
> > 
> > What about all this pointer arithmetic? Is it really correct?
> 
> lar->map is a uchar, which is a size of 1, so the math works.

Yes, that's right. Sorry about the noise.


> I think by convention, sizeof(uchar) is 1 everywhere, so there
> shouldn't be a portability issue here.  If there is, then we'll
> have to do some very ugly casting in about 30 places in the code,
> and I'm hoping it doesn't come to that.

The alternative is u8 *map. Copy u32 size reasoning but much less
important. No. Never mind.


> > > +	p = (unsigned int *) (ptr + BOOTBLOCK_SIZE - 12);
> > > +	p[0] = size;
> > > +}
> > 
> > Then there's the matter of the pointer arithmetic again. Since ptr
> > is uchar * this will work, but then writing size to p[0] will write
> > a different number of bytes on different archs, right?
> 
> sizeof(unsigned int) is 4 on all the platforms we care about.

640k will be enough. ;)


> I guess I could use u32 instead -

Please do. Or do I need to be hit over the head hard with a C
cluestick?


> but thats just going to end up decoding back down to unsigned int.

Fine.


> If we used an unsigned long, then we would be in trouble, but I've
> made very sure we didn't do something like that.

Yeah, that's good. But is it good enough?



> > > + err:
> > > +	if (lar->fd >= 0)
> > > +		close(lar->fd);
> > > +
> > > +	unlink(archive);
> > > +
> > > +	if (lar)
> > > +		free(lar);
> > 
> > If lar can be 0 at err: then the fd deref is a segfault waiting
> > to happen.
> 
> Lar can't be 0 at err

Then the if (lar) free(lar); should change IMHO. It's confusing.

I'd like this though:

if (lar) {
  if (lar->fd >= 0)
    close(lar->fd);
  free(lar);
}
unlink(archive);


Is lar->fd initialized to -1 btw?


> > Race conditions. First open() then fstat() to get the size.
> 
> Okay, I agree.  It will be a little bit more complex, but its
> probably better.

Make the size be a & argument to _open_lar() instead and hide the
fstat() in there.


> > Also, the file size can change even though we've opened the file.
> > 
> > Since the size is a rather important variable throughout lar we
> > want to be able to handle it changing under our feet, but I don't
> > know what the best way would be?
> 
> Do we care?   We're not designing LAR to be able to handle
> concurent processes changing the file at the same time - if it
> happens, it will be just pure, unmigitaged bad luck - same as if
> you happen to change a file while you 'cat' or 'dd' it.  Is this
> something thats realistic enough to worry about?

It depends on the rest of the code. As long as lar does not go crazy
if a larball changes in size while running we don't care, but some
calculations do use that total size..

The file can be corrupt, I just want to avoid making it 4G-256k.

I would be happy if lar exits with an error if the file size has
changed between _open_lar() and _close_lar().


> > > +static int file_in_list(struct file *files, char *filename)
> > > +{
> > > +	struct file *p;
> > > +
> > > +	if (files == NULL)
> > > +		return 1;
> > 
> > Shouldn't this if just be removed so that a NULL list falls
> > through the for and returns 0?
> 
> No - it should return a 1, because by design, files==NULL means
> "show all files".

That seems sort of unintuitive for a function named file_in_list?

I'd prefer having that negation in the caller. Or at the very least
doxygen comment it.


> > > +		ptr += (ntohl(header->len) + ntohl(header->offset) - 1)
> > > +			& 0xfffffff0;
> > 
> > We want this piece of code in a single place before it's in 1000
> > places. Could you make a function of it?
> 
> Sure.

Also note that ntohl() already uses uint32_t - another reason for us
to use all u32.


> > Again perror() or strerror(errno) would be nice. Goes for the
> > entire patch of course. :)
> 
> Most of these were pretty quick and dirty.  I was thinking while I
> was writing this that we should go through and standardize all the
> error and warning messages.  This would be one of those things to
> do.

Sure, separate patch for this some other time would be great. I
figured I'd mention it since this was all new code though.


> > > +			if (ntohl(header->compression) == none) {
> > 
> > This ntohl() everywhere is tedious and a bit error prone. Perhaps
> > it would be better to convert all data to machine byte order only
> > when it's read rather than every time it's used?
> 
> The file is mmaped, so thats really impossible.  It is tedious, but
> its the only way to ensure compatability with big endian machines.

We can abstract the header. I am generally strongly against
unneccessary abstraction but in this case I think it's warranted. The
code will be MUCH more readable and writable without all the ntohl().

Either have get functions for the header fields or make a native copy
of the header in the new function that finds the next valid file
header. I like the latter.


> > > +	if (filename[0] == '.' && filename[1] == '/')
> > > +		filename += 2;
> > 
> > realpath() ?
> 
> I don't know if realpath is the right one here - because it returns
> the absolute path, which I don't think is the goal here.

No, but cwd would be stripped away to get a canonicalized relative
path. I can break the above code just by doing ././filename while a
construct based on realpath() would clean anything up.

There's no reason for a person to write ././foo of course, but it
could easily happen with a layer or two of scripting.


> I tried to squeeze the filename : pathname stuff in here without
> making too many changes - perhaps we should revisit that.

I think so.


> > ?! Is the compressor function required even with algo none?
> 
> I think it does it to avoid complex logic - but we can look at this
> again - there's probably cleanup that can happen here.

Not that complex.. if (algo != none) { do_compression_stuff; } :)


> Thanks for your comments.

Welcome. Thanks for the patch! =)


//Peter



From peter at stuge.se  Thu Jul 12 02:58:49 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 02:58:49 +0200
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames for
	create and add
In-Reply-To: <20070711235010.GD3127@cosmic.amd.com>
References: <20070711182227.GF20885@cosmic.amd.com>
	<20070711233610.7951.qmail@stuge.se>
	<20070711235010.GD3127@cosmic.amd.com>
Message-ID: <20070712005849.20953.qmail@stuge.se>

On Wed, Jul 11, 2007 at 05:50:10PM -0600, Jordan Crouse wrote:
> > "lar script"
> 
> I was definately thinking about going that direction.  In fact, I
> talked to Stefan about it at OLS.  It wouldn't really have to be a
> script - Stefan has been thinking about creating a MANIFEST file
> when we extract the LAR that lists the blobs and where they are
> located - we could use the exact same format on the input side too:

I say just print it to stdout on extract. The filenames (on disk)
will obviously always be homogenous on extract, but lar could have a
-C option like tar to relocate from cwd. Pathnames are always
straight from the larball.


> --------------------------------------------
> # MANIFEST
> # Filename	    pathname		algorithm
> /root/my.payload    normal/payload	lzma
> ...
> bootblock	    bootblock		-
> ---------------------------------------------
> 
> (As an example).

Yeah, I guess the GMTA principle says this is the way to go.

The one-line-per-file is slightly problematic in that it makes
whitespace instead of : be reserved in filenames. :\ (Because the
filename needs to be there twice it's not possible to just put the
algo first and use the rest as filename.)

And I prefer "none" over "-" for no compression. Bikeshed though.


> This might actually be better for buildROM - then each target that
> builds a blob for the LAR would just echo the line into this file -
> thats probably cleaner then something ugly like
> 
> LAR_BLOBS += $(SOURCE_DIR)/$(GEODE_VSA):vsa 
> 
> Which is what I'm doing now.

Sure, the manifest is certainly nice for scriptability. I'd like it
to be readable from stdin too. Maybe you can use some clever here
documents in buildrom then.


//Peter



From svn at openbios.org  Thu Jul 12 03:03:05 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 12 Jul 2007 03:03:05 +0200
Subject: [LinuxBIOS] r447 - in LinuxBIOSv3: include/device
	mainboard/emulation/qemu-x86
Message-ID: <mailman.513.1355071132.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-12 03:03:05 +0200 (Thu, 12 Jul 2007)
New Revision: 447

Modified:
   LinuxBIOSv3/include/device/pci_ids.h
   LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile
   LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c
   LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c
Log:
Add (and use) the new PCI IDs:
 - PCI_VENDOR_ID_CIRRUS
 - PCI_DEVICE_ID_CIRRUS_5446

Some minor cosmetic fixes (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/include/device/pci_ids.h
===================================================================
--- LinuxBIOSv3/include/device/pci_ids.h	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/include/device/pci_ids.h	2007-07-12 01:03:05 UTC (rev 447)
@@ -11,151 +11,148 @@
 #ifndef DEVICE_PCI_IDS_H
 #define DEVICE_PCI_IDS_H
 
-/*
- *	PCI Class, Vendor and Device IDs
- *
- *	Please keep sorted.
- */
-
 /* Device classes and subclasses. */
 
-#define PCI_CLASS_NOT_DEFINED		0x0000
-#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
+#define PCI_CLASS_NOT_DEFINED			0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA		0x0001
 
-#define PCI_BASE_CLASS_STORAGE		0x01
-#define PCI_CLASS_STORAGE_SCSI		0x0100
-#define PCI_CLASS_STORAGE_IDE		0x0101
-#define PCI_CLASS_STORAGE_FLOPPY	0x0102
-#define PCI_CLASS_STORAGE_IPI		0x0103
-#define PCI_CLASS_STORAGE_RAID		0x0104
-#define PCI_CLASS_STORAGE_SATA		0x0106
-#define PCI_CLASS_STORAGE_SATA_AHCI	0x010601
-#define PCI_CLASS_STORAGE_SAS		0x0107
-#define PCI_CLASS_STORAGE_OTHER		0x0180
+#define PCI_BASE_CLASS_STORAGE			0x01
+#define PCI_CLASS_STORAGE_SCSI			0x0100
+#define PCI_CLASS_STORAGE_IDE			0x0101
+#define PCI_CLASS_STORAGE_FLOPPY		0x0102
+#define PCI_CLASS_STORAGE_IPI			0x0103
+#define PCI_CLASS_STORAGE_RAID			0x0104
+#define PCI_CLASS_STORAGE_SATA			0x0106
+#define PCI_CLASS_STORAGE_SATA_AHCI		0x010601
+#define PCI_CLASS_STORAGE_SAS			0x0107
+#define PCI_CLASS_STORAGE_OTHER			0x0180
 
-#define PCI_BASE_CLASS_NETWORK		0x02
-#define PCI_CLASS_NETWORK_ETHERNET	0x0200
-#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
-#define PCI_CLASS_NETWORK_FDDI		0x0202
-#define PCI_CLASS_NETWORK_ATM		0x0203
-#define PCI_CLASS_NETWORK_OTHER		0x0280
+#define PCI_BASE_CLASS_NETWORK			0x02
+#define PCI_CLASS_NETWORK_ETHERNET		0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING		0x0201
+#define PCI_CLASS_NETWORK_FDDI			0x0202
+#define PCI_CLASS_NETWORK_ATM			0x0203
+#define PCI_CLASS_NETWORK_OTHER			0x0280
 
-#define PCI_BASE_CLASS_DISPLAY		0x03
-#define PCI_CLASS_DISPLAY_VGA		0x0300
-#define PCI_CLASS_DISPLAY_XGA		0x0301
-#define PCI_CLASS_DISPLAY_3D		0x0302
-#define PCI_CLASS_DISPLAY_OTHER		0x0380
+#define PCI_BASE_CLASS_DISPLAY			0x03
+#define PCI_CLASS_DISPLAY_VGA			0x0300
+#define PCI_CLASS_DISPLAY_XGA			0x0301
+#define PCI_CLASS_DISPLAY_3D			0x0302
+#define PCI_CLASS_DISPLAY_OTHER			0x0380
 
-#define PCI_BASE_CLASS_MULTIMEDIA	0x04
-#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
-#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
-#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
-#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
+#define PCI_BASE_CLASS_MULTIMEDIA		0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO		0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO		0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE		0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER		0x0480
 
-#define PCI_BASE_CLASS_MEMORY		0x05
-#define PCI_CLASS_MEMORY_RAM		0x0500
-#define PCI_CLASS_MEMORY_FLASH		0x0501
-#define PCI_CLASS_MEMORY_OTHER		0x0580
+#define PCI_BASE_CLASS_MEMORY			0x05
+#define PCI_CLASS_MEMORY_RAM			0x0500
+#define PCI_CLASS_MEMORY_FLASH			0x0501
+#define PCI_CLASS_MEMORY_OTHER			0x0580
 
-#define PCI_BASE_CLASS_BRIDGE		0x06
-#define PCI_CLASS_BRIDGE_HOST		0x0600
-#define PCI_CLASS_BRIDGE_ISA		0x0601
-#define PCI_CLASS_BRIDGE_EISA		0x0602
-#define PCI_CLASS_BRIDGE_MC		0x0603
-#define PCI_CLASS_BRIDGE_PCI		0x0604
-#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
-#define PCI_CLASS_BRIDGE_NUBUS		0x0606
-#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
-#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
-#define PCI_CLASS_BRIDGE_OTHER		0x0680
+#define PCI_BASE_CLASS_BRIDGE			0x06
+#define PCI_CLASS_BRIDGE_HOST			0x0600
+#define PCI_CLASS_BRIDGE_ISA			0x0601
+#define PCI_CLASS_BRIDGE_EISA			0x0602
+#define PCI_CLASS_BRIDGE_MC			0x0603
+#define PCI_CLASS_BRIDGE_PCI			0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA			0x0605
+#define PCI_CLASS_BRIDGE_NUBUS			0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS		0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY		0x0608
+#define PCI_CLASS_BRIDGE_OTHER			0x0680
 
-#define PCI_BASE_CLASS_COMMUNICATION	0x07
-#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
-#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
-#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
-#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
-#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
+#define PCI_BASE_CLASS_COMMUNICATION		0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL		0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL	0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL	0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM		0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER		0x0780
 
-#define PCI_BASE_CLASS_SYSTEM		0x08
-#define PCI_CLASS_SYSTEM_PIC		0x0800
-#define PCI_CLASS_SYSTEM_PIC_IOAPIC	0x080010
-#define PCI_CLASS_SYSTEM_PIC_IOXAPIC	0x080020
-#define PCI_CLASS_SYSTEM_DMA		0x0801
-#define PCI_CLASS_SYSTEM_TIMER		0x0802
-#define PCI_CLASS_SYSTEM_RTC		0x0803
-#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
-#define PCI_CLASS_SYSTEM_SDHCI		0x0805
-#define PCI_CLASS_SYSTEM_OTHER		0x0880
+#define PCI_BASE_CLASS_SYSTEM			0x08
+#define PCI_CLASS_SYSTEM_PIC			0x0800
+#define PCI_CLASS_SYSTEM_PIC_IOAPIC		0x080010
+#define PCI_CLASS_SYSTEM_PIC_IOXAPIC		0x080020
+#define PCI_CLASS_SYSTEM_DMA			0x0801
+#define PCI_CLASS_SYSTEM_TIMER			0x0802
+#define PCI_CLASS_SYSTEM_RTC			0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG		0x0804
+#define PCI_CLASS_SYSTEM_SDHCI			0x0805
+#define PCI_CLASS_SYSTEM_OTHER			0x0880
 
-#define PCI_BASE_CLASS_INPUT		0x09
-#define PCI_CLASS_INPUT_KEYBOARD	0x0900
-#define PCI_CLASS_INPUT_PEN		0x0901
-#define PCI_CLASS_INPUT_MOUSE		0x0902
-#define PCI_CLASS_INPUT_SCANNER		0x0903
-#define PCI_CLASS_INPUT_GAMEPORT	0x0904
-#define PCI_CLASS_INPUT_OTHER		0x0980
+#define PCI_BASE_CLASS_INPUT			0x09
+#define PCI_CLASS_INPUT_KEYBOARD		0x0900
+#define PCI_CLASS_INPUT_PEN			0x0901
+#define PCI_CLASS_INPUT_MOUSE			0x0902
+#define PCI_CLASS_INPUT_SCANNER			0x0903
+#define PCI_CLASS_INPUT_GAMEPORT		0x0904
+#define PCI_CLASS_INPUT_OTHER			0x0980
 
-#define PCI_BASE_CLASS_DOCKING		0x0a
-#define PCI_CLASS_DOCKING_GENERIC	0x0a00
-#define PCI_CLASS_DOCKING_OTHER		0x0a80
+#define PCI_BASE_CLASS_DOCKING			0x0a
+#define PCI_CLASS_DOCKING_GENERIC		0x0a00
+#define PCI_CLASS_DOCKING_OTHER			0x0a80
 
-#define PCI_BASE_CLASS_PROCESSOR	0x0b
-#define PCI_CLASS_PROCESSOR_386		0x0b00
-#define PCI_CLASS_PROCESSOR_486		0x0b01
-#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
-#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
-#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
-#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
-#define PCI_CLASS_PROCESSOR_CO		0x0b40
+#define PCI_BASE_CLASS_PROCESSOR		0x0b
+#define PCI_CLASS_PROCESSOR_386			0x0b00
+#define PCI_CLASS_PROCESSOR_486			0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM		0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA		0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC		0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS		0x0b30
+#define PCI_CLASS_PROCESSOR_CO			0x0b40
 
-#define PCI_BASE_CLASS_SERIAL		0x0c
-#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
-#define PCI_CLASS_SERIAL_FIREWIRE_OHCI	0x0c0010
-#define PCI_CLASS_SERIAL_ACCESS		0x0c01
-#define PCI_CLASS_SERIAL_SSA		0x0c02
-#define PCI_CLASS_SERIAL_USB		0x0c03
-#define PCI_CLASS_SERIAL_USB_UHCI	0x0c0300
-#define PCI_CLASS_SERIAL_USB_OHCI	0x0c0310
-#define PCI_CLASS_SERIAL_USB_EHCI	0x0c0320
-#define PCI_CLASS_SERIAL_FIBER		0x0c04
-#define PCI_CLASS_SERIAL_SMBUS		0x0c05
+#define PCI_BASE_CLASS_SERIAL			0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE		0x0c00
+#define PCI_CLASS_SERIAL_FIREWIRE_OHCI		0x0c0010
+#define PCI_CLASS_SERIAL_ACCESS			0x0c01
+#define PCI_CLASS_SERIAL_SSA			0x0c02
+#define PCI_CLASS_SERIAL_USB			0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI		0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI		0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI		0x0c0320
+#define PCI_CLASS_SERIAL_FIBER			0x0c04
+#define PCI_CLASS_SERIAL_SMBUS			0x0c05
 
 #define PCI_BASE_CLASS_WIRELESS			0x0d
 #define PCI_CLASS_WIRELESS_RF_CONTROLLER	0x0d10
 #define PCI_CLASS_WIRELESS_WHCI			0x0d1010
 
-#define PCI_BASE_CLASS_INTELLIGENT	0x0e
-#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
+#define PCI_BASE_CLASS_INTELLIGENT		0x0e
+#define PCI_CLASS_INTELLIGENT_I2O		0x0e00
 
-#define PCI_BASE_CLASS_SATELLITE	0x0f
-#define PCI_CLASS_SATELLITE_TV		0x0f00
-#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
-#define PCI_CLASS_SATELLITE_VOICE	0x0f03
-#define PCI_CLASS_SATELLITE_DATA	0x0f04
+#define PCI_BASE_CLASS_SATELLITE		0x0f
+#define PCI_CLASS_SATELLITE_TV			0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO		0x0f01
+#define PCI_CLASS_SATELLITE_VOICE		0x0f03
+#define PCI_CLASS_SATELLITE_DATA		0x0f04
 
-#define PCI_BASE_CLASS_CRYPT		0x10
-#define PCI_CLASS_CRYPT_NETWORK		0x1000
-#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
-#define PCI_CLASS_CRYPT_OTHER		0x1080
+#define PCI_BASE_CLASS_CRYPT			0x10
+#define PCI_CLASS_CRYPT_NETWORK			0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT		0x1001
+#define PCI_CLASS_CRYPT_OTHER			0x1080
 
-#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
-#define PCI_CLASS_SP_DPIO		0x1100
-#define PCI_CLASS_SP_OTHER		0x1180
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING	0x11
+#define PCI_CLASS_SP_DPIO			0x1100
+#define PCI_CLASS_SP_OTHER			0x1180
 
-#define PCI_CLASS_OTHERS		0xff
+#define PCI_CLASS_OTHERS			0xff
 
 /* Vendors and devices. Sort key: vendor first, device next. */
 
-#define PCI_VENDOR_ID_AMD		0x1022
-#define PCI_DEVICE_ID_AMD_LXBRIDGE	0x2080
-#define PCI_DEVICE_ID_AMD_CS5536_ISA	0x2090
-#define PCI_DEVICE_ID_AMD_CS5536_FLASH	0x2091
-#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE	0x2092
-#define PCI_DEVICE_ID_AMD_CS5536_AUDIO	0x2093
-#define PCI_DEVICE_ID_AMD_CS5536_OHCI	0x2094
-#define PCI_DEVICE_ID_AMD_CS5536_EHCI	0x2095
-#define PCI_DEVICE_ID_AMD_CS5536_UDC	0x2096
-#define PCI_DEVICE_ID_AMD_CS5536_OTG	0x2097
-#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE	0x209A
+#define PCI_VENDOR_ID_AMD			0x1022
+#define PCI_DEVICE_ID_AMD_LXBRIDGE		0x2080
+#define PCI_DEVICE_ID_AMD_CS5536_ISA		0x2090
+#define PCI_DEVICE_ID_AMD_CS5536_FLASH		0x2091
+#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE		0x2092
+#define PCI_DEVICE_ID_AMD_CS5536_AUDIO		0x2093
+#define PCI_DEVICE_ID_AMD_CS5536_OHCI		0x2094
+#define PCI_DEVICE_ID_AMD_CS5536_EHCI		0x2095
+#define PCI_DEVICE_ID_AMD_CS5536_UDC		0x2096
+#define PCI_DEVICE_ID_AMD_CS5536_OTG		0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE		0x209A
 
+#define PCI_VENDOR_ID_CIRRUS			0x1013
+#define PCI_DEVICE_ID_CIRRUS_5446		0x00b8	/* Used by QEMU */
+
 #endif /* DEVICE_PCI_IDS_H */

Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile	2007-07-12 01:03:05 UTC (rev 447)
@@ -19,11 +19,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-STAGE0_MAINBOARD_OBJ :=\
-		$(obj)/mainboard/$(MAINBOARDDIR)/stage1.o 
 #
-# VPD or SIP ROM or ... how does NVIDIA call it?
+# VPD or SIP ROM or... how does NVIDIA call it?
 # Some space to cope with dirty southbridge tricks.
 # Do we want to put our own stuff there, too?
 #
@@ -38,12 +37,13 @@
 # The initram file is always uncompressed. It belongs into the mainboard
 # directory and is built from what was auto.c in v2.
 #
-INITRAM_OBJ =   $(obj)/mainboard/$(MAINBOARDDIR)/initram.o 
 
-$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ) 
+INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o
+
+$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ)
 	$(Q)# initram links against stage0
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ)  \
+	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ) \
 		--entry=main -o $(obj)/linuxbios.initram.o
 	$(Q)printf "  OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \
@@ -70,15 +70,15 @@
 	$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
 	$(Q)$(obj)/util/options/build_opt_tbl -b \
 		--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
-		--option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c 
+		--option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
 
 $(obj)/option_table: $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o
 	$(Q)printf "  OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(OBJCOPY) -O binary $< $@ 
+	$(Q)$(OBJCOPY) -O binary $< $@
 
-STAGE2_MAINBOARD_OBJ = vga.o 
+STAGE2_MAINBOARD_OBJ = vga.o
 
-STAGE2_CHIPSET_OBJ = 
+STAGE2_CHIPSET_OBJ =
 
 $(obj)/mainboard/$(MAINBOARDDIR)/%.o: $(src)/mainboard/$(MAINBOARDDIR)/%.c
 	$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)

Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c	2007-07-12 01:03:05 UTC (rev 447)
@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* no printk allowed until hardware is ready; hardware is ready */
 /** 
- * start up hardware needed for stage1
+ * Start up hardware needed for stage1.
+ *
+ * No printk() allowed until hardware is ready; hardware is ready.
+ * TODO: Fix above comment? It's unclear.
  */
 void hardware_stage1(void)
 {

Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c	2007-07-12 01:03:05 UTC (rev 447)
@@ -23,6 +23,7 @@
 #include <console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <string.h>
 #include <keyboard.h>
 
@@ -40,19 +41,21 @@
 }
 
 static struct device_operations qemuvga_pci_ops_dev = {
-	.constructor		 = default_device_constructor,
-	.phase3_scan		 = 0,
-	.phase4_read_resources	 = pci_dev_read_resources,
-	.phase4_set_resources	 = pci_dev_set_resources,
-	.phase4_enable_disable	 = setup_onboard,
-	.phase5_enable_resources = pci_dev_enable_resources,
-	.phase6_init		 = pci_dev_init,
-	.ops_pci		 = &pci_dev_ops_pci,
+	.constructor			= default_device_constructor,
+	.phase3_scan			= 0,
+	.phase4_read_resources		= pci_dev_read_resources,
+	.phase4_set_resources		= pci_dev_set_resources,
+	.phase4_enable_disable		= setup_onboard,
+	.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase6_init			= pci_dev_init,
+	.ops_pci			= &pci_dev_ops_pci,
 };
 
 struct constructor qemuvga_constructors[] = {
 	{.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = 0x1013,.device = 0x00b8}}},
+		.u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
+			      .device = PCI_DEVICE_ID_CIRRUS_5446}}},
 	 &qemuvga_pci_ops_dev},
+
 	{.ops = 0},
 };




From peter at stuge.se  Thu Jul 12 03:05:50 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 03:05:50 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <429EB3D7-44E4-447D-931C-2B83D73F9163@kernel.crashing.org>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711221134.27245.qmail@stuge.se>
	<429EB3D7-44E4-447D-931C-2B83D73F9163@kernel.crashing.org>
Message-ID: <20070712010550.22074.qmail@stuge.se>

On Thu, Jul 12, 2007 at 02:16:21AM +0200, Segher Boessenkool wrote:
> > 1 means combining flashrom and lar somehow.. Thoughts?
> 
> I think the boot block should be outside of the LAR completely.

Hmm. Interesting!


> A normal LinuxBIOS upgrade shouldn't touch the bootblock;

I agree. That's why lar should know about flash chip sector sizes.

And/or flashrom about larballs.

The idea is to rearrange the files in the larball apropriately for
the current flash chip before writing.


> that way, recovery code in there can help the user load a working
> image into flash after some screw-up, over a serial port or
> whatever.
> 
> This also handily solves the current problem :-)

But it creates another quite real problem for the first upgrade to LB
where we need to distribute the bootblock separately. I think that's
a _really_ undesirable scenario. :\ Especially since it will be the
common case for some time still.

One file is no file, two files are two files too many. ;)


//Peter



From uwe at hermann-uwe.de  Thu Jul 12 03:24:12 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 03:24:12 +0200
Subject: [LinuxBIOS] [PATCH][v3] Intel 82371FB/SB/AB/EB/MB southbridge
	support
Message-ID: <20070712012412.GG8025@greenwood>

See patch.

I used the name stage2.c for the code (not i82371xx.c) for now.

Shall we do that for all our chipsets and devices? A stage1.c file
for early init stuff, and stage2.c for the "normal" code?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Thu Jul 12 03:26:44 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 12 Jul 2007 03:26:44 +0200
Subject: [LinuxBIOS] r448 - in LinuxBIOSv3: arch/x86/geodelx
	include/arch/x86 northbridge/amd/geodelx southbridge/amd/cs5536
Message-ID: <mailman.514.1355071132.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-12 03:26:43 +0200 (Thu, 12 Jul 2007)
New Revision: 448

Modified:
   LinuxBIOSv3/arch/x86/geodelx/cpu.c
   LinuxBIOSv3/arch/x86/geodelx/geodelx.c
   LinuxBIOSv3/arch/x86/geodelx/stage1.c
   LinuxBIOSv3/include/arch/x86/amd_geodelx.h
   LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c
   LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c
   LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
   LinuxBIOSv3/northbridge/amd/geodelx/raminit.h
   LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c
   LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c
   LinuxBIOSv3/southbridge/amd/cs5536/stage1.c
Log:
Remove some include files which are not required (and add some which are).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: LinuxBIOSv3/arch/x86/geodelx/cpu.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/cpu.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/arch/x86/geodelx/cpu.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -29,7 +29,6 @@
  */
 
 #include <console.h>
-#include <string.h>
 #include <device/device.h>
 #include <lib.h>
 #include <io.h>
@@ -103,5 +102,6 @@
 		/* TODO: This is incorrect, these are _not_ PCI IDs! */
 		.u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},
 	 .ops = &geodelx_cpuops},
+
 	{.ops = 0},
 };

Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -23,9 +23,6 @@
 #include <types.h>
 #include <lib.h>
 #include <console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
 #include <msr.h>
 #include <io.h>
 #include <hlt.h>

Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -20,14 +20,8 @@
 
 #include <types.h>
 #include <lib.h>
-#include <console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
 #include <msr.h>
-#include <io.h>
 #include <amd_geodelx.h>
-#include <spd.h>
 
 static struct msrinit {
 	u32 msrnum;

Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h	2007-07-12 01:26:43 UTC (rev 448)
@@ -25,6 +25,11 @@
 #ifndef CPU_AMD_LXDEF_H
 #define CPU_AMD_LXDEF_H
 
+#ifndef __ASSEMBLER__
+#include <types.h>
+#include <io.h>
+#endif
+
 #define CPU_ID_1_X				0x00000560	/* Stepping ID 1.x CPUbug fix to change it to 5A0 */
 #define CPU_ID_2_0				0x000005A1
 #define CPU_ID_3_0				0x000005A2

Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -19,15 +19,11 @@
  */
 
 #include <types.h>
-#include <lib.h>
 #include <console.h>
-#include <post_code.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <string.h>
 #include <msr.h>
-#include <io.h>
 #include <amd_geodelx.h>
 
 /* Here is programming for the various MSRs. */

Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -19,14 +19,9 @@
  */
 
 #include <types.h>
-#include <lib.h>
 #include <console.h>
 #include <post_code.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
 #include <msr.h>
-#include <io.h>
 #include <cpu.h>
 #include <amd_geodelx.h>
 

Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -22,9 +22,6 @@
 #include <lib.h>
 #include <console.h>
 #include <post_code.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
 #include <msr.h>
 #include <spd.h>
 #include <io.h>

Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.h
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/raminit.h	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.h	2007-07-12 01:26:43 UTC (rev 448)
@@ -18,6 +18,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#ifndef NORTHBRIDGE_AMD_GEODELX_RAMINIT_H
+#define NORTHBRIDGE_AMD_GEODELX_RAMINIT_H
+
+#include <types.h>
+
 void sdram_set_registers(void);
 void sdram_set_spd_registers(u8 dimm0, u8 dimm1);
 void sdram_enable(u8 dimm0, u8 dimm1);
+
+#endif /* NORTHBRIDGE_AMD_GEODELX_RAMINIT_H */

Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -21,13 +21,10 @@
 #include <lib.h>
 #include <console.h>
 #include <post_code.h>
-#include <device/device.h>
 #include <device/pci.h>
-#include <string.h>
 #include <msr.h>
-#include <io.h>
 #include <amd_geodelx.h>
-#include <cpu.h>
+#include <cpu.h>		// TODO: Move rtc_init() etc. to legacy.h
 #include <device/pci_ids.h>
 #include <statictree.h>
 #include "cs5536.h"

Modified: LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <types.h>
 #include <console.h>
 #include <io.h>
 #include "cs5536.h"

Modified: LinuxBIOSv3/southbridge/amd/cs5536/stage1.c
===================================================================
--- LinuxBIOSv3/southbridge/amd/cs5536/stage1.c	2007-07-12 01:03:05 UTC (rev 447)
+++ LinuxBIOSv3/southbridge/amd/cs5536/stage1.c	2007-07-12 01:26:43 UTC (rev 448)
@@ -17,8 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <console.h>
-#include <io.h>
+#include <types.h>
 #include <msr.h>
 #include <amd_geodelx.h>
 #include "cs5536.h"




From uwe at hermann-uwe.de  Thu Jul 12 03:27:01 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 03:27:01 +0200
Subject: [LinuxBIOS] [PATCH][v3] geodelx: Remove useless includes
In-Reply-To: <20070711232321.5931.qmail@stuge.se>
References: <20070711202029.GE8025@greenwood>
	<20070711232321.5931.qmail@stuge.se>
Message-ID: <20070712012701.GH8025@greenwood>

On Thu, Jul 12, 2007 at 01:23:21AM +0200, Peter Stuge wrote:
> On Wed, Jul 11, 2007 at 10:20:29PM +0200, Uwe Hermann wrote:
> > Remove some include files which are not required (and add some which are).
> > 
> > Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> Acked-by: Peter Stuge <peter at stuge.se>

Thanks, r448.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Jul 12 03:44:23 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 03:44:23 +0200
Subject: [LinuxBIOS] [PATCH][v3] Merge hlt() into cpu.h (svn resync)
Message-ID: <20070712014423.GI8025@greenwood>

See patch.

Having an extra file just for the tiny hlt() is really not required.

Btw, why does die() do an endless loop around hlt()? Is there a reason
a hlt() will _not_ immediately halt the CPU? Can that happen?

If so, shall we move the loop into hlt() itself?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Jul 12 03:45:02 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 03:45:02 +0200
Subject: [LinuxBIOS] [PATCH] Add support for 17 new SMSC Super
	I/O	devices
In-Reply-To: <20070707191814.GA5859@greenwood>
References: <20070707191814.GA5859@greenwood>
Message-ID: <20070712014502.GJ8025@greenwood>

On Sat, Jul 07, 2007 at 09:18:14PM +0200, Uwe Hermann wrote:
> here's a new generic driver for SMSC Super I/O chips which should put an
> end to the copy+paste style of development when it comes to Super I/O
> code in LinuxBIOS and massively reduce the amount of duplicated code.

*ping*

Comments, reviews, acks?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From peter at stuge.se  Thu Jul 12 04:27:46 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 04:27:46 +0200
Subject: [LinuxBIOS] [PATCH][v3] Merge hlt() into cpu.h (svn resync)
In-Reply-To: <20070712014423.GI8025@greenwood>
References: <20070712014423.GI8025@greenwood>
Message-ID: <20070712022746.2410.qmail@stuge.se>

On Thu, Jul 12, 2007 at 03:44:23AM +0200, Uwe Hermann wrote:
> Btw, why does die() do an endless loop around hlt()? Is there a
> reason a hlt() will _not_ immediately halt the CPU? Can that
> happen?

It should halt, but the CPU may wake up again and continue executing
if an interrupt arrives. All should be masked, but you never know..


> If so, shall we move the loop into hlt() itself?

I don't think so. hlt() is just a C wrapper around the instruction.

Eventually I imagine building a panic room into die() so that
recovery can be made via console on fatal errors. Ideally with
some kind of stub for debugging stage0 and definately one for
initram.


> Merge hlt() into cpu.h where it belongs. Add some documentation.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Thu Jul 12 04:29:13 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 04:29:13 +0200
Subject: [LinuxBIOS] [PATCH][v3] Intel 82371FB/SB/AB/EB/MB southbridge
	support
In-Reply-To: <20070712012412.GG8025@greenwood>
References: <20070712012412.GG8025@greenwood>
Message-ID: <20070712022913.2716.qmail@stuge.se>

On Thu, Jul 12, 2007 at 03:24:12AM +0200, Uwe Hermann wrote:
> I used the name stage2.c for the code (not i82371xx.c) for now.
> 
> Shall we do that for all our chipsets and devices? A stage1.c file
> for early init stuff, and stage2.c for the "normal" code?

Does it scale? Will we be able to tell different stage2.o files from
each other when linking etc?


//Peter



From corey.osgood at gmail.com  Thu Jul 12 05:18:06 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 11 Jul 2007 23:18:06 -0400
Subject: [LinuxBIOS] [PATCH] Add support for 17 new SMSC
	Super	I/O	devices
In-Reply-To: <20070712014502.GJ8025@greenwood>
References: <20070707191814.GA5859@greenwood> <20070712014502.GJ8025@greenwood>
Message-ID: <46959D6E.1030306@gmail.com>

Uwe Hermann wrote:
> On Sat, Jul 07, 2007 at 09:18:14PM +0200, Uwe Hermann wrote:
>   
>> here's a new generic driver for SMSC Super I/O chips which should put an
>> end to the copy+paste style of development when it comes to Super I/O
>> code in LinuxBIOS and massively reduce the amount of duplicated code.
>>     
>
> *ping*
>
> Comments, reviews, acks?
>
>
> Uwe.
>   
Whoops, could have sworn I'd already sent this. It looked good to me,
I'll test it out on lpc47b272 when I get a chance.

Acked-by: Corey Osgood <corey.osgood at gmail.com>



From shirishag75 at gmail.com  Thu Jul 12 05:19:52 2007
From: shirishag75 at gmail.com (shirish)
Date: Thu, 12 Jul 2007 08:49:52 +0530
Subject: [LinuxBIOS] [OT]Using KiB instead of KB in linuxbios
Message-ID: <511f47f50707112019n5a40379ered23d18d5c8ce0ba@mail.gmail.com>

Hi all,
      I'm no developer but just a simple user. One thing which would
be nice to see is
having explicit nomenclature to say 1024 bytes instead of confusion
between 1000 bytes & 1024 bytes. http://en.wikipedia.org/wiki/KiB
explains it much better than I can. While all the developers may be
able to differentiate or know when any kind of testing takes place on
general motherboards it would arise in difficulties. If however you
guys took the KiB it makes things that much more simpler for everybody
to understand. Dunno if you guys use the nomenclature internally or
not.
         Please lemme know. Cheers!
-- 
          Shirish Agarwal
  This email is licensed under http://creativecommons.org/licenses/by-nc/3.0/

065C 6D79 A68C E7EA 52B3  8D70 950D 53FB 729A 8B17



From corey.osgood at gmail.com  Thu Jul 12 05:27:26 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 11 Jul 2007 23:27:26 -0400
Subject: [LinuxBIOS] [PATCH][v3] Intel 82371FB/SB/AB/EB/MB southbridge
 support
In-Reply-To: <20070712022913.2716.qmail@stuge.se>
References: <20070712012412.GG8025@greenwood>
	<20070712022913.2716.qmail@stuge.se>
Message-ID: <46959F9E.3070109@gmail.com>

Peter Stuge wrote:
> On Thu, Jul 12, 2007 at 03:24:12AM +0200, Uwe Hermann wrote:
>   
>> I used the name stage2.c for the code (not i82371xx.c) for now.
>>
>> Shall we do that for all our chipsets and devices? A stage1.c file
>> for early init stuff, and stage2.c for the "normal" code?
>>     
>
> Does it scale? Will we be able to tell different stage2.o files from
> each other when linking etc?

Good point. Should we go with stage2-82371xx.c or similar? Also, with
stuff like SMBus where in v2 we have a header that stores a bunch of
functions used in both "stage1" and "stage2" (example: nvidia mcp55,
intel i82801xx, etc), how do we define naming of those?

-Corey



From shirishag75 at gmail.com  Thu Jul 12 05:45:35 2007
From: shirishag75 at gmail.com (shirish)
Date: Thu, 12 Jul 2007 09:15:35 +0530
Subject: [LinuxBIOS] [OT]Using KiB instead of KB in linuxbios
Message-ID: <511f47f50707112045o71d1e2a4r89149095f1a993c8@mail.gmail.com>

> Message: 8
> Date: Thu, 12 Jul 2007 08:49:52 +0530
> From: shirish <shirishag75 at gmail.com>
> Subject: [LinuxBIOS] [OT]Using KiB instead of KB in linuxbios
> To: linuxbios at linuxbios.org
> Message-ID:
>         <511f47f50707112019n5a40379ered23d18d5c8ce0ba at mail.gmail.com>
> Content-Type: text/plain; charset=UTF-8; format=flowed
>
> Hi all,
>       I'm no developer but just a simple user. One thing which would
> be nice to see is
> having explicit nomenclature to say 1024 bytes instead of confusion
> between 1000 bytes & 1024 bytes. http://en.wikipedia.org/wiki/KiB
> explains it much better than I can. While all the developers may be
> able to differentiate or know when any kind of testing takes place on
> general motherboards it would arise in difficulties. If however you
> guys took the KiB it makes things that much more simpler for everybody
> to understand. Dunno if you guys use the nomenclature internally or
> not.
>          Please lemme know. Cheers!
> --
>           Shirish Agarwal
>   This email is licensed under http://creativecommons.org/licenses/by-nc/3.0/
>
> 065C 6D79 A68C E7EA 52B3  8D70 950D 53FB 729A 8B17

Me bad, what I wanted to say was that while the developers would know
the naunces of 1KB & 1 KiB when giving support to users who might not
be so technically sound as you it might arise to problems esp. as I
see you guys are actively working on v3 now (yay!).

 [More OT]  Looking forward to more news, screenshots, videos the
works when v3   is near to ready or ready [/More OT] ;)

-- 
          Shirish Agarwal
  This email is licensed under http://creativecommons.org/licenses/by-nc/3.0/

065C 6D79 A68C E7EA 52B3  8D70 950D 53FB 729A 8B17



From svn at openbios.org  Thu Jul 12 05:46:01 2007
From: svn at openbios.org (LinuxBIOS)
Date: Thu, 12 Jul 2007 03:46:01 -0000
Subject: [LinuxBIOS]  #85: fix milli/mega and 1000/1024 ambiguities
Message-ID: <042.6fb6dd8111960c771a02aa1cb962cfb3@openbios.org>

#85: fix milli/mega and 1000/1024 ambiguities
---------------------------------+------------------------------------------
   Reporter:  stuge              |          Owner:  somebody        
       Type:  defect             |         Status:  new             
   Priority:  minor              |      Milestone:  Going mainstream
  Component:  code               |        Version:                  
   Keywords:  usability          |   Dependencies:                  
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 Do not confuse milli (m) with mega (M) in any output or input.
 Similarly try to clarify whether k means 1000 or 1024 and M means 1000000
 or 1024*1024 whenever it is not perfectly clear from context.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/85>
LinuxBIOS <http://www.linuxbios.org/>

From peter at stuge.se  Thu Jul 12 05:46:36 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 05:46:36 +0200
Subject: [LinuxBIOS] [OT]Using KiB instead of KB in linuxbios
In-Reply-To: <511f47f50707112019n5a40379ered23d18d5c8ce0ba@mail.gmail.com>
References: <511f47f50707112019n5a40379ered23d18d5c8ce0ba@mail.gmail.com>
Message-ID: <20070712034636.13831.qmail@stuge.se>

Hi shirish,

On Thu, Jul 12, 2007 at 08:49:52AM +0530, shirish wrote:
>       I'm no developer but just a simple user. One thing which would
> be nice to see is having explicit nomenclature to say 1024 bytes
> instead of confusion between 1000 bytes & 1024 bytes.

Not so off-topic.

I just suggested the very same thing for a help message in lar, a
utility to be used with v3 of LB. That is; to explicity state 1024
rather than abbreviating it with K.


> While all the developers may be able to differentiate or know when
> any kind of testing takes place on general motherboards it would
> arise in difficulties. If however you guys took the KiB it makes
> things that much more simpler for everybody to understand. Dunno if
> you guys use the nomenclature internally or not.

For all our purposes except one, the multipliers are always 1024 and
1024*1024=1048576, and never 1000 and 1000000.

No rule without an exception I guess. For time or frequencies, e.g.
CPU MHz, M always means 1000000 and k always means 1000.

Sometimes we can be sloppy with m vs. M too. m means milli and M
means mega. But since milli is less than 1 it is usually clear from
context that it is not applicable. For example with memory - it's not
possible to have less than 1 byte of memory, so 1mb must mean
megabyte even though it is strictly 1 millibyte. (1/1000 byte)

Thanks for pointing this out. We should fix any and all ambiguities.

I've filed a ticket in trac.


//Peter



From darmawan.salihun at gmail.com  Thu Jul 12 09:19:47 2007
From: darmawan.salihun at gmail.com (Darmawan Salihun)
Date: Thu, 12 Jul 2007 14:19:47 +0700
Subject: [LinuxBIOS] Winflashrom -- Current Status
In-Reply-To: <20070702193703.21913.qmail@stuge.se>
References: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>	<4688C2BF.2040600@gmail.com>
	<20070702193703.21913.qmail@stuge.se>
Message-ID: <4695D613.6080603@gmail.com>

Peter Stuge wrote:
> Hi,
>
> On Mon, Jul 02, 2007 at 04:17:51PM +0700, Darmawan Salihun wrote:
>> The diff for the latest winflashrom code is attached.
>
> The diff is reversed, so a bit hard to read. Please do svn diff
> -r1:HEAD next time.
>
> Also, instead of commenting out non-Windows code and adding new
> Windows-only code, please suggest good ways to abstract the code.
>

There are a few things that need to be abstracted in order to unify
the Unix-based code and the Windows version. After thinking about the
solution for a while I found that it maybe better if I made a kind of
abstraction layer for the "incompatible" parts that only impose minor
changes to the current flashrom code base prior to doing a "redesign"
to the overall source code to address the Windows-*NIX
"incompatibilities". This is only a temporary workaround.
The most obvious parts are:

1. Libpci abstraction for Windows. In this case the libpci logic in
   the flashrom code base need not be changed. I will make a "libpci
   for Windows" that doesn't change the logic within the current
   flashrom code. Even after the redesign, we might choose to preserve
   this part.

2. Direct I/O access abstraction. I think, in the short term, I will just
   provide a simple direct I/O "compatibility layer" for inX,outX family of
   functions in the winflashrom.
 

3. File I/O abstraction. We might need this because fopen(..) behaves
   not exactly the same in Windows and *NIX.


Remember that this is only a short term solution. Anyway, do you think
it's good to make a branch for the current flashrom code in order to
develop the unified (redesigned) flashrom that will host a single
code base for both the *NIX version and winflashrom?
I mean the branch will be merged into the trunk once we have a well tested
unified version of flashrom/winflashrom.

Another note that I have difficulty in limiting the direct I/O access
in the current driver because I don't know exactly which port to give
access to and which one to block. Below is what I've found from the current
flashrom code so far. I/O port usage:

       0x2E (Winbond W836_INDEX port)
       0x2F (Winbond W836_DATA port)
       0x4E
       0x4F
       0xCD6
       0xCD7
       0xCFC - 0xCFF (PCI I/O port on x86)
       0xC6F
       a "base + 0x4D" in Via Epia motherboard
       0xE1
       0xE800 (what port is this? )
       0xE801
       0xE802
       0xE803
       0xE804
       0xE807
       0xEB
       0xFF
      
       I couldn't conclude the the I/O port ranges to open from the port
list above because there is still unknown (I think it's dynamically 
relocatable) I/O port such as the one used by EPIA board. 
Any explanation on this issue?

That's all for now.

Regards,
Darmawan Salihun










From tiansm at lemote.com  Thu Jul 12 09:26:07 2007
From: tiansm at lemote.com (Songmao Tian)
Date: Thu, 12 Jul 2007 15:26:07 +0800
Subject: [LinuxBIOS] about cs5536 interrupt ack
In-Reply-To: <Pine.LNX.4.64N.0707111634430.26459@blysk.ds.pg.gda.pl>
References: <4694A495.1050006@lemote.com>
	<Pine.LNX.4.64N.0707111347360.26459@blysk.ds.pg.gda.pl>
	<4694F4EB.8040000@lemote.com>
	<Pine.LNX.4.64N.0707111634430.26459@blysk.ds.pg.gda.pl>
Message-ID: <4695D78F.8010806@lemote.com>

8259 problem  seems to be done with the attached patch, IDE hung seems 
to be the dma setting problem.

Thanks all for your advise, comments. I have learned a lot. now I 
continue to trace down the IDE problem.

Mao

Maciej W. Rozycki wrote:
> On Wed, 11 Jul 2007, Songmao Tian wrote:
>
>   
>>> Huh?  Have you managed to find an 8259A clone *that* broken?  So what does
>>> it return if you write 0xc to the address 0x20 in the I/O port space and
>>> then read back from that location?  You should complain to the 
>>>   
>>>       
>> It's the value of IRR, so guess IRR. AMD has well documented cs5536, I
>> appreciate that.
>>     
>
>  Indeed.  I am surprised they have decided to drop the poll command -- it 
> surely does not require much logic as it mostly reuses what's used to 
> produce the vector anyway and it is commonly used when 8259A 
> implementations are interfaced to non-i386 processors.  PPC is another 
> example.
>
>   
>>> More or less -- 3-5 should probably be the outcome of a single read
>>> transaction from the north bridge.  I.e. you issue a read to a "magic"
>>> location, 3-5 happen, and the data value returned is the vector presented by
>>> the interrupt controller on the PCI bus.
>>>   
>>>       
>> yeah, we can implement a register in north bridge.
>>     
>
>  Strictly speaking it would not be a register, but a "PCI INTA address 
> space" much like PCI memory or I/O port address spaces.  Though as the 
> former ignores addresses driven on the bus, the space occupied does not 
> have to be extensive -- I would assume whatever slot size is available 
> with the address decoder you have implemented would do.
>
>   
>>> You can still dispatch interrupts manually by examining the IRR register,
>>> but having a way to ask the 8259A's prioritiser would be nice.  Although
>>> given such a lethal erratum you report I would not count on the prioritiser
>>> to provide any useful flexibility...
>>>   
>>>       
>> yeah, that's a straight thought, tried but failed:(, patch followed.
>>     
>
>  You may have to modify other functions from arch/mips/kernel/i8259.c; 
> yes, this makes the whole experience not as pretty as one would hope...
>
>   Maciej
>
>
>
>   

-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: diff
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20070712/ebbec9ca/attachment.ksh>

From peter at stuge.se  Thu Jul 12 09:50:11 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 09:50:11 +0200
Subject: [LinuxBIOS] PATCH: mkdirp() error on new directory outside given
	parent
Message-ID: <20070712075011.16157.qmail@stuge.se>

Have a look.

I haven't gotten lar to build, but the function works in a separate
test program.


//Peter
-------------- next part --------------
Make mkdirp() abort directory creation and return an error if a directory
in dirpath is located outside the specified parent directory. Use the parent
"/" to allow new directories anywhere.

Signed-off-by: Peter Stuge <peter at stuge.se>

Index: util/lar/lib.c
===================================================================
--- util/lar/lib.c	(revision 447)
+++ util/lar/lib.c	(working copy)
@@ -24,6 +24,7 @@
 #include <strings.h>
 #include <unistd.h>
 #include <dirent.h>
+#include <errno.h>
 #include <sys/stat.h>
 #include <sys/types.h>
 
@@ -33,42 +34,72 @@
 
 static struct file *files = NULL;
 
-int mkdirp(const char *dirpath, mode_t mode)
+/**
+ * Create a new directory including any missing parent directories.
+ *
+ * @param parent Return an error if a new directory would be created outside
+ * this directory. Pass "/" to allow new directories to be created anywhere.
+ * @param dirpath The new directory that should be created.
+ * @param mode Permissions to use for newly created directories.
+ */
+int mkdirp(const char *parent, const char *dirpath, mode_t mode)
 {
-	char *pos, *currpath, *path;
-	char cwd[MAX_PATH];
-	int ret = 0;
+	int ret = -1;
+	size_t dirsep, parlen, sublen;
+	char c, *r, *path = NULL, *subdir, rpar[PATH_MAX], rsub[PATH_MAX];
 
+	if (!dirpath) {
+		fprintf(stderr, "mkdirp: No new directory specified\n");
+		goto done;
+	}
+
 	path = strdup(dirpath);
 	if (!path) {
-		fprintf(stderr, "Out of memory.\n");
-		exit(1);
+		perror("Duplicate new directory failed:");
+		goto done;
 	}
 
-	currpath = path;
-
-	if (!getcwd(cwd, MAX_PATH)) {
-		free(path);
-		fprintf(stderr, "Error getting cwd.\n");
-		return -1;
+	if (NULL == realpath(parent, rpar)) {
+		fprintf(stderr, "realpath(%s) failed: %s\n", parent,
+			strerror(errno));
+		goto done;
 	}
+	parlen = strlen(rpar);
 
-	do {
-		pos = index(currpath, '/');
-		if (pos)
-			*pos = 0;
+	for (subdir = path, dirsep = 0; subdir[dirsep]; subdir += dirsep) {
+		dirsep = strcspn(subdir, "/\\");
+		if (!dirsep) {
+			subdir++;
+			continue;
+		}
 
-		/* printf("cp=%s\n", currpath); */
-		mkdir(currpath, mode);
-		ret = chdir(currpath);
+		c = subdir[dirsep];
+		subdir[dirsep] = 0;
+		r = realpath(path, rsub);
+		sublen = strlen(rsub);
+		if (NULL == r) {
+			if(ENOENT != errno) {
+				fprintf(stderr, "realpath(%s) failed: %s\n",
+					path, strerror(errno));
+				goto done;
+			}
+		} else if (sublen < parlen || strncmp(rpar, rsub, parlen)) {
+			fprintf(stderr, "Abort: %s is outside %s\n", dirpath,
+				parent);
+			goto done;
+		}
+		if(-1 == mkdir(path, mode) && EEXIST != errno) {
+			fprintf(stderr, "mkdir(%s): %s\n", path,
+				strerror(errno));
+			goto done;
+		}
+		subdir[dirsep] = c;
+	}
+	ret = 0;
 
-		if (pos)
-			currpath = pos + 1;
-	} while (pos && !ret && strlen(currpath));
-
-	chdir(cwd);
-	free(path);
-
+done:
+	if (path)
+		free(path);
 	return ret;
 }
 
Index: util/lar/extract.c
===================================================================
--- util/lar/extract.c	(revision 447)
+++ util/lar/extract.c	(working copy)
@@ -119,7 +119,7 @@
 		if (pos) {
 			pos[1] = 0;
 			/* printf("Pathname %s\n",pathname); */
-			mkdirp(pathname, 0755);
+			mkdirp(".", pathname, 0755);
 		}
 		free(pathname);
 
Index: util/lar/lib.h
===================================================================
--- util/lar/lib.h	(revision 447)
+++ util/lar/lib.h	(working copy)
@@ -41,7 +41,7 @@
 char *get_bootblock(void);
 
 /* prototypes for lib.c functions */
-int mkdirp(const char *dirpath, mode_t mode);
+int mkdirp(const char *parent, const char *dirpath, mode_t mode);
 
 int add_files(const char *name);
 int add_file_or_directory(const char *name);

From nathanael at gnat.ca  Thu Jul 12 10:05:26 2007
From: nathanael at gnat.ca (Nathanael D. Noblet)
Date: Thu, 12 Jul 2007 02:05:26 -0600
Subject: [LinuxBIOS] Add a top level target for LAR
In-Reply-To: <20070711230847.3685.qmail@stuge.se>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070711181204.22915.qmail@stuge.se>
	<20070711183009.GI20885@cosmic.amd.com>
	<20070711230847.3685.qmail@stuge.se>
Message-ID: <4695E0C6.9070904@gnat.ca>

Peter Stuge wrote:
> On Wed, Jul 11, 2007 at 12:30:09PM -0600, Jordan Crouse wrote:
>>> I would expect lar to be a target in util/
>> I agree.  But as its written right now, the makefiles depend on
>> the rules in the toplevel directory
> 
> Ah. I see.
> 
> This is another reason to move util/ out to it's own home.
> 
> What was decided? I'm not religious about a separate repo but I
> do think it's appropriate since it's not really a part of LB.
> 

And since you are using svn, wouldn't it be fairly trivial to patch it 
in as a svn:externals?



From peter at stuge.se  Thu Jul 12 10:05:56 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 10:05:56 +0200
Subject: [LinuxBIOS] Winflashrom -- Current Status
In-Reply-To: <4695D613.6080603@gmail.com>
References: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>
	<4688C2BF.2040600@gmail.com> <20070702193703.21913.qmail@stuge.se>
	<4695D613.6080603@gmail.com>
Message-ID: <20070712080556.18303.qmail@stuge.se>

On Thu, Jul 12, 2007 at 02:19:47PM +0700, Darmawan Salihun wrote:
> 1. Libpci abstraction for Windows. In this case the libpci logic in
> the flashrom code base need not be changed. I will make a "libpci
> for Windows" that doesn't change the logic within the current
> flashrom code. Even after the redesign, we might choose to preserve
> this part.

Perhaps you can make a small libpci-win32 package out of it? I'm sure
others would appreciate it as well.


> 2. Direct I/O access abstraction. I think, in the short term, I
> will just provide a simple direct I/O "compatibility layer" for
> inX,outX family of functions in the winflashrom.

This can just be some #defines, use some functions in Windows and the
normal in()/out() stuff otherwise.

Put this in some header:

#ifndef __WIN32__
#define my_inb(a,b) inb(a,b)
#define my_inw(a,b) inw(a,b)
#define my_inl(a,b) inl(a,b)
#endif /* __WIN32__ */

..and then implement my_in[bwl]() in a .c file together with all the
other stuff needed for Windows. Have a conditional in the Makefile to
build and link that file on Windows only. Voila, done.


> 3. File I/O abstraction. We might need this because fopen(..)
> behaves not exactly the same in Windows and *NIX.

C89 has the b mode so just change all fopen calls to use "rb", "wb",
"ab", "rb+", "wb+" and "ab+" respectively.


> do you think it's good to make a branch for the current flashrom
> code in order to develop the unified (redesigned) flashrom that
> will host a single code base for both the *NIX version and
> winflashrom?

Is that really needed? Just submit nice and neat patches against
trunk to get them reviewed, acked and applied.


> Another note that I have difficulty in limiting the direct I/O
> access in the current driver because I don't know exactly which
> port to give access to and which one to block. Below is what I've
> found from the current flashrom code so far. I/O port usage:
> 
>        0x2E (Winbond W836_INDEX port)
>        0x2F (Winbond W836_DATA port)
>        0x4E
>        0x4F
>        0xCD6
>        0xCD7
>        0xCFC - 0xCFF (PCI I/O port on x86)
>        0xC6F
>        a "base + 0x4D" in Via Epia motherboard
>        0xE1
>        0xE800 (what port is this? )
>        0xE801
>        0xE802
>        0xE803
>        0xE804
>        0xE807
>        0xEB
>        0xFF
>       
> I couldn't conclude the the I/O port ranges to open from the port
> list above because there is still unknown (I think it's dynamically
> relocatable) I/O port such as the one used by EPIA board.
> Any explanation on this issue?

This list is still much better than allowing everything!

As for the EPIA board, well, where is that base specified? In a PCI
config register or where?


//Peter



From patrick at georgi-clan.de  Thu Jul 12 10:24:03 2007
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 12 Jul 2007 10:24:03 +0200
Subject: [LinuxBIOS] PATCH: mkdirp() error on new directory outside
	given parent
In-Reply-To: <20070712075011.16157.qmail@stuge.se>
References: <20070712075011.16157.qmail@stuge.se>
Message-ID: <f74ogp$1t0$1@sea.gmane.org>

Peter Stuge wrote:
> -int mkdirp(const char *dirpath, mode_t mode)
> +/**
> + * Create a new directory including any missing parent directories.
> + *
> + * @param parent Return an error if a new directory would be created outside
> + * this directory. Pass "/" to allow new directories to be created anywhere.
> + * @param dirpath The new directory that should be created.
> + * @param mode Permissions to use for newly created directories.
> + */
> +int mkdirp(const char *parent, const char *dirpath, mode_t mode)
conflicts with: (where libgen is a compatibility dummy in solaris 10 at 
least, deferring that object to libc, so it always conflicts)

String Pattern-Matching Library Functions            mkdirp(3GEN)

NAME
      mkdirp, rmdirp - create or remove directories in a path

SYNOPSIS
      cc [ flag ... ] file ... -lgen [ library ... ]
      #include <libgen.h>

      int mkdirp(const char *path, mode_t mode);
[...]


Regards,
Patrick Georgi




From stepan at coresystems.de  Thu Jul 12 10:43:47 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 10:43:47 +0200
Subject: [LinuxBIOS] r447 - in LinuxBIOSv3:
	include/device	mainboard/emulation/qemu-x86
Message-ID: <20070712084347.GA30653@coresystems.de>

* svn at openbios.org <svn at openbios.org> [070712 03:03]:
> Some minor cosmetic fixes (trivial).

> -/*
> - *	PCI Class, Vendor and Device IDs
> - *
> - *	Please keep sorted.
> - */
> -

Why is removing comments considered a cosmetic fix?



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul 12 10:53:17 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 10:53:17 +0200
Subject: [LinuxBIOS] r447 - in LinuxBIOSv3:
	include/device	mainboard/emulation/qemu-x86
Message-ID: <20070712085317.GB30653@coresystems.de>

* svn at openbios.org <svn at openbios.org> [070712 03:03]:
> Some minor cosmetic fixes (trivial).
> -/* no printk allowed until hardware is ready; hardware is ready */
>  /** 
> - * start up hardware needed for stage1
> + * Start up hardware needed for stage1.
> + *
> + * No printk() allowed until hardware is ready; hardware is ready.
> + * TODO: Fix above comment? It's unclear.
>   */

I don't think it is. Without hardware to print on, no printk. What's
unclear with that?

I also think this should not go into the doxygen comment.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul 12 10:57:08 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 10:57:08 +0200
Subject: [LinuxBIOS] PATCH: mkdirp() error on new directory
	outside	given parent
In-Reply-To: <20070712075011.16157.qmail@stuge.se>
References: <20070712075011.16157.qmail@stuge.se>
Message-ID: <20070712085708.GD30653@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 09:50]:
> Have a look.
> 
> I haven't gotten lar to build, but the function works in a separate
> test program.
> 
> 
> //Peter

> Make mkdirp() abort directory creation and return an error if a directory
> in dirpath is located outside the specified parent directory. Use the parent
> "/" to allow new directories anywhere.
 
Are you trying to avoid an exploit, or what is it needed for?

mkdirp should not be changed to take other parameters than this: 
http://docsun.cites.uiuc.edu/sun_docs/C/solaris_9/SUNWaman/hman3gen/mkdirp.3gen.html


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From joe at smittys.pointclark.net  Thu Jul 12 11:00:23 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Thu, 12 Jul 2007 05:00:23 -0400
Subject: [LinuxBIOS] Another dumb C question
Message-ID: <20070712050023.lspcpwen40swo0kg@www.smittys.pointclark.net>

Hello,
I have another newbie C question.
Is this the same as 2^9 ??

value = 9

(2 << (value - 1))

This will give me 512, but will it work no matter what "value" is?
Or does linuxbios already have a "to the power of" global function?

Thanks - Joe



From peter at stuge.se  Thu Jul 12 11:06:47 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 11:06:47 +0200
Subject: [LinuxBIOS] PATCH: mkdirp() error on new directory outside
	given parent
In-Reply-To: <f74ogp$1t0$1@sea.gmane.org>
References: <20070712075011.16157.qmail@stuge.se> <f74ogp$1t0$1@sea.gmane.org>
Message-ID: <20070712090647.26941.qmail@stuge.se>

Hey,

On Thu, Jul 12, 2007 at 10:24:03AM +0200, Patrick Georgi wrote:
> > +int mkdirp(const char *parent, const char *dirpath, mode_t mode)
> conflicts with: (where libgen is a compatibility dummy in solaris
> 10 at least, deferring that object to libc, so it always conflicts)
> 
>       int mkdirp(const char *path, mode_t mode);

Thanks!

New patch, rename mkdirp() to mkdirp_below(). :)

I just had a thought; parent and dirpath are currently treated as
either absolute or relative cwd but perhaps dirpath should always
be treated as absolute or relative parent instead?

mkdirp_below("subdir","x/y/z",077);

would create subdir/x/y/z. Feels much more intuitive, no?


//Peter
-------------- next part --------------
Replaces mkdirp() with mkdirp_below() that aborts directory creation and
returns an error if a part of dirpath is located outside the specified
parent directory. Use the parent "/" to allow new directories anywhere.

Signed-off-by: Peter Stuge <peter at stuge.se>

Index: util/lar/lib.c
===================================================================
--- util/lar/lib.c	(revision 447)
+++ util/lar/lib.c	(working copy)
@@ -24,6 +24,7 @@
 #include <strings.h>
 #include <unistd.h>
 #include <dirent.h>
+#include <errno.h>
 #include <sys/stat.h>
 #include <sys/types.h>
 
@@ -33,42 +34,80 @@
 
 static struct file *files = NULL;
 
-int mkdirp(const char *dirpath, mode_t mode)
+/**
+ * Create a new directory including any missing parent directories.
+ *
+ * NOTE: This function does not do complete path resolution as described in
+ * Linux path_resolution(2) and hence will fail for complex paths:
+ *
+ * e.g.: mkdirp_below("subdir", "subdir/../subdir/x", 0777);
+ *
+ * This call should create subdir/x, but since subdir/.. is outside subdir,
+ * the function will fail.
+ *
+ * @param parent Return an error if a new directory would be created outside
+ * this directory. Pass "/" to allow new directories to be created anywhere.
+ * @param dirpath The new directory that should be created.
+ * @param mode Permissions to use for newly created directories.
+ */
+int mkdirp_below(const char *parent, const char *dirpath, mode_t mode)
 {
-	char *pos, *currpath, *path;
-	char cwd[MAX_PATH];
-	int ret = 0;
+	int ret = -1;
+	size_t dirsep, parlen, sublen;
+	char c, *r, *path = NULL, *subdir, rpar[PATH_MAX], rsub[PATH_MAX];
 
+	if (!dirpath) {
+		fprintf(stderr, "mkdirp_below: No new directory specified\n");
+		goto done;
+	}
+
 	path = strdup(dirpath);
 	if (!path) {
-		fprintf(stderr, "Out of memory.\n");
-		exit(1);
+		perror("Duplicate new directory failed:");
+		goto done;
 	}
 
-	currpath = path;
-
-	if (!getcwd(cwd, MAX_PATH)) {
-		free(path);
-		fprintf(stderr, "Error getting cwd.\n");
-		return -1;
+	if (NULL == realpath(parent, rpar)) {
+		fprintf(stderr, "realpath(%s) failed: %s\n", parent,
+			strerror(errno));
+		goto done;
 	}
+	parlen = strlen(rpar);
 
-	do {
-		pos = index(currpath, '/');
-		if (pos)
-			*pos = 0;
+	for (subdir = path, dirsep = 0; subdir[dirsep]; subdir += dirsep) {
+		dirsep = strcspn(subdir, "/\\");
+		if (!dirsep) {
+			subdir++;
+			continue;
+		}
 
-		/* printf("cp=%s\n", currpath); */
-		mkdir(currpath, mode);
-		ret = chdir(currpath);
+		c = subdir[dirsep];
+		subdir[dirsep] = 0;
+		r = realpath(path, rsub);
+		sublen = strlen(rsub);
+		if (NULL == r) {
+			if(ENOENT != errno) {
+				fprintf(stderr, "realpath(%s) failed: %s\n",
+					path, strerror(errno));
+				goto done;
+			}
+		} else if (sublen < parlen || strncmp(rpar, rsub, parlen)) {
+			fprintf(stderr, "Abort: %s is outside %s\n", dirpath,
+				parent);
+			goto done;
+		}
+		if(-1 == mkdir(path, mode) && EEXIST != errno) {
+			fprintf(stderr, "mkdir(%s): %s\n", path,
+				strerror(errno));
+			goto done;
+		}
+		subdir[dirsep] = c;
+	}
+	ret = 0;
 
-		if (pos)
-			currpath = pos + 1;
-	} while (pos && !ret && strlen(currpath));
-
-	chdir(cwd);
-	free(path);
-
+done:
+	if (path)
+		free(path);
 	return ret;
 }
 
Index: util/lar/extract.c
===================================================================
--- util/lar/extract.c	(revision 447)
+++ util/lar/extract.c	(working copy)
@@ -119,7 +119,7 @@
 		if (pos) {
 			pos[1] = 0;
 			/* printf("Pathname %s\n",pathname); */
-			mkdirp(pathname, 0755);
+			mkdirp_below(".", pathname, 0755);
 		}
 		free(pathname);
 
Index: util/lar/lib.h
===================================================================
--- util/lar/lib.h	(revision 447)
+++ util/lar/lib.h	(working copy)
@@ -41,7 +41,7 @@
 char *get_bootblock(void);
 
 /* prototypes for lib.c functions */
-int mkdirp(const char *dirpath, mode_t mode);
+int mkdirp_below(const char *parent, const char *dirpath, mode_t mode);
 
 int add_files(const char *name);
 int add_file_or_directory(const char *name);

From stepan at coresystems.de  Thu Jul 12 11:08:20 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 11:08:20 +0200
Subject: [LinuxBIOS] [PATCH][v3] Move lar into global util/ directory
	+	svn:externals
In-Reply-To: <20070711202452.GF8025@greenwood>
References: <20070711202452.GF8025@greenwood>
Message-ID: <20070712090820.GB9439@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070711 22:24]:
> OK, not really a patch, but I think we can move lar into the global
> util/ directory and suck it into v3 via svn:externals.
> 
> That's a first step to make it independent of v3 (and to allow Jordan
> to use it in buildrom).
> 
> I'm waiting for comments or ACKs before doing this, though.


Will this drop the history? If so, strong NACK.

It is NOT a generic utility yet.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From peter at stuge.se  Thu Jul 12 11:09:26 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 11:09:26 +0200
Subject: [LinuxBIOS] PATCH: mkdirp() error on new directory
	outside	given parent
In-Reply-To: <20070712085708.GD30653@coresystems.de>
References: <20070712075011.16157.qmail@stuge.se>
	<20070712085708.GD30653@coresystems.de>
Message-ID: <20070712090926.27397.qmail@stuge.se>

On Thu, Jul 12, 2007 at 10:57:08AM +0200, Stefan Reinauer wrote:
> > Make mkdirp() abort directory creation and return an error if a
> > directory in dirpath is located outside the specified parent
>  
> Are you trying to avoid an exploit, or what is it needed for?

Right. But it was much more of a mess than I first thought. I forgot
that realpath() only works when the full path already exists.


> mkdirp should not be changed to take other parameters than this: 
> http://docsun.cites.uiuc.edu/sun_docs/C/solaris_9/SUNWaman/hman3gen/mkdirp.3gen.html

Aye.


//Peter



From peter at stuge.se  Thu Jul 12 11:11:15 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 11:11:15 +0200
Subject: [LinuxBIOS] r447 - in LinuxBIOSv3:
	include/device	mainboard/emulation/qemu-x86
In-Reply-To: <20070712085317.GB30653@coresystems.de>
References: <20070712085317.GB30653@coresystems.de>
Message-ID: <20070712091115.27711.qmail@stuge.se>

On Thu, Jul 12, 2007 at 10:53:17AM +0200, Stefan Reinauer wrote:
> > + * No printk() allowed until hardware is ready; hardware is ready.
> > + * TODO: Fix above comment? It's unclear.
> 
> I don't think it is. Without hardware to print on, no printk.
> What's unclear with that?

"hardware is ready" twice - is that just a mistake?


//Peter



From peter at stuge.se  Thu Jul 12 11:16:52 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 11:16:52 +0200
Subject: [LinuxBIOS] Another dumb C question
In-Reply-To: <20070712050023.lspcpwen40swo0kg@www.smittys.pointclark.net>
References: <20070712050023.lspcpwen40swo0kg@www.smittys.pointclark.net>
Message-ID: <20070712091652.28460.qmail@stuge.se>

On Thu, Jul 12, 2007 at 05:00:23AM -0400, Joseph Smith wrote:
> Hello,
> I have another newbie C question.
> Is this the same as 2^9 ??

Note that ^ means XOR in C. Exclusive or. Output 1 when only one
input bit is 1, but not both.

  00100011
^ 10101010
----------
  10001001



> value = 9
> 
> (2 << (value - 1))
> 
> This will give me 512, but will it work no matter what "value" is?

Yep.


> Or does linuxbios already have a "to the power of" global function?

No pow() in LB and the pow() in libm uses doubles so it's bad for the
task.


Bit shift is fine methinks but I would suggest:

(1 << value)

instead of

(2 << (value - 1))


//Peter



From stepan at coresystems.de  Thu Jul 12 11:17:30 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 11:17:30 +0200
Subject: [LinuxBIOS] [PATCH][v3] Intel 82371FB/SB/AB/EB/MB
	southbridge	support
In-Reply-To: <20070712022913.2716.qmail@stuge.se>
References: <20070712012412.GG8025@greenwood>
	<20070712022913.2716.qmail@stuge.se>
Message-ID: <20070712091730.GC9439@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 04:29]:
> On Thu, Jul 12, 2007 at 03:24:12AM +0200, Uwe Hermann wrote:
> > I used the name stage2.c for the code (not i82371xx.c) for now.
> > 
> > Shall we do that for all our chipsets and devices? A stage1.c file
> > for early init stuff, and stage2.c for the "normal" code?
> 
> Does it scale? Will we be able to tell different stage2.o files from
> each other when linking etc?
 
yes, by the path they are located in.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From peter at stuge.se  Thu Jul 12 11:26:57 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 11:26:57 +0200
Subject: [LinuxBIOS] [PATCH][v3] Intel 82371FB/SB/AB/EB/MB
	southbridge	support
In-Reply-To: <20070712091730.GC9439@coresystems.de>
References: <20070712012412.GG8025@greenwood>
	<20070712022913.2716.qmail@stuge.se>
	<20070712091730.GC9439@coresystems.de>
Message-ID: <20070712092657.29879.qmail@stuge.se>

On Thu, Jul 12, 2007 at 11:17:30AM +0200, Stefan Reinauer wrote:
> > > Shall we do that for all our chipsets and devices? A stage1.c file
> > > for early init stuff, and stage2.c for the "normal" code?
> > 
> > Does it scale? Will we be able to tell different stage2.o files from
> > each other when linking etc?
>  
> yes, by the path they are located in.

Also once linking is done? Any problem with two identical
southbridges or superios?

If no problems, it's great to know what the file does! :)


//Peter



From stepan at coresystems.de  Thu Jul 12 11:52:17 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 11:52:17 +0200
Subject: [LinuxBIOS] [PATCH][v3] Intel 82371FB/SB/AB/EB/MB
	southbridge	support
In-Reply-To: <20070712092657.29879.qmail@stuge.se>
References: <20070712012412.GG8025@greenwood>
	<20070712022913.2716.qmail@stuge.se>
	<20070712091730.GC9439@coresystems.de>
	<20070712092657.29879.qmail@stuge.se>
Message-ID: <20070712095217.GA24120@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 11:26]:
> On Thu, Jul 12, 2007 at 11:17:30AM +0200, Stefan Reinauer wrote:
> > > > Shall we do that for all our chipsets and devices? A stage1.c file
> > > > for early init stuff, and stage2.c for the "normal" code?
> > > 
> > > Does it scale? Will we be able to tell different stage2.o files from
> > > each other when linking etc?
> >  
> > yes, by the path they are located in.
> 
> Also once linking is done? 

I am sure I miss your point,..
When linking is done, the .o files are usually not needed anymore?

> Any problem with two identical
> southbridges or superios?

No.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From joe at smittys.pointclark.net  Thu Jul 12 11:54:10 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Thu, 12 Jul 2007 05:54:10 -0400
Subject: [LinuxBIOS] Another dumb C question
In-Reply-To: <20070712091652.28460.qmail@stuge.se>
References: <20070712050023.lspcpwen40swo0kg@www.smittys.pointclark.net>
	<20070712091652.28460.qmail@stuge.se>
Message-ID: <20070712055410.los1jiyeoosgw08s@www.smittys.pointclark.net>

Quoting Peter Stuge <peter at stuge.se>:

>
>> value = 9
>>
>> (2 << (value - 1))
>>

> Bit shift is fine methinks but I would suggest:
>
> (1 << value)
>
> instead of
>
> (2 << (value - 1))
>
>
> //Peter
>
Not sure I understand. I am trying to get 2 "to the power of" value.

if value = 9
(1 << value)
This equals 18???? Not 2^9 = 512
where
(2 << (value - 1))
(2 << (9 - 1))
2 << 8 = 512

Thanks - Joe



From corey.osgood at gmail.com  Thu Jul 12 12:08:04 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 12 Jul 2007 06:08:04 -0400
Subject: [LinuxBIOS] Another dumb C question
In-Reply-To: <20070712055410.los1jiyeoosgw08s@www.smittys.pointclark.net>
References: <20070712050023.lspcpwen40swo0kg@www.smittys.pointclark.net>	<20070712091652.28460.qmail@stuge.se>
	<20070712055410.los1jiyeoosgw08s@www.smittys.pointclark.net>
Message-ID: <4695FD84.50504@gmail.com>

Joseph Smith wrote:
> Quoting Peter Stuge <peter at stuge.se>:
>
>   
>>> value = 9
>>>
>>> (2 << (value - 1))
>>>
>>>       
>
>   
>> Bit shift is fine methinks but I would suggest:
>>
>> (1 << value)
>>
>> instead of
>>
>> (2 << (value - 1))
>>
>>
>> //Peter
>>
>>     
> Not sure I understand. I am trying to get 2 "to the power of" value.
>
> if value = 9
> (1 << value)
> This equals 18???? Not 2^9 = 512
> where
> (2 << (value - 1))
> (2 << (9 - 1))
> 2 << 8 = 512
>
> Thanks - Joe
>
>   
remember that 2 = (1 << 1). so 2 << (value - 1) = 1 << value. I'm not
sure where you're getting an 18 from, that makes no sense at all (since
18 in either hex or dec has two non-zero bits, so it's impossible to get
that result with just that binary shift).

-Corey



From darmawan.salihun at gmail.com  Thu Jul 12 12:13:38 2007
From: darmawan.salihun at gmail.com (Darmawan Salihun)
Date: Thu, 12 Jul 2007 17:13:38 +0700
Subject: [LinuxBIOS] Winflashrom -- Current Status
In-Reply-To: <20070712080556.18303.qmail@stuge.se>
References: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>	<4688C2BF.2040600@gmail.com>
	<20070702193703.21913.qmail@stuge.se>	<4695D613.6080603@gmail.com>
	<20070712080556.18303.qmail@stuge.se>
Message-ID: <4695FED2.6020100@gmail.com>

Peter Stuge wrote:
> On Thu, Jul 12, 2007 at 02:19:47PM +0700, Darmawan Salihun wrote:
>   
>> 1. Libpci abstraction for Windows. In this case the libpci logic in
>> the flashrom code base need not be changed. I will make a "libpci
>> for Windows" that doesn't change the logic within the current
>> flashrom code. Even after the redesign, we might choose to preserve
>> this part.
>>     
>
> Perhaps you can make a small libpci-win32 package out of it? I'm sure
> others would appreciate it as well.
>
>   
It should be trivial to do that.

>> 2. Direct I/O access abstraction. I think, in the short term, I
>> will just provide a simple direct I/O "compatibility layer" for
>> inX,outX family of functions in the winflashrom.
>>     
>
> This can just be some #defines, use some functions in Windows and the
> normal in()/out() stuff otherwise.
>
> Put this in some header:
>
> #ifndef __WIN32__
> #define my_inb(a,b) inb(a,b)
> #define my_inw(a,b) inw(a,b)
> #define my_inl(a,b) inl(a,b)
> #endif /* __WIN32__ */
>
> ..and then implement my_in[bwl]() in a .c file together with all the
> other stuff needed for Windows. Have a conditional in the Makefile to
> build and link that file on Windows only. Voila, done.
>
>
>   
>> 3. File I/O abstraction. We might need this because fopen(..)
>> behaves not exactly the same in Windows and *NIX.
>>     
>
> C89 has the b mode so just change all fopen calls to use "rb", "wb",
> "ab", "rb+", "wb+" and "ab+" respectively.
>
>   
OK

>> do you think it's good to make a branch for the current flashrom
>> code in order to develop the unified (redesigned) flashrom that
>> will host a single code base for both the *NIX version and
>> winflashrom?
>>     
>
> Is that really needed? Just submit nice and neat patches against
> trunk to get them reviewed, acked and applied.
>
>   
I see.

>> Another note that I have difficulty in limiting the direct I/O
>> access in the current driver because I don't know exactly which
>> port to give access to and which one to block. Below is what I've
>> found from the current flashrom code so far. I/O port usage:
>>
>>        0x2E (Winbond W836_INDEX port)
>>        0x2F (Winbond W836_DATA port)
>>        0x4E
>>        0x4F
>>        0xCD6
>>        0xCD7
>>        0xCFC - 0xCFF (PCI I/O port on x86)
>>        0xC6F
>>        a "base + 0x4D" in Via Epia motherboard
>>        0xE1
>>        0xE800 (what port is this? )
>>        0xE801
>>        0xE802
>>        0xE803
>>        0xE804
>>        0xE807
>>        0xEB
>>        0xFF
>>       
>> I couldn't conclude the the I/O port ranges to open from the port
>> list above because there is still unknown (I think it's dynamically
>> relocatable) I/O port such as the one used by EPIA board.
>> Any explanation on this issue?
>>     
>
> This list is still much better than allowing everything!
>
> As for the EPIA board, well, where is that base specified? In a PCI
> config register or where?
>   
The base is in a PCI config register. Relevant code as follows:
------------------- board_enable.c ----------------------------------------
static int board_via_epia_m(const char *name)
{
   ...
    /* Get Power Management IO address. */
    base = pci_read_word(dev, 0x88) & 0xFF80;

    /* enable GPIO15 which is connected to write protect. */
    val = inb(base + 0x4D);
    val |= 0x80;
    outb(val, base + 0x4D);
...
}

Cheers,

Darmawan





From stepan at coresystems.de  Thu Jul 12 12:18:45 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 12:18:45 +0200
Subject: [LinuxBIOS] [PATCH][LAR] Add a top level target for LAR
In-Reply-To: <20070711180747.GC20885@cosmic.amd.com>
References: <20070711180747.GC20885@cosmic.amd.com>
Message-ID: <20070712101845.GB24120@coresystems.de>

* Jordan Crouse <jordan.crouse at amd.com> [070711 20:07]:
> This is the easiest patch.. :)  Add a top level 'lar' target to v3, 
> so I can build the utility by itself.  Until LAR gets seperated out
> into its own repository, I'm going to have to figure out a way to make
> buildROM build lar independently of the rest of the v3 code, and this is
> probably the best way.

Not sure I get this right. What's the purpose? Don't you build
linuxbios, too?

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul 12 12:21:38 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 12:21:38 +0200
Subject: [LinuxBIOS] Add a top level target for LAR
In-Reply-To: <20070711230847.3685.qmail@stuge.se>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070711181204.22915.qmail@stuge.se>
	<20070711183009.GI20885@cosmic.amd.com>
	<20070711230847.3685.qmail@stuge.se>
Message-ID: <20070712102138.GC24120@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 01:08]:
> On Wed, Jul 11, 2007 at 12:30:09PM -0600, Jordan Crouse wrote:
> > > I would expect lar to be a target in util/
> > 
> > I agree.  But as its written right now, the makefiles depend on
> > the rules in the toplevel directory
> 
> Ah. I see.
> 
> This is another reason to move util/ out to it's own home.
 
Please: Whoever moves lar to it's own repository: Make sure that it
builds cleanly in v3 and out of v3 before doing so. Just moving it out
to another repo without making it compilable outside makes no sense.
Breaking the way it is built (out of the tree!) makes no sense either.

The same applies for flashrom.

BTW: We should really get lxbios.sf.net into the tree. That's far more
important than fixing something that is not broken.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From r.marek at assembler.cz  Thu Jul 12 12:43:27 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 12 Jul 2007 12:43:27 +0200
Subject: [LinuxBIOS] status update - K8T890/VT8237
In-Reply-To: <20070711005146.27625.qmail@stuge.se>
References: <4694125B.6030507@assembler.cz>
	<20070711005146.27625.qmail@stuge.se>
Message-ID: <469605CF.6020607@assembler.cz>

> Great news!

Yeah but I will need some help!

I have still problems with the RAM versus PCI MMIO. I think I found the problem:

LinuxBIOSv2/src/northbridge/amd/amdk8/northbridge.c:559

       resource->base = 0xa0000;
         resource->size = 0x20000;

         /* write the resource to the hardware */
         reg  = resource->index & 0xfc;
         base  = f1_read_config32(reg);
         limit = f1_read_config32(reg + 0x4);
         base  &= 0x000000f0;
         base  |= (resource->base >> 8) & 0xffffff00;
         base  |= 3;
     limit &= 0x00000048;
         limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
         limit |= (resource->index & 3) << 4;
         limit |= (nodeid & 7);
         f1_write_config32(reg + 0x4, limit);
         f1_write_config32(reg, base);

I think there is missing -1

((resource->base + resource->size - 1) >> 8) & 0xffffff00;

After this fix the MMIO for VGA is from A0000 to BFFFF

BUT! The VGA ROM seems to be mapped to C8000! How is this possible? Why is 
linuxbios claiming that the RAM is from C0000-EFFFF???

Where/what is wrong? How got the ROM there anyway? (MTRRs? VGA chip? PCI config???)

Thank you,

Rudolf






From stepan at coresystems.de  Thu Jul 12 13:02:56 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 13:02:56 +0200
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames
	for	create and add
In-Reply-To: <20070711233610.7951.qmail@stuge.se>
References: <20070711182227.GF20885@cosmic.amd.com>
	<20070711233610.7951.qmail@stuge.se>
Message-ID: <20070712110256.GD24120@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 01:36]:
> > ./lar -a my.lar ../sources/vsa.bin:vsa
> 
> I don't like having all this information (algo too) in-band with the
> filename.. I don't know a nice way to do it for when adding many
> files at once though. :\ I was thinking about a "lar script" that
> would say what goes where with what algo but it would be nice to not
> have to go there.

Yes, a lar script ("MANIFEST" ?) would be what we want here...

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Thu Jul 12 13:10:09 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 13:10:09 +0200
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames
	for	create and add
In-Reply-To: <20070711235010.GD3127@cosmic.amd.com>
References: <20070711182227.GF20885@cosmic.amd.com>
	<20070711233610.7951.qmail@stuge.se>
	<20070711235010.GD3127@cosmic.amd.com>
Message-ID: <20070712111009.GE24120@coresystems.de>

* Jordan Crouse <jordan.crouse at amd.com> [070712 01:50]:
> --------------------------------------------
> # MANIFEST
> # Filename	    pathname		algorithm
> /root/my.payload    normal/payload	lzma
> ...
> bootblock	    bootblock		-

Do we really need to distinguish between filename and pathname? I don't
understand the difference here, unless it's a copy operation instead of
an archive. Back when we invented lar, we thought about making all
matches via the filename. So I think pathname is an idea to go away from
that fixed mapping again...?

I'd rather define file types rather than pathnames? 

Or is the pathname such a filetype, and the name is just ambiguous?

I like that you can add/exchange a file via the command line, and one needs to
specify all the information in the manifest on the command line, too.
So we should think about what goes in there.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From Savchenko at altell.ru  Thu Jul 12 13:33:00 2007
From: Savchenko at altell.ru (Savchenko Mikhail)
Date: Thu, 12 Jul 2007 15:33:00 +0400
Subject: [LinuxBIOS] Virtual Iron and AMD Pacifica
Message-ID: <000001c7c478$67b36c40$0701a8c0@notebook255>

Any ideas about running Virtual Iron virtual machines hypervisor via
LinuxBIOS is it possible, and what about hardware virtualization (Pacifica)
of AMD64 CPUs support in LinuxBIOS, is it works? 

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From joe at smittys.pointclark.net  Thu Jul 12 13:56:51 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Thu, 12 Jul 2007 07:56:51 -0400
Subject: [LinuxBIOS] Another dumb C question
In-Reply-To: <4695FD84.50504@gmail.com>
References: <20070712050023.lspcpwen40swo0kg@www.smittys.pointclark.net>
	<20070712091652.28460.qmail@stuge.se>
	<20070712055410.los1jiyeoosgw08s@www.smittys.pointclark.net>
	<4695FD84.50504@gmail.com>
Message-ID: <20070712075651.bnla61paocssc8ck@www.smittys.pointclark.net>

Quoting Corey Osgood <corey.osgood at gmail.com>:

> Joseph Smith wrote:
>> Quoting Peter Stuge <peter at stuge.se>:
>>
>>
>>>> value = 9
>>>>
>>>> (2 << (value - 1))
>>>>
>>>>
>>
>>
>>> Bit shift is fine methinks but I would suggest:
>>>
>>> (1 << value)
>>>
>>> instead of
>>>
>>> (2 << (value - 1))
>>>
>>>
>>> //Peter
>>>
>>>
>> Not sure I understand. I am trying to get 2 "to the power of" value.
>>
>> if value = 9
>> (1 << value)
>> This equals 18???? Not 2^9 = 512
>> where
>> (2 << (value - 1))
>> (2 << (9 - 1))
>> 2 << 8 = 512
>>
>> Thanks - Joe
>>
>>
> remember that 2 = (1 << 1). so 2 << (value - 1) = 1 << value. I'm not
> sure where you're getting an 18 from, that makes no sense at all (since
> 18 in either hex or dec has two non-zero bits, so it's impossible to get
> that result with just that binary shift).
>
> -Corey
>
>
Well lets see if value = 9, which is 1001 in binary.
If you bitshift 1001 one position to the left it becomes 10010, correct?
Which is 18 in decimal.

Thanks - Joe



From joe at smittys.pointclark.net  Thu Jul 12 14:34:24 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Thu, 12 Jul 2007 08:34:24 -0400
Subject: [LinuxBIOS] Another dumb C question
In-Reply-To: <20070712075651.bnla61paocssc8ck@www.smittys.pointclark.net>
References: <20070712050023.lspcpwen40swo0kg@www.smittys.pointclark.net>
	<20070712091652.28460.qmail@stuge.se>
	<20070712055410.los1jiyeoosgw08s@www.smittys.pointclark.net>
	<4695FD84.50504@gmail.com>
	<20070712075651.bnla61paocssc8ck@www.smittys.pointclark.net>
Message-ID: <20070712083424.171i981jswo4csw0@www.smittys.pointclark.net>

Quoting Joseph Smith <joe at smittys.pointclark.net>:

> Quoting Corey Osgood <corey.osgood at gmail.com>:
>
>> Joseph Smith wrote:
>>> Quoting Peter Stuge <peter at stuge.se>:
>>>
>>>
>>>>> value = 9
>>>>>
>>>>> (2 << (value - 1))
>>>>>
>>>>>
>>>
>>>
>>>> Bit shift is fine methinks but I would suggest:
>>>>
>>>> (1 << value)
>>>>
>>>> instead of
>>>>
>>>> (2 << (value - 1))
>>>>
>>>>
>>>> //Peter
>>>>
>>>>
>>> Not sure I understand. I am trying to get 2 "to the power of" value.
>>>
>>> if value = 9
>>> (1 << value)
>>> This equals 18???? Not 2^9 = 512
>>> where
>>> (2 << (value - 1))
>>> (2 << (9 - 1))
>>> 2 << 8 = 512
>>>
>>> Thanks - Joe
>>>
>>>
>> remember that 2 = (1 << 1). so 2 << (value - 1) = 1 << value. I'm not
>> sure where you're getting an 18 from, that makes no sense at all (since
>> 18 in either hex or dec has two non-zero bits, so it's impossible to get
>> that result with just that binary shift).
>>
>> -Corey
>>
>>
> Well lets see if value = 9, which is 1001 in binary.
> If you bitshift 1001 one position to the left it becomes 10010, correct?
> Which is 18 in decimal.
>
> Thanks - Joe
>
Nevermind I get it. I was looking at it bass ackwards :-)
Sorry, I'm a little tired.


Thanks - Joe



From uwe at hermann-uwe.de  Thu Jul 12 14:43:52 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 14:43:52 +0200
Subject: [LinuxBIOS] r447 - in LinuxBIOSv3:
	include/device	mainboard/emulation/qemu-x86
In-Reply-To: <20070712084347.GA30653@coresystems.de>
References: <20070712084347.GA30653@coresystems.de>
Message-ID: <20070712124352.GA26506@greenwood>

On Thu, Jul 12, 2007 at 10:43:47AM +0200, Stefan Reinauer wrote:
> * svn at openbios.org <svn at openbios.org> [070712 03:03]:
> > Some minor cosmetic fixes (trivial).
> 
> > -/*
> > - *	PCI Class, Vendor and Device IDs
> > - *
> > - *	Please keep sorted.
> > - */
> > -
> 
> Why is removing comments considered a cosmetic fix?

I can re-add it if it's important, but it looked a bit superfluous, as
we already have

 /* Device classes and subclasses. */

and

 /* Vendors and devices. Sort key: vendor first, device next. */

below...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Thu Jul 12 14:47:02 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 14:47:02 +0200
Subject: [LinuxBIOS] Virtual Iron and AMD Pacifica
In-Reply-To: <000001c7c478$67b36c40$0701a8c0@notebook255>
References: <000001c7c478$67b36c40$0701a8c0@notebook255>
Message-ID: <20070712124702.GA23126@coresystems.de>

* Savchenko Mikhail <Savchenko at altell.ru> [070712 13:33]:
> Any ideas about running Virtual Iron virtual machines hypervisor via LinuxBIOS
> is it possible, and what about hardware virtualization (Pacifica) of AMD64 CPUs
> support in LinuxBIOS, is it works?

Pacifica works fine with LinuxBIOS.

No idea about Virtual Iron. You even have to register to view their
technical white papers / product descriptions. 


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul 12 14:49:36 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 14:49:36 +0200
Subject: [LinuxBIOS] PATCH: mkdirp() error on new directory
	outside	given parent
In-Reply-To: <20070712075011.16157.qmail@stuge.se>
References: <20070712075011.16157.qmail@stuge.se>
Message-ID: <20070712124936.GA25662@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 09:50]:
> Have a look.
> 
> I haven't gotten lar to build, but the function works in a separate
> test program.

I think the better way would be to check the paths for ../ and skip
those with a warning.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From uwe at hermann-uwe.de  Thu Jul 12 14:59:17 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 14:59:17 +0200
Subject: [LinuxBIOS] [PATCH][v3] Move lar into global util/ directory
	+	svn:externals
In-Reply-To: <20070712090820.GB9439@coresystems.de>
References: <20070711202452.GF8025@greenwood>
	<20070712090820.GB9439@coresystems.de>
Message-ID: <20070712125917.GB26506@greenwood>

On Thu, Jul 12, 2007 at 11:08:20AM +0200, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070711 22:24]:
> > OK, not really a patch, but I think we can move lar into the global
> > util/ directory and suck it into v3 via svn:externals.
> > 
> > That's a first step to make it independent of v3 (and to allow Jordan
> > to use it in buildrom).
> > 
> > I'm waiting for comments or ACKs before doing this, though.
> 
> Will this drop the history? If so, strong NACK.

Ouch. I was about to say "yes, history is preserved", but I forgot that
v3 is a _different_ repository at the moment! So no, we cannot just
'svn mv' lar easily (which is one of the many reasons why I object to
different repos for our code).

You'd have to dump the v3 repository, and import it into the v2
repository (which I think we should do anyway) -- there
are some tutorials on how to do that while preserving the history.

This has to be done by the admin (probably needs root access), and can
_not_ be done by anybody with svn commit access (not if you want to
preserve history, that is).

_Then_, it's a simple 'svn mv' to move lar into the global util/.


Oh, another possibility would be to just commit the current v3 code
into the v2 repository (and dropping the history!) like this:

- trunk
  - LinuxBIOSv1
  - LinuxBIOSv2
  - LinuxBIOSv3    <----- commit v3 right into that directory
  - util


Yes, we would _not_ have the history in that new LinuxBIOSv3 directory.
But maybe it's still an option, because we could leave the current
extra v3 repo around as an "early development testbed" repository, so
people can lookup the history there.


Comments? I'm fine with either of the two approaches.


> It is NOT a generic utility yet.

Yep, but patches are floating in to make it generic :)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Thu Jul 12 15:01:42 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 12 Jul 2007 15:01:42 +0200
Subject: [LinuxBIOS] r449 - in LinuxBIOSv3: arch/x86/geodelx
	include/arch/x86 lib northbridge/amd/geodelx
Message-ID: <mailman.515.1355071133.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-12 15:01:42 +0200 (Thu, 12 Jul 2007)
New Revision: 449

Removed:
   LinuxBIOSv3/include/arch/x86/hlt.h
Modified:
   LinuxBIOSv3/arch/x86/geodelx/geodelx.c
   LinuxBIOSv3/include/arch/x86/cpu.h
   LinuxBIOSv3/lib/console.c
   LinuxBIOSv3/lib/ram.c
   LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
Log:
Merge hlt() into cpu.h where it belongs. Add some documentation.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c
===================================================================
--- LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-12 01:26:43 UTC (rev 448)
+++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c	2007-07-12 13:01:42 UTC (rev 449)
@@ -25,7 +25,7 @@
 #include <console.h>
 #include <msr.h>
 #include <io.h>
-#include <hlt.h>
+#include <cpu.h>
 #include <amd_geodelx.h>
 #include <spd.h>
 #include <legacy.h>

Modified: LinuxBIOSv3/include/arch/x86/cpu.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/cpu.h	2007-07-12 01:26:43 UTC (rev 448)
+++ LinuxBIOSv3/include/arch/x86/cpu.h	2007-07-12 13:01:42 UTC (rev 449)
@@ -181,9 +181,21 @@
  */
 static inline void cpu_relax(void)
 {
-	__asm__ __volatile__("rep;nop" : : : "memory");
+	__asm__ __volatile__("rep; nop" : : : "memory");
 }
 
+/**
+ * Shut down the CPU.
+ *
+ * This function is '__attribute__((always_inline))' because it might be
+ * called before RAM is set up, thus pushing stuff on stack (for a function
+ * call) will not work.
+ */
+static inline __attribute__((always_inline)) void hlt(void)
+{
+	__asm__ __volatile__("hlt" : : : "memory");
+}
+
 /* Random other functions. These are not architecture-specific, except they
  * really are in many ways. Seperate the PC from the "X86" is hard.
  */

Deleted: LinuxBIOSv3/include/arch/x86/hlt.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/hlt.h	2007-07-12 01:26:43 UTC (rev 448)
+++ LinuxBIOSv3/include/arch/x86/hlt.h	2007-07-12 13:01:42 UTC (rev 449)
@@ -1,29 +0,0 @@
-/*
- * This file is part of the LinuxBIOS project.
- *
- * Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#ifndef ARCH_X86_HLT_H
-#define ARCH_X86_HLT_H
-
-static inline __attribute__((always_inline)) void hlt(void)
-{
-	asm("hlt");
-}
-
-#endif /* ARCH_X86_HLT_H */

Modified: LinuxBIOSv3/lib/console.c
===================================================================
--- LinuxBIOSv3/lib/console.c	2007-07-12 01:26:43 UTC (rev 448)
+++ LinuxBIOSv3/lib/console.c	2007-07-12 13:01:42 UTC (rev 449)
@@ -1,5 +1,5 @@
 #include <types.h>
-#include <hlt.h>
+#include <cpu.h>
 #include <console.h>
 #include <uart8250.h>
 #include <stdarg.h>
@@ -57,13 +57,11 @@
 		" starting...\n";
 
 	printk(BIOS_INFO, console_test);
-
 }
 
 void die(const char *str)
 {
 	printk(BIOS_EMERG, str);
-	do {
+	while (1)
 		hlt();
-	} while (1);
 }

Modified: LinuxBIOSv3/lib/ram.c
===================================================================
--- LinuxBIOSv3/lib/ram.c	2007-07-12 01:26:43 UTC (rev 448)
+++ LinuxBIOSv3/lib/ram.c	2007-07-12 13:01:42 UTC (rev 449)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <hlt.h>
+#include <cpu.h>
 #include <console.h>
 
 /**

Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-12 01:26:43 UTC (rev 448)
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c	2007-07-12 13:01:42 UTC (rev 449)
@@ -25,7 +25,7 @@
 #include <msr.h>
 #include <spd.h>
 #include <io.h>
-#include <hlt.h>
+#include <cpu.h>
 #include <amd_geodelx.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 




From svn at openbios.org  Thu Jul 12 15:03:53 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 12 Jul 2007 15:03:53 +0200
Subject: [LinuxBIOS] r450 - LinuxBIOSv3/arch/x86
Message-ID: <mailman.516.1355071133.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-07-12 15:03:53 +0200 (Thu, 12 Jul 2007)
New Revision: 450

Modified:
   LinuxBIOSv3/arch/x86/stage1.c
Log:
Ensure correct linking independent from compiler settings

Signed-off-by: Juergen Beisert <juergen at kreuzholzen.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: LinuxBIOSv3/arch/x86/stage1.c
===================================================================
--- LinuxBIOSv3/arch/x86/stage1.c	2007-07-12 13:01:42 UTC (rev 449)
+++ LinuxBIOSv3/arch/x86/stage1.c	2007-07-12 13:03:53 UTC (rev 450)
@@ -52,7 +52,11 @@
 	post_code(0xf2);
 }
 
-void stage1_main(u32 bist)
+/*
+ * This function is called from assembler code whith its argument on the
+ * stack. Force the compiler to generate always correct code for this case.
+ */
+void __attribute__((stdcall)) stage1_main(u32 bist)
 {
 	int ret;
 	struct mem_file archive, result;




From uwe at hermann-uwe.de  Thu Jul 12 15:06:57 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 15:06:57 +0200
Subject: [LinuxBIOS] [PATCH][v3] Merge hlt() into cpu.h (svn resync)
In-Reply-To: <20070712022746.2410.qmail@stuge.se>
References: <20070712014423.GI8025@greenwood>
	<20070712022746.2410.qmail@stuge.se>
Message-ID: <20070712130657.GC26506@greenwood>

On Thu, Jul 12, 2007 at 04:27:46AM +0200, Peter Stuge wrote:
> On Thu, Jul 12, 2007 at 03:44:23AM +0200, Uwe Hermann wrote:
> > Btw, why does die() do an endless loop around hlt()? Is there a
> > reason a hlt() will _not_ immediately halt the CPU? Can that
> > happen?
> 
> It should halt, but the CPU may wake up again and continue executing
> if an interrupt arrives. All should be masked, but you never know..
> 
> 
> > If so, shall we move the loop into hlt() itself?
> 
> I don't think so. hlt() is just a C wrapper around the instruction.

Hm, but given your above explanations that the hlt() may not really
completely halt, I'd say that we really should move the loop into
hlt(). When I call hlt() from my code I _expect_ a full halt, I don't
want _any_ other code exectuted.

Or ?s there some reason why you explicitly want that behaviour?


> Eventually I imagine building a panic room into die() so that
> recovery can be made via console on fatal errors. Ideally with
> some kind of stub for debugging stage0 and definately one for
> initram.

Yep, surely a nice idea (should be a Kconfig option, though).

But maybe hlt() and die() should do just what they are supposed to do.
It may be better to make an explicit panicroom() function or so...


> > Merge hlt() into cpu.h where it belongs. Add some documentation.
> > 
> > Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> Acked-by: Peter Stuge <peter at stuge.se>

Thanks, r449.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Thu Jul 12 15:12:47 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 12 Jul 2007 15:12:47 +0200
Subject: [LinuxBIOS] r2733 - trunk/LinuxBIOSv2/src/devices
Message-ID: <mailman.517.1355071133.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-12 15:12:47 +0200 (Thu, 12 Jul 2007)
New Revision: 2733

Modified:
   trunk/LinuxBIOSv2/src/devices/pnp_device.c
Log:
Generic driver for pretty much all known Standard Microsystems Corporation
(SMSC) Super I/O chips.

Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.

So far only the ASUS A8000 has been tested on real hardware!

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Modified: trunk/LinuxBIOSv2/src/devices/pnp_device.c
===================================================================
--- trunk/LinuxBIOSv2/src/devices/pnp_device.c	2007-07-04 17:51:49 UTC (rev 2732)
+++ trunk/LinuxBIOSv2/src/devices/pnp_device.c	2007-07-12 13:12:47 UTC (rev 2733)
@@ -240,6 +240,10 @@
 	
 	/* Setup the ops and resources on the newly allocated devices */
 	for(i = 0; i < functions; i++) {
+		/* Skip logical devices this Super I/O doesn't have. */
+		if (info[i].function == -1)
+			continue;
+
 		path.u.pnp.device = info[i].function;
 		dev = alloc_find_dev(base_dev->bus, &path);
 		




From svn at openbios.org  Thu Jul 12 15:13:56 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 12 Jul 2007 15:13:56 +0200
Subject: [LinuxBIOS] r2734 - in trunk/LinuxBIOSv2/src/superio/smsc: .
	smscsuperio
Message-ID: <mailman.518.1355071133.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-07-12 15:13:56 +0200 (Thu, 12 Jul 2007)
New Revision: 2734

Added:
   trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/
   trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb
   trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h
   trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
   trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c
Log:
[Arg! Forgot to 'svn add', sorry]

Generic driver for pretty much all known Standard Microsystems Corporation
(SMSC) Super I/O chips.

Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.

So far only the ASUS A8000 has been tested on real hardware!

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/Config.lb	2007-07-12 13:13:56 UTC (rev 2734)
@@ -0,0 +1,23 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config chip.h
+object superio.o
+

Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/chip.h	2007-07-12 13:13:56 UTC (rev 2734)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_smsc_smscsuperio_ops;
+
+struct superio_smsc_smscsuperio_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};

Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c	2007-07-12 13:13:56 UTC (rev 2734)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+
+/* All known/supported SMSC Super I/Os have the same logical device IDs
+ * for the serial ports (COM1, COM2).
+ */
+#define SMSCSUPERIO_SP1 4	/* Com1 */
+#define SMSCSUPERIO_SP2 5	/* Com2 */
+
+/**
+ * Enable the specified serial port.
+ *
+ * @param dev The device to use.
+ * @param dev The I/O base of the serial port (usually 0x3f8/0x2f8).
+ */
+static inline void smscsuperio_enable_serial(device_t dev, uint16_t iobase)
+{
+	uint16_t port = dev >> 8;
+
+	outb(0x55, port);		/* Enter the configuration state. */
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	outb(0xaa, port);		/* Exit the configuration state. */
+}

Added: trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c
===================================================================
--- trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/superio/smsc/smscsuperio/superio.c	2007-07-12 13:13:56 UTC (rev 2734)
@@ -0,0 +1,335 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Generic driver for pretty much all known Standard Microsystems Corporation
+ * (SMSC) Super I/O chips.
+ *
+ * Datasheets are available from: http://www.smsc.com/main/datasheet.html
+ *
+ * Most of the SMSC Super I/O chips seem to be similar enough (for our
+ * purposes) so that we can handle them with a unified driver.
+ *
+ * So far only the ASUS A8000 has been tested on real hardware!
+ *
+ * The floppy disk controller, the parallel port, the serial ports, and the
+ * keyboard controller should work with all the chips. For the more advanced
+ * stuff (e.g. HWM, ACPI, SMBus) more work is probably required.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+
+/* The following Super I/O chips are currently supported by this driver: */
+#define FDC37B80X	0x42	/* Same ID: FDC37M70X (a.k.a. FDC37M707) */
+#define FDC37B78X	0x44
+#define FDC37B72X	0x4c
+#define FDC37M81X	0x4d
+#define FDC37M60X	0x47
+#define LPC47B27X	0x51	/* a.k.a. LPC47B272 */
+#define LPC47M10X	0x59	/* Same ID: LPC47M112, LPC47M13X */
+#define LPC47M15X	0x60	/* Same ID: LPC47M192 */
+#define LPC47S45X	0x62
+#define LPC47B397	0x6f
+#define A8000		0x77	/* ASUS A8000, a rebranded DME1737(?) */
+#define DME1737		0x78
+#define SCH5307		0x81	/* Rebranded LPC47B397(?) */
+
+/* Register defines */
+#define DEVICE_ID_REG	0x20	/* Device ID register */
+#define DEVICE_REV_REG	0x21	/* Device revision register */
+
+/* Static variables for the Super I/O device ID and revision. */
+static int first_time = 1;
+static uint8_t superio_id = 0;
+static uint8_t superio_rev = 0;
+
+/* TODO: Move somewhere else, but where? */
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+/**
+ * A list of all possible logical devices which may be supported by at least
+ * one of the Super I/O chips. These values are used as index into the
+ * logical_device_table[i].devs array(s).
+ *
+ * If you change this enum, you must also adapt the logical_device_table[]
+ * array and MAX_LOGICAL_DEVICES!
+ */
+enum {
+	LD_FDC,		/* Floppy disk controller */
+	LD_PP,		/* Parallel port */
+	LD_SP1,		/* Serial port 1 (COM1) */
+	LD_SP2,		/* Serial port 2 (COM2) */
+	LD_RTC,		/* Real-time clock */
+	LD_KBC,		/* Keyboard controller */
+	LD_AUX,		/* Auxiliary I/O */
+	LD_XBUS,	/* X-Bus */
+	LD_HWM,		/* Hardware monitor */
+	LD_GAME,	/* Game port */
+	LD_PME,		/* Power management events */
+	LD_MPU401,	/* MPU-401 MIDI UART */
+	LD_RT,		/* Runtime registers / security key registers */
+	LD_ACPI,	/* ACPI */
+	LD_SMB,		/* SMBus */
+};
+
+/* Note: This value must match the number of items in the enum above! */
+#define MAX_LOGICAL_DEVICES 15
+
+/**
+ * A table describing the logical devices which are present on the
+ * supported Super I/O chips.
+ *
+ * The first entry (superio_id) is the device ID of the Super I/O chip
+ * as stored in the (read-only) DEVICE_ID_REG register.
+ *
+ * The second entry (devs) is the list of logical device IDs which are
+ * present on that particular Super I/O chip. A value of -1 means the
+ * device is not present on that chip.
+ *
+ * Note: Do _not_ list chips with different name but same device ID twice!
+ *       The result would be that the init code would be executed twice!
+ */
+const static struct logical_devices {
+	uint8_t superio_id;
+	int devs[MAX_LOGICAL_DEVICES];
+} logical_device_table[] = {
+	// Chip   FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB
+	{FDC37B80X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, -1, -1}},
+	{FDC37B78X,{0, 3, 4,  5,  6,  7,  8,  -1, -1,  -1, -1, -1, -1, 10, -1}},
+	{FDC37B72X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, 10, -1}},
+	{FDC37M81X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, -1, -1}},
+	{FDC37M60X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, -1, -1}},
+	{LPC47B27X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, -1, 11, 10, -1, -1}},
+	{LPC47M10X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, 10, 11, -1, -1, -1}},
+	{LPC47M15X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, 10, 11, -1, -1, -1}},
+	{LPC47S45X,{0, 3, 4,  5,  6,  7, -1,   8, -1,  -1, -1, -1, 10, -1, 11}},
+	{LPC47B397,{0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
+	{A8000,    {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
+	{DME1737,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
+	{SCH5307,  {0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
+};
+
+/**
+ * Enter the configuration state by writing 0x55 to the config port.
+ *
+ * The Super I/O configuration registers can only be modified when the chip
+ * is in the configuration state. Thus, to program the registers you have
+ * to a) enter config mode, b) program the registers, c) exit config mode.
+ *
+ * @param dev The device to use.
+ */
+static inline void smsc_pnp_enter_conf_state(device_t dev)
+{
+	outb(0x55, dev->path.u.pnp.port);
+}
+
+/**
+ * Exit the configuration state by writing 0xaa to the config port.
+ *
+ * This puts the chip into the 'run' state again.
+ *
+ * @param dev The device to use.
+ */
+static inline void smsc_pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.u.pnp.port);
+}
+
+/** Wrapper for pnp_set_resources(). */
+static void smsc_pnp_set_resources(device_t dev)
+{
+	smsc_pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	smsc_pnp_exit_conf_state(dev);
+}
+
+/** Wrapper for pnp_enable_resources(). */
+static void smsc_pnp_enable_resources(device_t dev)
+{
+	smsc_pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	smsc_pnp_exit_conf_state(dev);
+}
+
+/**
+ * If so configured, enable the specified device, otherwise
+ * explicitly disable it.
+ *
+ * @param dev The device to use.
+ */
+static void smsc_pnp_enable(device_t dev)
+{
+	smsc_pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	(dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+	smsc_pnp_exit_conf_state(dev);
+}
+
+/**
+ * Initialize those logical devices which need a special init.
+ *
+ * @param dev The device to use.
+ */
+static void smsc_init(device_t dev)
+{
+	struct superio_smsc_smscsuperio_config *conf = dev->chip_info;
+	struct resource *res0, *res1;
+	int i, ld;
+
+	/* Do not initialize disabled devices. */
+	if (!dev->enabled)
+		return;
+
+	/* Find the correct Super I/O. */
+	for (i = 0; i < ARRAY_SIZE(logical_device_table); i++)
+		if (logical_device_table[i].superio_id == superio_id)
+			break;
+
+	/* If no Super I/O was found, return. */
+	if (i == ARRAY_SIZE(logical_device_table))
+		return;
+
+	/* A Super I/O was found, so initialize the respective device. */
+	ld = dev->path.u.pnp.device;
+	if (ld == logical_device_table[i].devs[LD_SP1]) {
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+	} else if (ld == logical_device_table[i].devs[LD_SP2]) {
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+	} else if (ld == logical_device_table[i].devs[LD_KBC]) {
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+	}
+}
+
+/** Standard device operations. */
+static struct device_operations ops = {
+	.read_resources		= pnp_read_resources,
+	.set_resources		= smsc_pnp_set_resources,
+	.enable_resources	= smsc_pnp_enable_resources,
+	.enable			= smsc_pnp_enable,
+	.init			= smsc_init,
+};
+
+/**
+ * TODO.
+ *
+ * This table should contain all possible entries for any of the supported
+ * Super I/O chips, even if some of them don't have the respective logical
+ * devices. That will be handled correctly by our code.
+ *
+ * The LD_FOO entries are device markers which tell you the type of the logical
+ * device (e.g. whether it's a floppy disk controller or a serial port etc.).
+ *
+ * Before using pnp_dev_info[] in pnp_enable_devices() these markers have
+ * to be replaced with the real logical device IDs of the respective
+ * Super I/O chip. This is done in enable_dev().
+ *
+ * TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet).
+ */
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, LD_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, LD_RTC, },
+	{ &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 },
+								 { 0x7ff, 4 },},
+	{ &ops, LD_AUX, },
+	{ &ops, LD_XBUS, },
+	{ &ops, LD_HWM, PNP_IO0, { 0x7f0, 0 }, },
+	{ &ops, LD_GAME, },
+	{ &ops, LD_PME, },
+	{ &ops, LD_MPU401, },
+	{ &ops, LD_RT,  PNP_IO0, { 0x780, 0 }, },
+	{ &ops, LD_ACPI, },
+	{ &ops, LD_SMB, },
+};
+
+/**
+ * Enable the logical devices of the Super I/O chip.
+ *
+ * TODO: Think about how to handle the case when a mainboard has multiple
+ *       Super I/O chips soldered on.
+ * TODO: Can this code be simplified a bit?
+ *
+ * @param dev The device to use.
+ */
+static void enable_dev(device_t dev)
+{
+	int i, j, fn;
+	int tmp[MAX_LOGICAL_DEVICES];
+
+	if (first_time) {
+		/* Read the device ID and revision of the Super I/O chip. */
+		smsc_pnp_enter_conf_state(dev);
+		superio_id = pnp_read_config(dev, DEVICE_ID_REG);
+		superio_rev = pnp_read_config(dev, DEVICE_REV_REG);
+		smsc_pnp_exit_conf_state(dev);
+
+		/* TODO: Error handling? */
+
+		printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
+			    superio_id, superio_rev);
+		first_time = 0;
+	}
+
+	/* Find the correct Super I/O. */
+	for (i = 0; i < ARRAY_SIZE(logical_device_table); i++)
+		if (logical_device_table[i].superio_id == superio_id)
+			break;
+
+	/* If no Super I/O was found, return. */
+	if (i == ARRAY_SIZE(logical_device_table))
+		return;
+
+	/* Temporarily save the LD_FOO values. */
+	for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
+		tmp[j] = pnp_dev_info[j].function;
+
+	/* Replace the LD_FOO markers in pnp_dev_info[] with
+	 * the real logical device IDs of this Super I/O chip.
+	 */
+	for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) {
+		fn = pnp_dev_info[j].function;
+		pnp_dev_info[j].function = logical_device_table[i].devs[fn];
+	}
+
+	/* Enable the specified devices (if present on the chip). */
+	pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
+			   &pnp_dev_info);
+
+	/* Restore LD_FOO values. */
+	for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
+		pnp_dev_info[j].function = tmp[j];
+}
+
+struct chip_operations superio_smsc_smscsuperio_ops = {
+	CHIP_NAME("Various SMSC Super I/Os")
+	.enable_dev = enable_dev
+};




From uwe at hermann-uwe.de  Thu Jul 12 15:14:40 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 15:14:40 +0200
Subject: [LinuxBIOS] [PATCH] Add support for 17 new SMSC Super
	I/O	devices
In-Reply-To: <46959D6E.1030306@gmail.com>
References: <20070707191814.GA5859@greenwood>
	<20070712014502.GJ8025@greenwood> <46959D6E.1030306@gmail.com>
Message-ID: <20070712131440.GD26506@greenwood>

On Wed, Jul 11, 2007 at 11:18:06PM -0400, Corey Osgood wrote:
> Acked-by: Corey Osgood <corey.osgood at gmail.com>

Thanks, r2733 (and r2734 :)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Jul 12 15:15:50 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 15:15:50 +0200
Subject: [LinuxBIOS] r431 - in LinuxBIOSv3: .
	include	include/arch/x86/arch
In-Reply-To: <20070704163115.GA20684@coresystems.de>
References: <20070704155009.GC7595@coresystems.de>
	<20070704161424.GJ17746@greenwood>
	<20070704163115.GA20684@coresystems.de>
Message-ID: <20070712131550.GE26506@greenwood>

On Wed, Jul 04, 2007 at 06:31:15PM +0200, Stefan Reinauer wrote:
> I think 3 is the best one.. We are already going safe in so many places
> (licenses for dts files and Kconfig files), so we should maybe just do
> the same here.
> 
> Other opinions?

Yeah, I agree. I'll send a patch later this day.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Jul 12 15:19:07 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 15:19:07 +0200
Subject: [LinuxBIOS] Acer TravelMate 660
In-Reply-To: <4694BDB0.3030309@ascolab.com>
References: <200707111037.18127.gerhard.gappmeier@ascolab.com>
	<4694AF9C.9090608@gmail.com> <4694BDB0.3030309@ascolab.com>
Message-ID: <20070712131907.GF26506@greenwood>

Hi,

On Wed, Jul 11, 2007 at 01:23:28PM +0200, Gerhard Gappmeier wrote:
> > LinuxBIOS on laptops is a mess that we're only beginning to jump into.
> > Laptops have an embedded controller, sometimes referred to as an EC,
> > that can control everything from power to LCD control, etc, etc. The
> > docs on these are usually covered by an NDA, with one real exception:
> > the part used by OLPC's XO. See also http://www.linuxbios.org/Laptop
> >   
> Sounds not ver optimistic for me.

Yeah, it's not trivial, sorry. Currently the OLPC is the only known
laptop supported by LinuxBIOS. We _do_ intend to support laptops, but
it's hard.


> > As for the rest of your hardware, I think some work was being done on
> > the i855, but I don't know what the outcome of it was. The i82801dbm
> > should work, either through the regular or generic implementation. You
> > haven't listed the Super IO, so I can't tell if that would work or not,
> >   
> Actually I don't know what this Super IO is and where I can get this
> information from.

lm-sensors may or may not detect it. But the safest bet is looking at
the hardware, of course (i.e., opening the laptop, which probably voids
the warranty). But there's no need to do that anyway, see above. We
don't support laptops at the moment, unfortunately.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Jul 12 15:23:05 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 15:23:05 +0200
Subject: [LinuxBIOS] Does my MoBo supported?
In-Reply-To: <adf480660707110621l20783bf8v67e7d652defde993@mail.gmail.com>
References: <adf480660707110621l20783bf8v67e7d652defde993@mail.gmail.com>
Message-ID: <20070712132305.GG26506@greenwood>

Hi,

On Wed, Jul 11, 2007 at 05:21:12PM +0400, Peter Lemenkov wrote:
> I've got a small number of motherboards on which I would like to
> install LinuxBIOS instead of proprietary BLOBs.
> 
> One of that cars identified as Gigabyte 7VT880-RZ (based on VIA KT880 + VT8237R)

Not supported yet, sorry. However, Rudolf Marek is working on K8T890/VT8237
support if that helps...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Thu Jul 12 15:23:40 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 15:23:40 +0200
Subject: [LinuxBIOS] [PATCH][v3] Merge hlt() into cpu.h (svn resync)
In-Reply-To: <20070712130657.GC26506@greenwood>
References: <20070712014423.GI8025@greenwood>
	<20070712022746.2410.qmail@stuge.se>
	<20070712130657.GC26506@greenwood>
Message-ID: <20070712132340.GB29188@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [070712 15:06]:
> Hm, but given your above explanations that the hlt() may not really
> completely halt, I'd say that we really should move the loop into
> hlt(). When I call hlt() from my code I _expect_ a full halt, I don't
> want _any_ other code exectuted.

It's hlt, not halt. This is the instruction that used to be
called in the idle loop to make the cpu _sleep_ until new work occurs.

Please don't break the current, correct behavior.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From lemenkov at gmail.com  Thu Jul 12 15:30:53 2007
From: lemenkov at gmail.com (Peter Lemenkov)
Date: Thu, 12 Jul 2007 17:30:53 +0400
Subject: [LinuxBIOS] Does my MoBo supported?
In-Reply-To: <20070712132305.GG26506@greenwood>
References: <adf480660707110621l20783bf8v67e7d652defde993@mail.gmail.com>
	<20070712132305.GG26506@greenwood>
Message-ID: <adf480660707120630s636ef1b0x4bfe77b4cc78b989@mail.gmail.com>

Hello All!

2007/7/12, Uwe Hermann <uwe at hermann-uwe.de>:

> > One of that cars identified as Gigabyte 7VT880-RZ (based on VIA KT880 + VT8237R)
>
> Not supported yet, sorry. However, Rudolf Marek is working on K8T890/VT8237
> support if that helps...

I've got an idea!
There is a list of supported and partially supported chipsets and mainboards.
Why don't list also unsupported chipsets (and, maybe m/b too)?
I think it would be useful also.

-- 
With best regards!



From uwe at hermann-uwe.de  Thu Jul 12 15:34:29 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 15:34:29 +0200
Subject: [LinuxBIOS] r447 - in LinuxBIOSv3:
	include/device	mainboard/emulation/qemu-x86
In-Reply-To: <20070712085317.GB30653@coresystems.de>
References: <20070712085317.GB30653@coresystems.de>
Message-ID: <20070712133429.GH26506@greenwood>

On Thu, Jul 12, 2007 at 10:53:17AM +0200, Stefan Reinauer wrote:
> * svn at openbios.org <svn at openbios.org> [070712 03:03]:
> > Some minor cosmetic fixes (trivial).
> > -/* no printk allowed until hardware is ready; hardware is ready */
> >  /** 
> > - * start up hardware needed for stage1
> > + * Start up hardware needed for stage1.
> > + *
> > + * No printk() allowed until hardware is ready; hardware is ready.
> > + * TODO: Fix above comment? It's unclear.
> >   */
> 
> I don't think it is. Without hardware to print on, no printk. What's
> unclear with that?

Hm, I don't understand the intention and why it's in that file.

Sure, as a general comment it's correct. If you don't have hardware you
cannot print on it. For QEMU this is not correct, though, it emulates
a serial console (and/or VGA console), so it _is_ posible to pritnk().

Is the comment supposed to say that we don't need special UART init
for QEMU, as it will work right from the start?

The comment just confuses me.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Jul 12 15:48:20 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 12 Jul 2007 15:48:20 +0200
Subject: [LinuxBIOS] Does my MoBo supported?
In-Reply-To: <adf480660707120630s636ef1b0x4bfe77b4cc78b989@mail.gmail.com>
References: <adf480660707110621l20783bf8v67e7d652defde993@mail.gmail.com>
	<20070712132305.GG26506@greenwood>
	<adf480660707120630s636ef1b0x4bfe77b4cc78b989@mail.gmail.com>
Message-ID: <20070712134820.GJ26506@greenwood>

On Thu, Jul 12, 2007 at 05:30:53PM +0400, Peter Lemenkov wrote:
> Hello All!
>
> 2007/7/12, Uwe Hermann <uwe at hermann-uwe.de>:
>
>> > One of that cars identified as Gigabyte 7VT880-RZ (based on VIA KT880 + 
>> VT8237R)
>>
>> Not supported yet, sorry. However, Rudolf Marek is working on 
>> K8T890/VT8237
>> support if that helps...
>
> I've got an idea!
> There is a list of supported and partially supported chipsets and 
> mainboards.
> Why don't list also unsupported chipsets (and, maybe m/b too)?
> I think it would be useful also.

Everything which is not listed is not supported. :) No need to list "all"
non-supported chipsets (we wouldn't be able to gather the "full" list
anyway, and there's not point in doing it).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From juergen127 at kreuzholzen.de  Thu Jul 12 15:57:03 2007
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Thu, 12 Jul 2007 15:57:03 +0200
Subject: [LinuxBIOS] [PATCH][v3] Merge hlt() into cpu.h (svn resync)
In-Reply-To: <20070712132340.GB29188@coresystems.de>
References: <20070712014423.GI8025@greenwood>
	<20070712130657.GC26506@greenwood>
	<20070712132340.GB29188@coresystems.de>
Message-ID: <200707121557.04926.juergen127@kreuzholzen.de>

On Thursday 12 July 2007 15:23, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [070712 15:06]:
> > Hm, but given your above explanations that the hlt() may not really
> > completely halt, I'd say that we really should move the loop into
> > hlt(). When I call hlt() from my code I _expect_ a full halt, I don't
> > want _any_ other code exectuted.
>
> It's hlt, not halt. This is the instruction that used to be
> called in the idle loop to make the cpu _sleep_ until new work occurs.

When no interrupt, reset, NMI or SMI occures the "hlt" opcode let the CPU 
sleep forever.
Do we are using interrupts in LBv3?

Juergen



From stepan at coresystems.de  Thu Jul 12 16:00:07 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 16:00:07 +0200
Subject: [LinuxBIOS] [PATCH][v3] Merge hlt() into cpu.h (svn resync)
In-Reply-To: <200707121557.04926.juergen127@kreuzholzen.de>
References: <20070712014423.GI8025@greenwood>
	<20070712130657.GC26506@greenwood>
	<20070712132340.GB29188@coresystems.de>
	<200707121557.04926.juergen127@kreuzholzen.de>
Message-ID: <20070712140007.GA1765@coresystems.de>

* Juergen Beisert <juergen127 at kreuzholzen.de> [070712 15:57]:
> When no interrupt, reset, NMI or SMI occures the "hlt" opcode let the CPU 
> sleep forever.
> Do we are using interrupts in LBv3?

I guess we can not guarantee that there is no NMI.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From info at coresystems.de  Thu Jul 12 16:00:46 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 12 Jul 2007 16:00:46 +0200
Subject: [LinuxBIOS] r2733 build service
Message-ID: <E1I8zDq-0001VO-Nd@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2733 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Generic driver for pretty much all known Standard Microsystems Corporation
(SMSC) Super I/O chips.

Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.

So far only the ASUS A8000 has been tested on real hardware!

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2733&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2733&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2733&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2733&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2733&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2733&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From polytan at gmail.com  Thu Jul 12 16:05:07 2007
From: polytan at gmail.com (polytan)
Date: Thu, 12 Jul 2007 16:05:07 +0200
Subject: [LinuxBIOS] Does my MoBo supported?
In-Reply-To: <20070712134820.GJ26506@greenwood>
References: <adf480660707110621l20783bf8v67e7d652defde993@mail.gmail.com>
	<20070712132305.GG26506@greenwood>
	<adf480660707120630s636ef1b0x4bfe77b4cc78b989@mail.gmail.com>
	<20070712134820.GJ26506@greenwood>
Message-ID: <741f8c060707120705m4a64bcb6l33757b5a245ddb93@mail.gmail.com>

I would like my chipset supported to, a intel i845 on MS-6391 !

http://www.msicomputer.com/product/detail_spec/845pro4.htm

The bios is not soldered, just on a PLCC support.

Cheers,

Polytan

2007/7/12, Uwe Hermann <uwe at hermann-uwe.de>:
>
> On Thu, Jul 12, 2007 at 05:30:53PM +0400, Peter Lemenkov wrote:
> > Hello All!
> >
> > 2007/7/12, Uwe Hermann <uwe at hermann-uwe.de>:
> >
> >> > One of that cars identified as Gigabyte 7VT880-RZ (based on VIA KT880
> +
> >> VT8237R)
> >>
> >> Not supported yet, sorry. However, Rudolf Marek is working on
> >> K8T890/VT8237
> >> support if that helps...
> >
> > I've got an idea!
> > There is a list of supported and partially supported chipsets and
> > mainboards.
> > Why don't list also unsupported chipsets (and, maybe m/b too)?
> > I think it would be useful also.
>
> Everything which is not listed is not supported. :) No need to list "all"
> non-supported chipsets (we wouldn't be able to gather the "full" list
> anyway, and there's not point in doing it).
>
>
> Uwe.
> --
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
>
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.6 (GNU/Linux)
>
> iD8DBQFGljEkXdVoV3jWIbQRAsBZAJ9VploWH7YjbBSIOrNxSMXXprSLrgCgmnnb
> 9AbBUQ9ydD54bRfS480JuO8=
> =Pjuy
> -----END PGP SIGNATURE-----
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>



-- 

  -=( Polytan )=-
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From stepan at coresystems.de  Thu Jul 12 16:37:09 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 16:37:09 +0200
Subject: [LinuxBIOS] [PATCH] v3: compile on Mac OS X
Message-ID: <20070712143709.GA8372@coresystems.de>

This patch fixes compilation on OS X

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
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From stepan at coresystems.de  Thu Jul 12 16:49:35 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 16:49:35 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <20070711224920.761.qmail@stuge.se>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711224920.761.qmail@stuge.se>
Message-ID: <20070712144935.GA13584@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 00:49]:
> > +static int lar_read_size(struct lar *lar, int filelen)
> > +{
> > +	unsigned int *ptr = (unsigned int *) (lar->map + (filelen - 12));
> > +	return ptr[0];
> > +}
> 
> What about all this pointer arithmetic? Is it really correct?
 
This code is not new, it is in another file already.

> Doesn't adding 1 to a pointer actually add sizeof pointed-to-type to
> the address? Ie. this code isn't portable?

What makes you think so? It fetches an int from 12 bytes before the end
of the file (ie. after the reset vector). 

It is of course not portable because there is no reset vector at
fffffff0 on non x86 machines. But that's another issue.

> Then there's the matter of the pointer arithmetic again. Since ptr is
> uchar * this will work, but then writing size to p[0] will write a
> different number of bytes on different archs, right?

int is 32bit on all GNU architectures I know that could theoretically
run LinuxBIOS. But since this is an x86 only thing anyways I would not
care too much.
 
> > +	lar =  _open_lar(archive, s.st_size, O_RDWR);
> 
> Race conditions. First open() then fstat() to get the size.
> 
> Also, the file size can change even though we've opened the file.
> 
> Since the size is a rather important variable throughout lar we
> want to be able to handle it changing under our feet, but I don't
> know what the best way would be?
 
What kind of situation that realisticly happens would produce such an
issue? i.e. While a payload builds a lar, or while LinuxBIOS is
compiled?

> > +	mkdirp((const char *) dirname(path), 0755);
> > +	free(path);
> > +
> > +	fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644);
> > +
> > +	if (fd == -1) {
> > +		err("Error creating file %s\n", filename);
> > +		return -1;
> > +	}
> 
> I don't think lar should mkdir -p implicitly. Just open() and
> perror() or print strerror(errno) in case of failure.
 
Oh it does not do this implicitly. It only does it if the archive
explicitly contains a directory.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From info at coresystems.de  Thu Jul 12 16:51:21 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 12 Jul 2007 16:51:21 +0200
Subject: [LinuxBIOS] r2734 build service
Message-ID: <E1I900n-0000Z6-5O@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2734 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
[Arg! Forgot to 'svn add', sorry]

Generic driver for pretty much all known Standard Microsystems Corporation
(SMSC) Super I/O chips.

Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.

So far only the ASUS A8000 has been tested on real hardware!

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2734&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2734&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2734&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2734&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2734&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2734&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From stepan at coresystems.de  Thu Jul 12 16:52:12 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 16:52:12 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <20070711225841.2044.qmail@stuge.se>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711224920.761.qmail@stuge.se>
	<20070711225841.2044.qmail@stuge.se>
Message-ID: <20070712145212.GB13584@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 00:58]:
> Sorry. Since we don't store directories in lar it should indeed mkdir
> -p implicitly. But I think a bit of sanity would be nice here since a
> lar could otherwise be used to overwrite arbitrary system files.

You compile LinuxBIOS as root?

> I'll make a patch for mkdirp() that ensures the directory to be
> created is actually below the current directory (and also improve the
> return-to-cwd code in mkdir() a bit while at it) if there's interest.
> Would that be the right place to put it?

Rather check the path before mkdir()ing.

I am pretty sure the mkdir efforts can easily be tricked by a couple of
symlinks in the path, so I wonder how much use there is in trying to
make this "secure" since it never runs as root anyways, and in a very
controlled environment.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Thu Jul 12 16:54:13 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 16:54:13 +0200
Subject: [LinuxBIOS] [PATCH][LAR] New LAR access functions
In-Reply-To: <20070711181517.GD20885@cosmic.amd.com>
References: <20070711181517.GD20885@cosmic.amd.com>
Message-ID: <20070712145413.GC13584@coresystems.de>

* Jordan Crouse <jordan.crouse at amd.com> [070711 20:15]:
> This takes the code previous in create.c, extract.c, list.c
> and bootblock.c, and consolidates them into one file. 

Why?


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul 12 16:56:12 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 16:56:12 +0200
Subject: [LinuxBIOS] [PATCH][LAR]  Remove old files
In-Reply-To: <20070711230541.3127.qmail@stuge.se>
References: <20070711181619.GE20885@cosmic.amd.com>
	<20070711230541.3127.qmail@stuge.se>
Message-ID: <20070712145612.GD13584@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 01:05]:
> On Wed, Jul 11, 2007 at 12:16:19PM -0600, Jordan Crouse wrote:
> > Simple patch - this removes the files that were obsoleted by the
> > previous patch.
> 
> For the next iteration please add these two patches together since
> they belong together IMHO.

Or better: First do the concatenation and deletion and then start
changing the new file. If we really have to make one big mess out of it.
It makes me think of romcc with 26klocs in a single file :)

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From joe at smittys.pointclark.net  Thu Jul 12 16:59:02 2007
From: joe at smittys.pointclark.net (Joseph Smith)
Date: Thu, 12 Jul 2007 10:59:02 -0400
Subject: [LinuxBIOS] Does my MoBo supported?
In-Reply-To: <741f8c060707120705m4a64bcb6l33757b5a245ddb93@mail.gmail.com>
References: <adf480660707110621l20783bf8v67e7d652defde993@mail.gmail.com>
	<20070712132305.GG26506@greenwood>
	<adf480660707120630s636ef1b0x4bfe77b4cc78b989@mail.gmail.com>
	<20070712134820.GJ26506@greenwood>
	<741f8c060707120705m4a64bcb6l33757b5a245ddb93@mail.gmail.com>
Message-ID: <20070712105902.8wsovr2in4k8w4g8@www.smittys.pointclark.net>

Quoting polytan <polytan at gmail.com>:

> I would like my chipset supported to, a intel i845 on MS-6391 !
>
> http://www.msicomputer.com/product/detail_spec/845pro4.htm
>
> The bios is not soldered, just on a PLCC support.
>
> Cheers,
>
> Polytan
>
> 2007/7/12, Uwe Hermann <uwe at hermann-uwe.de>:
>>
>> On Thu, Jul 12, 2007 at 05:30:53PM +0400, Peter Lemenkov wrote:
>>> Hello All!
>>>
>>> 2007/7/12, Uwe Hermann <uwe at hermann-uwe.de>:
>>>
>>>> > One of that cars identified as Gigabyte 7VT880-RZ (based on VIA KT880
>> +
>>>> VT8237R)
>>>>
>>>> Not supported yet, sorry. However, Rudolf Marek is working on
>>>> K8T890/VT8237
>>>> support if that helps...
>>>
>>> I've got an idea!
>>> There is a list of supported and partially supported chipsets and
>>> mainboards.
>>> Why don't list also unsupported chipsets (and, maybe m/b too)?
>>> I think it would be useful also.
>>
>> Everything which is not listed is not supported. :) No need to list "all"
>> non-supported chipsets (we wouldn't be able to gather the "full" list
>> anyway, and there's not point in doing it).
>>
>>
>> Uwe.
>> --
>> http://www.hermann-uwe.de  | http://www.holsham-traders.de
>> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
>>
>> -----BEGIN PGP SIGNATURE-----
>> Version: GnuPG v1.4.6 (GNU/Linux)
>>
>> iD8DBQFGljEkXdVoV3jWIbQRAsBZAJ9VploWH7YjbBSIOrNxSMXXprSLrgCgmnnb
>> 9AbBUQ9ydD54bRfS480JuO8=
>> =Pjuy
>> -----END PGP SIGNATURE-----
>>
>> --
>> linuxbios mailing list
>> linuxbios at linuxbios.org
>> http://www.linuxbios.org/mailman/listinfo/linuxbios
>>
>
>
>
> -- 
>
>  -=( Polytan )=-

Hello,
The i845 is very close to the chipset I am working on. I have refered  
to it's datasheets a few times, just to have another view. This will  
be my next mission.

Thanks - Joe



From jordan.crouse at amd.com  Thu Jul 12 17:03:07 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 12 Jul 2007 09:03:07 -0600
Subject: [LinuxBIOS] PATCH][LAR] Allow user to specify pathnames for
 create and add
In-Reply-To: <20070712111009.GE24120@coresystems.de>
References: <20070711182227.GF20885@cosmic.amd.com>
	<20070711233610.7951.qmail@stuge.se>
	<20070711235010.GD3127@cosmic.amd.com>
	<20070712111009.GE24120@coresystems.de>
Message-ID: <20070712150307.GG3127@cosmic.amd.com>

On 12/07/07 13:10 +0200, Stefan Reinauer wrote:
> * Jordan Crouse <jordan.crouse at amd.com> [070712 01:50]:
> > --------------------------------------------
> > # MANIFEST
> > # Filename	    pathname		algorithm
> > /root/my.payload    normal/payload	lzma
> > ...
> > bootblock	    bootblock		-
> 
> Do we really need to distinguish between filename and pathname? I don't
> understand the difference here, unless it's a copy operation instead of
> an archive. Back when we invented lar, we thought about making all
> matches via the filename. So I think pathname is an idea to go away from
> that fixed mapping again...?

Actually - pathname *is* the fixed mapping.  The filename:pathname scheme
is to bridge the gap between a real world filename (like say, filo.elf),
and the mapping within the LAR that LinuxBIOS understands (normal/payload).

> I'd rather define file types rather than pathnames? 
> 
> Or is the pathname such a filetype, and the name is just ambiguous?

Sure - we can use the term filetype if you want.  Pathname is a little
bit more descriptive, since the LAR can technically hold arbitrary blobs
of data - what ever the loader needs ('vsa') comes to mind.

But its just a term - I would be happy to use filetype if thats a better
way to think about these things.

Jordan
-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From jordan.crouse at amd.com  Thu Jul 12 17:05:25 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 12 Jul 2007 09:05:25 -0600
Subject: [LinuxBIOS] Add a top level target for LAR
In-Reply-To: <20070712101845.GB24120@coresystems.de>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070712101845.GB24120@coresystems.de>
Message-ID: <20070712150525.GH3127@cosmic.amd.com>

On 12/07/07 12:18 +0200, Stefan Reinauer wrote:
> * Jordan Crouse <jordan.crouse at amd.com> [070711 20:07]:
> > This is the easiest patch.. :)  Add a top level 'lar' target to v3, 
> > so I can build the utility by itself.  Until LAR gets seperated out
> > into its own repository, I'm going to have to figure out a way to make
> > buildROM build lar independently of the rest of the v3 code, and this is
> > probably the best way.
> 
> Not sure I get this right. What's the purpose? Don't you build
> linuxbios, too?

Yes - but I would like to build LAR seperately, if I can.  buildROM works
better when the pieces are more modular, and I can pick and choose what
I need to build.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From stepan at coresystems.de  Thu Jul 12 17:25:31 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 17:25:31 +0200
Subject: [LinuxBIOS] status update - K8T890/VT8237
In-Reply-To: <469605CF.6020607@assembler.cz>
References: <4694125B.6030507@assembler.cz>
	<20070711005146.27625.qmail@stuge.se>
	<469605CF.6020607@assembler.cz>
Message-ID: <20070712152531.GA10184@coresystems.de>

* Rudolf Marek <r.marek at assembler.cz> [070712 12:43]:
>          limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
> 
> I think there is missing -1
> 
> ((resource->base + resource->size - 1) >> 8) & 0xffffff00;
 
> After this fix the MMIO for VGA is from A0000 to BFFFF
 
Looks reasonable

> BUT! The VGA ROM seems to be mapped to C8000! How is this possible? Why is 
> linuxbios claiming that the RAM is from C0000-EFFFF???

Weird. It should be mapped to C0000 and that is usually hardcoded. What
card is that? External? Is there onboard VGA?


 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From peter at stuge.se  Thu Jul 12 17:27:35 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 17:27:35 +0200
Subject: [LinuxBIOS] Winflashrom -- Current Status
In-Reply-To: <4695FED2.6020100@gmail.com>
References: <46886eb7.27ed720a.5795.ffffedbb@mx.google.com>
	<4688C2BF.2040600@gmail.com> <20070702193703.21913.qmail@stuge.se>
	<4695D613.6080603@gmail.com> <20070712080556.18303.qmail@stuge.se>
	<4695FED2.6020100@gmail.com>
Message-ID: <20070712152735.21325.qmail@stuge.se>

On Thu, Jul 12, 2007 at 05:13:38PM +0700, Darmawan Salihun wrote:
> > As for the EPIA board, well, where is that base specified? In a
> > PCI config register or where?
> 
> The base is in a PCI config register. Relevant code as follows:
> 
>     base = pci_read_word(dev, 0x88) & 0xFF80;
> 
>     val = inb(base + 0x4D);
>     val |= 0x80;
>     outb(val, base + 0x4D);

Ok! Put all of board_enable.c in the kernel driver and add some way
for the app to call any function in the board_pciid_enables list, in
the kernel driver. Sort of RPC but over a app/kernel split instead of
over a network.

Then compile board_enable.c also into the app, but not to call any of
the functions (which would fail anyway) but only to get the same
board_pciid_enables list. The struct may have to be extended to have
a unique index for each entry so that the driver and app can agree on
which function is which.

All of the device detection should be done where it is easiest to do
it. Since the driver will need to do safe PCI accesses for board
enables perhaps it makes sense to contain all PCI accesses in the
driver.

On the other hand, perhaps the app will need to do some PCI accesses
to choose the right board_enable function and then it's better to do
most of them in the app.

What do you think?


Another general matter, make sure the app and driver can exchange
version numbers. That way both the driver and the app could have
compatiblity code in order to be backwards compatible.

I would like the app to exit with an error message if it can't agree
with the kernel driver on a "protocol version" that both of them
support. Need not be fancy right now, a simple two-way version check
is plenty good.


//Peter



From jordan.crouse at amd.com  Thu Jul 12 17:27:49 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 12 Jul 2007 09:27:49 -0600
Subject: [LinuxBIOS] New LAR access functions
In-Reply-To: <20070712010550.22074.qmail@stuge.se>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711221134.27245.qmail@stuge.se>
	<429EB3D7-44E4-447D-931C-2B83D73F9163@kernel.crashing.org>
	<20070712010550.22074.qmail@stuge.se>
Message-ID: <20070712152749.GK3127@cosmic.amd.com>

On 12/07/07 03:05 +0200, Peter Stuge wrote:
> On Thu, Jul 12, 2007 at 02:16:21AM +0200, Segher Boessenkool wrote:
> > > 1 means combining flashrom and lar somehow.. Thoughts?
> > 
> > I think the boot block should be outside of the LAR completely.
> 
> Hmm. Interesting!
> 
> 
> > A normal LinuxBIOS upgrade shouldn't touch the bootblock;
> 
> I agree. That's why lar should know about flash chip sector sizes.

This is probably best - lar is best suited for doing the math and
making sure that the blobs are written out in the right format. Somewhat
safer then making flashrom rearrange the bits later.

I'm thinking that we could probably get away with someting simple like
a -S <sector size> option, and LAR would would arrange the archive
correctly, and then write the sector size along with the total ROM size
in the "bootblock header".

> And/or flashrom about larballs.

flashrom should at the very least know how to read a lar and make sure
it is sane.  If we include the sector size from above, then flashrom 
could do some very basic sanity checking before starting.
> 
> > that way, recovery code in there can help the user load a working
> > image into flash after some screw-up, over a serial port or
> > whatever.
> > 
> > This also handily solves the current problem :-)
> 
> But it creates another quite real problem for the first upgrade to LB
> where we need to distribute the bootblock separately. I think that's
> a _really_ undesirable scenario. :\ Especially since it will be the
> common case for some time still.
> 
> One file is no file, two files are two files too many. ;)

I completely agree.  Its always best to only have a single deliverable.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From peter at stuge.se  Thu Jul 12 17:33:57 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 17:33:57 +0200
Subject: [LinuxBIOS] PATCH: mkdirp() error on new directory
	outside	given parent
In-Reply-To: <20070712124936.GA25662@coresystems.de>
References: <20070712075011.16157.qmail@stuge.se>
	<20070712124936.GA25662@coresystems.de>
Message-ID: <20070712153357.22175.qmail@stuge.se>

On Thu, Jul 12, 2007 at 02:49:36PM +0200, Stefan Reinauer wrote:
> * Peter Stuge <peter at stuge.se> [070712 09:50]:
> > Have a look.
> 
> I think the better way would be to check the paths for ../ and skip
> those with a warning.

Then there are the symlinks. :\


//Peter



From jordan.crouse at amd.com  Thu Jul 12 17:34:58 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 12 Jul 2007 09:34:58 -0600
Subject: [LinuxBIOS] New LAR access functions
In-Reply-To: <20070712004606.19095.qmail@stuge.se>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711224920.761.qmail@stuge.se>
	<20070711233841.GB3127@cosmic.amd.com>
	<20070712004606.19095.qmail@stuge.se>
Message-ID: <20070712153458.GL3127@cosmic.amd.com>

On 12/07/07 02:46 +0200, Peter Stuge wrote:
> On Wed, Jul 11, 2007 at 05:38:41PM -0600, Jordan Crouse wrote:
> > > > +	int size;
> > > 
> > > u32 size maybe?
> > 
> > I guess, though I'll bet this code doesn't survive long enough to
> > see those 2G ROM chips.. :)
> 
> I won't take that bet.
> 
> But it is nice to show that we have thought about it by being
> explicit. Eliminating potential portability problems is another plus.

Agreed - I'll make the change everywhere.

> > > > +	p = (unsigned int *) (ptr + BOOTBLOCK_SIZE - 12);
> > > > +	p[0] = size;
> > > > +}
> > > 
> > > Then there's the matter of the pointer arithmetic again. Since ptr
> > > is uchar * this will work, but then writing size to p[0] will write
> > > a different number of bytes on different archs, right?
> > 
> > sizeof(unsigned int) is 4 on all the platforms we care about.
> 
> 640k will be enough. ;)

Heh.  Fair enough - depending on compilers to obey convention is probably
not a smart idea.    I'll switch over to u8 and u32 universally - then
we'll be absolutely positive that we're !x86 friendly.

> 
> > > > + err:
> > > > +	if (lar->fd >= 0)
> > > > +		close(lar->fd);
> > > > +
> > > > +	unlink(archive);
> > > > +
> > > > +	if (lar)
> > > > +		free(lar);
> > > 
> > > If lar can be 0 at err: then the fd deref is a segfault waiting
> > > to happen.
> > 
> > Lar can't be 0 at err
> 
> Then the if (lar) free(lar); should change IMHO. It's confusing.

Oh wow - I didn't even notice that.  Yeah, it is confusing.  Sorry
about that.

> 
> Is lar->fd initialized to -1 btw?

lar->fd is the result of the open() - which will either be a -1 for
errors or >= for a legit file descriptor.

> The file can be corrupt, I just want to avoid making it 4G-256k.
> 
> I would be happy if lar exits with an error if the file size has
> changed between _open_lar() and _close_lar().

I'll do that - thats an easy check and it will probably save our bacon.
Then you can tell me "I told you so!".

> I'd prefer having that negation in the caller. Or at the very least
> doxygen comment it.

Yes.  Much doxygen is in my future.

Thanks.  I'm updating the code in real time, but suspect that we still
have a bit more discussion before the next revision goes out.. :)

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From peter at stuge.se  Thu Jul 12 17:47:16 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 17:47:16 +0200
Subject: [LinuxBIOS] [PATCH][v3] Merge hlt() into cpu.h (svn resync)
In-Reply-To: <20070712130657.GC26506@greenwood>
References: <20070712014423.GI8025@greenwood>
	<20070712022746.2410.qmail@stuge.se>
	<20070712130657.GC26506@greenwood>
Message-ID: <20070712154716.24583.qmail@stuge.se>

On Thu, Jul 12, 2007 at 03:06:57PM +0200, Uwe Hermann wrote:
> > > If so, shall we move the loop into hlt() itself?
> > 
> > I don't think so. hlt() is just a C wrapper around the instruction.
> 
> Hm, but given your above explanations that the hlt() may not really
> completely halt, I'd say that we really should move the loop into
> hlt().

Again, the function is a C interface to the instruction.

The instruction will always halt the CPU, but the CPU can wake up
again. All by design. :)


> When I call hlt() from my code I _expect_ a full halt, I don't want
> _any_ other code exectuted.

I think that's another function. Maybe it's die() or halt() but it
sure isn't what the hlt instruction does.


> Or ??s there some reason why you explicitly want that behaviour?

hlt can be used to sleep until further notice. I don't know if we do
in LB yet, but Linux executes hlt all the time. (Less with dynamic
clocks.)

There is definately a legitimate use of hlt() as it stands, but we
may not actually need it in LB at the moment. We would probably be
fine with just a halt().

Until we've looked into it further I think looping in die() is good.


> > Eventually I imagine building a panic room into die() so that
> 
> Yep, surely a nice idea (should be a Kconfig option, though).

Maybe an expert option that is enabled by default? Typically I'd like
it to always be available. But discussion for later.


> But maybe hlt() and die() should do just what they are supposed to
> do.

I think they do now.


> It may be better to make an explicit panicroom() function or so...

Yep, definately.


//Peter



From svn at openbios.org  Thu Jul 12 17:56:03 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu, 12 Jul 2007 17:56:03 +0200
Subject: [LinuxBIOS] r2735 - trunk/LinuxBIOSv2/src/mainboard/agami/aruma
Message-ID: <mailman.519.1355071133.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-07-12 17:56:02 +0200 (Thu, 12 Jul 2007)
New Revision: 2735

Modified:
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/mainboard.c
Log:
some agami i2c merges

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb	2007-07-12 13:13:56 UTC (rev 2734)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Config.lb	2007-07-12 15:56:02 UTC (rev 2735)
@@ -241,9 +241,7 @@
 
 dir /pc80
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # config for agami/aruma
 chip northbridge/amd/amdk8/root_complex
@@ -323,42 +321,52 @@
 				device pci 1.1 on end
 				device pci 1.2 on end
 				device pci 1.3 on 
-					chip drivers/generic/generic
-						#phillips pca9545 smbus mux
-						device i2c 70 on 
-							# analog_devices adm1026	
-							chip drivers/generic/generic
-								device i2c 2c on end
+                                        chip drivers/i2c/i2cmux2 # pca9545 smbus mux
+                                                device i2c 71 on     #pca9545 channel0
+                                                        chip drivers/i2c/adm1026
+                                                                device i2c 2d on end
+                                                        end
+                                                end
+						device i2c 71 on     #pca9545 channel1
+                                                        chip drivers/generic/generic # fan board / pstray behind another mux
+                                                                device i2c 2d on end
+                                                        end
+                                                end
+                                        end
+                                        chip drivers/i2c/i2cmux2 # pca9543 smbus mux
+                                                device i2c 73 on     #pca9543 channel0
+							chip drivers/generic/generic #dimm 0-0-0
+								device i2c 50 on end
 							end
+							chip drivers/generic/generic #dimm 0-0-1
+								device i2c 51 on end
+							end 
+							chip drivers/generic/generic #dimm 0-1-0
+								device i2c 52 on end
+							end 
+							chip drivers/generic/generic #dimm 0-1-1
+								device i2c 53 on end
+							end 
 						end
-						device i2c 70 on end
-						device i2c 70 on end
-						device i2c 70 on end
+
+                                                device i2c 73 on     #pca9543 channel1
+							chip drivers/generic/generic #dimm 1-0-0
+								device i2c 50 on end 
+							end
+							chip drivers/generic/generic #dimm 1-0-1
+								device i2c 51 on end
+							end 
+							chip drivers/generic/generic #dimm 1-1-0
+								device i2c 52 on end
+							end 
+							chip drivers/generic/generic #dimm 1-1-1
+								device i2c 53 on end
+							end 
+						end
+					end # chip end
+					chip drivers/generic/generic # ICS950405AF
+						device i2c 69 on end
 					end
-#					chip drivers/generic/generic #dimm 0-0-0
-#						device i2c 50 on end
-#					end
-#					chip drivers/generic/generic #dimm 0-0-1
-#						device i2c 51 on end
-#					end 
-#					chip drivers/generic/generic #dimm 0-1-0
-#						device i2c 52 on end
-#					end 
-#					chip drivers/generic/generic #dimm 0-1-1
-#						device i2c 53 on end
-#					end 
-#					chip drivers/generic/generic #dimm 1-0-0
-#						device i2c 54 on end 
-#					end
-#					chip drivers/generic/generic #dimm 1-0-1
-#						device i2c 55 on end
-#					end 
-#					chip drivers/generic/generic #dimm 1-1-0
-#						device i2c 56 on end
-#					end 
-#					chip drivers/generic/generic #dimm 1-1-1
-#						device i2c 57 on end
-#					end 
 				end
 				device pci 1.5 off end
 				device pci 1.6 on end

Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb	2007-07-12 13:13:56 UTC (rev 2734)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb	2007-07-12 15:56:02 UTC (rev 2735)
@@ -93,7 +93,15 @@
 # 256k
 default FALLBACK_SIZE=0x40000
 
+
 ##
+## Set this.
+##
+
+default CONFIG_CHIP_NAME=1
+
+
+##
 ## Build code for the fallback boot
 ##
 default HAVE_FALLBACK_BOOT=1

Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c	2007-07-12 13:13:56 UTC (rev 2734)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c	2007-07-12 15:56:02 UTC (rev 2735)
@@ -257,6 +257,10 @@
 	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
+	/* Reset SMBus switches to access the ADM1026 */
+        smbus_send_byte(SMBUS_SWITCH1, 0x0);
+        smbus_send_byte(SMBUS_SWITCH2, 0x0);
+
 	post_cache_as_ram();
 
 }

Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/mainboard.c	2007-07-12 13:13:56 UTC (rev 2734)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/mainboard.c	2007-07-12 15:56:02 UTC (rev 2735)
@@ -97,7 +97,7 @@
 }
 #endif
 
-#if 0
+#if 1
 static void handle_smbus_error(int value, const char *msg)
 {
 	if (value >= 0) {
@@ -118,7 +118,7 @@
 	}
 }
 
-#define ADM1026_DEVICE 0x2c /* 0x2e or 0x2d */
+#define ADM1026_DEVICE 0x2d /* 0x2e or 0x2c */
 #define ADM1026_REG_CONFIG1 0x00
 #define CFG1_MONITOR     0x01
 #define CFG1_INT_ENABLE  0x02
@@ -235,7 +235,7 @@
 		cpu_volts, delta);
 }
 
-#define SMBUS_MUX 0x70
+#define SMBUS_MUX 0x71
 
 static void do_verify_cpu_voltages(void)
 {
@@ -250,7 +250,7 @@
 	if (!smbus_dev) {
 		die("SMBUS controller not found\n");
 	}
-	
+
 	/* Find the smbus mux */
 	mux_path.type         = DEVICE_PATH_I2C;
 	mux_path.u.i2c.device = SMBUS_MUX;
@@ -309,31 +309,22 @@
 {
 	root_dev_init(dev);
 
-	do_verify_cpu_voltages();
+	printk_info("Initializing mainboard components... ");
+	// do_verify_cpu_voltages();
+	printk_info("ok\n");
 
 	printk_info("Initializing mainboard specific functions... ");
 	fixup_aruma();
 	printk_info("ok\n");
 }
 
-static struct device_operations mainboard_operations = {
-	.read_resources   = root_dev_read_resources,
-	.set_resources    = root_dev_set_resources,
-	.enable_resources = root_dev_enable_resources,
-	.init             = mainboard_init,
-#if !DEBUG
-	.scan_bus         = root_dev_scan_bus,
-#else
-	.scan_bus         = scan_root_bus,
-#endif
-	.enable           = 0,
-};
-
 static void enable_dev(struct device *dev)
 {
-	dev->ops = &mainboard_operations;
+	dev->ops->init = mainboard_init;
 }
+
 struct chip_operations mainboard_agami_aruma_ops = {
+	CHIP_NAME("AGAMI Aruma Mainboard")
 	.enable_dev = enable_dev, 
 };
 




From peter at stuge.se  Thu Jul 12 17:59:07 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 17:59:07 +0200
Subject: [LinuxBIOS] Add a top level target for LAR
In-Reply-To: <20070712102138.GC24120@coresystems.de>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070711181204.22915.qmail@stuge.se>
	<20070711183009.GI20885@cosmic.amd.com>
	<20070711230847.3685.qmail@stuge.se>
	<20070712102138.GC24120@coresystems.de>
Message-ID: <20070712155907.26551.qmail@stuge.se>

On Thu, Jul 12, 2007 at 12:21:38PM +0200, Stefan Reinauer wrote:
> > This is another reason to move util/ out to it's own home.
>  
> Please: Whoever moves lar to it's own repository: Make sure that it
> builds cleanly in v3 and out of v3 before doing so.

Good point. I can't even get it to build in v3:

LinuxBIOSv3 $ make util/lar/lar
gcc -Wall -g -I/home/stuge/lb/LinuxBIOSv3 -Iinclude -I/home/stuge/lb/LinuxBIOSv3/include -I/home/stuge/lb/LinuxBIOSv3/include/arch/x86/ -include /home/stuge/lb/LinuxBIOSv3/build/config.h -include /home/stuge/lb/LinuxBIOSv3/build/build.h   util/lar/lar.c   -o util/lar/lar
In file included from include/string.h:24,
                 from util/lar/lar.c:23:
/home/stuge/lb/LinuxBIOSv3/include/arch/x86/types.h:18: error: conflicting types for 'size_t'
/usr/lib/gcc/i686-pc-linux-gnu/4.1.1/include/stddef.h:214: error: previous declaration of 'size_t' was here
In file included from util/lar/lar.c:34:
util/lar/lar.h:58: error: redefinition of typedef 'u32'
/home/stuge/lb/LinuxBIOSv3/include/arch/x86/types.h:9: error: previous declaration of 'u32' was here
util/lar/lar.c: In function 'main':
util/lar/lar.c:99: warning: implicit declaration of function 'strcasecmp'
util/lar/lar.c:116: warning: implicit declaration of function 'strdup'
util/lar/lar.c:116: warning: incompatible implicit declaration of built-in function 'strdup'
util/lar/lar.c:140: warning: implicit declaration of function 'strncmp'
make: *** [util/lar/lar] Error 1

Help?


> Just moving it out to another repo without making it compilable
> outside makes no sense.
> Breaking the way it is built (out of the tree!) makes no sense
> either.
> 
> The same applies for flashrom.

I agree. What I actually am after is the same as Jordan - I want to
be able to build lar completely independently of v3.

Ie. checkout just v3/util/lar and go.

It does make sense to keep lar in the v3 repo until the point where
it is actually used in multiple versions of LB.


> BTW: We should really get lxbios.sf.net into the tree. That's far
> more important than fixing something that is not broken.

Agree! Is it possible to download the complete repo files from SF to
run cvs2svn on or will we lose history?


//Peter



From stepan at coresystems.de  Thu Jul 12 18:20:26 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 18:20:26 +0200
Subject: [LinuxBIOS] [PATCH] utils - include lxbios utility from
	lxbios.sf.net
Message-ID: <20070712162026.GA24178@coresystems.de>

Hi,

I think lxbios should be part of our utils/ suite...

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
-------------- next part --------------
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From peter at stuge.se  Thu Jul 12 18:21:37 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jul 2007 18:21:37 +0200
Subject: [LinuxBIOS] New LAR access functions
In-Reply-To: <20070712152749.GK3127@cosmic.amd.com>
References: <20070711181517.GD20885@cosmic.amd.com>
	<20070711221134.27245.qmail@stuge.se>
	<429EB3D7-44E4-447D-931C-2B83D73F9163@kernel.crashing.org>
	<20070712010550.22074.qmail@stuge.se>
	<20070712152749.GK3127@cosmic.amd.com>
Message-ID: <20070712162138.29920.qmail@stuge.se>

On Thu, Jul 12, 2007 at 09:27:49AM -0600, Jordan Crouse wrote:
> > I agree. That's why lar should know about flash chip sector sizes.
> 
> This is probably best - lar is best suited for doing the math and
> making sure that the blobs are written out in the right format.
> Somewhat safer then making flashrom rearrange the bits later.

I agree. But..


> I'm thinking that we could probably get away with someting simple
> like a -S <sector size> option, and LAR would would arrange the
> archive correctly, and then write the sector size along with the
> total ROM size in the "bootblock header".

..flash doesn't always have uniform sector sizes. E.g. SST49LF080A
http://www.sst.com/downloads/datasheet/S71235.pdf which has 16*4kb at
the bottom and 15*64kb for the rest. It would be nice to be able to
use those 16*4kb sectors for different things and not always need to
treat them as a single 64kb sector. -S is a great start though.


> > And/or flashrom about larballs.
> 
> flashrom should at the very least know how to read a lar and make
> sure it is sane.  If we include the sector size from above, then
> flashrom could do some very basic sanity checking before starting.

The real fun begins when larball has one sector size and flash chip
another, and we only want to replace a single larfile.


//Peter



From stepan at coresystems.de  Thu Jul 12 18:22:30 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 18:22:30 +0200
Subject: [LinuxBIOS] Add a top level target for LAR
In-Reply-To: <20070712155907.26551.qmail@stuge.se>
References: <20070711180747.GC20885@cosmic.amd.com>
	<20070711181204.22915.qmail@stuge.se>
	<20070711183009.GI20885@cosmic.amd.com>
	<20070711230847.3685.qmail@stuge.se>
	<20070712102138.GC24120@coresystems.de>
	<20070712155907.26551.qmail@stuge.se>
Message-ID: <20070712162229.GA25229@coresystems.de>

* Peter Stuge <peter at stuge.se> [070712 17:59]:
> On Thu, Jul 12, 2007 at 12:21:38PM +0200, Stefan Reinauer wrote:
> > > This is another reason to move util/ out to it's own home.
> >  
> > Please: Whoever moves lar to it's own repository: Make sure that it
> > builds cleanly in v3 and out of v3 before doing so.
> 
> Good point. I can't even get it to build in v3:
> 
> LinuxBIOSv3 $ make util/lar/lar

make build/util/lar/lar ?


> 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From stepan at coresystems.de  Thu Jul 12 18:23:19 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 12 Jul 2007 18:23:19 +0200
Subject: [LinuxBIOS] [PATCH][LAR] Add a top level target for LAR
In-Reply-To: <20070711180747.GC20885@cosmic.amd.com>
References: <20070711180747.GC20885@cosmic.amd.com>
Message-ID: <20070712162319.GB25229@coresystems.de>

* Jordan Crouse <jordan.crouse at amd.com> [070711 20:07]:
> This is the easiest patch.. :)  Add a top level 'lar' target to v3, 
> so I can build the utility by itself.  Until LAR gets seperated out
> into its own repository, I'm going to have to figure out a way to make
> buildROM build lar independently of the rest of the v3 code, and this is
> probably the best way.
> 
> Jordan

> [PATCH][LAR] Add a top level target for LAR
> 
> Add a top level target to the LAR makefile so it can be built by itself
> in the LBv3 tree.
> 
> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>

Not exectly sugar of elegance, but I think this works for us.

Acked-by: Stefan Reinauer <stepan at coresystems.de>


> Index: LinuxBIOSv3/util/lar/Makefile
> ===================================================================
> --- LinuxBIOSv3.orig/util/lar/Makefile	2007-07-09 11:47:18.000000000 -0600
> +++ LinuxBIOSv3/util/lar/Makefile	2007-07-09 11:47:33.000000000 -0600
> @@ -47,6 +47,8 @@
>  	$(Q)$(HOSTCC) $(HOSTCFLAGS) -c $< -o $@
>  
>  
> +lar: $(obj)/util/lar/lar
> +
>  # -----------------------------------------------------------------------------
>  # Stuff below this line is for debugging purposes only.
>  

> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From jordan.crouse at amd.com  Thu Jul 12 18:24:31 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 12 Jul 2007 10:24:31 -0600
Subject: [LinuxBIOS] utils - include lxbios utility from lxbios.sf.net
In-Reply-To: <20070712162026.GA24178@coresystems.de>
References: <20070712162026.GA24178@coresystems.de>
Message-ID: <20070712162431.GN3127@cosmic.amd.com>

On 12/07/07 18:20 +0200, Stefan Reinauer wrote:
> Hi,
> 
> I think lxbios should be part of our utils/ suite...
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>

> 
> 
> -- 
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

> Index: lxbios/lxbios.c
> ===================================================================
> --- lxbios/lxbios.c	(revision 0)
> +++ lxbios/lxbios.c	(revision 0)
> @@ -0,0 +1,754 @@
> +/*****************************************************************************\
> + * lxbios.c
> + * $Id: lxbios.c,v 1.3 2006/01/24 00:25:40 dsp_llnl Exp $
> + *****************************************************************************
> + *  Copyright (C) 2002-2005 The Regents of the University of California.
> + *  Produced at the Lawrence Livermore National Laboratory.
> + *  Written by Dave Peterson <dsp at llnl.gov> <dave_peterson at pobox.com>.
> + *  UCRL-CODE-2003-012
> + *  All rights reserved.
> + *
> + *  This file is part of lxbios, a utility for reading/writing LinuxBIOS
> + *  parameters and displaying information from the LinuxBIOS table.
> + *  For details, see <http://www.llnl.gov/linux/lxbios/>.
> + *
> + *  Please also read the file DISCLAIMER which is included in this software
> + *  distribution.
> + *
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License (as published by the
> + *  Free Software Foundation) version 2, dated June 1991.
> + *
> + *  This program is distributed in the hope that it will be useful, but
> + *  WITHOUT ANY WARRANTY; without even the IMPLIED WARRANTY OF
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the terms and
> + *  conditions of the GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, write to the Free Software Foundation, Inc.,
> + *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
> +\*****************************************************************************/
> +
> +#include "common.h"
> +#include "opts.h"
> +#include "lbtable.h"
> +#include "layout.h"
> +#include "layout_file.h"
> +#include "input_file.h"
> +#include "cmos_ops.h"
> +#include "cmos_lowlevel.h"
> +#include "reg_expr.h"
> +#include "hexdump.h"
> +
> +typedef void (*op_fn_t) (void);
> +
> +static void op_show_version (void);
> +static void op_show_usage (void);
> +static void op_lbtable_show_info (void);
> +static void op_lbtable_dump (void);
> +static void op_show_param_values (void);
> +static void op_cmos_show_one_param (void);
> +static void op_cmos_show_all_params (void);
> +static void op_cmos_set_one_param (void);
> +static void op_cmos_set_params_stdin (void);
> +static void op_cmos_set_params_file (void);
> +static void op_cmos_checksum (void);
> +static void op_show_layout (void);
> +static void op_write_cmos_dump (void);
> +static void op_read_cmos_dump (void);
> +static void op_show_cmos_hex_dump (void);
> +static void op_show_cmos_dumpfile (void);
> +static int list_one_param (const char name[], int show_name);
> +static int list_all_params (void);
> +static void list_param_enums (const char name[]);
> +static void set_one_param (const char name[], const char value[]);
> +static void set_params (FILE *f);
> +static void parse_assignment (char arg[], const char **name,
> +                              const char **value);
> +static int list_cmos_entry (const cmos_entry_t *e, int show_name);
> +static uint16_t convert_checksum_value (const char value[]);
> +
> +static const op_fn_t op_fns[] =
> + { op_show_version,
> +   op_show_usage,
> +   op_lbtable_show_info,
> +   op_lbtable_dump,
> +   op_show_param_values,
> +   op_cmos_show_one_param,
> +   op_cmos_show_all_params,
> +   op_cmos_set_one_param,
> +   op_cmos_set_params_stdin,
> +   op_cmos_set_params_file,
> +   op_cmos_checksum,
> +   op_show_layout,
> +   op_write_cmos_dump,
> +   op_read_cmos_dump,
> +   op_show_cmos_hex_dump,
> +   op_show_cmos_dumpfile
> + };
> +
> +static const hexdump_format_t cmos_dump_format =
> + { 16, 2, "", " | ", " ", " | ", '.', NULL };
> +
> +/****************************************************************************
> + * main
> + ****************************************************************************/
> +int main (int argc, char *argv[])
> + { cmos_layout_get_fn_t fn;
> +
> +   parse_lxbios_args(argc, argv);
> +
> +   if (lxbios_op_modifiers[LXBIOS_MOD_USE_CMOS_LAYOUT_FILE].found)
> +    { set_layout_filename(
> +            lxbios_op_modifiers[LXBIOS_MOD_USE_CMOS_LAYOUT_FILE].param);
> +      fn = get_layout_from_file;
> +    }
> +   else
> +      fn = get_layout_from_cmos_table;
> +
> +   register_cmos_layout_get_fn(fn);
> +   op_fns[lxbios_op.op]();
> +   return 0;
> + }
> +
> +/****************************************************************************
> + * op_show_version
> + *
> + * -v
> + *
> + * Show version information for this program.
> + ****************************************************************************/
> +static void op_show_version (void)
> + { printf("This is %s version %s.\n", prog_name, prog_version); }
> +
> +/****************************************************************************
> + * op_show_usage
> + *
> + * -h
> + *
> + * Show a usage message for this program.
> + ****************************************************************************/
> +static void op_show_usage (void)
> + { usage(stdout); }
> +
> +/****************************************************************************
> + * op_lbtable_show_info
> + *
> + * -l [ARG]
> + *
> + * If ARG is present, show LinuxBIOS table information specified by ARG.
> + * Else show all possible values for ARG.
> + ****************************************************************************/
> +static void op_lbtable_show_info (void)
> + { if (lxbios_op.param == NULL)
> +      list_lbtable_choices();
> +   else
> +    { get_lbtable();
> +      list_lbtable_item(lxbios_op.param);
> +    }
> + }
> +
> +/****************************************************************************
> + * op_lbtable_dump
> + *
> + * -d
> + *
> + * Do low-level dump of LinuxBIOS table.
> + ****************************************************************************/
> +static void op_lbtable_dump (void)
> + { get_lbtable();
> +   dump_lbtable();
> + }
> +
> +/****************************************************************************
> + * op_show_param_values
> + *
> + * -e NAME option
> + *
> + * Show all possible values for parameter NAME.
> + ****************************************************************************/
> +static void op_show_param_values (void)
> + { get_cmos_layout();
> +   list_param_enums(lxbios_op.param);
> + }
> +
> +/****************************************************************************
> + * op_cmos_show_one_param
> + *
> + * [-n] -r NAME
> + *
> + * Show parameter NAME.  If -n is specified, show value only.  Else show name
> + * and value.
> + ****************************************************************************/
> +static void op_cmos_show_one_param (void)
> + { int result;
> +
> +   get_cmos_layout();
> +   result = list_one_param(lxbios_op.param,
> +                  !lxbios_op_modifiers[LXBIOS_MOD_SHOW_VALUE_ONLY].found);
> +   cmos_checksum_verify();
> +
> +   if (result)
> +      exit(1);
> + }
> +
> +/****************************************************************************
> + * op_cmos_show_all_params
> + *
> + * -a
> + *
> + * Show names and values for all parameters.
> + ****************************************************************************/
> +static void op_cmos_show_all_params (void)
> + { int result;
> +
> +   get_cmos_layout();
> +   result = list_all_params();
> +   cmos_checksum_verify();
> +
> +   if (result)
> +      exit(1);
> + }
> +
> +/****************************************************************************
> + * op_cmos_set_one_param
> + *
> + * -w NAME=VALUE
> + *
> + * Set parameter NAME to VALUE.
> + ****************************************************************************/
> +static void op_cmos_set_one_param (void)
> + { const char *name, *value;
> +
> +   get_cmos_layout();
> +
> +   /* Separate 'NAME=VALUE' syntax into two strings representing NAME and
> +    * VALUE.
> +    */
> +   parse_assignment(lxbios_op.param, &name, &value);
> +
> +   set_one_param(name, value);
> + }
> +
> +/****************************************************************************
> + * op_cmos_set_params_stdin
> + *
> + * -i
> + *
> + * Set parameters according to standard input.
> + ****************************************************************************/
> +static void op_cmos_set_params_stdin (void)
> + { get_cmos_layout();
> +   set_params(stdin);
> + }
> +
> +/****************************************************************************
> + * op_cmos_set_params_file
> + *
> + * -p INPUT_FILE
> + *
> + * Set parameters according to INPUT_FILE.
> + ****************************************************************************/
> +static void op_cmos_set_params_file (void)
> + { FILE *f;
> +
> +   if ((f = fopen(lxbios_op.param, "r")) == NULL)
> +    { fprintf(stderr, "%s: Can not open file %s for reading: %s\n",
> +              prog_name, lxbios_op.param, strerror(errno));
> +      exit(1);
> +    }
> +
> +   get_cmos_layout();
> +   set_params(f);
> +   fclose(f);
> + }
> +
> +/****************************************************************************
> + * op_cmos_checksum
> + *
> + * -c [VALUE]
> + *
> + * If VALUE is present, set LinuxBIOS CMOS checksum to VALUE.  Else show
> + * checksum value.
> + ****************************************************************************/
> +static void op_cmos_checksum (void)
> + { uint16_t checksum;
> +
> +   get_cmos_layout();
> +
> +   if (lxbios_op.param == NULL)
> +    { set_iopl(3);
> +      checksum = cmos_checksum_read();
> +      set_iopl(0);
> +      printf("0x%x\n", checksum);
> +    }
> +   else
> +    { checksum = convert_checksum_value(lxbios_op.param);
> +      set_iopl(3);
> +      cmos_checksum_write(checksum);
> +      set_iopl(0);
> +    }
> + }
> +
> +/****************************************************************************
> + * op_show_layout
> + *
> + * -Y
> + *
> + * Write CMOS layout information to standard output.
> + ****************************************************************************/
> +static void op_show_layout (void)
> + { get_cmos_layout();
> +   write_cmos_layout(stdout);
> + }
> +
> +/****************************************************************************
> + * op_write_cmos_dump
> + *
> + * -b OUTPUT_FILE
> + *
> + * Write the contents of CMOS memory to a binary file.
> + ****************************************************************************/
> +static void op_write_cmos_dump (void)
> + { unsigned char data[CMOS_SIZE];
> +   FILE *f;
> +
> +   if ((f = fopen(lxbios_op.param, "w")) == NULL)
> +    { fprintf(stderr, "%s: Can not open file %s for writing: %s\n",
> +              prog_name, lxbios_op.param, strerror(errno));
> +      exit(1);
> +    }
> +
> +   set_iopl(3);
> +   cmos_read_all(data);
> +   set_iopl(0);
> +
> +   if (fwrite(data, 1, CMOS_SIZE, f) != CMOS_SIZE)
> +    { fprintf(stderr, "%s: Error writing CMOS data to file %s: %s\n",
> +              prog_name, lxbios_op.param, strerror(errno));
> +      exit(1);
> +    }
> +
> +   fclose(f);
> + }
> +
> +/****************************************************************************
> + * op_read_cmos_dump
> + *
> + * -B INPUT_FILE
> + *
> + * Read binary data from a file and write the data to CMOS memory.
> + ****************************************************************************/
> +static void op_read_cmos_dump (void)
> + { unsigned char data[CMOS_SIZE];
> +   size_t nr_bytes;
> +   FILE *f;
> +
> +   if ((f = fopen(lxbios_op.param, "r")) == NULL)
> +    { fprintf(stderr, "%s: Can not open file %s for reading: %s\n",
> +              prog_name, lxbios_op.param, strerror(errno));
> +      exit(1);
> +    }
> +
> +   if ((nr_bytes = fread(data, 1, CMOS_SIZE, f)) != CMOS_SIZE)
> +    { fprintf(stderr, "%s: Error: Only able to read %d bytes of CMOS data "
> +              "from file %s.  CMOS data is unchanged.\n", prog_name,
> +              (int) nr_bytes, lxbios_op.param);
> +      exit(1);
> +    }
> +
> +   fclose(f);
> +   set_iopl(3);
> +   cmos_write_all(data);
> +   set_iopl(0);
> + }
> +
> +/****************************************************************************
> + * op_show_cmos_hex_dump
> + *
> + * -x
> + *
> + * Write a hex dump of CMOS memory to standard output.
> + ****************************************************************************/
> +static void op_show_cmos_hex_dump (void)
> + { unsigned char data[CMOS_SIZE];
> +
> +   set_iopl(3);
> +   cmos_read_all(data);
> +   set_iopl(0);
> +   hexdump(data, CMOS_SIZE, 0, stdout, &cmos_dump_format);
> + }
> +
> +/****************************************************************************
> + * op_show_cmos_dumpfile
> + *
> + * -X DUMP_FILE
> + *
> + * Read binary data from a file (presumably a CMOS dump file) and display a
> + * hex dump of the CMOS data from the file.
> + ****************************************************************************/
> +static void op_show_cmos_dumpfile (void)
> + { unsigned char data[CMOS_SIZE];
> +   size_t nr_bytes;
> +   FILE *f;
> +
> +   if ((f = fopen(lxbios_op.param, "r")) == NULL)
> +    { fprintf(stderr, "%s: Can not open file %s for reading: %s\n",
> +              prog_name, lxbios_op.param, strerror(errno));
> +      exit(1);
> +    }
> +
> +   nr_bytes = fread(data, 1, CMOS_SIZE, f);
> +   fclose(f);
> +   hexdump(data, nr_bytes, 0, stdout, &cmos_dump_format);
> + }
> +
> +/****************************************************************************
> + * list_one_param
> + *
> + * Attempt to list one CMOS parameter given by 'name'.  'show_name' is a
> + * boolean value indicating whether the parameter name should be displayed
> + * along with its value.  Return 1 if error was encountered.  Else return OK.
> + ****************************************************************************/
> +static int list_one_param (const char name[], int show_name)
> + { const cmos_entry_t *e;
> +
> +   if (is_checksum_name(name) || ((e = find_cmos_entry(name)) == NULL))
> +    { fprintf(stderr, "%s: CMOS parameter %s not found.\n", prog_name, name);
> +      exit(1);
> +    }
> +
> +   if (e->config == CMOS_ENTRY_RESERVED)
> +    { fprintf(stderr, "%s: Parameter %s is reserved.\n", prog_name, name);
> +      exit(1);
> +    }
> +
> +   return (list_cmos_entry(e, show_name) != 0);
> + }
> +
> +/****************************************************************************
> + * list_all_params
> + *
> + * Attempt to list all CMOS parameters.  Return 1 if error was encountered.
> + * Else return OK.
> + ****************************************************************************/
> +static int list_all_params (void)
> + { const cmos_entry_t *e;
> +   int result;
> +
> +   result = OK;
> +
> +   for (e = first_cmos_entry(); e != NULL; e = next_cmos_entry(e))
> +    { if ((e->config == CMOS_ENTRY_RESERVED) || is_checksum_name(e->name))
> +         continue;
> +
> +      if (list_cmos_entry(e, TRUE))
> +         result = 1;
> +    }
> +
> +   return result;
> + }
> +
> +/****************************************************************************
> + * list_param_enums
> + *
> + * List all possible values for CMOS parameter given by 'name'.
> + ****************************************************************************/
> +static void list_param_enums (const char name[])
> + { const cmos_entry_t *e;
> +   const cmos_enum_t *p;
> +
> +   if (is_checksum_name(name) || (e = find_cmos_entry(name)) == NULL)
> +    { fprintf(stderr, "%s: CMOS parameter %s not found.\n", prog_name, name);
> +      exit(1);
> +    }
> +
> +   switch (e->config)
> +    { case CMOS_ENTRY_ENUM:
> +         for (p = first_cmos_enum_id(e->config_id);
> +              p != NULL;
> +              p = next_cmos_enum_id(p))
> +            printf("%s\n", p->text);
> +
> +         break;
> +
> +      case CMOS_ENTRY_HEX:
> +         printf("Parameter %s requires a %u-bit unsigned integer.\n", name,
> +                e->length);
> +         break;
> +
> +      case CMOS_ENTRY_RESERVED:
> +         printf("Parameter %s is reserved.\n", name);
> +         break;
> +
> +      default:
> +         BUG();
> +    }
> + }
> +
> +/****************************************************************************
> + * set_one_param
> + *
> + * Set the CMOS parameter given by 'name' to 'value'.  The 'name' parameter
> + * is case-sensitive.  If we are setting an enum parameter, then 'value' is
> + * interpreted as a case-sensitive string that must match the option name
> + * exactly.  If we are setting a 'hex' parameter, then 'value' is treated as
> + * a string representation of an unsigned integer that may be specified in
> + * decimal, hex, or octal.
> + ****************************************************************************/
> +static void set_one_param (const char name[], const char value[])
> + { const cmos_entry_t *e;
> +   unsigned long long n;
> +
> +   if (is_checksum_name(name) || (e = find_cmos_entry(name)) == NULL)
> +    { fprintf(stderr, "%s: CMOS parameter %s not found.", prog_name, name);
> +      exit(1);
> +    }
> +
> +   switch (prepare_cmos_write(e, value, &n))
> +    { case OK:
> +         break;
> +
> +      case CMOS_OP_BAD_ENUM_VALUE:
> +         fprintf(stderr, "%s: Bad value for parameter %s.", prog_name, name);
> +         goto fail;
> +
> +      case CMOS_OP_NEGATIVE_INT:
> +         fprintf(stderr,
> +                 "%s: This program does not support assignment of negative "
> +                 "numbers to LinuxBIOS parameters.", prog_name);
> +         goto fail;
> +
> +      case CMOS_OP_INVALID_INT:
> +         fprintf(stderr, "%s: %s is not a valid integer.", prog_name, value);
> +         goto fail;
> +
> +      case CMOS_OP_RESERVED:
> +         fprintf(stderr,
> +                 "%s: Can not modify reserved LinuxBIOS parameter %s.",
> +                 prog_name, name);
> +         goto fail;
> +
> +      case CMOS_OP_VALUE_TOO_WIDE:
> +         fprintf(stderr,
> +                 "%s: Can not write value %s to CMOS parameter %s that is "
> +                 "only %d bits wide.", prog_name, value, name, e->length);
> +         goto fail;
> +
> +      case CMOS_OP_NO_MATCHING_ENUM:
> +         fprintf(stderr,
> +                 "%s: LinuxBIOS parameter %s has no matching enums.",
> +                 prog_name, name);
> +         goto fail;
> +
> +      case CMOS_AREA_OUT_OF_RANGE:
> +         fprintf(stderr,
> +                 "%s: The CMOS area specified by the layout info for "
> +                 "LinuxBIOS parameter %s is out of range.", prog_name, name);
> +         goto fail;
> +
> +      case CMOS_AREA_OVERLAPS_RTC:
> +         fprintf(stderr,
> +                 "%s: The CMOS area specified by the layout info for "
> +                 "LinuxBIOS parameter %s overlaps the realtime clock area.",
> +                 prog_name, name);
> +         goto fail;
> +
> +      case CMOS_AREA_TOO_WIDE:
> +         fprintf(stderr,
> +                 "%s: The CMOS area specified by the layout info for "
> +                 "LinuxBIOS parameter %s is too wide.",
> +                 prog_name, name);
> +         goto fail;
> +
> +      default:
> +         fprintf(stderr,
> +                 "%s: Unknown error encountered while attempting to modify "
> +                 "LinuxBIOS parameter %s.", prog_name, name);
> +         goto fail;
> +    }
> +
> +   /* write the value to nonvolatile RAM */
> +   set_iopl(3);
> +   cmos_write(e->bit, e->length, n);
> +   cmos_checksum_write(cmos_checksum_compute());
> +   set_iopl(0);
> +   return;
> +
> +fail:
> +   fprintf(stderr, "  CMOS write not performed.\n");
> +   exit(1);
> + }
> +
> +/****************************************************************************
> + * set_params
> + *
> + * Set LinuxBIOS parameters according to the contents of file 'f'.
> + ****************************************************************************/
> +static void set_params (FILE *f)
> + { /* First process the input file.  Then perform writes only if there were
> +    * no problems processing the input.  Either all values will be written
> +    * successfully or no values will be written.
> +    */
> +   do_cmos_writes(process_input_file(f));
> + }
> +
> +/****************************************************************************
> + * parse_assignment
> + *
> + * Parse the string 'arg' (which supposedly represents an assignment) into a
> + * NAME and a VALUE.  If 'arg' does not conform to the proper assignment
> + * syntax, exit with a usage message.  Otherwise, on return, 'arg' is broken
> + * into substrings representing NAME and VALUE, and *name and *value are set
> + * to point to these two substrings.
> + ****************************************************************************/
> +static void parse_assignment (char arg[], const char **name,
> +                              const char **value)
> + { static const size_t N_MATCHES = 4;
> +   regmatch_t match[N_MATCHES];
> +   regex_t assignment;
> +
> +   compile_reg_exprs(REG_EXTENDED | REG_NEWLINE, 1, assignment_regex,
> +                     &assignment);
> +
> +   /* Does 'arg' conform to proper assignment syntax?  If not, exit with a
> +    * usage message.
> +    */
> +   if (regexec(&assignment, arg, N_MATCHES, match, 0))
> +      usage(stderr);
> +
> +   /* Ok, we found a valid assignment.  Break it into two strings
> +    * representing NAME and VALUE.
> +    */
> +   arg[match[1].rm_eo] = '\0';
> +   arg[match[2].rm_eo] = '\0';
> +   *name = &arg[match[1].rm_so];
> +   *value = &arg[match[2].rm_so];
> +
> +   free_reg_exprs(1, &assignment);
> + }
> +
> +/****************************************************************************
> + * list_cmos_entry
> + *
> + * Attempt to list the CMOS entry represented by 'e'.  'show_name' is a
> + * boolean value indicating whether the parameter name should be displayed
> + * along with its value.  On success, return OK.  On error, print an error
> + * message and return 1.
> + ****************************************************************************/
> +static int list_cmos_entry (const cmos_entry_t *e, int show_name)
> + { const cmos_enum_t *p;
> +   unsigned long long value;
> +
> +   /* sanity check CMOS entry */
> +   switch (prepare_cmos_read(e))
> +    { case OK:
> +         break;
> +
> +      case CMOS_OP_RESERVED:
> +         BUG();
> +
> +      case CMOS_AREA_OUT_OF_RANGE:
> +         fprintf(stderr, "%s: Can not read LinuxBIOS parameter %s because "
> +                 "layout info specifies out of range CMOS area.\n", prog_name,
> +                 e->name);
> +         return 1;
> +
> +      case CMOS_AREA_OVERLAPS_RTC:
> +         fprintf(stderr, "%s: Can not read LinuxBIOS parameter %s because "
> +                 "layout info specifies CMOS area that overlaps realtime "
> +                 "clock area.\n", prog_name, e->name);
> +         return 1;
> +
> +      case CMOS_AREA_TOO_WIDE:
> +         fprintf(stderr, "%s: Can not read LinuxBIOS parameter %s because "
> +                 "layout info specifies CMOS area that is too wide.\n",
> +                 prog_name, e->name);
> +         return 1;
> +
> +      default:
> +         fprintf(stderr, "%s: Unknown error encountered while attempting to "
> +                 "read LinuxBIOS parameter %s\n", prog_name, e->name);
> +         return 1;
> +    }
> +
> +   /* read the value from CMOS */
> +   set_iopl(3);
> +   value = cmos_read(e->bit, e->length);
> +   set_iopl(0);
> +
> +   /* display the value */
> +   switch (e->config)
> +    { case CMOS_ENTRY_ENUM:
> +         if ((p = find_cmos_enum(e->config_id, value)) == NULL)
> +          { if (show_name)
> +               printf("# Bad value -> %s = 0x%llx\n", e->name, value);
> +            else
> +               printf("Bad value -> 0x%llx\n", value);
> +          }
> +         else
> +          { if (show_name)
> +               printf("%s = %s\n", e->name, p->text);
> +            else
> +               printf("%s\n", p->text);
> +          }
> +
> +         break;
> +
> +      case CMOS_ENTRY_HEX:
> +         if (show_name)
> +            printf("%s = 0x%llx\n", e->name, value);
> +         else
> +            printf("0x%llx\n", value);
> +
> +         break;
> +
> +      case CMOS_ENTRY_RESERVED:
> +      default:
> +         BUG();
> +    }
> +
> +   return OK;
> + }
> +
> +/****************************************************************************
> + * convert_checksum_value
> + *
> + * 'value' is the string representation of a checksum value that the user
> + * wishes to set using the -c option.  Convert the string to a 16-bit
> + * unsigned integer and return the result.  Exit with an error message if
> + * 'value' is invalid.
> + ****************************************************************************/
> +static uint16_t convert_checksum_value (const char value[])
> + { unsigned long n;
> +   const char *p;
> +   uint16_t result;
> +   int negative;
> +
> +   for (p = value; isspace(*p); p++);
> +
> +   negative = (*p == '-');
> +   n = strtoul(value, (char **) &p, 0);
> +
> +   if (*p)
> +    { fprintf(stderr, "%s: Checksum value %s is not a valid integer.\n",
> +              prog_name, value);
> +      exit(1);
> +    }
> +
> +   if (negative)
> +    { fprintf(stderr,
> +              "%s: Checksum must be an unsigned integer.\n", prog_name);
> +      exit(1);
> +    }
> +
> +   result = (uint16_t) n;
> +
> +   if (result != n)
> +    { fprintf(stderr,
> +              "%s: Checksum value must fit within 16 bits.\n", prog_name);
> +      exit(1);
> +    }
> +
> +   return result;
> + }
> Index: lxbios/lbtable.c
> ===================================================================
> --- lxbios/lbtable.c	(revision 0)
> +++ lxbios/lbtable.c	(revision 0)
> @@ -0,0 +1,1270 @@
> +/*****************************************************************************\
> + * lbtable.c
> + * $Id: lbtable.c,v 1.3 2006/01/24 00:25:40 dsp_llnl Exp $
> + *****************************************************************************
> + *  Copyright (C) 2002-2005 The Regents of the University of California.
> + *  Produced at the Lawrence Livermore National Laboratory.
> + *  Written by Dave Peterson <dsp at llnl.gov> <dave_peterson at pobox.com>
> + *  and Stefan Reinauer <stepan at openbios.org>.
> + *  UCRL-CODE-2003-012
> + *  All rights reserved.
> + *
> + *  This file is part of lxbios, a utility for reading/writing LinuxBIOS
> + *  parameters and displaying information from the LinuxBIOS table.
> + *  For details, see <http://www.llnl.gov/linux/lxbios/>.
> + *
> + *  Please also read the file DISCLAIMER which is included in this software
> + *  distribution.
> + *
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License (as published by the
> + *  Free Software Foundation) version 2, dated June 1991.
> + *
> + *  This program is distributed in the hope that it will be useful, but
> + *  WITHOUT ANY WARRANTY; without even the IMPLIED WARRANTY OF
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the terms and
> + *  conditions of the GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, write to the Free Software Foundation, Inc.,
> + *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
> +\*****************************************************************************/
> +
> +#include <sys/mman.h>
> +#include "common.h"
> +#include "linuxbios_tables.h"
> +#include "ip_checksum.h"
> +#include "lbtable.h"
> +#include "layout.h"
> +#include "cmos_lowlevel.h"
> +#include "hexdump.h"
> +
> +typedef void (*lbtable_print_fn_t) (const struct lb_record *rec);
> +
> +/* This structure represents an item in the LinuxBIOS table that may be
> + * displayed using the -l option.
> + */
> +typedef struct
> + { uint32_t tag;
> +   const char *name;
> +   const char *description;
> +   const char *nofound_msg;
> +   lbtable_print_fn_t print_fn;
> + }
> +lbtable_choice_t;
> +
> +typedef struct
> + { unsigned long start;  /* address of first byte of memory range */
> +   unsigned long end;  /* address of last byte of memory range */
> + }
> +mem_range_t;
> +
> +static const struct lb_header * lbtable_scan (unsigned long start,
> +                                              unsigned long end,
> +                                              int *bad_header_count,
> +                                              int *bad_table_count);
> +static void process_cmos_table (void);
> +static void get_cmos_checksum_info (void);
> +static void try_convert_checksum_layout (cmos_checksum_layout_t *layout);
> +static void try_add_cmos_table_enum (cmos_enum_t *cmos_enum);
> +static void try_add_cmos_table_entry (cmos_entry_t *cmos_entry);
> +static const struct lb_record * find_lbrec (uint32_t tag);
> +static const char * lbrec_tag_to_str (uint32_t tag);
> +static const struct cmos_entries * first_cmos_table_entry (void);
> +static const struct cmos_entries *
> +      next_cmos_table_entry (const struct cmos_entries *last);
> +static const struct cmos_enums * first_cmos_table_enum (void);
> +static const struct cmos_enums * next_cmos_table_enum
> +      (const struct cmos_enums *last);
> +static const struct lb_record * first_cmos_rec (uint32_t tag);
> +static const struct lb_record * next_cmos_rec (const struct lb_record *last,
> +                                               uint32_t tag);
> +static void memory_print_fn (const struct lb_record *rec);
> +static void mainboard_print_fn (const struct lb_record *rec);
> +static void cmos_opt_table_print_fn (const struct lb_record *rec);
> +static void print_option_record (const struct cmos_entries *cmos_entry);
> +static void print_enum_record (const struct cmos_enums *cmos_enum);
> +static void print_defaults_record (const struct cmos_defaults *cmos_defaults);
> +static void print_unknown_record (const struct lb_record *cmos_item);
> +static void option_checksum_print_fn (const struct lb_record *rec);
> +static void string_print_fn (const struct lb_record *rec);
> +static void uint64_to_hex_string (char str[], uint64_t n);
> +
> +static const char memory_desc[] =
> +"    This shows information about system memory.\n";
> +
> +static const char mainboard_desc[] =
> +"    This shows information about your mainboard.\n";
> +
> +static const char version_desc[] =
> +"    This shows LinuxBIOS version information.\n";
> +
> +static const char extra_version_desc[] =
> +"    This shows extra LinuxBIOS version information.\n";
> +
> +static const char build_desc[] =
> +"    This shows LinuxBIOS build information.\n";
> +
> +static const char compile_time_desc[] =
> +"    This shows when LinuxBIOS was compiled.\n";
> +
> +static const char compile_by_desc[] =
> +"    This shows who compiled LinuxBIOS.\n";
> +
> +static const char compile_host_desc[] =
> +"    This shows the name of the machine that compiled LinuxBIOS.\n";
> +
> +static const char compile_domain_desc[] =
> +"    This shows the domain name of the machine that compiled LinuxBIOS.\n";
> +
> +static const char compiler_desc[] =
> +"    This shows the name of the compiler used to build LinuxBIOS.\n";
> +
> +static const char linker_desc[] =
> +"    This shows the name of the linker used to build LinuxBIOS.\n";
> +
> +static const char assembler_desc[] =
> +"    This shows the name of the assembler used to build LinuxBIOS.\n";
> +
> +static const char cmos_opt_table_desc[] =
> +"    This does a low-level dump of the CMOS option table.  The table "
> +"contains\n"
> +"    information about the layout of the values that LinuxBIOS stores in\n"
> +"    nonvolatile RAM.\n";
> +
> +static const char option_checksum_desc[] =
> +"    This shows the location of the CMOS checksum and the area over which it "
> +"is\n"
> +"    calculated.\n";
> +
> +static const char generic_nofound_msg[] =
> +"%s: Item %s not found in LinuxBIOS table.\n";
> +
> +static const char nofound_msg_cmos_opt_table[] =
> +"%s: Item %s not found in LinuxBIOS table.  Apparently, the "
> +"LinuxBIOS installed on this system was built without specifying "
> +"HAVE_OPTION_TABLE.\n";
> +
> +static const char nofound_msg_option_checksum[] =
> +"%s: Item %s not found in LinuxBIOS table. Apparently, you are "
> +"using LinuxBIOS v1.\n";
> +
> +/* This is the number of items from the LinuxBIOS table that may be displayed
> + * using the -l option.
> + */
> +#define NUM_LBTABLE_CHOICES 14
> +
> +/* These represent the various items from the LinuxBIOS table that may be
> + * displayed using the -l option.
> + */
> +static const lbtable_choice_t lbtable_choices[NUM_LBTABLE_CHOICES] =
> + { { LB_TAG_MEMORY,            "memory",
> +     memory_desc,              generic_nofound_msg,
> +     memory_print_fn
> +   },
> +   { LB_TAG_MAINBOARD,         "mainboard",
> +     mainboard_desc,           generic_nofound_msg,
> +     mainboard_print_fn
> +   },
> +   { LB_TAG_VERSION,           "version",
> +     version_desc,             generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_EXTRA_VERSION,     "extra_version",
> +     extra_version_desc,       generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_BUILD,             "build",
> +     build_desc,               generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_COMPILE_TIME,      "compile_time",
> +     compile_time_desc,        generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_COMPILE_BY,        "compile_by",
> +     compile_by_desc,          generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_COMPILE_HOST,      "compile_host",
> +     compile_host_desc,        generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_COMPILE_DOMAIN,    "compile_domain",
> +     compile_domain_desc,      generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_COMPILER,          "compiler",
> +     compiler_desc,            generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_LINKER,            "linker",
> +     linker_desc,              generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_ASSEMBLER,         "assembler",
> +     assembler_desc,           generic_nofound_msg,
> +     string_print_fn
> +   },
> +   { LB_TAG_CMOS_OPTION_TABLE, "cmos_opt_table",
> +     cmos_opt_table_desc,      nofound_msg_cmos_opt_table,
> +     cmos_opt_table_print_fn
> +   },
> +   { LB_TAG_OPTION_CHECKSUM, "option_checksum",
> +     option_checksum_desc,     nofound_msg_option_checksum,
> +     option_checksum_print_fn
> +   }
> + };
> +
> +/* The LinuxBIOS table resides in low physical memory, which we access using
> + * /dev/mem.  These are ranges of physical memory that should be scanned for a
> + * LinuxBIOS table.
> + */
> +
> +#define NUM_MEM_RANGES 2
> +
> +static const mem_range_t mem_ranges[NUM_MEM_RANGES] =
> + { { 0x00000000, 0x00000fff },
> +   { 0x000f0000, 0x000fffff }
> + };
> +
> +/* This is the number of bytes of physical memory to map, starting at physical
> + * address 0.  This value must be large enough to contain all memory ranges
> + * specified in mem_ranges above plus the maximum possible size of the
> + * LinuxBIOS table (since the start of the table could potentially occur at
> + * the end of the last memory range).
> + */
> +static const size_t BYTES_TO_MAP = (1024 * 1024);
> +
> +/* Pointer to low physical memory that we access by calling mmap() on
> + * /dev/mem.
> + */
> +static const void *low_phys_mem;
> +
> +/* Pointer to LinuxBIOS table. */
> +static const struct lb_header *lbtable = NULL;
> +
> +/* The CMOS option table is located within the LinuxBIOS table.  It tells us
> + * where the CMOS parameters are located in the nonvolatile RAM.
> + */
> +static const struct cmos_option_table *cmos_table = NULL;
> +
> +static const hexdump_format_t format =
> + { 12, 4, "            ", " | ", " ", " | ", '.', NULL };
> +
> +/****************************************************************************
> + * vtophys
> + *
> + * Convert a virtual address to a physical address.  'vaddr' is a virtual
> + * address in the address space of the current process.  It points to
> + * somewhere in the chunk of memory that we mapped by calling mmap() on
> + * /dev/mem.  This macro converts 'vaddr' to a physical address.
> + ****************************************************************************/
> +#define vtophys(vaddr) (((unsigned long) vaddr) -       \
> +                        ((unsigned long) low_phys_mem))
> +
> +/****************************************************************************
> + * phystov
> + *
> + * Convert a physical address to a virtual address.  'paddr' is a physical
> + * address.  This macro converts 'paddr' to a virtual address in the address
> + * space of the current process.  The virtual to physical mapping was set up
> + * by calling mmap() on /dev/mem.
> + ****************************************************************************/
> +#define phystov(paddr) (((unsigned long) low_phys_mem) + \
> +                        ((unsigned long) paddr))
> +
> +/****************************************************************************
> + * get_lbtable
> + *
> + * Find the LinuxBIOS table and set global variable lbtable to point to it.
> + ****************************************************************************/
> +void get_lbtable (void)
> + { int fd, i, bad_header_count, bad_table_count, bad_headers, bad_tables;
> +
> +   if (lbtable != NULL)
> +      return;
> +
> +   /* The LinuxBIOS table is located in low physical memory, which may be
> +    * conveniently accessed by calling mmap() on /dev/mem.
> +    */
> +
> +   if ((fd = open("/dev/mem", O_RDONLY, 0)) < 0)
> +    { fprintf(stderr, "%s: Can not open /dev/mem for reading: %s\n",
> +              prog_name, strerror(errno));
> +      exit(1);
> +    }
> +
> +   if ((low_phys_mem = mmap(NULL, BYTES_TO_MAP, PROT_READ, MAP_SHARED, fd, 0))
> +       == MAP_FAILED)
> +    { fprintf(stderr, "%s: Failed to mmap /dev/mem: %s\n", prog_name,
> +              strerror(errno));
> +      exit(1);
> +    }
> +
> +   bad_header_count = 0;
> +   bad_table_count = 0;
> +
> +   for (i = 0; i < NUM_MEM_RANGES; i++)
> +    { lbtable = lbtable_scan(phystov(mem_ranges[i].start),
> +                             phystov(mem_ranges[i].end),
> +                             &bad_headers, &bad_tables);
> +
> +      if (lbtable != NULL)
> +         return; /* success: we found it! */
> +
> +      bad_header_count += bad_headers;
> +      bad_table_count += bad_tables;
> +    }
> +
> +   fprintf(stderr,
> +           "%s: LinuxBIOS table not found.  LinuxBIOS does not appear to\n"
> +           "        be installed on this system.  Scanning for the table "
> +           "produced the\n"
> +           "        following results:\n\n"
> +           "            %d valid signatures were found with bad header "
> +           "checksums.\n"
> +           "            %d valid headers were found with bad table "
> +           "checksums.\n",
> +           prog_name, bad_header_count, bad_table_count);
> +   exit(1);
> + }
> +
> +/****************************************************************************
> + * get_layout_from_cmos_table
> + *
> + * Find the CMOS table which is stored within the LinuxBIOS table and set the
> + * global variable cmos_table to point to it.
> + ****************************************************************************/
> +void get_layout_from_cmos_table (void)
> + {
> +
> +   get_lbtable();
> +   cmos_table = (const struct cmos_option_table *)
> +                find_lbrec(LB_TAG_CMOS_OPTION_TABLE);
> +
> +   if ((cmos_table) == NULL)
> +    { fprintf(stderr,
> +              "%s: CMOS option table not found in LinuxBIOS table.  "
> +              "Apparently, the LinuxBIOS installed on this system was "
> +              "built without specifying HAVE_OPTION_TABLE.\n",
> +              prog_name);
> +      exit(1);
> +    }
> +
> +   process_cmos_table();
> +   get_cmos_checksum_info();
> + }
> +
> +/****************************************************************************
> + * dump_lbtable
> + *
> + * Do a low-level dump of the LinuxBIOS table.
> + ****************************************************************************/
> +void dump_lbtable (void)
> + { const char *p, *data;
> +   uint32_t bytes_processed;
> +   const struct lb_record *lbrec;
> +
> +   p = ((const char *) lbtable) + lbtable->header_bytes;
> +   printf("LinuxBIOS table at physical address 0x%lx:\n"
> +          "    signature:       0x%x (ASCII: %c%c%c%c)\n"
> +          "    header_bytes:    0x%x (decimal: %d)\n"
> +          "    header_checksum: 0x%x (decimal: %d)\n"
> +          "    table_bytes:     0x%x (decimal: %d)\n"
> +          "    table_checksum:  0x%x (decimal: %d)\n"
> +          "    table_entries:   0x%x (decimal: %d)\n\n",
> +          vtophys(lbtable), *((uint32_t *) lbtable->signature),
> +          lbtable->signature[0], lbtable->signature[1],lbtable->signature[2],
> +          lbtable->signature[3], lbtable->header_bytes, lbtable->header_bytes,
> +          lbtable->header_checksum, lbtable->header_checksum,
> +          lbtable->table_bytes, lbtable->table_bytes, lbtable->table_checksum,
> +          lbtable->table_checksum, lbtable->table_entries,
> +          lbtable->table_entries);
> +
> +   if ((lbtable->table_bytes == 0) != (lbtable->table_entries == 0))
> +    { printf("Inconsistent values for table_bytes and table_entries!!!\n"
> +             "They should be either both 0 or both nonzero.\n");
> +      return;
> +    }
> +
> +   if (lbtable->table_bytes == 0)
> +    { printf("The LinuxBIOS table is empty!!!\n");
> +      return;
> +    }
> +
> +   for (bytes_processed = 0; ; )
> +    { lbrec = (const struct lb_record *) &p[bytes_processed];
> +      printf("    %s record at physical address 0x%lx:\n"
> +             "        tag:  0x%x (decimal: %d)\n"
> +             "        size: 0x%x (decimal: %d)\n"
> +             "        data:\n",
> +             lbrec_tag_to_str(lbrec->tag), vtophys(lbrec), lbrec->tag,
> +             lbrec->tag, lbrec->size, lbrec->size);
> +
> +      data = ((const char *) lbrec) + sizeof(*lbrec);
> +      hexdump(data, lbrec->size - sizeof(*lbrec), vtophys(data), stdout,
> +              &format);
> +
> +      bytes_processed += lbrec->size;
> +
> +      if (bytes_processed >= lbtable->table_bytes)
> +         break;
> +
> +      printf("\n");
> +    }
> + }
> +
> +/****************************************************************************
> + * list_lbtable_choices
> + *
> + * List names and informational blurbs for items from the LinuxBIOS table
> + * that may be displayed using the -l option.
> + ****************************************************************************/
> +void list_lbtable_choices (void)
> + { int i;
> +
> +   for (i = 0; ; )
> +    { printf("%s:\n%s",
> +             lbtable_choices[i].name, lbtable_choices[i].description);
> +
> +      if (++i >= NUM_LBTABLE_CHOICES)
> +         break;
> +
> +      printf("\n");
> +    }
> + }
> +
> +/****************************************************************************
> + * list_lbtable_item
> + *
> + * Show the LinuxBIOS table item specified by 'item'.
> + ****************************************************************************/
> +void list_lbtable_item (const char item[])
> + { int i;
> +   const struct lb_record *rec;
> +
> +   for (i = 0; i < NUM_LBTABLE_CHOICES; i++)
> +    { if (strcmp(item, lbtable_choices[i].name) == 0)
> +         break;
> +    }
> +
> +   if (i == NUM_LBTABLE_CHOICES)
> +    { fprintf(stderr, "%s: Invalid LinuxBIOS table item %s.\n", prog_name,
> +              item);
> +      exit(1);
> +    }
> +
> +   if ((rec = find_lbrec(lbtable_choices[i].tag)) == NULL)
> +    { fprintf(stderr, lbtable_choices[i].nofound_msg, prog_name,
> +              lbtable_choices[i].name);
> +      exit(1);
> +    }
> +
> +   lbtable_choices[i].print_fn(rec);
> + }
> +
> +/****************************************************************************
> + * lbtable_scan
> + *
> + * Scan the chunk of memory specified by 'start' and 'end' for a LinuxBIOS
> + * table.  The first 4 bytes of the table are marked by the signature
> + * { 'L', 'B', 'I', 'O' }.  'start' and 'end' indicate the addresses of the
> + * first and last bytes of the chunk of memory to be scanned.  For instance,
> + * values of 0x10000000 and 0x1000ffff for 'start' and 'end' specify a 64k
> + * chunk of memory starting at address 0x10000000.  'start' and 'end' are
> + * virtual addresses in the address space of the current process.  They
> + * represent a chunk of memory obtained by calling mmap() on /dev/mem.
> + *
> + * If a LinuxBIOS table is found, return a pointer to it.  Otherwise return
> + * NULL.  On return, *bad_header_count and *bad_table_count are set as
> + * follows:
> + *
> + *     *bad_header_count:
> + *         Indicates the number of times in which a valid signature was found
> + *         but the header checksum was invalid.
> + *
> + *     *bad_table_count:
> + *         Indicates the number of times in which a header with a valid
> + *         checksum was found but the table checksum was invalid.
> + ****************************************************************************/
> +static const struct lb_header * lbtable_scan (unsigned long start,
> +                                              unsigned long end,
> +                                              int *bad_header_count,
> +                                              int *bad_table_count)
> + { static const char signature[] = { 'L', 'B', 'I', 'O' };
> +   const struct lb_header *table;
> +   const uint32_t *p;
> +   uint32_t sig;
> +
> +   assert(end >= start);
> +   sig = (*((const uint32_t *) signature));
> +   table = NULL;
> +   *bad_header_count = 0;
> +   *bad_table_count = 0;
> +
> +   /* Look for signature.  Table is aligned on 16-byte boundary.  Therefore
> +    * only check every fourth 32-bit memory word.  As the loop is coded below,
> +    * this function will behave in a reasonable manner for ALL possible values
> +    * for 'start' and 'end': even weird boundary cases like 0x00000000 and
> +    * 0xffffffff on a 32-bit architecture.
> +    */
> +   for (p = (const uint32_t *) start;
> +        (((unsigned long) p) <= end) &&
> +        ((end - (unsigned long) p) >= (sizeof(uint32_t) - 1));
> +        p += 4)
> +    { if (*p != sig)
> +         continue;
> +
> +      /* We found a valid signature. */
> +      table = (const struct lb_header *) p;
> +
> +      /* validate header checksum */
> +      if (compute_ip_checksum((void *) table, sizeof(*table)))
> +       { (*bad_header_count)++;
> +         continue;
> +       }
> +
> +      /* validate table checksum */
> +      if (table->table_checksum !=
> +          compute_ip_checksum(((char *) table) + sizeof(*table),
> +                              table->table_bytes))
> +       { (*bad_table_count)++;
> +         continue;
> +       }
> +
> +      /* checksums are ok: we found it! */
> +      return table;
> +    }
> +
> +   return NULL;
> + }
> +
> +/****************************************************************************
> + * process_cmos_table
> + *
> + * Extract layout information from the CMOS option table and store it in our
> + * internal repository.
> + ****************************************************************************/
> +static void process_cmos_table (void)
> + { const struct cmos_enums *p;
> +   const struct cmos_entries *q;
> +   cmos_enum_t cmos_enum;
> +   cmos_entry_t cmos_entry;
> +
> +   /* First add the enums. */
> +   for (p = first_cmos_table_enum(); p != NULL; p = next_cmos_table_enum(p))
> +    { cmos_enum.config_id = p->config_id;
> +      cmos_enum.value = p->value;
> +      strncpy(cmos_enum.text, p->text, CMOS_MAX_TEXT_LENGTH);
> +      cmos_enum.text[CMOS_MAX_TEXT_LENGTH] = '\0';
> +      try_add_cmos_table_enum(&cmos_enum);
> +    }
> +
> +   /* Now add the entries.  We must add the entries after the enums because
> +    * the entries are sanity checked against the enums as they are added.
> +    */
> +   for (q = first_cmos_table_entry(); q != NULL; q = next_cmos_table_entry(q))
> +    { cmos_entry.bit = q->bit;
> +      cmos_entry.length = q->length;
> +
> +      switch (q->config)
> +       { case 'e':
> +            cmos_entry.config = CMOS_ENTRY_ENUM;
> +            break;
> +
> +         case 'h':
> +            cmos_entry.config = CMOS_ENTRY_HEX;
> +            break;
> +
> +         case 'r':
> +            cmos_entry.config = CMOS_ENTRY_RESERVED;
> +            break;
> +
> +         default:
> +            fprintf(stderr,
> +                    "%s: Entry in CMOS option table has unknown config "
> +                    "value.\n", prog_name);
> +            exit(1);
> +       }
> +
> +      cmos_entry.config_id = q->config_id;
> +      strncpy(cmos_entry.name, q->name, CMOS_MAX_NAME_LENGTH);
> +      cmos_entry.name[CMOS_MAX_NAME_LENGTH] = '\0';
> +      try_add_cmos_table_entry(&cmos_entry);
> +    }
> + }
> +
> +/****************************************************************************
> + * get_cmos_checksum_info
> + *
> + * Get layout information for CMOS checksum.
> + ****************************************************************************/
> +static void get_cmos_checksum_info (void)
> + { const cmos_entry_t *e;
> +   struct cmos_checksum *checksum;
> +   cmos_checksum_layout_t layout;
> +   unsigned index, index2;
> +
> +   checksum = (struct cmos_checksum *) find_lbrec(LB_TAG_OPTION_CHECKSUM);
> +
> +   if (checksum != NULL)
> +    { /* We are lucky.  The LinuxBIOS table hints us to the checksum.
> +       * We might have to check the type field here though.
> +       */
> +      layout.summed_area_start = checksum->range_start;
> +      layout.summed_area_end = checksum->range_end;
> +      layout.checksum_at = checksum->location;
> +      try_convert_checksum_layout(&layout);
> +      cmos_checksum_start = layout.summed_area_start;
> +      cmos_checksum_end = layout.summed_area_end;
> +      cmos_checksum_index = layout.checksum_at;
> +      return;
> +    }
> +
> +   if ((e = find_cmos_entry(checksum_param_name)) == NULL)
> +      return;
> +
> +   /* If we get here, we are unlucky.  The CMOS option table contains the
> +    * location of the CMOS checksum.  However, there is no information
> +    * regarding which bytes of the CMOS area the checksum is computed over.
> +    * Thus we have to hope our presets will be fine.
> +    */
> +
> +   if (e->bit % 8)
> +    { fprintf(stderr, "%s: Error: CMOS checksum is not byte-aligned.\n",
> +              prog_name);
> +      exit(1);
> +    }
> +
> +   index = e->bit / 8;
> +   index2 = index + 1;  /* The CMOS checksum occupies 16 bits. */
> +
> +   if (verify_cmos_byte_index(index) || verify_cmos_byte_index(index2))
> +    { fprintf(stderr, "%s: Error: CMOS checksum location out of range.\n",
> +              prog_name);
> +      exit(1);
> +    }
> +
> +   if (((index >= cmos_checksum_start) && (index <= cmos_checksum_end)) ||
> +       (((index2) >= cmos_checksum_start) && ((index2) <= cmos_checksum_end)))
> +    { fprintf(stderr, "%s: Error: CMOS checksum overlaps checksummed area.\n",
> +              prog_name);
> +      exit(1);
> +    }
> +
> +   cmos_checksum_index = index;
> + }
> +
> +/****************************************************************************
> + * try_convert_checksum_layout
> + *
> + * Perform sanity checking on CMOS checksum layout information and attempt to
> + * convert information from bit positions to byte positions.  Return OK on
> + * success or an error code on failure.
> + ****************************************************************************/
> +static void try_convert_checksum_layout (cmos_checksum_layout_t *layout)
> + { switch (checksum_layout_to_bytes(layout))
> +    { case OK:
> +         return;
> +
> +      case LAYOUT_SUMMED_AREA_START_NOT_ALIGNED:
> +         fprintf(stderr,
> +                 "%s: CMOS checksummed area start is not byte-aligned.\n",
> +                 prog_name);
> +         break;
> +
> +      case LAYOUT_SUMMED_AREA_END_NOT_ALIGNED:
> +         fprintf(stderr,
> +                 "%s: CMOS checksummed area end is not byte-aligned.\n",
> +                 prog_name);
> +         break;
> +
> +      case LAYOUT_CHECKSUM_LOCATION_NOT_ALIGNED:
> +         fprintf(stderr,
> +                 "%s: CMOS checksum location is not byte-aligned.\n",
> +                 prog_name);
> +         break;
> +
> +      case LAYOUT_INVALID_SUMMED_AREA:
> +         fprintf(stderr,
> +                 "%s: CMOS checksummed area end must be greater than "
> +                 "CMOS checksummed area start.\n",
> +                 prog_name);
> +         break;
> +
> +      case LAYOUT_CHECKSUM_OVERLAPS_SUMMED_AREA:
> +         fprintf(stderr,
> +                 "%s: CMOS checksum overlaps checksummed area.\n",
> +                 prog_name);
> +         break;
> +
> +      case LAYOUT_SUMMED_AREA_OUT_OF_RANGE:
> +         fprintf(stderr,
> +                 "%s: CMOS checksummed area out of range.\n",
> +                 prog_name);
> +         break;
> +
> +      case LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE:
> +         fprintf(stderr,
> +                 "%s: CMOS checksum location out of range.\n",
> +                 prog_name);
> +         break;
> +
> +      default:
> +         BUG();
> +    }
> +
> +   exit(1);
> + }
> +
> +/****************************************************************************
> + * try_add_cmos_table_enum
> + *
> + * Attempt to add a CMOS enum to our internal repository.  Exit with an error
> + * message on failure.
> + ****************************************************************************/
> +static void try_add_cmos_table_enum (cmos_enum_t *cmos_enum)
> + { switch (add_cmos_enum(cmos_enum))
> +    { case OK:
> +         return;
> +
> +      case LAYOUT_DUPLICATE_ENUM:
> +         fprintf(stderr, "%s: Duplicate enum %s found in CMOS option "
> +                 "table.\n", prog_name, cmos_enum->text);
> +         break;
> +
> +      default:
> +         BUG();
> +    }
> +
> +   exit(1);
> + }
> +
> +/****************************************************************************
> + * try_add_cmos_table_entry
> + *
> + * Attempt to add a CMOS entry to our internal repository.  Exit with an
> + * error message on failure.
> + ****************************************************************************/
> +static void try_add_cmos_table_entry (cmos_entry_t *cmos_entry)
> + { const cmos_entry_t *conflict;
> +
> +   switch (add_cmos_entry(cmos_entry, &conflict))
> +    { case OK:
> +         return;
> +
> +      case CMOS_AREA_OUT_OF_RANGE:
> +         fprintf(stderr,
> +                 "%s: Bad CMOS option layout in CMOS option table entry "
> +                 "%s.\n", prog_name, cmos_entry->name);
> +         break;
> +
> +      case CMOS_AREA_TOO_WIDE:
> +         fprintf(stderr,
> +                 "%s: Area too wide for CMOS option table entry %s.\n",
> +                 prog_name, cmos_entry->name);
> +         break;
> +
> +      case LAYOUT_ENTRY_OVERLAP:
> +         fprintf(stderr,
> +                 "%s: CMOS option table entries %s and %s have overlapping "
> +                 "layouts.\n", prog_name, cmos_entry->name, conflict->name);
> +         break;
> +
> +      case LAYOUT_ENTRY_BAD_LENGTH:
> +         /* Silently ignore entries with zero length.  Although this should
> +          * never happen in practice, we should handle the case in a
> +          * reasonable manner just to be safe.
> +          */
> +         return;
> +
> +      default:
> +         BUG();
> +    }
> +
> +   exit(1);
> + }
> +
> +/****************************************************************************
> + * find_lbrec
> + *
> + * Find the record in the LinuxBIOS table that matches 'tag'.  Return pointer
> + * to record on success or NULL if record not found.
> + ****************************************************************************/
> +static const struct lb_record * find_lbrec (uint32_t tag)
> + { const char *p;
> +   uint32_t bytes_processed;
> +   const struct lb_record *lbrec;
> +
> +   p = ((const char *) lbtable) + lbtable->header_bytes;
> +
> +   for (bytes_processed = 0;
> +        bytes_processed < lbtable->table_bytes;
> +        bytes_processed += lbrec->size)
> +    { lbrec = (const struct lb_record *) &p[bytes_processed];
> +
> +      if (lbrec->tag == tag)
> +         return lbrec;
> +    }
> +
> +   return NULL;
> + }
> +
> +/****************************************************************************
> + * lbrec_tag_to_str
> + *
> + * Return a pointer to the string representation of the given LinuxBIOS table
> + * tag.
> + ****************************************************************************/
> +static const char * lbrec_tag_to_str (uint32_t tag)
> + { switch (tag)
> +    { case LB_TAG_UNUSED:
> +         return "UNUSED";
> +
> +      case LB_TAG_MEMORY:
> +         return "MEMORY";
> +
> +      case LB_TAG_HWRPB:
> +         return "HWRPB";
> +
> +      case LB_TAG_MAINBOARD:
> +         return "MAINBOARD";
> +
> +      case LB_TAG_VERSION:
> +         return "VERSION";
> +
> +      case LB_TAG_EXTRA_VERSION:
> +         return "EXTRA_VERSION";
> +
> +      case LB_TAG_BUILD:
> +         return "BUILD";
> +
> +      case LB_TAG_COMPILE_TIME:
> +         return "COMPILE_TIME";
> +
> +      case LB_TAG_COMPILE_BY:
> +         return "COMPILE_BY";
> +
> +      case LB_TAG_COMPILE_HOST:
> +         return "COMPILE_HOST";
> +
> +      case LB_TAG_COMPILE_DOMAIN:
> +         return "COMPILE_DOMAIN";
> +
> +      case LB_TAG_COMPILER:
> +         return "COMPILER";
> +
> +      case LB_TAG_LINKER:
> +         return "LINKER";
> +
> +      case LB_TAG_ASSEMBLER:
> +         return "ASSEMBLER";
> +
> +      case LB_TAG_CMOS_OPTION_TABLE:
> +         return "CMOS_OPTION_TABLE";
> +
> +      case LB_TAG_OPTION_CHECKSUM:
> +         return "OPTION_CHECKSUM";
> +
> +      default:
> +         break;
> +    }
> +
> +   return "UNKNOWN";
> + }
> +
> +/****************************************************************************
> + * first_cmos_table_entry
> + *
> + * Return a pointer to the first entry in the CMOS table that represents a
> + * CMOS parameter.  Return NULL if CMOS table is empty.
> + ****************************************************************************/
> +static const struct cmos_entries * first_cmos_table_entry (void)
> + { return (const struct cmos_entries *) first_cmos_rec(LB_TAG_OPTION); }
> +
> +/****************************************************************************
> + * next_cmos_table_entry
> + *
> + * Return a pointer to the next entry after 'last' in the CMOS table that
> + * represents a CMOS parameter.  Return NULL if there are no more parameters.
> + ****************************************************************************/
> +static const struct cmos_entries *
> +      next_cmos_table_entry (const struct cmos_entries *last)
> + { return (const struct cmos_entries *)
> +          next_cmos_rec((const struct lb_record *) last, LB_TAG_OPTION);
> + }
> +
> +/****************************************************************************
> + * first_cmos_table_enum
> + *
> + * Return a pointer to the first entry in the CMOS table that represents a
> + * possible CMOS parameter value.  Return NULL if the table does not contain
> + * any such entries.
> + ****************************************************************************/
> +static const struct cmos_enums * first_cmos_table_enum (void)
> + { return (const struct cmos_enums *) first_cmos_rec(LB_TAG_OPTION_ENUM); }
> +
> +/****************************************************************************
> + * next_cmos_table_enum
> + *
> + * Return a pointer to the next entry after 'last' in the CMOS table that
> + * represents a possible CMOS parameter value.  Return NULL if there are no
> + * more parameter values.
> + ****************************************************************************/
> +static const struct cmos_enums * next_cmos_table_enum
> +      (const struct cmos_enums *last)
> + { return (const struct cmos_enums *)
> +          next_cmos_rec((const struct lb_record *) last, LB_TAG_OPTION_ENUM);
> + }
> +
> +/****************************************************************************
> + * first_cmos_rec
> + *
> + * Return a pointer to the first entry in the CMOS table whose type matches
> + * 'tag'.  Return NULL if CMOS table contains no such entry.
> + *
> + * Possible values for 'tag' are as follows:
> + *
> + *     LB_TAG_OPTION:      The entry represents a CMOS parameter.
> + *     LB_TAG_OPTION_ENUM: The entry represents a possible value for a CMOS
> + *                         parameter of type 'enum'.
> + *
> + * The CMOS table tells us where in the nonvolatile RAM to look for CMOS
> + * parameter values and specifies their types as 'enum', 'hex', or
> + * 'reserved'.
> + ****************************************************************************/
> +static const struct lb_record * first_cmos_rec (uint32_t tag)
> + { const char             *p;
> +   uint32_t               bytes_processed, bytes_for_entries;
> +   const struct lb_record *lbrec;
> +
> +   p = ((const char *) cmos_table) + cmos_table->header_length;
> +   bytes_for_entries = cmos_table->size - cmos_table->header_length;
> +
> +   for (bytes_processed = 0;
> +        bytes_processed < bytes_for_entries;
> +        bytes_processed += lbrec->size)
> +    { lbrec = (const struct lb_record *) &p[bytes_processed];
> +
> +      if (lbrec->tag == tag)
> +         return lbrec;
> +    }
> +
> +   return NULL;
> + }
> +
> +/****************************************************************************
> + * next_cmos_rec
> + *
> + * Return a pointer to the next entry after 'last' in the CMOS table whose
> + * type matches 'tag'.  Return NULL if the table contains no more entries of
> + * this type.
> + ****************************************************************************/
> +static const struct lb_record * next_cmos_rec (const struct lb_record *last,
> +                                               uint32_t tag)
> + { const char *p;
> +   uint32_t bytes_processed, bytes_for_entries, last_offset;
> +   const struct lb_record *lbrec;
> +
> +   p = ((const char *) cmos_table) + cmos_table->header_length;
> +   bytes_for_entries = cmos_table->size - cmos_table->header_length;
> +   last_offset = ((const char *) last) - p;
> +
> +   for (bytes_processed = last_offset + last->size;
> +        bytes_processed < bytes_for_entries;
> +        bytes_processed += lbrec->size)
> +    { lbrec = (const struct lb_record *) &p[bytes_processed];
> +
> +      if (lbrec->tag == tag)
> +         return lbrec;
> +    }
> +
> +   return NULL;
> + }
> +
> +/****************************************************************************
> + * memory_print_fn
> + *
> + * Display function for 'memory' item of LinuxBIOS table.
> + ****************************************************************************/
> +static void memory_print_fn (const struct lb_record *rec)
> + { char start_str[19], end_str[19], size_str[19];
> +   const struct lb_memory *p;
> +   const char *mem_type;
> +   const struct lb_memory_range *ranges;
> +   uint64_t size, start, end;
> +   int i, entries;
> +
> +   p = (const struct lb_memory *) rec;
> +   entries = (p->size -  sizeof(*p)) / sizeof(p->map[0]);
> +   ranges = p->map;
> +
> +   if (entries == 0)
> +    { printf("No memory ranges were found.\n");
> +      return;
> +    }
> +
> +   for (i = 0; ; )
> +    { switch (ranges[i].type)
> +       { case LB_MEM_RAM:
> +            mem_type = "AVAILABLE";
> +            break;
> +
> +         case LB_MEM_RESERVED:
> +            mem_type = "RESERVED";
> +            break;
> +
> +         case LB_MEM_TABLE:
> +            mem_type = "CONFIG_TABLE";
> +            break;
> +
> +         default:
> +            mem_type = "UNKNOWN";
> +            break;
> +       }
> +
> +      size = unpack_lb64(ranges[i].size);
> +      start = unpack_lb64(ranges[i].start);
> +      end  = start + size - 1;
> +      uint64_to_hex_string(start_str, start);
> +      uint64_to_hex_string(end_str, end);
> +      uint64_to_hex_string(size_str, size);
> +      printf("%s memory:\n"
> +             "    from physical addresses %s to %s\n"
> +             "    size is %s bytes (%lld in decimal)\n",
> +             mem_type, start_str, end_str, size_str,
> +             (unsigned long long) size);
> +
> +      if (++i >= entries)
> +         break;
> +
> +      printf("\n");
> +    }
> + }
> +
> +/****************************************************************************
> + * mainboard_print_fn
> + *
> + * Display function for 'mainboard' item of LinuxBIOS table.
> + ****************************************************************************/
> +static void mainboard_print_fn (const struct lb_record *rec)
> + { const struct lb_mainboard *p;
> +
> +   p = (const struct lb_mainboard *) rec;
> +   printf("Vendor:      %s\n"
> +          "Part number: %s\n",
> +          &p->strings[p->vendor_idx],
> +          &p->strings[p->part_number_idx]);
> + }
> +
> +/****************************************************************************
> + * cmos_opt_table_print_fn
> + *
> + * Display function for 'cmos_opt_table' item of LinuxBIOS table.
> + ****************************************************************************/
> +static void cmos_opt_table_print_fn (const struct lb_record *rec)
> + {
> +   const struct cmos_option_table *p;
> +   const struct lb_record *cmos_item;
> +   uint32_t bytes_processed, bytes_for_entries;
> +   const char *q;
> +
> +   p = (const struct cmos_option_table *) rec;
> +   q = ((const char *) p) + p->header_length;
> +   bytes_for_entries = p->size - p->header_length;
> +
> +   printf("CMOS option table at physical address 0x%lx:\n"
> +          "    tag:           0x%x (decimal: %d)\n"
> +          "    size:          0x%x (decimal: %d)\n"
> +          "    header_length: 0x%x (decimal: %d)\n\n",
> +          vtophys(p), p->tag, p->tag, p->size, p->size, p->header_length,
> +          p->header_length);
> +
> +   if (p->header_length > p->size)
> +    { printf("Header length for CMOS option table is greater than the size "
> +             "of the entire table including header!!!\n");
> +      return;
> +    }
> +
> +   if (bytes_for_entries == 0)
> +    { printf("The CMOS option table is empty!!!\n");
> +      return;
> +    }
> +
> +   for (bytes_processed = 0; ; )
> +    { cmos_item = (const struct lb_record *) &q[bytes_processed];
> +
> +      switch (cmos_item->tag)
> +       { case LB_TAG_OPTION:
> +            print_option_record((const struct cmos_entries *) cmos_item);
> +            break;
> +
> +         case LB_TAG_OPTION_ENUM:
> +            print_enum_record((const struct cmos_enums *) cmos_item);
> +            break;
> +
> +         case LB_TAG_OPTION_DEFAULTS:
> +            print_defaults_record((const struct cmos_defaults *) cmos_item);
> +            break;
> +
> +         default:
> +            print_unknown_record(cmos_item);
> +            break;
> +       }
> +
> +      bytes_processed += cmos_item->size;
> +
> +      if (bytes_processed >= bytes_for_entries)
> +         break;
> +
> +      printf("\n");
> +    }
> + }
> +
> +/****************************************************************************
> + * print_option_record
> + *
> + * Display "option" record from CMOS option table.
> + ****************************************************************************/
> +static void print_option_record (const struct cmos_entries *cmos_entry)
> + { static const size_t S_BUFSIZE = 80;
> +   char s[S_BUFSIZE];
> +
> +   switch (cmos_entry->config)
> +    { case 'e':
> +         strcpy(s, "ENUM");
> +         break;
> +
> +      case 'h':
> +         strcpy(s, "HEX");
> +         break;
> +
> +      case 'r':
> +         strcpy(s, "RESERVED");
> +         break;
> +
> +      default:
> +         snprintf(s, S_BUFSIZE, "UNKNOWN: value is 0x%x (decimal: %d)",
> +                  cmos_entry->config, cmos_entry->config);
> +         break;
> +    }
> +
> +   printf("    OPTION record at physical address 0x%lx:\n"
> +          "        tag:       0x%x (decimal: %d)\n"
> +          "        size:      0x%x (decimal: %d)\n"
> +          "        bit:       0x%x (decimal: %d)\n"
> +          "        length:    0x%x (decimal: %d)\n"
> +          "        config:    %s\n"
> +          "        config_id: 0x%x (decimal: %d)\n"
> +          "        name:      %s\n",
> +          vtophys(cmos_entry), cmos_entry->tag, cmos_entry->tag,
> +          cmos_entry->size, cmos_entry->size, cmos_entry->bit,
> +          cmos_entry->bit, cmos_entry->length, cmos_entry->length, s,
> +          cmos_entry->config_id, cmos_entry->config_id, cmos_entry->name);
> + }
> +
> +/****************************************************************************
> + * print_enum_record
> + *
> + * Display "enum" record from CMOS option table.
> + ****************************************************************************/
> +static void print_enum_record (const struct cmos_enums *cmos_enum)
> + { printf("    ENUM record at physical address 0x%lx:\n"
> +          "        tag:       0x%x (decimal: %d)\n"
> +          "        size:      0x%x (decimal: %d)\n"
> +          "        config_id: 0x%x (decimal: %d)\n"
> +          "        value:     0x%x (decimal: %d)\n"
> +          "        text:      %s\n",
> +          vtophys(cmos_enum), cmos_enum->tag, cmos_enum->tag, cmos_enum->size,
> +          cmos_enum->size, cmos_enum->config_id, cmos_enum->config_id,
> +          cmos_enum->value, cmos_enum->value, cmos_enum->text);
> + }
> +
> +/****************************************************************************
> + * print_defaults_record
> + *
> + * Display "defaults" record from CMOS option table.
> + ****************************************************************************/
> +static void print_defaults_record (const struct cmos_defaults *cmos_defaults)
> + { printf("    DEFAULTS record at physical address 0x%lx:\n"
> +          "        tag:         0x%x (decimal: %d)\n"
> +          "        size:        0x%x (decimal: %d)\n"
> +          "        name_length: 0x%x (decimal: %d)\n"
> +          "        name:        %s\n"
> +          "        default_set:\n",
> +          vtophys(cmos_defaults), cmos_defaults->tag, cmos_defaults->tag,
> +          cmos_defaults->size, cmos_defaults->size,
> +          cmos_defaults->name_length, cmos_defaults->name_length,
> +          cmos_defaults->name);
> +   hexdump(cmos_defaults->default_set, CMOS_IMAGE_BUFFER_SIZE,
> +           vtophys(cmos_defaults->default_set), stdout, &format);
> + }
> +
> +/****************************************************************************
> + * print_unknown_record
> + *
> + * Display record of unknown type from CMOS option table.
> + ****************************************************************************/
> +static void print_unknown_record (const struct lb_record *cmos_item)
> + { const char *data;
> +
> +   printf("    UNKNOWN record at physical address 0x%lx:\n"
> +          "        tag:  0x%x (decimal: %d)\n"
> +          "        size: 0x%x (decimal: %d)\n"
> +          "        data:\n",
> +          vtophys(cmos_item), cmos_item->tag, cmos_item->tag,
> +          cmos_item->size, cmos_item->size);
> +   data = ((const char *) cmos_item) + sizeof(*cmos_item);
> +   hexdump(data, cmos_item->size - sizeof(*cmos_item), vtophys(data), stdout,
> +           &format);
> + }
> +
> +/****************************************************************************
> + * option_checksum_print_fn
> + *
> + * Display function for 'option_checksum' item of LinuxBIOS table.
> + ****************************************************************************/
> +static void option_checksum_print_fn (const struct lb_record *rec)
> + { struct cmos_checksum *p;
> +
> +   p = (struct cmos_checksum *) rec;
> +   printf("CMOS checksum from bit %d to bit %d\n"
> +          "at position %d is type %s.\n",
> +          p->range_start, p->range_end, p->location,
> +          (p->type == CHECKSUM_PCBIOS) ? "PC BIOS" : "NONE");
> + }
> +
> +/****************************************************************************
> + * string_print_fn
> + *
> + * Display function for a generic item of LinuxBIOS table that simply
> + * consists of a string.
> + ****************************************************************************/
> +static void string_print_fn (const struct lb_record *rec)
> + { const struct lb_string *p;
> +
> +   p = (const struct lb_string *) rec;
> +   printf("%s\n", p->string);
> + }
> +
> +/****************************************************************************
> + * uint64_to_hex_string
> + *
> + * Convert the 64-bit integer 'n' to its hexadecimal string representation,
> + * storing the result in 's'.  's' must point to a buffer at least 19 bytes
> + * long.  The result is displayed with as many leading zeros as needed to
> + * make a 16-digit hex number including a 0x prefix (example: the number 1
> + * will be displayed as "0x0000000000000001").
> + ****************************************************************************/
> +static void uint64_to_hex_string (char str[], uint64_t n)
> + { int chars_printed;
> +
> +   str[0] = '0';
> +   str[1] = 'x';
> +
> +   /* Print the result right-justified with leading spaces in a
> +    * 16-character field. */
> +   chars_printed = sprintf(&str[2], "%016llx", (unsigned long long) n);
> +   assert(chars_printed == 16);
> + }
> Index: lxbios/lbtable.h
> ===================================================================
> --- lxbios/lbtable.h	(revision 0)
> +++ lxbios/lbtable.h	(revision 0)
> @@ -0,0 +1,43 @@
> +/*****************************************************************************\
> + * lbtable.h
> + * $Id: lbtable.h,v 1.2 2005/12/16 22:45:49 dsp_llnl Exp $
> + *****************************************************************************
> + *  Copyright (C) 2002-2005 The Regents of the University of California.
> + *  Produced at the Lawrence Livermore National Laboratory.
> + *  Written by Dave Peterson <dsp at llnl.gov> <dave_peterson at pobox.com>.
> + *  UCRL-CODE-2003-012
> + *  All rights reserved.
> + *
> + *  This file is part of lxbios, a utility for reading/writing LinuxBIOS
> + *  parameters and displaying information from the LinuxBIOS table.
> + *  For details, see <http://www.llnl.gov/linux/lxbios/>.
> + *
> + *  Please also read the file DISCLAIMER which is included in this software
> + *  distribution.
> + *
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License (as published by the
> + *  Free Software Foundation) version 2, dated June 1991.
> + *
> + *  This program is distributed in the hope that it will be useful, but
> + *  WITHOUT ANY WARRANTY; without even the IMPLIED WARRANTY OF
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the terms and
> + *  conditions of the GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, write to the Free Software Foundation, Inc.,
> + *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
> +\*****************************************************************************/
> +
> +#ifndef LXBIOS_LBTABLE_H
> +#define LXBIOS_LBTABLE_H
> +
> +#include "common.h"
> +
> +void get_lbtable (void);
> +void get_layout_from_cmos_table (void);
> +void dump_lbtable (void);
> +void list_lbtable_choices (void);
> +void list_lbtable_item (const char item[]);
> +
> +#endif  /* LXBIOS_LBTABLE_H */
> Index: lxbios/hexdump.c
> ===================================================================
> --- lxbios/hexdump.c	(revision 0)
> +++ lxbios/hexdump.c	(revision 0)
> @@ -0,0 +1,248 @@
> +/*****************************************************************************\
> + * hexdump.c
> + * $Id: hexdump.c,v 1.2 2005/12/16 22:45:49 dsp_llnl Exp $
> +\*****************************************************************************/
> +
> +#include "hexdump.h"
> +
> +/* hexdump.c
> + *
> + * Copyright (C) 2002
> + *     David S. Peterson.  All rights reserved.
> + *
> + * Author: David S. Peterson <dave_peterson at pobox.com>
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are
> + * met:
> + * 1. Redistributions of source code must retain the above copyright notice,
> + *    this list of conditions, and the entire permission notice, including
> + *    the following disclaimer of warranties.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions, and the entire permission notice,
> + *    including the following disclaimer in the documentation and/or other
> + *    materials provided with the distribution.
> + * 3. The name(s) of the author(s) may not be used to endorse or promote
> + *    products derived from this software without specific prior written
> + *    permission.
> + *
> + * ALTERNATIVELY, this product may be distributed under the terms of the GNU
> + * General Public License, in which case the provisions of the GPL are
> + * required INSTEAD OF the above restrictions.  (This clause is necessary due
> + * to a potential bad interaction between the GPL and the restrictions
> + * contained in a BSD-style copyright.)
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS OR
> + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
> + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED.
> + * IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +static void addrprint (FILE *outfile, uint64_t address, int width);
> +static void hexprint (FILE *outfile, unsigned char byte);
> +static void charprint (FILE *outfile, unsigned char byte,
> +                       unsigned char nonprintable,
> +                       is_printable_fn_t is_printable_fn);
> +
> +/*--------------------------------------------------------------------------
> + * hexdump
> + *
> + * Write a hex dump of 'mem' to 'outfile'.
> + *
> + * parameters:
> + *     mem:             a pointer to the memory to display
> + *     bytes:           the number of bytes of data to display
> + *     addrprint_start: The address to associate with the first byte of
> + *                      data.  For instance, a value of 0 indicates that the
> + *                      first byte displayed should be labeled as byte 0.
> + *     outfile:         The place where the hex dump should be written.
> + *                      For instance, stdout or stderr may be passed here.
> + *     format:          A structure specifying how the hex dump should be
> + *                      formatted.
> + *--------------------------------------------------------------------------*/
> +void hexdump (const void *mem, int bytes, uint64_t addrprint_start,
> +              FILE *outfile, const hexdump_format_t *format)
> + { int bytes_left, index, i;
> +   const unsigned char *p;
> +   is_printable_fn_t is_printable_fn;
> +
> +   /* Quietly return if the caller asks us to do something unreasonable. */
> +   if ((format->bytes_per_line <= 0) || (bytes < 0))
> +      return;
> +
> +   is_printable_fn = format->is_printable_fn;
> +
> +   if (is_printable_fn == NULL)
> +      is_printable_fn = default_is_printable_fn;
> +
> +   p = (const unsigned char *) mem;
> +   index = 0;
> +
> +   /* Each iteration handles one full line of output.  When loop terminates,
> +    * the number of remaining bytes to display (if any) will not be enough to
> +    * fill an entire line.
> +    */
> +   for (bytes_left = bytes;
> +        bytes_left >= format->bytes_per_line;
> +        bytes_left -= format->bytes_per_line)
> +    { /* print start address for current line */
> +      fprintf(outfile, format->indent);
> +      addrprint(outfile, addrprint_start + index, format->addrprint_width);
> +      fprintf(outfile, format->sep1);
> +
> +      /* display the bytes in hex */
> +      for (i = 0; ; )
> +       { hexprint(outfile, p[index++]);
> +
> +         if (++i >= format->bytes_per_line)
> +            break;
> +
> +         fprintf(outfile, format->sep2);
> +       }
> +
> +      index -= format->bytes_per_line;
> +      fprintf(outfile, format->sep3);
> +
> +      /* display the bytes as characters */
> +      for (i = 0; i < format->bytes_per_line; i++)
> +         charprint(outfile, p[index++], format->nonprintable,
> +                   is_printable_fn);
> +
> +      fprintf(outfile, "\n");
> +    }
> +
> +   if (bytes_left == 0)
> +      return;
> +
> +   /* print start address for last line */
> +   fprintf(outfile, format->indent);
> +   addrprint(outfile, addrprint_start + index, format->addrprint_width);
> +   fprintf(outfile, format->sep1);
> +
> +   /* display bytes for last line in hex */
> +   for (i = 0; i < bytes_left; i++)
> +    { hexprint(outfile, p[index++]);
> +      fprintf(outfile, format->sep2);
> +    }
> +
> +   index -= bytes_left;
> +
> +   /* pad the rest of the hex byte area with spaces */
> +   for (; ; )
> +    { fprintf(outfile, "  ");
> +
> +      if (++i >= format->bytes_per_line)
> +         break;
> +
> +      fprintf(outfile, format->sep2);
> +    }
> +
> +   fprintf(outfile, format->sep3);
> +
> +   /* display bytes for last line as characters */
> +   for (i = 0; i < bytes_left; i++)
> +      charprint(outfile, p[index++], format->nonprintable, is_printable_fn);
> +
> +   /* pad the rest of the character area with spaces */
> +   for (; i < format->bytes_per_line; i++)
> +      fprintf(outfile, " ");
> +
> +   fprintf(outfile, "\n");
> + }
> +
> +/*--------------------------------------------------------------------------
> + * default_is_printable_fn
> + *
> + * Determine whether the input character is printable.  The proper behavior
> + * for this type of function may be system-dependent.  This function takes a
> + * conservative approach.  If it is not adequate for your purposes, you can
> + * write your own.
> + *
> + * parameters:
> + *     c: the input character
> + *
> + * return value:
> + *     Return 1 if the input character is printable.  Otherwise return 0.
> + *--------------------------------------------------------------------------*/
> +int default_is_printable_fn (unsigned char c)
> + { return (c >= 0x20) && (c <= 0x7e); }
> +
> +/*--------------------------------------------------------------------------
> + * addrprint
> + *
> + * Display an address as a hexadecimal number.
> + *
> + * parameters:
> + *     outfile: the place where the output should be written
> + *     address: the address to display
> + *     width:   The number of bytes wide the address should be displayed as.
> + *              Must be a value from 1 to 8.
> + *--------------------------------------------------------------------------*/
> +static void addrprint (FILE *outfile, uint64_t address, int width)
> + { char s[17];
> +   int i;
> +
> +   /* force the user's input to be valid */
> +   if (width < 1)
> +      width = 1;
> +   else if (width > 8)
> +      width = 8;
> +
> +   /* convert address to string */
> +   sprintf(s, "%016llx", (unsigned long long) address);
> +
> +   /* write it out, with colons separating consecutive 16-bit chunks of the
> +    * address
> +    */
> +   for (i = 16 - (2 * width); ; )
> +    { fprintf(outfile, "%c", s[i]);
> +
> +      if (++i >= 16)
> +         break;
> +
> +      if ((i % 4) == 0)
> +         fprintf(outfile, ":");
> +    }
> + }
> +
> +/*--------------------------------------------------------------------------
> + * hexprint
> + *
> + * Display a byte as a two digit hex value.
> + *
> + * parameters:
> + *     outfile: the place where the output should be written
> + *     byte:    the byte to display
> + *--------------------------------------------------------------------------*/
> +static void hexprint (FILE *outfile, unsigned char byte)
> + { static const char tbl[] =
> +    { '0', '1', '2', '3', '4', '5', '6', '7',
> +      '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'
> +    };
> +
> +   fprintf(outfile, "%c%c", tbl[byte >> 4], tbl[byte & 0x0f]);
> + }
> +
> +/*--------------------------------------------------------------------------
> + * charprint
> + *
> + * Display a byte as its character representation.
> + *
> + * parameters:
> + *     outfile:         the place where the output should be written
> + *     byte:            the byte to display
> + *     nonprintable:    a substitute character to display if the byte
> + *                      represents a nonprintable character
> + *     is_printable_fn: a function that returns a boolean value indicating
> + *                      whether a given character is printable
> + *--------------------------------------------------------------------------*/
> +static void charprint (FILE *outfile, unsigned char byte,
> +                       unsigned char nonprintable,
> +                       is_printable_fn_t is_printable_fn)
> + { fprintf(outfile, "%c", is_printable_fn(byte) ? byte : nonprintable); }
> Index: lxbios/lxbios.1
> ===================================================================
> --- lxbios/lxbios.1	(revision 0)
> +++ lxbios/lxbios.1	(revision 0)
> @@ -0,0 +1,255 @@
> +.\"***************************************************************************\
> +.\" lxbios.1
> +.\" $Id: lxbios.1,v 1.2 2005/12/16 22:45:49 dsp_llnl Exp $
> +.\"***************************************************************************
> +.\"  Copyright (C) 2002, 2003 The Regents of the University of California.
> +.\"  Produced at the Lawrence Livermore National Laboratory.
> +.\"  Written by David S. Peterson <dsp at llnl.gov> <dave_peterson at pobox.com>.
> +.\"  UCRL-CODE-2003-012
> +.\"  All rights reserved.
> +.\"
> +.\"  This file is part of lxbios, a utility for reading/writing LinuxBIOS
> +.\"  parameters and displaying information from the LinuxBIOS table.
> +.\"  For details, see <http://www.llnl.gov/linux/lxbios/>.
> +.\"
> +.\"  Please also read the file DISCLAIMER which is included in this software
> +.\"  distribution.
> +.\"
> +.\"  This program is free software; you can redistribute it and/or modify it
> +.\"  under the terms of the GNU General Public License (as published by the
> +.\"  Free Software Foundation) version 2, dated June 1991.
> +.\"
> +.\"  This program is distributed in the hope that it will be useful, but
> +.\"  WITHOUT ANY WARRANTY; without even the IMPLIED WARRANTY OF
> +.\"  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the terms and
> +.\"  conditions of the GNU General Public License for more details.
> +.\"
> +.\"  You should have received a copy of the GNU General Public License along
> +.\"  with this program; if not, write to the Free Software Foundation, Inc.,
> +.\"  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
> +.\"***************************************************************************/
> +.TH LXBIOS 1 "December 2005" Linux
> +.SH NAME
> +lxbios \- read/write LinuxBIOS-related information
> +.SH SYNOPSIS
> +.B "lxbios [OPTS] [-n] -r NAME"
> +.br
> +.B "lxbios [OPTS] -e NAME"
> +.br
> +.B "lxbios [OPTS] -a"
> +.br
> +.B "lxbios [OPTS] -w NAME=VALUE"
> +.br
> +.B "lxbios [OPTS] -p INPUT_FILE"
> +.br
> +.B "lxbios [OPTS] -i"
> +.br
> +.B "lxbios [OPTS] -c [VALUE]"
> +.br
> +.B "lxbios [OPTS] -l [ARG]"
> +.br
> +.B "lxbios [OPTS] -d"
> +.br
> +.B "lxbios [OPTS] -Y"
> +.br
> +.B "lxbios [OPTS] -b OUTPUT_FILE"
> +.br
> +.B "lxbios [OPTS] -B INPUT_FILE"
> +.br
> +.B "lxbios [OPTS] -x"
> +.br
> +.B "lxbios [OPTS] -X DUMPFILE"
> +.br
> +.B "lxbios [OPTS] -v"
> +.br
> +.B "lxbios [OPTS] -h"
> +.SH DESCRIPTION
> +.B "lxbios"
> +is a utility for reading/writing LinuxBIOS parameters and displaying
> +information from the LinuxBIOS table.
> +
> +The LinuxBIOS table resides in low physical memory.  It is created at boot
> +time by LinuxBIOS, and contains various system information such as the type
> +of mainboard in use.  It specifies locations in the CMOS (nonvolatile RAM)
> +where the LinuxBIOS parameters are stored.
> +
> +This program is intended for x86-based systems that use LinuxBIOS.  For
> +information about LinuxBIOS, see
> +.br
> +http://www.linuxbios.org/.
> +.SH PARAMETERS
> +.TP
> +.B "[-n] -r NAME"
> +Show the value of the LinuxBIOS parameter given by
> +.B "NAME."
> +If
> +.B "-n"
> +is specified, show only the value.  Otherwise show both parameter name and
> +value.
> +.TP
> +.B "-e NAME"
> +Show all possible values for parameter given by
> +.B "NAME."
> +.TP
> +.B "-a"
> +Show the names and values for all LinuxBIOS parameters.
> +.TP
> +.B "-w NAME=VALUE"
> +Assign
> +.B "VALUE"
> +to LinuxBIOS parameter given by
> +.B "NAME."
> +.TP
> +.B "-p INPUT_FILE"
> +Assign values to LinuxBIOS parameters according to the contents of
> +.B "INPUT_FILE."
> +The format of this file is described below.
> +.TP
> +.B "-i"
> +This is similar to the
> +.B "-p"
> +option, except that the contents of the input file are taken from standard
> +input.
> +.TP
> +.B "-c [VALUE]"
> +If
> +.B "VALUE"
> +is present then set the CMOS checksum for the LinuxBIOS parameters to
> +.B "VALUE." 
> +Otherwise, show the checksum value.
> +.TP
> +.B "-l [ARG]"
> +If
> +.B "ARG"
> +is present then show information from the LinuxBIOS table as specified by
> +.B "ARG."
> +Otherwise show all possible values for
> +.B "ARG."
> +.TP
> +.B "-d"
> +Do a low-level dump of the LinuxBIOS table.
> +.TP
> +.B "-Y"
> +Write CMOS layout information to standard output.  If redirected to a file,
> +the layout information may be used as input for the
> +.B "'-y LAYOUT_FILE'"
> +option (see below).
> +.TP
> +.B "-b OUTPUT_FILE"
> +Write the contents of CMOS memory to the binary file
> +.B "OUTPUT_FILE."
> +The first 14 bytes of
> +.B "OUTPUT_FILE"
> +do not contain actual CMOS data, and are always written as zeros.  This is
> +because the first 14 bytes of the CMOS area do not contain CMOS memory.  These
> +bytes are involved with the functioning of the real time clock.
> +.TP
> +.B "-B INPUT_FILE"
> +Read binary data from
> +.B "INPUT_FILE"
> +and write the data to CMOS memory.  The first 14 bytes of
> +.B "INPUT_FILE"
> +are skipped and data is written to CMOS starting at the 15th byte of the CMOS
> +area.  This is because the first 14 bytes of the CMOS area do not contain CMOS
> +memory.  These bytes are involved with the functioning of the real time clock.
> +.TP
> +.B "-x"
> +Show a hex dump of all CMOS data.  The first 14 bytes of the dump do not
> +contain actual CMOS data, and are always shown as zeros.  This is because the
> +first 14 bytes of the CMOS area do not contain CMOS memory.  These bytes are
> +involved with the functioning of the real time clock.
> +.TP
> +.B "-X DUMPFILE"
> +Read binary data from
> +.B "DUMPFILE"
> +(presumably a CMOS dumpfile created using the
> +.B "-b OUTPUT_FILE"
> +option) and show a hex dump of the data.
> +.TP
> +.B "-v"
> +Show version information for this program.
> +.TP
> +.B "-h"
> +Show a help message for this program.
> +.SH "OPTIONS"
> +In all cases above,
> +.B "[OPTS]"
> +evaluates to the following:
> +
> +.B "    [-y LAYOUT_FILE | -t]"
> +
> +The
> +.B "'-y LAYOUT_FILE'"
> +option tells lxbios to obtain CMOS layout information from the contents of
> +.B "LAYOUT_FILE."
> +Likewise, the
> +.B "'-t'"
> +option tells lxbios to obtain CMOS layout information from the CMOS option
> +table (contained within the LinuxBIOS table).  If neither option is
> +specified, the CMOS option table is used by default.
> +.B "LAYOUT_FILE"
> +follows the format of the
> +.B "cmos.layout"
> +files provided by LinuxBIOS.
> +
> +If the LinuxBIOS installed on your system was built without specifying
> +.B "HAVE_OPTION_TABLE,"
> +then the LinuxBIOS table will not contain a CMOS option table.  In this case,
> +the
> +.B "'-y LAYOUT_FILE'"
> +option must be used.
> +
> +These two options are silently ignored when used in combination with other
> +options (such as
> +.B "-h,"
> +for instance) for which they are not applicable.
> +.SH FILE FORMAT
> +For the
> +.B "-p"
> +option,
> +.B "INPUT_FILE"
> +must consist of a sequence of lines such that each line is either a blank
> +line, a comment, or an assignment.  A blank line consists only of zero or
> +more whitespace characters (spaces and tabs).  A comment is constructed as
> +follows:
> +
> +.B "    [ws]#[text]"
> +
> +Here,
> +.B "[ws]"
> +indicates optional whitespace characters and
> +.B "[text]"
> +indicates optional text.  Blank lines and comments are both ignored.  An
> +assignment is constructed as follows:
> +
> +.B "    [ws]NAME[ws]=[ws]VALUE[ws]"
> +
> +Here,
> +.B "NAME"
> +is the name of a LinuxBIOS parameter and
> +.B "VALUE"
> +is the value that will be assigned to
> +.B "NAME."
> +.B "VALUE"
> +is allowed to contain whitespace characters, but it must begin and end with
> +nonwhitespace characters.  Note that each comment must appear on a line by
> +itself.  If you attempt to add a comment to the end of an assignment, then the
> +comment will be interpreted as part of
> +.B "VALUE."
> +It is useful to observe that the output produced by both the
> +.B "-a"
> +and the
> +.B "'[-n] NAME'"
> +options (without
> +.B "-n"
> +specified) adheres to this file format.
> +.SH BUGS
> +This program does not implement any type of synchronization to ensure that
> +different processes don't stomp on each other when trying to access the
> +nonvolatile RAM simultaneously.  Therefore, corruption of the BIOS parameter
> +values may occur if multiple instances of this program are executed
> +concurrently.
> +.SH AUTHORS
> +David S. Peterson <dsp at llnl.gov> <dave_peterson at pobox.com>
> +.br
> +Stefan Reinauer <stepan at openbios.org>
> Index: lxbios/hexdump.h
> ===================================================================
> --- lxbios/hexdump.h	(revision 0)
> +++ lxbios/hexdump.h	(revision 0)
> @@ -0,0 +1,132 @@
> +/*****************************************************************************\
> + * hexdump.h
> + * $Id: hexdump.h,v 1.2 2005/12/16 22:45:49 dsp_llnl Exp $
> +\*****************************************************************************/
> +
> +#ifndef _HEXDUMP_H
> +#define _HEXDUMP_H
> +
> +/* hexdump.h
> + *
> + * Copyright (C) 2002
> + *     David S. Peterson.  All rights reserved.
> + *
> + * Author: David S. Peterson <dave_peterson at pobox.com>
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are
> + * met:
> + * 1. Redistributions of source code must retain the above copyright notice,
> + *    this list of conditions, and the entire permission notice, including
> + *    the following disclaimer of warranties.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions, and the entire permission notice,
> + *    including the following disclaimer in the documentation and/or other
> + *    materials provided with the distribution.
> + * 3. The name(s) of the author(s) may not be used to endorse or promote
> + *    products derived from this software without specific prior written
> + *    permission.
> + *
> + * ALTERNATIVELY, this product may be distributed under the terms of the GNU
> + * General Public License, in which case the provisions of the GPL are
> + * required INSTEAD OF the above restrictions.  (This clause is necessary due
> + * to a potential bad interaction between the GPL and the restrictions
> + * contained in a BSD-style copyright.)
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS OR
> + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
> + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED.
> + * IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +#include <stdint.h>
> +#include <sys/types.h>
> +#include <stdio.h>
> +
> +typedef int (*is_printable_fn_t) (unsigned char c);
> +
> +/*--------------------------------------------------------------------------
> + * hexdump_format_t
> + *
> + * This specifies how the output of the 'hexdump' function should look.
> + *
> + * fields:
> + *     bytes_per_line:  the number of data bytes to display per line of
> + *                      output
> + *     addrprint_width: Each line of output begins with the address of the
> + *                      first data byte displayed on that line.  This
> + *                      specifies the number of bytes wide the address
> + *                      should be displayed as.  This value must be from 1
> + *                      to 8.
> + *     indent:          This is a string to display at the start of each
> + *                      output line.  Its purpose is to indent the output.
> + *     sep1:            This is a string to display between the address and
> + *                      the bytes of data displayed in hex.  It serves as a
> + *                      separator.
> + *     sep2:            This is a string to display between individual hex
> + *                      values.  It serves as a separator.
> + *     sep3:            This is a string to display between the bytes of
> + *                      data in hex and the bytes of data displayed as
> + *                      characters.  It serves as a separator.
> + *     nonprintable:    This is a substitute character to display in place
> + *                      of nonprintable characters.
> + *     is_printable_fn: This is a user-supplied function that takes a byte
> + *                      value as input and returns a boolean value
> + *                      indicating whether the corresponding character is
> + *                      printable.  A value of NULL will cause
> + *                      default_is_printable_fn to be used.
> + *--------------------------------------------------------------------------*/
> +typedef struct
> + { int bytes_per_line;
> +   int addrprint_width;
> +   const char *indent;
> +   const char *sep1;
> +   const char *sep2;
> +   const char *sep3;
> +   unsigned char nonprintable;
> +   is_printable_fn_t is_printable_fn;
> + }
> +hexdump_format_t;
> +
> +/*--------------------------------------------------------------------------
> + * hexdump
> + *
> + * Write a hex dump of 'mem' to 'outfile'.
> + *
> + * parameters:
> + *     mem:             a pointer to the memory to display
> + *     bytes:           the number of bytes of data to display
> + *     addrprint_start: The address to associate with the first byte of
> + *                      data.  For instance, a value of 0 indicates that the
> + *                      first byte displayed should be labeled as byte 0.
> + *     outfile:         The place where the hex dump should be written.
> + *                      For instance, stdout or stderr may be passed here.
> + *     format:          A structure specifying how the hex dump should be
> + *                      formatted.
> + *--------------------------------------------------------------------------*/
> +void hexdump (const void *mem, int bytes, uint64_t addrprint_start,
> +              FILE *outfile, const hexdump_format_t *format);
> +
> +/*--------------------------------------------------------------------------
> + * default_is_printable_fn
> + *
> + * Determine whether the input character is printable.  The proper behavior
> + * for this type of function may be system-dependent.