[LinuxBIOS] r447 - in LinuxBIOSv3: include/device mainboard/emulation/qemu-x86

svn at openbios.org svn at openbios.org
Thu Jul 12 03:03:05 CEST 2007


Author: uwe
Date: 2007-07-12 03:03:05 +0200 (Thu, 12 Jul 2007)
New Revision: 447

Modified:
   LinuxBIOSv3/include/device/pci_ids.h
   LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile
   LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c
   LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c
Log:
Add (and use) the new PCI IDs:
 - PCI_VENDOR_ID_CIRRUS
 - PCI_DEVICE_ID_CIRRUS_5446

Some minor cosmetic fixes (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: LinuxBIOSv3/include/device/pci_ids.h
===================================================================
--- LinuxBIOSv3/include/device/pci_ids.h	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/include/device/pci_ids.h	2007-07-12 01:03:05 UTC (rev 447)
@@ -11,151 +11,148 @@
 #ifndef DEVICE_PCI_IDS_H
 #define DEVICE_PCI_IDS_H
 
-/*
- *	PCI Class, Vendor and Device IDs
- *
- *	Please keep sorted.
- */
-
 /* Device classes and subclasses. */
 
-#define PCI_CLASS_NOT_DEFINED		0x0000
-#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
+#define PCI_CLASS_NOT_DEFINED			0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA		0x0001
 
-#define PCI_BASE_CLASS_STORAGE		0x01
-#define PCI_CLASS_STORAGE_SCSI		0x0100
-#define PCI_CLASS_STORAGE_IDE		0x0101
-#define PCI_CLASS_STORAGE_FLOPPY	0x0102
-#define PCI_CLASS_STORAGE_IPI		0x0103
-#define PCI_CLASS_STORAGE_RAID		0x0104
-#define PCI_CLASS_STORAGE_SATA		0x0106
-#define PCI_CLASS_STORAGE_SATA_AHCI	0x010601
-#define PCI_CLASS_STORAGE_SAS		0x0107
-#define PCI_CLASS_STORAGE_OTHER		0x0180
+#define PCI_BASE_CLASS_STORAGE			0x01
+#define PCI_CLASS_STORAGE_SCSI			0x0100
+#define PCI_CLASS_STORAGE_IDE			0x0101
+#define PCI_CLASS_STORAGE_FLOPPY		0x0102
+#define PCI_CLASS_STORAGE_IPI			0x0103
+#define PCI_CLASS_STORAGE_RAID			0x0104
+#define PCI_CLASS_STORAGE_SATA			0x0106
+#define PCI_CLASS_STORAGE_SATA_AHCI		0x010601
+#define PCI_CLASS_STORAGE_SAS			0x0107
+#define PCI_CLASS_STORAGE_OTHER			0x0180
 
-#define PCI_BASE_CLASS_NETWORK		0x02
-#define PCI_CLASS_NETWORK_ETHERNET	0x0200
-#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
-#define PCI_CLASS_NETWORK_FDDI		0x0202
-#define PCI_CLASS_NETWORK_ATM		0x0203
-#define PCI_CLASS_NETWORK_OTHER		0x0280
+#define PCI_BASE_CLASS_NETWORK			0x02
+#define PCI_CLASS_NETWORK_ETHERNET		0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING		0x0201
+#define PCI_CLASS_NETWORK_FDDI			0x0202
+#define PCI_CLASS_NETWORK_ATM			0x0203
+#define PCI_CLASS_NETWORK_OTHER			0x0280
 
-#define PCI_BASE_CLASS_DISPLAY		0x03
-#define PCI_CLASS_DISPLAY_VGA		0x0300
-#define PCI_CLASS_DISPLAY_XGA		0x0301
-#define PCI_CLASS_DISPLAY_3D		0x0302
-#define PCI_CLASS_DISPLAY_OTHER		0x0380
+#define PCI_BASE_CLASS_DISPLAY			0x03
+#define PCI_CLASS_DISPLAY_VGA			0x0300
+#define PCI_CLASS_DISPLAY_XGA			0x0301
+#define PCI_CLASS_DISPLAY_3D			0x0302
+#define PCI_CLASS_DISPLAY_OTHER			0x0380
 
-#define PCI_BASE_CLASS_MULTIMEDIA	0x04
-#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
-#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
-#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
-#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
+#define PCI_BASE_CLASS_MULTIMEDIA		0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO		0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO		0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE		0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER		0x0480
 
-#define PCI_BASE_CLASS_MEMORY		0x05
-#define PCI_CLASS_MEMORY_RAM		0x0500
-#define PCI_CLASS_MEMORY_FLASH		0x0501
-#define PCI_CLASS_MEMORY_OTHER		0x0580
+#define PCI_BASE_CLASS_MEMORY			0x05
+#define PCI_CLASS_MEMORY_RAM			0x0500
+#define PCI_CLASS_MEMORY_FLASH			0x0501
+#define PCI_CLASS_MEMORY_OTHER			0x0580
 
-#define PCI_BASE_CLASS_BRIDGE		0x06
-#define PCI_CLASS_BRIDGE_HOST		0x0600
-#define PCI_CLASS_BRIDGE_ISA		0x0601
-#define PCI_CLASS_BRIDGE_EISA		0x0602
-#define PCI_CLASS_BRIDGE_MC		0x0603
-#define PCI_CLASS_BRIDGE_PCI		0x0604
-#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
-#define PCI_CLASS_BRIDGE_NUBUS		0x0606
-#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
-#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
-#define PCI_CLASS_BRIDGE_OTHER		0x0680
+#define PCI_BASE_CLASS_BRIDGE			0x06
+#define PCI_CLASS_BRIDGE_HOST			0x0600
+#define PCI_CLASS_BRIDGE_ISA			0x0601
+#define PCI_CLASS_BRIDGE_EISA			0x0602
+#define PCI_CLASS_BRIDGE_MC			0x0603
+#define PCI_CLASS_BRIDGE_PCI			0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA			0x0605
+#define PCI_CLASS_BRIDGE_NUBUS			0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS		0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY		0x0608
+#define PCI_CLASS_BRIDGE_OTHER			0x0680
 
-#define PCI_BASE_CLASS_COMMUNICATION	0x07
-#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
-#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
-#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
-#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
-#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
+#define PCI_BASE_CLASS_COMMUNICATION		0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL		0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL	0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL	0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM		0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER		0x0780
 
-#define PCI_BASE_CLASS_SYSTEM		0x08
-#define PCI_CLASS_SYSTEM_PIC		0x0800
-#define PCI_CLASS_SYSTEM_PIC_IOAPIC	0x080010
-#define PCI_CLASS_SYSTEM_PIC_IOXAPIC	0x080020
-#define PCI_CLASS_SYSTEM_DMA		0x0801
-#define PCI_CLASS_SYSTEM_TIMER		0x0802
-#define PCI_CLASS_SYSTEM_RTC		0x0803
-#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
-#define PCI_CLASS_SYSTEM_SDHCI		0x0805
-#define PCI_CLASS_SYSTEM_OTHER		0x0880
+#define PCI_BASE_CLASS_SYSTEM			0x08
+#define PCI_CLASS_SYSTEM_PIC			0x0800
+#define PCI_CLASS_SYSTEM_PIC_IOAPIC		0x080010
+#define PCI_CLASS_SYSTEM_PIC_IOXAPIC		0x080020
+#define PCI_CLASS_SYSTEM_DMA			0x0801
+#define PCI_CLASS_SYSTEM_TIMER			0x0802
+#define PCI_CLASS_SYSTEM_RTC			0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG		0x0804
+#define PCI_CLASS_SYSTEM_SDHCI			0x0805
+#define PCI_CLASS_SYSTEM_OTHER			0x0880
 
-#define PCI_BASE_CLASS_INPUT		0x09
-#define PCI_CLASS_INPUT_KEYBOARD	0x0900
-#define PCI_CLASS_INPUT_PEN		0x0901
-#define PCI_CLASS_INPUT_MOUSE		0x0902
-#define PCI_CLASS_INPUT_SCANNER		0x0903
-#define PCI_CLASS_INPUT_GAMEPORT	0x0904
-#define PCI_CLASS_INPUT_OTHER		0x0980
+#define PCI_BASE_CLASS_INPUT			0x09
+#define PCI_CLASS_INPUT_KEYBOARD		0x0900
+#define PCI_CLASS_INPUT_PEN			0x0901
+#define PCI_CLASS_INPUT_MOUSE			0x0902
+#define PCI_CLASS_INPUT_SCANNER			0x0903
+#define PCI_CLASS_INPUT_GAMEPORT		0x0904
+#define PCI_CLASS_INPUT_OTHER			0x0980
 
-#define PCI_BASE_CLASS_DOCKING		0x0a
-#define PCI_CLASS_DOCKING_GENERIC	0x0a00
-#define PCI_CLASS_DOCKING_OTHER		0x0a80
+#define PCI_BASE_CLASS_DOCKING			0x0a
+#define PCI_CLASS_DOCKING_GENERIC		0x0a00
+#define PCI_CLASS_DOCKING_OTHER			0x0a80
 
-#define PCI_BASE_CLASS_PROCESSOR	0x0b
-#define PCI_CLASS_PROCESSOR_386		0x0b00
-#define PCI_CLASS_PROCESSOR_486		0x0b01
-#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
-#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
-#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
-#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
-#define PCI_CLASS_PROCESSOR_CO		0x0b40
+#define PCI_BASE_CLASS_PROCESSOR		0x0b
+#define PCI_CLASS_PROCESSOR_386			0x0b00
+#define PCI_CLASS_PROCESSOR_486			0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM		0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA		0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC		0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS		0x0b30
+#define PCI_CLASS_PROCESSOR_CO			0x0b40
 
-#define PCI_BASE_CLASS_SERIAL		0x0c
-#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
-#define PCI_CLASS_SERIAL_FIREWIRE_OHCI	0x0c0010
-#define PCI_CLASS_SERIAL_ACCESS		0x0c01
-#define PCI_CLASS_SERIAL_SSA		0x0c02
-#define PCI_CLASS_SERIAL_USB		0x0c03
-#define PCI_CLASS_SERIAL_USB_UHCI	0x0c0300
-#define PCI_CLASS_SERIAL_USB_OHCI	0x0c0310
-#define PCI_CLASS_SERIAL_USB_EHCI	0x0c0320
-#define PCI_CLASS_SERIAL_FIBER		0x0c04
-#define PCI_CLASS_SERIAL_SMBUS		0x0c05
+#define PCI_BASE_CLASS_SERIAL			0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE		0x0c00
+#define PCI_CLASS_SERIAL_FIREWIRE_OHCI		0x0c0010
+#define PCI_CLASS_SERIAL_ACCESS			0x0c01
+#define PCI_CLASS_SERIAL_SSA			0x0c02
+#define PCI_CLASS_SERIAL_USB			0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI		0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI		0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI		0x0c0320
+#define PCI_CLASS_SERIAL_FIBER			0x0c04
+#define PCI_CLASS_SERIAL_SMBUS			0x0c05
 
 #define PCI_BASE_CLASS_WIRELESS			0x0d
 #define PCI_CLASS_WIRELESS_RF_CONTROLLER	0x0d10
 #define PCI_CLASS_WIRELESS_WHCI			0x0d1010
 
-#define PCI_BASE_CLASS_INTELLIGENT	0x0e
-#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
+#define PCI_BASE_CLASS_INTELLIGENT		0x0e
+#define PCI_CLASS_INTELLIGENT_I2O		0x0e00
 
-#define PCI_BASE_CLASS_SATELLITE	0x0f
-#define PCI_CLASS_SATELLITE_TV		0x0f00
-#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
-#define PCI_CLASS_SATELLITE_VOICE	0x0f03
-#define PCI_CLASS_SATELLITE_DATA	0x0f04
+#define PCI_BASE_CLASS_SATELLITE		0x0f
+#define PCI_CLASS_SATELLITE_TV			0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO		0x0f01
+#define PCI_CLASS_SATELLITE_VOICE		0x0f03
+#define PCI_CLASS_SATELLITE_DATA		0x0f04
 
-#define PCI_BASE_CLASS_CRYPT		0x10
-#define PCI_CLASS_CRYPT_NETWORK		0x1000
-#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
-#define PCI_CLASS_CRYPT_OTHER		0x1080
+#define PCI_BASE_CLASS_CRYPT			0x10
+#define PCI_CLASS_CRYPT_NETWORK			0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT		0x1001
+#define PCI_CLASS_CRYPT_OTHER			0x1080
 
-#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
-#define PCI_CLASS_SP_DPIO		0x1100
-#define PCI_CLASS_SP_OTHER		0x1180
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING	0x11
+#define PCI_CLASS_SP_DPIO			0x1100
+#define PCI_CLASS_SP_OTHER			0x1180
 
-#define PCI_CLASS_OTHERS		0xff
+#define PCI_CLASS_OTHERS			0xff
 
 /* Vendors and devices. Sort key: vendor first, device next. */
 
-#define PCI_VENDOR_ID_AMD		0x1022
-#define PCI_DEVICE_ID_AMD_LXBRIDGE	0x2080
-#define PCI_DEVICE_ID_AMD_CS5536_ISA	0x2090
-#define PCI_DEVICE_ID_AMD_CS5536_FLASH	0x2091
-#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE	0x2092
-#define PCI_DEVICE_ID_AMD_CS5536_AUDIO	0x2093
-#define PCI_DEVICE_ID_AMD_CS5536_OHCI	0x2094
-#define PCI_DEVICE_ID_AMD_CS5536_EHCI	0x2095
-#define PCI_DEVICE_ID_AMD_CS5536_UDC	0x2096
-#define PCI_DEVICE_ID_AMD_CS5536_OTG	0x2097
-#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE	0x209A
+#define PCI_VENDOR_ID_AMD			0x1022
+#define PCI_DEVICE_ID_AMD_LXBRIDGE		0x2080
+#define PCI_DEVICE_ID_AMD_CS5536_ISA		0x2090
+#define PCI_DEVICE_ID_AMD_CS5536_FLASH		0x2091
+#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE		0x2092
+#define PCI_DEVICE_ID_AMD_CS5536_AUDIO		0x2093
+#define PCI_DEVICE_ID_AMD_CS5536_OHCI		0x2094
+#define PCI_DEVICE_ID_AMD_CS5536_EHCI		0x2095
+#define PCI_DEVICE_ID_AMD_CS5536_UDC		0x2096
+#define PCI_DEVICE_ID_AMD_CS5536_OTG		0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE		0x209A
 
+#define PCI_VENDOR_ID_CIRRUS			0x1013
+#define PCI_DEVICE_ID_CIRRUS_5446		0x00b8	/* Used by QEMU */
+
 #endif /* DEVICE_PCI_IDS_H */

Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile	2007-07-12 01:03:05 UTC (rev 447)
@@ -19,11 +19,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-STAGE0_MAINBOARD_OBJ :=\
-		$(obj)/mainboard/$(MAINBOARDDIR)/stage1.o 
 #
-# VPD or SIP ROM or ... how does NVIDIA call it?
+# VPD or SIP ROM or... how does NVIDIA call it?
 # Some space to cope with dirty southbridge tricks.
 # Do we want to put our own stuff there, too?
 #
@@ -38,12 +37,13 @@
 # The initram file is always uncompressed. It belongs into the mainboard
 # directory and is built from what was auto.c in v2.
 #
-INITRAM_OBJ =   $(obj)/mainboard/$(MAINBOARDDIR)/initram.o 
 
-$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ) 
+INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o
+
+$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(INITRAM_OBJ)
 	$(Q)# initram links against stage0
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ)  \
+	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(INITRAM_OBJ) \
 		--entry=main -o $(obj)/linuxbios.initram.o
 	$(Q)printf "  OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \
@@ -70,15 +70,15 @@
 	$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
 	$(Q)$(obj)/util/options/build_opt_tbl -b \
 		--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
-		--option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c 
+		--option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
 
 $(obj)/option_table: $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o
 	$(Q)printf "  OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(OBJCOPY) -O binary $< $@ 
+	$(Q)$(OBJCOPY) -O binary $< $@
 
-STAGE2_MAINBOARD_OBJ = vga.o 
+STAGE2_MAINBOARD_OBJ = vga.o
 
-STAGE2_CHIPSET_OBJ = 
+STAGE2_CHIPSET_OBJ =
 
 $(obj)/mainboard/$(MAINBOARDDIR)/%.o: $(src)/mainboard/$(MAINBOARDDIR)/%.c
 	$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)

Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c	2007-07-12 01:03:05 UTC (rev 447)
@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* no printk allowed until hardware is ready; hardware is ready */
 /** 
- * start up hardware needed for stage1
+ * Start up hardware needed for stage1.
+ *
+ * No printk() allowed until hardware is ready; hardware is ready.
+ * TODO: Fix above comment? It's unclear.
  */
 void hardware_stage1(void)
 {

Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c
===================================================================
--- LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c	2007-07-11 19:47:36 UTC (rev 446)
+++ LinuxBIOSv3/mainboard/emulation/qemu-x86/vga.c	2007-07-12 01:03:05 UTC (rev 447)
@@ -23,6 +23,7 @@
 #include <console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <string.h>
 #include <keyboard.h>
 
@@ -40,19 +41,21 @@
 }
 
 static struct device_operations qemuvga_pci_ops_dev = {
-	.constructor		 = default_device_constructor,
-	.phase3_scan		 = 0,
-	.phase4_read_resources	 = pci_dev_read_resources,
-	.phase4_set_resources	 = pci_dev_set_resources,
-	.phase4_enable_disable	 = setup_onboard,
-	.phase5_enable_resources = pci_dev_enable_resources,
-	.phase6_init		 = pci_dev_init,
-	.ops_pci		 = &pci_dev_ops_pci,
+	.constructor			= default_device_constructor,
+	.phase3_scan			= 0,
+	.phase4_read_resources		= pci_dev_read_resources,
+	.phase4_set_resources		= pci_dev_set_resources,
+	.phase4_enable_disable		= setup_onboard,
+	.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase6_init			= pci_dev_init,
+	.ops_pci			= &pci_dev_ops_pci,
 };
 
 struct constructor qemuvga_constructors[] = {
 	{.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = 0x1013,.device = 0x00b8}}},
+		.u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
+			      .device = PCI_DEVICE_ID_CIRRUS_5446}}},
 	 &qemuvga_pci_ops_dev},
+
 	{.ops = 0},
 };





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