[LinuxBIOS] Opteron caching of device memory
kononov at dls.net
Fri Jun 15 00:00:43 CEST 2007
On 06/14/2007 03:59 PM, ron minnich wrote:
> On 6/14/07, Marc Jones <Marc.Jones at amd.com> wrote:
>> Now that I think about it, it makes sense that you can't set writeback
>> to noncoherent (nonsystem) memory space. What if another device wants to
>> write to that memory. There is no way for the cache to snoop that it was
>> written. You would need a coherent HT link to to your FPGA to get the
>> cache snoop messaging.
> Also, writeback would be a disaster for drivers. The expectation for a
> driver is that when the code sets bist in an MMIO space, that bit gets
> set. That's a writethrough semantic.
I know for sure that the PowerPC architecture has no problems with caching
anything regardless whether it is SMP or not. Cache coherency is somewhat
"religiuos" for x86.
If my driver and only my driver accesses a device why cannot the device be
cached? If needed, I can use cflush instructions to synchronize the cache
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