[LinuxBIOS] Accessing MCP55 internal serial UART, GPIOs
Gregg C Levine
hansolofalcon at worldnet.att.net
Wed Mar 14 17:03:28 CET 2007
Ed, you are describing this board as a custom one. This tells me that it
might have been made for a customer I am using it that way because I
frequently end up looking at a similar design for a project. It's the
complexities that end up stopping me. Can you provide a good photo of the
board? I freely admit that I am curious.
And I do admit that your problems with this design are not unique, I've
heard stories of problems similar to yours for the PPC family, and that's
with its own ideas of how to start up properly.
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you. Always." Obi-Wan Kenobi
> -----Original Message-----
> From: linuxbios-bounces+hansolofalcon=worldnet.att.net at linuxbios.org
> bounces+hansolofalcon=worldnet.att.net at linuxbios.org] On Behalf Of Ed
> Sent: Wednesday, March 14, 2007 1:14 AM
> To: LinuxBIOS
> Subject: [LinuxBIOS] Accessing MCP55 internal serial UART, GPIOs
> I'm trying to get LinuxBIOS booting on a custom board with a Socket
> AM2 Athlon and an MCP55. There is no SuperIO; instead, we're using the
> MCP55's internal serial UART. A couple of the MCP55's GPIO pins are
> hooked up to LEDs.
> I have had no luck getting either the serial port or the LEDs to work,
> though. My cache_as_ram_main() sets up the serial port by:
> - enabling the serial port and configuring the IO address and IRQ in
> register 0x78 on PCI device 1:0
> - NOT redirecting IO address 0x3f8 to the LPC bus in register 0xa0 on
> PCI device 1:0 (as is done when the serial port is on a SuperIO)
> - setting GPIO pins 11, 12, 13 and 14 to their "normal" (non-GPIO)
> mode, which I hope is RX, TX, DTR and DSR
> It also tries to turn on an LED on GPIO pin 1 by setting it to GPIO
> output mode, drive low.
> Has anyone tried tried this with an MCP55-based board? Any ideas for
> other ways to communicate with the outside world when the serial port
> doesn't work?
More information about the coreboot