[LinuxBIOS] 82830.h

joe at smittys.pointclark.net joe at smittys.pointclark.net
Thu Mar 22 18:13:33 CET 2007


Can someone take a look at my memory Register definitions file. Is it  
too much??
Do you think I should weed out the Graphic and Read Only ones?

Thanks - Joe
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/*
 * This file is part of the LinuxBIOS project.
 *
 * Copyright (C) 2003-2005 John Doe <john at example.com>
 * Copyright (C) 2005 Jane Doe <jane at example.com>
 *
 * Copyright (C) 2006 Company, Inc.
 * Written by Janet Doe <janet at example.com> for Company, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#define VID 0X00     /* Vendor Identification Register - Default Value 0X8086 - 16 bits Read Only */
#define DID 0X02     /* Device Identification Register - Default Value 0X3575 - 16 bits Read Only */
#define PCICMD 0X04  /* PCI Command Register - Default Value 0X0006 - 16 bits */
#define PCICMD_VAL 0X0006  /* PCI Command Register Value - 16 bits */
#define PCISTS 0X06  /* PCI Status Register - Default Value 0X0010 - 16 bits */
#define PCISTS_VAL 0X2010  /* PCI Status Register Value - 16 bits */
#define RID 0X08     /* Revision Identification Register - Default Value 0X04 - 8 bits Read Only */
#define SUBC 0X0A     /* SUB-Class Code Register - Default Value 0X00 - 8 bits Read Only */
#define BCC 0X0B     /* Base Class Code Register - Default Value 0X06 - 8 bits Read Only */
#define MLT 0X0D     /* Master Latency Timer Register - Default Value 0X00 - 8 bits Read Only */
#define HDR 0X0E     /* Header Type Register - Default Value 0X00 - 8 bits Read Only */
#define APBASE 0X10    /* Aperture Base Configuration Register - Default Value 0X00000008 - 32 bits */
#define APBASE_VAL 0X00000008    /* Aperture Base Configuration Register Value - 32 bits */
#define SVID 0X2C    /* Subsystem Vendor ID - Default Value 0X0000 - 16 bits */
#define SVID_VAL 0X0000    /* Subsystem Vendor ID Value - 16 bits */
#define SID 0X2E    /* Subsystem ID - Default Value 0X0000 - 16 bits */
#define SID_VAL 0X0000    /* Subsystem ID Value - 16 bits */
#define CAPPTR 0X34     /* Capablities Pointer - Default Value 0X40 - 8 bits Read Only */
#define RRBAR 0X48    /* Register Range Base Address Register - Default Value 0X00000000 - 32 bits */
#define RRBAR_VAL 0X00000000    /* Register Range Base Address Register Value - 32 bits */
#define GCC0 0X50    /* GMCH Control Register #0 - Default Value 0XA072 - 16 bits */
#define GCC0_VAL 0XA072    /* GMCH Control Register #0 Value - 16 bits */
#define GCC1 0X52    /* GMCH Control Register #1 - Default Value 0X0000 - 16 bits */
#define GCC1_VAL 0X0030    /* GMCH Control Register #1 Value - 16 bits */
#define FDHC 0X58    /* Fixed DRAM Hole Control Register - Default Value 0X00 - 8 bits */
#define FDHC_VAL 0X00    /* Fixed DRAM Hole Control Register Value - 8 bits */
#define PAM0 0x59     /* Programable Attribute Map Register #0 - Default Value 0X00 - 8 bits */
#define PAM0_VAL 0x30     /* Programable Attribute Map Register #0 Value - 8 bits */
#define PAM1 0x5A     /* Programable Attribute Map Register #1 - Default Value 0X00 - 8 bits */
#define PAM1_VAL 0x33     /* Programable Attribute Map Register #1 Value - 8 bits */
#define PAM2 0x5B     /* Programable Attribute Map Register #2 - Default Value 0X00 - 8 bits */
#define PAM2_VAL 0x33     /* Programable Attribute Map Register #2 Value - 8 bits */
#define PAM3 0x5C     /* Programable Attribute Map Register #3 - Default Value 0X00 - 8 bits */
#define PAM3_VAL 0x33     /* Programable Attribute Map Register #3 Value - 8 bits */
#define PAM4 0x5D     /* Programable Attribute Map Register #4 - Default Value 0X00 - 8 bits */
#define PAM4_VAL 0x33     /* Programable Attribute Map Register #4 Value - 8 bits */
#define PAM5 0x5E     /* Programable Attribute Map Register #5 - Default Value 0X00 - 8 bits */
#define PAM5_VAL 0x33     /* Programable Attribute Map Register #5 Value - 8 bits */
#define PAM6 0x5F     /* Programable Attribute Map Register #6 - Default Value 0X00 - 8 bits */
#define PAM6_VAL 0x33     /* Programable Attribute Map Register #6 Value - 8 bits */
#define DRB0 0X60     /* DRAM Row Boundary Register #0 - Default Value 0X00 - 8 bits */
#define DRB0_VAL 0X00     /* DRAM Row Boundary Register #0 Value - 8 bits */
#define DRB1 0X61     /* DRAM Row Boundary Register #1 - Default Value 0X00 - 8 bits */
#define DRB1_VAL 0X00     /* DRAM Row Boundary Register #1 Value - 8 bits */
#define DRB2 0X62     /* DRAM Row Boundary Register #2 - Default Value 0X00 - 8 bits */
#define DRB2_VAL 0X04     /* DRAM Row Boundary Register #2 Value - 8 bits */
#define DRB3 0X63     /* DRAM Row Boundary Register #3 - Default Value 0X00 - 8 bits */
#define DRB3_VAL 0X04     /* DRAM Row Boundary Register #3 Value - 8 bits */
#define DRA0 0X70     /* DRAM Row Attribute Register #0 - Default Value 0XFF - 8 bits */
#define DRA0_VAL 0XFF     /* DRAM Row Attribute Register #0 Value - 8 bits */
#define DRA1 0X71     /* DRAM Row Attribute Register #1 - Default Value 0XFF - 8 bits */
#define DRA1_VAL 0XF1     /* DRAM Row Attribute Register #1 Value - 8 bits */
#define DRT	0X78     /* DRAM Timing Register - Default Value 0X00000010 - 32 bits */
#define DRT_VAL 0X00000010     /* DRAM Timing Register Value 0X00000010 - 32 bits */
#define DRC	0X7C     /* DRAM Controller Mode Register - Default Value 0X00000000 - 32 bits */
#define DRC_VAL 0X00000270     /* DRAM Controller Mode Register Value - 32 bits */
#define DTC	0X8C     /* DRAM Throttling Control Register - Default Value 0X0000_0000 - 32 bits */
#define DTC_VAL 0X0000_0000     /* DRAM Throttling Control Register Value - 32 bits */
#define SMRAM 0X90   /* System Management RAM Control Register - Default Value 0X02 - 8 bits */
#define SMRAM_VAL 0X02   /* System Management RAM Control Register Value - 8 bits */
#define ESMRAMC 0X91 /* Extended System Management RAM Control Register - Default Value 0X38 - 8 bits */
#define ESMRAMC_VAL 0X38 /* Extended System Management RAM Control Register Value - 8 bits */
#define ERRSTS 0X92    /* Error Status Register - Default Value 0X0000 - 16 bits */
#define ERRSTS_VAL 0X0000    /* Error Status Register - 16 bits */
#define ERRCMD 0X94    /* Error Command Register - Default Value 0X0000 - 16 bits */
#define ERRCMD_VAL 0X0000    /* Error Command Register - 16 bits */
#define APSIZE 0XB4     /* Apterture Size - Default Value 0X00 - 8 bits */
#define APSIZE_VAL 0X00     /* Apterture Size Value - 8 bits */
#define ATTBASE 0XB8     /* Aperture Translation Table Base Register - Default Value 0X00000000 - 32 bits */
#define ATTBASE_VAL 0X00000000     /* Aperture Translation Table Base Register Value - 32 bits */
#define BUFF_SC0 0XEC     /* System Memory Buffer Strength Control Register #0 - Default Value 0X00000000 - 32 bits */
#define BUFF_SC0_VAL 0X0000491B     /* System Memory Buffer Strength Control Register #0 Value - 32 bits */
#define BUFF_SC1 0XED     /* System Memory Buffer Strength Control Register #1 - Default Value 0X00000000 - 32 bits */
#define BUFF_SC1_VAL 0X00009B49     /* System Memory Buffer Strength Control Register #1 Value - 32 bits */
#define BUFF_SC2 0XEE     /* System Memory Buffer Strength Control Register #2 - Default Value 0X00000000 - 32 bits */
#define BUFF_SC2_VAL 0X0000FC9B     /* System Memory Buffer Strength Control Register #2 Value - 32 bits */
#define BUFF_SC3 0XEF     /* System Memory Buffer Strength Control Register #3 - Default Value 0X00000000 - 32 bits */
#define BUFF_SC3_VAL 0X000014FC     /* System Memory Buffer Strength Control Register #3 Value - 32 bits */



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