[LinuxBIOS] GA-M57SLI-S4 dual bios pins was Re: New with a GA-M57SLI-S4

ST st at iss.tu-darmstadt.de
Thu Mar 29 00:23:12 CEST 2007

Hi Peter, Stefan, Corey, Jose
> Chip pin = (37-yourpin) mod 32
Unfortunately i counted clockwise while the std pin numeration is 
counter-clockwise. This makes the pinsfunctions somehow weird and your work 
unfortunately moot... but you managed to motivate me to take a closer 
look :-).

Bios Pins       connected to			True Pin(tm)
1               1,2				4	A8,GPI2
2               2,1				3	A9,GPI3
3               3				2	RST#
4               ?				1	NC
5               5				32	VCC
6               6				31	R/C# CLK
7               7,WP_BIOS_2,T13			30	A10,GPI4

8               8				29	IC
9               9,WP_BIOS_2,T13			28	NC  <-Error?
10              ?				27	NC
11              ?				26	NC
12              12,WP_BIOS_2,T13		25	VCC <- Error?
13              				24	OE#,Init# <- nice
14              14,BT_PCI_2			23	WE#,LFrame,FWH4
15              ?				22	NC
16              ?				21	I/O7
17              ?				20	I/O6
18              ?				19	I/O5
19              19,WP_BIOS_2,T13		18	I/O4 <-Error?
20              20				17	I/O3,LAD3,FWH3	
21              21,WP_BIOS_2,T13		16	GND <-error?
22              22				15	I/O2,LAD2,FWH2
23              23				14	I/O1,LAD1,FWH1
24              24				13	I/O0,LAD0,FWH0
25              ?				12	A0,RES,ID0
26              ?				11	A1,RES,ID1
27              ?				10	A2,RES,ID2
28              ?				9	A3,RES,ID3
29              29				8	A4,TBL#,TBL#
30              30,WP_BIOS_1			7	A5,WP# <-makes sense
31              31,WP_BIOS_2,T13		6	A6,GPI0,GPI0
32              32,WP_BIOS_2,T13		5	A7,GPI1,GPI1

So according to my great connection list VCC is connected to GND. Ouch, who 
has designed this MB 8-). Oh wait... Jose could you do me a favor and recheck 
these lines with error? (Btw. our listing of the not connected pins is 
identical to mine). Especially the T1 or T2 pin and WP_BIOS connections.

> TBL is top boot block protection. 
This doesn't seem to connect to any of the jumpers.
> WP is write protection for the 
> entire chip except the top boot block....
> which supports your 
> theory! :)

> Also, what are T22 and T12?
Please see: 

These are open pins which might be transistors but are only Three open pins 
each. Between the PCIex1 sockets and the flash chips.
> > T13,T23 and WP_BIOS_2 are connected.
Theres some error in there. I'm not sure. But WP# is active low so, at least 
WP_BIOS_2 should be GND or s.t. like that?

> All pins/pads you marked with ? are either N/C (not connected) or RES
> (reserverd) on the chip and can be ignored for booting purposes.
Yeah, i think there is not to much doubt. The only thing (beside my obvious 
error i made somewhere with the VCC pin). The fact that ID0-ID3 are not 
connected pins seems to lie in the fact that these are the identification 
inputs for the chips. This makes multiple FWH Chips possible. WE,LFRAME,FWH4 
is connected to the jumper PCI_BT. Could that mean s.t. like PCI boot or is 
this also write protection? It would be nice if this jumper could control WE 
for each chip somehow, but i doubt it.

Pins I/O4-I/O6 seem to be unused. Which means that the chip is not used in A/A 
Mux mode. Thus the A6-A9 pins or better the GPIO0-GPI4 pins are also not 
used. I think they are all pulled to ground. Which leaves us with no unknown 
pins for both sockets?

Open questions:
* How can writing to only one chip be realized?
* Are these lower open pads above Q4 and R102 really not connected? Somehow i 
think these should be the transistors for controlling the write pins of these 

Good night

PS: I haven't taken a closer look at the patent.

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