[LinuxBIOS] r324 - LinuxBIOSv3/arch/x86

[svn at openbios.org]

Author: stepan
Date: 2007-05-19 10:47:42 +0200 (Sat, 19 May 2007)
New Revision: 324

Modified:
   LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S
Log:
small fix (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S
===================================================================
--- LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S	2007-05-19 08:44:14 UTC (rev 323)
+++ LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S	2007-05-19 08:47:42 UTC (rev 324)
@@ -32,8 +32,8 @@
 #include "macros.h"
 #include <amd_geodelx.h>
 
-#define	LX_STACK_BASE		CONFIG_DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
-#define	LX_STACK_END		LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-4)
+#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define	LX_STACK_END		LX_STACK_BASE+(DCACHE_RAM_SIZE-4)
 
 #define	LX_NUM_CACHELINES	0x080	/* there are 128lines per way */
 #define	LX_CACHELINE_SIZE	0x020	/* there are 32bytes per line */
@@ -246,7 +246,7 @@
 	xorl	%esi, %esi
 	xorl	%ebp, %ebp
 
-	/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
+	/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
 	/* remember,  there is NO stack yet... */
 
 	/* Tell cache we want to fill WAY 0 starting at the top */