[LinuxBIOS] r2700 - trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb

[svn at openbios.org]

Author: uwe
Date: 2007-05-27 23:43:58 +0200 (Sun, 27 May 2007)
New Revision: 2700

Modified:
   trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h
Log:
Init for the Intel 82371EB southbridge: make all ROM/BIOS regions
accessible (but not writable), so that reading/loading a payload
from that area can work (for instance).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c	2007-05-26 13:56:34 UTC (rev 2699)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c	2007-05-27 21:43:58 UTC (rev 2700)
@@ -18,12 +18,42 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+/* Datasheet:
+ *   - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
+ *   - URL: http://www.intel.com/design/intarch/datashts/290562.htm
+ *   - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
+ *   - Order Number: 290562-001
+ */
+
+#include <console/console.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include "i82371eb.h"
 
+/**
+ * Enable access to all BIOS regions. Do not enable write access to the ROM.
+ *
+ * @param dev TODO
+ */
 void i82371eb_enable(device_t dev)
 {
-	/* TODO. */
+	uint16_t reg;
+
+	/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
+	 *            FFF00000-FFF7FFFF are forwarded to ISA).
+	 * Set bit 7: Extended BIOS Enable (PCI master accesses to
+	 *            FFF80000-FFFDFFFF are forwarded to ISA).
+	 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
+	 *            the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
+	 *            of 1 Mbyte, or the aliases at the top of 4 Gbyte
+	 *            (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
+	 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
+	 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
+	 */
+
+	reg = pci_read_config16(dev, XBCS);
+	reg |= 0x2c0;
+	pci_write_config16(dev, XBCS, reg);
 }
 
 struct chip_operations southbridge_intel_i82371eb_ops = {

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h	2007-05-26 13:56:34 UTC (rev 2699)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h	2007-05-27 21:43:58 UTC (rev 2700)
@@ -25,6 +25,8 @@
 
 #include "chip.h"
 
+#define XBCS		0x4e	/* X-Bus Chip Select register */
+
 void i82371eb_enable(device_t dev);
 
 #endif