From info at coresystems.de  Thu Nov  1 00:16:40 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 01 Nov 2007 00:16:40 +0100
Subject: [LinuxBIOS] r2922 build service
Message-ID: <E1InMng-0005Px-FR@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2922 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Use the preferred order of 'static const' instead of 'const static'.
This is the common style in both Linux as well as in LinuxBIOS.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=hdama&vendor=arima
Compilation of gigabyte:ga_2761gxdk is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=ga_2761gxdk&vendor=gigabyte
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=dk8x&vendor=iwill
Compilation of newisys:khepri is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2922&device=khepri&vendor=newisys


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From info at coresystems.de  Thu Nov  1 01:11:00 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 01 Nov 2007 01:11:00 +0100
Subject: [LinuxBIOS] r2923 build service
Message-ID: <E1InNeG-0003dK-Ba@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2923 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Use the preferred order of 'static const' instead of 'const static'.
This is the common style in both Linux as well as in LinuxBIOS.

Self-ack as this is pretty trivial and a similar patch was already acked.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=hdama&vendor=arima
Compilation of gigabyte:ga_2761gxdk is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=ga_2761gxdk&vendor=gigabyte
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=dk8x&vendor=iwill
Compilation of newisys:khepri is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2923&device=khepri&vendor=newisys


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From joe at smittys.pointclark.net  Thu Nov  1 01:43:25 2007
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Wed, 31 Oct 2007 20:43:25 -0400
Subject: [LinuxBIOS] GRUB 2 and LinuxBIOS
In-Reply-To: <20071031223713.GA3901@thorin>
References: <20071031223713.GA3901@thorin>
Message-ID: <20071031204325.oa7tmpbnac8s4c8s@www.smittys.pointclark.net>

Quoting Robert Millan <rmh at aybabtu.com>:

>
> Hi
>
> I'm glad to announce that as of current CVS, GRUB 2 officialy supports
> LinuxBIOS.  There are still a few remaining issues, but most of the meat is
> there right now.
>
> Please could someone update the wiki?  (or give me perms to do it)
>
> Thanks!
>
> --
> Robert Millan
>
> <GPLv2> I know my rights; I want my phone call!
> <DRM> What use is a phone call, if you are unable to speak?
> (as seen on /.)
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>
Do you mean GRUB2 as a Payload? If so, SWEET!!
Great work.

Thanks - Joe



From rminnich at gmail.com  Thu Nov  1 01:47:46 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 31 Oct 2007 17:47:46 -0700
Subject: [LinuxBIOS] GRUB 2 and LinuxBIOS
In-Reply-To: <20071031223713.GA3901@thorin>
References: <20071031223713.GA3901@thorin>
Message-ID: <13426df10710311747s159f3706j32c54c1f3aa70284@mail.gmail.com>

Robert, would grub2 under linuxbios be able to boot QNX?

thanks

ron



From stepan at coresystems.de  Thu Nov  1 13:04:33 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Nov 2007 13:04:33 +0100
Subject: [LinuxBIOS] GRUB 2 and LinuxBIOS
In-Reply-To: <20071031223713.GA3901@thorin>
References: <20071031223713.GA3901@thorin>
Message-ID: <4729C0D1.6000107@coresystems.de>

Robert Millan wrote:
> Hi
>
> I'm glad to announce that as of current CVS, GRUB 2 officialy supports
> LinuxBIOS.  There are still a few remaining issues, but most of the meat is
> there right now.
>   

Oh thank you very much for merging Patrick Georgi's work. I think he did
a really great job.

What about
- the outstanding fixes for grub-mkimage
- linuxbios table support
- proper serial console handling
- larfs support
- (rom) support?

> Please could someone update the wiki?  (or give me perms to do it)
>
>   
Yes, we'll be glad to do this as soon as LinuxBIOS is properly supported
by GRUB2.


Thanks for working so hard on Patricks code to make it happen.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From rmh at aybabtu.com  Thu Nov  1 13:06:23 2007
From: rmh at aybabtu.com (Robert Millan)
Date: Thu, 1 Nov 2007 13:06:23 +0100
Subject: [LinuxBIOS] GRUB 2 and LinuxBIOS
In-Reply-To: <13426df10710311747s159f3706j32c54c1f3aa70284@mail.gmail.com>
References: <20071031223713.GA3901@thorin>
	<13426df10710311747s159f3706j32c54c1f3aa70284@mail.gmail.com>
Message-ID: <20071101120623.GB13876@thorin>

On Wed, Oct 31, 2007 at 05:47:46PM -0700, ron minnich wrote:
> Robert, would grub2 under linuxbios be able to boot QNX?

I'm not familiar with QNX, but it seems like on grub-pc it's loaded via
chainloader.  Normaly this means it uses BIOS calls; this is not the case
here?

In that case it would make sense to enable the chainloader command.  I was
under the impression it would only be useful on BIOS.

-- 
Robert Millan

<GPLv2> I know my rights; I want my phone call!
<DRM> What use is a phone call, if you are unable to speak?
(as seen on /.)



From stepan at coresystems.de  Thu Nov  1 13:09:13 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Nov 2007 13:09:13 +0100
Subject: [LinuxBIOS] GRUB 2 and LinuxBIOS
In-Reply-To: <20071031204325.oa7tmpbnac8s4c8s@www.smittys.pointclark.net>
References: <20071031223713.GA3901@thorin>
	<20071031204325.oa7tmpbnac8s4c8s@www.smittys.pointclark.net>
Message-ID: <4729C1E9.9090009@coresystems.de>

joe at smittys.pointclark.net wrote:

> Do you mean GRUB2 as a Payload? If so, SWEET!!
> Great work.
>
>   
Yes, thanks to Patrick Georgi who did this as a Google Summer of Code
project.

Kudos to him for the great job. Without Patrick, LinuxBIOS wouldn't be
where it is now.

See the official GRUB2 on LinuxBIOS page for information about it, it's
been there for a couple of months:

    http://linuxbios.org/GRUB2


Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From my_tsai at sis.com  Thu Nov  1 13:24:23 2007
From: my_tsai at sis.com (Morgan Tsai /SiS)
Date: Thu, 1 Nov 2007 20:24:23 +0800
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
References: <006b01c8058d$38dc52f0$0200a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710030928160.3653@bigred.russwhit.org>
	<001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>
	<20071004025851.GA32267@greenwood>
	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
Message-ID: <005501c81c82$23b72330$0200a8c0@sis.com.tw>

Change Log:

1. Add integrated VGA bios within redistributed notice,
please help to put '6330VGA.rom' into targets/gigabyte/ga_2761gxdk/
2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in src/include/device/pci_ids.h
4. Trim trailing spaces for all files



Signed-off-by: Morgan Tsai <my_tsai at sis.com>

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From joe at smittys.pointclark.net  Thu Nov  1 14:24:53 2007
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Thu, 01 Nov 2007 09:24:53 -0400
Subject: [LinuxBIOS] GRUB 2 and LinuxBIOS
In-Reply-To: <4729C1E9.9090009@coresystems.de>
References: <20071031223713.GA3901@thorin>
	<20071031204325.oa7tmpbnac8s4c8s@www.smittys.pointclark.net>
	<4729C1E9.9090009@coresystems.de>
Message-ID: <20071101092453.4plol92jokgcwck0@www.smittys.pointclark.net>

Quoting Stefan Reinauer <stepan at coresystems.de>:

> joe at smittys.pointclark.net wrote:
>
>> Do you mean GRUB2 as a Payload? If so, SWEET!!
>> Great work.
>>
>>
> Yes, thanks to Patrick Georgi who did this as a Google Summer of Code
> project.
>
> Kudos to him for the great job. Without Patrick, LinuxBIOS wouldn't be
> where it is now.
>
> See the official GRUB2 on LinuxBIOS page for information about it, it's
> been there for a couple of months:
>
>     http://linuxbios.org/GRUB2
>
>
> Stefan
>
Oh, I have been following the page on the wiki, but I was under the  
asumption that is was still being developed:-)


Thanks - Joe



From joe at smittys.pointclark.net  Thu Nov  1 14:30:11 2007
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Thu, 01 Nov 2007 09:30:11 -0400
Subject: [LinuxBIOS] mptable util not working?
Message-ID: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>

Hello,
I am having prolems with the mptable utility. I keeps telling me "MP  
FPS NOT found, suggest trying -grope option!!!". If I try the grope  
option it still spits out the same message. Am I doing something wrong?

Thanks - Joe



From myles at pel.cs.byu.edu  Thu Nov  1 15:32:20 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Thu, 1 Nov 2007 07:32:20 -0700
Subject: [LinuxBIOS] Patch quality
In-Reply-To: <20071030170347.GA12444@cosmic.amd.com>
References: <47230218.70605@assembler.cz> <20071028015838.23972.qmail@stuge.se>
	<13426df10710280906k3ec894bcu594da0998f7ea9e3@mail.gmail.com>
	<20071029155738.GE11779@cosmic.amd.com>
	<13426df10710291551w6f2a453fn88fe4ecd7258037d@mail.gmail.com>
	<20071030012850.GA24090@coresystems.de> <47268EC7.9080202@gmail.com>
	<13426df10710291856k6a5f5f5cne391cce72e8cfb96@mail.gmail.com>
	<20071030022453.GA21022@coresystems.de>
	<20071030170347.GA12444@cosmic.amd.com>
Message-ID: <2831fecf0711010732x5ed72f3avb60a4d67b0853e61@mail.gmail.com>

On 10/30/07, Jordan Crouse <jordan.crouse at amd.com> wrote:
> On 30/10/07 03:24 +0100, Stefan Reinauer wrote:
> > An important issue will be to get the code compiling. I was not
> > successful doing so due to the old ld overlapping sections friend.
>
> We've seen this before -  Whats happening here is that the ld script
> snippet for .id is going into the ld script after the snippet for .reset,
> so to LD, the current pointer appears to jump backwards, and it can't figure
> out the math correctly.  The immediately work around is to re-arrange
> the order of the .id and the .reset snippets in the script.  I believe this
> was fixed in later versions of ld - I can't get it to happen on my trusty
> Ubuntu Gutsy box.

When I get this error, it is because my ROM_IMAGE_SIZE is set too
small. Increasing it fixes the problem for me.

Myles

> Jordan
>
> --
> Jordan Crouse
> Systems Software Development Engineer
> Advanced Micro Devices, Inc.
>
>
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>



From svn at openbios.org  Thu Nov  1 16:15:14 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  1 Nov 2007 16:15:14 +0100
Subject: [LinuxBIOS] r2924 - trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c
Message-ID: <mailman.818.1355071194.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2007-11-01 16:15:14 +0100 (Thu, 01 Nov 2007)
New Revision: 2924

Modified:
   trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
Log:
This patch is a trivial response to a good comment from Uwe, so I am
self-acking before it gets lost.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	2007-10-31 22:26:51 UTC (rev 2923)
+++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	2007-11-01 15:15:14 UTC (rev 2924)
@@ -86,7 +86,7 @@
 	[SPD_tRRD] = 10,
 };
 
-static u8 spd_read_byte(unsigned device, unsigned address)
+static u8 spd_read_byte(u8 device, u8 address)
 {
 	print_debug("spd_read_byte dev ");
 	print_debug_hex8(device);




From jordan.crouse at amd.com  Thu Nov  1 16:36:56 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 1 Nov 2007 09:36:56 -0600
Subject: [LinuxBIOS] GRUB 2 and LinuxBIOS
In-Reply-To: <4729C0D1.6000107@coresystems.de>
References: <20071031223713.GA3901@thorin>
 <4729C0D1.6000107@coresystems.de>
Message-ID: <20071101153656.GF12393@cosmic.amd.com>

On 01/11/07 13:04 +0100, Stefan Reinauer wrote:
> Robert Millan wrote:
> > Please could someone update the wiki?  (or give me perms to do it)
> >
> >   
> Yes, we'll be glad to do this as soon as LinuxBIOS is properly supported
> by GRUB2.

When that happens, can I talk somebody into adding grub2 as a
buildROM payload too?

Jordan

---
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From jordan.crouse at amd.com  Thu Nov  1 16:38:59 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 1 Nov 2007 09:38:59 -0600
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <005501c81c82$23b72330$0200a8c0@sis.com.tw>
References: <001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>
	<20071004025851.GA32267@greenwood>
	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw> <4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
Message-ID: <20071101153859.GG12393@cosmic.amd.com>

Morgan -

Thank you very much!   We'll get this in immediately.

Stefan - can you put the .rom and the copyright notice somewhere
wgetable on linuxbios.org, and I'll teach buildROM how to download 
them.

Jordan

On 01/11/07 20:24 +0800, Morgan Tsai /SiS wrote:
> Change Log:
>
> 1. Add integrated VGA bios within redistributed notice,
> please help to put '6330VGA.rom' into targets/gigabyte/ga_2761gxdk/
> 2. Rename sisnb.c to sis761.c
> 3. Delete many mis-definition for sis device in 
> src/include/device/pci_ids.h
> 4. Trim trailing spaces for all files


>
>
> Signed-off-by: Morgan Tsai <my_tsai at sis.com>
>



> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From myles at pel.cs.byu.edu  Thu Nov  1 17:00:50 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Thu, 1 Nov 2007 09:00:50 -0700
Subject: [LinuxBIOS] [PATCH] Add support for a 64-bit target for Serengeti
	Cheetah
Message-ID: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>

I think this is very close.  There are a few things to work out that
I'd like help with.

1. If I set a variable like UCLIBC_VER in the
config/platforms/serengeti_cheetah-x86_64.conf file, it doesn't make
it to uclibc.mk
2. Could someone that has the actual hardware see if you need to
comment out soft_resest_x in cache_as_ram_auto.c, or if that's a
SimNow issue? (LinuxBIOS enters an infinite loop resetting itself if
the reset is not commented out)

Thanks,
Myles

Here's the change log for the patch
added config/platforms/serengeti_cheetah-x86_64.conf
added PLATFORM_SERENGETI_CHEETAH_64 to config/platforms/Config.in
changed config/platforms/serengeti_cheetah.conf to point to its own
linuxbios make file instead of generic-linuxbios.mk
changed scripts/Makefile.lab to use bzImage instead of vmlinux for
mkelfimage so that it works on x86_64
updated Build.settings to include a UCLIBC_LOADER variable for 64-bit
removed the magic number from bin/checkrom.sh (Was LinuxBIOS version
and platform dependent) and changed it to an informational message
added a kernel config file and .mk file
changed packages/kernel/kernel.inc to be platform aware
changed packages/busybox/busybox.mk to be platform aware
added a defconfig for busybox with 64-bit uClibc
added a defconfig for uClibc 64-bit
added a uClibc version variable UCLIBC_VER to uclibc.mk (0.9.28
doesn't have resolve.S for x86_64)
changed "Building target config file" to "Building target" because it
is executing ./buildtarget
added patches for Config.lb for serengeti_cheetah-payload and
serengeti_cheetah-lab
added serengeti_cheetah.mk which
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From info at coresystems.de  Thu Nov  1 17:10:09 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Thu, 01 Nov 2007 17:10:09 +0100
Subject: [LinuxBIOS] r2924 build service
Message-ID: <E1InccT-0003t6-Su@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "rminnich" checked in revision 2924 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
This patch is a trivial response to a good comment from Uwe, so I am
self-acking before it gets lost.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=hdama&vendor=arima
Compilation of gigabyte:ga_2761gxdk is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=ga_2761gxdk&vendor=gigabyte
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=dk8x&vendor=iwill
Compilation of newisys:khepri is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2924&device=khepri&vendor=newisys


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From myles at pel.cs.byu.edu  Thu Nov  1 17:13:30 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Thu, 1 Nov 2007 09:13:30 -0700
Subject: [LinuxBIOS] [PATCH] Add support for a 64-bit target for
	Serengeti Cheetah
In-Reply-To: <2831fecf0711010910i1fa32bc7j94c1fce0f9711fd4@mail.gmail.com>
References: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
	<2831fecf0711010910i1fa32bc7j94c1fce0f9711fd4@mail.gmail.com>
Message-ID: <2831fecf0711010913l7c55df96xe100ae5fa4f5b047@mail.gmail.com>

Here is the changelog again in case everyone's mailer mangled it as
badly as mine did.

> I think this is very close.  There are a few things to work out that
> I'd like help with.
>
> 1. If I set a variable like UCLIBC_VER in the
> config/platforms/serengeti_cheetah-x86_64.conf file, it doesn't make
> it to uclibc.mk

> 2. Could someone that has the actual hardware see if you need to
> comment out soft_resest_x in cache_as_ram_auto.c, or if that's a
> SimNow issue? (LinuxBIOS enters an infinite loop resetting itself if
> the reset is not commented out)

>
> Thanks,
> Myles
>
> Here's the change log for the patch

> added config/platforms/serengeti_cheetah-x86_64.conf

> added PLATFORM_SERENGETI_CHEETAH_64 to config/platforms/Config.in

> changed config/platforms/serengeti_cheetah.conf to point to its own linuxbios make file instead of generic-linuxbios.mk

> changed scripts/Makefile.lab to use bzImage instead of vmlinux for

> mkelfimage so that it works on x86_64

> updated Build.settings to include a UCLIBC_LOADER variable for 64-bit

> removed the magic number from bin/checkrom.sh (Was LinuxBIOS version and platform dependent) and changed it to an informational message

> added a kernel config file and .mk file

> changed packages/kernel/kernel.inc to be platform aware

> changed packages/busybox/busybox.mk to be platform aware

> added a defconfig for busybox with 64-bit uClibc

> added a defconfig for uClibc 64-bit

> added a uClibc version variable UCLIBC_VER to uclibc.mk (0.9.28 doesn't have resolve.S for x86_64)

> changed "Building target config file" to "Building target" because it is executing ./buildtarget

> added patches for Config.lb for serengeti_cheetah-payload and serengeti_cheetah-lab

> added serengeti_cheetah.mk

Sorry about the need to repost.
Myles



From myles at pel.cs.byu.edu  Thu Nov  1 17:35:50 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Thu, 1 Nov 2007 10:35:50 -0600
Subject: [LinuxBIOS] [PATCH] Add support for a 64-bit target for
	Serengeti Cheetah
In-Reply-To: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
References: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
Message-ID: <02d201c81ca5$437e4770$1223040a@chimp>


I forgot one more thing that I'd like help improving in buildrom:

I'd like to pass -j 6 to make to speed compilation (I added it to the kernel
makefile for the target), but if you pass it to the top-level makefile it
doesn't respect ordering.  Is there a way to have the top-level makefile
include a jobs setting without breaking the build?






From jordan.crouse at amd.com  Thu Nov  1 17:56:26 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 1 Nov 2007 10:56:26 -0600
Subject: [LinuxBIOS] Add support for a 64-bit target for Serengeti
	Cheetah
In-Reply-To: <02d201c81ca5$437e4770$1223040a@chimp>
References: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
	<02d201c81ca5$437e4770$1223040a@chimp>
Message-ID: <20071101165626.GC21220@cosmic.amd.com>

On 01/11/07 10:35 -0600, Myles Watson wrote:
> 
> I forgot one more thing that I'd like help improving in buildrom:
> 
> I'd like to pass -j 6 to make to speed compilation (I added it to the kernel
> makefile for the target), but if you pass it to the top-level makefile it
> doesn't respect ordering.  Is there a way to have the top-level makefile
> include a jobs setting without breaking the build?

-j should always be the number of cores on your system + 1.  But ensuring
that the code builds cleanly is the job of the system.  If we have out of
order issues with buildrom we can try to address them, but if we start
getting too deeply into respecting strict dependencies then we will very
quickly get overly complex.  My suggestion is to pass in -j independently
to each package so that you can get the speed advantage there.

This is yet another reason why I'm pushing so hard to move the LAB and kernel
compile out of buildrom and into something else like buildroot or Firmware
Linux or <insert favorite tool here>.  I don't know if we want buildROM to
be in the business of understanding how to build a distro - there are other
packages out there that do a better job of that.  Where buildROM comes in
useful is managing the juxtaposition of LinuxBIOS and its payloads.  So instead
of building the kernel & LAB distro, if buildrom can pass control to buildroot
or one of its friends, and then consume the resulting filesystem image and
turn it into an ELF.  

But until we get that working, I have no objection to passing -j <whatever>
into the various Makefiles.  We can make <whatever> a configurable option
in the advanced settings.

Jordan





From myles at pel.cs.byu.edu  Thu Nov  1 18:27:16 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Thu, 1 Nov 2007 11:27:16 -0600
Subject: [LinuxBIOS] Broken build for kexec-boot-loader on tyan s2891
In-Reply-To: <20071101165626.GC21220@cosmic.amd.com>
References: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
	<02d201c81ca5$437e4770$1223040a@chimp>
	<20071101165626.GC21220@cosmic.amd.com>
Message-ID: <02d301c81cac$72f1eff0$1223040a@chimp>

If I configure tyan_s2891 to have Linux As Bootloader and include the kexec
tools, the build fails. Here's the last bit of the build log

gcc --32 -c -o kexec/x86-setup-32.o kexec/x86-setup-32.S
cc1: error: unrecognized command line option "-f32"

Is this another place where there should be quotes around flags being passed
around?

Myles





From peter at stuge.se  Thu Nov  1 19:33:23 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Nov 2007 19:33:23 +0100
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <20071101153859.GG12393@cosmic.amd.com>
References: <20071004025851.GA32267@greenwood>
	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101153859.GG12393@cosmic.amd.com>
Message-ID: <20071101183323.30359.qmail@stuge.se>

On Thu, Nov 01, 2007 at 09:38:59AM -0600, Jordan Crouse wrote:
> Stefan - can you put the .rom and the copyright notice somewhere
> wgetable on linuxbios.org, and I'll teach buildROM how to download
> them.

Maybe we even want it committed?


//Peter



From dhbarr at gozelle.com  Thu Nov  1 19:36:29 2007
From: dhbarr at gozelle.com (David H. Barr)
Date: Thu, 1 Nov 2007 13:36:29 -0500
Subject: [LinuxBIOS] "Borrowed" plumage
Message-ID: <e8d467740711011136w7d71dbccm5a34227badc52586@mail.gmail.com>

I was doing some random surfing over lunch on the fine Gigabyte / SiS
/ AMD DTX board we've been so recently discussing, and ran across some
weird hits.

It's odd, they all redirect to
http://linuxbios.org/index.php/Desktops, but they're hosted at:

  img?zol?com?cn
  myarticle?enet?com?cn
  unlimitpc?com

My hunch is they're doing some sort of http 3xx redirection status
code to artificially inflate their content, but... probably not
important, it was simply something I stumbled across.


Regards,
-dhbarr.



From uwe at hermann-uwe.de  Thu Nov  1 20:07:37 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Nov 2007 20:07:37 +0100
Subject: [LinuxBIOS] Linking issues in v3...
In-Reply-To: <4727EF26.9000603@gmail.com>
References: <47278EDA.4030302@gmail.com> <20071030234125.GF19408@greenwood>
	<4727EF26.9000603@gmail.com>
Message-ID: <20071101190737.GA18188@greenwood>

Hi,

sorry for the delay.


On Tue, Oct 30, 2007 at 10:57:42PM -0400, Corey Osgood wrote:
> +#ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
> +#define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
> +
> +/* Note: need to be moved into dts */
> +#define SMBUS_IO_BASE		0x0f00 //from award bios
> +#define PMIO_BASE		0x0500 //might as well set this while we're here

Yep, sounds like the correct location.


> +
> +#define SMBHSTSTAT		SMBUS_IO_BASE + 0x0

Should probably be

#define SMBHSTSTAT           (SMBUS_IO_BASE + 0x0)

(just in case; same for the other entries)


> +#define SMBSLVSTAT		SMBUS_IO_BASE + 0x1
> +#define SMBHSTCTL		SMBUS_IO_BASE + 0x2
> +#define SMBHSTCMD		SMBUS_IO_BASE + 0x3
> +#define SMBXMITADD		SMBUS_IO_BASE + 0x4
> +#define SMBHSTDAT0		SMBUS_IO_BASE + 0x5
> +
> +/* Define register settings */
> +#define HOST_RESET 		0xff
> +#define READ_CMD		0x01	// 1 in the 0 bit of SMBHSTADD states to READ
> +
> +#define SMBUS_TIMEOUT		(100*1000*10)
> +
> +#define I2C_TRANS_CMD		0x40
> +#define CLOCK_SLAVE_ADDRESS	0x69
> +
> +#define SMBUS_DELAY()		inb(0x80)
> +
> +
> +/* IDE specific bits */
> +#define IDE_MODE_REG		0x09
> +#define IDE0_NATIVE_MODE	(1 << 0)
> +#define IDE1_NATIVE_MODE	(1 << 2)
> +#define CHANNEL_ENABLE_REG	0x40
> +#define ENABLE_IDE0		(1 << 0)
> +#define ENABLE_IDE1		(1 << 1)
> +
> +/* These are default addresses according to Via */
> +/* Again, should really be in the dts, with a big warning "Don't touch unless 
> + * you know what you're doing" */
> +#define IDE0_DATA_ADDR		0x1f0
> +#define IDE0_CONTROL_ADDR	0x3f4
> +#define IDE1_DATA_ADDR		0x170
> +#define IDE1_CONTROL_ADDR	0x370

Yes.


> +
> +/* By Award default, Via default is 0xCC0 */
> +#define BUS_MASTER_ADDR		0xfe00
> +
> +#endif /* SOUTHBRIDGE_VIA_VT8237R_VT8237R_H */

One note though: Please try to merge your VT8237R code/changes into v2
first. This file (and smbus_initram.c and maybe other files) seems to differ
in various (smaller or bigger) ways from the v2 code, and we should try to avoid
two diverging code-"streams" in v2/v3.

Please post a patch against v2 so we can get one "mainstream" working
version of the VT8237R code, then base your v3 port on the committed
v2 version.


> Index: southbridge/via/vt8237r/stage1.c
> ===================================================================
> --- southbridge/via/vt8237r/stage1.c	(revision 0)
> +++ southbridge/via/vt8237r/stage1.c	(revision 0)
> @@ -0,0 +1,26 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007

Missing name.


> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <lib.h>
> +
> +void vt8237r_stage1(void)
> +{
> +	/* Nothing to do for the moment, but there will be later */
> +}

OK, but let's add the file later then. You can leave the Makefile
snippet for stage1.c in there (commented) for now.


> Index: southbridge/via/vt8237r/debug.c
> ===================================================================
> --- southbridge/via/vt8237r/debug.c	(revision 0)
> +++ southbridge/via/vt8237r/debug.c	(revision 0)
> @@ -0,0 +1,12 @@
> +static void dump_dev(device_t dev)
> +{
> +	int i,j;
> +	
> +	for(i = 0; i < 256; i += 16) {
> +		printk_debug("0x%x: ", i);
> +		for(j = 0; j < 16; j++) {
> +			printk_debug("%02x ", pci_read_config8(dev, i+j));
> +		}
> +		printk_debug("\n");
> +	}
> +}

Nah, please drop this file. If it's really needed it should go in some
other *.c file here, or in some global place.


> Index: southbridge/via/vt8237r/dts
> ===================================================================
> --- southbridge/via/vt8237r/dts	(revision 0)
> +++ southbridge/via/vt8237r/dts	(revision 0)
> @@ -0,0 +1,35 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>

Not quite, unless you got renamed recently ;)


> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +{
> +	constructor = "vt8237r_constructors";
> +
> +	/* Interrupt enables for LPC bus. Each bit is an IRQ 0-15. */
> +	lpc_serirq_enable = "0";
> +
> +	/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
> +	lpc_serirq_polarity = "0";
> +
> +	/* 0:continuous 1:quiet */
> +	lpc_serirq_mode = "0";
> +
> +	/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
> +	enable_gpio_int_route = "0";
> +};

Yep, nice.


> Index: southbridge/via/vt8237r/Makefile
> ===================================================================
> --- southbridge/via/vt8237r/Makefile	(revision 0)
> +++ southbridge/via/vt8237r/Makefile	(revision 0)
> @@ -0,0 +1,28 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2007 coresystems GmbH
> +## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)

Also not quite, but, well, doesn't really matter anyway.


> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237R),y)
> +
> +STAGE2_CHIPSET_OBJ += $(obj)/southbridge/via/vt8237r/vt8237r.o
> +
> +STAGE0_CHIPSET_OBJ += $(obj)/southbridge/via/vt8237r/stage1.o

We have STAGE0 but stage1.o which will confuse everybody. Not related to
this patch, but we should fix it later...


> +
> +endif
> Index: southbridge/via/vt8237r/smbus_initram.c
> ===================================================================
> --- southbridge/via/vt8237r/smbus_initram.c	(revision 0)
> +++ southbridge/via/vt8237r/smbus_initram.c	(revision 0)
> @@ -0,0 +1,179 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <console.h>
> +#include <io.h>
> +#include <device/pci.h>
> +#include "vt8237r.h"

See above, this file seems to diverge from what's in v2 currently.


> +
> +/**
> + * Enable the SMBus.
> + *
> + * Basically, set the enable bit in the controller. This can be (and is)
> + * called multiple times.
> + */
> +static void smbus_init(void)
> +{
> +	struct device *dev;
> +
> +	/* Power management controller */
> +	/* This should work, but there are more important things to work on */
> +	/* dev = PCI_DEV(0, 0x11, 0); */
> +	
> +	dev = dev_find_device(0x1106, 0x3227, 0);
> +	
> +	if (dev->device != 0x3227)
> +	{
> +		/* This won't display text if enable_smbus() is before serial init */
> +		die("Power Managment Controller not found\n");
> +	}
> +	
> +	/* Set clock source */
> +	pci_write_config8(dev, 0x94, 0xa0);
> +	
> +	/* Write SMBus IO base to 0xd0 and enable SMBus */
> +	pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
> +	 
> +	/* Set to Award value */
> +	pci_write_config8(dev, 0xd2, 0x01);
> +	
> +	/* Make it work for I/O ...*/
> +	/* Note: the datasheet lists this register as read-only, but smbus 
> +	doesn't work without this. Weird... */
> +	pci_write_config16(dev, 0x04, 0x0001);
> +	
> +	/* Set the power management IO base while we're here */
> +	pci_write_config32(dev, 0x88, PMIO_BASE | 1 );
> +}
> +
> +static void smbus_print_error(unsigned char host_status_register, int loops)
> +{
> +	/* Check if there actually was an error */	
> +	if ((!host_status_register || host_status_register == 0x40 || 
> +		host_status_register == 0x42) && loops < SMBUS_TIMEOUT) return;
> +
> +	printk(BIOS_ERR, "smbus_error: 0x%02x\n", host_status_register);
> +	if (loops >= SMBUS_TIMEOUT) printk(BIOS_ERR, "SMBus Timout\n");
> +	if (host_status_register & (1 << 4)) 
> +		printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
> +	if (host_status_register & (1 << 3)) printk(BIOS_ERR, "Bus Error\n");
> +	if (host_status_register & (1 << 2)) printk(BIOS_ERR, "Device Error\n");
> +	if (host_status_register & (1 << 1)) 
> +		/* This isn't a real error... */
> +		printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
> +	if (host_status_register & (1 << 0)) printk(BIOS_ERR, "Host Busy\n");
> +}
> +
> +/**
> + * Wait for the SMBus controller to become ready.
> + *
> + * This isn't quite as fancy as some functions, but it does the trick.
> + *
> + * @param smbus_io_base The SMBus I/O base.
> + */
> +static void smbus_wait(u16 smbus_io_base)
> +{
> +	int loops;
> +	
> +	loops = 0;
> +	/* Yes, this is a mess, but it's the easiest way to do it */
> +	while ((inb(SMBHSTSTAT) & 1) && (loops <= SMBUS_TIMEOUT)) ++loops;
> +	smbus_print_error(inb(SMBHSTSTAT), loops);
> +}
> +
> +static void smbus_reset(void)
> +{
> +	outb(HOST_RESET, SMBHSTSTAT);
> +	/* Datasheet says we have to read to take ownership of SMBus */
> +	inb(SMBHSTSTAT);
> +}
> +
> +int smbus_read_byte(u32 device, u32 address)
> +{
> +	u32 val;
> +
> +	smbus_reset();
> +	/* clear host data port */
> +	outb(0x00, SMBHSTDAT0);
> +	SMBUS_DELAY();
> +	smbus_wait(SMBUS_IO_BASE);
> +
> +	/* actual addr to reg format */
> +	device = (device << 1);
> +	device |= 1;
> +	outb(device, SMBXMITADD);
> +	outb(address, SMBHSTCMD);
> +	/* start transaction, byte data read */
> +	outb(0x48, SMBHSTCTL);
> +
> +	SMBUS_DELAY();
> +
> +	smbus_wait(SMBUS_IO_BASE);
> +
> +	val = inb(SMBHSTDAT0);
> +
> +	smbus_reset();		/* probably don't have to do this, but it can't hurt */
> +	return val;		/* can I just "return inb(SMBHSTDAT0)"? */
> +}
> +
> +
> +/**
> + * Read a byte from the SPD. 
> + *
> + * For this chip, that is really just saying 'read a byte from SMBus'.
> + * So we use smbus_read_byte(). Nota Bene: leave this here as a function 
> + * rather than a #define in an obscure location. This function is called 
> + * only a few dozen times, and it's not performance critical. 
> + *
> + * @param device The device.
> + * @param address The address.
> + * @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
> + */
> +inline int spd_read_byte(u16 device, u8 address)
> +{
> +	return smbus_read_byte(device, address);
> +}
> +
> +/**
> + * Read a few bytes from smbus to confirm it's working.
> + *
> + * On some systems, it may take a long (or very long) time for smbus to 
> + * "warm up". This fixup will eventually cycle through possible dimm locations
> + * searching for a known bit of data, to confirm that smbus is ready to work.
> + *
> + * @param mem_controller The memory controller and spd addresses
> + */
> +static void smbus_fixup(void)
> +{
> +	int i;
> +	unsigned int byte = 0x00;
> +	/* SMBus reads fail for ~22 reads without some fixup */
> +	/* Read until we get the right data for a known byte */
> +	/* This method has one major flaw: it needs DDR2 in DIMM0 */
> +	printk(BIOS_DEBUG, "Waiting until SMBus ready");
> +	for(i = 0; i < SMBUS_TIMEOUT && byte != 0x08; i++) 
> +	{
> +		printk(BIOS_DEBUG, ".");
> +		byte = smbus_read_byte(0xa0, 2); //ctrl->channel[0], 2);
> +	}
> +	
> +	if (i >= SMBUS_TIMEOUT - 1) printk(BIOS_ERR, "-SMBus error!-\n");
> +	else printk(BIOS_DEBUG, "Done!\n");
> +}
> Index: Kconfig
> ===================================================================
> --- Kconfig	(revision 507)
> +++ Kconfig	(working copy)
> @@ -74,16 +74,22 @@
>  	boolean
>  config NORTHBRIDGE_INTEL_I440BXEMULATION
>  	boolean
> +config NORTHBRIDGE_VIA_CN700
> +	boolean
>  
>  # Southbridges:
>  config SOUTHBRIDGE_AMD_CS5536
>  	boolean
>  config SOUTHBRIDGE_INTEL_I82371EB
>  	boolean
> +config SOUTHBRIDGE_VIA_VT8237R
> +	boolean
>  
>  # Super I/Os:
>  config SUPERIO_WINBOND_W83627HF
>  	boolean
> +config SUPERIO_FINTEK_F71805F
> +	boolean

Yep.


>  
>  # Source all northbridge/southbridge/superio Kconfig files:
>  source northbridge/intel/i440bxemulation/Kconfig
> Index: include/device/pci_ids.h
> ===================================================================
> --- include/device/pci_ids.h	(revision 507)
> +++ include/device/pci_ids.h	(working copy)
> @@ -152,6 +152,24 @@
>  #define PCI_DEVICE_ID_AMD_CS5536_OTG		0x2097
>  #define PCI_DEVICE_ID_AMD_CS5536_B0_IDE		0x209A
>  
> +#define PCI_VENDOR_ID_VIA			0x1106
> +#define PCI_DEVICE_ID_CN700_0			0x0314
> +#define PCI_DEVICE_ID_CN700_1			0x1314
> +#define PCI_DEVICE_ID_CN700_2			0x2314
> +#define PCI_DEVICE_ID_CN700_3			0x3208
> +#define PCI_DEVICE_ID_CN700_4			0x4314
> +#define PCI_DEVICE_ID_CN700_7			0x7314
> +#define PCI_DEVICE_ID_CN700_BRIDGE		0xb198
> +#define PCI_DEVICE_ID_VT8237R_SATA		0x3149
> +#define PCI_DEVICE_ID_VT8237R_IDE		0x7111
> +#define PCI_DEVICE_ID_VT8237R_UHCI		0x3038
> +#define PCI_DEVICE_ID_VT8237R_EHCI		0x3104
> +#define PCI_DEVICE_ID_VT8237R_UDCI		0xd104
> +#define PCI_DEVICE_ID_VT8237R_LPC		0x3227
> +#define PCI_DEVICE_ID_VT8237R_AC97		0x3059
> +#define PCI_DEVICE_ID_VT8237R_MC97		0x3068
> +#define PCI_DEVICE_ID_VT8237R_LAN		0x3065
> +
>  #define PCI_VENDOR_ID_CIRRUS			0x1013
>  #define PCI_DEVICE_ID_CIRRUS_5446		0x00b8	/* Used by QEMU */
>  
> Index: superio/fintek/f71805f/f71805f.h
> ===================================================================
> --- superio/fintek/f71805f/f71805f.h	(revision 508)
> +++ superio/fintek/f71805f/f71805f.h	(working copy)
> @@ -24,8 +24,10 @@
>   *  - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17
>   *  - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf
>   *  - Revision: V0.25P
> - */ 
> + */
>  
> +void f71805f_enable_serial(u8, u8, u16);
> +
>  /* Logical Device Numbers (LDN). */
>  #define	F71805F_FDC	0x00	/* Floppy */
>  #define	F71805F_SP1	0x01	/* UART1 */
> Index: mainboard/Kconfig
> ===================================================================
> --- mainboard/Kconfig	(revision 507)
> +++ mainboard/Kconfig	(working copy)
> @@ -47,12 +47,18 @@
>  	help
>  	  Select this option for various system emulators, such as QEMU.
>  
> +config VENDOR_JETWAY
> +	bool "Jetway"
> +	help
> +	  Select this for various systems from Jetway.
> +
>  endchoice
>  
>  source "mainboard/adl/Kconfig"
>  source "mainboard/amd/Kconfig"
>  source "mainboard/artecgroup/Kconfig"
>  source "mainboard/emulation/Kconfig"
> +source "mainboard/jetway/Kconfig"
>  
>  choice
>  	prompt "ROM chip size"
> Index: mainboard/jetway/Kconfig
> ===================================================================
> --- mainboard/jetway/Kconfig	(revision 0)
> +++ mainboard/jetway/Kconfig	(revision 0)
> @@ -0,0 +1,40 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2007 coresystems GmbH
> +## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +choice
> +	prompt "Mainboard model"
> +	depends on VENDOR_JETWAY
> +
> +config BOARD_JETWAY_J7F2WE
> +	bool "J7F2WE"
> +	select ARCH_X86
> +	select CPU_I586
> +	select OPTION_TABLE
> +	select NORTHBRIDGE_VIA_CN700
> +	select SOUTHBRIDGE_VIA_VT8237R
> +	select SUPERIO_FINTEK_F71805F
> +	help
> +	  Jetway J7F2WE mainboard.
> +
> +endchoice
> +
> +source "mainboard/jetway/j7f2we/Kconfig"
> +
> Index: mainboard/jetway/j7f2we/Kconfig
> ===================================================================
> --- mainboard/jetway/j7f2we/Kconfig	(revision 0)
> +++ mainboard/jetway/j7f2we/Kconfig	(revision 0)
> @@ -0,0 +1,44 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2007 coresystems GmbH
> +## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +config MAINBOARD_NAME
> +	string
> +	default jetway/j7f2we
> +	depends BOARD_JETWAY_J7F2WE
> +	help
> +	  This is the default mainboard name.
> +
> +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
> +	hex
> +	# TODO: Fix PCI ID.
> +	default 0x1022
> +	depends BOARD_JETWAY_J7F2WE
> +	help
> +	  Mainboard specific PCI subsystem vendor ID.
> +
> +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
> +	hex
> +	# TODO: Fix PCI ID.
> +	default 0x2323
> +	depends BOARD_JETWAY_J7F2WE
> +	help
> +	  Mainboard specific PCI subsystem device ID.
> +
> Index: mainboard/jetway/j7f2we/initram.c
> ===================================================================
> --- mainboard/jetway/j7f2we/initram.c	(revision 0)
> +++ mainboard/jetway/j7f2we/initram.c	(revision 0)
> @@ -0,0 +1,125 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Advanced Micro Devices, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +//#include <post_code.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <io.h>
> +//#include <mtrr.h>
> +//#include "superio/fintek/f71805f/stage1.c"
> +#include "northbridge/via/cn700/raminit.h"
> +
> +/**
> + * Disable GP2 and GP3 on the vt8237r. If this isn't done, the system will
> + * reboot ~3 seconds after the initial powerup.
> + */
> +#if 0
> +static void mb_gpio_init(struct device *lpc_dev) 
> +{
> +	pci_write_config8(lpc_dev, 0x98, 0x00);
> +}
> +
> +/**
> + * enable_shadow_ram on the cn700. There are two sets of registers that
> + * control shadow ram, and they need to be kept in sync.
> + */
> +
> +static void enable_shadow_ram(const struct mem_controller *ctrl) 
> +{
> +	u8 shadowreg;
> +	
> +	printk(BIOS_DEBUG, "Enabling shadow ram\r\n");
> +	/* Enable shadow ram as normal dram */
> +	/* 0xc0000-0xcffff */
> +	pci_write_config8(ctrl->d0f3, 0x80, 0xff);
> +	pci_write_config8(ctrl->d0f7, 0x61, 0xff);
> +	/* 0xd0000-0xdffff */
> +	pci_write_config8(ctrl->d0f3, 0x81, 0xff);
> +	pci_write_config8(ctrl->d0f7, 0x62, 0xff);
> +	/* 0xe0000-0xeffff */
> +	pci_write_config8(ctrl->d0f3, 0x82, 0xff);
> +	pci_write_config8(ctrl->d0f7, 0x64, 0xff);
> +
> +	/* 0xf0000-0xfffff */
> +	shadowreg = pci_read_config8(ctrl->d0f3, 0x83);
> +	shadowreg |= 0x30;
> +	pci_write_config8(ctrl->d0f3, 0x83, 0x30);
> +
> +	/* Do it again for the vlink controller */
> +	shadowreg = pci_read_config8(ctrl->d0f7, 0x63);
> +	shadowreg |= 0x30;
> +	pci_write_config8(ctrl->d0f7, 0x63, 0x30);
> +}
> +
> +#endif
> +/** 
> +  * main for initram for the Jetway J7F2WE. Based heavily on my own v2 code.
> +  */
> +int main(void)
> +{
> +	//f71805f_enable_serial(0x2e, F71805F_SP2, 0x2f8);
> +#if 0
> +	const struct mem_controller cn700[] = {
> +		{
> +			.d0f0 = dev_find_device(0x1106, 0x0314, 0),

Maybe use pci_ids.h #defines here, too.


> +			.d0f1 = dev_find_device(0x1106, 0x1314, 0),
> +			.d0f2 = dev_find_device(0x1106, 0x2314, 0),
> +			.d0f3 = dev_find_device(0x1106, 0x3208, 0),
> +			.d0f4 = dev_find_device(0x1106, 0x4314, 0),
> +			.d0f7 = dev_find_device(0x1106, 0x7314, 0),
> +			.d1f0 = dev_find_device(0x1106, 0xb198, 0),
> +		},
> +	};
> +
> +	//post_code(POST_START_OF_MAIN);
> +
> +	struct device *lpc_dev;

Move all variable definitions to the top of the function, please.


> +	lpc_dev = dev_find_device(0x1106, 0x3227, 0);

pci_ids.h


> +	mb_gpio_init(lpc_dev);
> +
> +	//f71805f_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
> +	
> +	/* Allows access to all northbridge devices. */
> +	pci_write_config8(cn700->d0f0, 0x4f, 0x01);
> +
> +	if (lpc_dev->device != 0x3227) {
> +		printk(BIOS_DEBUG, "Southbridge not found!!!\n\r");
> +	} else {
> +		//disable_sata(lpc_dev);
> +		printk(BIOS_DEBUG, "Enabling mainboard devices\r\n");
> +		//enable_mainboard_devices(lpc_dev);
> +	}
> +
> +	enable_shadow_ram(cn700);
> +	
> +	sdram_set_registers(cn700);
> +	//sdram_set_spd_registers(cn700);
> +	sdram_enable(cn700);
> +	/* Check low memory */
> +	//ram_check(0x00000000, 640*1024);
> +	/* Check 32mb */
> +	//ram_check(1024*1024, 32*1024*1024);
> +#endif
> +	return 0;
> +}
> Index: mainboard/jetway/j7f2we/stage1.c
> ===================================================================
> --- mainboard/jetway/j7f2we/stage1.c	(revision 0)
> +++ mainboard/jetway/j7f2we/stage1.c	(revision 0)
> @@ -0,0 +1,40 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +#include <post_code.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <io.h>
> +#include <superio/fintek/f71805f/f71805f.h>
> +
> +#define SERIAL_DEV F71805F_SP2

Not needed, use F71805F_SP2 directly for now.


> +#define SERIAL_IOBASE 0x2f8

Yes, but both this and the COM2 LDN etc. etc. should all be in dts, I
think.


> +
> +void hardware_stage1(void)
> +{
> +	post_code(POST_START_OF_MAIN);
> +
> +	f71805f_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
> +	printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__);
> +}
> Index: mainboard/jetway/j7f2we/irq_tables.c
> ===================================================================
> --- mainboard/jetway/j7f2we/irq_tables.c	(revision 0)
> +++ mainboard/jetway/j7f2we/irq_tables.c	(revision 0)

IRQ tables should become part of dts too. No code support for that yet
I'm afraid, so I guess we'll have to keep the file around for now.

Or, as it's probably not successfully usable right now anyway, let's
add it later?


> @@ -0,0 +1,60 @@
> +/* This file was generated by getpir.c, do not modify! 
> +   (but if you do, please run checkpir on it to verify)
> + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
> + *
> + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
> +*/

Drop this, unneeded (and don't want a copy of it in each board).


> +
> +#include <arch/pirq_routing.h>
> +
> +#define ID_SLOT_PCI_NET		1			// ThinCan ethernet
> +#define ID_SLOT_PCI_RSVD1	2           // reserved entry 1
> +#define ID_SLOT_PCI_RSVD3	3           // reserved entry 2
> +#define ID_SLOT_PCI_RSVD2	4			// reserved entry 3
> +#define ID_EMBED_PCI		0xff		// onboard PCI device
> +
> +// CS5535 PCI INT[A-D] Interrupt Routing lines.
> +#define NO_CONNECT			0			// not used
> +#define CS_PCI_INTA			1			// PCI INTA
> +#define CS_PCI_INTB			2			// PCI INTB
> +#define CS_PCI_INTC			3			// PCI INTC
> +#define CS_PCI_INTD			4			// PCI INTD
> +
> +// IRQ bitmap reference line	FEDCBA9876543210
> +//								0000110000100000b
> +#define PCI_IRQ					0xc20	// PCI allowed IRQs here
> +
> +const struct irq_routing_table intel_irq_routing_table = 
> +{
> +	PIRQ_SIGNATURE,  /* u32 signature */
> +	PIRQ_VERSION,    /* u16 version   */
> +	32+16*6,		/* there can be total 2 devices on the bus */
> +	0x00,		 /* Where the interrupt router lies (bus) */
> +	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
> +	0x0800,			/* IRQs devoted exclusively to PCI usage */
> +	0x1022,			/* Vendor */
> +	0x208f,			/* Device */
> +	0x00000000,		/* Crap (miniport) */
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
> +	0xdf,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
> +	{
> +		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
> +		// Geode GX3 Host Bridge and VGA Graphics
> +		{0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
> +		// Realtek RTL8100/8139 Network Controller
> +		{0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
> +		// Reserved for future extensions
> +		{0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
> +		// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
> +		{0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
> +		// Reserved for future extensions
> +		{0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
> +		// Reserved for future extensions
> +		{0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
> +	}
> +};
> +
> +unsigned long write_pirq_routing_table(unsigned long addr)
> +{
> +        return copy_pirq_routing_table(addr);
> +}
> Index: mainboard/jetway/j7f2we/dts
> ===================================================================
> --- mainboard/jetway/j7f2we/dts	(revision 0)
> +++ mainboard/jetway/j7f2we/dts	(revision 0)
> @@ -0,0 +1,46 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +/{
> +	mainboard-vendor = "Jetway";
> +	mainboard-name = "J7F2WE";
> +	enabled;
> +	cpus {
> +		enabled;
> +	};
> +	domain0 {
> +		enabled;
> +		pcidomain = "0";
> +		device0,0 {
> +			enabled;
> +			pcipath = "1,0";
> +		};
> +		southbridge {
> +			/config/("southbridge/via/vt8237r");
> +			pcipath = "11,0";
> +			enabled;
> +		};
> +		superio {
> +			/config/("superio/fintek/f71805f");
> +			com1enable = "1";
> +			com2enable = "1";
> +		};
> +	};
> +};
> Index: mainboard/jetway/j7f2we/cmos.layout
> ===================================================================
> --- mainboard/jetway/j7f2we/cmos.layout	(revision 0)
> +++ mainboard/jetway/j7f2we/cmos.layout	(revision 0)

Let's leave this out for now. I'm not even sure we can handle these
files at the momen in v3, and the method _how_ we handle it might
also change.

It _might_ make sense to become a part of dts, but I'm not entirely
sure. The dts is mostly for hardware properties and config, not sure
if this can be considered as such? Comments, opinions?


> @@ -0,0 +1,74 @@
> +entries
> +
> +#start-bit length  config config-ID    name
> +#0            8       r       0        seconds
> +#8            8       r       0        alarm_seconds
> +#16           8       r       0        minutes
> +#24           8       r       0        alarm_minutes
> +#32           8       r       0        hours
> +#40           8       r       0        alarm_hours
> +#48           8       r       0        day_of_week
> +#56           8       r       0        day_of_month
> +#64           8       r       0        month
> +#72           8       r       0        year
> +#80           4       r       0        rate_select
> +#84           3       r       0        REF_Clock
> +#87           1       r       0        UIP
> +#88           1       r       0        auto_switch_DST
> +#89           1       r       0        24_hour_mode
> +#90           1       r       0        binary_values_enable
> +#91           1       r       0        square-wave_out_enable
> +#92           1       r       0        update_finished_enable
> +#93           1       r       0        alarm_interrupt_enable
> +#94           1       r       0        periodic_interrupt_enable
> +#95           1       r       0        disable_clock_updates
> +#96         288       r       0        temporary_filler
> +0          384       r       0        reserved_memory
> +384          1       e       4        boot_option
> +385          1       e       4        last_boot
> +386          1       e       1        ECC_memory
> +388          4       r       0        reboot_bits
> +392          3       e       5        baud_rate
> +400          1       e       1        power_on_after_fail
> +412          4       e       6        debug_level
> +416          4       e       7        boot_first
> +420          4       e       7        boot_second
> +424          4       e       7        boot_third
> +428          4       h       0        boot_index
> +432	     8       h       0        boot_countdown
> +1008         16      h       0        check_sum
> +
> +enumerations
> +
> +#ID value   text
> +1     0     Disable
> +1     1     Enable
> +2     0     Enable
> +2     1     Disable
> +4     0     Fallback
> +4     1     Normal
> +5     0     115200
> +5     1     57600
> +5     2     38400
> +5     3     19200
> +5     4     9600
> +5     5     4800
> +5     6     2400
> +5     7     1200
> +6     6     Notice
> +6     7     Info
> +6     8     Debug
> +6     9     Spew
> +7     0     Network
> +7     1     HDD
> +7     2     Floppy
> +7     8     Fallback_Network
> +7     9     Fallback_HDD
> +7     10    Fallback_Floppy
> +#7     3     ROM
> +
> +checksums
> +
> +checksum 392 1007 1008
> +
> +
> Index: mainboard/jetway/j7f2we/Makefile
> ===================================================================
> --- mainboard/jetway/j7f2we/Makefile	(revision 0)
> +++ mainboard/jetway/j7f2we/Makefile	(revision 0)
> @@ -0,0 +1,50 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2006-2007 coresystems GmbH
> +## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
> +
> +STAGE2_MAINBOARD_OBJ = 
> +
> +$(obj)/linuxbios.vpd:
> +	$(Q)printf "  BUILD   DUMMY VPD\n"
> +	$(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
> +
> +INITRAM_OBJ =   $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \
> +		$(obj)/southbridge/via/vt8237r/smbus_initram.o
> +
> +# Next Quest: Make a single rule out of those:
> +$(obj)/mainboard/$(MAINBOARDDIR)/initram.o: $(src)/mainboard/$(MAINBOARDDIR)/initram.c
> +	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@
> +$(obj)/northbridge/via/cn700/raminit.o: $(src)/northbridge/via/cn700/raminit.c
> +	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@
> +$(obj)/southbridge/via/vt8237r/smbus_initram.o: $(src)/southbridge/via/vt8237r/smbus_initram.c
> +	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@
> +
> +$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
> +	$(Q)# initram links against stage0
> +	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
> +	$(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \
> +		$(INITRAM_OBJ) -o $(obj)/linuxbios.initram.o
> +	$(Q)printf "  OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
> +	$(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \
> +		$(obj)/linuxbios.initram
> +	$(Q)printf "  NM      $(subst $(shell pwd)/,,$(@))\n"
> +	$(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map
> Index: arch/x86/stage1.c
> ===================================================================
> --- arch/x86/stage1.c	(revision 507)
> +++ arch/x86/stage1.c	(working copy)
> @@ -51,7 +51,52 @@
>  	post_code(0xf2);
>  }
>  
> +/* From v2, amd k8 car. Might work, might need some research */
> +inline __attribute__((always_inline)) void disable_car(void)
> +{
>  
> +        __asm__ volatile (
> +
> +        /* We don't need cache as ram for now on */
> +        /* disable cache */
> +        "movl    %cr0, %eax\n\t"
> +        "orl    $(0x1<<30),%eax\n\t"
> +        "movl    %eax, %cr0\n\t"
> +
> +        /* clear sth */
> +        "movl    $0x269, %ecx\n\t"  /* fix4k_c8000*/
> +        "xorl    %edx, %edx\n\t"
> +        "xorl    %eax, %eax\n\t"
> +	"wrmsr\n\t"
> +#if DCACHE_RAM_SIZE > 0x8000
> +	"movl    $0x268, %ecx\n\t"  /* fix4k_c0000*/
> +        "wrmsr\n\t"
> +#endif
> +
> +        /* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
> +        "movl    $0xC0010010, %ecx\n\t"
> +//        "movl    $SYSCFG_MSR, %ecx\n\t"
> +        "rdmsr\n\t"
> +        "andl    $(~(3<<18)), %eax\n\t"
> +//        "andl    $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
> +        "wrmsr\n\t"
> +
> +        /* Set the default memory type and disable fixed and enable variable MTRRs */
> +        "movl    $0x2ff, %ecx\n\t"
> +//        "movl    $MTRRdefType_MSR, %ecx\n\t"
> +        "xorl    %edx, %edx\n\t"
> +        /* Enable Variable and Disable Fixed MTRRs */
> +        "movl    $0x00000800, %eax\n\t"
> +        "wrmsr\n\t"
> +
> +        /* enable cache */
> +        "movl    %cr0, %eax\n\t"
> +        "andl    $0x9fffffff,%eax\n\t"
> +        "movl    %eax, %cr0\n\t"
> +
> +        );
> +}
> +

Can you explain? Why it this here at all? You don't seem to call it. Why
is it in stage1.c and not stage0_i586.S? Does it work? Does it work
for any x86 system of only K8?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
-------------- next part --------------
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From jordan.crouse at amd.com  Thu Nov  1 20:23:24 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 1 Nov 2007 13:23:24 -0600
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <20071101183323.30359.qmail@stuge.se>
References: <13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw> <4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101153859.GG12393@cosmic.amd.com>
	<20071101183323.30359.qmail@stuge.se>
Message-ID: <20071101192324.GH21220@cosmic.amd.com>

On 01/11/07 19:33 +0100, Peter Stuge wrote:
> On Thu, Nov 01, 2007 at 09:38:59AM -0600, Jordan Crouse wrote:
> > Stefan - can you put the .rom and the copyright notice somewhere
> > wgetable on linuxbios.org, and I'll teach buildROM how to download
> > them.
> 
> Maybe we even want it committed?

Thats a good question.  Do we?  On one hand, I hate putting binaries
into revision control - they gum up the works, and we really don't need
to track the history on this file, since we won't be changing it.  Its
another 32k that you don't need unless you are building for this
board, and there will be very few of those in the near future.

On the other hand, committing it in to SVN puts it in a known location,
and presumably Stefan is backing up the SVN, which is always good for
posterity.  So there are good arguments on both sides.

My vote is to make it web accessable and thats it.  I want to hear from
others, though.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From jordan.crouse at amd.com  Thu Nov  1 21:02:16 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 1 Nov 2007 14:02:16 -0600
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <005501c81c82$23b72330$0200a8c0@sis.com.tw>
References: <001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>
	<20071004025851.GA32267@greenwood>
	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw> <4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
Message-ID: <20071101200216.GL21220@cosmic.amd.com>

On 01/11/07 20:24 +0800, Morgan Tsai /SiS wrote:
> Change Log:
>
> 1. Add integrated VGA bios within redistributed notice,
> please help to put '6330VGA.rom' into targets/gigabyte/ga_2761gxdk/
> 2. Rename sisnb.c to sis761.c
> 3. Delete many mis-definition for sis device in 
> src/include/device/pci_ids.h
> 4. Trim trailing spaces for all files
>
>
>
> Signed-off-by: Morgan Tsai <my_tsai at sis.com>

Something strange happened to the patch, I think the mailserver
may have mangled it;  it didn't apply cleanly to the tree.  I fixed it up,
here is the same patch again that will apply against current SVN,
and compiles on my box.

Acked-by: Jordan Crouse <jordan.crouse at amd.com>
Jordan
-------------- next part --------------
Index: LinuxBIOSv2/src/include/device/pci_ids.h
===================================================================
--- LinuxBIOSv2.orig/src/include/device/pci_ids.h	2007-11-01 13:55:53.000000000 -0600
+++ LinuxBIOSv2/src/include/device/pci_ids.h	2007-11-01 13:55:53.000000000 -0600
@@ -312,11 +312,11 @@
 #define PCI_DEVICE_ID_NS_CS5535_AUDIO	0x002e
 #define PCI_DEVICE_ID_NS_CS5535_USB	0x002f
 #define PCI_DEVICE_ID_NS_CS5535_GX2VGA	0x0030
-#define PCI_DEVICE_ID_NS_SCx200_BRIDGE  0x0500 
-#define PCI_DEVICE_ID_NS_SCx200_SMI     0x0501 
+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE  0x0500
+#define PCI_DEVICE_ID_NS_SCx200_SMI     0x0501
 #define PCI_DEVICE_ID_NS_SCx200_IDE     0x0502
-#define PCI_DEVICE_ID_NS_SCx200_AUDIO   0x0503   
-#define PCI_DEVICE_ID_NS_SCx200_VIDEO   0x0504   
+#define PCI_DEVICE_ID_NS_SCx200_AUDIO   0x0503
+#define PCI_DEVICE_ID_NS_SCx200_VIDEO   0x0504
 #define PCI_DEVICE_ID_NS_SCx200_XBUS    0x0505
 #define PCI_DEVICE_ID_NS_87410		0xd001
 
@@ -652,7 +652,7 @@
 
 #define PCI_VENDOR_ID_ANIGMA		0x1051
 #define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
-  
+
 #define PCI_VENDOR_ID_EFAR		0x1055
 #define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
 #define PCI_DEVICE_ID_EFAR_SLC90E66_0	0x9460
@@ -1223,7 +1223,7 @@
 #define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
 #define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
 #define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
- 
+
 #define PCI_VENDOR_ID_CYCLONE		0x113c
 #define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
 
@@ -1726,7 +1726,7 @@
 #define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
 
 #define PCI_VENDOR_ID_ZOLTRIX		0x15b0
-#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0 
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0
 
 #define PCI_VENDOR_ID_PDC		0x15e9
 #define PCI_DEVICE_ID_PDC_1841		0x1841
@@ -1967,26 +1967,26 @@
 #define PCI_DEVICE_ID_INTEL_PCIE_PC	0x3599
 
 #define PCI_DEVICE_ID_INTEL_82801DBM_1E0 0x2448
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F0 0x24cc 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F1 0x24ca 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F3 0x24c3 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F5 0x24c5 
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F0 0x24cc
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F1 0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F3 0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F5 0x24c5
 #define PCI_DEVICE_ID_INTEL_82801DBM_1F6 0x24c6
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D0 0x24c2 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D1 0x24c4 
+#define PCI_DEVICE_ID_INTEL_82801DBM_1D0 0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DBM_1D1 0x24c4
 #define PCI_DEVICE_ID_INTEL_82801DBM_1D2 0x24c7
 #define PCI_DEVICE_ID_INTEL_82801DBM_1D7 0x24cd
 
-#define PCI_DEVICE_ID_INTEL_82801ER_1E0 0x244e 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F0 0x24d0 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F1 0x24db 
+#define PCI_DEVICE_ID_INTEL_82801ER_1E0 0x244e
+#define PCI_DEVICE_ID_INTEL_82801ER_1F0 0x24d0
+#define PCI_DEVICE_ID_INTEL_82801ER_1F1 0x24db
 #define PCI_DEVICE_ID_INTEL_82801ER_1F2 0x24d1
-#define PCI_DEVICE_ID_INTEL_82801ER_1F2_R 0x24df 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F3 0x24d3 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F5 0x24d5 
+#define PCI_DEVICE_ID_INTEL_82801ER_1F2_R 0x24df
+#define PCI_DEVICE_ID_INTEL_82801ER_1F3 0x24d3
+#define PCI_DEVICE_ID_INTEL_82801ER_1F5 0x24d5
 #define PCI_DEVICE_ID_INTEL_82801ER_1F6 0x24d6
-#define PCI_DEVICE_ID_INTEL_82801ER_1D0 0x24d2 
-#define PCI_DEVICE_ID_INTEL_82801ER_1D1 0x24d4 
+#define PCI_DEVICE_ID_INTEL_82801ER_1D0 0x24d2
+#define PCI_DEVICE_ID_INTEL_82801ER_1D1 0x24d4
 #define PCI_DEVICE_ID_INTEL_82801ER_1D2 0x24d7
 #define PCI_DEVICE_ID_INTEL_82801ER_1D3 0x24de
 #define PCI_DEVICE_ID_INTEL_82801ER_1D7 0x24dd
@@ -2076,55 +2076,33 @@
 #define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
 
 #define PCI_VENDOR_ID_SIS		0x1039
+#define PCI_DEVICE_ID_SIS_AGP 		0x0002
+#define PCI_DEVICE_ID_SIS_SIS761	0x0761
 #define PCI_DEVICE_ID_SIS_SIS966_SB	0x0966
+#define PCI_DEVICE_ID_SIS_SIS966_ISA	0x0966
 #define PCI_DEVICE_ID_SIS_SIS966_LPC	0x0966
-#define PCI_DEVICE_ID_SIS_SIS966_SLAVE	0x0361
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_2	0x0362
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_3	0x0363
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_4	0x0364
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_5	0x0365
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_6	0x0366
-#define PCI_DEVICE_ID_SIS_SIS966_PRO	0x0367
 #define PCI_DEVICE_ID_SIS_SIS966_SM2	0x0368
-#define PCI_DEVICE_ID_SIS_SIS966_IDE	0x5513
-#define PCI_DEVICE_ID_SIS_SIS966_SATA0	0x1183
-#define PCI_DEVICE_ID_SIS_SIS966_SATA1	0x037F
-#define PCI_DEVICE_ID_SIS_SIS966_NIC0	0x190
-#define PCI_DEVICE_ID_SIS_SIS966_NIC1	0x191
-#define PCI_DEVICE_ID_SIS_SIS966_NIC2	0x192
-#define PCI_DEVICE_ID_SIS_SIS966_NIC3	0x193
-#define PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE 0x0373
-#define PCI_DEVICE_ID_SIS_SIS966_AZA	0x7502
+#define PCI_DEVICE_ID_SIS_SIS966_HT	0x0369
 #define PCI_DEVICE_ID_SIS_SIS966_PCI	0x0370
+#define PCI_DEVICE_ID_SIS_SIS966_SMB	0x25a4
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_A_B 0x000A
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C 0x1002
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_E	0x1003
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_A	0x1004
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_F	0x1005
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_D	0x1006
-#define PCI_DEVICE_ID_SIS_SIS966_HT	0x0369
-#define PCI_DEVICE_ID_SIS_SIS966_TRIM	0x036A
-#define PCI_DEVICE_ID_SIS_SIS966_PMU	0x036B
-#define PCI_DEVICE_ID_SIS_SIS966_NORTHBRIDGE 0x0756
-#define PCI_DEVICE_ID_SIS_SIS966_ISA	0x0966
 #define PCI_DEVICE_ID_SIS_SIS966_AC97_AUDIO 0x7012
 #define PCI_DEVICE_ID_SIS_SIS966_AC97_MODEM 0x7013
-#define PCI_DEVICE_ID_SIS_SIS966_EHCI	0x7002
 #define PCI_DEVICE_ID_SIS_SIS966_IDE	0x5513
-#define PCI_DEVICE_ID_SIS_SIS966_SMB	0x25a4
+#define PCI_DEVICE_ID_SIS_SIS966_SATA0	0x1183
+#define PCI_DEVICE_ID_SIS_SIS966_NIC0	0x0190
+#define PCI_DEVICE_ID_SIS_SIS966_NIC1	0x0191
+#define PCI_DEVICE_ID_SIS_SIS966_AZA	0x7502
 #define PCI_DEVICE_ID_SIS_SIS966_USB	0x7001
-#define PCI_DEVICE_ID_SIS_SIS966_USB2	0x7001
-#define PCI_DEVICE_ID_SIS_SIS966_USB3	0x7001
-#define PCI_DEVICE_ID_SIS_SIS966_SATA	0x1183
-#define PCI_DEVICE_ID_SIS_SIS966_SATA_R	0x1183
-#define PCI_DEVICE_ID_SIS_SIS966_PIC1	0x25ac
-#define PCI_DEVICE_ID_SIS_SIS966_BRIDGE1C 0x0966
-#define PCI_DEVICE_ID_SIS_AGP 		0x0002
-#define PCI_DEVICE_ID_SIS_SIS761	0x0761
-#define PCI_DEVICE_ID_SIS_SIS756	0x0756
+#define PCI_DEVICE_ID_SIS_SIS966_USB2	0x7002
 
 /* OLD USAGE FOR LINUXBIOS */
-#define PCI_VENDOR_ID_ACER              0x10b9   
+#define PCI_VENDOR_ID_ACER              0x10b9
 #define PCI_DEVICE_ID_ACER_M1535D         0x1533
 
 #define PCI_DEVICE_ID_AMD_761_0         0x700E
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2007-11-01 13:55:54.000000000 -0600
@@ -239,15 +239,12 @@
 				#  devices on link 0, link 0 == LDT 0
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   # Northbridge
-					#################################################
-					device pci 1.0 on 			# AGP bridge
+					device pci 1.0 on		# AGP bridge
 					  chip drivers/pci/onboard	# Integrated VGA
 						device pci 0.0 on end
 						register "rom_address" = "0xfff80000"
 					  end
 					end
-					#################################################
-					## device pci 1.0 on end   # PCIE
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f
 							device pnp 2e.0 off #  Floppy
@@ -272,12 +269,12 @@
                 	                 			io 0x62 = 0x230
                 	                			irq 0x70 = 9
 							end
-                	        			device pnp 2e.5 off #  Keyboard
+                	        			device pnp 2e.5 on #  Keyboard
                 	                 			io 0x60 = 0x60
                 	                 			io 0x62 = 0x64
                 	                			irq 0x70 = 1
 							end
-                	        			device pnp 2e.6 off #  Mouse
+                	        			device pnp 2e.6 on #  Mouse
                 	                			irq 0x70 = 12
 							end
                 	        			device pnp 2e.8 off #  MIDI
@@ -291,30 +288,27 @@
 						end
 					end
 
- 					device pci 2.5 on end # IDE (SiS5513)
- 					device pci 2.6 off end # Modem (SiS7013)
- 					device pci 2.7 off end # Audio (SiS7012)
-                			device pci 3.0 on end # USB (SiS7001,USB1.1)
-	                		device pci 3.1 on end # USB (SiS7001,USB1.1)
-	                		device pci 3.3 on end # USB (SiS7002,USB2.0)
-	                		device pci 4.0 on end # NIC (SiS191)
-                			device pci 5.0 on end # SATA (SiS1183)
-                			device pci 6.0 off end # SB PCIE1 (SiS000A)
-                			device pci 7.0 off end # SB PCIE2 (SiS000A)
-        	       			device pci 9.0 off end # PCI E 6
-        	       			device pci a.0 off end # PCI E 5
-        	       			device pci b.0 off end # PCI E 4
-                			device pci c.0 off end # PCI E 3
-                			device pci d.0 off end # PCI E 2
-                			device pci e.0 off end # PCI E 1
-        	       			device pci f.0 on end # Hda
+                                        device pci 2.5 off end # IDE (SiS5513)
+                                        device pci 2.6 off end # Modem (SiS7013)
+                                        device pci 2.7 off end # Audio (SiS7012)
+                                        device pci 3.0 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.1 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.3 on end # USB (SiS7002,USB2.0)
+                                        device pci 4.0 on end # NIC (SiS191)
+                                        device pci 5.0 on end # SATA (SiS1183,IDE Mode)
+                                        device pci 6.0 off end # PCI-E (SiS000A)
+                                        device pci 7.0 off end # PCI-E (SiS000A)
+                                        device pci a.0 off end
+                                        device pci b.0 off end
+                                        device pci c.0 off end
+                                        device pci d.0 off end
+                                        device pci e.0 off end
+                                        device pci f.0 off end # HD Audio (SiS7502)
 
-	                                register "ide0_enable" = "1"
-	                                register "ide1_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-				   	#register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-				   	#register "mac_eeprom_addr" = "0x51"
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+                                        register "sata0_enable" = "1"
+                                        register "sata1_enable" = "1"
 				end
 			end #  device pci 18.0
 			device pci 18.0 on end # Link 1
@@ -328,14 +322,14 @@
 
 #       chip drivers/generic/debug
 #               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 on end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
+#               device pnp 0.1 on end # pci_regs_all
+#               device pnp 0.2 on end # mem
+#               device pnp 0.3 off end # cpuid
+#               device pnp 0.4 on end # smbus_regs_all
+#               device pnp 0.5 off end # dual core msr
+#               device pnp 0.6 off end # cache size
 #               device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 off end # io
+#               device pnp 0.8 off  end # io
+#               device pnp 0.9 off end # io
 #       end
 end #root_complex
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2007-11-01 13:55:55.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2007-11-01 13:55:55.000000000 -0600
@@ -1,25 +1,25 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
 ## Written by Morgan Tsai <my_tsai at sis.com> for SiS.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
@@ -197,7 +197,7 @@
 #CHIP_NAME ?
 default CONFIG_CHIP_NAME=1
 
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000
 #1G
@@ -253,8 +253,8 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="SiS"
-default MAINBOARD_VENDOR="SIS"
+default MAINBOARD_PART_NUMBER="ga_2761gxdk"
+default MAINBOARD_VENDOR="GIGABYTE"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
 
@@ -294,7 +294,7 @@
 
 ###
 ### Defaults of options that you may want to override in the target config file
-### 
+###
 
 ##
 ## The default compiler
@@ -304,7 +304,7 @@
 
 ##
 ## Disable the gdb stub by default
-## 
+##
 default CONFIG_GDB_STUB=0
 
 ##
@@ -335,15 +335,15 @@
 ##
 ### Select the linuxBIOS loglevel
 ##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
 
 ## Request this level of debugging output
 default  DEFAULT_CONSOLE_LOGLEVEL=8
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2007-11-01 13:55:53.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2007-11-01 13:55:53.000000000 -0600
@@ -27,7 +27,7 @@
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
-#define SET_NB_CFG_54 1 
+#define SET_NB_CFG_54 1
 
 //used by raminit
 #define QRANK_DIMM_SUPPORT 1
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2007-11-01 13:55:54.000000000 -0600
@@ -46,7 +46,7 @@
 #endif
 
 #define DBGP_DEFAULT 7
- 
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -95,7 +95,7 @@
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
 #include "southbridge/sis/sis966/sis966_early_ctrl.c"
 
@@ -126,7 +126,7 @@
 
 #include "sdram/generic_sdram.c"
 
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -171,13 +171,13 @@
         uint8_t byte;
 
         byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
-        
+
         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
@@ -237,15 +237,15 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
+#if HAVE_FAILOVER_BOOT==1
     #if USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
+	failover_process(bist, cpu_init_detectedx);
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
     #if USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
+	failover_process(bist, cpu_init_detectedx);
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
@@ -281,7 +281,7 @@
         setup_mb_resource_map();
 
         uart_init();
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -340,7 +340,6 @@
 
         needs_reset |= optimize_link_coherent_ht();
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
-        needs_reset |= sis966_early_setup_x();
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
@@ -353,8 +352,8 @@
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
         sis_init_stage1();
-        enable_smbus(); 
-       
+        enable_smbus();
+
         memreset_setup();
 
         //do we need apci timer, tsc...., only debug need it for better output
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/chip.h
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/chip.h	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/chip.h	2007-11-01 13:55:54.000000000 -0600
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout	2007-11-01 13:55:54.000000000 -0600
@@ -1,23 +1,23 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 entries
 
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	2007-11-01 13:55:54.000000000 -0600
@@ -40,7 +40,7 @@
         unsigned apicid_sis966;
 
 
-unsigned pci1234x[] = 
+unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -52,7 +52,7 @@
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] = 
+unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 //	0x20202020,
@@ -63,7 +63,7 @@
 //        0x20202020,
 //        0x20202020,
 };
-unsigned bus_type[256]; 
+unsigned bus_type[256];
 
 extern void get_sblk_pci1234(void);
 
@@ -96,13 +96,13 @@
 	for(i=0; i<8; i++) {
 		bus_sis966[i] = 0;
 	}
-	
+
 	for(i=0;i<256; i++) {
 		bus_type[i] = 0;
 	}
 
 	bus_type[0] = 1; //pci
-	
+
 	bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 
 	bus_type[bus_sis966[0]] = 1;
@@ -140,8 +140,8 @@
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
-#else 
-	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
 	apicid_sis966 = apicid_base+0;
 
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	2007-11-01 13:55:54.000000000 -0600
@@ -32,7 +32,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <arch/pirq_routing.h>
-
+#include <device/pci_ids.h>
 #include <cpu/amd/amdk8_sysconf.h>
 
 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
@@ -75,7 +75,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk_info("Writing IRQ routing tables to 0x%x...\n", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -88,8 +88,8 @@
 
 	pirq->exclusive_irqs = 0;
 
-	pirq->rtr_vendor = 0x10de;
-	pirq->rtr_device = 0x0370;
+	pirq->rtr_vendor = PCI_VENDOR_ID_SIS;
+	pirq->rtr_device = PCI_DEVICE_ID_SIS_SIS966_PCI;
 
 	pirq->miniport_data = 0;
 
@@ -124,11 +124,17 @@
                 }
 
                 printk_debug("Setting Onboard SiS Southbridge\n");
-//                dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
-//                pci_write_config8(dev, 0x3C, 0x0A);
-                dev = dev_find_slot(0, PCI_DEVFN(3,0));   // USB 1.1 -1
+
+                /*
+                 * Non-layout for GA-2761GX
+                 *
+                dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
+                pci_write_config8(dev, 0x3C, 0x0A);
+                */
+
+                dev = dev_find_slot(0, PCI_DEVFN(3,0));   // USB 1.1
                 pci_write_config8(dev, 0x3C, 0x0B);
-                dev = dev_find_slot(0, PCI_DEVFN(3,1));   // USB 1.1 -2
+                dev = dev_find_slot(0, PCI_DEVFN(3,1));   // USB 1.1
                 pci_write_config8(dev, 0x3C, 0x05);
                 dev = dev_find_slot(0, PCI_DEVFN(3,3));   // USB 2.0
                 pci_write_config8(dev, 0x3C, 0x0A);
@@ -136,12 +142,17 @@
                 pci_write_config8(dev, 0x3C, 0x05);
                 dev = dev_find_slot(0, PCI_DEVFN(5,0));    // 1183 (SATA)
                 pci_write_config8(dev, 0x3C, 0x0B);
-//                dev = dev_find_slot(0, PCI_DEVFN(6,0));   // PCI-E
-//                pci_write_config8(dev, 0x3C, 0x0A);
-//                dev = dev_find_slot(0, PCI_DEVFN(7,0));   // PCI-E
-//                pci_write_config8(dev, 0x3C, 0x0A);
+
+                /*
+                 * Non-layout for GA-2761GX
+                 *
+                dev = dev_find_slot(0, PCI_DEVFN(6,0));   // PCI-E
+                pci_write_config8(dev, 0x3C, 0x0A);
+                dev = dev_find_slot(0, PCI_DEVFN(7,0));   // PCI-E
+                pci_write_config8(dev, 0x3C, 0x0A);
                 dev = dev_find_slot(0, PCI_DEVFN(15,0));  // Azalia
                 pci_write_config8(dev, 0x3C, 0x05);
+                */
         }
 
 //pci bridge
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c	2007-11-01 13:55:54.000000000 -0600
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/mptable.c	2007-11-01 13:55:54.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c	2007-11-01 13:55:54.000000000 -0600
@@ -33,7 +33,7 @@
 
 extern unsigned apicid_sis966;
 
-extern unsigned bus_type[256]; 
+extern unsigned bus_type[256];
 
 void *smp_write_config_table(void *v)
 {
@@ -80,7 +80,7 @@
                 device_t dev;
 		struct resource *res;
 		uint32_t dword;
- 
+
                 dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
                 if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_1);
@@ -99,7 +99,7 @@
 
                 }
 	}
-  
+
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
 */	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sis966, 0x1);
@@ -135,7 +135,7 @@
         	}
 	}
 
-	for(j=0; j<2; j++) 
+	for(j=0; j<2; j++)
 	        for(i=0;i<4;i++) {
         	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[1], ((0x06+j)<<2)|i, apicid_sis966, 0x10 + (2+i+j)%4);
 	        }
Index: LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
===================================================================
--- LinuxBIOSv2.orig/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c	2007-11-01 13:55:55.000000000 -0600
+++ LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c	2007-11-01 13:55:55.000000000 -0600
@@ -161,7 +161,7 @@
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -199,7 +199,7 @@
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
@@ -217,7 +217,7 @@
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -225,7 +225,7 @@
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
@@ -270,9 +270,9 @@
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
Index: LinuxBIOSv2/src/southbridge/sis/sis966/Config.lb
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/Config.lb	2007-11-01 13:55:55.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/Config.lb	2007-11-01 13:55:55.000000000 -0600
@@ -1,27 +1,26 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
 ## Written by Morgan Tsai <my_tsai at sis.com> for SiS.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 config chip.h
-#driver sis_agp.o
-driver sisnb.o
+driver sis761.o
 driver sis966.o
 driver sis966_usb.o
 driver sis966_lpc.o
Index: LinuxBIOSv2/src/southbridge/sis/sis966/chip.h
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/chip.h	2007-11-01 13:55:55.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/chip.h	2007-11-01 13:55:55.000000000 -0600
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *
Index: LinuxBIOSv2/src/southbridge/sis/sis966/romstrap.inc
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/romstrap.inc	2007-11-01 13:55:55.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/romstrap.inc	2007-11-01 13:55:55.000000000 -0600
@@ -43,28 +43,16 @@
 	.long 0xFFFFFFFF			// 28h
 	.long 0xFFFFFFFF			// 2Ch
 
-// MAC address -------------------------------- 0x7FFC0h	
 	.long 0x56341200			// 30h, MAC address low 4 byte ---> keep it in 0xffffffc0
 	.long 0x00009078			// 34h, MAC address high 4 byte
 
 	.long 0x002309CE			// 38h, UUID low 4 byte
 	.long 0x00E08100			// 3Ch, UUID high 4 byte
 
-
-// Firmware Trap --------------------------------  0x7FFD0h	
-/* 
-//Firmware trap for SiS761+966         
-        .long 0x00402000
-        .long 0x6043A800  
-        .long 0x00180000
-        .long 0x1421C402 	
-*/        
- 
-//Firmware trap for SiS756+966              ---> keep it in 0xffffffd0
-        .long 0x00402000
-        .long 0xE043A800  
-        .long 0x00180000
-        .long 0x1421C402 
+	.long 0x00402000			//Firmware trap for SiS761+966
+	.long 0xE043A800
+	.long 0x00180000
+	.long 0x1421C402
 
 rspointers:
 	.long rstables				// It will be 0xffffffe0
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	2007-11-01 13:55:55.000000000 -0600
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ * Turn off machine check triggers when reading
+ * pci space where there are no devices.
+ * This is necessary when scaning the bus for
+ * devices which is done by the kernel
+ *
+ * written in 2003 by Eric Biederman
+ *
+ *  - Athlon64 workarounds by Stefan Reinauer
+ *  - "reset once" logic by Yinghai Lu
+ * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
+ * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <part/hard_reset.h>
+#include <pc80/mc146818rtc.h>
+#include <bitops.h>
+#include <cpu/amd/model_fxx_rev.h>
+
+//#include "amdk8.h"
+
+#include <arch/io.h>
+
+/**
+ * @brief Read resources for AGP aperture
+ *
+ * @param
+ *
+ * There is only one AGP aperture resource needed. The resoruce is added to
+ * the northbridge of BSP.
+ *
+ * The same trick can be used to augment legacy VGA resources which can
+ * be detect by generic pci reousrce allocator for VGA devices.
+ * BAD: it is more tricky than I think, the resource allocation code is
+ * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * purpose :-(.
+ */
+
+
+typedef struct msr_struct
+{
+	unsigned lo;
+	unsigned hi;
+} msr_t;
+
+static inline msr_t rdmsr(unsigned index)
+{
+	msr_t result;
+	result.lo = 0;
+	result.hi = 0;
+	return result;
+}
+
+
+
+static void sis761_read_resources(device_t dev)
+{
+	struct resource *resource;
+	unsigned char iommu;
+	/* Read the generic PCI resources */
+	printk_debug("sis761_read_resources\n");
+	pci_dev_read_resources(dev);
+
+	/* If we are not the first processor don't allocate the gart apeture */
+	if (dev->path.u.pci.devfn != PCI_DEVFN(0x0, 0)) {
+		return;
+	}
+
+
+	return;
+
+	iommu = 1;
+	get_option(&iommu, "iommu");
+
+	if (iommu) {
+		/* Add a Gart apeture resource */
+		resource = new_resource(dev, 0x94);
+		resource->size = iommu?AGP_APERTURE_SIZE:1;
+		resource->align = log2(resource->size);
+		resource->gran  = log2(resource->size);
+		resource->limit = 0xffffffff; /* 4G */
+		resource->flags = IORESOURCE_MEM;
+	}
+}
+
+static void set_agp_aperture(device_t dev)
+{
+	struct resource *resource;
+
+	return;
+
+	resource = probe_resource(dev, 0x94);
+	if (resource) {
+		device_t pdev;
+		uint32_t gart_base, gart_acr;
+
+		/* Remember this resource has been stored */
+		resource->flags |= IORESOURCE_STORED;
+
+		/* Find the size of the GART aperture */
+		gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
+
+		/* Get the base address */
+		gart_base = ((resource->base) >> 25) & 0x00007fff;
+
+		/* Update the other northbriges */
+		pdev = 0;
+		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
+			/* Store the GART size but don't enable it */
+			pci_write_config32(pdev, 0x90, gart_acr);
+
+			/* Store the GART base address */
+			pci_write_config32(pdev, 0x94, gart_base);
+
+			/* Don't set the GART Table base address */
+			pci_write_config32(pdev, 0x98, 0);
+
+			/* Report the resource has been stored... */
+			report_resource_stored(pdev, resource, " <gart>");
+		}
+	}
+}
+
+static void sis761_set_resources(device_t dev)
+{
+        printk_debug("sis761_set_resources ------->\n");
+	/* Set the gart apeture */
+//	set_agp_aperture(dev);
+
+	/* Set the generic PCI resources */
+	pci_dev_set_resources(dev);
+	printk_debug("sis761_set_resources <-------\n");
+}
+
+static void sis761_init(struct device *dev)
+{
+	uint32_t cmd, cmd_ref;
+	int needs_reset;
+	struct device *f0_dev, *f2_dev;
+	msr_t	msr;
+
+
+	needs_reset = 0;
+	printk_debug("sis761_init: ---------->\n");
+
+	msr = rdmsr(0xC001001A);
+	pci_write_config16(dev, 0x8E, msr.lo >> 16);				// Topbound
+	pci_write_config8(dev, 0x7F, 0x08);			// ACPI Base
+	outb(inb(0x856) | 0x40, 0x856);	 // Auto-Reset Function
+
+	printk_debug("sis761_init: <----------\n");
+	printk_debug("done.\n");
+}
+
+
+static struct device_operations sis761_ops  = {
+	.read_resources   = sis761_read_resources,
+	.set_resources    = sis761_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = sis761_init,
+	.scan_bus         = 0,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver sis761_driver __pci_driver = {
+	.ops    = &sis761_ops,
+	.vendor = PCI_VENDOR_ID_SIS,
+	.device = PCI_DEVICE_ID_SIS_SIS761,
+};
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966.c	2007-11-01 13:55:55.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966.c	2007-11-01 13:55:55.000000000 -0600
@@ -49,7 +49,7 @@
 		) ) {
 			uint32_t id;
 			id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
-			if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16))) 	
+			if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16)))
 				) {
 				lpc_dev = 0;
 			}
@@ -62,19 +62,18 @@
 {
 	device_t lpc_dev = 0;
 	device_t sm_dev = 0;
-	unsigned index = 0;
-	unsigned index2 = 0;
+	uint16_t index = 0;
+	uint16_t index2 = 0;
 	uint32_t reg_old, reg;
 	uint8_t byte;
-	unsigned deviceid;
-	unsigned vendorid;
+	uint16_t deviceid;
+	uint16_t vendorid;
+	uint16_t devfn;
 
 	struct southbridge_sis_sis966_config *conf;
 	conf = dev->chip_info;
 	int i;
 
-	unsigned devfn;
-
 	if(dev->device==0x0000) {
 		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
 		deviceid = (vendorid>>16) & 0xffff;
@@ -88,25 +87,16 @@
 	switch(deviceid) {
 		case PCI_DEVICE_ID_SIS_SIS966_HT:
 			return;
-
-		case PCI_DEVICE_ID_SIS_SIS966_SM2://?
-			index = 16;
 			break;
 		case PCI_DEVICE_ID_SIS_SIS966_USB:
 			devfn -= (1<<3);
 			index = 8;
 			break;
-		case PCI_DEVICE_ID_SIS_SIS966_EHCI:
-			devfn -= (1<<3);
-			index = 20;
-			break;
-/*		case PCI_DEVICE_ID_SIS_SIS966_USB3:
+		case PCI_DEVICE_ID_SIS_SIS966_USB2:
 			devfn -= (1<<3);
 			index = 20;
 			break;
-*/
-		case PCI_DEVICE_ID_SIS_SIS966_NIC1: //two
-		case PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE://two
+		case PCI_DEVICE_ID_SIS_SIS966_NIC1:
 			devfn -= (7<<3);
 			index = 10;
 			for(i=0;i<2;i++) {
@@ -125,8 +115,7 @@
 			devfn -= (3<<3);
 			index = 14;
 			break;
-		case PCI_DEVICE_ID_SIS_SIS966_SATA0: //three
-		case PCI_DEVICE_ID_SIS_SIS966_SATA1: //three
+		case PCI_DEVICE_ID_SIS_SIS966_SATA0:
 			devfn -= (4<<3);
 			index = 22;
 			i = (dev->path.u.pci.devfn) & 7;
@@ -138,11 +127,7 @@
 			devfn -= (5<<3);
 			index = 15;
 			break;
-//		case PCI_DEVICE_ID_SIS_SIS966_PCIE_A:
-//			devfn -= (0x9<<3);  // to LPC
-//			index2 = 9;
-//			break;
-		case PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C: //two
+		case PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C:
 			devfn -= (0xa<<3);  // to LPC
 			index2 = 8;
 			for(i=0;i<2;i++) {
@@ -216,17 +201,8 @@
 		if(!sm_dev) return;
 
 		final_reg = pci_read_config32(sm_dev, 0xe8);
-		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
+		final_reg &= ~0x0057cf00;
 		pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
-#if 0
-		reg_old = reg = pci_read_config32(sm_dev, 0xe4);
-//		reg |= (1<<0);
-		reg &= ~(0x3f<<4);
-		if (reg != reg_old) {
-			printk_debug("sis966.c pcie enabled\n");
-			pci_write_config32(sm_dev, 0xe4, reg);
-		}
-#endif
 	}
 
 	if (!dev->enabled) {
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966.h
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966.h	2007-11-01 13:55:55.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966.h	2007-11-01 13:55:55.000000000 -0600
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *
@@ -24,6 +22,13 @@
 #ifndef SIS966_H
 #define SIS966_H
 
+#define DEBUG_AZA 0
+#define DEBUG_NIC 0
+#define DEBUG_IDE 0
+#define DEBUG_SATA 0
+#define DEBUG_USB 0
+#define DEBUG_USB2 0
+
 #include "chip.h"
 
 void sis966_enable(device_t dev);
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_aza.c	2007-11-01 13:55:56.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c	2007-11-01 13:55:56.000000000 -0600
@@ -32,10 +32,10 @@
 #include "sis966.h"
 
 uint8_t	SiS_SiS7502_init[7][3]={
-{0x04, 0xFF, 0x07},					 
-{0x2C, 0xFF, 0x39},					 
-{0x2D, 0xFF, 0x10},					 
-{0x2E, 0xFF, 0x91},					 
+{0x04, 0xFF, 0x07},
+{0x2C, 0xFF, 0x39},
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x91},
 {0x2F, 0xFF, 0x01},
 {0x04, 0xFF, 0x06},
 {0x00, 0x00, 0x00}					//End of table
@@ -61,7 +61,7 @@
 
 	if(!count) return -1;
 
-	udelay(540);
+	udelay(500);
 	return 0;
 
 }
@@ -71,30 +71,29 @@
 
 
      uint32_t dword;
-	 
+
      dword = readl(base + 0x68);
      dword=dword|(unsigned long)0x0002;
      writel(dword,base + 0x68);
-     do {	  	
-	 	dword = readl(base + 0x68);	   
+     do {
+	 	dword = readl(base + 0x68);
      }  while ((dword & 1)!=0);
      writel(verb, base + 0x60);
-     udelay(500);	 
-     dword = readl(base + 0x68);	  
-     dword =(dword |0x1);   
+     udelay(500);
+     dword = readl(base + 0x68);
+     dword =(dword |0x1);
      writel(dword, base + 0x68);
      do {
-	 	udelay(120);
+	 	udelay(100);
 		dword = readl(base + 0x68);
      } while ((dword & 3) != 2);
 
      dword = readl(base + 0x64);
      return dword;
-		
+
 }
 
 
-#if 1
 static int codec_detect(uint8_t *base)
 {
 	uint32_t dword;
@@ -102,97 +101,31 @@
 
 	/* 1 */ // controller reset
 	printk_debug("controller reset\n");
-      
+
 	set_bits(base + 0x08, 1, 1);
-      
+
       do{
-	  	dword = readl(base + 0x08)&0x1;	
+	  	dword = readl(base + 0x08)&0x1;
 		if(idx++>1000) { printk_debug("controller reset fail !!! \n"); break;}
 	   } while (dword !=1);
-       
+
        dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
-       
+
        if(dword==0) {
 	   	printk_debug("No codec!\n");
 		return 0;
        }
 
 	 printk_debug("Codec ID = %lx\n", dword);
-	  
-#if 0
-	/* 2 */
-	dword = readl(base + 0x0e);
-	dword |= 7;
-	writel(dword, base + 0x0e);
-
-	/* 3 */
-	set_bits(base + 0x08, 1, 0);
 
-	/* 4 */
-	set_bits(base + 0x08, 1, 1);
-		
-	/* 5 */
-	dword = readl(base + 0xe);
-	dword &= 7;
-       
-	/* 6 */
-	if(!dword) {
-		set_bits(base + 0x08, 1, 0);
-		printk_debug("No codec!\n");
-		return 0;
-	}
-#endif 
        dword=0x1;
 	return dword;
 
 }
 
-#else
-
-static int codec_detect(uint8_t *base)
-{
-	uint32_t dword;
 
-	/* 1 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 2 */
-	dword = readl(base + 0x0e);
-	dword |= 7;
-	writel(dword, base + 0x0e);
-
-	/* 3 */
-	set_bits(base + 0x08, 1, 0);
-
-	/* 4 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 5 */
-	dword = readl(base + 0xe);
-	dword &= 7;
-
-	/* 6 */
-	if(!dword) {
-		set_bits(base + 0x08, 1, 0);
-		printk_debug("No codec!\n");
-		return 0;
-	}
-	return dword;
-
-}
-
-#endif
-
-#if 1
-
-// For SiS demo board PinConfig
 static uint32_t verb_data[] = {
-#if 0
- 00172083h,
- 00172108h,
- 001722ECh,
- 00172310h,
-#endif
+
 //14
 	0x01471c10,
 	0x01471d40,
@@ -255,79 +188,6 @@
 	0x01f71f01,
 };
 
-#else
-// orginal codec pin configuration setting
-
-static uint32_t verb_data[] = {
-#if 0
-	0x00172001,
-	0x001721e6,
-	0x00172200,
-	0x00172300,
-#endif
-
-	0x01471c10,
-	0x01471d44,
-	0x01471e01,
-	0x01471f01,
-//1
-	0x01571c12,
-	0x01571d14,
-	0x01571e01,
-	0x01571f01,
-//2
-	0x01671c11,
-	0x01671d60,
-	0x01671e01,
-	0x01671f01,
-//3
-	0x01771c14,
-	0x01771d20,
-	0x01771e01,
-	0x01771f01,
-//4
-	0x01871c30,
-	0x01871d9c,
-	0x01871ea1,
-	0x01871f01,
-//5
-	0x01971c40,
-	0x01971d9c,
-	0x01971ea1,
-	0x01971f02,
-//6
-	0x01a71c31,
-	0x01a71d34,
-	0x01a71e81,
-	0x01a71f01,
-//7
-	0x01b71c1f,
-	0x01b71d44,
-	0x01b71e21,
-	0x01b71f02,
-//8
-	0x01c71cf0,
-	0x01c71d11,
-	0x01c71e11,
-	0x01c71f41,
-//9
-	0x01d71c3e,
-	0x01d71d01,
-	0x01d71e83,
-	0x01d71f99,
-//10
-	0x01e71c20,
-	0x01e71d41,
-	0x01e71e45,
-	0x01e71f01,
-//11
-	0x01f71c50,
-	0x01f71d91,
-	0x01f71ec5,
-	0x01f71f01,
-};
-
-#endif 
 static unsigned find_verb(uint32_t viddid, uint32_t **verb)
 {
         if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
@@ -370,17 +230,6 @@
 	/* 3 */
 	for(i=0; i<verb_size; i++) {
 		send_verb(base,verb[i]);
-#if 0
-		do {
-			dword = readl(base + 0x68);
-		} while (dword & 1);
-
-		writel(verb[i], base + 0x60);
-
-		do {
-			dword = readl(base + 0x68);
-		} while ((dword & 3) != 2);
-#endif 
 	}
 	printk_debug("verb loaded!\n");
 }
@@ -398,45 +247,50 @@
 
 static void aza_init(struct device *dev)
 {
-	uint8_t *base;
-	struct resource *res;
-	uint32_t codec_mask;
+        uint8_t *base;
+        struct resource *res;
+        uint32_t codec_mask;
 
+        print_debug("AZALIA_INIT:---------->\n");
 
 //-------------- enable AZA (SiS7502) -------------------------
 {
-       uint8_t  temp8;
-       int i=0;
-	while(SiS_SiS7502_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
-					temp8 &= SiS_SiS7502_init[i][1];
-					temp8 |= SiS_SiS7502_init[i][2];									
-					pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
-					i++;
-	};
+        uint8_t  temp8;
+        int i=0;
+        while(SiS_SiS7502_init[i][0] != 0)
+        {
+                temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
+                temp8 &= SiS_SiS7502_init[i][1];
+                temp8 |= SiS_SiS7502_init[i][2];
+                pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
+                i++;
+        };
 }
 //-----------------------------------------------------------
 
 
-// put audio to D0 state
-pci_write_config8(dev, 0x54,0x00);
+        // put audio to D0 state
+        pci_write_config8(dev, 0x54,0x00);
 
-#if 0
+#if DEBUG_AZA
 {
-    int i;
-    printk_debug("Azalia PCI config \n");
-    for(i=0;i<0xFF;i+=4)
-    {
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug("  ");
+        int i;
+
+        print_debug("****** Azalia PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
         }
-        print_debug_hex32(pci_read_config32(dev,i));
-        print_debug("  ");    
-    }
-    print_debug("\r\n");
+        print_debug("\r\n");
 }
-#endif 
+#endif
 
 	res = find_resource(dev, 0x10);
 	if(!res)
@@ -452,24 +306,7 @@
 		codecs_init(base, codec_mask);
 	}
 
-#if 0
-{
-    int i;
-    printk_debug("Azalia PCI config \n");
-    for(i=0;i<0xFF;i+=4)
-    {
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug("  ");
-        }
-        outl(0x80000800+i,0xcf8);     
-        print_debug_hex32(inl(0xcfc));
-        print_debug("  ");    
-    }
-    print_debug("\r\n");
-}
-#endif 
-
+        print_debug("AZALIA_INIT:<----------\n");
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_early_ctrl.c	2007-11-01 13:55:56.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	2007-11-01 13:55:56.000000000 -0600
@@ -51,10 +51,10 @@
 static void soft_reset(void)
 {
 	set_bios_reset();
-#if 1
+
 	/* link reset */
 	outb(0x02, 0x0cf9);
 	outb(0x06, 0x0cf9);
-#endif
+
 }
 
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_setup_car.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_early_setup_car.c	2007-11-01 13:55:56.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_setup_car.c	2007-11-01 13:55:56.000000000 -0600
@@ -21,125 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-static int set_ht_link_sis966(uint8_t ht_c_num)
-{
-	unsigned vendorid = 0x10de;
-	unsigned val = 0x01610109;
-	/* Nvidia sis966 hardcode, hw can not set it automatically */
-	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
-}
-
-static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
-{
-	int i;
-
-	unsigned val;
-
-	val = inl(control);
-	val &= 0xfffffffe;
-	outl(val, control);
-
-	outl(0, index); //index
-	for(i = 0; i < max; i++) {
-		unsigned long reg;
-		reg = register_values[i];
-		outl(reg, where);
-	}
-
-	val = inl(control);
-	val |= 1;
-	outl(val, control);
-
-}
-
-/* SIZE 0x100 */
-#define ANACTRL_IO_BASE	0x2800
-#define ANACTRL_REG_POS	0x68
-
-/* SIZE 0x100 */
-#define SYSCTRL_IO_BASE	0x2400
-#define SYSCTRL_REG_POS	0x64
-
-/* SIZE 0x100 */
-#define ACPICTRL_IO_BASE	0x2000
-#define ACPICTRL_REG_POS	0x60
-
-/*
-	16 1 1 1 1 8 :0
-	16 0 4 0 0 8 :1
-	16 0 4 2 2 4 :2
-	 4 4 4 4 4 8 :3
-	 8 8 4 0 0 8 :4
-	 8 0 4 4 4 8 :5
-*/
-
-#ifndef SIS966_PCI_E_X_0
-	#define SIS966_PCI_E_X_0	4
-#endif
-#ifndef SIS966_PCI_E_X_1
-	#define SIS966_PCI_E_X_1	4
-#endif
-#ifndef SIS966_PCI_E_X_2
-	#define SIS966_PCI_E_X_2	4
-#endif
-#ifndef SIS966_PCI_E_X_3
-	#define SIS966_PCI_E_X_3	4
-#endif
-
-#ifndef SIS966_USE_NIC
-	#define SIS966_USE_NIC	0
-#endif
-
-#ifndef SIS966_USE_AZA
-	#define SIS966_USE_AZA	0
-#endif
-
-#define SIS966_CHIP_REV	3
-
-static void sis966_early_set_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base)
-{
-
-	static const unsigned int ctrl_devport_conf[] = {
-		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
-		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
-	};
-
-	int j;
-	for(j = 0; j < sis966_num; j++ ) {
-		setup_resource_map_offset(ctrl_devport_conf,
-			sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
-			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
-	}
-}
-
-static void sis966_early_clear_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base)
-{
-
-	static const unsigned int ctrl_devport_conf_clear[] = {
-		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
-	};
-
-	int j;
-	for(j = 0; j < sis966_num; j++ ) {
-		setup_resource_map_offset(ctrl_devport_conf_clear,
-			sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
-			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
-	}
-
-
-}
-static void delayx(uint8_t value) {
-#if 1
-	int i;
-	for(i=0;i<0x8000;i++) {
-		outb(value, 0x80);
-	}
-#endif
-}
-
 static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
 {
 	uint32_t tgio_ctrl;
@@ -170,260 +51,13 @@
 	outl(tgio_ctrl, anactrl_io_base + 0xcc);
 
 //	wait 100us
-	delayx(1);
+	udelay(100);
 
 	dword = pci_read_config32(dev, 0xe4);
 	dword &= ~(0x3f0); // enable
 	pci_write_config32(dev, 0xe4, dword);
 
 //	need to wait 100ms
-	delayx(1000);
+	mdelay(100);
 }
 
-static void sis966_early_setup(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
-{
-
-    static const unsigned int ctrl_conf_1[] = {
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
-
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
-
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
-
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
-    };
-
-    static const unsigned int ctrl_conf_1_1[] = {
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
-    };
-
-
-    static const unsigned int ctrl_conf_sis966_only[] = {
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
-
-//	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
-//	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
-
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
-#if SIS966_USE_AZA == 1
-	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
-
-//	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
-#endif
-// play a while with GPIO in SIS966
-#ifdef SIS966_MB_SETUP
-	SIS966_MB_SETUP
-#endif
-
-#if SIS966_USE_AZA == 1
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
-#endif
-
-
-    };
-
-    static const unsigned int ctrl_conf_master_only[] = {
-
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
-
-	//Master SIS966 ????YHLU
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
-
-    };
-
-    static const unsigned int ctrl_conf_2[] = {
-	/* I didn't put pcie related stuff here */
-
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
-
-	RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
-
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
-
-
-#if SIS966_USE_NIC == 1
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
-
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
-#endif
-
-    };
-
-
-	int j, i;
-
-	for(j=0; j<sis966_num; j++) {
-		sis966_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
-
-		setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-		for(i=0; i<3; i++) { // three SATA
-			setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
-				PCI_DEV(busn[j], devn[j], i), io_base[j]);
-		}
-		if(busn[j] == 0) {
-			setup_resource_map_x_offset(ctrl_conf_sis966_only, sizeof(ctrl_conf_sis966_only)/sizeof(ctrl_conf_sis966_only[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-		}
-
-		if( (busn[j] == 0) && (sis966_num>1) ) {
-			setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-		}
-
-		setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-
-	}
-
-#if 0
-	for(j=0; j< sis966_num; j++) {
-		// PCI-E (XSPLL) SS table 0x40, x044, 0x48
-		// SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
-		// CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
-			io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
-			io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
-			io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
-	}
-#endif
-
-}
-
-#ifndef HT_CHAIN_NUM_MAX
-
-#define HT_CHAIN_NUM_MAX	4
-#define HT_CHAIN_BUSN_D	0x40
-#define HT_CHAIN_IOBASE_D	0x4000
-
-#endif
-
-static int sis966_early_setup_x(void)
-{
-	/*find out how many sis966 we have */
-	unsigned busn[HT_CHAIN_NUM_MAX];
-	unsigned devn[HT_CHAIN_NUM_MAX];
-	unsigned io_base[HT_CHAIN_NUM_MAX];
-	/*
-		FIXME: May have problem if there is different SIS966 HTX card with different PCI_E lane allocation
-		Need to use same trick about pci1234 to verify node/link connection
-	*/
-	unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {SIS966_PCI_E_X_0, SIS966_PCI_E_X_1, SIS966_PCI_E_X_2, SIS966_PCI_E_X_3 };
-	int sis966_num = 0;
-	unsigned busnx;
-	unsigned devnx;
-	int ht_c_index,j;
-
-	/* FIXME: multi pci segment handling */
-
-	/* Any system that only have IO55 without SIS966? */
-	for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) {
-		busnx = ht_c_index * HT_CHAIN_BUSN_D;
-		for(devnx=0;devnx<0x20;devnx++) {
-			uint32_t id;
-			device_t dev;
-			dev = PCI_DEV(busnx, devnx, 0);
-			id = pci_read_config32(dev, PCI_VENDOR_ID);
-			if(id == 0x036910de) {
-				busn[sis966_num] = busnx;
-				devn[sis966_num] = devnx;
-				io_base[sis966_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than SIS966
-				sis966_num++;
-				if(sis966_num == SIS966_NUM) goto out;
-				break; // only one SIS966 on one chain
-			}
-		}
-	}
-
-out:
-	print_debug("sis966_num:"); print_debug_hex8(sis966_num); print_debug("\r\n");
-
-	//sis966_early_set_port(sis966_num, busn, devn, io_base);
-	//sis966_early_setup(sis966_num, busn, devn, io_base, pci_e_x);
-
-	//sis966_early_clear_port(sis966_num, busn, devn, io_base);
-
-//	set_ht_link_sis966(HT_CHAIN_NUM_MAX);
-
-	return 0;
-
-}
-
-
-
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-01 13:55:56.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-01 13:55:56.000000000 -0600
@@ -134,7 +134,7 @@
 };
 
 
-#if 1
+
 uint8_t	SiS_NB_init[56][3]={
 {0x04, 0x00 ,0x07},					//Reg 0x04
 {0x05, 0x00 ,0x00},					//Reg 0x05 // alex
@@ -191,85 +191,11 @@
 {0x97, 0x00 ,0x00},					//Reg 0x97
 {0x98, 0x00 ,0x00},					//Reg 0x98
 {0x99, 0x00 ,0x00},					//Reg 0x99
-// alex
-//{0xD7, 0x00 ,0x00},					//Reg 0x99
-//{0xDD, 0x00 ,0x02},					//Reg 0x99
-//
-//{0x13, 0x00 ,0xF0},					//Reg 0x99
-
-{0x00, 0x00, 0x00}					//End of table
-};
-
-#else
-uint8_t	SiS_NB_init[61][3]={
-{0x04, 0x00 ,0x07},					//Reg 0x04
-{0x05, 0x00 ,0x00},					//Reg 0x05 // alex
-{0x0D, 0x00 ,0x20},					//Reg 0x0D
-{0x2C, 0x00 ,0x39},					//Reg 0x2C
-{0x2D, 0x00 ,0x10},					//Reg 0x2D
-{0x2E, 0x00 ,0x61},					//Reg 0x2E
-{0x2F, 0x00 ,0x07},					//Reg 0x2F
-{0x34, 0x00 ,0xA0},					//Reg 0x34
-{0x40, 0x00 ,0x36},					//Reg 0x40
-{0x42, 0x00 ,0xB9},					//Reg 0x42
-{0x43, 0x00 ,0x8B},					//Reg 0x43
-{0x44, 0x00 ,0x05},					//Reg 0x44
-{0x45, 0x00 ,0xFF},					//Reg 0x45
-{0x46, 0x00 ,0x90},					//Reg 0x46
-{0x47, 0x00 ,0xA0},					//Reg 0x47
-{0x4C, 0xFF ,0x50},					//Reg 0x4C //  SiS307 enable
-{0x4E, 0x00 ,0x00},					//Reg 0x4E
-{0x4F, 0x00 ,0x02},					//Reg 0x4F
-{0x5B, 0x00 ,0x44},					//Reg 0x5B
-{0x5D, 0x00 ,0x00},					//Reg 0x5D
-{0x5E, 0x00 ,0x25},					//Reg 0x5E
-{0x61, 0x00 ,0xB0},					//Reg 0x61
-{0x65, 0x00 ,0xB0},					//Reg 0x65
-{0x68, 0x00 ,0x4C},					//Reg 0x68
-{0x69, 0x00 ,0xD0},					//Reg 0x69
-{0x6B, 0x00 ,0x07},					//Reg 0x6B
-{0x6C, 0x00 ,0xDD},					//Reg 0x6C
-{0x6D, 0x00 ,0xAD},					//Reg 0x6D
-{0x6E, 0x00 ,0xE8},					//Reg 0x6E
-{0x6F, 0x00 ,0x4D},					//Reg 0x6F
-{0x70, 0x00 ,0x00},					//Reg 0x70
-{0x71, 0x00 ,0x80},					//Reg 0x71
-{0x72, 0x00 ,0x00},					//Reg 0x72
-{0x73, 0x00 ,0x00},					//Reg 0x73
-{0x74, 0x00 ,0x01},					//Reg 0x74
-{0x75, 0x00 ,0x10},					//Reg 0x75
-{0x7E, 0x00 ,0x29},					//Reg 0x7E
-{0x8B, 0x00 ,0x10},					//Reg 0x8B
-{0x8D, 0x00 ,0x03},					//Reg 0x8D
-{0xA1, 0x00 ,0xD0},					//Reg 0xA1
-{0xA2, 0x00 ,0x30},					//Reg 0xA2
-{0xA4, 0x00 ,0x0B},					//Reg 0xA4
-{0xA9, 0x00 ,0x02},					//Reg 0xA9
-{0xB0, 0x00 ,0x30},					//Reg 0xB0
-{0xB4, 0x00 ,0x30},					//Reg 0xB4
-{0x90, 0x00 ,0x00},					//Reg 0x90
-{0x91, 0x00 ,0x00},					//Reg 0x91
-{0x92, 0x00 ,0x00},					//Reg 0x92
-{0x93, 0x00 ,0x00},					//Reg 0x93
-{0x94, 0x00 ,0x00},					//Reg 0x94
-{0x95, 0x00 ,0x00},					//Reg 0x95
-{0x96, 0x00 ,0x00},					//Reg 0x96
-{0x97, 0x00 ,0x00},					//Reg 0x97
-{0x98, 0x00 ,0x00},					//Reg 0x98
-{0x99, 0x00 ,0x00},					//Reg 0x99
-// alex
-{0x86, 0x00 ,0x14},					//Reg 0x99
-{0x87, 0x00 ,0xC8},					//Reg 0x99
-{0xF4, 0x00 ,0x01},
-//
-{0x13, 0x00 ,0xF0},					//Reg 0x99
 
 {0x00, 0x00, 0x00}					//End of table
 };
 
 
-#endif
-#if 1
 uint8_t SiS_NBAGP_init[34][3]={
 {0xCF, 0xDF, 0x00},      //HT issue
 {0x06, 0xDF, 0x20},
@@ -309,78 +235,6 @@
 {0x00, 0x00, 0x00}     //End of table
 };
 
-
-
-#else
-
-//uint8_t SiS_NBAGP_init[53][3]={
-uint8_t SiS_NBAGP_init[40][3]={
-{0x04, 0x00 ,0x07},					//Reg 0x04
-{0x05, 0x00 ,0x01},					//Reg 0x05 // alex
-
-{0xCF, 0xDF, 0x00},      //HT issue
-{0x06, 0xDF, 0x20},
-{0x1E, 0xDF, 0x20},
-{0x50, 0x00, 0x02},
-{0x51, 0x00, 0x00},
-{0x54, 0x00, 0x09},
-{0x55, 0x00, 0x00},
-{0x56, 0x00, 0x80},
-{0x58, 0x00, 0x08},
-{0x60, 0x00, 0xB1},
-{0x61, 0x00, 0x02},
-{0x62, 0x00, 0x60},
-{0x63, 0x00, 0x60},
-{0x64, 0x00, 0xAA},
-{0x65, 0x00, 0x18},
-{0x68, 0x00, 0x23},
-{0x69, 0x00, 0x23},
-{0x6A, 0x00, 0xC8},
-{0x6B, 0x00, 0x08},
-{0x6C, 0x00, 0x00},
-{0x6D, 0x00, 0x00},
-{0x6E, 0x00, 0x08},
-{0x6F, 0x00, 0x00},
-{0xBB, 0x00, 0x00},
-{0xB5, 0x00, 0x30},
-{0xB0, 0x00, 0xDB},
-{0xB6, 0x00, 0x73},
-{0xB7, 0x00, 0x50},
-{0xBA, 0xBF, 0x41},
-{0xB4, 0x3F, 0xC0},
-{0xBF, 0xF9, 0x06},
-{0xBA, 0x00, 0x61},
-{0xBD, 0x7F, 0x80},
-
-
-
-{0x0D, 0x00 ,0x40},					//Reg 0x05 // alex
-/*
-{0x19, 0x00 ,0x01},					//Reg 0x05 // alex
-{0x1A, 0x00 ,0x01},					//Reg 0x05 // alex
-{0x1B, 0x00 ,0x40},					//Reg 0x05 // alex
-{0x1C, 0x00 ,0xE0},					//Reg 0x05 // alex
-{0x1D, 0x00 ,0xE0},					//Reg 0x05 // alex
-{0x20, 0x00 ,0xB0},					//Reg 0x05 // alex
-{0x21, 0x00 ,0xFE},					//Reg 0x05 // alex
-{0x22, 0x00 ,0xB0},					//Reg 0x05 // alex
-{0x23, 0x00 ,0xFE},					//Reg 0x05 // alex
-{0x24, 0x00 ,0x00},					//Reg 0x05 // alex
-{0x25, 0x00 ,0xD8},					//Reg 0x05 // alex
-{0x26, 0x00 ,0xF0},					//Reg 0x05 // alex
-{0x27, 0x00 ,0xDF},					//Reg 0x05 // alex
-*/
-{0x3E, 0x00 ,0x0A},					//Reg 0x05 // alex
-
-{0xCB, 0x00 ,0x10},					//Reg 0x05 // alex
-{0xCF, 0x00 ,0x48},					//Reg 0x05 // alex
-
-
-{0x00, 0x00, 0x00}     //End of table
-};
-
-#endif
-
 uint8_t	SiS_ACPI_2_init[56][3]={
 {0x00, 0x00, 0xFF},					//Reg 0x00
 {0x01, 0x00, 0xFF},					//Reg 0x01
@@ -440,129 +294,55 @@
 {0x00, 0x00, 0x00}					//End of table
 };
 
-#if 0
-uint8_t	SiS_SiS1183_init[60][3]={
-{0x04, 0x00, 0x05},					 
-{0x09, 0x00, 0x05},					 
-{0x2C, 0x00, 0x39},					 
-{0x2D, 0x00, 0x10},					  
-{0x2E, 0x00, 0x83},					 
-{0x2F, 0x00, 0x11},					 
-{0x90, 0x00, 0x40},					 
-{0x91, 0x00, 0x00},	// set mode				 
-{0x50, 0x00, 0xA2},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0x00, 0x96},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0xF7, 0x00},					 
-{0x56, 0x00, 0xC0},	
-{0x57, 0x00, 0x14},
-{0x67, 0x00, 0x28},					 
-{0x81, 0x00, 0xB3},					 
-{0x82, 0x00, 0x72},					 
-{0x83, 0x00, 0x40},					 
-{0x85, 0x00, 0xB3},					 
-{0x86, 0x00, 0x72},					 
-{0x87, 0x00, 0x40},
-{0x88, 0x00, 0xDE},      // after set mode					 
-{0x89, 0x00, 0xB3},					 
-{0x8A, 0x00, 0x72},					 
-{0x8B, 0x00, 0x40},					 
-{0x8C, 0x00, 0xDE},					 
-{0x8D, 0x00, 0xB3},					 
-{0x8E, 0x00, 0x92},					 
-{0x8F, 0x00, 0x40},					 
-{0x93, 0x00, 0x00},					 
-{0x94, 0x00, 0x80},					 
-{0x95, 0x00, 0x08},					 
-{0x96, 0x00, 0x80},					 
-{0x97, 0x00, 0x08},
-{0x9C, 0x00, 0x80},					 
-{0x9D, 0x00, 0x08},					 
-{0x9E, 0x00, 0x80},					 
-{0x9F, 0x00, 0x08},					 
-{0xA0, 0x00, 0x15},					 
-{0xA1, 0x00, 0x15},					 
-{0xA2, 0x00, 0x15},					 
-{0xA3, 0x00, 0x15},
-
-//{0xD8, 0xFE, 0x01},	// Com reset				
-//{0xC8, 0xFE, 0x01},
-//{0xE8, 0xFE, 0x01},
-//{0xF8, 0xFE, 0x01},
-{0xC4, 0xFF, 0xFF},    // Clear status					 
-{0xC5, 0xFF, 0xFF},
-{0xC6, 0xFF, 0xFF},
-{0xC7, 0xFF, 0xFF},
-{0xD4, 0xFF, 0xFF},
-{0xD5, 0xFF, 0xFF},
-{0xD6, 0xFF, 0xFF},
-{0xD7, 0xFF, 0xFF},
-{0xE4, 0xFF, 0xFF},    // Clear status					 
-{0xE5, 0xFF, 0xFF},
-{0xE6, 0xFF, 0xFF},
-{0xE7, 0xFF, 0xFF},
-{0xF4, 0xFF, 0xFF},
-{0xF5, 0xFF, 0xFF},
-{0xF6, 0xFF, 0xFF},
-{0xF7, 0xFF, 0xFF},
-{0x00, 0x00, 0x00}					//End of table
-};
-
-#else
-
 uint8_t	SiS_SiS1183_init[44][3]={
-{0x04, 0x00, 0x05},					 
-{0x09, 0x00, 0x05},					 
-{0x2C, 0x00, 0x39},					 
-{0x2D, 0x00, 0x10},					  
-{0x2E, 0x00, 0x83},					 
-{0x2F, 0x00, 0x11},					 
-{0x90, 0x00, 0x40},					 
-{0x91, 0x00, 0x00},	// set mode				 
-{0x50, 0x00, 0xA2},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0x00, 0x96},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0xF7, 0x00},					 
-{0x56, 0x00, 0xC0},	
+{0x04, 0x00, 0x05},
+{0x09, 0x00, 0x05},
+{0x2C, 0x00, 0x39},
+{0x2D, 0x00, 0x10},
+{0x2E, 0x00, 0x83},
+{0x2F, 0x00, 0x11},
+{0x90, 0x00, 0x40},
+{0x91, 0x00, 0x00},	// set mode
+{0x50, 0x00, 0xA2},
+{0x52, 0x00, 0xA2},
+{0x55, 0x00, 0x96},
+{0x52, 0x00, 0xA2},
+{0x55, 0xF7, 0x00},
+{0x56, 0x00, 0xC0},
 {0x57, 0x00, 0x14},
-{0x67, 0x00, 0x28},					 
-{0x81, 0x00, 0xB3},					 
-{0x82, 0x00, 0x72},					 
-{0x83, 0x00, 0x40},					 
-{0x85, 0x00, 0xB3},					 
-{0x86, 0x00, 0x72},					 
+{0x67, 0x00, 0x28},
+{0x81, 0x00, 0xB3},
+{0x82, 0x00, 0x72},
+{0x83, 0x00, 0x40},
+{0x85, 0x00, 0xB3},
+{0x86, 0x00, 0x72},
 {0x87, 0x00, 0x40},
-{0x88, 0x00, 0xDE},      // after set mode					 
-{0x89, 0x00, 0xB3},					 
-{0x8A, 0x00, 0x72},					 
-{0x8B, 0x00, 0x40},					 
-{0x8C, 0x00, 0xDE},					 
-{0x8D, 0x00, 0xB3},					 
-{0x8E, 0x00, 0x92},					 
-{0x8F, 0x00, 0x40},					 
-{0x93, 0x00, 0x00},					 
-{0x94, 0x00, 0x80},					 
-{0x95, 0x00, 0x08},					 
-{0x96, 0x00, 0x80},					 
+{0x88, 0x00, 0xDE},      // after set mode
+{0x89, 0x00, 0xB3},
+{0x8A, 0x00, 0x72},
+{0x8B, 0x00, 0x40},
+{0x8C, 0x00, 0xDE},
+{0x8D, 0x00, 0xB3},
+{0x8E, 0x00, 0x92},
+{0x8F, 0x00, 0x40},
+{0x93, 0x00, 0x00},
+{0x94, 0x00, 0x80},
+{0x95, 0x00, 0x08},
+{0x96, 0x00, 0x80},
 {0x97, 0x00, 0x08},
-{0x9C, 0x00, 0x80},					 
-{0x9D, 0x00, 0x08},					 
-{0x9E, 0x00, 0x80},					 
-{0x9F, 0x00, 0x08},					 
-{0xA0, 0x00, 0x15},					 
-{0xA1, 0x00, 0x15},					 
-{0xA2, 0x00, 0x15},					 
+{0x9C, 0x00, 0x80},
+{0x9D, 0x00, 0x08},
+{0x9E, 0x00, 0x80},
+{0x9F, 0x00, 0x08},
+{0xA0, 0x00, 0x15},
+{0xA1, 0x00, 0x15},
+{0xA2, 0x00, 0x15},
 {0xA3, 0x00, 0x15},
-
-
 {0x00, 0x00, 0x00}					//End of table
 };
 
-#endif
 
-/*       In => Share Memory size 
+/*       In => Share Memory size
                             => 00h :    0MBytes
                             => 02h :   32MBytes
                             => 03h :   64MBytes
@@ -570,14 +350,14 @@
                             => Others:  Reserved
 */
 void Init_Share_Memory(uint8_t ShareSize)
-{  
+{
     device_t dev;
- 
+
     dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
     pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5));
 }
- 
-/* In:     => Aperture size 
+
+/* In:     => Aperture size
                => 00h :   32MBytes
                => 01h :   64MBytes
                => 02h :  128MBytes
@@ -587,77 +367,24 @@
 */
 void Init_Aper_Size(uint8_t AperSize)
 {
- device_t dev;
- uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
- 
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
- pci_write_config8(dev, 0x90, AperSize << 1);
-
-//pci_write_config32(dev, 0x94, 0x78);
-//pci_write_config32(dev, 0x98, 0x0);
- 
-#if 0
-{
-int i;
-print_debug("Function3 Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{   if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
+        device_t dev;
+        uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
 
-dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
-pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
+        pci_write_config8(dev, 0x90, AperSize << 1);
 
-#if 0
-{
-int i;
-dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1101), 0);
-print_debug("Function1 Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+        pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
 }
-print_debug("\n");  
-}
-
- #endif 
-
- 
-}
-
- 
-
-
 
 void sis_init_stage1(void)
 {
-  device_t dev;
-	uint8_t temp8;
-  int	i;
-	uint8_t	GUI_En;   
+        device_t dev;
+        uint8_t temp8;
+        int	i;
+        uint8_t	GUI_En;
 
-#if 0
-{
-int i;
-print_debug("Northbridge PCI Config in sis_init_stage1.0\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 	
-
-// SiS_Chipset_Initialization	
+// SiS_Chipset_Initialization
 // ========================== NB =============================
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
 	i=0;
@@ -669,23 +396,6 @@
 					i++;
 	};
 
-
-#if 0
-{
-int i;
-print_debug("Northbridge PCI Config in sis_init_stage1.1\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
-
-
-	
 // ========================== LPC =============================
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 	i=0;
@@ -723,16 +433,16 @@
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);		//Restore Internal GUI enable bit
 	temp8 = pci_read_config8(dev, 0x4C);
 	pci_write_config8(dev, 0x4C, temp8 | GUI_En);
-	
-     return;				
+
+     return;
 }
 
 
 
 void sis_init_stage2(void)
 {
-  	device_t dev;	
-  	msr_t	msr; 
+  	device_t dev;
+  	msr_t	msr;
 	int	i;
 	uint32_t j;
 	uint8_t temp8;
@@ -740,89 +450,56 @@
 
 
 // ========================== NB_AGP =============================
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);   //Enable Internal GUI enable bit
- pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
- 
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, 0x0002), 0);
- i=0;
- while(SiS_NBAGP_init[i][0] != 0)
- {    temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
-     temp8 &= SiS_NBAGP_init[i][1];
-     temp8 |= SiS_NBAGP_init[i][2];
-     pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
-     i++;
- };
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);   //Enable Internal GUI enable bit
+        pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
 
-/*       In => Share Memory size 
-                            => 00h :    0MBytes
-                            => 02h :   32MBytes
-                            => 03h :   64MBytes
-                            => 04h :  128MBytes
-                            => Others:  Reserved
-*/
-/* In:     => Aperture size 
-               => 00h :   32MBytes
-               => 01h :   64MBytes
-               => 02h :  128MBytes
-               => 03h :  256MBytes
-               => 04h :  512MBytes
-               => Others:  Reserved
-*/
- 
-  Init_Share_Memory(0x02);  //0x02 : 32M  0x03 : 64M
-  Init_Aper_Size(0x01);   // 0x1
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
+        i=0;
 
-#if 0
-{
-int i;
-print_debug("AGP PCI Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
+        while(SiS_NBAGP_init[i][0] != 0)
+        {
+                temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
+                temp8 &= SiS_NBAGP_init[i][1];
+                temp8 |= SiS_NBAGP_init[i][2];
+                pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
+                i++;
+        };
+
+/**
+  *   Share Memory size
+  *             => 00h :    0MBytes
+  *             => 02h :   32MBytes
+  *             => 03h :   64MBytes
+  *             => 04h :  128MBytes
+  *             => Others:  Reserved
+  *
+  *   Aperture size
+  *             => 00h :   32MBytes
+  *             => 01h :   64MBytes
+  *             => 02h :  128MBytes
+  *             => 03h :  256MBytes
+  *             => 04h :  512MBytes
+  *             => Others:  Reserved
+  */
 
+        Init_Share_Memory(0x02);  //0x02 : 32M
+        Init_Aper_Size(0x01);   //0x1 : 64M
 
 // ========================== NB =============================
 
-	printk_debug("Init NorthBridge sis761 -------->\n");
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
-	msr = rdmsr(0xC001001A);
-	printk_debug("Memory Top Bound %lx\n",msr.lo );
-// 	pci_write_config16(dev, 0x8E, msr.lo >> 16);				// Topbound
-//    pci_write_config16(dev, 0x8E, (msr.lo >> 16) - ((pci_read_config8(dev, 0x4C) & 0xE0) >> 5));
- 
-    temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
-    //printk_debug("0x4c = %x\n",temp16);
-    temp16=0x0001<<(temp16-1);
-    temp16<<=8;
-   
-    printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
-    pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
-  // pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16);
-    pci_write_config8(dev, 0x7F, 0x08);									// ACPI Base
-    outb(inb(0x856) | 0x40, 0x856);										// Auto-Reset Function
-
-#if 0
-{
-int i;
-print_debug("Northbridge PCI Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
-
-
-
+        printk_debug("Init NorthBridge sis761 -------->\n");
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+        msr = rdmsr(0xC001001A);
+	 printk_debug("Memory Top Bound %lx\n",msr.lo );
+
+        temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
+        temp16=0x0001<<(temp16-1);
+        temp16<<=8;
+
+        printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
+        pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
+        pci_write_config8(dev, 0x7F, 0x08);									// ACPI Base
+        outb(inb(0x856) | 0x40, 0x856);										// Auto-Reset Function
 
 // ========================== ACPI =============================
 	i=0;
@@ -839,37 +516,20 @@
        printk_debug("Init Misc -------->\n");
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_ISA), 0);
 	// PCI Device Enable
-	pci_write_config8(dev, 0x7C, 0x03);  // bit0=0 : enable audio controller(), bit1=1 : disable modem 
+	pci_write_config8(dev, 0x7C, 0x03);  // bit0=0 : enable audio controller(), bit1=1 : disable modem
 	pci_write_config8(dev, 0x76, pci_read_config8(dev, 0x76)|0x30);  // SM bus enable, PCIEXP Controller 1 and 2 disable
-	pci_write_config8(dev, 0x7E, 0x00);  // azalia controller enable 
+	pci_write_config8(dev, 0x7E, 0x00);  // azalia controller enable
 
 	temp8=inb(0x878)|0x4;   //bit2=1 enable Azalia  =0 enable AC97
 	outb(temp8, 0x878);  // ACPI select AC97 or HDA controller
 	printk_debug("Audio select %x\n",inb(0x878));
-	
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, 0x1183), 0);	
-	if(!dev){			
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA0), 0);
+	if(!dev){
 		print_debug("SiS 1183 does not exist !!");
 	}
 	// SATA Set Mode
 	pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);
-	
-
-//-------------- enable IDE (SiS1183) -------------------------
-/*
-{    
-       uint8_t  temp8;
-       int i=0;
-	while(SiS_SiS1183_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
-					temp8 &= SiS_SiS1183_init[i][1];
-					temp8 |= SiS_SiS1183_init[i][2];				
-					pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
-					i++;
-	};
-}
-
-*/
 
 }
 
@@ -880,16 +540,16 @@
 	device_t dev;
 	uint8_t temp8;
 	printk_debug("enable_smbus -------->\n");
-	
+
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 
 	/* set smbus iobase && enable ACPI Space*/
-	pci_write_config16(dev, 0x74, 0x0800);			// Set ACPI Base
+	pci_write_config16(dev, 0x74, 0x0800);				// Set ACPI Base
 	temp8=pci_read_config8(dev, 0x40);					// Enable ACPI Space
 	pci_write_config8(dev, 0x40, temp8 | 0x80);
 	temp8=pci_read_config8(dev, 0x76);					// Enable SMBUS
 	pci_write_config8(dev, 0x76, temp8 | 0x03);
-	
+
 	printk_debug("enable_smbus <--------\n");
 }
 
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_enable_rom.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_enable_rom.c	2007-11-01 13:55:56.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_enable_rom.c	2007-11-01 13:55:56.000000000 -0600
@@ -32,7 +32,7 @@
 static void sis966_enable_rom(void)
 {
 	device_t addr;
- 
+
 	/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
 	addr = pci_locate_device(PCI_ID(0x1039, 0x0966), 0);
 
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_ide.c	2007-11-01 13:55:56.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c	2007-11-01 13:55:56.000000000 -0600
@@ -32,44 +32,44 @@
 #include "sis966.h"
 
 uint8_t	SiS_SiS5513_init[49][3]={
-{0x04, 0xFF, 0x05},					 
-{0x0D, 0xFF, 0x80},					 
-{0x2C, 0xFF, 0x39},					 
-{0x2D, 0xFF, 0x10},					  
-{0x2E, 0xFF, 0x13},					 
-{0x2F, 0xFF, 0x55},					 
-{0x50, 0xFF, 0xA2},					 
-{0x51, 0xFF, 0x21},					 
-{0x53, 0xFF, 0x21},					 
-{0x54, 0xFF, 0x2A},					 
-{0x55, 0xFF, 0x96},					 
-{0x52, 0xFF, 0xA2},					 
-{0x56, 0xFF, 0x81},					 
-{0x57, 0xFF, 0xC0},					 
-{0x60, 0xFF, 0xFB},					 
-{0x61, 0xFF, 0xAA},					 
-{0x62, 0xFF, 0xFB},					 
-{0x63, 0xFF, 0xAA},					 
-{0x81, 0xFF, 0xB3},					 
-{0x82, 0xFF, 0x72},					 
-{0x83, 0xFF, 0x40},					 
-{0x85, 0xFF, 0xB3},					 
-{0x86, 0xFF, 0x72},					 
-{0x87, 0xFF, 0x40},					 
-{0x94, 0xFF, 0xC0},					 
-{0x95, 0xFF, 0x08},					 
-{0x96, 0xFF, 0xC0},					 
-{0x97, 0xFF, 0x08},					 
-{0x98, 0xFF, 0xCC},					 
-{0x99, 0xFF, 0x04},					 
-{0x9A, 0xFF, 0x0C},					 
-{0x9B, 0xFF, 0x14},					 
-{0xA0, 0xFF, 0x11},					 
-{0x57, 0xFF, 0xD0},	
-
-{0xD8, 0xFE, 0x01},	// Com reset				 
-{0xC8, 0xFE, 0x01},					 
-{0xC4, 0xFF, 0xFF},    // Clear status					 
+{0x04, 0xFF, 0x05},
+{0x0D, 0xFF, 0x80},
+{0x2C, 0xFF, 0x39},
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x13},
+{0x2F, 0xFF, 0x55},
+{0x50, 0xFF, 0xA2},
+{0x51, 0xFF, 0x21},
+{0x53, 0xFF, 0x21},
+{0x54, 0xFF, 0x2A},
+{0x55, 0xFF, 0x96},
+{0x52, 0xFF, 0xA2},
+{0x56, 0xFF, 0x81},
+{0x57, 0xFF, 0xC0},
+{0x60, 0xFF, 0xFB},
+{0x61, 0xFF, 0xAA},
+{0x62, 0xFF, 0xFB},
+{0x63, 0xFF, 0xAA},
+{0x81, 0xFF, 0xB3},
+{0x82, 0xFF, 0x72},
+{0x83, 0xFF, 0x40},
+{0x85, 0xFF, 0xB3},
+{0x86, 0xFF, 0x72},
+{0x87, 0xFF, 0x40},
+{0x94, 0xFF, 0xC0},
+{0x95, 0xFF, 0x08},
+{0x96, 0xFF, 0xC0},
+{0x97, 0xFF, 0x08},
+{0x98, 0xFF, 0xCC},
+{0x99, 0xFF, 0x04},
+{0x9A, 0xFF, 0x0C},
+{0x9B, 0xFF, 0x14},
+{0xA0, 0xFF, 0x11},
+{0x57, 0xFF, 0xD0},
+
+{0xD8, 0xFE, 0x01},    // Com reset
+{0xC8, 0xFE, 0x01},
+{0xC4, 0xFF, 0xFF},    // Clear status
 {0xC5, 0xFF, 0xFF},
 {0xC6, 0xFF, 0xFF},
 {0xC7, 0xFF, 0xFF},
@@ -78,10 +78,10 @@
 {0xD6, 0xFF, 0xFF},
 {0xD7, 0xFF, 0xFF},
 
-				 
-{0x2C, 0xFF, 0x39},	// set subsystem ID 					 
-{0x2D, 0xFF, 0x10},					 
-{0x2E, 0xFF, 0x13},					 
+
+{0x2C, 0xFF, 0x39},	// set subsystem ID
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x13},
 {0x2F, 0xFF, 0x55},
 
 
@@ -96,22 +96,23 @@
 	uint16_t word;
 	uint8_t byte;
 	conf = dev->chip_info;
-	
-	
 
-printk_debug("ide_init:---------->\n");
+
+
+print_debug("IDE_INIT:---------->\n");
 
 
 //-------------- enable IDE (SiS5513) -------------------------
 {
-       uint8_t  temp8;
-       int i=0;
+        uint8_t  temp8;
+        int i=0;
 	while(SiS_SiS5513_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
-					temp8 &= SiS_SiS5513_init[i][1];
-					temp8 |= SiS_SiS5513_init[i][2];				
-					pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
-					i++;
+	{
+                temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
+                temp8 &= SiS_SiS5513_init[i][1];
+                temp8 |= SiS_SiS5513_init[i][2];
+                pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
+                i++;
 	};
 }
 //-----------------------------------------------------------
@@ -146,6 +147,26 @@
 	pci_dev_init(dev);
 #endif
 
+#if DEBUG_IDE
+{
+        int i;
+
+        print_debug("****** IDE PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
+        }
+        print_debug("\r\n");
+}
+#endif
+print_debug("IDE_INIT:<----------\n");
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_lpc.c	2007-11-01 13:55:56.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c	2007-11-01 13:55:56.000000000 -0600
@@ -151,81 +151,33 @@
 	lpc_common_init(dev);
 }
 
-#if 0
-static void enable_hpet(struct device *dev)
-{
-	unsigned long hpet_address;
-
-	pci_write_config32(dev,0x44, 0xfed00001);
-	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
-	printk_debug("enabling HPET @0x%x\n", hpet_address);
-}
-#endif
 
 static void lpc_usb_legacy_init(device_t dev)
 {
     uint16_t acpi_base;
 
     acpi_base = (pci_read_config8(dev,0x75) << 8);
-    //printk_debug("ACPI Base Addr=0x%4.4x\n",acpi_base);
-
-    //printk_debug("acpi_base + 0xbb=%.2x\n", inb(acpi_base + 0xbb));
-    //printk_debug("acpi_base + 0xba=%.2x\n", inb(acpi_base + 0xba));
 
     outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
     outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
-
-    //printk_debug("acpi_base + 0xbb=%.2x\n", inb(acpi_base + 0xbb));
-    //printk_debug("acpi_base + 0xba=%.2x\n", inb(acpi_base + 0xba));
-
-    return;
 }
 
 static void lpc_init(device_t dev)
 {
-	uint8_t byte;
-	uint8_t byte_old;
-	int on;
-	int nmi_option;
+	 uint8_t byte;
+	 uint8_t byte_old;
+	 int on;
+	 int nmi_option;
 
-        printk_debug("lpc_init -------->\n");
+        printk_debug("LPC_INIT -------->\n");
         init_pc_keyboard(0x60, 0x64, 0);
 
-#if 0
-            {
-            int i;
-            printk_debug("LPC PCI config \n");
-            for(i=0;i<0xFF;i+=4)
-            {
-              if((i%16)==0)
-              {
-                print_debug("\r\n");
-                print_debug_hex8(i);
-                print_debug("  ");}
-                print_debug_hex32(pci_read_config32(dev,i));
-                print_debug("  ");    
-              }
-              print_debug("\r\n");
-            }
-#endif
-            printk_debug("lpc_init <--------\n");
-            lpc_usb_legacy_init(dev);
-            return;
-	
-       printk_debug("lpc_init\r\n");
-	lpc_common_init(dev);
-       printk_debug("lpc_init2\r\n");
-
-
-#if 0
-	/* posted memory write enable */
-	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0));
+        lpc_usb_legacy_init(dev);
+	 lpc_common_init(dev);
 
-#endif
 	/* power after power fail */
 
-#if 1
+
 	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
@@ -235,7 +187,7 @@
 	}
 	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 	printk_info("set power %s after power fail\n", on?"on":"off");
-#endif
+
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
@@ -249,44 +201,34 @@
 		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 				(on*12)+(on>>1),(on&1)*5);
 	}
- 
-#if 0
-// default is enabled
-	/* Enable Port 92 fast reset */
-	byte = pci_read_config8(dev, 0xe8);
-	byte |= ~(1 << 3);
-	pci_write_config8(dev, 0xe8, byte);
-#endif
-
-	/* Enable Error reporting */
-	/* Set up sync flood detected */
-	byte = pci_read_config8(dev, 0x47);
-	byte |= (1 << 1);
-	pci_write_config8(dev, 0x47, byte);
-
-	/* Set up NMI on errors */
-	byte = inb(0x70); // RTC70
-	byte_old = byte;
-	nmi_option = NMI_OFF;
-	get_option(&nmi_option, "nmi");
-	if (nmi_option) {
-		byte &= ~(1 << 7); /* set NMI */
-	} else {
-		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
-	}
-	if( byte != byte_old) {
-		outb(0x70, byte);
-	}
 
-	/* Initialize the real time clock */
-	rtc_init(0);
+        /* Enable Error reporting */
+        /* Set up sync flood detected */
+        byte = pci_read_config8(dev, 0x47);
+        byte |= (1 << 1);
+        pci_write_config8(dev, 0x47, byte);
+
+        /* Set up NMI on errors */
+        byte = inb(0x70); // RTC70
+        byte_old = byte;
+        nmi_option = NMI_OFF;
+        get_option(&nmi_option, "nmi");
+        if (nmi_option) {
+                byte &= ~(1 << 7); /* set NMI */
+        } else {
+                byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+        }
+        if( byte != byte_old) {
+                outb(0x70, byte);
+        }
 
-	/* Initialize isa dma */
-	isa_dma_init();
+        /* Initialize the real time clock */
+        rtc_init(0);
 
-	/* Initialize the High Precision Event Timers */
-//	enable_hpet(dev);
+        /* Initialize isa dma */
+        isa_dma_init();
 
+        printk_debug("LPC_INIT <--------\n");
 }
 
 static void sis966_lpc_read_resources(device_t dev)
@@ -403,38 +345,6 @@
 	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC,
 };
 
-static const struct pci_driver lpc_driver_pro __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_PRO,
-};
-
-static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_2,
-};
-static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_3,
-};
-static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_4,
-};
-static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_5,
-};
-static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_6,
-};
-
 static struct device_operations lpc_slave_ops  = {
 	.read_resources	= sis966_lpc_read_resources,
 	.set_resources	= pci_dev_set_resources,
@@ -443,9 +353,3 @@
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
-
-static const struct pci_driver lpc_driver_slave __pci_driver = {
-	.ops	= &lpc_slave_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_SLAVE,
-};
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_nic.c	2007-11-01 13:55:57.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	2007-11-01 13:55:57.000000000 -0600
@@ -35,16 +35,16 @@
 
 
 uint8_t	SiS_SiS191_init[6][3]={
-{0x04, 0xFF, 0x07},					 
-{0x2C, 0xFF, 0x39},					 
-{0x2D, 0xFF, 0x10},					 
-{0x2E, 0xFF, 0x91},					 
+{0x04, 0xFF, 0x07},
+{0x2C, 0xFF, 0x39},
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x91},
 {0x2F, 0xFF, 0x01},
 {0x00, 0x00, 0x00}					//End of table
 };
 
-#if 1
-#define StatusReg       0x1    
+
+#define StatusReg       0x1
 #define SMI_READ	0x0
 #define SMI_REQUEST	0x10
 #define TRUE            1
@@ -56,7 +56,7 @@
 void writeApcByte(int addr, uint8_t value)
 {
     outb(addr,0x78);
-    outb(value,0x79); 
+    outb(value,0x79);
 }
 uint8_t readApcByte(int addr)
 {
@@ -72,11 +72,11 @@
 
 // enable APC in south bridge sis966 D2F0
 
-    outl(0x80001048,0xcf8);  
+    outl(0x80001048,0xcf8);
     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
 
     printk_debug("MAC addr in APC = ");
-    for(i = 0x9 ; i <=0xe ; i++) 
+    for(i = 0x9 ; i <=0xe ; i++)
     {
         printk_debug("%2.2x",readApcByte(i));
     }
@@ -85,9 +85,9 @@
     /* Set APC Reload */
     writeApcByte(0x7,readApcByte(0x7)&0xf7);
     writeApcByte(0x7,readApcByte(0x7)|0x0a);
-          	
+
     /* disable APC in south bridge */
-    outl(0x80001048,0xcf8); 
+    outl(0x80001048,0xcf8);
     outl(inl(0xcfc)&0xffffffbf,0xcfc);
 }
 
@@ -100,9 +100,9 @@
     uint8_t   bTmp;
 
     /* enable APC in south bridge sis966 D2F0 */
-    outl(0x80001048,0xcf8);  
+    outl(0x80001048,0xcf8);
     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
-          
+
     for(i = 0 ; i <3; i++)
     {
        addr=0x9+2*i;
@@ -114,13 +114,13 @@
     /* Set APC Reload */
     writeApcByte(0x7,readApcByte(0x7)&0xf7);
     writeApcByte(0x7,readApcByte(0x7)|0x0a);
-          	
+
     /* disable APC in south bridge */
-    outl(0x80001048,0xcf8); 
+    outl(0x80001048,0xcf8);
     outl(inl(0xcfc)&0xffffffbf,0xcfc);
 
-    // CFG reg0x73 bit=1, tell driver MAC Address load to APC 	
-    bTmp = pci_read_config8(dev, 0x73);			
+    // CFG reg0x73 bit=1, tell driver MAC Address load to APC
+    bTmp = pci_read_config8(dev, 0x73);
     bTmp|=0x1;
     pci_write_config8(dev, 0x73, bTmp);
 }
@@ -142,12 +142,12 @@
     uint16_t 	data;
     uint32_t 	i;
     uint32_t 	ulValue;
-    
-    
+
+
     ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
 
     writel( ulValue,base+0x3c);
-		
+
     mdelay(10);
 
     for(i=0 ; i <= LoopNum; i++)
@@ -159,15 +159,15 @@
 
         mdelay(100);
     }
-	
+
     mdelay(50);
 
     if(i==LoopNum)   data=0x10000;
     else{
     	ulValue=readl(base+0x3c);
     	data = (uint16_t)((ulValue & 0xffff0000) >> 16);
-    }			
-    
+    }
+
     return data;
 }
 
@@ -179,9 +179,9 @@
     uint16_t   usData;
 
     uint16_t   tmp;
-	 
 
-	   Read_Cmd = ((phy_reg << 11) |	
+
+	   Read_Cmd = ((phy_reg << 11) |
                        (phy_addr << 6) |
      		       SMI_READ |
      		       SMI_REQUEST);
@@ -189,20 +189,20 @@
            // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
           writel( Read_Cmd,base+0x44);
           //outl( Read_Cmd,tmp+0x44);
-           
+
            // Polling SMI_REQ bit to be deasserted indicated read command completed
            do
            {
 	       // Wait 20 usec before checking status
     	       //StallAndWait(20);
 		   mdelay(20);
-    	       ulValue = readl(base+0x44);	    
-    	       //ulValue = inl(tmp+0x44);	
+    	       ulValue = readl(base+0x44);
+    	       //ulValue = inl(tmp+0x44);
            } while((ulValue & SMI_REQUEST) != 0);
-            //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);          
+            //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
            usData=(ulValue>>16);
 
-	
+
 
 	return usData;
 
@@ -216,55 +216,49 @@
     uint32_t		Read_Cmd;
     uint16_t		usData;
     int		       PhyAddress = 0;
-   
-  
+
+
         // Scan all PHY address(0 ~ 31) to find a valid PHY
         for(PhyAddress = 0; PhyAddress < 32; PhyAddress++)
-        {  
-		usData=phy_read(base,PhyAddress,StatusReg);  // Status register is a PHY's register(offset 01h)      
-           
-           // Found a valid PHY 
-     
+        {
+		usData=phy_read(base,PhyAddress,StatusReg);  // Status register is a PHY's register(offset 01h)
+
+           // Found a valid PHY
+
            if((usData != 0x0) && (usData != 0xffff))
            {
                bFoundPhy = TRUE;
                break;
            }
         }
-//        printk_debug(" PHY_Addr=%x\n",PhyAddress);
 
-	//usData=phy_read(base,PhyAddress,0x0);
-	//printk_debug("PHY=%x\n",usData);
 
 	if(!bFoundPhy)
 	{
 	    printk_debug("PHY not found !!!! \n");
-	   // DisableMac();
 	}
 
        *PhyAddr=PhyAddress;
-	
+
 	return bFoundPhy;
 }
 
 
 static void nic_init(struct device *dev)
 {
-	uint32_t dword, old;
-	uint32_t mac_h, mac_l;
-	int eeprom_valid = 0;
-	int val;
-	uint16_t  PhyAddr;
-	struct southbridge_sis_sis966_config *conf;
-
-	static uint32_t nic_index = 0;
-
-	uint32_t base;
-	struct resource *res;
-       uint32_t reg;
-	
-	
-printk_debug("SIS NIC init-------->\r\n");
+        uint32_t dword, old;
+        uint32_t mac_h, mac_l;
+        int eeprom_valid = 0;
+        int val;
+        uint16_t  PhyAddr;
+        struct southbridge_sis_sis966_config *conf;
+        static uint32_t nic_index = 0;
+        uint32_t base;
+        struct resource *res;
+        uint32_t reg;
+
+
+        print_debug("NIC_INIT:---------->\n");
 
 
 //-------------- enable NIC (SiS19x) -------------------------
@@ -272,121 +266,91 @@
         uint8_t  temp8;
         int i=0;
         while(SiS_SiS191_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
-					temp8 &= SiS_SiS191_init[i][1];
-					temp8 |= SiS_SiS191_init[i][2];				
-					pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
-					i++;
+	{
+                temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
+                temp8 &= SiS_SiS191_init[i][1];
+                temp8 |= SiS_SiS191_init[i][2];
+                pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
+                i++;
 	};
 }
 //-----------------------------------------------------------
 
-
-
-
 {
-unsigned long  i;
-unsigned long ulValue;
+        unsigned long  i;
+        unsigned long ulValue;
 
-#if 0
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\r\n");
-#endif
 	res = find_resource(dev, 0x10);
 
-	if(!res) return;
-
+	if(!res)
+	{
+		printk_debug("NIC Cannot find resource..\r\n");
+		return;
+	}
 	base = res->base;
-printk_debug("NIC base address %lx\n",base);
-	if(!(val=phy_detect(base,&PhyAddr)))  
-	  {
-	      printk_debug("PHY detect fail !!!!\r\n"); 
-		return;		  
-	   }	
-
-#if 0
-//------------ show op registers ----------------------
-{
-//device_t dev;
-int i;
-//dev = pci_locate_device(PCI_ID(0x1039, 0x5513), 0); 
-printk_debug("NIC OP Registers \n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(readl(base+i));
-    print_debug("  ");    
-}
+        printk_debug("NIC base address %lx\n",base);
 
-}
+	if(!(val=phy_detect(base,&PhyAddr)))
+	{
+	       printk_debug("PHY detect fail !!!!\r\n");
+		return;
+	}
 
-//----------------------------------------------------
-#endif
+        ulValue=readl(base + 0x38L);   //  check EEPROM existing
+
+        if((ulValue & 0x0002))
+        {
+
+          //	read MAC address from EEPROM at first
 
-    ulValue=readl(base + 0x38L);   //  check EEPROM existing
-   
-    if((ulValue & 0x0002))
-    {       
-         
-     //	read MAC address from EEPROM at first
-	
           //	if that is valid we will use that
-			
+
 			printk_debug("EEPROM contents %x \n",ReadEEprom( dev,  base,  0LL));
 			for(i=0;i<3;i++) {
 				//status = smbus_read_byte(dev_eeprom, i);
 				ulValue=ReadEEprom( dev,  base,  i+3L);
-				if (ulValue ==0x10000) break;  // error 
-				
-				MacAddr[i] =ulValue & 0xFFFF;	
-				
+				if (ulValue ==0x10000) break;  // error
+
+				MacAddr[i] =ulValue & 0xFFFF;
+
 			}
-		 
-    }else{
-             // read MAC address from firmware
+        }else{
+                 // read MAC address from firmware
 		 printk_debug("EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
 		 MacAddr[0]=readw(0xffffffc0); // mac address store at here
 		 MacAddr[1]=readw(0xffffffc2);
 		 MacAddr[2]=readw(0xffffffc4);
-    }	
+        }
 
+        set_apc(dev);
 
-#if 0
-//	read MAC address from EEPROM at first
-printk_debug("MAC address in firmware trap \n");
- for( i=0;i<3;i++)
- 	printk_debug(" %4x\n",MacAddr[i]);
- printk_debug("\n");      
-#endif
+        readApcMacAddr();
 
-set_apc(dev);
- 	
-readApcMacAddr();
-
-#if 0
-{
-//device_t dev;
-int i;
-//dev = pci_locate_device(PCI_ID(0x1039, 0x5513), 0); 
-printk_debug("NIC PCI config \n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
+#if DEBUG_NIC
+{
+        int i;
 
+        print_debug("****** NIC PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
+        }
+        print_debug("\r\n");
 }
+
+
 #endif
 
 }
 
-printk_debug("nic_init<--------\r\n");
+print_debug("NIC_INIT:<----------\n");
 return;
 
 #define RegStationMgtInf	0x44
@@ -429,161 +393,8 @@
 			}
 		}
 	}
-//	if that is invalid we will read that from romstrap
-	if(!eeprom_valid) {
-		unsigned long mac_pos;
-		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
-		mac_l = readl(mac_pos) + nic_index; // overflow?
-		mac_h = readl(mac_pos + 4);
-
-	}
-#if 1
-//	set that into NIC MMIO
-#define NvRegMacAddrA	0xA8
-#define NvRegMacAddrB	0xAC
-	writel(mac_l, base + NvRegMacAddrA);
-	writel(mac_h, base + NvRegMacAddrB);
-#else
-//	set that into NIC
-	pci_write_config32(dev, 0xa8, mac_l);
-	pci_write_config32(dev, 0xac, mac_h);
-#endif
-
-	nic_index++;
-
-#if CONFIG_PCI_ROM_RUN == 1
-	pci_dev_init(dev);// it will init option rom
-#endif
-
-}
-
-
-
-#else // orginal code
-
-tatic int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
-{
-	uint32_t dword;
-	unsigned loop = 0x100;
-	writel(0x8000, base+0x190); //Clear MDIO lock bit
-	mdelay(1);
-	dword = readl(base+0x190);
-	if(dword & (1<<15)) return -1;
-
-	writel(1, base+0x180);
-	writel((phy_addr<<5) | (phy_reg),base + 0x190);
-	do{
-		dword = readl(base + 0x190);
-		if(--loop==0) return -4;
-	} while ((dword & (1<<15)) );
-
-	dword = readl(base + 0x180);
-	if(dword & 1) return -3;
-
-	dword = readl(base + 0x194);
-
-	return dword;
-
-}
-
-static int phy_detect(uint8_t *base)
-{
-	uint32_t dword;
-	int i;
-	int val;
-	unsigned id;
-	dword = readl(base+0x188);
-	dword &= ~(1<<20);
-	writel(dword, base+0x188);
-
-	phy_read(base, 0, 1);
-
-	for(i=1; i<=32; i++) {
-		int phyaddr = i & 0x1f;
-		val = phy_read(base, phyaddr, 1);
-		if(val<0) continue;
-		if((val & 0xffff) == 0xfffff) continue;
-		if((val & 0xffff) == 0) continue;
-		if(!(val & 1)) {
-			break; // Ethernet PHY
-		}
-		val = phy_read(base, phyaddr, 3);
-		if (val < 0 || val == 0xffff) continue;
-		id = val & 0xfc00;
-		val = phy_read(base, phyaddr, 2);
-		if (val < 0 || val == 0xffff) continue;
-		id |= ((val & 0xffff)<<16);
-		printk_debug("SIS966 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
-//		if((id == 0xe0180000) || (id==0x0032cc00))
-			break;
-	}
-
-	if(i>32) {
-		printk_debug("SIS966 MAC PHY not found\n");
-	}
-
-}
-static void nic_init(struct device *dev)
-{
-	uint32_t dword, old;
-	uint32_t mac_h, mac_l;
-	int eeprom_valid = 0;
-	struct southbridge_sis_sis966_config *conf;
-
-	static uint32_t nic_index = 0;
-
-	uint8_t *base;
-	struct resource *res;
-	
-	res = find_resource(dev, 0x10);
-
-	if(!res) return;
-
-	base = res->base;
-
-	phy_detect(base);
-
-#define NvRegPhyInterface	0xC0
-#define PHY_RGMII	0x10000000
-
-	writel(PHY_RGMII, base + NvRegPhyInterface);
-
-	conf = dev->chip_info;
-
-	if(conf->mac_eeprom_smbus != 0) {
-//	read MAC address from EEPROM at first
-		struct device *dev_eeprom;
-		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
 
-		if(dev_eeprom) {
-		//	if that is valid we will use that
-			unsigned char dat[6];
-			int status;
-			int i;
-			for(i=0;i<6;i++) {
-				status = smbus_read_byte(dev_eeprom, i);
-				if(status < 0) break;
-				dat[i] = status & 0xff;
-			}
-			if(status >= 0) {
-				mac_l = 0;
-				for(i=3;i>=0;i--) {
-					mac_l <<= 8;
-					mac_l += dat[i];
-				}
-				if(mac_l != 0xffffffff) {
-					mac_l += nic_index;
-					mac_h = 0;
-					for(i=5;i>=4;i--) {
-						mac_h <<= 8;
-						mac_h += dat[i];
-					}
-					eeprom_valid = 1;
-				}
-			}
-		}
-	}
-//	if that is invalid we will read that from romstrap
+// if that is invalid we will read that from romstrap
 	if(!eeprom_valid) {
 		unsigned long mac_pos;
 		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
@@ -591,17 +402,12 @@
 		mac_h = readl(mac_pos + 4);
 
 	}
-#if 1
-//	set that into NIC MMIO
+
+// set that into NIC MMIO
 #define NvRegMacAddrA	0xA8
 #define NvRegMacAddrB	0xAC
 	writel(mac_l, base + NvRegMacAddrA);
 	writel(mac_h, base + NvRegMacAddrB);
-#else
-//	set that into NIC
-	pci_write_config32(dev, 0xa8, mac_l);
-	pci_write_config32(dev, 0xac, mac_h);
-#endif
 
 	nic_index++;
 
@@ -611,7 +417,6 @@
 
 }
 
-#endif
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
@@ -636,8 +441,3 @@
 	.vendor	= PCI_VENDOR_ID_SIS,
 	.device	= PCI_DEVICE_ID_SIS_SIS966_NIC1,
 };
-static const struct pci_driver nic_bridge_driver __pci_driver = {
-	.ops	= &nic_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE,
-};
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_pci.c	2007-11-01 13:55:57.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c	2007-11-01 13:55:57.000000000 -0600
@@ -46,19 +46,14 @@
 	dword |= (1<<30); /* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
 
-#if 1
-	//only need (a01,xx]
 	word = pci_read_config16(dev, 0x48);
 	word |= (1<<0); /* MRL2MRM */
 	word |= (1<<2); /* MR2MRM */
 	pci_write_config16(dev, 0x48, word);
-#endif
 
-#if 1
 	dword = pci_read_config32(dev, 0x4c);
 	dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
 	pci_write_config32(dev, 0x4c, dword);
-#endif
 
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_sata.c	2007-11-01 13:55:57.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c	2007-11-01 13:55:57.000000000 -0600
@@ -32,65 +32,64 @@
 #include "sis966.h"
 #include <arch/io.h>
 
-#if 1
 uint8_t	SiS_SiS1183_init[68][3]={
-{0x04, 0x00, 0x05},					 
-{0x09, 0x00, 0x05},					 
-{0x2C, 0x00, 0x39},					 
-{0x2D, 0x00, 0x10},					  
-{0x2E, 0x00, 0x83},					 
-{0x2F, 0x00, 0x11},					 
-{0x90, 0x00, 0x40},					 
-{0x91, 0x00, 0x00},	// set mode				 
-{0x50, 0x00, 0xA2},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0x00, 0x96},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0xF7, 0x00},					 
-{0x56, 0x00, 0xC0},	
+{0x04, 0x00, 0x05},
+{0x09, 0x00, 0x05},
+{0x2C, 0x00, 0x39},
+{0x2D, 0x00, 0x10},
+{0x2E, 0x00, 0x83},
+{0x2F, 0x00, 0x11},
+{0x90, 0x00, 0x40},
+{0x91, 0x00, 0x00},	// set mode
+{0x50, 0x00, 0xA2},
+{0x52, 0x00, 0xA2},
+{0x55, 0x00, 0x96},
+{0x52, 0x00, 0xA2},
+{0x55, 0xF7, 0x00},
+{0x56, 0x00, 0xC0},
 {0x57, 0x00, 0x14},
-{0x67, 0x00, 0x28},					 
-{0x81, 0x00, 0xB3},					 
-{0x82, 0x00, 0x72},					 
-{0x83, 0x00, 0x40},					 
-{0x85, 0x00, 0xB3},					 
-{0x86, 0x00, 0x72},					 
+{0x67, 0x00, 0x28},
+{0x81, 0x00, 0xB3},
+{0x82, 0x00, 0x72},
+{0x83, 0x00, 0x40},
+{0x85, 0x00, 0xB3},
+{0x86, 0x00, 0x72},
 {0x87, 0x00, 0x40},
-{0x88, 0x00, 0xDE},      // after set mode					 
-{0x89, 0x00, 0xB3},					 
-{0x8A, 0x00, 0x72},					 
-{0x8B, 0x00, 0x40},					 
-{0x8C, 0x00, 0xDE},					 
-{0x8D, 0x00, 0xB3},					 
-{0x8E, 0x00, 0x92},					 
-{0x8F, 0x00, 0x40},					 
-{0x93, 0x00, 0x00},					 
-{0x94, 0x00, 0x80},					 
-{0x95, 0x00, 0x08},					 
-{0x96, 0x00, 0x80},					 
+{0x88, 0x00, 0xDE},      // after set mode
+{0x89, 0x00, 0xB3},
+{0x8A, 0x00, 0x72},
+{0x8B, 0x00, 0x40},
+{0x8C, 0x00, 0xDE},
+{0x8D, 0x00, 0xB3},
+{0x8E, 0x00, 0x92},
+{0x8F, 0x00, 0x40},
+{0x93, 0x00, 0x00},
+{0x94, 0x00, 0x80},
+{0x95, 0x00, 0x08},
+{0x96, 0x00, 0x80},
 {0x97, 0x00, 0x08},
-{0x9C, 0x00, 0x80},					 
-{0x9D, 0x00, 0x08},					 
-{0x9E, 0x00, 0x80},					 
-{0x9F, 0x00, 0x08},					 
-{0xA0, 0x00, 0x15},					 
-{0xA1, 0x00, 0x15},					 
-{0xA2, 0x00, 0x15},					 
+{0x9C, 0x00, 0x80},
+{0x9D, 0x00, 0x08},
+{0x9E, 0x00, 0x80},
+{0x9F, 0x00, 0x08},
+{0xA0, 0x00, 0x15},
+{0xA1, 0x00, 0x15},
+{0xA2, 0x00, 0x15},
 {0xA3, 0x00, 0x15},
 
 
-{0xD8, 0xFE, 0x01},	// Com reset				 
+{0xD8, 0xFE, 0x01},	// Com reset
 {0xC8, 0xFE, 0x01},
 {0xE8, 0xFE, 0x01},
 {0xF8, 0xFE, 0x01},
 
-{0xD8, 0xFE, 0x00},	// Com reset				 
+{0xD8, 0xFE, 0x00},	// Com reset
 {0xC8, 0xFE, 0x00},
 {0xE8, 0xFE, 0x00},
 {0xF8, 0xFE, 0x00},
 
 
-{0xC4, 0xFF, 0xFF},    // Clear status					 
+{0xC4, 0xFF, 0xFF},    // Clear status
 {0xC5, 0xFF, 0xFF},
 {0xC6, 0xFF, 0xFF},
 {0xC7, 0xFF, 0xFF},
@@ -98,7 +97,7 @@
 {0xD5, 0xFF, 0xFF},
 {0xD6, 0xFF, 0xFF},
 {0xD7, 0xFF, 0xFF},
-{0xE4, 0xFF, 0xFF},    // Clear status					 
+{0xE4, 0xFF, 0xFF},    // Clear status
 {0xE5, 0xFF, 0xFF},
 {0xE6, 0xFF, 0xFF},
 {0xE7, 0xFF, 0xFF},
@@ -110,126 +109,33 @@
 {0x00, 0x00, 0x00}					//End of table
 };
 
-
-#else 
-uint8_t	SiS_SiS1183_init[5][3]={
-
-{0xD8, 0xFE, 0x01},	// Com reset				 
-{0xC8, 0xFE, 0x01},
-{0xE8, 0xFE, 0x01},
-{0xF8, 0xFE, 0x01},
-
-{0x00, 0x00, 0x00}
-};					//End of table
-
-uint8_t	SiS_SiS1183_init2[21][3]={
-{0xD8, 0xFE, 0x00},			 
-{0xC8, 0xFE, 0x00},
-{0xE8, 0xFE, 0x00},
-{0xF8, 0xFE, 0x00},
-
-
-{0xC4, 0xFF, 0xFF},    // Clear status					 
-{0xC5, 0xFF, 0xFF},
-{0xC6, 0xFF, 0xFF},
-{0xC7, 0xFF, 0xFF},
-{0xD4, 0xFF, 0xFF},
-{0xD5, 0xFF, 0xFF},
-{0xD6, 0xFF, 0xFF},
-{0xD7, 0xFF, 0xFF},
-{0xE4, 0xFF, 0xFF},    // Clear status					 
-{0xE5, 0xFF, 0xFF},
-{0xE6, 0xFF, 0xFF},
-{0xE7, 0xFF, 0xFF},
-{0xF4, 0xFF, 0xFF},
-{0xF5, 0xFF, 0xFF},
-{0xF6, 0xFF, 0xFF},
-{0xF7, 0xFF, 0xFF},
-
-
-{0x00, 0x00, 0x00}					//End of table
-};
-#endif
-
-
-
 static void sata_init(struct device *dev)
 {
-	uint32_t dword;       
+	uint32_t dword;
 	struct southbridge_sis_sis966_config *conf;
 
-	
+
 struct resource *res;
 uint16_t base;
 uint8_t temp8;
-	
+
 	conf = dev->chip_info;
-printk_debug("SATA(SiS1183)_init-------->\r\n");
+        print_debug("SATA_INIT:---------->\n");
 
-#if 1
-//-------------- enable IDE (SiS5513) -------------------------
-{    
-       uint8_t  temp8;
-       int i=0;
+//-------------- enable IDE (SiS1183) -------------------------
+{
+        uint8_t  temp8;
+        int i=0;
 	while(SiS_SiS1183_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
-					temp8 &= SiS_SiS1183_init[i][1];
-					temp8 |= SiS_SiS1183_init[i][2];				
-					pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
-					i++;
-	};
-}
-/*
-mdelay(5);
-{    
-       uint8_t  temp8;
-       int i=0;
-	while(SiS_SiS1183_init2[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS1183_init2[i][0]);
-					temp8 &= SiS_SiS1183_init2[i][1];
-					temp8 |= SiS_SiS1183_init2[i][2];				
-					pci_write_config8(dev, SiS_SiS1183_init2[i][0], temp8);
-					i++;
+	{
+                temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
+                temp8 &= SiS_SiS1183_init[i][1];
+                temp8 |= SiS_SiS1183_init[i][2];
+                pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
+                i++;
 	};
 }
-*/
 //-----------------------------------------------------------
-#endif
-
-
-#if 0
-
-	dword = pci_read_config32(dev, 0x50);
-	/* Ensure prefetch is disabled */
-	dword &= ~((1 << 15) | (1 << 13));
-	if(conf) {
-		if (conf->sata1_enable) {
-			/* Enable secondary SATA interface */
-			dword |= (1<<0);
-			printk_debug("SATA S \t");
-		}
-		if (conf->sata0_enable) {
-			/* Enable primary SATA interface */
-			dword |= (1<<1);
-			printk_debug("SATA P \n");
-		}
-	} else {
-		dword |= (1<<1) | (1<<0);
-		printk_debug("SATA P and S \n");
-	}
-
-
-#if 1
-	dword &= ~(0x1f<<24);
-	dword |= (0x15<<24);
-#endif
-	pci_write_config32(dev, 0x50, dword);
-
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 2;
-	pci_write_config32(dev, 0xf8, dword);
-
-#endif
 
 {
 uint32_t i,j;
@@ -239,33 +145,33 @@
    temp32=0;
    temp32= pci_read_config32(dev, 0xC0);
    for ( j=0;j<0xFFFF;j++);
-   printk_debug("status= %x",temp32);
+   printk_debug("status= %x\n",temp32);
    if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
 }
-printk_debug("\n");
+
 }
 
-#if 0	
+#if DEBUG_SATA
+{
+        int i;
 
-res = find_resource(dev, 0x10);	
-base =(uint16_t ) res->base;
-printk_debug("BASE ADDR %x\n",base);
-base&=0xFFFE;
-printk_debug("SATA status %x\n",inb(base+7));
+        print_debug("****** SATA PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
 
-{
-int i;
-for(i=0;i<0xFF;i+=4)
-{
-    if((i%16)==0)
-    {
-      print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-      print_debug_hex32(pci_read_config32(dev,i));
-      print_debug("  ");
-    }
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
+        }
+        print_debug("\r\n");
 }
 #endif
-printk_debug("sata_init <--------\r\n");
+
+        print_debug("SATA_INIT:<----------\n");
 
 }
 
@@ -293,9 +199,3 @@
 	.vendor	= PCI_VENDOR_ID_SIS,
 	.device	= PCI_DEVICE_ID_SIS_SIS966_SATA0,
 };
-
-static const struct pci_driver sata1_driver __pci_driver = {
-	.ops	= &sata_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_SATA1,
-};
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.h
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_smbus.h	2007-11-01 13:55:57.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.h	2007-11-01 13:55:57.000000000 -0600
@@ -158,14 +158,14 @@
 	}
 };
 
-	global_status_register = inb(smbus_io_base + 0x00); 
+	global_status_register = inb(smbus_io_base + 0x00);
 	byte = inb(smbus_io_base + 0x08);
 
 	if (global_status_register != 0x08) { // lose check, otherwise it should be 0
 		print_debug("Fail");print_debug("\r\t");
 			return -1;
 	}
-		print_debug("Success");print_debug("\r\t");	
+		print_debug("Success");print_debug("\r\t");
 	return byte;
 }
 
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_usb.c	2007-11-01 13:55:57.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c	2007-11-01 13:55:57.000000000 -0600
@@ -30,37 +30,38 @@
 #include <device/pci_ops.h>
 #include "sis966.h"
 
-// From Y.S.
-// PCI R47h-R44h=0001AD54h
-// PCI R4Bh-R48h=00000271h
-uint8_t	SiS_SiS7001_init[15][3]={
-{0x04, 0xFF, 0x07},
+uint8_t	SiS_SiS7001_init[16][3]={
+{0x04, 0x00, 0x07},
+{0x0C, 0x00, 0x08},
+{0x0D, 0x00, 0x20},
+
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
 {0x2E, 0xFF, 0x01},
 {0x2F, 0xFF, 0x70},
+
 {0x44, 0x00, 0x54},
 {0x45, 0x00, 0xAD},
 {0x46, 0x00, 0x01},
 {0x47, 0x00, 0x00},
-{0x48, 0x00, 0x71},
+
+{0x48, 0x00, 0x73},
 {0x49, 0x00, 0x02},
 {0x4A, 0x00, 0x00},
 {0x4B, 0x00, 0x00},
-{0x04, 0x00, 0x07},
+
 {0x00, 0x00, 0x00}					//End of table
 };
 
 static void usb_init(struct device *dev)
 {
+        print_debug("USB 1.1 INIT:---------->\n");
 
 //-------------- enable USB1.1 (SiS7001) -------------------------
 {
         uint8_t  temp8;
         int i=0;
 
-        printk_debug("USB1.1_Init\n");
-
 	 while(SiS_SiS7001_init[i][0] != 0)
 	 {				temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
 					temp8 &= SiS_SiS7001_init[i][1];
@@ -71,23 +72,28 @@
 }
 //-----------------------------------------------------------
 
-#if 0
+#if DEBUG_USB
 {
-    int i;
-    printk_debug("\nUSB 1.1 PCI config");
-    for(i=0;i<0xFF;i+=4)
-    {    
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug(": ");}
-            print_debug_hex32(pci_read_config32(dev,i));
-            print_debug("  ");
+        int i;
+
+        print_debug("****** USB 1.1 PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
         }
         print_debug("\r\n");
-    }
+}
 #endif
-
+        print_debug("USB 1.1 INIT:<----------\n");
 }
+
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c
===================================================================
--- LinuxBIOSv2.orig/src/southbridge/sis/sis966/sis966_usb2.c	2007-11-01 13:55:57.000000000 -0600
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c	2007-11-01 13:55:57.000000000 -0600
@@ -36,11 +36,9 @@
 
 extern struct ehci_debug_info dbg_info;
 
-// From Y.S.
-// PCI R43h-R40h=00000020h
-// PCI R4Bh-R48h=00078010h
-uint8_t	SiS_SiS7002_init[19][3]={
+uint8_t	SiS_SiS7002_init[22][3]={
 {0x04, 0x00, 0x06},
+{0x0D, 0x00, 0x00},
 
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
@@ -52,12 +50,15 @@
 {0x76, 0x00, 0x00},
 {0x77, 0x00, 0x00},
 
+{0x7A, 0x00, 0x00},
+{0x7B, 0x00, 0x00},
+
 {0x40, 0x00, 0x20},
 {0x41, 0x00, 0x00},
 {0x42, 0x00, 0x00},
 {0x43, 0x00, 0x08},
 
-{0x44, 0x00, 0x64},
+{0x44, 0x00, 0x04},
 
 {0x48, 0x00, 0x10},
 {0x49, 0x00, 0x80},
@@ -67,56 +68,58 @@
 {0x00, 0x00, 0x00}					//End of table
 };
 
-
-
 static void usb2_init(struct device *dev)
 {
-       uint8_t *base;
-	struct resource *res;
-	uint32_t temp32;
+        uint8_t *base;
+        struct resource *res;
+        uint32_t temp32;
 
+        print_debug("USB 2.0 INIT:---------->\n");
 
 //-------------- enable USB2.0 (SiS7002) -------------------------
 {
         uint8_t  temp8;
         int i=0;
 
-        printk_debug("USB2.0_Init\n");
-
-	while(SiS_SiS7002_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
-					temp8 &= SiS_SiS7002_init[i][1];
-					temp8 |= SiS_SiS7002_init[i][2];
-					pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
-					i++;
-	};
+        while(SiS_SiS7002_init[i][0] != 0)
+        {
+                temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
+                temp8 &= SiS_SiS7002_init[i][1];
+                temp8 |= SiS_SiS7002_init[i][2];
+                pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
+                i++;
+        };
 }
 
-       res = find_resource(dev, 0x10);
-	if(!res)
-		return;
-
-	base =(uint8_t *) res->base;
-	printk_debug("base = %08x\n", base);
-       writel(0x2,base+0x20);
+        res = find_resource(dev, 0x10);
+        if(!res)
+                return;
+
+        base =(uint8_t *) res->base;
+        printk_debug("base = %08x\n", base);
+        writel(0x2,base+0x20);
 //-----------------------------------------------------------
 
-#if 0
+#if DEBUG_USB2
 {
-    int i;
-    printk_debug("\nUSB 2.0 PCI config");
-    for(i=0;i<0xFF;i+=4)
-    {
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug(": ");}
-            print_debug_hex32(pci_read_config32(dev,i));
-            print_debug("  ");
+        int i;
+
+        print_debug("****** USB 2.0 PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
         }
         print_debug("\r\n");
-    }
+}
 #endif
-
+        print_debug("USB 2.0 INIT:<----------\n");
 }
 
 static void usb2_set_resources(struct device *dev)
@@ -164,5 +167,5 @@
 static const struct pci_driver usb2_driver __pci_driver = {
 	.ops	= &usb2_ops,
 	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_EHCI,
+	.device	= PCI_DEVICE_ID_SIS_SIS966_USB2,
 };
Index: LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/COPYRIGHT
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/COPYRIGHT	2007-11-01 13:55:57.000000000 -0600
@@ -0,0 +1,32 @@
+
+Copyright Notice
+----------------
+
+The copy of this 6330VGA.rom versions 3.42 (the "Software") is provided
+for your convenience.  In case of any redistribution of the Software, the
+following notices shall be included.
+
+COPYRIGHT NOTICE, DISCLAIMER, and LICENSE:
+
+6330VGA.rom versions 3.42 is Copyright (c) 2007 Silicon Integrated Systems
+Corporation ("SiS") and are distributed according to the following disclaimer:
+
+The Software is supplied "AS IS".  SiS disclaim all warranties, expressed or
+implied, including, without limitation, the warranties of merchantability and
+of fitness for any purpose. SiS assume no liability for direct, indirect,
+incidental, special, exemplary, or consequential damages, which may result
+from the use of the Software, even if advised of the possibility of such
+damage.
+
+Permission is hereby granted to use, copy, modify, and distribute the object
+code of the Software, for any purpose, without fee, subject to the following
+restrictions:
+
+1.The origin of this object code must not be misrepresented.
+
+2.No permission is granted for disassemble, reverse engineering or decompile
+  the Software under any circumstances.
+
+3.This Copyright notice may not be removed or altered from any source or
+  altered source distribution.
+
Index: LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- LinuxBIOSv2.orig/targets/gigabyte/ga_2761gxdk/Config.lb	2007-11-01 13:55:57.000000000 -0600
+++ LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/Config.lb	2007-11-01 13:55:57.000000000 -0600
@@ -3,6 +3,8 @@
 ##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
+## Written by Morgan Tsai <my_tsai at sis.com> for SiS.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -23,38 +25,22 @@
 mainboard gigabyte/ga_2761gxdk
 
 romimage "normal"
-#       48K for VGA BIOS
-         option ROM_SIZE = 475136
-#       48K for SCSI FW and 48K for ATI ROM
-#        option ROM_SIZE = 425984 
-#       64K for Etherboot
-#        option ROM_SIZE = 458752 
-#       44k for atixx.rom
-#        option ROM_SIZE = 479232
-#       32k for vbios
-#        option ROM_SIZE = 491520
+#       32K for VGA BIOS
+        option ROM_SIZE = (512*1024 - 32*1024)
 
         option USE_FAILOVER_IMAGE=0
-#	option ROM_IMAGE_SIZE=0x13800
-#	option ROM_IMAGE_SIZE=0x18800
-#	option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x20000
-#	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x40000
-	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+        option ROM_IMAGE_SIZE=0x20000
+        option XIP_ROM_SIZE=0x40000
+        option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
         payload ../../../../payloads/filo_uda1.elf
 end
 
-romimage "fallback" 
+romimage "fallback"
         option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=1
-#	option ROM_IMAGE_SIZE=0x13800
-#	option ROM_IMAGE_SIZE=0x18800
-#       option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x20000
-#	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x40000
-	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+        option USE_FALLBACK_IMAGE=1
+        option ROM_IMAGE_SIZE=0x20000
+        option XIP_ROM_SIZE=0x40000
+        option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
         payload ../../../../payloads/filo_uda1.elf
 end
 
@@ -66,5 +52,5 @@
         option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#       buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+        buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"

From jordan.crouse at amd.com  Thu Nov  1 21:02:54 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 1 Nov 2007 14:02:54 -0600
Subject: [LinuxBIOS] Broken build for kexec-boot-loader on tyan s2891
In-Reply-To: <02d301c81cac$72f1eff0$1223040a@chimp>
References: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
	<02d201c81ca5$437e4770$1223040a@chimp>
	<20071101165626.GC21220@cosmic.amd.com>
	<02d301c81cac$72f1eff0$1223040a@chimp>
Message-ID: <20071101200254.GM21220@cosmic.amd.com>

On 01/11/07 11:27 -0600, Myles Watson wrote:
> If I configure tyan_s2891 to have Linux As Bootloader and include the kexec
> tools, the build fails. Here's the last bit of the build log
> 
> gcc --32 -c -o kexec/x86-setup-32.o kexec/x86-setup-32.S
> cc1: error: unrecognized command line option "-f32"
> 
> Is this another place where there should be quotes around flags being passed
> around?

It looks like it got the ASFLAGS when it wanted the CFLAGS.  I'll look
at this along with the other problems.

> Myles
> 
> 
> 
> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
> 
> 

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From rminnich at gmail.com  Thu Nov  1 21:48:31 2007
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Nov 2007 13:48:31 -0700
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <20071101192324.GH21220@cosmic.amd.com>
References: <13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw> <4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101153859.GG12393@cosmic.amd.com>
	<20071101183323.30359.qmail@stuge.se>
	<20071101192324.GH21220@cosmic.amd.com>
Message-ID: <13426df10711011348t577af1d4m13b6c832f9864c64@mail.gmail.com>

On 11/1/07, Jordan Crouse <jordan.crouse at amd.com> wrote:

> My vote is to make it web accessable and thats it.  I want to hear from
> others, though.
>

I agree. Make it accessible via wget at linuxbios.org, and put the
wget into buildrom, and life is good ...

ron



From svn at openbios.org  Fri Nov  2 01:31:11 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 01:31:11 +0100
Subject: [LinuxBIOS] r2925 - trunk/LinuxBIOSv2/src/southbridge/sis/sis966
Message-ID: <mailman.819.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 01:31:11 +0100 (Fri, 02 Nov 2007)
New Revision: 2925

Modified:
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
Log:
trivial fix for the .data problem

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-01 15:15:14 UTC (rev 2924)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-02 00:31:11 UTC (rev 2925)
@@ -23,7 +23,7 @@
 
 #define SMBUS0_IO_BASE	0x8D0
 
-uint8_t	SiS_LPC_init[33][3]={
+static const uint8_t SiS_LPC_init[33][3]={
 {0x04, 0xF8, 0x07},					//Reg 0x04
 {0x45, 0x00, 0x00},					//Reg 0x45			//Enable Rom Flash
 {0x46, 0x00, 0x3D},					//Reg 0x46
@@ -59,7 +59,7 @@
 {0xDF, 0x00, 0xAA},					//Reg 0xDF
 {0x00, 0x00, 0x00}					//End of table
 };
-uint8_t	SiS_NBPCIE_init[43][3]={
+static const uint8_t	SiS_NBPCIE_init[43][3]={
 {0x3D, 0x00, 0x00},					//Reg 0x3D
 {0x1C, 0xFE, 0x01},					//Reg 0x1C
 {0x1D, 0xFE, 0x01},					//Reg 0x1D
@@ -105,7 +105,7 @@
 {0x4F, 0x00, 0x00},					//Reg 0x4F
 {0x00, 0x00, 0x00}					//End of table
 };
-uint8_t	SiS_ACPI_init[10][3]={
+static const uint8_t	SiS_ACPI_init[10][3]={
 {0x1B, 0xBF, 0x40},					//Reg 0x1B
 {0x84, 0x00, 0x0E},					//Reg 0x84
 {0x85, 0x00, 0x29},					//Reg 0x85
@@ -117,7 +117,7 @@
 {0x6F, 0xFF, 0x14},					//Reg 0x6F
 {0x00, 0x00, 0x00}					//End of table
 };
-uint8_t	SiS_SBPCIE_init[13][3]={
+static const uint8_t	SiS_SBPCIE_init[13][3]={
 {0x48, 0x00 ,0x07},					//Reg 0x48
 {0x49, 0x00 ,0x06},					//Reg 0x49
 {0x4A, 0x00 ,0x0C},					//Reg 0x4A
@@ -135,7 +135,7 @@
 
 
 #if 1
-uint8_t	SiS_NB_init[56][3]={
+static const uint8_t	SiS_NB_init[56][3]={
 {0x04, 0x00 ,0x07},					//Reg 0x04
 {0x05, 0x00 ,0x00},					//Reg 0x05 // alex
 {0x0D, 0x00 ,0x20},					//Reg 0x0D
@@ -201,7 +201,7 @@
 };
 
 #else
-uint8_t	SiS_NB_init[61][3]={
+static const uint8_t	SiS_NB_init[61][3]={
 {0x04, 0x00 ,0x07},					//Reg 0x04
 {0x05, 0x00 ,0x00},					//Reg 0x05 // alex
 {0x0D, 0x00 ,0x20},					//Reg 0x0D
@@ -270,7 +270,7 @@
 
 #endif
 #if 1
-uint8_t SiS_NBAGP_init[34][3]={
+static const uint8_t SiS_NBAGP_init[34][3]={
 {0xCF, 0xDF, 0x00},      //HT issue
 {0x06, 0xDF, 0x20},
 {0x1E, 0xDF, 0x20},
@@ -314,7 +314,7 @@
 #else
 
 //uint8_t SiS_NBAGP_init[53][3]={
-uint8_t SiS_NBAGP_init[40][3]={
+static const uint8_t SiS_NBAGP_init[40][3]={
 {0x04, 0x00 ,0x07},					//Reg 0x04
 {0x05, 0x00 ,0x01},					//Reg 0x05 // alex
 
@@ -381,7 +381,7 @@
 
 #endif
 
-uint8_t	SiS_ACPI_2_init[56][3]={
+static const uint8_t	SiS_ACPI_2_init[56][3]={
 {0x00, 0x00, 0xFF},					//Reg 0x00
 {0x01, 0x00, 0xFF},					//Reg 0x01
 {0x02, 0x00, 0x00},					//Reg 0x02
@@ -441,7 +441,7 @@
 };
 
 #if 0
-uint8_t	SiS_SiS1183_init[60][3]={
+static const uint8_t	SiS_SiS1183_init[60][3]={
 {0x04, 0x00, 0x05},					 
 {0x09, 0x00, 0x05},					 
 {0x2C, 0x00, 0x39},					 
@@ -511,7 +511,7 @@
 
 #else
 
-uint8_t	SiS_SiS1183_init[44][3]={
+static const uint8_t	SiS_SiS1183_init[44][3]={
 {0x04, 0x00, 0x05},					 
 {0x09, 0x00, 0x05},					 
 {0x2C, 0x00, 0x39},					 




From info at coresystems.de  Fri Nov  2 02:25:01 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 02 Nov 2007 02:25:01 +0100
Subject: [LinuxBIOS] r2925 build service
Message-ID: <E1InlHR-0000hv-JA@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2925 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
trivial fix for the .data problem

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=hdama&vendor=arima
Compilation of gigabyte:ga_2761gxdk has been fixed
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=dk8x&vendor=iwill
Compilation of newisys:khepri is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=khepri&vendor=newisys


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From my_tsai at sis.com  Fri Nov  2 05:02:06 2007
From: my_tsai at sis.com (Morgan Tsai /SiS)
Date: Fri, 2 Nov 2007 12:02:06 +0800
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
References: <001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>
	<20071004025851.GA32267@greenwood>
	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
Message-ID: <009201c81d05$27559020$0200a8c0@sis.com.tw>

Dear folks/

Here is the redone patch by TortoiseSVN, please try it again.
Another tarball is the source tree of sis revised files (include VGA bios).

It's identical for these two attachments.
Please ignore the patch yesterday, becasue 2924 has a trivial fix.
The newest I have is 2925.


Signed-off-by: Morgan Tsai <my_tsai at sis.com>



Morgan

----- Original Message ----- 
From: "Jordan Crouse" <jordan.crouse at amd.com>
To: "Morgan Tsai /SiS" <my_tsai at sis.com>
Cc: <linuxbios at linuxbios.org>; "ron minnich" <rminnich at gmail.com>; "Stefan 
Reinauer" <stepan at coresystems.de>; "Carl-Daniel Hailfinger" 
<c-d.hailfinger.devel.2006 at gmx.net>; "Ray Wang /SiS" <ray_wang at sis.com>; 
"Dennis Chang /SiS" <ktchang at sis.com>; "Eric Lin /SiS" <ericlin at sis.com>
Sent: Friday, November 02, 2007 4:02 AM
Subject: Re: GIGABYTE GA-2761GXDK


> On 01/11/07 20:24 +0800, Morgan Tsai /SiS wrote:
>> Change Log:
>>
>> 1. Add integrated VGA bios within redistributed notice,
>> please help to put '6330VGA.rom' into targets/gigabyte/ga_2761gxdk/
>> 2. Rename sisnb.c to sis761.c
>> 3. Delete many mis-definition for sis device in
>> src/include/device/pci_ids.h
>> 4. Trim trailing spaces for all files
>>
>>
>>
>> Signed-off-by: Morgan Tsai <my_tsai at sis.com>
>
> Something strange happened to the patch, I think the mailserver
> may have mangled it;  it didn't apply cleanly to the tree.  I fixed it up,
> here is the same patch again that will apply against current SVN,
> and compiles on my box.
>
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>
> Jordan
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From rminnich at gmail.com  Fri Nov  2 05:42:16 2007
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Nov 2007 21:42:16 -0700
Subject: [LinuxBIOS] Add support for a 64-bit target for Serengeti
	Cheetah
In-Reply-To: <20071101165626.GC21220@cosmic.amd.com>
References: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
	<02d201c81ca5$437e4770$1223040a@chimp>
	<20071101165626.GC21220@cosmic.amd.com>
Message-ID: <13426df10711012142x505c18camab2ca2280e475246@mail.gmail.com>

I've had really bad luck with buildroot lately. It seems to have
passed some sort of event horizon of mass, and it is really easy to
drive yourself into  corner to the point that you have a broken build,
a broken bulid system, nothing compiles, and nothing works -- and your
every attempt at reconfiguration only makes it worse. I am not sure
what the future of buildroot will be.

So, I am happy that buildrom can do what it does.

ron



From rminnich at gmail.com  Fri Nov  2 05:51:37 2007
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Nov 2007 21:51:37 -0700
Subject: [LinuxBIOS] Patch quality
In-Reply-To: <2831fecf0711010732x5ed72f3avb60a4d67b0853e61@mail.gmail.com>
References: <47230218.70605@assembler.cz>
	<13426df10710280906k3ec894bcu594da0998f7ea9e3@mail.gmail.com>
	<20071029155738.GE11779@cosmic.amd.com>
	<13426df10710291551w6f2a453fn88fe4ecd7258037d@mail.gmail.com>
	<20071030012850.GA24090@coresystems.de> <47268EC7.9080202@gmail.com>
	<13426df10710291856k6a5f5f5cne391cce72e8cfb96@mail.gmail.com>
	<20071030022453.GA21022@coresystems.de>
	<20071030170347.GA12444@cosmic.amd.com>
	<2831fecf0711010732x5ed72f3avb60a4d67b0853e61@mail.gmail.com>
Message-ID: <13426df10711012151q1e6db0fn11be4c5c437ab088@mail.gmail.com>

On 11/1/07, Myles Watson <myles at pel.cs.byu.edu> wrote:
> On 10/30/07, Jordan Crouse <jordan.crouse at amd.com> wrote:
> > On 30/10/07 03:24 +0100, Stefan Reinauer wrote:
> > > An important issue will be to get the code compiling. I was not
> > > successful doing so due to the old ld overlapping sections friend.
> >
> > We've seen this before -  Whats happening here is that the ld script
> > snippet for .id is going into the ld script after the snippet for .reset,
> > so to LD, the current pointer appears to jump backwards, and it can't figure
> > out the math correctly.  The immediately work around is to re-arrange
> > the order of the .id and the .reset snippets in the script.  I believe this
> > was fixed in later versions of ld - I can't get it to happen on my trusty
> > Ubuntu Gutsy box.
>
> When I get this error, it is because my ROM_IMAGE_SIZE is set too
> small. Increasing it fixes the problem for me.


It turns out none of these was the problem, for me, and I just figured
it out this morning. Also, I am not totally convinced the .reset and
.id section ordering in the ldscript is really a problem -- the start
of each is pretty clearly laid out in the ldscript, and that code has
been running that way for many years now. Were you folks seeing .reset
and .id overlap, or .reset and .data? Do you have output I can see?

In my case I was getting overlapping sections of .reset and .data.

There should be no .data sections in the rom code. That's the first
hint of trouble. A quick grep of .data in normal/cache_as_ram_auto.inc
was enough to find the problem.

There are several u8 arrays in the sis southbridge early smbus code.
This code is compiled into cache_as_ram_auto.c. Because it is not
declared const, it gets passed through and compiled as a .data
section. ld does not know where to put it, since the ldscript for the
cache as ram code (ldscript.ld) only deals with .rom.text, .rom.data,
and so on.

The fix is simple: declare the u8 arrays as const. This gets them
passed in as rom.data, and all the conflicts on this board disappear.
The board is building just fine for me now, and I have checked the
last 16 bytes and can see the jump to the start of the rom code. In
other words linuxbios.rom looks good.

I will test again tomorrow morning (or tonight, who knows) with
Morgan's patches to 2925.

thanks

ron



From corey.osgood at gmail.com  Fri Nov  2 07:02:30 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 02 Nov 2007 02:02:30 -0400
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
Message-ID: <472ABD76.9020705@gmail.com>

This patch is some small changes to the vt8237r to prepare it for
the Jetway J7F2 patch that should be coming soon, and also moves most
defines into vt8237r.h. I've changed some of the values from u32 to u8,
because that's all they should ever need to be. Also includes
doxygenized comments!

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>



From corey.osgood at gmail.com  Fri Nov  2 07:03:18 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 02 Nov 2007 02:03:18 -0400
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472ABD76.9020705@gmail.com>
References: <472ABD76.9020705@gmail.com>
Message-ID: <472ABDA6.4000602@gmail.com>

Corey Osgood wrote:
> This patch is some small changes to the vt8237r to prepare it for
> the Jetway J7F2 patch that should be coming soon, and also moves most
> defines into vt8237r.h. I've changed some of the values from u32 to u8,
> because that's all they should ever need to be. Also includes
> doxygenized comments!
>
> Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
>   

And here's the patch, for real this time!

-Corey

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From kbaski at yahoo.com  Fri Nov  2 07:05:27 2007
From: kbaski at yahoo.com (Baski)
Date: Thu, 1 Nov 2007 23:05:27 -0700 (PDT)
Subject: [LinuxBIOS] secondary cpu question
In-Reply-To: <mailman.462.1193976196.23407.linuxbios@linuxbios.org>
Message-ID: <281846.60052.qm@web51611.mail.re2.yahoo.com>

I have a question on secondary cpu exploitation.
  At the end of secondary_start(), I'm not issuing 'stop_this_cpu' to apic_id 1.  So this second 
  core is still up and running.  Just before jumping to elfboot, I want to run a small code, say,
  'while(1){send a char to com1 port}' on this second core and let the BSP load and run linux.
  the secondary eip is still valid.  I'll not show this core in mptable(thanks 2 Dr.YH).
  Any help is greatly appreciated.
  Thanks - Baski
   

 __________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
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From r.marek at assembler.cz  Fri Nov  2 08:49:00 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 02 Nov 2007 08:49:00 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472ABDA6.4000602@gmail.com>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
Message-ID: <472AD66C.4030100@assembler.cz>

Hi just a quick question,
Did you check with SVN version that it still needs warming up?

Thanks,

R.



From svn at openbios.org  Fri Nov  2 10:48:15 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 10:48:15 +0100
Subject: [LinuxBIOS] r2926 - trunk/LinuxBIOSv2/src/mainboard/newisys/khepri
Message-ID: <mailman.820.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 10:48:14 +0100 (Fri, 02 Nov 2007)
New Revision: 2926

Added:
   trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c
Modified:
   trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c
Log:
This patch fixes the superio of the khepri 2100e as detected:
> superiotool r2922
> Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e

Don't use the non-working trident driver for the blade3d (onboard vga 
in the rom emulator has not been tested either)

It also adds some preliminary CAR support to the board, so it has a chance to
build again.

This board was broken since a couple of months, and the changes are minimal, so
I consider this a trivial change -- It doesn't change anything that was used,
obviously

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb	2007-11-02 00:31:11 UTC (rev 2925)
+++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb	2007-11-02 09:48:14 UTC (rev 2926)
@@ -47,8 +47,27 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-dir /drivers/trident/blade3d
+if USE_DCACHE_RAM
 
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
+ 
 ##
 ## Romcc output
 ##
@@ -71,14 +90,28 @@
 	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
 
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
@@ -91,23 +124,36 @@
 end
 
 ### Should this be in the northbridge code?
+if USE_DCACHE_RAM
+else
 mainboardinit arch/i386/lib/cpu_reset.inc
-
+end
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
+if USE_DCACHE_RAM
+	ldscript /arch/i386/lib/failover.lds
+else
+	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end
+end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -116,6 +162,20 @@
 ##
 ## Setup RAM
 ##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
+##
+## Setup RAM
+##
+
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 mainboardinit cpu/x86/mmx/enable_mmx.inc
 mainboardinit cpu/x86/sse/enable_sse.inc
@@ -123,13 +183,22 @@
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
 
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
+end
+
 config chip.h
 
+# FIXME: ROM for onboard VGA
+
 chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
+	end
+
 	device pci_domain 0 on
 		chip northbridge/amd/amdk8
 			device pci 18.0 on end # LDT 0 
@@ -148,36 +217,45 @@
 						device pci 1.0 on end
 					end
 					device pci 1.0 on
-						chip superio/nsc/pc87360
-							device pnp 2e.0 off    # Floppy 
-								 io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
 							end
-							device pnp 2e.1 off     # Parallel Port
-								 io 0x60 = 0x378
-								irq 0x70 = 7
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
 							end
-							device pnp 2e.2 off     # Com 2
-								 io 0x60 = 0x2f8
-								irq 0x70 = 3
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
 							end
-							device pnp 2e.3 on      # Com 1
-								 io 0x60 = 0x3f8
-								irq 0x70 = 4
+                	        			device pnp 2e.3 on #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
 							end
-							device pnp 2e.4 off end # SWC
-							device pnp 2e.5 off end # Mouse
-							device pnp 2e.6 on      # Keyboard
-								 io 0x60 = 0x60
-								 io 0x62 = 0x64
-								irq 0x70 = 1
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
 							end
-							device pnp 2e.7 off end # GPIO
-							device pnp 2e.8 off end # ACB
-							device pnp 2e.9 off end # FSCM
-							device pnp 2e.a off end # WDT  
-			
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  GPIO2
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
 						end
 					end
 					device pci 1.1 on end
@@ -201,13 +279,5 @@
 			device pci 19.3 on end
 		end
 	end 
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-		chip cpu/amd/socket_940
-			device apic 1 on end
-		end
-	end
 end
 

Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb	2007-11-02 00:31:11 UTC (rev 2925)
+++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb	2007-11-02 09:48:14 UTC (rev 2926)
@@ -7,6 +7,7 @@
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
 uses FALLBACK_SIZE
@@ -18,6 +19,7 @@
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses PAYLOAD_SIZE
 uses _ROMBASE
 uses XIP_ROM_SIZE
@@ -31,6 +33,8 @@
 uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
@@ -40,11 +44,20 @@
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
 uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
 
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
 ###
@@ -59,6 +72,8 @@
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
+#default FALLBACK_SIZE=131072
+#256K
 default FALLBACK_SIZE=0x40000
 
 ##
@@ -75,7 +90,7 @@
 ## Build code to export a programmable irq routing table
 ##
 default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default IRQ_SLOT_COUNT=15
 
 ##
 ## Build code to export an x86 MP table
@@ -100,10 +115,30 @@
 ## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_CPUS=4
 default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
 
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#1G memory hole
+default HW_MEM_HOLE_SIZEK=0x100000
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+
 ##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=0
+
+##
 ## Build code to setup a generic IOAPIC
 ##
 default CONFIG_IOAPIC=1
@@ -113,6 +148,8 @@
 ##
 default MAINBOARD_PART_NUMBER="Khepri"
 default MAINBOARD_VENDOR="Newisys"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
 
 ###
 ### LinuxBIOS layout values
@@ -157,6 +194,11 @@
 default HOSTCC="gcc"
 
 ##
+## Disable the gdb stub by default
+## 
+default CONFIG_GDB_STUB=0
+
+##
 ## The Serial Console
 ##
 

Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c	2007-11-02 00:31:11 UTC (rev 2925)
+++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c	2007-11-02 09:48:14 UTC (rev 2926)
@@ -19,11 +19,11 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include <cpu/amd/model_fxx_rev.h>
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"
 
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 static void hard_reset(void)
 {
@@ -115,7 +115,7 @@
 	    	k8_init_and_stop_secondaries();
 	}
 	/* Setup the console */
-	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 	uart_init();
 	console_init();
 

Added: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c	2007-11-02 09:48:14 UTC (rev 2926)
@@ -0,0 +1,249 @@
+/*
+ * This code is derived from the Tyan s2882 cache_as_ram_auto.c
+ * Adapted by Stefan Reinauer <stepan at coresystems.de>
+ * Additional (C) 2007 coresystems GmbH 
+ */
+#define ASSEMBLY 1
+#define __ROMCC__
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#if 0
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+	if (is_cpu_pre_c0()) {
+		/* Set the memreset low */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		/* Ensure the BIOS has control of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
+	else {
+		/* Ensure the CPU has controll of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		/* Set memreset_high */
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		udelay(90);
+	}
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#define QRANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+ /* newisys khepri does not want the default */
+#include "resourcemap.c" 
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+#include "cpu/amd/dualcore/dualcore.c"
+
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        /* Setup the ck804 */
+        amd8111_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+//        post_code(0x22);
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+//        post_code(0x23);
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+//        post_code(0x25);
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr [] = {
+			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
+			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+#endif
+	};
+
+        int needs_reset;
+        unsigned bsp_apicid = 0;
+
+        struct mem_controller ctrl[8];
+        unsigned nodes;
+
+        if (bist == 0) {
+                bsp_apicid = init_cpus(cpu_init_detectedx);
+        }
+
+//	post_code(0x32);
+	
+ 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+//	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        setup_khepri_resource_map();
+#if 0
+        dump_pci_device(PCI_DEV(0, 0x18, 0));
+	dump_pci_device(PCI_DEV(0, 0x19, 0));
+#endif
+
+	needs_reset = setup_coherent_ht_domain();
+
+        wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        start_other_cores();
+        wait_all_other_cores_started(bsp_apicid);
+#endif
+
+        needs_reset |= ht_setup_chains_x();
+
+       	if (needs_reset) {
+               	print_info("ht reset -\r\n");
+               	soft_reset();
+       	}
+
+
+        allow_all_aps_stop(bsp_apicid);
+
+        nodes = get_nodes();
+        //It's the time to set ctrl now;
+        fill_mem_ctrl(nodes, ctrl, spd_addr);
+
+        enable_smbus();
+
+        memreset_setup();
+        sdram_initialize(nodes, ctrl);
+
+#if 0
+	dump_pci_devices();
+#endif
+
+	post_cache_as_ram();
+
+}




From svn at openbios.org  Fri Nov  2 11:36:15 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 11:36:15 +0100
Subject: [LinuxBIOS] r2927 - trunk/LinuxBIOSv2/targets/iei/juki-511p
Message-ID: <mailman.821.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 11:36:15 +0100 (Fri, 02 Nov 2007)
New Revision: 2927

Added:
   trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb
Log:
fix juki 511p abuild by adding a Config-abuild.lb. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Added: trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb	2007-11-02 10:36:15 UTC (rev 2927)
@@ -0,0 +1,29 @@
+# abuild config file for JUKI-511P 
+
+target iei_juki-511p
+mainboard iei/juki-511p
+
+__COMPRESSION__
+
+option ROM_SIZE=256*1024
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+option FALLBACK_SIZE=128*1024
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE=0
+	option ROM_IMAGE_SIZE=64*1024
+	option LINUXBIOS_EXTRA_VERSION=".0-Normal"
+	payload __PAYLOAD__
+end
+
+romimage "fallback" 
+	option USE_FALLBACK_IMAGE=1
+	option ROM_IMAGE_SIZE=64*1024
+	option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
+	payload __PAYLOAD__
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"




From info at coresystems.de  Fri Nov  2 11:42:20 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 02 Nov 2007 11:42:20 +0100
Subject: [LinuxBIOS] r2926 build service
Message-ID: <E1Intym-0003hQ-N8@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2926 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
This patch fixes the superio of the khepri 2100e as detected:
> superiotool r2922
> Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e

Don't use the non-working trident driver for the blade3d (onboard vga
in the rom emulator has not been tested either)

It also adds some preliminary CAR support to the board, so it has a chance to
build again.

This board was broken since a couple of months, and the changes are minimal, so
I consider this a trivial change -- It doesn't change anything that was used,
obviously

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=e326&vendor=ibm
Compilation of iei:juki-511p is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=juki-511p&vendor=iei
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=dk8x&vendor=iwill
Compilation of newisys:khepri has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Fri Nov  2 12:06:40 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 12:06:40 +0100
Subject: [LinuxBIOS] r2928 - trunk/LinuxBIOSv2/src/mainboard/arima/hdama
Message-ID: <mailman.822.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 12:06:40 +0100 (Fri, 02 Nov 2007)
New Revision: 2928

Added:
   trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c
Modified:
   trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c
Log:
get arima hdama building again.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb	2007-11-02 10:36:15 UTC (rev 2927)
+++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb	2007-11-02 11:06:40 UTC (rev 2928)
@@ -46,6 +46,26 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
 ##
 ## Romcc output
 ##
@@ -68,14 +88,28 @@
 	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
 
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
@@ -87,8 +121,11 @@
 	ldscript /cpu/x86/32bit/reset32.lds
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -96,15 +133,26 @@
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
 end
+end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -113,17 +161,30 @@
 ##
 ## Setup RAM
 ##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
+##
+## Setup RAM
+##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 mainboardinit cpu/x86/mmx/enable_mmx.inc
 mainboardinit cpu/x86/sse/enable_sse.inc
 mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
 
 ##
 ## Include the secondary Configuration files 
 ##
-dir /pc80
 config chip.h
 
 # config for arima/hdama

Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb	2007-11-02 10:36:15 UTC (rev 2927)
+++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb	2007-11-02 11:06:40 UTC (rev 2928)
@@ -51,7 +51,9 @@
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_LOGICAL_CPUS
-
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
 ###
@@ -120,6 +122,14 @@
 ##
 default CONFIG_IOAPIC=1
 
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=0
+ 
 #VGA
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1

Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c	2007-11-02 10:36:15 UTC (rev 2927)
+++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c	2007-11-02 11:06:40 UTC (rev 2928)
@@ -83,50 +83,6 @@
 	}
 }
 
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
-	/* Routing Table Node i 
-	 *
-	 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-	 *  i:    0,    1,    2,    3,    4,    5,    6,    7
-	 *
-	 * [ 0: 3] Request Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [11: 8] Response Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [19:16] Broadcast route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 */
-
-	uint32_t ret = 0x00010101; /* default row entry */
-
-	/* CPU0 LDT1 <-> LDT1 CPU1 */
-	static const unsigned int rows_2p[2][2] = {
-		{ 0x00050101, 0x00010404 },
-		{ 0x00010404, 0x00050101 }
-	};
-
-	if (maxnodes > 2) {
-		print_spew("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes = 2;
-	}
-
-	if (!(node >= maxnodes || row >= maxnodes)) {
-		ret = rows_2p[node][row];
-	}
-
-	return ret;
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */

Added: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c	2007-11-02 11:06:40 UTC (rev 2928)
@@ -0,0 +1,222 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/nsc/pc87360/pc87360_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
+static void memreset_setup(void)
+{
+	if (is_cpu_pre_c0()) {
+		/* Set the memreset low */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		/* Ensure the BIOS has control of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
+	else {
+		/* Ensure the CPU has controll of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		/* Set memreset_high */
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		udelay(90);
+	}
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#define QRANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define FIRST_CPU  1
+#define SECOND_CPU 1
+#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        amd8111_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const struct mem_controller cpu[] = {
+		{
+			.node_id = 0,
+			.f0 = PCI_DEV(0, 0x18, 0),
+			.f1 = PCI_DEV(0, 0x18, 1),
+			.f2 = PCI_DEV(0, 0x18, 2),
+			.f3 = PCI_DEV(0, 0x18, 3),
+			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
+			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+		},
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+		{
+			.node_id = 1,
+			.f0 = PCI_DEV(0, 0x19, 0),
+			.f1 = PCI_DEV(0, 0x19, 1),
+			.f2 = PCI_DEV(0, 0x19, 2),
+			.f3 = PCI_DEV(0, 0x19, 3),
+			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+		},
+#endif
+	};
+
+        int needs_reset;
+
+        if (bist == 0) {
+		init_cpus(cpu_init_detectedx);
+        }
+
+	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        setup_default_resource_map();
+
+	needs_reset = setup_coherent_ht_domain();
+	
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        start_other_cores();
+#endif
+        // automatically set that for you, but you might meet tight space
+        needs_reset |= ht_setup_chains_x();
+
+       	if (needs_reset) {
+               	print_info("ht reset -\r\n");
+               	soft_reset();
+       	}
+
+	enable_smbus();
+
+	memreset_setup();
+	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+
+	post_cache_as_ram();
+
+}




From duwe at lst.de  Fri Nov  2 12:15:08 2007
From: duwe at lst.de (Torsten Duwe)
Date: Fri, 2 Nov 2007 12:15:08 +0100
Subject: [LinuxBIOS] M57SLI interrupt routing
Message-ID: <200711021215.09184.duwe@lst.de>

irqpoll rulez !-)

With this kernel option I get full performance from glxgears, but the 
interrupts show up under the driver for the only working PCI slot, not the 
primary PCIe! Looking at the board layout I see that this one is exactly 4 
slots further -- maybe Gigabyte did the classic INT rotation over all slots?

I cannot pursue this further right now, this is just a quick note, in case 
someone has a naked board and a multimeter handy :)

	Torsten



From info at coresystems.de  Fri Nov  2 12:39:46 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 02 Nov 2007 12:39:46 +0100
Subject: [LinuxBIOS] r2927 build service
Message-ID: <E1InusM-0002hD-01@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2927 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
fix juki 511p abuild by adding a Config-abuild.lb. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of arima:hdama is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=hdama&vendor=arima
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=e326&vendor=ibm
Compilation of iei:juki-511p has been fixed
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Fri Nov  2 13:35:30 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 13:35:30 +0100
Subject: [LinuxBIOS] r2929 - in trunk/LinuxBIOSv2: src/mainboard/ibm/e325
	src/mainboard/ibm/e326 targets/ibm/e326
Message-ID: <mailman.823.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 13:35:30 +0100 (Fri, 02 Nov 2007)
New Revision: 2929

Added:
   trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb
Modified:
   trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c
   trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c
Log:
fix up IBM servers.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb	2007-11-02 11:06:40 UTC (rev 2928)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb	2007-11-02 12:35:30 UTC (rev 2929)
@@ -47,6 +47,26 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
 ##
 ## Romcc output
 ##
@@ -69,14 +89,28 @@
 	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
 
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
@@ -88,8 +122,11 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -97,15 +134,26 @@
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
 end
+end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -114,17 +162,30 @@
 ##
 ## Setup RAM
 ##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
+##
+## Setup RAM
+##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 mainboardinit cpu/x86/mmx/enable_mmx.inc
 mainboardinit cpu/x86/sse/enable_sse.inc
 mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
 
 ##
 ## Include the secondary Configuration files 
 ##
-dir /pc80
 config chip.h
 
 

Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb	2007-11-02 11:06:40 UTC (rev 2928)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb	2007-11-02 12:35:30 UTC (rev 2929)
@@ -44,7 +44,9 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
 
@@ -110,6 +112,14 @@
 default CONFIG_IOAPIC=1
 
 ##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=0
+ 
+##
 ## Clean up the motherboard id strings
 ##
 default MAINBOARD_PART_NUMBER="E325"

Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c	2007-11-02 11:06:40 UTC (rev 2928)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c	2007-11-02 12:35:30 UTC (rev 2929)
@@ -66,50 +66,6 @@
 	}
 }
 
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
-	/* Routing Table Node i 
-	 *
-	 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-	 *  i:    0,    1,    2,    3,    4,    5,    6,    7
-	 *
-	 * [ 0: 3] Request Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [11: 8] Response Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [19:16] Broadcast route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 */
-
-	uint32_t ret = 0x00010101; /* default row entry */
-
-	static const unsigned int rows_2p[2][2] = {
-		{ 0x00090101, 0x00010808 },
-		{ 0x00010808, 0x00090101 }
-	};
-
-	if (maxnodes > 2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes = 2;
-	}
-
-
-	if (!(node >= maxnodes || row >= maxnodes)) {
-		ret = rows_2p[node][row];
-	}
-
-	return ret;
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */

Added: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c	2007-11-02 12:35:30 UTC (rev 2929)
@@ -0,0 +1,218 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/nsc/pc87366/pc87366_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+	if (is_cpu_pre_c0()) {
+		/* Set the memreset low */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		/* Ensure the BIOS has control of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+	} else {
+		/* Ensure the CPU has controll of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+	}
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		/* Set memreset_high */
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		udelay(90);
+	}
+}
+
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#define QRANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "resourcemap.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define FIRST_CPU  1
+#define SECOND_CPU 1
+#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        amd8111_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const struct mem_controller cpu[] = {
+		{
+			.node_id = 0,
+			.f0 = PCI_DEV(0, 0x18, 0),
+			.f1 = PCI_DEV(0, 0x18, 1),
+			.f2 = PCI_DEV(0, 0x18, 2),
+			.f3 = PCI_DEV(0, 0x18, 3),
+			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
+			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+		},
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+		{
+			.node_id = 1,
+			.f0 = PCI_DEV(0, 0x19, 0),
+			.f1 = PCI_DEV(0, 0x19, 1),
+			.f2 = PCI_DEV(0, 0x19, 2),
+			.f3 = PCI_DEV(0, 0x19, 3),
+			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+		},
+#endif
+	};
+
+        int needs_reset;
+
+        if (bist == 0) {
+		init_cpus(cpu_init_detectedx);
+        }
+
+	pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        setup_ibm_e325_resource_map();
+
+	needs_reset = setup_coherent_ht_domain();
+	
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        start_other_cores();
+#endif
+        // automatically set that for you, but you might meet tight space
+        needs_reset |= ht_setup_chains_x();
+
+       	if (needs_reset) {
+               	print_info("ht reset -\r\n");
+               	soft_reset();
+       	}
+
+	enable_smbus();
+
+	memreset_setup();
+	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+
+	post_cache_as_ram();
+
+}

Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb	2007-11-02 11:06:40 UTC (rev 2928)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb	2007-11-02 12:35:30 UTC (rev 2929)
@@ -47,6 +47,26 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
 ##
 ## Romcc output
 ##
@@ -69,14 +89,28 @@
 	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
 
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
@@ -88,8 +122,11 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -97,15 +134,26 @@
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
 end
+end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -114,17 +162,30 @@
 ##
 ## Setup RAM
 ##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
+##
+## Setup RAM
+##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 mainboardinit cpu/x86/mmx/enable_mmx.inc
 mainboardinit cpu/x86/sse/enable_sse.inc
 mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
 
 ##
 ## Include the secondary Configuration files 
 ##
-dir /pc80
 config chip.h
 
 

Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb	2007-11-02 11:06:40 UTC (rev 2928)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb	2007-11-02 12:35:30 UTC (rev 2929)
@@ -46,7 +46,9 @@
 uses OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
 
@@ -116,6 +118,14 @@
 default CONFIG_PCI_ROM_RUN=1
 
 ##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=0
+ 
+##
 ## Clean up the motherboard id strings
 ##
 default MAINBOARD_PART_NUMBER="E326"

Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c	2007-11-02 11:06:40 UTC (rev 2928)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c	2007-11-02 12:35:30 UTC (rev 2929)
@@ -66,50 +66,6 @@
 	}
 }
 
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
-	/* Routing Table Node i 
-	 *
-	 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-	 *  i:    0,    1,    2,    3,    4,    5,    6,    7
-	 *
-	 * [ 0: 3] Request Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [11: 8] Response Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [19:16] Broadcast route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 */
-
-	uint32_t ret = 0x00010101; /* default row entry */
-
-	/* CPU0 LDT2 <-> LDT2 CPU1 */
-	static const unsigned int rows_2p[2][2] = {
-		{ 0x00090101, 0x00010808 },
-		{ 0x00010808, 0x00090101 }
-	};
-
-	if (maxnodes > 2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes = 2;
-	}
-
-	if (!(node >= maxnodes || row >= maxnodes)) {
-		ret = rows_2p[node][row];
-	}
-
-	return ret;
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */

Added: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c	2007-11-02 12:35:30 UTC (rev 2929)
@@ -0,0 +1,218 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/nsc/pc87366/pc87366_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+	if (is_cpu_pre_c0()) {
+		/* Set the memreset low */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		/* Ensure the BIOS has control of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+	} else {
+		/* Ensure the CPU has controll of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+	}
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		/* Set memreset_high */
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		udelay(90);
+	}
+}
+
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#define QRANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "resourcemap.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define FIRST_CPU  1
+#define SECOND_CPU 1
+#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+        unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        amd8111_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+        failover_process(bist, cpu_init_detectedx);
+#endif
+        real_main(bist, cpu_init_detectedx);
+
+}
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const struct mem_controller cpu[] = {
+		{
+			.node_id = 0,
+			.f0 = PCI_DEV(0, 0x18, 0),
+			.f1 = PCI_DEV(0, 0x18, 1),
+			.f2 = PCI_DEV(0, 0x18, 2),
+			.f3 = PCI_DEV(0, 0x18, 3),
+			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
+			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+		},
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+		{
+			.node_id = 1,
+			.f0 = PCI_DEV(0, 0x19, 0),
+			.f1 = PCI_DEV(0, 0x19, 1),
+			.f2 = PCI_DEV(0, 0x19, 2),
+			.f3 = PCI_DEV(0, 0x19, 3),
+			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+		},
+#endif
+	};
+
+        int needs_reset;
+
+        if (bist == 0) {
+		init_cpus(cpu_init_detectedx);
+        }
+
+	pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        setup_ibm_e326_resource_map();
+
+	needs_reset = setup_coherent_ht_domain();
+	
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        start_other_cores();
+#endif
+        // automatically set that for you, but you might meet tight space
+        needs_reset |= ht_setup_chains_x();
+
+       	if (needs_reset) {
+               	print_info("ht reset -\r\n");
+               	soft_reset();
+       	}
+
+	enable_smbus();
+
+	memreset_setup();
+	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+
+	post_cache_as_ram();
+
+}

Added: trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb	2007-11-02 12:35:30 UTC (rev 2929)
@@ -0,0 +1,30 @@
+# the IBM E326
+# This will make a target directory of ./e326
+
+target e326
+mainboard ibm/e326
+
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE=0
+	option ROM_IMAGE_SIZE=0x20000
+	option LINUXBIOS_EXTRA_VERSION=".0Normal"
+#	payload ../../filo.elf
+	payload ../../../payloads/filo.elf
+end
+
+romimage "fallback" 
+	option USE_FALLBACK_IMAGE=1
+	option ROM_IMAGE_SIZE=0x20000
+	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+#	payload ../../filo.elf
+	payload ../../../payloads/filo.elf
+# use this to test a build if you don't have the etherboot
+#	payload /etc/hosts
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"




From info at coresystems.de  Fri Nov  2 13:38:21 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 02 Nov 2007 13:38:21 +0100
Subject: [LinuxBIOS] r2928 build service
Message-ID: <E1Invn3-00022U-SS@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2928 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
get arima hdama building again.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of arima:hdama has been fixed
Compilation of ibm:e325 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2928&device=e325&vendor=ibm
Compilation of ibm:e326 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2928&device=e326&vendor=ibm
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2928&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2928&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Fri Nov  2 13:54:49 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 13:54:49 +0100
Subject: [LinuxBIOS] r2930 - in trunk/LinuxBIOSv2: src/mainboard/iwill/dk8s2
	src/mainboard/iwill/dk8x targets/iwill targets/iwill/dk8x
Message-ID: <mailman.824.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 13:54:49 +0100 (Fri, 02 Nov 2007)
New Revision: 2930

Added:
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/targets/iwill/dk8x/
   trunk/LinuxBIOSv2/targets/iwill/dk8x/Config.lb
Modified:
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/auto.c
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/auto.c
Log:
fix up iwill board compilation. Untested, trivial

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Config.lb	2007-11-02 12:35:30 UTC (rev 2929)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Config.lb	2007-11-02 12:54:49 UTC (rev 2930)
@@ -50,6 +50,26 @@
 ## ATI Rage XL framebuffering graphics driver
 dir /drivers/ati/ragexl
 
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
 ##
 ## Romcc output
 ##
@@ -72,14 +92,28 @@
 	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
 
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
@@ -91,8 +125,11 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -100,15 +137,26 @@
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
 end
+end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -117,17 +165,30 @@
 ##
 ## Setup RAM
 ##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
+##
+## Setup RAM
+##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 mainboardinit cpu/x86/mmx/enable_mmx.inc
 mainboardinit cpu/x86/sse/enable_sse.inc
 mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
 
 ##
 ## Include the secondary Configuration files 
 ##
-dir /pc80
 config chip.h
 
 # config for iwill/dk8s2

Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Options.lb	2007-11-02 12:35:30 UTC (rev 2929)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/Options.lb	2007-11-02 12:54:49 UTC (rev 2930)
@@ -48,7 +48,9 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
@@ -111,6 +113,14 @@
 default CONFIG_IOAPIC=1
 
 ##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=0
+ 
+##
 ## Clean up the motherboard id strings
 ##
 default MAINBOARD_PART_NUMBER="HDAMA"

Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/auto.c	2007-11-02 12:35:30 UTC (rev 2929)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/auto.c	2007-11-02 12:54:49 UTC (rev 2930)
@@ -69,49 +69,6 @@
 	}
 }
 
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
-	/* Routing Table Node i 
-	 *
-	 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-	 *  i:	  0,	1,    2,    3,	  4,	5,    6,    7
-	 *
-	 * [ 0: 3] Request Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [11: 8] Response Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [19:16] Broadcast route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 */
-
-	uint32_t ret=0x00010101; /* default row entry */
-
-	static const unsigned int rows_2p[2][2] = {
-		{ 0x00050101, 0x00010404 },
-		{ 0x00010404, 0x00050101 }
-	};
-
-	if(maxnodes>2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes=2;
-	}
-
-	if (!(node>=maxnodes || row>=maxnodes)) {
-		ret=rows_2p[node][row];
-	}
-
-	return ret;
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */

Added: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	2007-11-02 12:54:49 UTC (rev 2930)
@@ -0,0 +1,333 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+//used by incoherent_ht
+//#define K8_SCAN_PCI_BUS 1
+//#define K8_ALLOCATE_IO_RANGE 1
+
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 0
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include <cpu/amd/model_fxx_rev.h>
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#endif
+
+
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "cpu/x86/bist.h"
+
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+	#include "lib/memcpy.c"
+ // TODO: This doesn't compile at the moment. Fix later.
+ // #if CONFIG_USE_PRINTK_IN_CAR == 1
+ //        #include "lib/uart8250.c"
+ //        #include "console/vtxprintf.c"
+ //        #include "arch/i386/lib/printk_init.c"
+ // #endif
+#endif
+#include "northbridge/amd/amdk8/debug.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
+static void memreset_setup(void)
+{
+	if (is_cpu_pre_c0()) {
+		/* Set the memreset low */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		/* Ensure the BIOS has control of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	} else {
+		/* Ensure the CPU has controll of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		/* Set memreset_high */
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		udelay(90);
+	}
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+        return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/coherent_ht_car.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit.c"
+
+#include "sdram/generic_sdram.c"
+#include "ram/ramtest.c"
+
+ /* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+#define DIMM4 0x54
+#define DIMM5 0x55
+#define DIMM6 0x56
+#define DIMM7 0x57
+
+
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+	unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        /* Setup the rom access for 4M */
+        amd8111_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr[] = {
+			//first node
+                        DIMM0, DIMM2, 0, 0,
+                        DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			//second node
+                        DIMM4, DIMM6, 0, 0,
+                        DIMM5, DIMM7, 0, 0,
+#endif
+
+	};
+
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset; int i;
+        unsigned bsp_apicid = 0;
+
+        if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+ 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+        setup_default_resource_map();
+
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
+#endif
+	setup_coherent_ht_domain(); // routing table and start other core0
+
+	wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, 
+	 * So here need to make sure last core0 is started, esp for two way system,
+	 * (there may be apic id conflicts in that case) 
+	 */
+        start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+	
+	/* it will set up chains and store link pair for optimization later */
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+
+#if K8_SET_FIDVID == 1
+
+        {
+                msr_t msr;
+	        msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+
+	enable_fid_change();
+
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+               	msr=rdmsr(0xc0010042);
+               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); 
+
+        }
+#endif
+
+	needs_reset = optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+                soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
+        }
+
+	allow_all_aps_stop(bsp_apicid);
+
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	enable_smbus();
+
+#if 0
+	dump_smbus_registers();
+#endif
+
+	memreset_setup();
+
+	//do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+        init_timer(); // Need to use TMICT to synconize FID/VID
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+
+#if 0
+        dump_pci_devices();
+#endif
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+
+}
+#endif

Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Config.lb	2007-11-02 12:35:30 UTC (rev 2929)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Config.lb	2007-11-02 12:54:49 UTC (rev 2930)
@@ -47,6 +47,26 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
 ##
 ## Romcc output
 ##
@@ -69,14 +89,28 @@
 	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
+
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
 
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
@@ -88,8 +122,11 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -97,15 +134,26 @@
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
 end
+end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -114,17 +162,30 @@
 ##
 ## Setup RAM
 ##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
+##
+## Setup RAM
+##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 mainboardinit cpu/x86/mmx/enable_mmx.inc
 mainboardinit cpu/x86/sse/enable_sse.inc
 mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
 
 ##
 ## Include the secondary Configuration files 
 ##
-dir /pc80
 config chip.h
 
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Options.lb	2007-11-02 12:35:30 UTC (rev 2929)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/Options.lb	2007-11-02 12:54:49 UTC (rev 2930)
@@ -48,7 +48,9 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
@@ -111,6 +113,14 @@
 default CONFIG_IOAPIC=1
 
 ##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=0
+ 
+##
 ## Clean up the motherboard id strings
 ##
 #default MAINBOARD_PART_NUMBER="HDAMA"

Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/auto.c	2007-11-02 12:35:30 UTC (rev 2929)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/auto.c	2007-11-02 12:54:49 UTC (rev 2930)
@@ -70,50 +70,6 @@
 	}
 }
 
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
-	/* Routing Table Node i 
-	 *
-	 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-	 *  i:    0,    1,    2,    3,    4,    5,    6,    7
-	 *
-	 * [ 0: 3] Request Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [11: 8] Response Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [19:16] Broadcast route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 */
-
-	uint32_t ret=0x00010101; /* default row entry */
-
-	static const unsigned int rows_2p[2][2] = {
-		{ 0x00050101, 0x00010404 },
-		{ 0x00010404, 0x00050101 }
-	};
-
-	if(maxnodes>2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes=2;
-	}
-
-
-	if (!(node>=maxnodes || row>=maxnodes)) {
-		ret=rows_2p[node][row];
-	}
-
-	return ret;
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */

Added: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c	2007-11-02 12:54:49 UTC (rev 2930)
@@ -0,0 +1,333 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+//used by incoherent_ht
+//#define K8_SCAN_PCI_BUS 1
+//#define K8_ALLOCATE_IO_RANGE 1
+
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 0
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include <cpu/amd/model_fxx_rev.h>
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#endif
+
+
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "cpu/x86/bist.h"
+
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+	#include "lib/memcpy.c"
+ // TODO: This doesn't compile at the moment. Fix later.
+ // #if CONFIG_USE_PRINTK_IN_CAR == 1
+ //        #include "lib/uart8250.c"
+ //        #include "console/vtxprintf.c"
+ //        #include "arch/i386/lib/printk_init.c"
+ // #endif
+#endif
+#include "northbridge/amd/amdk8/debug.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
+static void memreset_setup(void)
+{
+	if (is_cpu_pre_c0()) {
+		/* Set the memreset low */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		/* Ensure the BIOS has control of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	} else {
+		/* Ensure the CPU has controll of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		/* Set memreset_high */
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		udelay(90);
+	}
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+        return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/coherent_ht_car.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit.c"
+
+#include "sdram/generic_sdram.c"
+#include "ram/ramtest.c"
+
+ /* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+#define DIMM4 0x54
+#define DIMM5 0x55
+#define DIMM6 0x56
+#define DIMM7 0x57
+
+
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+	unsigned last_boot_normal_x = last_boot_normal();
+
+        /* Is this a cpu only reset? or Is this a secondary cpu? */
+        if ((cpu_init_detectedx) || (!boot_cpu())) {
+                if (last_boot_normal_x) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        /* Setup the rom access for 4M */
+        amd8111_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal_x) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr[] = {
+			//first node
+                        DIMM0, DIMM2, 0, 0,
+                        DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			//second node
+                        DIMM4, DIMM6, 0, 0,
+                        DIMM5, DIMM7, 0, 0,
+#endif
+
+	};
+
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset; int i;
+        unsigned bsp_apicid = 0;
+
+        if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+        }
+
+ 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+        setup_default_resource_map();
+
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
+#endif
+	setup_coherent_ht_domain(); // routing table and start other core0
+
+	wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, 
+	 * So here need to make sure last core0 is started, esp for two way system,
+	 * (there may be apic id conflicts in that case) 
+	 */
+        start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+	
+	/* it will set up chains and store link pair for optimization later */
+        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+
+#if K8_SET_FIDVID == 1
+
+        {
+                msr_t msr;
+	        msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+        }
+
+	enable_fid_change();
+
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+               	msr=rdmsr(0xc0010042);
+               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); 
+
+        }
+#endif
+
+	needs_reset = optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+                soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
+        }
+
+	allow_all_aps_stop(bsp_apicid);
+
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	enable_smbus();
+
+#if 0
+	dump_smbus_registers();
+#endif
+
+	memreset_setup();
+
+	//do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+        init_timer(); // Need to use TMICT to synconize FID/VID
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+
+#if 0
+        dump_pci_devices();
+#endif
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+
+}
+#endif

Added: trunk/LinuxBIOSv2/targets/iwill/dk8x/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/iwill/dk8x/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/iwill/dk8x/Config.lb	2007-11-02 12:54:49 UTC (rev 2930)
@@ -0,0 +1,167 @@
+# Sample config file for 
+# the Iwill DK8X
+# This will make a target directory of ./dk8x
+
+target dk8x
+
+mainboard iwill/dk8x
+
+option HAVE_HARD_RESET=1
+
+option HAVE_OPTION_TABLE=1
+option HAVE_MP_TABLE=1
+option ROM_SIZE=1024*1024
+
+option HAVE_FALLBACK_BOOT=1
+  
+#option CONFIG_LSI_SCSI_FW_FIXUP=1
+
+
+#
+###
+### Build code to export a programmable irq routing table
+###
+option HAVE_PIRQ_TABLE=1
+option IRQ_SLOT_COUNT=12
+#
+###
+### Build code for SMP support
+### Only worry about 2 micro processors
+###
+option CONFIG_SMP=1
+option CONFIG_MAX_CPUS=2
+#option CONFIG_LOGICAL_CPUS=2
+option CONFIG_MAX_PHYSICAL_CPUS=2
+#
+###
+### Build code to setup a generic IOAPIC
+###
+option CONFIG_IOAPIC=1
+#
+###
+### MEMORY_HOLE instructs earlymtrr.inc to
+### enable caching from 0-640KB and to disable 
+### caching from 640KB-1MB using fixed MTRRs 
+###
+### Enabling this option breaks SMP because secondary
+### CPU identification depends on only variable MTRRs
+### being enabled.
+###
+#option MEMORY_HOLE=0
+#
+###
+### Clean up the motherboard id strings
+###
+option MAINBOARD_PART_NUMBER="DK8X"
+option MAINBOARD_VENDOR="IWILL"
+#
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+#option FALLBACK_SIZE=524288
+#option FALLBACK_SIZE=98304
+option FALLBACK_SIZE=131072
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+option ROM_IMAGE_SIZE=65536
+ 
+
+###
+### Compute where this copy of linuxBIOS will start in the boot rom
+###
+#
+###
+
+## We do use compressed image
+#option CONFIG_COMPRESS=1
+
+option CONFIG_CONSOLE_SERIAL8250=1
+option TTYS0_BAUD=115200
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+option DEFAULT_CONSOLE_LOGLEVEL=7
+## At a maximum only compile in this level of debugging
+option MAXIMUM_CONSOLE_LOGLEVEL=7
+
+#option DEBUG=1
+
+#
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x004000
+
+##
+## Use a 32K stack
+##
+option STACK_SIZE=0x8000 
+
+##
+## Use a 56K heap
+##
+option HEAP_SIZE=0xe000
+
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+option CONFIG_ROM_PAYLOAD     = 1
+
+#
+# 
+romimage "normal"
+#	48K for SCSI FW
+#        option ROM_SIZE = 512*1024-48*1024
+#	48K for SCSI FW and 48K for ATI ROM
+#	option ROM_SIZE = 512*1024-48*1024-48*1024
+        option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+	option USE_FALLBACK_IMAGE=0
+	option ROM_SECTION_SIZE  = (ROM_SIZE - FALLBACK_SIZE)
+	option ROM_SECTION_OFFSET= 0
+
+	option PAYLOAD_SIZE            = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+	option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+	option _ROMBASE      = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+
+#	option XIP_ROM_SIZE = FALLBACK_SIZE
+        option XIP_ROM_SIZE = 65536
+
+	option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+
+	payload /usr/src/filo-0.4.1_btext/filo.elf
+#	payload /usr/src/filo-0.4.2/filo.elf
+end
+
+romimage "fallback" 
+	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+	option USE_FALLBACK_IMAGE=1
+	option ROM_SECTION_SIZE  = FALLBACK_SIZE
+	option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
+
+	option PAYLOAD_SIZE            = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+	option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+	option _ROMBASE      = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+
+#	option XIP_ROM_SIZE = FALLBACK_SIZE
+	option XIP_ROM_SIZE = 65536
+	option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+
+	payload ../../../payloads/filo.elf
+#	payload /usr/src/filo-0.4.2/filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"




From info at coresystems.de  Fri Nov  2 14:32:21 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 02 Nov 2007 14:32:21 +0100
Subject: [LinuxBIOS] r2929 build service
Message-ID: <E1InwdJ-0001Rb-Lt@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2929 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
fix up IBM servers.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of ibm:e325 has been fixed
Compilation of ibm:e326 has been fixed
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2929&device=dk8s2&vendor=iwill
Compilation of iwill:dk8x is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2929&device=dk8x&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From info at coresystems.de  Fri Nov  2 15:15:38 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Fri, 02 Nov 2007 15:15:38 +0100
Subject: [LinuxBIOS] r2930 build service
Message-ID: <E1InxJC-0000fY-SN@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2930 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
fix up iwill board compilation. Untested, trivial

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of iwill:dk8s2 has been fixed
Compilation of iwill:dk8x has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From uwe at hermann-uwe.de  Fri Nov  2 16:56:03 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Nov 2007 16:56:03 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472ABDA6.4000602@gmail.com>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
Message-ID: <20071102155603.GA25764@greenwood>

On Fri, Nov 02, 2007 at 02:03:18AM -0400, Corey Osgood wrote:
> @@ -79,11 +62,14 @@
>  
>  	loops = 0;
>  	/* Yes, this is a mess, but it's the easiest way to do it. */
> -	while ((inb(SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT)
> +	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)

Rationale? Does it make a big difference?


> -u8 smbus_read_byte(u32 dimm, u32 offset)
> +/**
> + * Read a byte from the smbus
> + *
> + * @param dimm The address location of the dimm on the smbus
> + * @param offset The offset the data is located at
> + */

> +u8 smbus_read_byte(u8 dimm, u8 offset)

I'm still not entirely sure they're always only 8 bit. Do you have a
pointer to a datasheet or spec or standard where it's explicitly
defined as 8 bit? Yes, it _is_ 8 bits in most cases, but can we be sure
that it'll be 8 bit in _all_ of them? On all chipsets and controllers?


> -	/* Can I just "return inb(SMBHSTDAT0)"? */
> +	/* We could probably return inb(SMBHSTDAT0), but we'd lose the ability
> +	 * to debug the transaction */

OK, if that's the only issue, just drop the comment.


> +/**
> + * This is provided for compatibility, should it be needed
> + */
> +inline u8 spd_read_byte(u32 address, u8 offset)
> +{
> +	return smbus_read_byte(address, offset);
> +}

Hm, this is usually done in auto.c per-mainboard, I think. Either
you make spd_read_byte() a wrapper for smbus_read_byte(), or you
use the "fake spd" method to return hard-coded settings if there's
no real SPD data to be read.

Not sure this function makes sense in vt8237r_early_smbus.c, because of
the above and also because it's not SMBus-related per se. I'd say drop it.

Also, address is 32bit here but 8bit in smbus_read_byte()?


> +/**
> + * A fixup for some systems that need time for the smbus to "warm up"
> + * It reads the ID byte from SMBus, looking for good data from a slot/address
> + * Exits on either good data or a timeout

Yep, but please extend the comment a bit to contain more information,
rationale, example use case where this issue came up, how the problem
shows, how it's fixed etc. The comment is good, but a bit too short
for describing this non-trivial issue at hand.


> + *
> + * @param mem_controller The memory controller and smbus addresses
> + */
> +void smbus_fixup(const struct mem_controller *ctrl)
> +{
> +	int i, ram_slots, current_slot = 0;
> +	u8 result = 0;
> +
> +#ifdef DIMM_SOCKETS
> +	ram_slots = DIMM_SOCKETS;
> +#else
> +	ram_slots = sizeof(ctrl->channel0)/sizeof(ctrl->channel0[0]);
> +#endif

Can you explain? Shouldn't DIMM_SOCKETS always match
sizeof(ctrl->channel0)/sizeof(ctrl->channel0[0])? When does it happen
that they do not match (and why?).

Also, we now have ARRAY_SIZE(), please use it here.


> +	if (!ram_slots) {
> +		print_err("smbus_fixup thinks there are no ram slots!\r\n");
> +		return;
> +	}
> +	
> +	PRINT_DEBUG("Waiting for smbus to warm up");
> +		
> +	/* Bad SPD data should be either 0 or 0xff, so really the values we look
> +	 * for are arbitrary, as long as they're between 1 and 0xfe */
> +	for(i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || 
> +			(result > SPD_MEMORY_TYPE_SDRAM_DDR2))); i++)

Please explain the SPD_MEMORY_TYPE_SDRAM/SPD_MEMORY_TYPE_SDRAM_DDR2
check in the comment here.

If all you want is to know whether some sensible RAM type is
returned wouldn't "> 0" and "< 0xff" be enough (as per your comment)?
You don't really care about the exact type, you only want to know _if_ there's
a DIMM here, correct?

If I read this correctly you're checking whether you get one of these?

#define SPD_MEMORY_TYPE_SDRAM            4
#define SPD_MEMORY_TYPE_MULTIPLEXED_ROM  5
#define SPD_MEMORY_TYPE_SGRAM_DDR        6
#define SPD_MEMORY_TYPE_SDRAM_DDR        7
#define SPD_MEMORY_TYPE_SDRAM_DDR2       8

If we make this "> 0" and "< 0xff" ("< 10" or so should be enough, too)
then this function might be usable on non-vt8237r chipsets and can go
in some global SMBus file to be used by others?


> +	{
> +		if (current_slot > ram_slots) j = 0;
> +		result = spd_read_byte(ctrl->channel0[current_slot], 
> +							SPD_MEMORY_TYPE);
> +		current_slot++;
> +		PRINT_DEBUG(".");
> +	}
> +	if (i >= SMBUS_TIMEOUT)	print_err("SMBus timed out while warming up\r\n");
> +	else PRINT_DEBUG("Done\r\n");	
> +}


Looks good otherwise. Does this contain all of the changes required to
make it work on your board _and_ Rudolf's board?


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Fri Nov  2 17:09:58 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 17:09:58 +0100
Subject: [LinuxBIOS] r2931 - in trunk/LinuxBIOSv2: src/include/device
	src/mainboard/gigabyte/ga_2761gxdk src/southbridge/sis/sis966
	targets/gigabyte/ga_2761gxdk
Message-ID: <mailman.825.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 17:09:58 +0100 (Fri, 02 Nov 2007)
New Revision: 2931

Added:
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
Modified:
   trunk/LinuxBIOSv2/src/include/device/pci_ids.h
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/chip.h
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/Config.lb
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/chip.h
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/romstrap.inc
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.h
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_setup_car.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_enable_rom.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.h
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c
   trunk/LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/Config.lb
Log:
1. vgabios removed, will go to extra repository

2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in
   src/include/device/pci_ids.h
4. Trim trailing spaces for all files

Signed-off-by: Morgan Tsai <my_tsai at sis.com>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>                                                                                   
Acked-by: Stefan Reinauer <stepan at coresystems.de>




Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-11-02 16:09:58 UTC (rev 2931)
@@ -312,11 +312,11 @@
 #define PCI_DEVICE_ID_NS_CS5535_AUDIO	0x002e
 #define PCI_DEVICE_ID_NS_CS5535_USB	0x002f
 #define PCI_DEVICE_ID_NS_CS5535_GX2VGA	0x0030
-#define PCI_DEVICE_ID_NS_SCx200_BRIDGE  0x0500 
-#define PCI_DEVICE_ID_NS_SCx200_SMI     0x0501 
+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE  0x0500
+#define PCI_DEVICE_ID_NS_SCx200_SMI     0x0501
 #define PCI_DEVICE_ID_NS_SCx200_IDE     0x0502
-#define PCI_DEVICE_ID_NS_SCx200_AUDIO   0x0503   
-#define PCI_DEVICE_ID_NS_SCx200_VIDEO   0x0504   
+#define PCI_DEVICE_ID_NS_SCx200_AUDIO   0x0503
+#define PCI_DEVICE_ID_NS_SCx200_VIDEO   0x0504
 #define PCI_DEVICE_ID_NS_SCx200_XBUS    0x0505
 #define PCI_DEVICE_ID_NS_87410		0xd001
 
@@ -652,7 +652,7 @@
 
 #define PCI_VENDOR_ID_ANIGMA		0x1051
 #define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
-  
+
 #define PCI_VENDOR_ID_EFAR		0x1055
 #define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
 #define PCI_DEVICE_ID_EFAR_SLC90E66_0	0x9460
@@ -1223,7 +1223,7 @@
 #define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
 #define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
 #define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
- 
+
 #define PCI_VENDOR_ID_CYCLONE		0x113c
 #define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
 
@@ -1726,7 +1726,7 @@
 #define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
 
 #define PCI_VENDOR_ID_ZOLTRIX		0x15b0
-#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0 
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0
 
 #define PCI_VENDOR_ID_PDC		0x15e9
 #define PCI_DEVICE_ID_PDC_1841		0x1841
@@ -1967,26 +1967,26 @@
 #define PCI_DEVICE_ID_INTEL_PCIE_PC	0x3599
 
 #define PCI_DEVICE_ID_INTEL_82801DBM_1E0 0x2448
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F0 0x24cc 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F1 0x24ca 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F3 0x24c3 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F5 0x24c5 
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F0 0x24cc
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F1 0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F3 0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DBM_1F5 0x24c5
 #define PCI_DEVICE_ID_INTEL_82801DBM_1F6 0x24c6
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D0 0x24c2 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D1 0x24c4 
+#define PCI_DEVICE_ID_INTEL_82801DBM_1D0 0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DBM_1D1 0x24c4
 #define PCI_DEVICE_ID_INTEL_82801DBM_1D2 0x24c7
 #define PCI_DEVICE_ID_INTEL_82801DBM_1D7 0x24cd
 
-#define PCI_DEVICE_ID_INTEL_82801ER_1E0 0x244e 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F0 0x24d0 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F1 0x24db 
+#define PCI_DEVICE_ID_INTEL_82801ER_1E0 0x244e
+#define PCI_DEVICE_ID_INTEL_82801ER_1F0 0x24d0
+#define PCI_DEVICE_ID_INTEL_82801ER_1F1 0x24db
 #define PCI_DEVICE_ID_INTEL_82801ER_1F2 0x24d1
-#define PCI_DEVICE_ID_INTEL_82801ER_1F2_R 0x24df 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F3 0x24d3 
-#define PCI_DEVICE_ID_INTEL_82801ER_1F5 0x24d5 
+#define PCI_DEVICE_ID_INTEL_82801ER_1F2_R 0x24df
+#define PCI_DEVICE_ID_INTEL_82801ER_1F3 0x24d3
+#define PCI_DEVICE_ID_INTEL_82801ER_1F5 0x24d5
 #define PCI_DEVICE_ID_INTEL_82801ER_1F6 0x24d6
-#define PCI_DEVICE_ID_INTEL_82801ER_1D0 0x24d2 
-#define PCI_DEVICE_ID_INTEL_82801ER_1D1 0x24d4 
+#define PCI_DEVICE_ID_INTEL_82801ER_1D0 0x24d2
+#define PCI_DEVICE_ID_INTEL_82801ER_1D1 0x24d4
 #define PCI_DEVICE_ID_INTEL_82801ER_1D2 0x24d7
 #define PCI_DEVICE_ID_INTEL_82801ER_1D3 0x24de
 #define PCI_DEVICE_ID_INTEL_82801ER_1D7 0x24dd
@@ -2076,55 +2076,33 @@
 #define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
 
 #define PCI_VENDOR_ID_SIS		0x1039
+#define PCI_DEVICE_ID_SIS_AGP 		0x0002
+#define PCI_DEVICE_ID_SIS_SIS761	0x0761
 #define PCI_DEVICE_ID_SIS_SIS966_SB	0x0966
+#define PCI_DEVICE_ID_SIS_SIS966_ISA	0x0966
 #define PCI_DEVICE_ID_SIS_SIS966_LPC	0x0966
-#define PCI_DEVICE_ID_SIS_SIS966_SLAVE	0x0361
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_2	0x0362
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_3	0x0363
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_4	0x0364
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_5	0x0365
-#define PCI_DEVICE_ID_SIS_SIS966_LPC_6	0x0366
-#define PCI_DEVICE_ID_SIS_SIS966_PRO	0x0367
 #define PCI_DEVICE_ID_SIS_SIS966_SM2	0x0368
-#define PCI_DEVICE_ID_SIS_SIS966_IDE	0x5513
-#define PCI_DEVICE_ID_SIS_SIS966_SATA0	0x1183
-#define PCI_DEVICE_ID_SIS_SIS966_SATA1	0x037F
-#define PCI_DEVICE_ID_SIS_SIS966_NIC0	0x190
-#define PCI_DEVICE_ID_SIS_SIS966_NIC1	0x191
-#define PCI_DEVICE_ID_SIS_SIS966_NIC2	0x192
-#define PCI_DEVICE_ID_SIS_SIS966_NIC3	0x193
-#define PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE 0x0373
-#define PCI_DEVICE_ID_SIS_SIS966_AZA	0x7502
+#define PCI_DEVICE_ID_SIS_SIS966_HT	0x0369
 #define PCI_DEVICE_ID_SIS_SIS966_PCI	0x0370
+#define PCI_DEVICE_ID_SIS_SIS966_SMB	0x25a4
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_A_B 0x000A
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C 0x1002
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_E	0x1003
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_A	0x1004
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_F	0x1005
 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_D	0x1006
-#define PCI_DEVICE_ID_SIS_SIS966_HT	0x0369
-#define PCI_DEVICE_ID_SIS_SIS966_TRIM	0x036A
-#define PCI_DEVICE_ID_SIS_SIS966_PMU	0x036B
-#define PCI_DEVICE_ID_SIS_SIS966_NORTHBRIDGE 0x0756
-#define PCI_DEVICE_ID_SIS_SIS966_ISA	0x0966
 #define PCI_DEVICE_ID_SIS_SIS966_AC97_AUDIO 0x7012
 #define PCI_DEVICE_ID_SIS_SIS966_AC97_MODEM 0x7013
-#define PCI_DEVICE_ID_SIS_SIS966_EHCI	0x7002
 #define PCI_DEVICE_ID_SIS_SIS966_IDE	0x5513
-#define PCI_DEVICE_ID_SIS_SIS966_SMB	0x25a4
+#define PCI_DEVICE_ID_SIS_SIS966_SATA0	0x1183
+#define PCI_DEVICE_ID_SIS_SIS966_NIC0	0x0190
+#define PCI_DEVICE_ID_SIS_SIS966_NIC1	0x0191
+#define PCI_DEVICE_ID_SIS_SIS966_AZA	0x7502
 #define PCI_DEVICE_ID_SIS_SIS966_USB	0x7001
-#define PCI_DEVICE_ID_SIS_SIS966_USB2	0x7001
-#define PCI_DEVICE_ID_SIS_SIS966_USB3	0x7001
-#define PCI_DEVICE_ID_SIS_SIS966_SATA	0x1183
-#define PCI_DEVICE_ID_SIS_SIS966_SATA_R	0x1183
-#define PCI_DEVICE_ID_SIS_SIS966_PIC1	0x25ac
-#define PCI_DEVICE_ID_SIS_SIS966_BRIDGE1C 0x0966
-#define PCI_DEVICE_ID_SIS_AGP 		0x0002
-#define PCI_DEVICE_ID_SIS_SIS761	0x0761
-#define PCI_DEVICE_ID_SIS_SIS756	0x0756
+#define PCI_DEVICE_ID_SIS_SIS966_USB2	0x7002
 
 /* OLD USAGE FOR LINUXBIOS */
-#define PCI_VENDOR_ID_ACER              0x10b9   
+#define PCI_VENDOR_ID_ACER              0x10b9
 #define PCI_DEVICE_ID_ACER_M1535D         0x1533
 
 #define PCI_DEVICE_ID_AMD_761_0         0x700E

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2007-11-02 16:09:58 UTC (rev 2931)
@@ -239,15 +239,12 @@
 				#  devices on link 0, link 0 == LDT 0
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   # Northbridge
-					#################################################
-					device pci 1.0 on 			# AGP bridge
+					device pci 1.0 on		# AGP bridge
 					  chip drivers/pci/onboard	# Integrated VGA
 						device pci 0.0 on end
 						register "rom_address" = "0xfff80000"
 					  end
 					end
-					#################################################
-					## device pci 1.0 on end   # PCIE
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f
 							device pnp 2e.0 off #  Floppy
@@ -272,12 +269,12 @@
                 	                 			io 0x62 = 0x230
                 	                			irq 0x70 = 9
 							end
-                	        			device pnp 2e.5 off #  Keyboard
+                	        			device pnp 2e.5 on #  Keyboard
                 	                 			io 0x60 = 0x60
                 	                 			io 0x62 = 0x64
                 	                			irq 0x70 = 1
 							end
-                	        			device pnp 2e.6 off #  Mouse
+                	        			device pnp 2e.6 on #  Mouse
                 	                			irq 0x70 = 12
 							end
                 	        			device pnp 2e.8 off #  MIDI
@@ -291,30 +288,27 @@
 						end
 					end
 
- 					device pci 2.5 on end # IDE (SiS5513)
- 					device pci 2.6 off end # Modem (SiS7013)
- 					device pci 2.7 off end # Audio (SiS7012)
-                			device pci 3.0 on end # USB (SiS7001,USB1.1)
-	                		device pci 3.1 on end # USB (SiS7001,USB1.1)
-	                		device pci 3.3 on end # USB (SiS7002,USB2.0)
-	                		device pci 4.0 on end # NIC (SiS191)
-                			device pci 5.0 on end # SATA (SiS1183)
-                			device pci 6.0 off end # SB PCIE1 (SiS000A)
-                			device pci 7.0 off end # SB PCIE2 (SiS000A)
-        	       			device pci 9.0 off end # PCI E 6
-        	       			device pci a.0 off end # PCI E 5
-        	       			device pci b.0 off end # PCI E 4
-                			device pci c.0 off end # PCI E 3
-                			device pci d.0 off end # PCI E 2
-                			device pci e.0 off end # PCI E 1
-        	       			device pci f.0 on end # Hda
+                                        device pci 2.5 off end # IDE (SiS5513)
+                                        device pci 2.6 off end # Modem (SiS7013)
+                                        device pci 2.7 off end # Audio (SiS7012)
+                                        device pci 3.0 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.1 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.3 on end # USB (SiS7002,USB2.0)
+                                        device pci 4.0 on end # NIC (SiS191)
+                                        device pci 5.0 on end # SATA (SiS1183,IDE Mode)
+                                        device pci 6.0 off end # PCI-E (SiS000A)
+                                        device pci 7.0 off end # PCI-E (SiS000A)
+                                        device pci a.0 off end
+                                        device pci b.0 off end
+                                        device pci c.0 off end
+                                        device pci d.0 off end
+                                        device pci e.0 off end
+                                        device pci f.0 off end # HD Audio (SiS7502)
 
-	                                register "ide0_enable" = "1"
-	                                register "ide1_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-				   	#register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-				   	#register "mac_eeprom_addr" = "0x51"
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+                                        register "sata0_enable" = "1"
+                                        register "sata1_enable" = "1"
 				end
 			end #  device pci 18.0
 			device pci 18.0 on end # Link 1
@@ -328,14 +322,14 @@
 
 #       chip drivers/generic/debug
 #               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 on end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
+#               device pnp 0.1 on end # pci_regs_all
+#               device pnp 0.2 on end # mem
+#               device pnp 0.3 off end # cpuid
+#               device pnp 0.4 on end # smbus_regs_all
+#               device pnp 0.5 off end # dual core msr
+#               device pnp 0.6 off end # cache size
 #               device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 off end # io
+#               device pnp 0.8 off  end # io
+#               device pnp 0.9 off end # io
 #       end
 end #root_complex

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2007-11-02 16:09:58 UTC (rev 2931)
@@ -1,25 +1,25 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
 ## Written by Morgan Tsai <my_tsai at sis.com> for SiS.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
@@ -197,7 +197,7 @@
 #CHIP_NAME ?
 default CONFIG_CHIP_NAME=1
 
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000
 #1G
@@ -253,8 +253,8 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="SiS"
-default MAINBOARD_VENDOR="SIS"
+default MAINBOARD_PART_NUMBER="ga_2761gxdk"
+default MAINBOARD_VENDOR="GIGABYTE"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
 
@@ -294,7 +294,7 @@
 
 ###
 ### Defaults of options that you may want to override in the target config file
-### 
+###
 
 ##
 ## The default compiler
@@ -304,7 +304,7 @@
 
 ##
 ## Disable the gdb stub by default
-## 
+##
 default CONFIG_GDB_STUB=0
 
 ##
@@ -335,15 +335,15 @@
 ##
 ### Select the linuxBIOS loglevel
 ##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
 
 ## Request this level of debugging output
 default  DEFAULT_CONSOLE_LOGLEVEL=8

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -27,7 +27,7 @@
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
-#define SET_NB_CFG_54 1 
+#define SET_NB_CFG_54 1
 
 //used by raminit
 #define QRANK_DIMM_SUPPORT 1

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -46,7 +46,7 @@
 #endif
 
 #define DBGP_DEFAULT 7
- 
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -95,7 +95,7 @@
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
 #include "southbridge/sis/sis966/sis966_early_ctrl.c"
 
@@ -126,7 +126,7 @@
 
 #include "sdram/generic_sdram.c"
 
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -171,13 +171,13 @@
         uint8_t byte;
 
         byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
-        
+
         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
@@ -237,15 +237,15 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
+#if HAVE_FAILOVER_BOOT==1
     #if USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
+	failover_process(bist, cpu_init_detectedx);
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
     #if USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
+	failover_process(bist, cpu_init_detectedx);
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
@@ -281,7 +281,7 @@
         setup_mb_resource_map();
 
         uart_init();
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -340,7 +340,6 @@
 
         needs_reset |= optimize_link_coherent_ht();
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
-        needs_reset |= sis966_early_setup_x();
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
@@ -353,8 +352,8 @@
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
         sis_init_stage1();
-        enable_smbus(); 
-       
+        enable_smbus();
+
         memreset_setup();
 
         //do we need apci timer, tsc...., only debug need it for better output

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/chip.h	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/chip.h	2007-11-02 16:09:58 UTC (rev 2931)
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout	2007-11-02 16:09:58 UTC (rev 2931)
@@ -1,23 +1,23 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 entries
 

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -40,7 +40,7 @@
         unsigned apicid_sis966;
 
 
-unsigned pci1234x[] = 
+unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -52,7 +52,7 @@
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] = 
+unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 //	0x20202020,
@@ -63,7 +63,7 @@
 //        0x20202020,
 //        0x20202020,
 };
-unsigned bus_type[256]; 
+unsigned bus_type[256];
 
 extern void get_sblk_pci1234(void);
 
@@ -96,13 +96,13 @@
 	for(i=0; i<8; i++) {
 		bus_sis966[i] = 0;
 	}
-	
+
 	for(i=0;i<256; i++) {
 		bus_type[i] = 0;
 	}
 
 	bus_type[0] = 1; //pci
-	
+
 	bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 
 	bus_type[bus_sis966[0]] = 1;
@@ -140,8 +140,8 @@
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
-#else 
-	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
 	apicid_sis966 = apicid_base+0;
 

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -32,7 +32,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <arch/pirq_routing.h>
-
+#include <device/pci_ids.h>
 #include <cpu/amd/amdk8_sysconf.h>
 
 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
@@ -75,7 +75,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk_info("Writing IRQ routing tables to 0x%x...\n", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -88,8 +88,8 @@
 
 	pirq->exclusive_irqs = 0;
 
-	pirq->rtr_vendor = 0x10de;
-	pirq->rtr_device = 0x0370;
+	pirq->rtr_vendor = PCI_VENDOR_ID_SIS;
+	pirq->rtr_device = PCI_DEVICE_ID_SIS_SIS966_PCI;
 
 	pirq->miniport_data = 0;
 
@@ -124,11 +124,17 @@
                 }
 
                 printk_debug("Setting Onboard SiS Southbridge\n");
-//                dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
-//                pci_write_config8(dev, 0x3C, 0x0A);
-                dev = dev_find_slot(0, PCI_DEVFN(3,0));   // USB 1.1 -1
+
+                /*
+                 * Non-layout for GA-2761GX
+                 *
+                dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
+                pci_write_config8(dev, 0x3C, 0x0A);
+                */
+
+                dev = dev_find_slot(0, PCI_DEVFN(3,0));   // USB 1.1
                 pci_write_config8(dev, 0x3C, 0x0B);
-                dev = dev_find_slot(0, PCI_DEVFN(3,1));   // USB 1.1 -2
+                dev = dev_find_slot(0, PCI_DEVFN(3,1));   // USB 1.1
                 pci_write_config8(dev, 0x3C, 0x05);
                 dev = dev_find_slot(0, PCI_DEVFN(3,3));   // USB 2.0
                 pci_write_config8(dev, 0x3C, 0x0A);
@@ -136,12 +142,17 @@
                 pci_write_config8(dev, 0x3C, 0x05);
                 dev = dev_find_slot(0, PCI_DEVFN(5,0));    // 1183 (SATA)
                 pci_write_config8(dev, 0x3C, 0x0B);
-//                dev = dev_find_slot(0, PCI_DEVFN(6,0));   // PCI-E
-//                pci_write_config8(dev, 0x3C, 0x0A);
-//                dev = dev_find_slot(0, PCI_DEVFN(7,0));   // PCI-E
-//                pci_write_config8(dev, 0x3C, 0x0A);
+
+                /*
+                 * Non-layout for GA-2761GX
+                 *
+                dev = dev_find_slot(0, PCI_DEVFN(6,0));   // PCI-E
+                pci_write_config8(dev, 0x3C, 0x0A);
+                dev = dev_find_slot(0, PCI_DEVFN(7,0));   // PCI-E
+                pci_write_config8(dev, 0x3C, 0x0A);
                 dev = dev_find_slot(0, PCI_DEVFN(15,0));  // Azalia
                 pci_write_config8(dev, 0x3C, 0x05);
+                */
         }
 
 //pci bridge

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -33,7 +33,7 @@
 
 extern unsigned apicid_sis966;
 
-extern unsigned bus_type[256]; 
+extern unsigned bus_type[256];
 
 void *smp_write_config_table(void *v)
 {
@@ -80,7 +80,7 @@
                 device_t dev;
 		struct resource *res;
 		uint32_t dword;
- 
+
                 dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
                 if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_1);
@@ -99,7 +99,7 @@
 
                 }
 	}
-  
+
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
 */	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sis966, 0x1);
@@ -135,7 +135,7 @@
         	}
 	}
 
-	for(j=0; j<2; j++) 
+	for(j=0; j<2; j++)
 	        for(i=0;i<4;i++) {
         	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[1], ((0x06+j)<<2)|i, apicid_sis966, 0x10 + (2+i+j)%4);
 	        }

Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -161,7 +161,7 @@
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -199,7 +199,7 @@
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
@@ -217,7 +217,7 @@
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -225,7 +225,7 @@
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
@@ -270,9 +270,9 @@
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
 	};
 

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/Config.lb	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/Config.lb	2007-11-02 16:09:58 UTC (rev 2931)
@@ -1,27 +1,26 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
 ## Written by Morgan Tsai <my_tsai at sis.com> for SiS.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 config chip.h
-#driver sis_agp.o
-driver sisnb.o
+driver sis761.o
 driver sis966.o
 driver sis966_usb.o
 driver sis966_lpc.o

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/chip.h	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/chip.h	2007-11-02 16:09:58 UTC (rev 2931)
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/romstrap.inc
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/romstrap.inc	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/romstrap.inc	2007-11-02 16:09:58 UTC (rev 2931)
@@ -43,29 +43,17 @@
 	.long 0xFFFFFFFF			// 28h
 	.long 0xFFFFFFFF			// 2Ch
 
-// MAC address -------------------------------- 0x7FFC0h	
 	.long 0x56341200			// 30h, MAC address low 4 byte ---> keep it in 0xffffffc0
 	.long 0x00009078			// 34h, MAC address high 4 byte
 
 	.long 0x002309CE			// 38h, UUID low 4 byte
 	.long 0x00E08100			// 3Ch, UUID high 4 byte
 
+	.long 0x00402000			//Firmware trap for SiS761+966
+	.long 0xE043A800
+	.long 0x00180000
+	.long 0x1421C402
 
-// Firmware Trap --------------------------------  0x7FFD0h	
-/* 
-//Firmware trap for SiS761+966         
-        .long 0x00402000
-        .long 0x6043A800  
-        .long 0x00180000
-        .long 0x1421C402 	
-*/        
- 
-//Firmware trap for SiS756+966              ---> keep it in 0xffffffd0
-        .long 0x00402000
-        .long 0xE043A800  
-        .long 0x00180000
-        .long 0x1421C402 
-
 rspointers:
 	.long rstables				// It will be 0xffffffe0
 	.long rstables

Added: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ * Turn off machine check triggers when reading
+ * pci space where there are no devices.
+ * This is necessary when scaning the bus for
+ * devices which is done by the kernel
+ *
+ * written in 2003 by Eric Biederman
+ *
+ *  - Athlon64 workarounds by Stefan Reinauer
+ *  - "reset once" logic by Yinghai Lu
+ * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
+ * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <part/hard_reset.h>
+#include <pc80/mc146818rtc.h>
+#include <bitops.h>
+#include <cpu/amd/model_fxx_rev.h>
+
+//#include "amdk8.h"
+
+#include <arch/io.h>
+
+/**
+ * @brief Read resources for AGP aperture
+ *
+ * @param
+ *
+ * There is only one AGP aperture resource needed. The resoruce is added to
+ * the northbridge of BSP.
+ *
+ * The same trick can be used to augment legacy VGA resources which can
+ * be detect by generic pci reousrce allocator for VGA devices.
+ * BAD: it is more tricky than I think, the resource allocation code is
+ * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * purpose :-(.
+ */
+
+
+typedef struct msr_struct
+{
+	unsigned lo;
+	unsigned hi;
+} msr_t;
+
+static inline msr_t rdmsr(unsigned index)
+{
+	msr_t result;
+	result.lo = 0;
+	result.hi = 0;
+	return result;
+}
+
+
+
+static void sis761_read_resources(device_t dev)
+{
+	struct resource *resource;
+	unsigned char iommu;
+	/* Read the generic PCI resources */
+	printk_debug("sis761_read_resources\n");
+	pci_dev_read_resources(dev);
+
+	/* If we are not the first processor don't allocate the gart apeture */
+	if (dev->path.u.pci.devfn != PCI_DEVFN(0x0, 0)) {
+		return;
+	}
+
+
+	return;
+
+	iommu = 1;
+	get_option(&iommu, "iommu");
+
+	if (iommu) {
+		/* Add a Gart apeture resource */
+		resource = new_resource(dev, 0x94);
+		resource->size = iommu?AGP_APERTURE_SIZE:1;
+		resource->align = log2(resource->size);
+		resource->gran  = log2(resource->size);
+		resource->limit = 0xffffffff; /* 4G */
+		resource->flags = IORESOURCE_MEM;
+	}
+}
+
+static void set_agp_aperture(device_t dev)
+{
+	struct resource *resource;
+
+	return;
+
+	resource = probe_resource(dev, 0x94);
+	if (resource) {
+		device_t pdev;
+		uint32_t gart_base, gart_acr;
+
+		/* Remember this resource has been stored */
+		resource->flags |= IORESOURCE_STORED;
+
+		/* Find the size of the GART aperture */
+		gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
+
+		/* Get the base address */
+		gart_base = ((resource->base) >> 25) & 0x00007fff;
+
+		/* Update the other northbriges */
+		pdev = 0;
+		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
+			/* Store the GART size but don't enable it */
+			pci_write_config32(pdev, 0x90, gart_acr);
+
+			/* Store the GART base address */
+			pci_write_config32(pdev, 0x94, gart_base);
+
+			/* Don't set the GART Table base address */
+			pci_write_config32(pdev, 0x98, 0);
+
+			/* Report the resource has been stored... */
+			report_resource_stored(pdev, resource, " <gart>");
+		}
+	}
+}
+
+static void sis761_set_resources(device_t dev)
+{
+        printk_debug("sis761_set_resources ------->\n");
+	/* Set the gart apeture */
+//	set_agp_aperture(dev);
+
+	/* Set the generic PCI resources */
+	pci_dev_set_resources(dev);
+	printk_debug("sis761_set_resources <-------\n");
+}
+
+static void sis761_init(struct device *dev)
+{
+	uint32_t cmd, cmd_ref;
+	int needs_reset;
+	struct device *f0_dev, *f2_dev;
+	msr_t	msr;
+
+
+	needs_reset = 0;
+	printk_debug("sis761_init: ---------->\n");
+
+	msr = rdmsr(0xC001001A);
+	pci_write_config16(dev, 0x8E, msr.lo >> 16);				// Topbound
+	pci_write_config8(dev, 0x7F, 0x08);			// ACPI Base
+	outb(inb(0x856) | 0x40, 0x856);	 // Auto-Reset Function
+
+	printk_debug("sis761_init: <----------\n");
+	printk_debug("done.\n");
+}
+
+
+static struct device_operations sis761_ops  = {
+	.read_resources   = sis761_read_resources,
+	.set_resources    = sis761_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = sis761_init,
+	.scan_bus         = 0,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver sis761_driver __pci_driver = {
+	.ops    = &sis761_ops,
+	.vendor = PCI_VENDOR_ID_SIS,
+	.device = PCI_DEVICE_ID_SIS_SIS761,
+};

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -49,7 +49,7 @@
 		) ) {
 			uint32_t id;
 			id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
-			if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16))) 	
+			if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16)))
 				) {
 				lpc_dev = 0;
 			}
@@ -62,19 +62,18 @@
 {
 	device_t lpc_dev = 0;
 	device_t sm_dev = 0;
-	unsigned index = 0;
-	unsigned index2 = 0;
+	uint16_t index = 0;
+	uint16_t index2 = 0;
 	uint32_t reg_old, reg;
 	uint8_t byte;
-	unsigned deviceid;
-	unsigned vendorid;
+	uint16_t deviceid;
+	uint16_t vendorid;
+	uint16_t devfn;
 
 	struct southbridge_sis_sis966_config *conf;
 	conf = dev->chip_info;
 	int i;
 
-	unsigned devfn;
-
 	if(dev->device==0x0000) {
 		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
 		deviceid = (vendorid>>16) & 0xffff;
@@ -88,25 +87,16 @@
 	switch(deviceid) {
 		case PCI_DEVICE_ID_SIS_SIS966_HT:
 			return;
-
-		case PCI_DEVICE_ID_SIS_SIS966_SM2://?
-			index = 16;
 			break;
 		case PCI_DEVICE_ID_SIS_SIS966_USB:
 			devfn -= (1<<3);
 			index = 8;
 			break;
-		case PCI_DEVICE_ID_SIS_SIS966_EHCI:
+		case PCI_DEVICE_ID_SIS_SIS966_USB2:
 			devfn -= (1<<3);
 			index = 20;
 			break;
-/*		case PCI_DEVICE_ID_SIS_SIS966_USB3:
-			devfn -= (1<<3);
-			index = 20;
-			break;
-*/
-		case PCI_DEVICE_ID_SIS_SIS966_NIC1: //two
-		case PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE://two
+		case PCI_DEVICE_ID_SIS_SIS966_NIC1:
 			devfn -= (7<<3);
 			index = 10;
 			for(i=0;i<2;i++) {
@@ -125,8 +115,7 @@
 			devfn -= (3<<3);
 			index = 14;
 			break;
-		case PCI_DEVICE_ID_SIS_SIS966_SATA0: //three
-		case PCI_DEVICE_ID_SIS_SIS966_SATA1: //three
+		case PCI_DEVICE_ID_SIS_SIS966_SATA0:
 			devfn -= (4<<3);
 			index = 22;
 			i = (dev->path.u.pci.devfn) & 7;
@@ -138,11 +127,7 @@
 			devfn -= (5<<3);
 			index = 15;
 			break;
-//		case PCI_DEVICE_ID_SIS_SIS966_PCIE_A:
-//			devfn -= (0x9<<3);  // to LPC
-//			index2 = 9;
-//			break;
-		case PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C: //two
+		case PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C:
 			devfn -= (0xa<<3);  // to LPC
 			index2 = 8;
 			for(i=0;i<2;i++) {
@@ -216,17 +201,8 @@
 		if(!sm_dev) return;
 
 		final_reg = pci_read_config32(sm_dev, 0xe8);
-		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
+		final_reg &= ~0x0057cf00;
 		pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
-#if 0
-		reg_old = reg = pci_read_config32(sm_dev, 0xe4);
-//		reg |= (1<<0);
-		reg &= ~(0x3f<<4);
-		if (reg != reg_old) {
-			printk_debug("sis966.c pcie enabled\n");
-			pci_write_config32(sm_dev, 0xe4, reg);
-		}
-#endif
 	}
 
 	if (!dev->enabled) {

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.h	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966.h	2007-11-02 16:09:58 UTC (rev 2931)
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
  *
@@ -24,6 +22,13 @@
 #ifndef SIS966_H
 #define SIS966_H
 
+#define DEBUG_AZA 0
+#define DEBUG_NIC 0
+#define DEBUG_IDE 0
+#define DEBUG_SATA 0
+#define DEBUG_USB 0
+#define DEBUG_USB2 0
+
 #include "chip.h"
 
 void sis966_enable(device_t dev);

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -32,10 +32,10 @@
 #include "sis966.h"
 
 uint8_t	SiS_SiS7502_init[7][3]={
-{0x04, 0xFF, 0x07},					 
-{0x2C, 0xFF, 0x39},					 
-{0x2D, 0xFF, 0x10},					 
-{0x2E, 0xFF, 0x91},					 
+{0x04, 0xFF, 0x07},
+{0x2C, 0xFF, 0x39},
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x91},
 {0x2F, 0xFF, 0x01},
 {0x04, 0xFF, 0x06},
 {0x00, 0x00, 0x00}					//End of table
@@ -61,7 +61,7 @@
 
 	if(!count) return -1;
 
-	udelay(540);
+	udelay(500);
 	return 0;
 
 }
@@ -71,30 +71,29 @@
 
 
      uint32_t dword;
-	 
+
      dword = readl(base + 0x68);
      dword=dword|(unsigned long)0x0002;
      writel(dword,base + 0x68);
-     do {	  	
-	 	dword = readl(base + 0x68);	   
+     do {
+	 	dword = readl(base + 0x68);
      }  while ((dword & 1)!=0);
      writel(verb, base + 0x60);
-     udelay(500);	 
-     dword = readl(base + 0x68);	  
-     dword =(dword |0x1);   
+     udelay(500);
+     dword = readl(base + 0x68);
+     dword =(dword |0x1);
      writel(dword, base + 0x68);
      do {
-	 	udelay(120);
+	 	udelay(100);
 		dword = readl(base + 0x68);
      } while ((dword & 3) != 2);
 
      dword = readl(base + 0x64);
      return dword;
-		
+
 }
 
 
-#if 1
 static int codec_detect(uint8_t *base)
 {
 	uint32_t dword;
@@ -102,97 +101,31 @@
 
 	/* 1 */ // controller reset
 	printk_debug("controller reset\n");
-      
+
 	set_bits(base + 0x08, 1, 1);
-      
+
       do{
-	  	dword = readl(base + 0x08)&0x1;	
+	  	dword = readl(base + 0x08)&0x1;
 		if(idx++>1000) { printk_debug("controller reset fail !!! \n"); break;}
 	   } while (dword !=1);
-       
+
        dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
-       
+
        if(dword==0) {
 	   	printk_debug("No codec!\n");
 		return 0;
        }
 
 	 printk_debug("Codec ID = %lx\n", dword);
-	  
-#if 0
-	/* 2 */
-	dword = readl(base + 0x0e);
-	dword |= 7;
-	writel(dword, base + 0x0e);
 
-	/* 3 */
-	set_bits(base + 0x08, 1, 0);
-
-	/* 4 */
-	set_bits(base + 0x08, 1, 1);
-		
-	/* 5 */
-	dword = readl(base + 0xe);
-	dword &= 7;
-       
-	/* 6 */
-	if(!dword) {
-		set_bits(base + 0x08, 1, 0);
-		printk_debug("No codec!\n");
-		return 0;
-	}
-#endif 
        dword=0x1;
 	return dword;
 
 }
 
-#else
 
-static int codec_detect(uint8_t *base)
-{
-	uint32_t dword;
-
-	/* 1 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 2 */
-	dword = readl(base + 0x0e);
-	dword |= 7;
-	writel(dword, base + 0x0e);
-
-	/* 3 */
-	set_bits(base + 0x08, 1, 0);
-
-	/* 4 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 5 */
-	dword = readl(base + 0xe);
-	dword &= 7;
-
-	/* 6 */
-	if(!dword) {
-		set_bits(base + 0x08, 1, 0);
-		printk_debug("No codec!\n");
-		return 0;
-	}
-	return dword;
-
-}
-
-#endif
-
-#if 1
-
-// For SiS demo board PinConfig
 static uint32_t verb_data[] = {
-#if 0
- 00172083h,
- 00172108h,
- 001722ECh,
- 00172310h,
-#endif
+
 //14
 	0x01471c10,
 	0x01471d40,
@@ -255,79 +188,6 @@
 	0x01f71f01,
 };
 
-#else
-// orginal codec pin configuration setting
-
-static uint32_t verb_data[] = {
-#if 0
-	0x00172001,
-	0x001721e6,
-	0x00172200,
-	0x00172300,
-#endif
-
-	0x01471c10,
-	0x01471d44,
-	0x01471e01,
-	0x01471f01,
-//1
-	0x01571c12,
-	0x01571d14,
-	0x01571e01,
-	0x01571f01,
-//2
-	0x01671c11,
-	0x01671d60,
-	0x01671e01,
-	0x01671f01,
-//3
-	0x01771c14,
-	0x01771d20,
-	0x01771e01,
-	0x01771f01,
-//4
-	0x01871c30,
-	0x01871d9c,
-	0x01871ea1,
-	0x01871f01,
-//5
-	0x01971c40,
-	0x01971d9c,
-	0x01971ea1,
-	0x01971f02,
-//6
-	0x01a71c31,
-	0x01a71d34,
-	0x01a71e81,
-	0x01a71f01,
-//7
-	0x01b71c1f,
-	0x01b71d44,
-	0x01b71e21,
-	0x01b71f02,
-//8
-	0x01c71cf0,
-	0x01c71d11,
-	0x01c71e11,
-	0x01c71f41,
-//9
-	0x01d71c3e,
-	0x01d71d01,
-	0x01d71e83,
-	0x01d71f99,
-//10
-	0x01e71c20,
-	0x01e71d41,
-	0x01e71e45,
-	0x01e71f01,
-//11
-	0x01f71c50,
-	0x01f71d91,
-	0x01f71ec5,
-	0x01f71f01,
-};
-
-#endif 
 static unsigned find_verb(uint32_t viddid, uint32_t **verb)
 {
         if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
@@ -370,17 +230,6 @@
 	/* 3 */
 	for(i=0; i<verb_size; i++) {
 		send_verb(base,verb[i]);
-#if 0
-		do {
-			dword = readl(base + 0x68);
-		} while (dword & 1);
-
-		writel(verb[i], base + 0x60);
-
-		do {
-			dword = readl(base + 0x68);
-		} while ((dword & 3) != 2);
-#endif 
 	}
 	printk_debug("verb loaded!\n");
 }
@@ -398,45 +247,50 @@
 
 static void aza_init(struct device *dev)
 {
-	uint8_t *base;
-	struct resource *res;
-	uint32_t codec_mask;
+        uint8_t *base;
+        struct resource *res;
+        uint32_t codec_mask;
 
+        print_debug("AZALIA_INIT:---------->\n");
 
 //-------------- enable AZA (SiS7502) -------------------------
 {
-       uint8_t  temp8;
-       int i=0;
-	while(SiS_SiS7502_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
-					temp8 &= SiS_SiS7502_init[i][1];
-					temp8 |= SiS_SiS7502_init[i][2];									
-					pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
-					i++;
-	};
+        uint8_t  temp8;
+        int i=0;
+        while(SiS_SiS7502_init[i][0] != 0)
+        {
+                temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
+                temp8 &= SiS_SiS7502_init[i][1];
+                temp8 |= SiS_SiS7502_init[i][2];
+                pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
+                i++;
+        };
 }
 //-----------------------------------------------------------
 
 
-// put audio to D0 state
-pci_write_config8(dev, 0x54,0x00);
+        // put audio to D0 state
+        pci_write_config8(dev, 0x54,0x00);
 
-#if 0
+#if DEBUG_AZA
 {
-    int i;
-    printk_debug("Azalia PCI config \n");
-    for(i=0;i<0xFF;i+=4)
-    {
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug("  ");
+        int i;
+
+        print_debug("****** Azalia PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
         }
-        print_debug_hex32(pci_read_config32(dev,i));
-        print_debug("  ");    
-    }
-    print_debug("\r\n");
+        print_debug("\r\n");
 }
-#endif 
+#endif
 
 	res = find_resource(dev, 0x10);
 	if(!res)
@@ -452,26 +306,9 @@
 		codecs_init(base, codec_mask);
 	}
 
-#if 0
-{
-    int i;
-    printk_debug("Azalia PCI config \n");
-    for(i=0;i<0xFF;i+=4)
-    {
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug("  ");
-        }
-        outl(0x80000800+i,0xcf8);     
-        print_debug_hex32(inl(0xcfc));
-        print_debug("  ");    
-    }
-    print_debug("\r\n");
+        print_debug("AZALIA_INIT:<----------\n");
 }
-#endif 
 
-}
-
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -51,10 +51,10 @@
 static void soft_reset(void)
 {
 	set_bios_reset();
-#if 1
+
 	/* link reset */
 	outb(0x02, 0x0cf9);
 	outb(0x06, 0x0cf9);
-#endif
+
 }
 

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_setup_car.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_setup_car.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_setup_car.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -21,125 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-static int set_ht_link_sis966(uint8_t ht_c_num)
-{
-	unsigned vendorid = 0x10de;
-	unsigned val = 0x01610109;
-	/* Nvidia sis966 hardcode, hw can not set it automatically */
-	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
-}
-
-static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
-{
-	int i;
-
-	unsigned val;
-
-	val = inl(control);
-	val &= 0xfffffffe;
-	outl(val, control);
-
-	outl(0, index); //index
-	for(i = 0; i < max; i++) {
-		unsigned long reg;
-		reg = register_values[i];
-		outl(reg, where);
-	}
-
-	val = inl(control);
-	val |= 1;
-	outl(val, control);
-
-}
-
-/* SIZE 0x100 */
-#define ANACTRL_IO_BASE	0x2800
-#define ANACTRL_REG_POS	0x68
-
-/* SIZE 0x100 */
-#define SYSCTRL_IO_BASE	0x2400
-#define SYSCTRL_REG_POS	0x64
-
-/* SIZE 0x100 */
-#define ACPICTRL_IO_BASE	0x2000
-#define ACPICTRL_REG_POS	0x60
-
-/*
-	16 1 1 1 1 8 :0
-	16 0 4 0 0 8 :1
-	16 0 4 2 2 4 :2
-	 4 4 4 4 4 8 :3
-	 8 8 4 0 0 8 :4
-	 8 0 4 4 4 8 :5
-*/
-
-#ifndef SIS966_PCI_E_X_0
-	#define SIS966_PCI_E_X_0	4
-#endif
-#ifndef SIS966_PCI_E_X_1
-	#define SIS966_PCI_E_X_1	4
-#endif
-#ifndef SIS966_PCI_E_X_2
-	#define SIS966_PCI_E_X_2	4
-#endif
-#ifndef SIS966_PCI_E_X_3
-	#define SIS966_PCI_E_X_3	4
-#endif
-
-#ifndef SIS966_USE_NIC
-	#define SIS966_USE_NIC	0
-#endif
-
-#ifndef SIS966_USE_AZA
-	#define SIS966_USE_AZA	0
-#endif
-
-#define SIS966_CHIP_REV	3
-
-static void sis966_early_set_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base)
-{
-
-	static const unsigned int ctrl_devport_conf[] = {
-		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
-		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
-	};
-
-	int j;
-	for(j = 0; j < sis966_num; j++ ) {
-		setup_resource_map_offset(ctrl_devport_conf,
-			sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
-			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
-	}
-}
-
-static void sis966_early_clear_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base)
-{
-
-	static const unsigned int ctrl_devport_conf_clear[] = {
-		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
-	};
-
-	int j;
-	for(j = 0; j < sis966_num; j++ ) {
-		setup_resource_map_offset(ctrl_devport_conf_clear,
-			sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
-			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
-	}
-
-
-}
-static void delayx(uint8_t value) {
-#if 1
-	int i;
-	for(i=0;i<0x8000;i++) {
-		outb(value, 0x80);
-	}
-#endif
-}
-
 static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
 {
 	uint32_t tgio_ctrl;
@@ -170,260 +51,13 @@
 	outl(tgio_ctrl, anactrl_io_base + 0xcc);
 
 //	wait 100us
-	delayx(1);
+	udelay(100);
 
 	dword = pci_read_config32(dev, 0xe4);
 	dword &= ~(0x3f0); // enable
 	pci_write_config32(dev, 0xe4, dword);
 
 //	need to wait 100ms
-	delayx(1000);
+	mdelay(100);
 }
 
-static void sis966_early_setup(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
-{
-
-    static const unsigned int ctrl_conf_1[] = {
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
-
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
-
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
-
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
-    };
-
-    static const unsigned int ctrl_conf_1_1[] = {
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
-    };
-
-
-    static const unsigned int ctrl_conf_sis966_only[] = {
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
-
-//	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
-//	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
-
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
-
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
-#if SIS966_USE_AZA == 1
-	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
-
-//	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
-#endif
-// play a while with GPIO in SIS966
-#ifdef SIS966_MB_SETUP
-	SIS966_MB_SETUP
-#endif
-
-#if SIS966_USE_AZA == 1
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
-#endif
-
-
-    };
-
-    static const unsigned int ctrl_conf_master_only[] = {
-
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
-
-	//Master SIS966 ????YHLU
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
-
-    };
-
-    static const unsigned int ctrl_conf_2[] = {
-	/* I didn't put pcie related stuff here */
-
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
-
-	RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
-
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
-
-
-#if SIS966_USE_NIC == 1
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
-
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
-#endif
-
-    };
-
-
-	int j, i;
-
-	for(j=0; j<sis966_num; j++) {
-		sis966_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
-
-		setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-		for(i=0; i<3; i++) { // three SATA
-			setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
-				PCI_DEV(busn[j], devn[j], i), io_base[j]);
-		}
-		if(busn[j] == 0) {
-			setup_resource_map_x_offset(ctrl_conf_sis966_only, sizeof(ctrl_conf_sis966_only)/sizeof(ctrl_conf_sis966_only[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-		}
-
-		if( (busn[j] == 0) && (sis966_num>1) ) {
-			setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-		}
-
-		setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-
-	}
-
-#if 0
-	for(j=0; j< sis966_num; j++) {
-		// PCI-E (XSPLL) SS table 0x40, x044, 0x48
-		// SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
-		// CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
-			io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
-			io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
-		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
-			io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
-	}
-#endif
-
-}
-
-#ifndef HT_CHAIN_NUM_MAX
-
-#define HT_CHAIN_NUM_MAX	4
-#define HT_CHAIN_BUSN_D	0x40
-#define HT_CHAIN_IOBASE_D	0x4000
-
-#endif
-
-static int sis966_early_setup_x(void)
-{
-	/*find out how many sis966 we have */
-	unsigned busn[HT_CHAIN_NUM_MAX];
-	unsigned devn[HT_CHAIN_NUM_MAX];
-	unsigned io_base[HT_CHAIN_NUM_MAX];
-	/*
-		FIXME: May have problem if there is different SIS966 HTX card with different PCI_E lane allocation
-		Need to use same trick about pci1234 to verify node/link connection
-	*/
-	unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {SIS966_PCI_E_X_0, SIS966_PCI_E_X_1, SIS966_PCI_E_X_2, SIS966_PCI_E_X_3 };
-	int sis966_num = 0;
-	unsigned busnx;
-	unsigned devnx;
-	int ht_c_index,j;
-
-	/* FIXME: multi pci segment handling */
-
-	/* Any system that only have IO55 without SIS966? */
-	for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) {
-		busnx = ht_c_index * HT_CHAIN_BUSN_D;
-		for(devnx=0;devnx<0x20;devnx++) {
-			uint32_t id;
-			device_t dev;
-			dev = PCI_DEV(busnx, devnx, 0);
-			id = pci_read_config32(dev, PCI_VENDOR_ID);
-			if(id == 0x036910de) {
-				busn[sis966_num] = busnx;
-				devn[sis966_num] = devnx;
-				io_base[sis966_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than SIS966
-				sis966_num++;
-				if(sis966_num == SIS966_NUM) goto out;
-				break; // only one SIS966 on one chain
-			}
-		}
-	}
-
-out:
-	print_debug("sis966_num:"); print_debug_hex8(sis966_num); print_debug("\r\n");
-
-	//sis966_early_set_port(sis966_num, busn, devn, io_base);
-	//sis966_early_setup(sis966_num, busn, devn, io_base, pci_e_x);
-
-	//sis966_early_clear_port(sis966_num, busn, devn, io_base);
-
-//	set_ht_link_sis966(HT_CHAIN_NUM_MAX);
-
-	return 0;
-
-}
-
-
-

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -570,14 +570,14 @@
                             => Others:  Reserved
 */
 void Init_Share_Memory(uint8_t ShareSize)
-{  
+{
     device_t dev;
- 
+
     dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
     pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5));
 }
- 
-/* In:     => Aperture size 
+
+/* In:     => Aperture size
                => 00h :   32MBytes
                => 01h :   64MBytes
                => 02h :  128MBytes
@@ -587,77 +587,24 @@
 */
 void Init_Aper_Size(uint8_t AperSize)
 {
- device_t dev;
- uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
- 
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
- pci_write_config8(dev, 0x90, AperSize << 1);
+        device_t dev;
+        uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
 
-//pci_write_config32(dev, 0x94, 0x78);
-//pci_write_config32(dev, 0x98, 0x0);
- 
-#if 0
-{
-int i;
-print_debug("Function3 Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{   if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
+        pci_write_config8(dev, 0x90, AperSize << 1);
 
-dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
-pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
-
-#if 0
-{
-int i;
-dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1101), 0);
-print_debug("Function1 Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+        pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
 }
-print_debug("\n");  
-}
 
- #endif 
-
- 
-}
-
- 
-
-
-
 void sis_init_stage1(void)
 {
-  device_t dev;
-	uint8_t temp8;
-  int	i;
-	uint8_t	GUI_En;   
+        device_t dev;
+        uint8_t temp8;
+        int	i;
+        uint8_t	GUI_En;
 
-#if 0
-{
-int i;
-print_debug("Northbridge PCI Config in sis_init_stage1.0\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 	
-
-// SiS_Chipset_Initialization	
+// SiS_Chipset_Initialization
 // ========================== NB =============================
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
 	i=0;
@@ -669,23 +616,6 @@
 					i++;
 	};
 
-
-#if 0
-{
-int i;
-print_debug("Northbridge PCI Config in sis_init_stage1.1\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
-
-
-	
 // ========================== LPC =============================
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 	i=0;
@@ -723,16 +653,16 @@
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);		//Restore Internal GUI enable bit
 	temp8 = pci_read_config8(dev, 0x4C);
 	pci_write_config8(dev, 0x4C, temp8 | GUI_En);
-	
-     return;				
+
+     return;
 }
 
 
 
 void sis_init_stage2(void)
 {
-  	device_t dev;	
-  	msr_t	msr; 
+  	device_t dev;
+  	msr_t	msr;
 	int	i;
 	uint32_t j;
 	uint8_t temp8;
@@ -740,90 +670,57 @@
 
 
 // ========================== NB_AGP =============================
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);   //Enable Internal GUI enable bit
- pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
- 
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, 0x0002), 0);
- i=0;
- while(SiS_NBAGP_init[i][0] != 0)
- {    temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
-     temp8 &= SiS_NBAGP_init[i][1];
-     temp8 |= SiS_NBAGP_init[i][2];
-     pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
-     i++;
- };
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);   //Enable Internal GUI enable bit
+        pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
 
-/*       In => Share Memory size 
-                            => 00h :    0MBytes
-                            => 02h :   32MBytes
-                            => 03h :   64MBytes
-                            => 04h :  128MBytes
-                            => Others:  Reserved
-*/
-/* In:     => Aperture size 
-               => 00h :   32MBytes
-               => 01h :   64MBytes
-               => 02h :  128MBytes
-               => 03h :  256MBytes
-               => 04h :  512MBytes
-               => Others:  Reserved
-*/
- 
-  Init_Share_Memory(0x02);  //0x02 : 32M  0x03 : 64M
-  Init_Aper_Size(0x01);   // 0x1
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
+        i=0;
 
-#if 0
-{
-int i;
-print_debug("AGP PCI Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
+        while(SiS_NBAGP_init[i][0] != 0)
+        {
+                temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
+                temp8 &= SiS_NBAGP_init[i][1];
+                temp8 |= SiS_NBAGP_init[i][2];
+                pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
+                i++;
+        };
 
+/**
+  *   Share Memory size
+  *             => 00h :    0MBytes
+  *             => 02h :   32MBytes
+  *             => 03h :   64MBytes
+  *             => 04h :  128MBytes
+  *             => Others:  Reserved
+  *
+  *   Aperture size
+  *             => 00h :   32MBytes
+  *             => 01h :   64MBytes
+  *             => 02h :  128MBytes
+  *             => 03h :  256MBytes
+  *             => 04h :  512MBytes
+  *             => Others:  Reserved
+  */
 
+        Init_Share_Memory(0x02);  //0x02 : 32M
+        Init_Aper_Size(0x01);   //0x1 : 64M
+
 // ========================== NB =============================
 
-	printk_debug("Init NorthBridge sis761 -------->\n");
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
-	msr = rdmsr(0xC001001A);
-	printk_debug("Memory Top Bound %lx\n",msr.lo );
-// 	pci_write_config16(dev, 0x8E, msr.lo >> 16);				// Topbound
-//    pci_write_config16(dev, 0x8E, (msr.lo >> 16) - ((pci_read_config8(dev, 0x4C) & 0xE0) >> 5));
- 
-    temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
-    //printk_debug("0x4c = %x\n",temp16);
-    temp16=0x0001<<(temp16-1);
-    temp16<<=8;
-   
-    printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
-    pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
-  // pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16);
-    pci_write_config8(dev, 0x7F, 0x08);									// ACPI Base
-    outb(inb(0x856) | 0x40, 0x856);										// Auto-Reset Function
+        printk_debug("Init NorthBridge sis761 -------->\n");
+        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+        msr = rdmsr(0xC001001A);
+	 printk_debug("Memory Top Bound %lx\n",msr.lo );
 
-#if 0
-{
-int i;
-print_debug("Northbridge PCI Config in sis_init_stage2\n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\n");  
-}
-#endif 
+        temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
+        temp16=0x0001<<(temp16-1);
+        temp16<<=8;
 
+        printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
+        pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
+        pci_write_config8(dev, 0x7F, 0x08);									// ACPI Base
+        outb(inb(0x856) | 0x40, 0x856);										// Auto-Reset Function
 
-
-
 // ========================== ACPI =============================
 	i=0;
 	printk_debug("Init ACPI -------->\n");
@@ -839,57 +736,40 @@
        printk_debug("Init Misc -------->\n");
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_ISA), 0);
 	// PCI Device Enable
-	pci_write_config8(dev, 0x7C, 0x03);  // bit0=0 : enable audio controller(), bit1=1 : disable modem 
+	pci_write_config8(dev, 0x7C, 0x03);  // bit0=0 : enable audio controller(), bit1=1 : disable modem
 	pci_write_config8(dev, 0x76, pci_read_config8(dev, 0x76)|0x30);  // SM bus enable, PCIEXP Controller 1 and 2 disable
-	pci_write_config8(dev, 0x7E, 0x00);  // azalia controller enable 
+	pci_write_config8(dev, 0x7E, 0x00);  // azalia controller enable
 
 	temp8=inb(0x878)|0x4;   //bit2=1 enable Azalia  =0 enable AC97
 	outb(temp8, 0x878);  // ACPI select AC97 or HDA controller
 	printk_debug("Audio select %x\n",inb(0x878));
-	
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, 0x1183), 0);	
-	if(!dev){			
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA0), 0);
+	if(!dev){
 		print_debug("SiS 1183 does not exist !!");
 	}
 	// SATA Set Mode
 	pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);
-	
 
-//-------------- enable IDE (SiS1183) -------------------------
-/*
-{    
-       uint8_t  temp8;
-       int i=0;
-	while(SiS_SiS1183_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
-					temp8 &= SiS_SiS1183_init[i][1];
-					temp8 |= SiS_SiS1183_init[i][2];				
-					pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
-					i++;
-	};
 }
 
-*/
 
-}
 
-
-
 static void enable_smbus(void)
 {
 	device_t dev;
 	uint8_t temp8;
 	printk_debug("enable_smbus -------->\n");
-	
+
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 
 	/* set smbus iobase && enable ACPI Space*/
-	pci_write_config16(dev, 0x74, 0x0800);			// Set ACPI Base
+	pci_write_config16(dev, 0x74, 0x0800);				// Set ACPI Base
 	temp8=pci_read_config8(dev, 0x40);					// Enable ACPI Space
 	pci_write_config8(dev, 0x40, temp8 | 0x80);
 	temp8=pci_read_config8(dev, 0x76);					// Enable SMBUS
 	pci_write_config8(dev, 0x76, temp8 | 0x03);
-	
+
 	printk_debug("enable_smbus <--------\n");
 }
 

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_enable_rom.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_enable_rom.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_enable_rom.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -32,7 +32,7 @@
 static void sis966_enable_rom(void)
 {
 	device_t addr;
- 
+
 	/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
 	addr = pci_locate_device(PCI_ID(0x1039, 0x0966), 0);
 

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -32,44 +32,44 @@
 #include "sis966.h"
 
 uint8_t	SiS_SiS5513_init[49][3]={
-{0x04, 0xFF, 0x05},					 
-{0x0D, 0xFF, 0x80},					 
-{0x2C, 0xFF, 0x39},					 
-{0x2D, 0xFF, 0x10},					  
-{0x2E, 0xFF, 0x13},					 
-{0x2F, 0xFF, 0x55},					 
-{0x50, 0xFF, 0xA2},					 
-{0x51, 0xFF, 0x21},					 
-{0x53, 0xFF, 0x21},					 
-{0x54, 0xFF, 0x2A},					 
-{0x55, 0xFF, 0x96},					 
-{0x52, 0xFF, 0xA2},					 
-{0x56, 0xFF, 0x81},					 
-{0x57, 0xFF, 0xC0},					 
-{0x60, 0xFF, 0xFB},					 
-{0x61, 0xFF, 0xAA},					 
-{0x62, 0xFF, 0xFB},					 
-{0x63, 0xFF, 0xAA},					 
-{0x81, 0xFF, 0xB3},					 
-{0x82, 0xFF, 0x72},					 
-{0x83, 0xFF, 0x40},					 
-{0x85, 0xFF, 0xB3},					 
-{0x86, 0xFF, 0x72},					 
-{0x87, 0xFF, 0x40},					 
-{0x94, 0xFF, 0xC0},					 
-{0x95, 0xFF, 0x08},					 
-{0x96, 0xFF, 0xC0},					 
-{0x97, 0xFF, 0x08},					 
-{0x98, 0xFF, 0xCC},					 
-{0x99, 0xFF, 0x04},					 
-{0x9A, 0xFF, 0x0C},					 
-{0x9B, 0xFF, 0x14},					 
-{0xA0, 0xFF, 0x11},					 
-{0x57, 0xFF, 0xD0},	
+{0x04, 0xFF, 0x05},
+{0x0D, 0xFF, 0x80},
+{0x2C, 0xFF, 0x39},
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x13},
+{0x2F, 0xFF, 0x55},
+{0x50, 0xFF, 0xA2},
+{0x51, 0xFF, 0x21},
+{0x53, 0xFF, 0x21},
+{0x54, 0xFF, 0x2A},
+{0x55, 0xFF, 0x96},
+{0x52, 0xFF, 0xA2},
+{0x56, 0xFF, 0x81},
+{0x57, 0xFF, 0xC0},
+{0x60, 0xFF, 0xFB},
+{0x61, 0xFF, 0xAA},
+{0x62, 0xFF, 0xFB},
+{0x63, 0xFF, 0xAA},
+{0x81, 0xFF, 0xB3},
+{0x82, 0xFF, 0x72},
+{0x83, 0xFF, 0x40},
+{0x85, 0xFF, 0xB3},
+{0x86, 0xFF, 0x72},
+{0x87, 0xFF, 0x40},
+{0x94, 0xFF, 0xC0},
+{0x95, 0xFF, 0x08},
+{0x96, 0xFF, 0xC0},
+{0x97, 0xFF, 0x08},
+{0x98, 0xFF, 0xCC},
+{0x99, 0xFF, 0x04},
+{0x9A, 0xFF, 0x0C},
+{0x9B, 0xFF, 0x14},
+{0xA0, 0xFF, 0x11},
+{0x57, 0xFF, 0xD0},
 
-{0xD8, 0xFE, 0x01},	// Com reset				 
-{0xC8, 0xFE, 0x01},					 
-{0xC4, 0xFF, 0xFF},    // Clear status					 
+{0xD8, 0xFE, 0x01},    // Com reset
+{0xC8, 0xFE, 0x01},
+{0xC4, 0xFF, 0xFF},    // Clear status
 {0xC5, 0xFF, 0xFF},
 {0xC6, 0xFF, 0xFF},
 {0xC7, 0xFF, 0xFF},
@@ -78,10 +78,10 @@
 {0xD6, 0xFF, 0xFF},
 {0xD7, 0xFF, 0xFF},
 
-				 
-{0x2C, 0xFF, 0x39},	// set subsystem ID 					 
-{0x2D, 0xFF, 0x10},					 
-{0x2E, 0xFF, 0x13},					 
+
+{0x2C, 0xFF, 0x39},	// set subsystem ID
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x13},
 {0x2F, 0xFF, 0x55},
 
 
@@ -96,22 +96,23 @@
 	uint16_t word;
 	uint8_t byte;
 	conf = dev->chip_info;
-	
-	
 
-printk_debug("ide_init:---------->\n");
 
 
+print_debug("IDE_INIT:---------->\n");
+
+
 //-------------- enable IDE (SiS5513) -------------------------
 {
-       uint8_t  temp8;
-       int i=0;
+        uint8_t  temp8;
+        int i=0;
 	while(SiS_SiS5513_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
-					temp8 &= SiS_SiS5513_init[i][1];
-					temp8 |= SiS_SiS5513_init[i][2];				
-					pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
-					i++;
+	{
+                temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
+                temp8 &= SiS_SiS5513_init[i][1];
+                temp8 |= SiS_SiS5513_init[i][2];
+                pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
+                i++;
 	};
 }
 //-----------------------------------------------------------
@@ -146,7 +147,27 @@
 	pci_dev_init(dev);
 #endif
 
+#if DEBUG_IDE
+{
+        int i;
+
+        print_debug("****** IDE PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
+        }
+        print_debug("\r\n");
 }
+#endif
+print_debug("IDE_INIT:<----------\n");
+}
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -151,81 +151,33 @@
 	lpc_common_init(dev);
 }
 
-#if 0
-static void enable_hpet(struct device *dev)
-{
-	unsigned long hpet_address;
 
-	pci_write_config32(dev,0x44, 0xfed00001);
-	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
-	printk_debug("enabling HPET @0x%x\n", hpet_address);
-}
-#endif
-
 static void lpc_usb_legacy_init(device_t dev)
 {
     uint16_t acpi_base;
 
     acpi_base = (pci_read_config8(dev,0x75) << 8);
-    //printk_debug("ACPI Base Addr=0x%4.4x\n",acpi_base);
 
-    //printk_debug("acpi_base + 0xbb=%.2x\n", inb(acpi_base + 0xbb));
-    //printk_debug("acpi_base + 0xba=%.2x\n", inb(acpi_base + 0xba));
-
     outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
     outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
-
-    //printk_debug("acpi_base + 0xbb=%.2x\n", inb(acpi_base + 0xbb));
-    //printk_debug("acpi_base + 0xba=%.2x\n", inb(acpi_base + 0xba));
-
-    return;
 }
 
 static void lpc_init(device_t dev)
 {
-	uint8_t byte;
-	uint8_t byte_old;
-	int on;
-	int nmi_option;
+	 uint8_t byte;
+	 uint8_t byte_old;
+	 int on;
+	 int nmi_option;
 
-        printk_debug("lpc_init -------->\n");
+        printk_debug("LPC_INIT -------->\n");
         init_pc_keyboard(0x60, 0x64, 0);
 
-#if 0
-            {
-            int i;
-            printk_debug("LPC PCI config \n");
-            for(i=0;i<0xFF;i+=4)
-            {
-              if((i%16)==0)
-              {
-                print_debug("\r\n");
-                print_debug_hex8(i);
-                print_debug("  ");}
-                print_debug_hex32(pci_read_config32(dev,i));
-                print_debug("  ");    
-              }
-              print_debug("\r\n");
-            }
-#endif
-            printk_debug("lpc_init <--------\n");
-            lpc_usb_legacy_init(dev);
-            return;
-	
-       printk_debug("lpc_init\r\n");
-	lpc_common_init(dev);
-       printk_debug("lpc_init2\r\n");
+        lpc_usb_legacy_init(dev);
+	 lpc_common_init(dev);
 
-
-#if 0
-	/* posted memory write enable */
-	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0));
-
-#endif
 	/* power after power fail */
 
-#if 1
+
 	on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
@@ -235,7 +187,7 @@
 	}
 	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 	printk_info("set power %s after power fail\n", on?"on":"off");
-#endif
+
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
@@ -249,44 +201,34 @@
 		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 				(on*12)+(on>>1),(on&1)*5);
 	}
- 
-#if 0
-// default is enabled
-	/* Enable Port 92 fast reset */
-	byte = pci_read_config8(dev, 0xe8);
-	byte |= ~(1 << 3);
-	pci_write_config8(dev, 0xe8, byte);
-#endif
 
-	/* Enable Error reporting */
-	/* Set up sync flood detected */
-	byte = pci_read_config8(dev, 0x47);
-	byte |= (1 << 1);
-	pci_write_config8(dev, 0x47, byte);
+        /* Enable Error reporting */
+        /* Set up sync flood detected */
+        byte = pci_read_config8(dev, 0x47);
+        byte |= (1 << 1);
+        pci_write_config8(dev, 0x47, byte);
 
-	/* Set up NMI on errors */
-	byte = inb(0x70); // RTC70
-	byte_old = byte;
-	nmi_option = NMI_OFF;
-	get_option(&nmi_option, "nmi");
-	if (nmi_option) {
-		byte &= ~(1 << 7); /* set NMI */
-	} else {
-		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
-	}
-	if( byte != byte_old) {
-		outb(0x70, byte);
-	}
+        /* Set up NMI on errors */
+        byte = inb(0x70); // RTC70
+        byte_old = byte;
+        nmi_option = NMI_OFF;
+        get_option(&nmi_option, "nmi");
+        if (nmi_option) {
+                byte &= ~(1 << 7); /* set NMI */
+        } else {
+                byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+        }
+        if( byte != byte_old) {
+                outb(0x70, byte);
+        }
 
-	/* Initialize the real time clock */
-	rtc_init(0);
+        /* Initialize the real time clock */
+        rtc_init(0);
 
-	/* Initialize isa dma */
-	isa_dma_init();
+        /* Initialize isa dma */
+        isa_dma_init();
 
-	/* Initialize the High Precision Event Timers */
-//	enable_hpet(dev);
-
+        printk_debug("LPC_INIT <--------\n");
 }
 
 static void sis966_lpc_read_resources(device_t dev)
@@ -403,38 +345,6 @@
 	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC,
 };
 
-static const struct pci_driver lpc_driver_pro __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_PRO,
-};
-
-static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_2,
-};
-static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_3,
-};
-static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_4,
-};
-static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_5,
-};
-static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC_6,
-};
-
 static struct device_operations lpc_slave_ops  = {
 	.read_resources	= sis966_lpc_read_resources,
 	.set_resources	= pci_dev_set_resources,
@@ -443,9 +353,3 @@
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
-
-static const struct pci_driver lpc_driver_slave __pci_driver = {
-	.ops	= &lpc_slave_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_SLAVE,
-};

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -35,16 +35,16 @@
 
 
 uint8_t	SiS_SiS191_init[6][3]={
-{0x04, 0xFF, 0x07},					 
-{0x2C, 0xFF, 0x39},					 
-{0x2D, 0xFF, 0x10},					 
-{0x2E, 0xFF, 0x91},					 
+{0x04, 0xFF, 0x07},
+{0x2C, 0xFF, 0x39},
+{0x2D, 0xFF, 0x10},
+{0x2E, 0xFF, 0x91},
 {0x2F, 0xFF, 0x01},
 {0x00, 0x00, 0x00}					//End of table
 };
 
-#if 1
-#define StatusReg       0x1    
+
+#define StatusReg       0x1
 #define SMI_READ	0x0
 #define SMI_REQUEST	0x10
 #define TRUE            1
@@ -56,7 +56,7 @@
 void writeApcByte(int addr, uint8_t value)
 {
     outb(addr,0x78);
-    outb(value,0x79); 
+    outb(value,0x79);
 }
 uint8_t readApcByte(int addr)
 {
@@ -72,11 +72,11 @@
 
 // enable APC in south bridge sis966 D2F0
 
-    outl(0x80001048,0xcf8);  
+    outl(0x80001048,0xcf8);
     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
 
     printk_debug("MAC addr in APC = ");
-    for(i = 0x9 ; i <=0xe ; i++) 
+    for(i = 0x9 ; i <=0xe ; i++)
     {
         printk_debug("%2.2x",readApcByte(i));
     }
@@ -85,9 +85,9 @@
     /* Set APC Reload */
     writeApcByte(0x7,readApcByte(0x7)&0xf7);
     writeApcByte(0x7,readApcByte(0x7)|0x0a);
-          	
+
     /* disable APC in south bridge */
-    outl(0x80001048,0xcf8); 
+    outl(0x80001048,0xcf8);
     outl(inl(0xcfc)&0xffffffbf,0xcfc);
 }
 
@@ -100,9 +100,9 @@
     uint8_t   bTmp;
 
     /* enable APC in south bridge sis966 D2F0 */
-    outl(0x80001048,0xcf8);  
+    outl(0x80001048,0xcf8);
     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
-          
+
     for(i = 0 ; i <3; i++)
     {
        addr=0x9+2*i;
@@ -114,13 +114,13 @@
     /* Set APC Reload */
     writeApcByte(0x7,readApcByte(0x7)&0xf7);
     writeApcByte(0x7,readApcByte(0x7)|0x0a);
-          	
+
     /* disable APC in south bridge */
-    outl(0x80001048,0xcf8); 
+    outl(0x80001048,0xcf8);
     outl(inl(0xcfc)&0xffffffbf,0xcfc);
 
-    // CFG reg0x73 bit=1, tell driver MAC Address load to APC 	
-    bTmp = pci_read_config8(dev, 0x73);			
+    // CFG reg0x73 bit=1, tell driver MAC Address load to APC
+    bTmp = pci_read_config8(dev, 0x73);
     bTmp|=0x1;
     pci_write_config8(dev, 0x73, bTmp);
 }
@@ -142,12 +142,12 @@
     uint16_t 	data;
     uint32_t 	i;
     uint32_t 	ulValue;
-    
-    
+
+
     ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
 
     writel( ulValue,base+0x3c);
-		
+
     mdelay(10);
 
     for(i=0 ; i <= LoopNum; i++)
@@ -159,15 +159,15 @@
 
         mdelay(100);
     }
-	
+
     mdelay(50);
 
     if(i==LoopNum)   data=0x10000;
     else{
     	ulValue=readl(base+0x3c);
     	data = (uint16_t)((ulValue & 0xffff0000) >> 16);
-    }			
-    
+    }
+
     return data;
 }
 
@@ -179,9 +179,9 @@
     uint16_t   usData;
 
     uint16_t   tmp;
-	 
 
-	   Read_Cmd = ((phy_reg << 11) |	
+
+	   Read_Cmd = ((phy_reg << 11) |
                        (phy_addr << 6) |
      		       SMI_READ |
      		       SMI_REQUEST);
@@ -189,21 +189,21 @@
            // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
           writel( Read_Cmd,base+0x44);
           //outl( Read_Cmd,tmp+0x44);
-           
+
            // Polling SMI_REQ bit to be deasserted indicated read command completed
            do
            {
 	       // Wait 20 usec before checking status
     	       //StallAndWait(20);
 		   mdelay(20);
-    	       ulValue = readl(base+0x44);	    
-    	       //ulValue = inl(tmp+0x44);	
+    	       ulValue = readl(base+0x44);
+    	       //ulValue = inl(tmp+0x44);
            } while((ulValue & SMI_REQUEST) != 0);
-            //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);          
+            //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
            usData=(ulValue>>16);
 
-	
 
+
 	return usData;
 
 }
@@ -216,55 +216,49 @@
     uint32_t		Read_Cmd;
     uint16_t		usData;
     int		       PhyAddress = 0;
-   
-  
+
+
         // Scan all PHY address(0 ~ 31) to find a valid PHY
         for(PhyAddress = 0; PhyAddress < 32; PhyAddress++)
-        {  
-		usData=phy_read(base,PhyAddress,StatusReg);  // Status register is a PHY's register(offset 01h)      
-           
-           // Found a valid PHY 
-     
+        {
+		usData=phy_read(base,PhyAddress,StatusReg);  // Status register is a PHY's register(offset 01h)
+
+           // Found a valid PHY
+
            if((usData != 0x0) && (usData != 0xffff))
            {
                bFoundPhy = TRUE;
                break;
            }
         }
-//        printk_debug(" PHY_Addr=%x\n",PhyAddress);
 
-	//usData=phy_read(base,PhyAddress,0x0);
-	//printk_debug("PHY=%x\n",usData);
 
 	if(!bFoundPhy)
 	{
 	    printk_debug("PHY not found !!!! \n");
-	   // DisableMac();
 	}
 
        *PhyAddr=PhyAddress;
-	
+
 	return bFoundPhy;
 }
 
 
 static void nic_init(struct device *dev)
 {
-	uint32_t dword, old;
-	uint32_t mac_h, mac_l;
-	int eeprom_valid = 0;
-	int val;
-	uint16_t  PhyAddr;
-	struct southbridge_sis_sis966_config *conf;
+        uint32_t dword, old;
+        uint32_t mac_h, mac_l;
+        int eeprom_valid = 0;
+        int val;
+        uint16_t  PhyAddr;
+        struct southbridge_sis_sis966_config *conf;
+        static uint32_t nic_index = 0;
+        uint32_t base;
+        struct resource *res;
+        uint32_t reg;
 
-	static uint32_t nic_index = 0;
 
-	uint32_t base;
-	struct resource *res;
-       uint32_t reg;
-	
-	
-printk_debug("SIS NIC init-------->\r\n");
+        print_debug("NIC_INIT:---------->\n");
 
 
 //-------------- enable NIC (SiS19x) -------------------------
@@ -272,121 +266,91 @@
         uint8_t  temp8;
         int i=0;
         while(SiS_SiS191_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
-					temp8 &= SiS_SiS191_init[i][1];
-					temp8 |= SiS_SiS191_init[i][2];				
-					pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
-					i++;
+	{
+                temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
+                temp8 &= SiS_SiS191_init[i][1];
+                temp8 |= SiS_SiS191_init[i][2];
+                pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
+                i++;
 	};
 }
 //-----------------------------------------------------------
 
-
-
-
 {
-unsigned long  i;
-unsigned long ulValue;
+        unsigned long  i;
+        unsigned long ulValue;
 
-#if 0
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
-print_debug("\r\n");
-#endif
 	res = find_resource(dev, 0x10);
 
-	if(!res) return;
-
+	if(!res)
+	{
+		printk_debug("NIC Cannot find resource..\r\n");
+		return;
+	}
 	base = res->base;
-printk_debug("NIC base address %lx\n",base);
-	if(!(val=phy_detect(base,&PhyAddr)))  
-	  {
-	      printk_debug("PHY detect fail !!!!\r\n"); 
-		return;		  
-	   }	
+        printk_debug("NIC base address %lx\n",base);
 
-#if 0
-//------------ show op registers ----------------------
-{
-//device_t dev;
-int i;
-//dev = pci_locate_device(PCI_ID(0x1039, 0x5513), 0); 
-printk_debug("NIC OP Registers \n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(readl(base+i));
-    print_debug("  ");    
-}
+	if(!(val=phy_detect(base,&PhyAddr)))
+	{
+	       printk_debug("PHY detect fail !!!!\r\n");
+		return;
+	}
 
-}
+        ulValue=readl(base + 0x38L);   //  check EEPROM existing
 
-//----------------------------------------------------
-#endif
+        if((ulValue & 0x0002))
+        {
 
-    ulValue=readl(base + 0x38L);   //  check EEPROM existing
-   
-    if((ulValue & 0x0002))
-    {       
-         
-     //	read MAC address from EEPROM at first
-	
+          //	read MAC address from EEPROM at first
+
           //	if that is valid we will use that
-			
+
 			printk_debug("EEPROM contents %x \n",ReadEEprom( dev,  base,  0LL));
 			for(i=0;i<3;i++) {
 				//status = smbus_read_byte(dev_eeprom, i);
 				ulValue=ReadEEprom( dev,  base,  i+3L);
-				if (ulValue ==0x10000) break;  // error 
-				
-				MacAddr[i] =ulValue & 0xFFFF;	
-				
+				if (ulValue ==0x10000) break;  // error
+
+				MacAddr[i] =ulValue & 0xFFFF;
+
 			}
-		 
-    }else{
-             // read MAC address from firmware
+        }else{
+                 // read MAC address from firmware
 		 printk_debug("EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
 		 MacAddr[0]=readw(0xffffffc0); // mac address store at here
 		 MacAddr[1]=readw(0xffffffc2);
 		 MacAddr[2]=readw(0xffffffc4);
-    }	
+        }
 
+        set_apc(dev);
 
-#if 0
-//	read MAC address from EEPROM at first
-printk_debug("MAC address in firmware trap \n");
- for( i=0;i<3;i++)
- 	printk_debug(" %4x\n",MacAddr[i]);
- printk_debug("\n");      
-#endif
+        readApcMacAddr();
 
-set_apc(dev);
- 	
-readApcMacAddr();
-
-#if 0
+#if DEBUG_NIC
 {
-//device_t dev;
-int i;
-//dev = pci_locate_device(PCI_ID(0x1039, 0x5513), 0); 
-printk_debug("NIC PCI config \n");
-for(i=0;i<0xFF;i+=4)
-{    if((i%16)==0)
-    {print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-    print_debug_hex32(pci_read_config32(dev,i));
-    print_debug("  ");    
-}
+        int i;
 
+        print_debug("****** NIC PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
+        }
+        print_debug("\r\n");
 }
+
+
 #endif
 
 }
 
-printk_debug("nic_init<--------\r\n");
+print_debug("NIC_INIT:<----------\n");
 return;
 
 #define RegStationMgtInf	0x44
@@ -429,161 +393,8 @@
 			}
 		}
 	}
-//	if that is invalid we will read that from romstrap
-	if(!eeprom_valid) {
-		unsigned long mac_pos;
-		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
-		mac_l = readl(mac_pos) + nic_index; // overflow?
-		mac_h = readl(mac_pos + 4);
 
-	}
-#if 1
-//	set that into NIC MMIO
-#define NvRegMacAddrA	0xA8
-#define NvRegMacAddrB	0xAC
-	writel(mac_l, base + NvRegMacAddrA);
-	writel(mac_h, base + NvRegMacAddrB);
-#else
-//	set that into NIC
-	pci_write_config32(dev, 0xa8, mac_l);
-	pci_write_config32(dev, 0xac, mac_h);
-#endif
-
-	nic_index++;
-
-#if CONFIG_PCI_ROM_RUN == 1
-	pci_dev_init(dev);// it will init option rom
-#endif
-
-}
-
-
-
-#else // orginal code
-
-tatic int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
-{
-	uint32_t dword;
-	unsigned loop = 0x100;
-	writel(0x8000, base+0x190); //Clear MDIO lock bit
-	mdelay(1);
-	dword = readl(base+0x190);
-	if(dword & (1<<15)) return -1;
-
-	writel(1, base+0x180);
-	writel((phy_addr<<5) | (phy_reg),base + 0x190);
-	do{
-		dword = readl(base + 0x190);
-		if(--loop==0) return -4;
-	} while ((dword & (1<<15)) );
-
-	dword = readl(base + 0x180);
-	if(dword & 1) return -3;
-
-	dword = readl(base + 0x194);
-
-	return dword;
-
-}
-
-static int phy_detect(uint8_t *base)
-{
-	uint32_t dword;
-	int i;
-	int val;
-	unsigned id;
-	dword = readl(base+0x188);
-	dword &= ~(1<<20);
-	writel(dword, base+0x188);
-
-	phy_read(base, 0, 1);
-
-	for(i=1; i<=32; i++) {
-		int phyaddr = i & 0x1f;
-		val = phy_read(base, phyaddr, 1);
-		if(val<0) continue;
-		if((val & 0xffff) == 0xfffff) continue;
-		if((val & 0xffff) == 0) continue;
-		if(!(val & 1)) {
-			break; // Ethernet PHY
-		}
-		val = phy_read(base, phyaddr, 3);
-		if (val < 0 || val == 0xffff) continue;
-		id = val & 0xfc00;
-		val = phy_read(base, phyaddr, 2);
-		if (val < 0 || val == 0xffff) continue;
-		id |= ((val & 0xffff)<<16);
-		printk_debug("SIS966 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
-//		if((id == 0xe0180000) || (id==0x0032cc00))
-			break;
-	}
-
-	if(i>32) {
-		printk_debug("SIS966 MAC PHY not found\n");
-	}
-
-}
-static void nic_init(struct device *dev)
-{
-	uint32_t dword, old;
-	uint32_t mac_h, mac_l;
-	int eeprom_valid = 0;
-	struct southbridge_sis_sis966_config *conf;
-
-	static uint32_t nic_index = 0;
-
-	uint8_t *base;
-	struct resource *res;
-	
-	res = find_resource(dev, 0x10);
-
-	if(!res) return;
-
-	base = res->base;
-
-	phy_detect(base);
-
-#define NvRegPhyInterface	0xC0
-#define PHY_RGMII	0x10000000
-
-	writel(PHY_RGMII, base + NvRegPhyInterface);
-
-	conf = dev->chip_info;
-
-	if(conf->mac_eeprom_smbus != 0) {
-//	read MAC address from EEPROM at first
-		struct device *dev_eeprom;
-		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
-
-		if(dev_eeprom) {
-		//	if that is valid we will use that
-			unsigned char dat[6];
-			int status;
-			int i;
-			for(i=0;i<6;i++) {
-				status = smbus_read_byte(dev_eeprom, i);
-				if(status < 0) break;
-				dat[i] = status & 0xff;
-			}
-			if(status >= 0) {
-				mac_l = 0;
-				for(i=3;i>=0;i--) {
-					mac_l <<= 8;
-					mac_l += dat[i];
-				}
-				if(mac_l != 0xffffffff) {
-					mac_l += nic_index;
-					mac_h = 0;
-					for(i=5;i>=4;i--) {
-						mac_h <<= 8;
-						mac_h += dat[i];
-					}
-					eeprom_valid = 1;
-				}
-			}
-		}
-	}
-//	if that is invalid we will read that from romstrap
+// if that is invalid we will read that from romstrap
 	if(!eeprom_valid) {
 		unsigned long mac_pos;
 		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
@@ -591,17 +402,12 @@
 		mac_h = readl(mac_pos + 4);
 
 	}
-#if 1
-//	set that into NIC MMIO
+
+// set that into NIC MMIO
 #define NvRegMacAddrA	0xA8
 #define NvRegMacAddrB	0xAC
 	writel(mac_l, base + NvRegMacAddrA);
 	writel(mac_h, base + NvRegMacAddrB);
-#else
-//	set that into NIC
-	pci_write_config32(dev, 0xa8, mac_l);
-	pci_write_config32(dev, 0xac, mac_h);
-#endif
 
 	nic_index++;
 
@@ -611,7 +417,6 @@
 
 }
 
-#endif
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,
@@ -636,8 +441,3 @@
 	.vendor	= PCI_VENDOR_ID_SIS,
 	.device	= PCI_DEVICE_ID_SIS_SIS966_NIC1,
 };
-static const struct pci_driver nic_bridge_driver __pci_driver = {
-	.ops	= &nic_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE,
-};

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -46,19 +46,14 @@
 	dword |= (1<<30); /* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
 
-#if 1
-	//only need (a01,xx]
 	word = pci_read_config16(dev, 0x48);
 	word |= (1<<0); /* MRL2MRM */
 	word |= (1<<2); /* MR2MRM */
 	pci_write_config16(dev, 0x48, word);
-#endif
 
-#if 1
 	dword = pci_read_config32(dev, 0x4c);
 	dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
 	pci_write_config32(dev, 0x4c, dword);
-#endif
 
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -32,65 +32,64 @@
 #include "sis966.h"
 #include <arch/io.h>
 
-#if 1
 uint8_t	SiS_SiS1183_init[68][3]={
-{0x04, 0x00, 0x05},					 
-{0x09, 0x00, 0x05},					 
-{0x2C, 0x00, 0x39},					 
-{0x2D, 0x00, 0x10},					  
-{0x2E, 0x00, 0x83},					 
-{0x2F, 0x00, 0x11},					 
-{0x90, 0x00, 0x40},					 
-{0x91, 0x00, 0x00},	// set mode				 
-{0x50, 0x00, 0xA2},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0x00, 0x96},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0xF7, 0x00},					 
-{0x56, 0x00, 0xC0},	
+{0x04, 0x00, 0x05},
+{0x09, 0x00, 0x05},
+{0x2C, 0x00, 0x39},
+{0x2D, 0x00, 0x10},
+{0x2E, 0x00, 0x83},
+{0x2F, 0x00, 0x11},
+{0x90, 0x00, 0x40},
+{0x91, 0x00, 0x00},	// set mode
+{0x50, 0x00, 0xA2},
+{0x52, 0x00, 0xA2},
+{0x55, 0x00, 0x96},
+{0x52, 0x00, 0xA2},
+{0x55, 0xF7, 0x00},
+{0x56, 0x00, 0xC0},
 {0x57, 0x00, 0x14},
-{0x67, 0x00, 0x28},					 
-{0x81, 0x00, 0xB3},					 
-{0x82, 0x00, 0x72},					 
-{0x83, 0x00, 0x40},					 
-{0x85, 0x00, 0xB3},					 
-{0x86, 0x00, 0x72},					 
+{0x67, 0x00, 0x28},
+{0x81, 0x00, 0xB3},
+{0x82, 0x00, 0x72},
+{0x83, 0x00, 0x40},
+{0x85, 0x00, 0xB3},
+{0x86, 0x00, 0x72},
 {0x87, 0x00, 0x40},
-{0x88, 0x00, 0xDE},      // after set mode					 
-{0x89, 0x00, 0xB3},					 
-{0x8A, 0x00, 0x72},					 
-{0x8B, 0x00, 0x40},					 
-{0x8C, 0x00, 0xDE},					 
-{0x8D, 0x00, 0xB3},					 
-{0x8E, 0x00, 0x92},					 
-{0x8F, 0x00, 0x40},					 
-{0x93, 0x00, 0x00},					 
-{0x94, 0x00, 0x80},					 
-{0x95, 0x00, 0x08},					 
-{0x96, 0x00, 0x80},					 
+{0x88, 0x00, 0xDE},      // after set mode
+{0x89, 0x00, 0xB3},
+{0x8A, 0x00, 0x72},
+{0x8B, 0x00, 0x40},
+{0x8C, 0x00, 0xDE},
+{0x8D, 0x00, 0xB3},
+{0x8E, 0x00, 0x92},
+{0x8F, 0x00, 0x40},
+{0x93, 0x00, 0x00},
+{0x94, 0x00, 0x80},
+{0x95, 0x00, 0x08},
+{0x96, 0x00, 0x80},
 {0x97, 0x00, 0x08},
-{0x9C, 0x00, 0x80},					 
-{0x9D, 0x00, 0x08},					 
-{0x9E, 0x00, 0x80},					 
-{0x9F, 0x00, 0x08},					 
-{0xA0, 0x00, 0x15},					 
-{0xA1, 0x00, 0x15},					 
-{0xA2, 0x00, 0x15},					 
+{0x9C, 0x00, 0x80},
+{0x9D, 0x00, 0x08},
+{0x9E, 0x00, 0x80},
+{0x9F, 0x00, 0x08},
+{0xA0, 0x00, 0x15},
+{0xA1, 0x00, 0x15},
+{0xA2, 0x00, 0x15},
 {0xA3, 0x00, 0x15},
 
 
-{0xD8, 0xFE, 0x01},	// Com reset				 
+{0xD8, 0xFE, 0x01},	// Com reset
 {0xC8, 0xFE, 0x01},
 {0xE8, 0xFE, 0x01},
 {0xF8, 0xFE, 0x01},
 
-{0xD8, 0xFE, 0x00},	// Com reset				 
+{0xD8, 0xFE, 0x00},	// Com reset
 {0xC8, 0xFE, 0x00},
 {0xE8, 0xFE, 0x00},
 {0xF8, 0xFE, 0x00},
 
 
-{0xC4, 0xFF, 0xFF},    // Clear status					 
+{0xC4, 0xFF, 0xFF},    // Clear status
 {0xC5, 0xFF, 0xFF},
 {0xC6, 0xFF, 0xFF},
 {0xC7, 0xFF, 0xFF},
@@ -98,7 +97,7 @@
 {0xD5, 0xFF, 0xFF},
 {0xD6, 0xFF, 0xFF},
 {0xD7, 0xFF, 0xFF},
-{0xE4, 0xFF, 0xFF},    // Clear status					 
+{0xE4, 0xFF, 0xFF},    // Clear status
 {0xE5, 0xFF, 0xFF},
 {0xE6, 0xFF, 0xFF},
 {0xE7, 0xFF, 0xFF},
@@ -110,127 +109,34 @@
 {0x00, 0x00, 0x00}					//End of table
 };
 
-
-#else 
-uint8_t	SiS_SiS1183_init[5][3]={
-
-{0xD8, 0xFE, 0x01},	// Com reset				 
-{0xC8, 0xFE, 0x01},
-{0xE8, 0xFE, 0x01},
-{0xF8, 0xFE, 0x01},
-
-{0x00, 0x00, 0x00}
-};					//End of table
-
-uint8_t	SiS_SiS1183_init2[21][3]={
-{0xD8, 0xFE, 0x00},			 
-{0xC8, 0xFE, 0x00},
-{0xE8, 0xFE, 0x00},
-{0xF8, 0xFE, 0x00},
-
-
-{0xC4, 0xFF, 0xFF},    // Clear status					 
-{0xC5, 0xFF, 0xFF},
-{0xC6, 0xFF, 0xFF},
-{0xC7, 0xFF, 0xFF},
-{0xD4, 0xFF, 0xFF},
-{0xD5, 0xFF, 0xFF},
-{0xD6, 0xFF, 0xFF},
-{0xD7, 0xFF, 0xFF},
-{0xE4, 0xFF, 0xFF},    // Clear status					 
-{0xE5, 0xFF, 0xFF},
-{0xE6, 0xFF, 0xFF},
-{0xE7, 0xFF, 0xFF},
-{0xF4, 0xFF, 0xFF},
-{0xF5, 0xFF, 0xFF},
-{0xF6, 0xFF, 0xFF},
-{0xF7, 0xFF, 0xFF},
-
-
-{0x00, 0x00, 0x00}					//End of table
-};
-#endif
-
-
-
 static void sata_init(struct device *dev)
 {
-	uint32_t dword;       
+	uint32_t dword;
 	struct southbridge_sis_sis966_config *conf;
 
-	
+
 struct resource *res;
 uint16_t base;
 uint8_t temp8;
-	
+
 	conf = dev->chip_info;
-printk_debug("SATA(SiS1183)_init-------->\r\n");
+        print_debug("SATA_INIT:---------->\n");
 
-#if 1
-//-------------- enable IDE (SiS5513) -------------------------
-{    
-       uint8_t  temp8;
-       int i=0;
+//-------------- enable IDE (SiS1183) -------------------------
+{
+        uint8_t  temp8;
+        int i=0;
 	while(SiS_SiS1183_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
-					temp8 &= SiS_SiS1183_init[i][1];
-					temp8 |= SiS_SiS1183_init[i][2];				
-					pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
-					i++;
+	{
+                temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
+                temp8 &= SiS_SiS1183_init[i][1];
+                temp8 |= SiS_SiS1183_init[i][2];
+                pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
+                i++;
 	};
 }
-/*
-mdelay(5);
-{    
-       uint8_t  temp8;
-       int i=0;
-	while(SiS_SiS1183_init2[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS1183_init2[i][0]);
-					temp8 &= SiS_SiS1183_init2[i][1];
-					temp8 |= SiS_SiS1183_init2[i][2];				
-					pci_write_config8(dev, SiS_SiS1183_init2[i][0], temp8);
-					i++;
-	};
-}
-*/
 //-----------------------------------------------------------
-#endif
 
-
-#if 0
-
-	dword = pci_read_config32(dev, 0x50);
-	/* Ensure prefetch is disabled */
-	dword &= ~((1 << 15) | (1 << 13));
-	if(conf) {
-		if (conf->sata1_enable) {
-			/* Enable secondary SATA interface */
-			dword |= (1<<0);
-			printk_debug("SATA S \t");
-		}
-		if (conf->sata0_enable) {
-			/* Enable primary SATA interface */
-			dword |= (1<<1);
-			printk_debug("SATA P \n");
-		}
-	} else {
-		dword |= (1<<1) | (1<<0);
-		printk_debug("SATA P and S \n");
-	}
-
-
-#if 1
-	dword &= ~(0x1f<<24);
-	dword |= (0x15<<24);
-#endif
-	pci_write_config32(dev, 0x50, dword);
-
-	dword = pci_read_config32(dev, 0xf8);
-	dword |= 2;
-	pci_write_config32(dev, 0xf8, dword);
-
-#endif
-
 {
 uint32_t i,j;
 uint32_t temp32;
@@ -239,34 +145,34 @@
    temp32=0;
    temp32= pci_read_config32(dev, 0xC0);
    for ( j=0;j<0xFFFF;j++);
-   printk_debug("status= %x",temp32);
+   printk_debug("status= %x\n",temp32);
    if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
 }
-printk_debug("\n");
+
 }
 
-#if 0	
+#if DEBUG_SATA
+{
+        int i;
 
-res = find_resource(dev, 0x10);	
-base =(uint16_t ) res->base;
-printk_debug("BASE ADDR %x\n",base);
-base&=0xFFFE;
-printk_debug("SATA status %x\n",inb(base+7));
+        print_debug("****** SATA PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
 
-{
-int i;
-for(i=0;i<0xFF;i+=4)
-{
-    if((i%16)==0)
-    {
-      print_debug("\r\n");print_debug_hex8(i);print_debug("  ");}
-      print_debug_hex32(pci_read_config32(dev,i));
-      print_debug("  ");
-    }
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
+        }
+        print_debug("\r\n");
 }
 #endif
-printk_debug("sata_init <--------\r\n");
 
+        print_debug("SATA_INIT:<----------\n");
+
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -293,9 +199,3 @@
 	.vendor	= PCI_VENDOR_ID_SIS,
 	.device	= PCI_DEVICE_ID_SIS_SIS966_SATA0,
 };
-
-static const struct pci_driver sata1_driver __pci_driver = {
-	.ops	= &sata_ops,
-	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_SATA1,
-};

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.h	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.h	2007-11-02 16:09:58 UTC (rev 2931)
@@ -158,14 +158,14 @@
 	}
 };
 
-	global_status_register = inb(smbus_io_base + 0x00); 
+	global_status_register = inb(smbus_io_base + 0x00);
 	byte = inb(smbus_io_base + 0x08);
 
 	if (global_status_register != 0x08) { // lose check, otherwise it should be 0
 		print_debug("Fail");print_debug("\r\t");
 			return -1;
 	}
-		print_debug("Success");print_debug("\r\t");	
+		print_debug("Success");print_debug("\r\t");
 	return byte;
 }
 

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -30,37 +30,38 @@
 #include <device/pci_ops.h>
 #include "sis966.h"
 
-// From Y.S.
-// PCI R47h-R44h=0001AD54h
-// PCI R4Bh-R48h=00000271h
-uint8_t	SiS_SiS7001_init[15][3]={
-{0x04, 0xFF, 0x07},
+uint8_t	SiS_SiS7001_init[16][3]={
+{0x04, 0x00, 0x07},
+{0x0C, 0x00, 0x08},
+{0x0D, 0x00, 0x20},
+
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
 {0x2E, 0xFF, 0x01},
 {0x2F, 0xFF, 0x70},
+
 {0x44, 0x00, 0x54},
 {0x45, 0x00, 0xAD},
 {0x46, 0x00, 0x01},
 {0x47, 0x00, 0x00},
-{0x48, 0x00, 0x71},
+
+{0x48, 0x00, 0x73},
 {0x49, 0x00, 0x02},
 {0x4A, 0x00, 0x00},
 {0x4B, 0x00, 0x00},
-{0x04, 0x00, 0x07},
+
 {0x00, 0x00, 0x00}					//End of table
 };
 
 static void usb_init(struct device *dev)
 {
+        print_debug("USB 1.1 INIT:---------->\n");
 
 //-------------- enable USB1.1 (SiS7001) -------------------------
 {
         uint8_t  temp8;
         int i=0;
 
-        printk_debug("USB1.1_Init\n");
-
 	 while(SiS_SiS7001_init[i][0] != 0)
 	 {				temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
 					temp8 &= SiS_SiS7001_init[i][1];
@@ -71,23 +72,28 @@
 }
 //-----------------------------------------------------------
 
-#if 0
+#if DEBUG_USB
 {
-    int i;
-    printk_debug("\nUSB 1.1 PCI config");
-    for(i=0;i<0xFF;i+=4)
-    {    
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug(": ");}
-            print_debug_hex32(pci_read_config32(dev,i));
-            print_debug("  ");
+        int i;
+
+        print_debug("****** USB 1.1 PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
         }
         print_debug("\r\n");
-    }
+}
 #endif
+        print_debug("USB 1.1 INIT:<----------\n");
+}
 
-}
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x40,

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c	2007-11-02 16:09:58 UTC (rev 2931)
@@ -36,11 +36,9 @@
 
 extern struct ehci_debug_info dbg_info;
 
-// From Y.S.
-// PCI R43h-R40h=00000020h
-// PCI R4Bh-R48h=00078010h
-uint8_t	SiS_SiS7002_init[19][3]={
+uint8_t	SiS_SiS7002_init[22][3]={
 {0x04, 0x00, 0x06},
+{0x0D, 0x00, 0x00},
 
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
@@ -52,12 +50,15 @@
 {0x76, 0x00, 0x00},
 {0x77, 0x00, 0x00},
 
+{0x7A, 0x00, 0x00},
+{0x7B, 0x00, 0x00},
+
 {0x40, 0x00, 0x20},
 {0x41, 0x00, 0x00},
 {0x42, 0x00, 0x00},
 {0x43, 0x00, 0x08},
 
-{0x44, 0x00, 0x64},
+{0x44, 0x00, 0x04},
 
 {0x48, 0x00, 0x10},
 {0x49, 0x00, 0x80},
@@ -67,56 +68,58 @@
 {0x00, 0x00, 0x00}					//End of table
 };
 
-
-
 static void usb2_init(struct device *dev)
 {
-       uint8_t *base;
-	struct resource *res;
-	uint32_t temp32;
+        uint8_t *base;
+        struct resource *res;
+        uint32_t temp32;
 
+        print_debug("USB 2.0 INIT:---------->\n");
 
 //-------------- enable USB2.0 (SiS7002) -------------------------
 {
         uint8_t  temp8;
         int i=0;
 
-        printk_debug("USB2.0_Init\n");
-
-	while(SiS_SiS7002_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
-					temp8 &= SiS_SiS7002_init[i][1];
-					temp8 |= SiS_SiS7002_init[i][2];
-					pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
-					i++;
-	};
+        while(SiS_SiS7002_init[i][0] != 0)
+        {
+                temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
+                temp8 &= SiS_SiS7002_init[i][1];
+                temp8 |= SiS_SiS7002_init[i][2];
+                pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
+                i++;
+        };
 }
 
-       res = find_resource(dev, 0x10);
-	if(!res)
-		return;
+        res = find_resource(dev, 0x10);
+        if(!res)
+                return;
 
-	base =(uint8_t *) res->base;
-	printk_debug("base = %08x\n", base);
-       writel(0x2,base+0x20);
+        base =(uint8_t *) res->base;
+        printk_debug("base = %08x\n", base);
+        writel(0x2,base+0x20);
 //-----------------------------------------------------------
 
-#if 0
+#if DEBUG_USB2
 {
-    int i;
-    printk_debug("\nUSB 2.0 PCI config");
-    for(i=0;i<0xFF;i+=4)
-    {
-        if((i%16)==0)
-        {
-            print_debug("\r\n");print_debug_hex8(i);print_debug(": ");}
-            print_debug_hex32(pci_read_config32(dev,i));
-            print_debug("  ");
+        int i;
+
+        print_debug("****** USB 2.0 PCI config ******");
+        print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+        for(i=0;i<0xff;i+=4){
+                if((i%16)==0){
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                print_debug_hex32(pci_read_config32(dev,i));
+                print_debug("  ");
         }
         print_debug("\r\n");
-    }
+}
 #endif
-
+        print_debug("USB 2.0 INIT:<----------\n");
 }
 
 static void usb2_set_resources(struct device *dev)
@@ -164,5 +167,5 @@
 static const struct pci_driver usb2_driver __pci_driver = {
 	.ops	= &usb2_ops,
 	.vendor	= PCI_VENDOR_ID_SIS,
-	.device	= PCI_DEVICE_ID_SIS_SIS966_EHCI,
+	.device	= PCI_DEVICE_ID_SIS_SIS966_USB2,
 };

Modified: trunk/LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/Config.lb	2007-11-02 12:54:49 UTC (rev 2930)
+++ trunk/LinuxBIOSv2/targets/gigabyte/ga_2761gxdk/Config.lb	2007-11-02 16:09:58 UTC (rev 2931)
@@ -3,6 +3,8 @@
 ##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
+## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
+## Written by Morgan Tsai <my_tsai at sis.com> for SiS.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -23,38 +25,22 @@
 mainboard gigabyte/ga_2761gxdk
 
 romimage "normal"
-#       48K for VGA BIOS
-         option ROM_SIZE = 475136
-#       48K for SCSI FW and 48K for ATI ROM
-#        option ROM_SIZE = 425984 
-#       64K for Etherboot
-#        option ROM_SIZE = 458752 
-#       44k for atixx.rom
-#        option ROM_SIZE = 479232
-#       32k for vbios
-#        option ROM_SIZE = 491520
+#       32K for VGA BIOS
+        option ROM_SIZE = (512*1024 - 32*1024)
 
         option USE_FAILOVER_IMAGE=0
-#	option ROM_IMAGE_SIZE=0x13800
-#	option ROM_IMAGE_SIZE=0x18800
-#	option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x20000
-#	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x40000
-	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+        option ROM_IMAGE_SIZE=0x20000
+        option XIP_ROM_SIZE=0x40000
+        option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
         payload ../../../../payloads/filo_uda1.elf
 end
 
-romimage "fallback" 
+romimage "fallback"
         option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=1
-#	option ROM_IMAGE_SIZE=0x13800
-#	option ROM_IMAGE_SIZE=0x18800
-#       option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x20000
-#	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x40000
-	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+        option USE_FALLBACK_IMAGE=1
+        option ROM_IMAGE_SIZE=0x20000
+        option XIP_ROM_SIZE=0x40000
+        option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
         payload ../../../../payloads/filo_uda1.elf
 end
 
@@ -66,5 +52,5 @@
         option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#       buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+        buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"




From svn at openbios.org  Fri Nov  2 17:18:25 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 17:18:25 +0100
Subject: [LinuxBIOS] r2932 - trunk/LinuxBIOSv2/src/southbridge/sis/sis966
Message-ID: <mailman.826.1355071195.16123.coreboot@coreboot.org>

Author: jcrouse
Date: 2007-11-02 17:18:25 +0100 (Fri, 02 Nov 2007)
New Revision: 2932

Removed:
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c
Log:
Delete a file no longer used by the SiS implementation
No functional code changes.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Deleted: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c	2007-11-02 16:09:58 UTC (rev 2931)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c	2007-11-02 16:18:25 UTC (rev 2932)
@@ -1,192 +0,0 @@
-/*
- * This file is part of the LinuxBIOS project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
- * Turn off machine check triggers when reading
- * pci space where there are no devices.
- * This is necessary when scaning the bus for
- * devices which is done by the kernel
- *
- * written in 2003 by Eric Biederman
- * 
- *  - Athlon64 workarounds by Stefan Reinauer
- *  - "reset once" logic by Yinghai Lu
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
- *
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <part/hard_reset.h>
-#include <pc80/mc146818rtc.h>
-#include <bitops.h>
-#include <cpu/amd/model_fxx_rev.h>
-
-//#include "amdk8.h"
-
-#include <arch/io.h>
-
-/**
- * @brief Read resources for AGP aperture
- *
- * @param 
- *
- * There is only one AGP aperture resource needed. The resoruce is added to
- * the northbridge of BSP.
- *
- * The same trick can be used to augment legacy VGA resources which can
- * be detect by generic pci reousrce allocator for VGA devices.
- * BAD: it is more tricky than I think, the resource allocation code is
- * implemented in a way to NOT DOING legacy VGA resource allcation on
- * purpose :-(.
- */
-
-
-typedef struct msr_struct 
-{
-	unsigned lo;
-	unsigned hi;
-} msr_t;
-
-static inline msr_t rdmsr(unsigned index)
-{
-	msr_t result;
-	result.lo = 0;
-	result.hi = 0;
-	return result;
-}
-
-
-
-static void sisnb_read_resources(device_t dev)
-{
-	struct resource *resource;
-	unsigned char iommu;
-	/* Read the generic PCI resources */
-	printk_debug("sisnb_read_resources\n");
-	pci_dev_read_resources(dev);
-
-	/* If we are not the first processor don't allocate the gart apeture */
-	if (dev->path.u.pci.devfn != PCI_DEVFN(0x0, 0)) {
-		return;
-	}
-
-
-	return;
-
-	iommu = 1;
-	get_option(&iommu, "iommu");
-
-	if (iommu) {
-		/* Add a Gart apeture resource */
-		resource = new_resource(dev, 0x94);
-		resource->size = iommu?AGP_APERTURE_SIZE:1;
-		resource->align = log2(resource->size);
-		resource->gran  = log2(resource->size);
-		resource->limit = 0xffffffff; /* 4G */
-		resource->flags = IORESOURCE_MEM;
-	}
-}
-
-static void set_agp_aperture(device_t dev)
-{
-	struct resource *resource;
-
-	return;	
-	
-	resource = probe_resource(dev, 0x94);
-	if (resource) {
-		device_t pdev;
-		uint32_t gart_base, gart_acr;
-
-		/* Remember this resource has been stored */
-		resource->flags |= IORESOURCE_STORED;
-
-		/* Find the size of the GART aperture */
-		gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
-
-		/* Get the base address */
-		gart_base = ((resource->base) >> 25) & 0x00007fff;
-		
-		/* Update the other northbriges */
-		pdev = 0;
-		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
-			/* Store the GART size but don't enable it */
-			pci_write_config32(pdev, 0x90, gart_acr);
-
-			/* Store the GART base address */
-			pci_write_config32(pdev, 0x94, gart_base);
-
-			/* Don't set the GART Table base address */
-			pci_write_config32(pdev, 0x98, 0);
-			
-			/* Report the resource has been stored... */
-			report_resource_stored(pdev, resource, " <gart>");
-		}
-	}
-}
-
-static void sisnb_set_resources(device_t dev)
-{
-printk_debug("sisnb_set_resources ------->\n");
-	/* Set the gart apeture */
-//	set_agp_aperture(dev);
-
-	/* Set the generic PCI resources */
-	pci_dev_set_resources(dev);
-	printk_debug("sisnb_set_resources <-------\n");	
-}
-
-static void sisnb_init(struct device *dev)
-{
-	uint32_t cmd, cmd_ref;
-	int needs_reset;
-	struct device *f0_dev, *f2_dev;
-	msr_t	msr;
-	
-	
-	needs_reset = 0;
-	printk_debug("sisnb_init: ---------->\n");	
-
-	//dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS756), 0);		
-	msr = rdmsr(0xC001001A);	
-	pci_write_config16(dev, 0x8E, msr.lo >> 16);				// Topbound	
-	pci_write_config8(dev, 0x7F, 0x08);			// ACPI Base	
-	outb(inb(0x856) | 0x40, 0x856);	 // Auto-Reset Function
-		
-	printk_debug("sisnb_init: <----------\n");
-	printk_debug("done.\n");
-}
-
-
-static struct device_operations sisnb_ops  = {
-	.read_resources   = sisnb_read_resources,
-	.set_resources    = sisnb_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = sisnb_init,
-	.scan_bus         = 0,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver sisnb_driver __pci_driver = {
-	.ops    = &sisnb_ops,
-	.vendor = PCI_VENDOR_ID_SIS,
-	.device = PCI_DEVICE_ID_SIS_SIS761,
-};




From corey.osgood at gmail.com  Fri Nov  2 17:39:16 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 02 Nov 2007 12:39:16 -0400
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <20071102155603.GA25764@greenwood>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood>
Message-ID: <472B52B4.9050801@gmail.com>

Uwe Hermann wrote:
> On Fri, Nov 02, 2007 at 02:03:18AM -0400, Corey Osgood wrote:
>   
>> @@ -79,11 +62,14 @@
>>  
>>  	loops = 0;
>>  	/* Yes, this is a mess, but it's the easiest way to do it. */
>> -	while ((inb(SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT)
>> +	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
>>     
>
> Rationale? Does it make a big difference?
>   

No, not really. Just that now the loop runs SMBUS_TIMEOUT times, instead
if SMBUS_TIMEOUT + 1.

>> -u8 smbus_read_byte(u32 dimm, u32 offset)
>> +/**
>> + * Read a byte from the smbus
>> + *
>> + * @param dimm The address location of the dimm on the smbus
>> + * @param offset The offset the data is located at
>> + */
>>     
>
>   
>> +u8 smbus_read_byte(u8 dimm, u8 offset)
>>     
>
> I'm still not entirely sure they're always only 8 bit. Do you have a
> pointer to a datasheet or spec or standard where it's explicitly
> defined as 8 bit? Yes, it _is_ 8 bits in most cases, but can we be sure
> that it'll be 8 bit in _all_ of them? On all chipsets and controllers?
>   

The offset will always be 8 bit, since there are 256 offsets (and >half
of them we'll never touch anyways). The address also has to be 8 bit,
since it's programmed into an 8 bit register (per vt8237r datasheet, p125).

>> -	/* Can I just "return inb(SMBHSTDAT0)"? */
>> +	/* We could probably return inb(SMBHSTDAT0), but we'd lose the ability
>> +	 * to debug the transaction */
>>     
>
> OK, if that's the only issue, just drop the comment.
>
>
>   
>> +/**
>> + * This is provided for compatibility, should it be needed
>> + */
>> +inline u8 spd_read_byte(u32 address, u8 offset)
>> +{
>> +	return smbus_read_byte(address, offset);
>> +}
>>     
>
> Hm, this is usually done in auto.c per-mainboard, I think. Either
> you make spd_read_byte() a wrapper for smbus_read_byte(), or you
> use the "fake spd" method to return hard-coded settings if there's
> no real SPD data to be read.
>
> Not sure this function makes sense in vt8237r_early_smbus.c, because of
> the above and also because it's not SMBus-related per se. I'd say drop it.
>   

ok

> Also, address is 32bit here but 8bit in smbus_read_byte()?
>   

oops!

>> +/**
>> + * A fixup for some systems that need time for the smbus to "warm up"
>> + * It reads the ID byte from SMBus, looking for good data from a slot/address
>> + * Exits on either good data or a timeout
>>     
>
> Yep, but please extend the comment a bit to contain more information,
> rationale, example use case where this issue came up, how the problem
> shows, how it's fixed etc. The comment is good, but a bit too short
> for describing this non-trivial issue at hand.
>   

ok

>> + *
>> + * @param mem_controller The memory controller and smbus addresses
>> + */
>> +void smbus_fixup(const struct mem_controller *ctrl)
>> +{
>> +	int i, ram_slots, current_slot = 0;
>> +	u8 result = 0;
>> +
>> +#ifdef DIMM_SOCKETS
>> +	ram_slots = DIMM_SOCKETS;
>> +#else
>> +	ram_slots = sizeof(ctrl->channel0)/sizeof(ctrl->channel0[0]);
>> +#endif
>>     
>
> Can you explain? Shouldn't DIMM_SOCKETS always match
> sizeof(ctrl->channel0)/sizeof(ctrl->channel0[0])? When does it happen
> that they do not match (and why?).
>   

Unless someone doesn't define DIMM_SOCKETS, or uses some other name. I
suppose that could be just dropped in favor of ARRAY_SIZE().

> Also, we now have ARRAY_SIZE(), please use it here.
>
>
>   
>> +	if (!ram_slots) {
>> +		print_err("smbus_fixup thinks there are no ram slots!\r\n");
>> +		return;
>> +	}
>> +	
>> +	PRINT_DEBUG("Waiting for smbus to warm up");
>> +		
>> +	/* Bad SPD data should be either 0 or 0xff, so really the values we look
>> +	 * for are arbitrary, as long as they're between 1 and 0xfe */
>> +	for(i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || 
>> +			(result > SPD_MEMORY_TYPE_SDRAM_DDR2))); i++)
>>     
>
> Please explain the SPD_MEMORY_TYPE_SDRAM/SPD_MEMORY_TYPE_SDRAM_DDR2
> check in the comment here.
>
> If all you want is to know whether some sensible RAM type is
> returned wouldn't "> 0" and "< 0xff" be enough (as per your comment)?
> You don't really care about the exact type, you only want to know _if_ there's
> a DIMM here, correct?
>   

Safety's sake. If the smbus happens to spurt out some odd value (I've
seen 0x30 once) while this is going on, we want to be sure it's really
valid data. Originally it only sought DDR2, but that's bad since this
southbridge can be used on DDR systems as well. Looking further though,
it's only DDR/DDR2, so the SDRAM bit could be dropped.

> If I read this correctly you're checking whether you get one of these?
>
> #define SPD_MEMORY_TYPE_SDRAM            4
> #define SPD_MEMORY_TYPE_MULTIPLEXED_ROM  5
> #define SPD_MEMORY_TYPE_SGRAM_DDR        6
> #define SPD_MEMORY_TYPE_SDRAM_DDR        7
> #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
>
> If we make this "> 0" and "< 0xff" ("< 10" or so should be enough, too)
> then this function might be usable on non-vt8237r chipsets and can go
> in some global SMBus file to be used by others?
>   

Perhaps. vt8231/8235 could use something similar, they just use a big
delay as of right now.

>> +	{
>> +		if (current_slot > ram_slots) j = 0;
>> +		result = spd_read_byte(ctrl->channel0[current_slot], 
>> +							SPD_MEMORY_TYPE);
>> +		current_slot++;
>> +		PRINT_DEBUG(".");
>> +	}
>> +	if (i >= SMBUS_TIMEOUT)	print_err("SMBus timed out while warming up\r\n");
>> +	else PRINT_DEBUG("Done\r\n");	
>> +}
>>     
>
>
> Looks good otherwise. Does this contain all of the changes required to
> make it work on your board _and_ Rudolf's board?
>   

These are only required for my board, Rudolf's works fine without it. I
don't think it will break Rudolf's.

>
> Thanks, Uwe.
>   
Updated patch soon :)

-Corey



From stepan at coresystems.de  Fri Nov  2 17:44:03 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Nov 2007 17:44:03 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <20071102155603.GA25764@greenwood>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood>
Message-ID: <20071102164403.GA22159@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [071102 16:56]:
> >  	loops = 0;
> >  	/* Yes, this is a mess, but it's the easiest way to do it. */
> > -	while ((inb(SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT)
> > +	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
> 
> Rationale? Does it make a big difference?

Yes, the one is correct, the other is not because it counts
SMBUS_TIMEOUT+1 loops. 

> > -u8 smbus_read_byte(u32 dimm, u32 offset)
> > +/**
> > + * Read a byte from the smbus
> > + *
> > + * @param dimm The address location of the dimm on the smbus
> > + * @param offset The offset the data is located at
> > + */
> 
> > +u8 smbus_read_byte(u8 dimm, u8 offset)
> 
> I'm still not entirely sure they're always only 8 bit. Do you have a
> pointer to a datasheet or spec or standard where it's explicitly
> defined as 8 bit? Yes, it _is_ 8 bits in most cases, but can we be sure
> that it'll be 8 bit in _all_ of them? On all chipsets and controllers?

smbus address space is 8 bits. Let's reflect this in the code. We can
think about this when we find the first machine where it is not.

> > +inline u8 spd_read_byte(u32 address, u8 offset)
> > +{
> > +	return smbus_read_byte(address, offset);
> > +}
> 
> Hm, this is usually done in auto.c per-mainboard, I think. Either
> you make spd_read_byte() a wrapper for smbus_read_byte(), or you
> use the "fake spd" method to return hard-coded settings if there's
> no real SPD data to be read.
 
Yes, this is a mainboard specific abstraction. It might have to
circumvent smbus switches on the bus.

> Not sure this function makes sense in vt8237r_early_smbus.c, because of
> the above and also because it's not SMBus-related per se. I'd say drop it.
> 
> Also, address is 32bit here but 8bit in smbus_read_byte()?

That's fine. The i2c has 8 (actually 7) bits address space. spd might
not necessarily be behind the i2c bus. Or it might have a number of
switches. So you might have an address of 0xaabbccdd saying that aa, bb,
cc, dd are the settings of 3 i2c switches, while dd is the actual
address of the spd on the bus _after_ doing the other settings. This is
done on the ag?mi aruma in a similar way.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Fri Nov  2 17:45:30 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Nov 2007 17:45:30 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472B52B4.9050801@gmail.com>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
Message-ID: <20071102164530.GB22159@coresystems.de>

* Corey Osgood <corey.osgood at gmail.com> [071102 17:39]:
> >> +/**
> >> + * This is provided for compatibility, should it be needed
> >> + */
> >> +inline u8 spd_read_byte(u32 address, u8 offset)
> >> +{
> >> +	return smbus_read_byte(address, offset);
> >> +}
>     
> > Also, address is 32bit here but 8bit in smbus_read_byte()?
> >   
> 
> oops!
 
That's the whole point behind the abstraction. 

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Fri Nov  2 17:50:34 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Nov 2007 17:50:34 +0100
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <20071101200216.GL21220@cosmic.amd.com>
References: <20071004025851.GA32267@greenwood>
	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
Message-ID: <20071102165034.GA22854@coresystems.de>

* Jordan Crouse <jordan.crouse at amd.com> [071101 21:02]:
> Something strange happened to the patch, I think the mailserver
> may have mangled it;  it didn't apply cleanly to the tree.  I fixed it up,
> here is the same patch again that will apply against current SVN,
> and compiles on my box.
> 
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>
> Jordan

everything except the early_smbus changes is checked in. I broke that
portion yesterday while fixing compilation of the port. 

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From uwe at hermann-uwe.de  Fri Nov  2 17:52:23 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Nov 2007 17:52:23 +0100
Subject: [LinuxBIOS] mptable util not working?
In-Reply-To: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>
References: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>
Message-ID: <20071102165223.GB25764@greenwood>

On Thu, Nov 01, 2007 at 09:30:11AM -0400, joe at smittys.pointclark.net wrote:
> Hello,
> I am having prolems with the mptable utility. I keeps telling me "MP  
> FPS NOT found, suggest trying -grope option!!!". If I try the grope  
> option it still spits out the same message. Am I doing something wrong?

Probably not, could be that your system doesn't _have_ an mptable.
Not all systems do. Which board are we talking about here? Is it multi-CPU?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Nov  2 17:53:34 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Nov 2007 17:53:34 +0100
Subject: [LinuxBIOS] r2921
	-	trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
In-Reply-To: <20071031022657.GA7871@localdomain>
References: <E1In1nX-0007td-TB@mi002.mc1.hosteurope.de>
	<20071031011224.GR19408@greenwood>
	<20071031022657.GA7871@localdomain>
Message-ID: <20071102165334.GC25764@greenwood>

On Tue, Oct 30, 2007 at 10:26:57PM -0400, Ward Vandewege wrote:
> > Can somebody please update the wiki status page?
> 
> Done.

Are you sure? I don't see any changes. Maybe you forgot to press "Submit"?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From joe at smittys.pointclark.net  Fri Nov  2 17:57:05 2007
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Fri, 02 Nov 2007 12:57:05 -0400
Subject: [LinuxBIOS] mptable util not working?
In-Reply-To: <20071102165223.GB25764@greenwood>
References: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>
	<20071102165223.GB25764@greenwood>
Message-ID: <20071102125705.12gtctx6ows84sgk@www.smittys.pointclark.net>

Quoting Uwe Hermann <uwe at hermann-uwe.de>:

> On Thu, Nov 01, 2007 at 09:30:11AM -0400, joe at smittys.pointclark.net wrote:
>> Hello,
>> I am having prolems with the mptable utility. I keeps telling me "MP
>> FPS NOT found, suggest trying -grope option!!!". If I try the grope
>> option it still spits out the same message. Am I doing something wrong?
>
> Probably not, could be that your system doesn't _have_ an mptable.
> Not all systems do. Which board are we talking about here? Is it multi-CPU?
>
>
> Uwe.

No single Processor, that's probibly why. It seems to contain alot of  
IO data though. I think this is my problem, CPU to IO doesn't seem to  
be communicating, and I thought the mptable might help. I'm  
stumped.... But Corey maybe able to help me figure this out very soon.

Thanks - Joe



From svn at openbios.org  Fri Nov  2 18:05:04 2007
From: svn at openbios.org (svn at openbios.org)
Date: Fri,  2 Nov 2007 18:05:04 +0100
Subject: [LinuxBIOS] r2933 - trunk/LinuxBIOSv2/src/southbridge/sis/sis966
Message-ID: <mailman.827.1355071195.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-02 18:05:04 +0100 (Fri, 02 Nov 2007)
New Revision: 2933

Modified:
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
Log:
remaining part of the patch.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-02 16:18:25 UTC (rev 2932)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-02 17:05:04 UTC (rev 2933)
@@ -134,7 +134,7 @@
 };
 
 
-#if 1
+
 static const uint8_t	SiS_NB_init[56][3]={
 {0x04, 0x00 ,0x07},					//Reg 0x04
 {0x05, 0x00 ,0x00},					//Reg 0x05 // alex
@@ -191,85 +191,11 @@
 {0x97, 0x00 ,0x00},					//Reg 0x97
 {0x98, 0x00 ,0x00},					//Reg 0x98
 {0x99, 0x00 ,0x00},					//Reg 0x99
-// alex
-//{0xD7, 0x00 ,0x00},					//Reg 0x99
-//{0xDD, 0x00 ,0x02},					//Reg 0x99
-//
-//{0x13, 0x00 ,0xF0},					//Reg 0x99
 
 {0x00, 0x00, 0x00}					//End of table
 };
 
-#else
-static const uint8_t	SiS_NB_init[61][3]={
-{0x04, 0x00 ,0x07},					//Reg 0x04
-{0x05, 0x00 ,0x00},					//Reg 0x05 // alex
-{0x0D, 0x00 ,0x20},					//Reg 0x0D
-{0x2C, 0x00 ,0x39},					//Reg 0x2C
-{0x2D, 0x00 ,0x10},					//Reg 0x2D
-{0x2E, 0x00 ,0x61},					//Reg 0x2E
-{0x2F, 0x00 ,0x07},					//Reg 0x2F
-{0x34, 0x00 ,0xA0},					//Reg 0x34
-{0x40, 0x00 ,0x36},					//Reg 0x40
-{0x42, 0x00 ,0xB9},					//Reg 0x42
-{0x43, 0x00 ,0x8B},					//Reg 0x43
-{0x44, 0x00 ,0x05},					//Reg 0x44
-{0x45, 0x00 ,0xFF},					//Reg 0x45
-{0x46, 0x00 ,0x90},					//Reg 0x46
-{0x47, 0x00 ,0xA0},					//Reg 0x47
-{0x4C, 0xFF ,0x50},					//Reg 0x4C //  SiS307 enable
-{0x4E, 0x00 ,0x00},					//Reg 0x4E
-{0x4F, 0x00 ,0x02},					//Reg 0x4F
-{0x5B, 0x00 ,0x44},					//Reg 0x5B
-{0x5D, 0x00 ,0x00},					//Reg 0x5D
-{0x5E, 0x00 ,0x25},					//Reg 0x5E
-{0x61, 0x00 ,0xB0},					//Reg 0x61
-{0x65, 0x00 ,0xB0},					//Reg 0x65
-{0x68, 0x00 ,0x4C},					//Reg 0x68
-{0x69, 0x00 ,0xD0},					//Reg 0x69
-{0x6B, 0x00 ,0x07},					//Reg 0x6B
-{0x6C, 0x00 ,0xDD},					//Reg 0x6C
-{0x6D, 0x00 ,0xAD},					//Reg 0x6D
-{0x6E, 0x00 ,0xE8},					//Reg 0x6E
-{0x6F, 0x00 ,0x4D},					//Reg 0x6F
-{0x70, 0x00 ,0x00},					//Reg 0x70
-{0x71, 0x00 ,0x80},					//Reg 0x71
-{0x72, 0x00 ,0x00},					//Reg 0x72
-{0x73, 0x00 ,0x00},					//Reg 0x73
-{0x74, 0x00 ,0x01},					//Reg 0x74
-{0x75, 0x00 ,0x10},					//Reg 0x75
-{0x7E, 0x00 ,0x29},					//Reg 0x7E
-{0x8B, 0x00 ,0x10},					//Reg 0x8B
-{0x8D, 0x00 ,0x03},					//Reg 0x8D
-{0xA1, 0x00 ,0xD0},					//Reg 0xA1
-{0xA2, 0x00 ,0x30},					//Reg 0xA2
-{0xA4, 0x00 ,0x0B},					//Reg 0xA4
-{0xA9, 0x00 ,0x02},					//Reg 0xA9
-{0xB0, 0x00 ,0x30},					//Reg 0xB0
-{0xB4, 0x00 ,0x30},					//Reg 0xB4
-{0x90, 0x00 ,0x00},					//Reg 0x90
-{0x91, 0x00 ,0x00},					//Reg 0x91
-{0x92, 0x00 ,0x00},					//Reg 0x92
-{0x93, 0x00 ,0x00},					//Reg 0x93
-{0x94, 0x00 ,0x00},					//Reg 0x94
-{0x95, 0x00 ,0x00},					//Reg 0x95
-{0x96, 0x00 ,0x00},					//Reg 0x96
-{0x97, 0x00 ,0x00},					//Reg 0x97
-{0x98, 0x00 ,0x00},					//Reg 0x98
-{0x99, 0x00 ,0x00},					//Reg 0x99
-// alex
-{0x86, 0x00 ,0x14},					//Reg 0x99
-{0x87, 0x00 ,0xC8},					//Reg 0x99
-{0xF4, 0x00 ,0x01},
-//
-{0x13, 0x00 ,0xF0},					//Reg 0x99
 
-{0x00, 0x00, 0x00}					//End of table
-};
-
-
-#endif
-#if 1
 static const uint8_t SiS_NBAGP_init[34][3]={
 {0xCF, 0xDF, 0x00},      //HT issue
 {0x06, 0xDF, 0x20},
@@ -309,78 +235,6 @@
 {0x00, 0x00, 0x00}     //End of table
 };
 
-
-
-#else
-
-//uint8_t SiS_NBAGP_init[53][3]={
-static const uint8_t SiS_NBAGP_init[40][3]={
-{0x04, 0x00 ,0x07},					//Reg 0x04
-{0x05, 0x00 ,0x01},					//Reg 0x05 // alex
-
-{0xCF, 0xDF, 0x00},      //HT issue
-{0x06, 0xDF, 0x20},
-{0x1E, 0xDF, 0x20},
-{0x50, 0x00, 0x02},
-{0x51, 0x00, 0x00},
-{0x54, 0x00, 0x09},
-{0x55, 0x00, 0x00},
-{0x56, 0x00, 0x80},
-{0x58, 0x00, 0x08},
-{0x60, 0x00, 0xB1},
-{0x61, 0x00, 0x02},
-{0x62, 0x00, 0x60},
-{0x63, 0x00, 0x60},
-{0x64, 0x00, 0xAA},
-{0x65, 0x00, 0x18},
-{0x68, 0x00, 0x23},
-{0x69, 0x00, 0x23},
-{0x6A, 0x00, 0xC8},
-{0x6B, 0x00, 0x08},
-{0x6C, 0x00, 0x00},
-{0x6D, 0x00, 0x00},
-{0x6E, 0x00, 0x08},
-{0x6F, 0x00, 0x00},
-{0xBB, 0x00, 0x00},
-{0xB5, 0x00, 0x30},
-{0xB0, 0x00, 0xDB},
-{0xB6, 0x00, 0x73},
-{0xB7, 0x00, 0x50},
-{0xBA, 0xBF, 0x41},
-{0xB4, 0x3F, 0xC0},
-{0xBF, 0xF9, 0x06},
-{0xBA, 0x00, 0x61},
-{0xBD, 0x7F, 0x80},
-
-
-
-{0x0D, 0x00 ,0x40},					//Reg 0x05 // alex
-/*
-{0x19, 0x00 ,0x01},					//Reg 0x05 // alex
-{0x1A, 0x00 ,0x01},					//Reg 0x05 // alex
-{0x1B, 0x00 ,0x40},					//Reg 0x05 // alex
-{0x1C, 0x00 ,0xE0},					//Reg 0x05 // alex
-{0x1D, 0x00 ,0xE0},					//Reg 0x05 // alex
-{0x20, 0x00 ,0xB0},					//Reg 0x05 // alex
-{0x21, 0x00 ,0xFE},					//Reg 0x05 // alex
-{0x22, 0x00 ,0xB0},					//Reg 0x05 // alex
-{0x23, 0x00 ,0xFE},					//Reg 0x05 // alex
-{0x24, 0x00 ,0x00},					//Reg 0x05 // alex
-{0x25, 0x00 ,0xD8},					//Reg 0x05 // alex
-{0x26, 0x00 ,0xF0},					//Reg 0x05 // alex
-{0x27, 0x00 ,0xDF},					//Reg 0x05 // alex
-*/
-{0x3E, 0x00 ,0x0A},					//Reg 0x05 // alex
-
-{0xCB, 0x00 ,0x10},					//Reg 0x05 // alex
-{0xCF, 0x00 ,0x48},					//Reg 0x05 // alex
-
-
-{0x00, 0x00, 0x00}     //End of table
-};
-
-#endif
-
 static const uint8_t	SiS_ACPI_2_init[56][3]={
 {0x00, 0x00, 0xFF},					//Reg 0x00
 {0x01, 0x00, 0xFF},					//Reg 0x01
@@ -440,129 +294,55 @@
 {0x00, 0x00, 0x00}					//End of table
 };
 
-#if 0
-static const uint8_t	SiS_SiS1183_init[60][3]={
-{0x04, 0x00, 0x05},					 
-{0x09, 0x00, 0x05},					 
-{0x2C, 0x00, 0x39},					 
-{0x2D, 0x00, 0x10},					  
-{0x2E, 0x00, 0x83},					 
-{0x2F, 0x00, 0x11},					 
-{0x90, 0x00, 0x40},					 
-{0x91, 0x00, 0x00},	// set mode				 
-{0x50, 0x00, 0xA2},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0x00, 0x96},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0xF7, 0x00},					 
-{0x56, 0x00, 0xC0},	
-{0x57, 0x00, 0x14},
-{0x67, 0x00, 0x28},					 
-{0x81, 0x00, 0xB3},					 
-{0x82, 0x00, 0x72},					 
-{0x83, 0x00, 0x40},					 
-{0x85, 0x00, 0xB3},					 
-{0x86, 0x00, 0x72},					 
-{0x87, 0x00, 0x40},
-{0x88, 0x00, 0xDE},      // after set mode					 
-{0x89, 0x00, 0xB3},					 
-{0x8A, 0x00, 0x72},					 
-{0x8B, 0x00, 0x40},					 
-{0x8C, 0x00, 0xDE},					 
-{0x8D, 0x00, 0xB3},					 
-{0x8E, 0x00, 0x92},					 
-{0x8F, 0x00, 0x40},					 
-{0x93, 0x00, 0x00},					 
-{0x94, 0x00, 0x80},					 
-{0x95, 0x00, 0x08},					 
-{0x96, 0x00, 0x80},					 
-{0x97, 0x00, 0x08},
-{0x9C, 0x00, 0x80},					 
-{0x9D, 0x00, 0x08},					 
-{0x9E, 0x00, 0x80},					 
-{0x9F, 0x00, 0x08},					 
-{0xA0, 0x00, 0x15},					 
-{0xA1, 0x00, 0x15},					 
-{0xA2, 0x00, 0x15},					 
-{0xA3, 0x00, 0x15},
-
-//{0xD8, 0xFE, 0x01},	// Com reset				
-//{0xC8, 0xFE, 0x01},
-//{0xE8, 0xFE, 0x01},
-//{0xF8, 0xFE, 0x01},
-{0xC4, 0xFF, 0xFF},    // Clear status					 
-{0xC5, 0xFF, 0xFF},
-{0xC6, 0xFF, 0xFF},
-{0xC7, 0xFF, 0xFF},
-{0xD4, 0xFF, 0xFF},
-{0xD5, 0xFF, 0xFF},
-{0xD6, 0xFF, 0xFF},
-{0xD7, 0xFF, 0xFF},
-{0xE4, 0xFF, 0xFF},    // Clear status					 
-{0xE5, 0xFF, 0xFF},
-{0xE6, 0xFF, 0xFF},
-{0xE7, 0xFF, 0xFF},
-{0xF4, 0xFF, 0xFF},
-{0xF5, 0xFF, 0xFF},
-{0xF6, 0xFF, 0xFF},
-{0xF7, 0xFF, 0xFF},
-{0x00, 0x00, 0x00}					//End of table
-};
-
-#else
-
 static const uint8_t	SiS_SiS1183_init[44][3]={
-{0x04, 0x00, 0x05},					 
-{0x09, 0x00, 0x05},					 
-{0x2C, 0x00, 0x39},					 
-{0x2D, 0x00, 0x10},					  
-{0x2E, 0x00, 0x83},					 
-{0x2F, 0x00, 0x11},					 
-{0x90, 0x00, 0x40},					 
-{0x91, 0x00, 0x00},	// set mode				 
-{0x50, 0x00, 0xA2},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0x00, 0x96},					 
-{0x52, 0x00, 0xA2},					 
-{0x55, 0xF7, 0x00},					 
-{0x56, 0x00, 0xC0},	
+{0x04, 0x00, 0x05},
+{0x09, 0x00, 0x05},
+{0x2C, 0x00, 0x39},
+{0x2D, 0x00, 0x10},
+{0x2E, 0x00, 0x83},
+{0x2F, 0x00, 0x11},
+{0x90, 0x00, 0x40},
+{0x91, 0x00, 0x00},	// set mode
+{0x50, 0x00, 0xA2},
+{0x52, 0x00, 0xA2},
+{0x55, 0x00, 0x96},
+{0x52, 0x00, 0xA2},
+{0x55, 0xF7, 0x00},
+{0x56, 0x00, 0xC0},
 {0x57, 0x00, 0x14},
-{0x67, 0x00, 0x28},					 
-{0x81, 0x00, 0xB3},					 
-{0x82, 0x00, 0x72},					 
-{0x83, 0x00, 0x40},					 
-{0x85, 0x00, 0xB3},					 
-{0x86, 0x00, 0x72},					 
+{0x67, 0x00, 0x28},
+{0x81, 0x00, 0xB3},
+{0x82, 0x00, 0x72},
+{0x83, 0x00, 0x40},
+{0x85, 0x00, 0xB3},
+{0x86, 0x00, 0x72},
 {0x87, 0x00, 0x40},
-{0x88, 0x00, 0xDE},      // after set mode					 
-{0x89, 0x00, 0xB3},					 
-{0x8A, 0x00, 0x72},					 
-{0x8B, 0x00, 0x40},					 
-{0x8C, 0x00, 0xDE},					 
-{0x8D, 0x00, 0xB3},					 
-{0x8E, 0x00, 0x92},					 
-{0x8F, 0x00, 0x40},					 
-{0x93, 0x00, 0x00},					 
-{0x94, 0x00, 0x80},					 
-{0x95, 0x00, 0x08},					 
-{0x96, 0x00, 0x80},					 
+{0x88, 0x00, 0xDE},      // after set mode
+{0x89, 0x00, 0xB3},
+{0x8A, 0x00, 0x72},
+{0x8B, 0x00, 0x40},
+{0x8C, 0x00, 0xDE},
+{0x8D, 0x00, 0xB3},
+{0x8E, 0x00, 0x92},
+{0x8F, 0x00, 0x40},
+{0x93, 0x00, 0x00},
+{0x94, 0x00, 0x80},
+{0x95, 0x00, 0x08},
+{0x96, 0x00, 0x80},
 {0x97, 0x00, 0x08},
-{0x9C, 0x00, 0x80},					 
-{0x9D, 0x00, 0x08},					 
-{0x9E, 0x00, 0x80},					 
-{0x9F, 0x00, 0x08},					 
-{0xA0, 0x00, 0x15},					 
-{0xA1, 0x00, 0x15},					 
-{0xA2, 0x00, 0x15},					 
+{0x9C, 0x00, 0x80},
+{0x9D, 0x00, 0x08},
+{0x9E, 0x00, 0x80},
+{0x9F, 0x00, 0x08},
+{0xA0, 0x00, 0x15},
+{0xA1, 0x00, 0x15},
+{0xA2, 0x00, 0x15},
 {0xA3, 0x00, 0x15},
-
-
 {0x00, 0x00, 0x00}					//End of table
 };
 
-#endif
 
-/*       In => Share Memory size 
+/*       In => Share Memory size
                             => 00h :    0MBytes
                             => 02h :   32MBytes
                             => 03h :   64MBytes




From corey.osgood at gmail.com  Fri Nov  2 18:06:40 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 02 Nov 2007 13:06:40 -0400
Subject: [LinuxBIOS] mptable util not working?
In-Reply-To: <20071102125705.12gtctx6ows84sgk@www.smittys.pointclark.net>
References: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>	<20071102165223.GB25764@greenwood>
	<20071102125705.12gtctx6ows84sgk@www.smittys.pointclark.net>
Message-ID: <472B5920.4090501@gmail.com>

joe at smittys.pointclark.net wrote:
> Quoting Uwe Hermann <uwe at hermann-uwe.de>:
>
>   
>> On Thu, Nov 01, 2007 at 09:30:11AM -0400, joe at smittys.pointclark.net wrote:
>>     
>>> Hello,
>>> I am having prolems with the mptable utility. I keeps telling me "MP
>>> FPS NOT found, suggest trying -grope option!!!". If I try the grope
>>> option it still spits out the same message. Am I doing something wrong?
>>>       
>> Probably not, could be that your system doesn't _have_ an mptable.
>> Not all systems do. Which board are we talking about here? Is it multi-CPU?
>>
>>
>> Uwe.
>>     
>
> No single Processor, that's probibly why. It seems to contain alot of  
> IO data though. I think this is my problem, CPU to IO doesn't seem to  
> be communicating, and I thought the mptable might help. I'm  
> stumped.... But Corey maybe able to help me figure this out very soon.
>
> Thanks - Joe

Yeah, there's probably no mptable on that system. Even if there was, the
data output by it won't compile unless CONFIG_SMP is set in LB (which
you really don't need, since it's not an SMP system).

Uwe recently sent in some fixes to the 440bx to help speed that up, you
should take a look at it. I think one of the issues was with the cpu.

-Corey



From uwe at hermann-uwe.de  Fri Nov  2 18:08:56 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Nov 2007 18:08:56 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <20071102164403.GA22159@coresystems.de>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood>
	<20071102164403.GA22159@coresystems.de>
Message-ID: <20071102170856.GD25764@greenwood>

On Fri, Nov 02, 2007 at 05:44:03PM +0100, Stefan Reinauer wrote:
> > > -u8 smbus_read_byte(u32 dimm, u32 offset)
> > > +/**
> > > + * Read a byte from the smbus
> > > + *
> > > + * @param dimm The address location of the dimm on the smbus
> > > + * @param offset The offset the data is located at
> > > + */
> > 
> > > +u8 smbus_read_byte(u8 dimm, u8 offset)
> > 
> > I'm still not entirely sure they're always only 8 bit. Do you have a
> > pointer to a datasheet or spec or standard where it's explicitly
> > defined as 8 bit? Yes, it _is_ 8 bits in most cases, but can we be sure
> > that it'll be 8 bit in _all_ of them? On all chipsets and controllers?
> 
> smbus address space is 8 bits. Let's reflect this in the code. We can

ACK.


> think about this when we find the first machine where it is not.

I don't know if there are any, I was just speculating. If SMBus address
space is specified as 8 bits u8 is the way to go.


> 
> > > +inline u8 spd_read_byte(u32 address, u8 offset)
> > > +{
> > > +	return smbus_read_byte(address, offset);
> > > +}
> > 
> > Hm, this is usually done in auto.c per-mainboard, I think. Either
> > you make spd_read_byte() a wrapper for smbus_read_byte(), or you
> > use the "fake spd" method to return hard-coded settings if there's
> > no real SPD data to be read.
>  
> Yes, this is a mainboard specific abstraction. It might have to
> circumvent smbus switches on the bus.

OK, should be dropped here then.


> > Not sure this function makes sense in vt8237r_early_smbus.c, because of
> > the above and also because it's not SMBus-related per se. I'd say drop it.
> > 
> > Also, address is 32bit here but 8bit in smbus_read_byte()?
> 
> That's fine. The i2c has 8 (actually 7) bits address space. spd might
> not necessarily be behind the i2c bus. Or it might have a number of
> switches. So you might have an address of 0xaabbccdd saying that aa, bb,
> cc, dd are the settings of 3 i2c switches, while dd is the actual
> address of the spd on the bus _after_ doing the other settings. This is
> done on the ag?mi aruma in a similar way.

Thanks for the clarifications! For this patch that's not relevant though
as spd_read_byte() should be dropped anyway then as it's board specific.

But maybe we should have this info somewhere in the wiki?
http://linuxbios.org/Developer_Manual ?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Fri Nov  2 18:15:55 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Nov 2007 18:15:55 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472B52B4.9050801@gmail.com>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
Message-ID: <20071102171555.GE25764@greenwood>

On Fri, Nov 02, 2007 at 12:39:16PM -0400, Corey Osgood wrote:
> >>  	/* Yes, this is a mess, but it's the easiest way to do it. */
> >> -	while ((inb(SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT)
> >> +	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
> >>     
> >
> > Rationale? Does it make a big difference?
> >   
> 
> No, not really. Just that now the loop runs SMBUS_TIMEOUT times, instead
> if SMBUS_TIMEOUT + 1.

OK, so it's more a cosmetical issue, no real code/functionality changes?


> The offset will always be 8 bit, since there are 256 offsets (and >half
> of them we'll never touch anyways). The address also has to be 8 bit,
> since it's programmed into an 8 bit register (per vt8237r datasheet, p125).

Yep, u8 for both is fine then.


> >> +#ifdef DIMM_SOCKETS
> >> +	ram_slots = DIMM_SOCKETS;
> >> +#else
> >> +	ram_slots = sizeof(ctrl->channel0)/sizeof(ctrl->channel0[0]);
> >> +#endif
> >>     
> >
> > Can you explain? Shouldn't DIMM_SOCKETS always match
> > sizeof(ctrl->channel0)/sizeof(ctrl->channel0[0])? When does it happen
> > that they do not match (and why?).
> >   
> 
> Unless someone doesn't define DIMM_SOCKETS, or uses some other name. I
> suppose that could be just dropped in favor of ARRAY_SIZE().

Yes, drop the DIMM_SOCKETS part and dependency IMO.

  ARRAY_SIZE(ctrl->channel0);

should do (if there's only one channel).


> > Please explain the SPD_MEMORY_TYPE_SDRAM/SPD_MEMORY_TYPE_SDRAM_DDR2
> > check in the comment here.
> >
> > If all you want is to know whether some sensible RAM type is
> > returned wouldn't "> 0" and "< 0xff" be enough (as per your comment)?
> > You don't really care about the exact type, you only want to know _if_ there's
> > a DIMM here, correct?
> >   
> 
> Safety's sake. If the smbus happens to spurt out some odd value (I've
> seen 0x30 once) while this is going on, we want to be sure it's really

OK, but how do we know the odd values can never be e.g. 8 (which is
valid) in some cases? In such a scenario this code wouldn't work?


> valid data. Originally it only sought DDR2, but that's bad since this
> southbridge can be used on DDR systems as well. Looking further though,
> it's only DDR/DDR2, so the SDRAM bit could be dropped.
> 
> > If I read this correctly you're checking whether you get one of these?
> >
> > #define SPD_MEMORY_TYPE_SDRAM            4
> > #define SPD_MEMORY_TYPE_MULTIPLEXED_ROM  5
> > #define SPD_MEMORY_TYPE_SGRAM_DDR        6
> > #define SPD_MEMORY_TYPE_SDRAM_DDR        7
> > #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
> >
> > If we make this "> 0" and "< 0xff" ("< 10" or so should be enough, too)
> > then this function might be usable on non-vt8237r chipsets and can go
> > in some global SMBus file to be used by others?
> >   
> 
> Perhaps. vt8231/8235 could use something similar, they just use a big
> delay as of right now.

I'd rather match all legit RAM types (1-8 or so) and make it a function
which can be used by every chip (not only vt*). Think EDO, DDR3, whatever.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Fri Nov  2 18:18:18 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Nov 2007 18:18:18 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <20071102170856.GD25764@greenwood>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood>
	<20071102164403.GA22159@coresystems.de>
	<20071102170856.GD25764@greenwood>
Message-ID: <20071102171818.GB26123@coresystems.de>

* Uwe Hermann <uwe at hermann-uwe.de> [071102 18:08]:
> > That's fine. The i2c has 8 (actually 7) bits address space. spd might
> > not necessarily be behind the i2c bus. Or it might have a number of
> > switches. So you might have an address of 0xaabbccdd saying that aa, bb,
> > cc, dd are the settings of 3 i2c switches, while dd is the actual
> > address of the spd on the bus _after_ doing the other settings. This is
> > done on the ag?mi aruma in a similar way.
> 
> Thanks for the clarifications! For this patch that's not relevant though
> as spd_read_byte() should be dropped anyway then as it's board specific.
> 
> But maybe we should have this info somewhere in the wiki?
> http://linuxbios.org/Developer_Manual ?

Sounds reasonable

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From joe at smittys.pointclark.net  Fri Nov  2 18:20:56 2007
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Fri, 02 Nov 2007 13:20:56 -0400
Subject: [LinuxBIOS] mptable util not working?
In-Reply-To: <472B5920.4090501@gmail.com>
References: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>
	<20071102165223.GB25764@greenwood>
	<20071102125705.12gtctx6ows84sgk@www.smittys.pointclark.net>
	<472B5920.4090501@gmail.com>
Message-ID: <20071102132056.voikawze8ooc0w8g@www.smittys.pointclark.net>

Quoting Corey Osgood <corey.osgood at gmail.com>:

> joe at smittys.pointclark.net wrote:
>> Quoting Uwe Hermann <uwe at hermann-uwe.de>:
>>
>>
>>> On Thu, Nov 01, 2007 at 09:30:11AM -0400, joe at smittys.pointclark.net wrote:
>>>
>>>> Hello,
>>>> I am having prolems with the mptable utility. I keeps telling me "MP
>>>> FPS NOT found, suggest trying -grope option!!!". If I try the grope
>>>> option it still spits out the same message. Am I doing something wrong?
>>>>
>>> Probably not, could be that your system doesn't _have_ an mptable.
>>> Not all systems do. Which board are we talking about here? Is it multi-CPU?
>>>
>>>
>>> Uwe.
>>>
>>
>> No single Processor, that's probibly why. It seems to contain alot of
>> IO data though. I think this is my problem, CPU to IO doesn't seem to
>> be communicating, and I thought the mptable might help. I'm
>> stumped.... But Corey maybe able to help me figure this out very soon.
>>
>> Thanks - Joe
>
> Yeah, there's probably no mptable on that system. Even if there was, the
> data output by it won't compile unless CONFIG_SMP is set in LB (which
> you really don't need, since it's not an SMP system).
>
> Uwe recently sent in some fixes to the 440bx to help speed that up, you
> should take a look at it. I think one of the issues was with the cpu.
>
> -Corey
>
The only thing I coud see is Uwe changed it to do a 200us delay at the  
begining of the sdram_enable cycle is there more?


Thanks - Joe



From ward at gnu.org  Fri Nov  2 18:25:48 2007
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 2 Nov 2007 13:25:48 -0400
Subject: [LinuxBIOS] r2921
	-	trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
In-Reply-To: <20071102165334.GC25764@greenwood>
References: <E1In1nX-0007td-TB@mi002.mc1.hosteurope.de>
	<20071031011224.GR19408@greenwood>
	<20071031022657.GA7871@localdomain>
	<20071102165334.GC25764@greenwood>
Message-ID: <20071102172548.GA9655@localdomain>

On Fri, Nov 02, 2007 at 05:53:34PM +0100, Uwe Hermann wrote:
> On Tue, Oct 30, 2007 at 10:26:57PM -0400, Ward Vandewege wrote:
> > > Can somebody please update the wiki status page?
> > 
> > Done.
> 
> Are you sure? I don't see any changes. Maybe you forgot to press "Submit"?

Hmm, I guess so. Sorry about that. Now fixed.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From corey.osgood at gmail.com  Fri Nov  2 18:30:25 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 02 Nov 2007 13:30:25 -0400
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <20071102171555.GE25764@greenwood>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
	<20071102171555.GE25764@greenwood>
Message-ID: <472B5EB1.6000100@gmail.com>

Updated patch attached.

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>

Comments inline below.

Uwe Hermann wrote:
> On Fri, Nov 02, 2007 at 12:39:16PM -0400, Corey Osgood wrote:
>   
>>> Please explain the SPD_MEMORY_TYPE_SDRAM/SPD_MEMORY_TYPE_SDRAM_DDR2
>>> check in the comment here.
>>>
>>> If all you want is to know whether some sensible RAM type is
>>> returned wouldn't "> 0" and "< 0xff" be enough (as per your comment)?
>>> You don't really care about the exact type, you only want to know _if_ there's
>>> a DIMM here, correct?
>>>   
>>>       
>> Safety's sake. If the smbus happens to spurt out some odd value (I've
>> seen 0x30 once) while this is going on, we want to be sure it's really
>>     
>
> OK, but how do we know the odd values can never be e.g. 8 (which is
> valid) in some cases? In such a scenario this code wouldn't work?
>   

Yes, but as I said, once, and this has run a lot of times. And IIRC it
was the last cycle before valid data was returned. It would be very rare
for this to fail, IMO (although the more dram types we add, the more
likely it is to fail).

>> valid data. Originally it only sought DDR2, but that's bad since this
>> southbridge can be used on DDR systems as well. Looking further though,
>> it's only DDR/DDR2, so the SDRAM bit could be dropped.
>>
>>     
>>> If I read this correctly you're checking whether you get one of these?
>>>
>>> #define SPD_MEMORY_TYPE_SDRAM            4
>>> #define SPD_MEMORY_TYPE_MULTIPLEXED_ROM  5
>>> #define SPD_MEMORY_TYPE_SGRAM_DDR        6
>>> #define SPD_MEMORY_TYPE_SDRAM_DDR        7
>>> #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
>>>
>>> If we make this "> 0" and "< 0xff" ("< 10" or so should be enough, too)
>>> then this function might be usable on non-vt8237r chipsets and can go
>>> in some global SMBus file to be used by others?
>>>   
>>>       
>> Perhaps. vt8231/8235 could use something similar, they just use a big
>> delay as of right now.
>>     
>
> I'd rather match all legit RAM types (1-8 or so) and make it a function
> which can be used by every chip (not only vt*). Think EDO, DDR3, whatever.
>   

EDO I don't think we really need to support, but if someone needs it in
the future, they can change it easily enough. I've added DDR3 (0xb
according to micron), just in case. I've left the function in vt8237r
because there's no file that it would really fit into right now. If
someone else wants/needs to use it in the future, it should be moved.
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From uwe at hermann-uwe.de  Fri Nov  2 18:32:46 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Nov 2007 18:32:46 +0100
Subject: [LinuxBIOS] mptable util not working?
In-Reply-To: <20071102132056.voikawze8ooc0w8g@www.smittys.pointclark.net>
References: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>
	<20071102165223.GB25764@greenwood>
	<20071102125705.12gtctx6ows84sgk@www.smittys.pointclark.net>
	<472B5920.4090501@gmail.com>
	<20071102132056.voikawze8ooc0w8g@www.smittys.pointclark.net>
Message-ID: <20071102173246.GF25764@greenwood>

On Fri, Nov 02, 2007 at 01:20:56PM -0400, joe at smittys.pointclark.net wrote:
> The only thing I coud see is Uwe changed it to do a 200us delay at the 
> begining of the sdram_enable cycle is there more?

The important thing is this (in Config.lb):

  device apic_cluster 0 on
    chip cpu/intel/slot_2
      device apic 0 on end
    end
  end

If you only use

  chip cpu/intel/slot_2
  end

that'll not do the full CPU init and thus result in a _very_ slow
system. I'm not entirely sure it's the _correct_ fix, but it _does_
fix the issue I have seen on the 440BX boards.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From joe at smittys.pointclark.net  Fri Nov  2 18:52:09 2007
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Fri, 02 Nov 2007 13:52:09 -0400
Subject: [LinuxBIOS] mptable util not working?
In-Reply-To: <20071102173246.GF25764@greenwood>
References: <20071101093011.yf27zu12iskw0g8c@www.smittys.pointclark.net>
	<20071102165223.GB25764@greenwood>
	<20071102125705.12gtctx6ows84sgk@www.smittys.pointclark.net>
	<472B5920.4090501@gmail.com>
	<20071102132056.voikawze8ooc0w8g@www.smittys.pointclark.net>
	<20071102173246.GF25764@greenwood>
Message-ID: <20071102135209.3rhfeut5z9q8k44o@www.smittys.pointclark.net>

Quoting Uwe Hermann <uwe at hermann-uwe.de>:

> On Fri, Nov 02, 2007 at 01:20:56PM -0400, joe at smittys.pointclark.net wrote:
>> The only thing I coud see is Uwe changed it to do a 200us delay at the
>> begining of the sdram_enable cycle is there more?
>
> The important thing is this (in Config.lb):
>
>   device apic_cluster 0 on
>     chip cpu/intel/slot_2
>       device apic 0 on end
>     end
>   end
>
> If you only use
>
>   chip cpu/intel/slot_2
>   end
>
> that'll not do the full CPU init and thus result in a _very_ slow
> system. I'm not entirely sure it's the _correct_ fix, but it _does_
> fix the issue I have seen on the 440BX boards.
>
>
> Uwe.
>
Thanks Uwe I will give that a try.

Thanks - Joe



From myles at pel.cs.byu.edu  Fri Nov  2 19:18:33 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Fri, 2 Nov 2007 12:18:33 -0600
Subject: [LinuxBIOS] Stale payloads
Message-ID: <035401c81d7c$c78e6f90$1223040a@chimp>

I've been spinning my wheels because of a stale payload.

In the fallback directory, the payload file depends on the
../{../}*/payload.elf file.  If you change that to ../../payload.lzma.elf to
retry, it won't get the new file if payload is newer than payload.lzma.elf.


It seems like there are several possible fixes, but the one I like is
changing buildtarget to remove the payload* files from normal, fallback,
etc.  The problem is that it doesn't look like buildtarget knows about those
directories.

Is there a better way?

Thanks,
Myles





From r.marek at assembler.cz  Fri Nov  2 22:30:26 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 02 Nov 2007 22:30:26 +0100
Subject: [LinuxBIOS] [PATCH] Add support for the Asus A8V-E
	SE	motherboard
In-Reply-To: <20071031104008.GB11911@coresystems.de>
References: <4723883C.8010908@assembler.cz> <20071030141811.GG23532@greenwood>
	<47279B0A.9050602@assembler.cz>
	<20071031104008.GB11911@coresystems.de>
Message-ID: <472B96F2.6030709@assembler.cz>

> one is wrong.. which one?

It is 4 bytes, followed by 4 bytes of revision.
So the memcpy is wrong. I fixed that

> Then make it LNXB. LNXI is Linux Networx, a former contributor or
> LinuxBIOS.

OK

> 
>>> Copyright (C) xxxx Stefan Reinauer <stepan at openbios.org>
>>> Copyright (C) xxxx Nick Barker <nick.barker9 at btinternet.com>
>>>
>>> then. I think this is not done in the original file either, and should
>>> be fixed there, too. Listing all copyright owners explicitly is important.
>> What about xxxxx?
>  
> Just forget about this for now. It's a different issue and should not
> block your code.


I put 2004 Stefan and Nick 2005

>>>> +
>>>> +	while (1) {
>>>> +		/* daisy daisy ... */
>>> ???
>> http://en.wikipedia.org/wiki/Hal_9000
>  
> :-)) I love it.

Cool, the chipset is quite stupid here, you need to hold 1 and wait until it 
comes...

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

I will repost some patches which have not yet been accepted, so my SVN tree have 
no diffs.

Rudolf
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From r.marek at assembler.cz  Fri Nov  2 22:53:14 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 02 Nov 2007 22:53:14 +0100
Subject: [LinuxBIOS] [PATCH] Add ACPI MCFG table (resend)
Message-ID: <472B9C4A.2010309@assembler.cz>

Hello,

This patch adds support for MCFG table, which allows OS to find the MMCONFIG for 
memory mapped PCIe config.

However this patch is not enough to enable it on Linux, Linux do not trust 
BIOSes too much, so a small patch to kernel to disable the check if this region 
is e820 reserved.

PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
PCI: Not using MMCONFIG.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf
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From r.marek at assembler.cz  Fri Nov  2 23:32:49 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 02 Nov 2007 23:32:49 +0100
Subject: [LinuxBIOS] [PATCH] Fix the AMD K8 DDR init (resend)
Message-ID: <472BA591.1020806@assembler.cz>

Hello,

This patch changes the "if else" style of parameter matching to table and also
changes the rdpreamble parameter, which will cause that more then one DIMM will
work for 939 motherboard. It seems that this code was written with some very 
early version of the specs.

What about the 2T support? Now it can be triggered with the code change only.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf

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From jordan.crouse at amd.com  Fri Nov  2 23:54:14 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 2 Nov 2007 16:54:14 -0600
Subject: [LinuxBIOS] Fix the AMD K8 DDR init (resend)
In-Reply-To: <472BA591.1020806@assembler.cz>
References: <472BA591.1020806@assembler.cz>
Message-ID: <20071102225414.GF20979@cosmic.amd.com>

On 02/11/07 23:32 +0100, Rudolf Marek wrote:
> Hello,
>
> This patch changes the "if else" style of parameter matching to table and 
> also
> changes the rdpreamble parameter, which will cause that more then one DIMM 
> will
> work for 939 motherboard. It seems that this code was written with some 
> very early version of the specs.
>
> What about the 2T support? Now it can be triggered with the code change 
> only.
>
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Tested it here - looks great.  Thank you very much!  This is
great stuff.

Jordan





From uwe at hermann-uwe.de  Sat Nov  3 00:02:55 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 3 Nov 2007 00:02:55 +0100
Subject: [LinuxBIOS] ACPI license cleanup
Message-ID: <20071102230255.GG25764@greenwood>

[New thread, as it's not related to the A8V-E SE only]

On Wed, Oct 31, 2007 at 11:44:43AM +0100, Stefan Reinauer wrote:
> * Uwe Hermann <uwe at hermann-uwe.de> [071031 00:12]:
> > >>> Index: src/mainboard/asus/a8v-e_se/acpi_tables.c
> > >>> ===================================================================
> > >>> --- src/mainboard/asus/a8v-e_se/acpi_tables.c	(revision 0)
> > >>> +++ src/mainboard/asus/a8v-e_se/acpi_tables.c	(revision 0)
> > >>> @@ -0,0 +1,170 @@
> > >>> +/*
> > >>> + * This file is part of the LinuxBIOS project.
> > >>> + * written by Stefan Reinauer <stepan at openbios.org>
> > >>> + * ACPI FADT, FACS, and DSDT table support added by + * Nick Barker 
> > >>> <nick.barker9 at btinternet.com>, and those portions
> > >>> + *
> > >>> + * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
> > >> Hm, please add
> > >> Copyright (C) xxxx Stefan Reinauer <stepan at openbios.org>
> > >> Copyright (C) xxxx Nick Barker <nick.barker9 at btinternet.com>
> > >> then. I think this is not done in the original file either, and should
> > >> be fixed there, too. Listing all copyright owners explicitly is important.
> > >
> > > What about xxxxx?
> > 
> > The year(s) of the copyright. 
> > 
> >  * (C) Copyright 2004 Nick Barker
> >  * (C) Copyright 2005 Stefan Reinauer
>  
> Uwe.. I am listed as the original author.. how comes you suggest Nick
> has a copyright older than mine, even though the comment says he _added_
> something to my code? 

No idea :)

I copied the lines from the file I thought was used as a basis,
src/mainboard/via/epia-m/acpi_tables.c, but it seems several of the
ACPI-related files have incomplete, maybe even incorrect, copyright and
license lines.


Here's the current status of all *acpi.c files in svn:

./src/southbridge/via/vt8231/vt8231_acpi.c:
No license header at all.

./src/southbridge/amd/amd8111/amd8111_acpi.c:
No license header at all.

./src/mainboard/iwill/dk8_htx/acpi_tables.c:
/*
 * Island Aruma ACPI support
 * written by Stefan Reinauer <stepan at openbios.org>
 *  (C) 2005 Stefan Reinauer
 *
 *
 *  Copyright 2005 AMD
 *  2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
 */

./src/mainboard/amd/serengeti_cheetah/acpi_tables.c:
/*
 * Island Aruma ACPI support
 * written by Stefan Reinauer <stepan at openbios.org>
 *  (C) 2005 Stefan Reinauer
 *
 *
 *  Copyright 2005 AMD
 *  2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
 */

./src/mainboard/via/epia-m/acpi_tables.c:
/*
 * LinuxBIOS ACPI Table support
 * written by Stefan Reinauer <stepan at openbios.org>
 * ACPI FADT, FACS, and DSDT table support added by 
 * Nick Barker <nick.barker9 at btinternet.com>, and those portions
 * (C) Copyright 2004 Nick Barker
 * (C) Copyright 2005 Stefan Reinauer
 */

./src/mainboard/intel/xe7501devkit/acpi_tables.c:
/*
 * Ported to Intel XE7501DEVKIT from Agami Aruma
 * written by Stefan Reinauer <stepan at openbios.org>
 *  (C) 2005 Stefan Reinauer
 *  (C) 2005 Digital Design Corporation
 */

./src/mainboard/agami/aruma/acpi_tables.c:
/*
 * Agami Aruma ACPI support
 * 
 *  Copyright 2005 Stefan Reinauer
 *  Copyright 2005 AMD
 *  
 * written by Stefan Reinauer <stepan at openbios.org>
 *  2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
 */

./src/mainboard/agami/aruma/acpi_tables_static.c:
/*
 * Agami Aruma ACPI support
 * 
 * written by Stefan Reinauer <stepan at coresystems.de>
 *  (C) 2005 Stefan Reinauer
 *  (C) 2007 coresystems GmbH
 */

./src/northbridge/amd/amdk8/amdk8_acpi.c:
/*============================================================================
Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
This software and any related documentation (the "Materials") are the
confidential proprietary information of AMD. Unless otherwise provided in a
software agreement specifically licensing the Materials, the Materials are
provided in confidence and may not be distributed, modified, or reproduced in
whole or in part by any means.
LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
LIMITATION MAY NOT APPLY TO YOU.
AMD does not assume any responsibility for any errors which may appear in the
Materials nor any responsibility to support or update the Materials. AMD
retains the right to modify the Materials at any time, without notice, and is
not obligated to provide such modified Materials to you.
NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
further information, software, technical information, know-how, or show-how
available to you.
U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
RIGHTS." Use, duplication, or disclosure by the Government is subject to the
restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
its successor. Use of the Materials by the Government constitutes
acknowledgement of AMD's proprietary rights in them.
============================================================================*/
// 2005.9 serengeti support
// by yhlu
//
/*
 * 2005.9 yhlu add madt lapic creat dynamically and SRAT related
 */

./src/arch/i386/boot/acpi.c:
/*
 * LinuxBIOS ACPI Table support
 * written by Stefan Reinauer <stepan at openbios.org>
 *  (C) 2004 SUSE LINUX AG
 *  (C) 2005 Stefan Reinauer
 *
 * ACPI FADT, FACS, and DSDT table support added by 
 * Nick Barker <nick.barker9 at btinternet.com>, and those portions
 *  (C) Copyright 2004 Nick Barker
 *
 * Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
 * 2005.9 yhlu add SRAT table generation
 */


I have only looked at files with "acpi" in the name so far. Other
relevant files might also need works, e.g. *fadt* etc.


> I wrote the ACPI code in 2003, originally for K8. This code is derived
> from it.
> 
> Which is why this is (C) 2003 SUSE Linux AG

OK, so if all of the above is based on that 2003 SUSE code, all of the above
files (and likely some other ACPI-related ones?) need some serious fixing.

Please let me know _how_ they are to be fixed and I can provide patches (or
you do the work and post patches, either is fine).

All of the files share (at least) one problem, the missing GPL header (GPLv2,
I assume?), which we should add. Other problems are the seemingly
incorrect/incomplete (C) lines.


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Sat Nov  3 00:17:58 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  3 Nov 2007 00:17:58 +0100
Subject: [LinuxBIOS] r2934 - in trunk/LinuxBIOSv2: src/mainboard/asus
	src/mainboard/asus/a8v-e_se targets/asus targets/asus/a8v-e_se
Message-ID: <mailman.828.1355071196.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-03 00:17:57 +0100 (Sat, 03 Nov 2007)
New Revision: 2934

Added:
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/acpi_tables.c
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/chip.h
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cmos.layout
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/dsdt.asl
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/fadt.c
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mainboard.c
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mptable.c
   trunk/LinuxBIOSv2/targets/asus/a8v-e_se/
   trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb
Log:
Asus A8V-E-SE support from Rudolf Marek


Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Config.lb	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,274 @@
+## 
+## This file is part of the LinuxBIOS project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+##
+## Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+    if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+    else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+    end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD     = 1
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end 
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_ACPI_TABLES
+        object acpi_tables.o
+        object fadt.o
+	makerule dsdt.c
+		depends "$(MAINBOARD)/dsdt.asl"
+		action  "iasl -tc $(MAINBOARD)/dsdt.asl"
+		action  "mv dsdt.hex dsdt.c"
+	end
+        object ./dsdt.o
+end
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT	
+		makerule ./cache_as_ram_auto.o
+		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+		end
+	else
+		makerule ./cache_as_ram_auto.inc
+        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+		end
+	end
+
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+	mainboardinit southbridge/via/k8t890/romstrap.inc
+	ldscript /southbridge/via/k8t890/romstrap.lds
+
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+end
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+
+if USE_FALLBACK_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	end
+end
+
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject cache_as_ram_auto.o
+	else
+		mainboardinit ./cache_as_ram_auto.inc
+	end
+end
+
+##
+## Include the secondary Configuration files 
+##
+if CONFIG_CHIP_NAME
+	config chip.h
+end
+
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_939
+                        device apic 0 on end
+                end
+        end
+
+       device pci_domain 0 on
+               chip northbridge/amd/amdk8 #mc0
+                       device pci 18.0 on #  northbridge
+                               #  devices on link 0, link 0 == LDT 0
+                               chip southbridge/via/vt8237r
+					#both IDE channels
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+					#both cables are 80pin
+					register "ide0_80pin_cable" = "1"
+					register "ide1_80pin_cable" = "1"
+					#enables the functions of SB
+					register "fn_ctrl_lo" = "0"
+					register "fn_ctrl_hi" = "0xad"
+					
+                                       device pci 0.0 on end   # HT
+                                       device pci f.1 on end   # IDE
+                                       device pci 11.0 on # LPC
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+
+                                               chip superio/winbond/w83627ehg
+                                                       device pnp 2e.0 on #  Floppy
+                                                               io 0x60 = 0x3f0
+                                                               irq 0x70 = 6
+                                                               drq 0x74 = 2
+                                                       end
+                                                       device pnp 2e.1 on #  Parallel Port
+                                                               io 0x60 = 0x378
+                                                               irq 0x70 = 7
+                                                               drq 0x74 = 3
+                                                       end
+                                                       device pnp 2e.2 on #  Com1
+                                                               io 0x60 = 0x3f8
+                                                               irq 0x70 = 4
+                                                       end
+                                                       device pnp 2e.3 off #  Com2
+                                                               io 0x60 = 0x2f8
+                                                               irq 0x70 = 3
+                                                       end
+                                                       device pnp 2e.5 off #keyb OFF
+                                                       end
+                                                       device pnp 2e.6 off #  SERIAL_FLASH
+                                                               io 0x60 = 0x100
+                                                       end
+                                                       device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                                                              # io 0x60 = 0x220
+                                                              # io 0x62 = 0x300
+                                                              # irq 0x70 = a
+                                                       end
+                                                       device pnp 2e.8 off end #  WDTO_PLED
+                                                       device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5 0x30 0x9
+										#GPIO 5 and 2 active
+								#0xe0 = de
+								#0xe1 = 01
+								#0xe2 = 00
+								#0xe3 = 03
+								#0xe4 = a4
+								#0xe5 = 00
+
+                                                       device pnp 2e.a off end #  ACPI
+                                                       device pnp 2e.b on #  HW Monitor
+                                                               io 0x60 = 0x290
+                                                               irq 0x70 = 0
+                                                       end
+                                               end #end SIO
+                                       end #end 11
+
+                                       device pci 12.0 off end # VIA LAN is disabled, Asus used other chip
+                               end
+
+                               chip southbridge/via/k8t890
+				end
+
+                       end #  device pci 18.0
+                       device pci 18.1 on end
+                       device pci 18.2 on end
+                       device pci 18.3 on end
+               end #mc0
+
+       end # pci_domain
+
+end # root_complex

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,313 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License v2 as published by
+## the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+##uses USE_OPTION_TABLE
+##uses CONFIG_LB_MEM_TOPK
+
+uses HAVE_ACPI_TABLES
+
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+#bx_b005+
+uses SB_HT_CHAIN_ON_BUS0
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+#512K bytes
+default ROM_SIZE=512 * 1024
+
+#1M bytes
+#bx- default ROM_SIZE=1024 * 1024
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#256K
+default FALLBACK_SIZE=256 * 1024
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=0
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=0
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=0
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_PHYSICAL_CPUS=1
+default CONFIG_LOGICAL_CPUS=1
+
+#acpi
+default HAVE_ACPI_TABLES=1
+
+#CHIP_NAME ?
+#default CONFIG_CHIP_NAME=1
+
+#1G memory hole
+#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0
+
+#make the SB HT chain on bus 0, default is not (0)
+#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
+
+##bx_b005+ make the SB HT chain on bus 0
+default SB_HT_CHAIN_ON_BUS0=1
+
+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#VGA
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcc000
+default DCACHE_RAM_SIZE=0x4000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
+
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="A8V-E SE"
+default MAINBOARD_VENDOR="ASUS"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1043
+#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 64 * 1024
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE= 8 * 1024
+
+##
+## Use a small 256K heap
+##
+default HEAP_SIZE=256 * 1024
+
+#more 1M for pgtbl
+##default CONFIG_LB_MEM_TOPK=2048
+
+##
+## Only use the option table in a normal image
+##
+##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/acpi_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/acpi_tables.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/acpi_tables.c	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ * written by Stefan Reinauer <stepan at openbios.org>
+ * ACPI FADT, FACS, and DSDT table support added by 
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan at openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9 at btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+
+#include <../../../southbridge/via/vt8237r/vt8237r.h>
+#include <../../../southbridge/via/k8t890/k8t890.h>
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	struct resource *res;
+	dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
+	if (!dev)
+		return current;
+
+	res = find_resource(dev, K8T890_MMCONFIG_MBAR);
+	if (res) {
+		current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
+				current, res->base, 0x0, 0x0, 0xff);
+	}
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	unsigned int gsi_base = 0x18;
+
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB IOAPIC */
+	current +=
+	    acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, VT8237R_APIC_ID,
+				    VT8237R_APIC_BASE, 0);
+
+	/* Write NB IOAPIC */
+	current +=
+	    acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, K8T890_APIC_ID,
+				    K8T890_APIC_BASE, gsi_base);
+	/* IRQ9 ACPI active low */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+	/* IRQ0 -> APIC IRQ2 */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0x0);	
+
+	/* create all subtables for processors */
+	current =
+	    acpi_create_madt_lapic_nmis(current,
+					MP_IRQ_TRIGGER_EDGE |
+					MP_IRQ_POLARITY_HIGH, 1);
+
+	return current;
+}
+
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_srat_t *srat;
+	acpi_rsdt_t *rsdt;
+	acpi_mcfg_t *mcfg;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+
+	/* Align ACPI tables to 16byte */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk_debug("ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	current += ((acpi_header_t *) AmlCode)->length;
+	memcpy((void *) dsdt, (void *) AmlCode,
+	       ((acpi_header_t *) AmlCode)->length);
+	dsdt->checksum = 0;	// don't trust intel iasl compiler to get this right
+	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
+	printk_debug("ACPI:     * DSDT @ %08x Length %x\n", dsdt,
+		     dsdt->length);
+	printk_debug("ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdt, fadt);
+
+	printk_debug("ACPI:    * HPET\n");
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdt, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk_debug("ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdt, madt);
+
+	printk_debug("ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdt, mcfg);
+
+	/* SRAT */
+	printk_debug("ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdt, srat);
+
+	printk_info("ACPI: done.\n");
+	return current;
+}

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,331 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz> 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+unsigned int get_sbdn(unsigned bus);
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 1
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+//#define DEBUG_SMBUS 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+
+#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
+#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#define K8_4RANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#include "southbridge/via/k8t890/k8t890_early_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+
+void activate_spd_rom(const struct mem_controller *ctrl)
+{
+
+}
+
+void hard_reset(void)
+{
+	print_info("NO HARD RESET  FIX ME!\n");
+}
+
+void soft_reset(void)
+{
+	uint8_t tmp;
+	set_bios_reset();
+	print_debug("soft reset \r\n");
+
+	/* PCI reset */
+	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
+	tmp |= 0x01;
+	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+
+	while (1) {
+		/* daisy daisy ... */
+		hlt();
+	}
+}
+
+unsigned int get_sbdn(unsigned bus)
+{
+	device_t dev;
+
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+					PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
+	return (dev >> 15) & 0x1f;
+}
+
+#if USE_FALLBACK_IMAGE == 1
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+//        unsigned last_boot_normal_x = last_boot_normal();
+//FIXME
+	unsigned last_boot_normal_x = 1;
+	u8 reg;
+
+	pnp_enter_ext_func_mode(SERIAL_DEV);
+	reg = pnp_read_config(SERIAL_DEV, 0x24);
+	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));	/* we have 24MHz input */
+
+	reg = pnp_read_config(SERIAL_DEV, 0x2A);
+	pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1));	/* we have GPIO for KB/MS PIN */
+
+	reg = pnp_read_config(SERIAL_DEV, 0x2C);
+	pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0));	/* we have all RESTOUT and even some reserved bits too */
+
+	pnp_exit_ext_func_mode(SERIAL_DEV);
+
+	pnp_enter_ext_func_mode(GPIO_DEV);
+	pnp_set_logical_device(GPIO_DEV);
+	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	// 1101110  0=output 1=input
+	pnp_write_config(GPIO_DEV, 0xe1, 0x1);	//set output val
+	pnp_write_config(GPIO_DEV, 0xe2, 0x0);	//no inversion
+	pnp_write_config(GPIO_DEV, 0xe3, 0x3);	//0000 0011 0=output 1=input
+	pnp_write_config(GPIO_DEV, 0xe4, 0xa4);	//set output val
+	pnp_write_config(GPIO_DEV, 0xe5, 0x0);	//no inversion
+	pnp_write_config(GPIO_DEV, 0x30, 0x9);	//Enable GPIO 2 & GPIO 5
+	pnp_exit_ext_func_mode(GPIO_DEV);
+
+
+	w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	print_info("now booting... fallback\r\n");
+
+	/* Is this a cpu only reset? or Is this a secondary cpu? */
+	if ((cpu_init_detectedx) || (!boot_cpu())) {
+		if (last_boot_normal_x) {
+			goto normal_image;
+		} else {
+			goto fallback_image;
+		}
+	}
+
+	/* Nothing special needs to be done to find bus 0 */
+	/* Allow the HT devices to be found */
+
+	enumerate_ht_chain();
+
+	/* Is this a deliberate reset by the bios */
+	if (bios_reset_detected() && last_boot_normal_x) {
+		goto normal_image;
+	}
+	/* This is the primary cpu how should I boot? */
+	else if (do_normal_boot()) {
+		goto normal_image;
+	} else {
+		goto fallback_image;
+	}
+      normal_image:
+	//print_info("JMP normal image\r\n");
+
+	__asm__ volatile ("jmp __normal_image":	/* outputs */
+			  :"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
+	    );
+
+      fallback_image:
+	;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist,
+		       unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);
+#endif
+	real_main(bist, cpu_init_detectedx);
+
+}
+
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr[] = {
+		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
+		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
+		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+#endif
+	};
+	unsigned bsp_apicid = 0;
+	int needs_reset = 0;
+	struct sys_info *sysinfo =
+	    (DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
+	     DCACHE_RAM_GLOBAL_VAR_SIZE);
+	char *p;
+	u8 reg;
+
+	pnp_enter_ext_func_mode(SERIAL_DEV);
+	reg = pnp_read_config(SERIAL_DEV, 0x24);
+	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));	/* we have 24MHz input */
+
+	reg = pnp_read_config(SERIAL_DEV, 0x2A);
+	pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1));	/* we have GPIO for KB/MS PIN */
+
+	reg = pnp_read_config(SERIAL_DEV, 0x2C);
+	pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0));	/* we have all RESTOUT and even some reserved bits too */
+
+	pnp_exit_ext_func_mode(SERIAL_DEV);
+
+	pnp_enter_ext_func_mode(GPIO_DEV);
+	pnp_set_logical_device(GPIO_DEV);
+	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	// 1101110  0=output 1=input
+	pnp_write_config(GPIO_DEV, 0xe1, 0x1);	//set output val
+	pnp_write_config(GPIO_DEV, 0xe2, 0x0);	//no inversion
+	pnp_write_config(GPIO_DEV, 0xe3, 0x3);	//0000 0011 0=output 1=input
+	pnp_write_config(GPIO_DEV, 0xe4, 0xa4);	//set output val
+	//0x10 seems to control something with SGD VIA
+
+	pnp_write_config(GPIO_DEV, 0xe5, 0x0);	//no inversion
+	pnp_write_config(GPIO_DEV, 0x30, 0x9);	//Enable GPIO 2 & GPIO 5
+	pnp_exit_ext_func_mode(GPIO_DEV);
+
+
+	w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	print_info("now booting... real_main\r\n");
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+	}
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+	setup_default_resource_map();
+	setup_coherent_ht_domain();
+	wait_all_core0_started();
+	print_info("now booting... Core0 started\r\n");
+
+#if CONFIG_LOGICAL_CPUS==1
+	// It is said that we should start core1 after all core0 launched
+	start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+	init_timer();
+	ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn
+	needs_reset = optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+	/* Fixme it assumes that 1000MHz LDT is selected. */
+	needs_reset |= k8t890_early_setup_car(16, 0x6);
+
+	if (needs_reset) {
+		print_debug("ht reset -\r\n");
+		soft_reset();
+	}
+	/* stop the APs so we can start them later in init */
+        allow_all_aps_stop(bsp_apicid);
+	/* It's the time to set ctrl now; */
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	enable_smbus();
+	memreset_setup();
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+	post_cache_as_ram();
+}
+

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/chip.h	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/chip.h	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_asus_a8v_e_se_ops;
+
+struct mainboard_asus_a8v_e_se_config {
+     
+};

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cmos.layout
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cmos.layout	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/cmos.layout	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/dsdt.asl
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/dsdt.asl	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/dsdt.asl	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,245 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Minimalist ACPI DSDT table for EPIA-M / MII
+ * (C) Copyright 2004 Nick Barker <Nick.Barker9 at btinternet.com>
+ *
+ * (C) Copyright 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * ISA portions taken from QEMU acpi-dsdt.dsl  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+
+
+
+
+	/*  
+	 * Define the main processor
+	 */
+	Scope (\_PR)
+	{
+		Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
+		Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
+	}
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 * any others would involve declaring the wake up methods
+	 */
+	Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
+
+	/* Root of the bus hierarchy */
+	Scope (\_SB)
+    	{
+		/* top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+			
+			/* PCI Routing Table */
+			//aaa
+			Name (_PRT, Package () {
+	                    Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, //slot 0xB
+        	            Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
+                	    Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
+	                    Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
+        	            Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, //Slot 0xC
+                	    Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
+                	    Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
+			    Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
+        	            Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, //Slot 0xD
+                	    Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
+                	    Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
+			    Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
+        	            Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, //0xf SATA IRQ 20
+                	    Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, //0xf NAtive IDE IRQ 20
+        	            Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, //USB routing
+                	    Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
+                	    Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
+			    Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
+			    Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, //AC97 MC97
+        	            Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, //PCIE16 bridge IRQ27
+                	    Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+                	    Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
+			    Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
+        	            Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, //PCIE bridge IRQ31
+                	    Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, //IRQ36
+                	    Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, //IRQ39
+			    Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } //IRQ43
+            		})
+
+		
+		Device (PEGG)
+		{
+			Name (_ADR, 0x00020000)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x02)
+			
+			Name (_PRT, Package () {
+	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, //PCIE IRQ24-IRQ27
+        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
+                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
+	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
+			})	
+		} //end of PCIEG
+
+		Device (PEX0)
+		{
+			Name (_ADR, 0x00030000)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x03)
+			
+			Name (_PRT, Package () {
+	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, //PCIE IRQ28-IRQ31
+        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
+                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
+	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
+			})	
+		} //end of PEX0
+
+		Device (PEX1)
+		{
+			Name (_ADR, 0x00030001)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x04)
+			
+			Name (_PRT, Package () {
+	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, //PCIE IRQ32-IRQ35
+        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
+                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
+	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
+			})	
+		} //end f PEX1
+
+		Device (PEX2)
+		{
+			Name (_ADR, 0x00030002)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x05)
+			
+			Name (_PRT, Package () {
+	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, //PCIE IRQ36-IRQ39
+        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
+                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
+	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
+			})	
+		} //end f PEX2
+
+		Device (PEX3)
+		{
+			Name (_ADR, 0x00030003)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x06)
+			
+			Name (_PRT, Package () {
+	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, //PCIE IRQ40-IRQ43
+        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
+                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
+	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
+			})	
+		} //end f PEX3
+
+        Device (ISA) {
+            Name (_ADR, 0x00110000)
+        
+            /* Keyboard seems to be important for WinXP install */
+            Device (KBD)
+            {
+                Name (_HID, EisaId ("PNP0303"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+
+                Method (_CRS, 0, NotSerialized)
+                {
+                     Name (TMP, ResourceTemplate ()
+                     {
+                    IO (Decode16,
+                        0x0060,             // Address Range Minimum
+                        0x0060,             // Address Range Maximum
+                        0x01,               // Address Alignment
+                        0x01,               // Address Length
+                        )
+                    IO (Decode16,
+                        0x0064,             // Address Range Minimum
+                        0x0064,             // Address Range Maximum
+                        0x01,               // Address Alignment
+                        0x01,               // Address Length
+                        )
+                    IRQNoFlags ()
+                        {1}
+                    })
+                    Return (TMP)
+                }
+            }
+
+	    /* PS/2 mouse */
+            Device (MOU) 
+            {
+                Name (_HID, EisaId ("PNP0F13"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Name (TMP, ResourceTemplate ()
+                    {
+                         IRQNoFlags () {12}
+                    })
+                    Return (TMP)
+                }
+            }
+
+	    /* PS/2 floppy controller */
+	    Device (FDC0)
+	    {
+	        Name (_HID, EisaId ("PNP0700"))
+		Method (_STA, 0, NotSerialized)
+		{
+		    Return (0x0F)
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+                        IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+                        IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+                        IRQNoFlags () {6}
+                        DMA (Compatibility, NotBusMaster, Transfer8) {2}
+                    })
+		    Return (BUF0)
+		}
+	    } //FD END
+
+        } //ISA END
+
+	} // End of PCI0
+		
+		
+	} // End of _SB
+
+} // End of Definition Block
+

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/fadt.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/fadt.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/fadt.c	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,151 @@
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ * (C) Copyright 2004 Nick Barker <nick.barker9 at btinternet.com>
+ * (C) Copyright 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <../../../southbridge/via/vt8237r/vt8237r.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, "LXBIOS", 6);
+	memcpy(header->oem_table_id, "LXBACPI ", 8);
+	memcpy(header->asl_compiler_id, "IASL", 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = facs;
+	fadt->dsdt = dsdt;
+	fadt->preferred_pm_profile = 0;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8;
+	fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20;
+	fadt->gpe1_blk = 0x0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 4;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 90;
+	fadt->p_lvl3_lat = 900;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 0;
+	fadt->duty_width = 1;	//??
+	fadt->day_alrm = 0x7d;
+	fadt->mon_alrm = 0x7e;
+	fadt->century = 0x32;
+	/* fixme 5 - 10 */
+	fadt->iapc_boot_arch = 0x1;
+	/* fixme */
+	fadt->flags = 0x4a5;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 4;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = VT8237R_ACPI_IO_BASE;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 2;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = VT8237R_ACPI_IO_BASE + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = 0x0;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 4;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = VT8237R_ACPI_IO_BASE + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 0;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = VT8237R_ACPI_IO_BASE + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mainboard.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mainboard.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mainboard.c	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_asus_a8v_e_se_ops = {
+	CHIP_NAME("ASUS A8V-E SE Mainboard")
+};
+#endif

Added: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mptable.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/mptable.c	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/smp/mpspec.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <../../../southbridge/via/vt8237r/vt8237r.h>
+#include <../../../southbridge/via/k8t890/k8t890.h>
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "LNXB    ";
+        static const char productid[12] = "A8V-E SE    ";
+        struct mp_config_table *mc;
+	unsigned int conforms = 0;
+	int bus_isa = 42;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+
+/*Bus:		Bus ID	Type*/
+	smp_write_bus(mc, 0, "PCI   ");
+	smp_write_bus(mc, 1, "PCI   ");
+	smp_write_bus(mc, 2, "PCI   ");
+	smp_write_bus(mc, 3, "PCI   ");
+	smp_write_bus(mc, 4, "PCI   ");
+	smp_write_bus(mc, 5, "PCI   ");
+	smp_write_bus(mc, 6, "PCI   ");
+	smp_write_bus(mc, bus_isa, "ISA   ");
+/*I/O APICs:	APIC ID	Version	State		Address*/
+
+	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
+	smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+
+
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, VT8237R_APIC_ID, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, VT8237R_APIC_ID, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, VT8237R_APIC_ID, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, VT8237R_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, VT8237R_APIC_ID, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, VT8237R_APIC_ID, 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, VT8237R_APIC_ID, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, VT8237R_APIC_ID, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, VT8237R_APIC_ID, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, VT8237R_APIC_ID, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, VT8237R_APIC_ID, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, VT8237R_APIC_ID, 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, VT8237R_APIC_ID, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, VT8237R_APIC_ID, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, VT8237R_APIC_ID, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, VT8237R_APIC_ID, 0xf);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb	                        (rev 0)
+++ trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb	2007-11-02 23:17:57 UTC (rev 2934)
@@ -0,0 +1,62 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License v2 as published by
+## the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target a8v-e_se
+mainboard asus/a8v-e_se
+
+romimage "normal"
+#       48K for SCSI FW
+#        option ROM_SIZE = 475136
+#       option ROM_SIZE = 512*1024-36*1024
+      option ROM_SIZE = 512*1024
+#       48K for SCSI FW and 48K for ATI ROM
+#       option ROM_SIZE = 425984
+#       64K for Etherboot
+#        option ROM_SIZE = 458752
+#        option USE_FAILOVER_IMAGE=0
+	option USE_FALLBACK_IMAGE=0
+
+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x18800
+       option ROM_IMAGE_SIZE=0x20000
+#      option ROM_IMAGE_SIZE=0x15800
+       option XIP_ROM_SIZE=0x40000
+       option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+
+# give path to filo.elf if needed
+       payload filo.elf
+end
+
+romimage "fallback"
+       option USE_FALLBACK_IMAGE=1
+#       option USE_FAILOVER_IMAGE=0
+
+#      option ROM_IMAGE_SIZE=0x13800
+#      option ROM_IMAGE_SIZE=0x19800
+       option ROM_IMAGE_SIZE=0x20000
+#      option ROM_IMAGE_SIZE=0x15800
+       option XIP_ROM_SIZE=0x40000
+       option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+
+# give path to filo.elf if needed
+
+       payload filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"




From stepan at coresystems.de  Sat Nov  3 00:18:56 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 3 Nov 2007 00:18:56 +0100
Subject: [LinuxBIOS] [PATCH] Add support for the Asus A8V-E
	SE	motherboard
In-Reply-To: <472B96F2.6030709@assembler.cz>
References: <4723883C.8010908@assembler.cz> <20071030141811.GG23532@greenwood>
	<47279B0A.9050602@assembler.cz>
	<20071031104008.GB11911@coresystems.de>
	<472B96F2.6030709@assembler.cz>
Message-ID: <20071102231856.GA24858@coresystems.de>

* Rudolf Marek <r.marek at assembler.cz> [071102 22:30]:
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
>
> I will repost some patches which have not yet been accepted, so my SVN tree 
> have no diffs.
>
> Rudolf

> Index: src/mainboard/asus/a8v-e_se/fadt.c

r2934.



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From svn at openbios.org  Sat Nov  3 00:27:12 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  3 Nov 2007 00:27:12 +0100
Subject: [LinuxBIOS] r2935 - trunk/LinuxBIOSv2/src/northbridge/amd/amdk8
Message-ID: <mailman.829.1355071196.16123.coreboot@coreboot.org>

Author: mjones
Date: 2007-11-03 00:27:12 +0100 (Sat, 03 Nov 2007)
New Revision: 2935

Modified:
   trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h
   trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c
Log:
This patch changes the "if else" style of parameter matching to table and also changes the rdpreamble parameter, which will cause that more then one DIMM will work for 939 motherboard.


Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h	2007-11-02 23:17:57 UTC (rev 2934)
+++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/amdk8.h	2007-11-02 23:27:12 UTC (rev 2935)
@@ -134,7 +134,9 @@
 #define	 DCL_D_DRV	   (1<<1)
 #define	 DCL_QFC_EN	   (1<<2)
 #define	 DCL_DisDqsHys	   (1<<3)
+#define	 DCL_Burst2Opt     (1<<5)
 #define	 DCL_DramInit	   (1<<8)
+#define	 DCL_DualDIMMen    (1<<9)
 #define	 DCL_DramEnable	   (1<<10)
 #define	 DCL_MemClrStatus  (1<<11)
 #define	 DCL_ESR	   (1<<12)
@@ -147,7 +149,8 @@
 #define	 DCL_DisInRcvrs    (1<<24)
 #define	 DCL_BypMax_SHIFT  25
 #define	 DCL_En2T          (1<<28)
-
+#define	 DCL_UpperCSMap    (1<<29)
+	
 #define DRAM_CONFIG_HIGH   0x94
 #define	 DCH_ASYNC_LAT_SHIFT  0
 #define	 DCH_ASYNC_LAT_MASK   0xf

Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c	2007-11-02 23:17:57 UTC (rev 2934)
+++ trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c	2007-11-02 23:27:12 UTC (rev 2935)
@@ -1177,6 +1177,7 @@
 	int i;
 	int registered;
 	int unbuffered;
+	int has_dualch = is_opteron(ctrl);
 	uint32_t dcl;
 	unbuffered = 0;
 	registered = 0;
@@ -1201,17 +1202,22 @@
 	if (unbuffered && registered) {
 		die("Mixed buffered and registered dimms not supported");
 	}
-#if 1
-	// yhlu debug: Athlon64 939 can do dual channel, but it uses unbuffered DIMMs
-	if (unbuffered && is_opteron(ctrl)) {
-		die("Unbuffered Dimms not supported on Opteron");
-	}
-#endif
 
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_UnBufDimm;
 	if (unbuffered) {
-		dcl |= DCL_UnBufDimm;
+		if ((has_dualch) && (!is_cpu_pre_d0())) {
+			dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
+			
+			/* set DCL_En2T if you have non-equal DDR mem types! */
+			
+			if ((cpuid_eax(1) & 0x30) == 0x30) {
+				/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
+				dcl |= DCL_UpperCSMap;
+			}
+		} else {
+			dcl |= DCL_UnBufDimm;
+		}
 	}
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 #if 0
@@ -1333,6 +1339,9 @@
 	uint32_t dch_memclk;
 	uint16_t dch_tref4k, dch_tref8k;
 	uint8_t	 dtl_twr;
+	uint8_t	 dtl_twtr;
+	uint8_t  dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */
+ 	uint8_t	 rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
 	char name[9];
 };
 
@@ -1349,6 +1358,9 @@
 			.dch_tref4k = DTH_TREF_100MHZ_4K,
 			.dch_tref8k = DTH_TREF_100MHZ_8K,
 			.dtl_twr    = 2,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
 		},
 		{
 			.name	    = "133Mhz\r\n",
@@ -1360,6 +1372,9 @@
 			.dch_tref4k = DTH_TREF_133MHZ_4K,
 			.dch_tref8k = DTH_TREF_133MHZ_8K,
 			.dtl_twr    = 2,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
 		},
 		{
 			.name	    = "166Mhz\r\n",
@@ -1371,6 +1386,9 @@
 			.dch_tref4k = DTH_TREF_166MHZ_4K,
 			.dch_tref8k = DTH_TREF_166MHZ_8K,
 			.dtl_twr    = 3,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }},
+			.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
 		},
 		{
 			.name	    = "200Mhz\r\n",
@@ -1382,6 +1400,9 @@
 			.dch_tref4k = DTH_TREF_200MHZ_4K,
 			.dch_tref8k = DTH_TREF_200MHZ_8K,
 			.dtl_twr    = 3,
+			.dtl_twtr   = 2,
+			.dtl_trwt   = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) }
 		},
 		{
 			.cycle_time = 0x00,
@@ -1423,8 +1444,8 @@
 		[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
 	};
 
-
 	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
 	bios_cycle_time = min_cycle_times[
 		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
@@ -1877,75 +1898,47 @@
 static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	uint32_t dth;
-	unsigned clocks;
-	clocks = 1; /* AMD says hard code this */
+
 	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
-	dth |= ((clocks - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
+	dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
 	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
 }
 
 static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	uint32_t dth, dtl;
-	unsigned divisor;
 	unsigned latency;
 	unsigned clocks;
+	int lat, mtype;
 
 	clocks = 0;
 	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
 	latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
-	divisor = param->divisor;
 
 	if (is_opteron(ctrl)) {
-		if (latency == DTL_CL_2) {
-			if (divisor == ((6 << 0) + 0)) {
-				/* 166Mhz */
-				clocks = 3;
-			}
-			else if (divisor > ((6 << 0)+0)) {
-				/* 100Mhz && 133Mhz */
-				clocks = 2;
-			}
-		}
-		else if (latency == DTL_CL_2_5) {
-			clocks = 3;
-		}
-		else if (latency == DTL_CL_3) {
-			if (divisor == ((6 << 0)+0)) {
-				/* 166Mhz */
-				clocks = 4;
-			}
-			else if (divisor > ((6 << 0)+0)) {
-				/* 100Mhz && 133Mhz */
-				clocks = 3;
-			}
-		}
+		mtype = 0; /* dual channel */
+	} else if (is_registered(ctrl)) {
+		mtype = 1; /* registered 64bit interface */
+	} else {
+		mtype = 2; /* unbuffered 64bit interface */
 	}
-	else /* Athlon64 */ {
-		if (is_registered(ctrl)) {
-			if (latency == DTL_CL_2) {
-				clocks = 2;
-			}
-			else if (latency == DTL_CL_2_5) {
-				clocks = 3;
-			}
-			else if (latency == DTL_CL_3) {
-				clocks = 3;
-			}
-		}
-		else /* Unbuffered */{
-			if (latency == DTL_CL_2) {
-				clocks = 3;
-			}
-			else if (latency == DTL_CL_2_5) {
-				clocks = 4;
-			}
-			else if (latency == DTL_CL_3) {
-				clocks = 4;
-			}
-		}
+
+	switch (latency) {
+		case DTL_CL_2:
+			lat = 0;
+			break;
+		case DTL_CL_2_5:
+			lat = 1;
+			break;
+		case DTL_CL_3:
+			lat = 2;
+			break;
+		default:
+			die("Unknown LAT for Trwt");
 	}
+
+	clocks = param->dtl_trwt[lat][mtype];
 	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
 		die("Unknown Trwt\r\n");
 	}
@@ -1977,83 +1970,38 @@
 static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	uint32_t dch;
-	unsigned divisor;
 	unsigned rdpreamble;
-	divisor = param->divisor;
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
-	rdpreamble = 0;
-	if (is_registered(ctrl)) {
-		if (divisor == ((10 << 1)+0)) {
-			/* 100Mhz, 9ns */
-			rdpreamble = ((9 << 1)+ 0);
+	int slots, i;
+
+	slots = 0;
+
+	for(i = 0; i < 4; i++) {
+		if (ctrl->channel0[i]) {
+			slots += 1;
 		}
-		else if (divisor == ((7 << 1)+1)) {
-			/* 133Mhz, 8ns */
-			rdpreamble = ((8 << 1)+0);
-		}
-		else if (divisor == ((6 << 1)+0)) {
-			/* 166Mhz, 7.5ns */
-			rdpreamble = ((7 << 1)+1);
-		}
-		else if (divisor == ((5 << 1)+0)) {
-			/* 200Mhz,  7ns */
-			rdpreamble = ((7 << 1)+0);
-		}
 	}
-	else {
-		int slots;
-		int i;
-		slots = 0;
-		for(i = 0; i < 4; i++) {
-			if (ctrl->channel0[i]) {
-				slots += 1;
-			}
-		}
-		if (divisor == ((10 << 1)+0)) {
-			/* 100Mhz */
-			if (slots <= 2) {
-				/* 9ns */
-				rdpreamble = ((9 << 1)+0);
-			} else {
-				/* 14ns */
-				rdpreamble = ((14 << 1)+0);
-			}
-		}
-		else if (divisor == ((7 << 1)+1)) {
-			/* 133Mhz */
-			if (slots <= 2) {
-				/* 7ns */
-				rdpreamble = ((7 << 1)+0);
-			} else {
-				/* 11 ns */
-				rdpreamble = ((11 << 1)+0);
-			}
-		}
-		else if (divisor == ((6 << 1)+0)) {
-			/* 166Mhz */
-			if (slots <= 2) {
-				/* 6ns */
-				rdpreamble = ((7 << 1)+0);
-			} else {
-				/* 9ns */
-				rdpreamble = ((9 << 1)+0);
-			}
-		}
-		else if (divisor == ((5 << 1)+0)) {
-			/* 200Mhz */
-			if (slots <= 2) {
-				/* 5ns */
-				rdpreamble = ((5 << 1)+0);
-			} else {
-				/* 7ns */
-				rdpreamble = ((7 << 1)+0);
-			}
-		}
+
+	/* map to index to param.rdpreamble array */
+	if (is_registered(ctrl)) {
+		i = 0;
+	} else if (slots < 3) {
+		i = 1;
+	} else if (slots == 3) {
+		i = 2;
+	} else if (slots == 4) {
+		i = 3;
+	} else {
+		die("Unknown rdpreamble for this nr of slots");
 	}
+
+	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
+	rdpreamble = param->rdpreamble[i];
+
 	if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
 		die("Unknown rdpreamble");
 	}
+
 	dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }




From marc.jones at amd.com  Sat Nov  3 00:27:37 2007
From: marc.jones at amd.com (Marc Jones)
Date: Fri, 02 Nov 2007 17:27:37 -0600
Subject: [LinuxBIOS] Fix the AMD K8 DDR init (resend)
In-Reply-To: <20071102225414.GF20979@cosmic.amd.com>
References: <472BA591.1020806@assembler.cz>
	<20071102225414.GF20979@cosmic.amd.com>
Message-ID: <472BB269.2070709@amd.com>



Jordan Crouse wrote:
> On 02/11/07 23:32 +0100, Rudolf Marek wrote:
>> Hello,
>>
>> This patch changes the "if else" style of parameter matching to table and 
>> also
>> changes the rdpreamble parameter, which will cause that more then one DIMM 
>> will
>> work for 939 motherboard. It seems that this code was written with some 
>> very early version of the specs.
>>
>> What about the 2T support? Now it can be triggered with the code change 
>> only.
>>
>> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
> 
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>
> 
> Tested it here - looks great.  Thank you very much!  This is
> great stuff.
> 
> Jordan
> 
> 
> 

Committed revision 2935.

-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From info at coresystems.de  Sat Nov  3 00:57:48 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sat, 03 Nov 2007 00:57:48 +0100
Subject: [LinuxBIOS] r2934 build service
Message-ID: <E1Io6Oa-0005U9-5q@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2934 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Asus A8V-E-SE support from Rudolf Marek


Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Configuration of asus:a8v-e_se is still broken


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From info at coresystems.de  Sat Nov  3 01:46:53 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sat, 03 Nov 2007 01:46:53 +0100
Subject: [LinuxBIOS] r2935 build service
Message-ID: <E1Io7A5-0004nM-H1@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "mjones" checked in revision 2935 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
This patch changes the "if else" style of parameter matching to table and also changes the rdpreamble parameter, which will cause that more then one DIMM will work for 939 motherboard.


Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Build Log:
Configuration of asus:a8v-e_se is still broken


If something broke during this checkin please be a pain 
in mjones's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Sat Nov  3 02:07:58 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Nov 2007 02:07:58 +0100
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <009201c81d05$27559020$0200a8c0@sis.com.tw>
References: <001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>
	<20071004025851.GA32267@greenwood>
	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
	<009201c81d05$27559020$0200a8c0@sis.com.tw>
Message-ID: <472BC9EE.1010200@gmx.net>

Dear Morgan,

this patch is against latest svn. Please review.

Thanks,
Carl-Daniel

Change one PCI vendor ID from Nvidia to SiS and remove some dead code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

--- 

Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	(Arbeitskopie)
@@ -23,14 +23,12 @@
 {
 	device_t dev;
 
-	/* Find the device.
-	 */
+	/* Find the device. */
 	dev = pci_locate_device_on_bus(
-		PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_SIS_SIS966_HT),
+		PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_HT),
 		bus);
 
 	return (dev>>15) & 0x1f;
-
 }
 
 static void hard_reset(void)
@@ -41,6 +39,7 @@
 	outb(0x0a, 0x0cf9);
 	outb(0x0e, 0x0cf9);
 }
+
 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
 /* default value for sis966 is good */
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	(Arbeitskopie)
@@ -353,64 +353,6 @@
 print_debug("NIC_INIT:<----------\n");
 return;
 
-#define RegStationMgtInf	0x44
-#define PHY_RGMII	0x10000000
-
-	writel(PHY_RGMII, base + RegStationMgtInf);
-	conf = dev->chip_info;
-
-	if(conf->mac_eeprom_smbus != 0) {
-//	read MAC address from EEPROM at first
-
-		struct device *dev_eeprom;
-		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
-
-		if(dev_eeprom) {
-		//	if that is valid we will use that
-			unsigned char dat[6];
-			int status;
-			int i;
-			for(i=0;i<6;i++) {
-				status = smbus_read_byte(dev_eeprom, i);
-				if(status < 0) break;
-				dat[i] = status & 0xff;
-			}
-			if(status >= 0) {
-				mac_l = 0;
-				for(i=3;i>=0;i--) {
-					mac_l <<= 8;
-					mac_l += dat[i];
-				}
-				if(mac_l != 0xffffffff) {
-					mac_l += nic_index;
-					mac_h = 0;
-					for(i=5;i>=4;i--) {
-						mac_h <<= 8;
-						mac_h += dat[i];
-					}
-					eeprom_valid = 1;
-				}
-			}
-		}
-	}
-
-// if that is invalid we will read that from romstrap
-	if(!eeprom_valid) {
-		unsigned long mac_pos;
-		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
-		mac_l = readl(mac_pos) + nic_index; // overflow?
-		mac_h = readl(mac_pos + 4);
-
-	}
-
-// set that into NIC MMIO
-#define NvRegMacAddrA	0xA8
-#define NvRegMacAddrB	0xAC
-	writel(mac_l, base + NvRegMacAddrA);
-	writel(mac_h, base + NvRegMacAddrB);
-
-	nic_index++;
-
 #if CONFIG_PCI_ROM_RUN == 1
 	pci_dev_init(dev);// it will init option rom
 #endif
@@ -436,6 +378,7 @@
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
+
 static const struct pci_driver nic_driver __pci_driver = {
 	.ops	= &nic_ops,
 	.vendor	= PCI_VENDOR_ID_SIS,





From peter at stuge.se  Sat Nov  3 02:28:17 2007
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Nov 2007 02:28:17 +0100
Subject: [LinuxBIOS] Add support for a 64-bit target for Serengeti
	Cheetah
In-Reply-To: <13426df10711012142x505c18camab2ca2280e475246@mail.gmail.com>
References: <2831fecf0711010900w5847bd4cp3b022baa77f74faf@mail.gmail.com>
	<02d201c81ca5$437e4770$1223040a@chimp>
	<20071101165626.GC21220@cosmic.amd.com>
	<13426df10711012142x505c18camab2ca2280e475246@mail.gmail.com>
Message-ID: <20071103012817.21692.qmail@stuge.se>

On Thu, Nov 01, 2007 at 09:42:16PM -0700, ron minnich wrote:
> I am not sure what the future of buildroot will be.
> 
> So, I am happy that buildrom can do what it does.

I like Gentoo's catalyst for building systems. Granted it's geared
toward full-fledged systems, but there's no reason it can't be used
for small ones too. There's also crossdev for cross-compiling.


//Peter



From peter at stuge.se  Sat Nov  3 02:31:54 2007
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Nov 2007 02:31:54 +0100
Subject: [LinuxBIOS] secondary cpu question
In-Reply-To: <281846.60052.qm@web51611.mail.re2.yahoo.com>
References: <mailman.462.1193976196.23407.linuxbios@linuxbios.org>
	<281846.60052.qm@web51611.mail.re2.yahoo.com>
Message-ID: <20071103013154.22319.qmail@stuge.se>

On Thu, Nov 01, 2007 at 11:05:27PM -0700, Baski wrote:
> I want to run a small code, say, 'while(1){send a char to com1
> port}' on this second core and let the BSP load and run linux.

> the secondary eip is still valid.

I suppose if you exclude a memory area that the second core runs in
it could work. Make sure Linux does not trample over your code.


//Peter



From peter at stuge.se  Sat Nov  3 02:38:35 2007
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Nov 2007 02:38:35 +0100
Subject: [LinuxBIOS] r2930 - in trunk/LinuxBIOSv2:
	src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x
	targets/iwill targets/iwill/dk8x
Message-ID: <20071103013835.23805.qmail@stuge.se>

On Fri, Nov 02, 2007 at 01:54:49PM +0100, svn at openbios.org wrote:
> fix up iwill board compilation. Untested, trivial

Great! :) Lovely to see all boards build again.


From peter at stuge.se  Sat Nov  3 02:41:21 2007
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Nov 2007 02:41:21 +0100
Subject: [LinuxBIOS] r2933 - trunk/LinuxBIOSv2/src/southbridge/sis/sis966
Message-ID: <20071103014121.24661.qmail@stuge.se>

On Fri, Nov 02, 2007 at 06:05:04PM +0100, svn at openbios.org wrote:
> Log:
> remaining part of the patch.

But wtf was in it?

All of us remember right now, but that's not why we have commit
messages.

Sorry for bitching about this on a Friday night.


//Peter



From peter at stuge.se  Sat Nov  3 02:52:01 2007
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Nov 2007 02:52:01 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472B5EB1.6000100@gmail.com>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
	<20071102171555.GE25764@greenwood> <472B5EB1.6000100@gmail.com>
Message-ID: <20071103015201.26537.qmail@stuge.se>

On Fri, Nov 02, 2007 at 01:30:25PM -0400, Corey Osgood wrote:
> +void smbus_fixup(const struct mem_controller *ctrl)
> +{
> +	int i, ram_slots, current_slot = 0;
> +	u8 result = 0;
> +
> +	ram_slots = ARRAY_SIZE(ctrl->channel0);
> +	if (!ram_slots) {
> +		print_err("smbus_fixup thinks there are no ram slots!\r\n");
> +		return;
> +	}
> +	
> +	PRINT_DEBUG("Waiting for smbus to warm up");
> +		
> +	/* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for the
> +	 * ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
> +	 * vt8237r has only been seen on DDR and DDR2 based systems, so far */
> +	for(i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || 
> +			(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++)
> +	{
> +		if (current_slot > ram_slots) j = 0;

What is j here?


> +++ src/include/spd.h	(working copy)
> @@ -105,6 +105,7 @@
>  #define SPD_MEMORY_TYPE_SGRAM_DDR        6
>  #define SPD_MEMORY_TYPE_SDRAM_DDR        7
>  #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
> +#define SPD_MEMORY_TYPE_SDRAM_DDR3	 0xb

Looks like bad whitespace, but that's a separate patch.

Otherwise I'll ack. Can you commit?


//Peter



From peter at stuge.se  Sat Nov  3 03:05:34 2007
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Nov 2007 03:05:34 +0100
Subject: [LinuxBIOS] r2935 - trunk/LinuxBIOSv2/src/northbridge/amd/amdk8
Message-ID: <20071103020534.29623.qmail@stuge.se>

On Sat, Nov 03, 2007 at 12:27:12AM +0100, svn at openbios.org wrote:
> Log:
> This patch changes the "if else" style of parameter matching to
> table and also changes the rdpreamble parameter, which will cause
> that more then one DIMM will work for 939 motherboard.

\o/


> -		dcl |= DCL_UnBufDimm;
> +		if ((has_dualch) && (!is_cpu_pre_d0())) {
> +			dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
> +			
> +			/* set DCL_En2T if you have non-equal DDR mem types! */
> +			
> +			if ((cpuid_eax(1) & 0x30) == 0x30) {
> +				/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
> +				dcl |= DCL_UpperCSMap;
> +			}
> +		} else {
> +			dcl |= DCL_UnBufDimm;
> +		}

This isn't super neat, the else could be removed.


//Peter



From peter at stuge.se  Sat Nov  3 03:21:38 2007
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Nov 2007 03:21:38 +0100
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <009201c81d05$27559020$0200a8c0@sis.com.tw>
References: <13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
	<009201c81d05$27559020$0200a8c0@sis.com.tw>
Message-ID: <20071103022138.331.qmail@stuge.se>

Hi Morgan!


On Fri, Nov 02, 2007 at 12:02:06PM +0800, Morgan Tsai /SiS wrote:
> Here is the redone patch by TortoiseSVN, please try it again.

Thanks! I think most of these changes have been committed from your
previous patch already.


> The newest I have is 2925.

I don't know if you already have a lot of experience with SVN, but it
can merge your changes in your working copy with whatever changes
that have been committed already in the svn update command. Note that
it will never overwrite the changes you have made, only combine what
can be combined, and mark conflicts where changes can not be
combined.

If you do an update as the last step (and resolving any conflicts)
before generating a patch you have made sure that your patch is
against the latest revision.

Please do an update if there have already been changes made in the
repo that affect the same files as your patch.

Please confirm that you are subscribed to the mailing list by the
way? Then I will only post to the list from now on.


//Peter



From corey.osgood at gmail.com  Sat Nov  3 04:02:55 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 02 Nov 2007 23:02:55 -0400
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <20071103015201.26537.qmail@stuge.se>
References: <472ABD76.9020705@gmail.com>
	<472ABDA6.4000602@gmail.com>	<20071102155603.GA25764@greenwood>
	<472B52B4.9050801@gmail.com>	<20071102171555.GE25764@greenwood>
	<472B5EB1.6000100@gmail.com> <20071103015201.26537.qmail@stuge.se>
Message-ID: <472BE4DF.10809@gmail.com>

Peter Stuge wrote:
> On Fri, Nov 02, 2007 at 01:30:25PM -0400, Corey Osgood wrote:
>   
>> +void smbus_fixup(const struct mem_controller *ctrl)
>> +{
>> +	int i, ram_slots, current_slot = 0;
>> +	u8 result = 0;
>> +
>> +	ram_slots = ARRAY_SIZE(ctrl->channel0);
>> +	if (!ram_slots) {
>> +		print_err("smbus_fixup thinks there are no ram slots!\r\n");
>> +		return;
>> +	}
>> +	
>> +	PRINT_DEBUG("Waiting for smbus to warm up");
>> +		
>> +	/* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for the
>> +	 * ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
>> +	 * vt8237r has only been seen on DDR and DDR2 based systems, so far */
>> +	for(i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || 
>> +			(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++)
>> +	{
>> +		if (current_slot > ram_slots) j = 0;
>>     
>
> What is j here?
>   

Oops, should have been current_slot. I can fix it before commit.

>> +++ src/include/spd.h	(working copy)
>> @@ -105,6 +105,7 @@
>>  #define SPD_MEMORY_TYPE_SGRAM_DDR        6
>>  #define SPD_MEMORY_TYPE_SDRAM_DDR        7
>>  #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
>> +#define SPD_MEMORY_TYPE_SDRAM_DDR3	 0xb
>>     
>
> Looks like bad whitespace, but that's a separate patch.
>   

Weird, it looks fine in the file.

> Otherwise I'll ack. Can you commit?

Yep, just gotta figure out how. I'll hop on IRC if I have a problem.

-Corey



From russ at ashlandhome.net  Sat Nov  3 04:30:46 2007
From: russ at ashlandhome.net (Russell Whitaker)
Date: Fri, 2 Nov 2007 20:30:46 -0700 (PDT)
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472BE4DF.10809@gmail.com>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
	<20071102171555.GE25764@greenwood> <472B5EB1.6000100@gmail.com>
	<20071103015201.26537.qmail@stuge.se> <472BE4DF.10809@gmail.com>
Message-ID: <Pine.LNX.4.64.0711022024430.2756@bigred.russwhit.org>



On Fri, 2 Nov 2007, Corey Osgood wrote:

> Peter Stuge wrote:
>> On Fri, Nov 02, 2007 at 01:30:25PM -0400, Corey Osgood wrote:
>
>>> +++ src/include/spd.h	(working copy)
>>> @@ -105,6 +105,7 @@
>>>  #define SPD_MEMORY_TYPE_SGRAM_DDR        6
>>>  #define SPD_MEMORY_TYPE_SDRAM_DDR        7
>>>  #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
>>> +#define SPD_MEMORY_TYPE_SDRAM_DDR3	 0xb
>>>
>>
>> Looks like bad whitespace, but that's a separate patch.
>>
>
> Weird, it looks fine in the file.
>
The 4th #define line has a tab chr right after the DDR3
while the first 3 #define lines have only space chrs.

    Russ



From corey.osgood at gmail.com  Sat Nov  3 05:24:10 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 03 Nov 2007 00:24:10 -0400
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <Pine.LNX.4.64.0711022024430.2756@bigred.russwhit.org>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
	<20071102171555.GE25764@greenwood> <472B5EB1.6000100@gmail.com>
	<20071103015201.26537.qmail@stuge.se> <472BE4DF.10809@gmail.com>
	<Pine.LNX.4.64.0711022024430.2756@bigred.russwhit.org>
Message-ID: <472BF7EA.3060504@gmail.com>

Russell Whitaker wrote:
>
>
> On Fri, 2 Nov 2007, Corey Osgood wrote:
>
>> Peter Stuge wrote:
>>> On Fri, Nov 02, 2007 at 01:30:25PM -0400, Corey Osgood wrote:
>>
>>>> +++ src/include/spd.h    (working copy)
>>>> @@ -105,6 +105,7 @@
>>>>  #define SPD_MEMORY_TYPE_SGRAM_DDR        6
>>>>  #define SPD_MEMORY_TYPE_SDRAM_DDR        7
>>>>  #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
>>>> +#define SPD_MEMORY_TYPE_SDRAM_DDR3     0xb
>>>>
>>>
>>> Looks like bad whitespace, but that's a separate patch.
>>>
>>
>> Weird, it looks fine in the file.
>>
> The 4th #define line has a tab chr right after the DDR3
> while the first 3 #define lines have only space chrs.
>
>    Russ
>

Which explains it perfectly. Fixed now, thanks.

-Corey



From r.marek at assembler.cz  Sat Nov  3 09:18:18 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 03 Nov 2007 09:18:18 +0100
Subject: [LinuxBIOS] r2935 - trunk/LinuxBIOSv2/src/northbridge/amd/amdk8
In-Reply-To: <20071103020534.29623.qmail@stuge.se>
References: <20071103020534.29623.qmail@stuge.se>
Message-ID: <472C2ECA.6070004@assembler.cz>

> 
> This isn't super neat, the else could be removed.

It is prepared for the 2T logic...  but I agree the DCL_UnBufDimm; coulde be 
before the if...

Rudolf



From stepan at coresystems.de  Sat Nov  3 11:59:20 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 3 Nov 2007 11:59:20 +0100
Subject: [LinuxBIOS] r2933 -	trunk/LinuxBIOSv2/src/southbridge/sis/sis966
In-Reply-To: <20071103014121.24661.qmail@stuge.se>
References: <20071103014121.24661.qmail@stuge.se>
Message-ID: <20071103105920.GA7169@coresystems.de>

* Peter Stuge <peter at stuge.se> [071103 02:41]:
> On Fri, Nov 02, 2007 at 06:05:04PM +0100, svn at openbios.org wrote:
> > Log:
> > remaining part of the patch.
> 
> But wtf was in it?
> 
> All of us remember right now, but that's not why we have commit
> messages.

It's all whitespace cleanup.

> Sorry for bitching about this on a Friday night.

Sorry for not repasting the boot log of the previous patch. I should
have. 

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From stepan at coresystems.de  Sat Nov  3 12:43:45 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 3 Nov 2007 12:43:45 +0100
Subject: [LinuxBIOS] r2930 - in
	trunk/LinuxBIOSv2:	src/mainboard/iwill/dk8s2
	src/mainboard/iwill/dk8x targets/iwill	targets/iwill/dk8x
In-Reply-To: <20071103013835.23805.qmail@stuge.se>
References: <20071103013835.23805.qmail@stuge.se>
Message-ID: <20071103114345.GA10814@coresystems.de>

* Peter Stuge <peter at stuge.se> [071103 02:38]:
> On Fri, Nov 02, 2007 at 01:54:49PM +0100, svn at openbios.org wrote:
> > fix up iwill board compilation. Untested, trivial
> 
> Great! :) Lovely to see all boards build again.
> 
> From a quick look it seems the changes needed on these boards were
> similar. Could you write a few lines about it? Like a changelog
> message.. "fix" is not very informative. :\ (Yes, I could try to
> understand the code.)

I will gladly take the time if someone is actually using those boards ;-)

Here's what I did:

I switched all those boards to use Cache As Ram. I copied the
cache_as_ram_auto.c (what a name!) from another board and adjusted 
the following settings:

 * number of CPUs and
 * Addresses of SPD on i2c
 * SuperIO 
 * memreset functions

As a side note this was an interesting practice for v3. The above
settings are what distinguishes the K8 autobuilds. 

So if we can abstract those properly, we can drop the requirement for
writing code to support a mainboard. (amongst other things that come
later, ACPI/PIRQ etc which should go to DTS anyways)



Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From uwe at hermann-uwe.de  Sat Nov  3 13:40:04 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 3 Nov 2007 13:40:04 +0100
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <472B5EB1.6000100@gmail.com>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
	<20071102171555.GE25764@greenwood> <472B5EB1.6000100@gmail.com>
Message-ID: <20071103124004.GA12713@greenwood>

On Fri, Nov 02, 2007 at 01:30:25PM -0400, Corey Osgood wrote:
> Signed-off-by: Corey Osgood <corey.osgood at gmail.com>

> according to micron), just in case. I've left the function in vt8237r
> because there's no file that it would really fit into right now. If
> someone else wants/needs to use it in the future, it should be moved.

Yeah, we can move it later.

For the latest version with Peter's suggestions:
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

There are some cosmetics to be fixed still, but I'll do than in a
follow-up commit.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Sat Nov  3 13:50:26 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  3 Nov 2007 13:50:26 +0100
Subject: [LinuxBIOS] r2936 - in trunk/LinuxBIOSv2/src/arch/i386: boot
	include/arch
Message-ID: <mailman.831.1355071196.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-03 13:50:26 +0100 (Sat, 03 Nov 2007)
New Revision: 2936

Modified:
   trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c
   trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h
Log:
This patch adds support for MCFG table, which allows OS to find the
MMCONFIG for memory mapped PCIe config.

However this patch is not enough to enable it on Linux, Linux do not trust
BIOSes too much, so a small patch to kernel to disable the check if this
region is e820 reserved.

PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
PCI: Not using MMCONFIG.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c
===================================================================
--- trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c	2007-11-02 23:27:12 UTC (rev 2935)
+++ trunk/LinuxBIOSv2/src/arch/i386/boot/acpi.c	2007-11-03 12:50:26 UTC (rev 2936)
@@ -65,7 +65,16 @@
 	printk_warning("ACPI: could not add ACPI table to RSDT. failed.\n");
 }
 
+int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end) {
+	mmconfig->base_address = base;
+	mmconfig->base_reserved = 0;
+	mmconfig->pci_segment_group_number = seg_nr;
+	mmconfig->start_bus_number = start;
+	mmconfig->end_bus_number = end;
+	return (sizeof(acpi_mcfg_mmconfig_t));
+}
 
+
 int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 {
 	lapic->type=0;
@@ -146,6 +155,31 @@
 	header->checksum	= acpi_checksum((void *)madt, header->length);
 }
 
+void acpi_create_mcfg(acpi_mcfg_t *mcfg)
+{
+
+	acpi_header_t *header=&(mcfg->header);
+	unsigned long current=(unsigned long)mcfg+sizeof(acpi_mcfg_t);
+	
+	memset((void *)mcfg, 0, sizeof(acpi_mcfg_t));
+	
+	/* fill out header fields */
+	memcpy(header->signature, MCFG_NAME, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, MCFG_TABLE, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	
+	header->length = sizeof(acpi_mcfg_t);
+	header->revision = 1;
+
+	current = acpi_fill_mcfg(current);
+	
+	/* recalculate length */
+	header->length= current - (unsigned long)mcfg;
+	
+	header->checksum	= acpi_checksum((void *)mcfg, header->length);
+}
+
 int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic)
 {
         lapic->type=0;

Modified: trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h
===================================================================
--- trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h	2007-11-02 23:27:12 UTC (rev 2935)
+++ trunk/LinuxBIOSv2/src/arch/i386/include/arch/acpi.h	2007-11-03 12:50:26 UTC (rev 2936)
@@ -26,11 +26,13 @@
 #define RSDT_NAME             "RSDT"
 #define HPET_NAME             "HPET"
 #define MADT_NAME             "APIC"
+#define MCFG_NAME             "MCFG"
 #define SRAT_NAME             "SRAT"
 #define SLIT_NAME	      "SLIT"
 
 #define RSDT_TABLE            "RSDT    "
 #define HPET_TABLE            "AMD64   "
+#define MCFG_TABLE            "MCFG    "
 #define MADT_TABLE            "MADT    "
 #define SRAT_TABLE	      "SRAT    "
 #define SLIT_TABLE	      "SLIT    "
@@ -81,7 +83,7 @@
 /* RSDT */
 typedef struct acpi_rsdt {
 	struct acpi_table_header header;
-	u32 entry[6+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
+	u32 entry[7+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
 } __attribute__ ((packed)) acpi_rsdt_t;
 
 /* XSDT */
@@ -100,6 +102,22 @@
 	u8 attributes;
 } __attribute__ ((packed)) acpi_hpet_t;
 
+/* MCFG taken from include/linux/acpi.h */
+typedef struct acpi_mcfg {
+	struct acpi_table_header header;
+	u8 reserved[8];
+} __attribute__ ((packed)) acpi_mcfg_t;
+
+typedef struct acpi_mcfg_mmconfig {
+	u32 base_address;
+	u32 base_reserved;
+	u16 pci_segment_group_number;
+	u8 start_bus_number;
+	u8 end_bus_number;
+	u8 reserved[4];
+} __attribute__ ((packed)) acpi_mcfg_mmconfig_t;
+
+
 /* SRAT */
 typedef struct acpi_srat {
         struct acpi_table_header header;
@@ -273,6 +291,7 @@
 /* These are implemented by the target port */
 unsigned long write_acpi_tables(unsigned long addr);
 unsigned long acpi_fill_madt(unsigned long current);
+unsigned long acpi_fill_mcfg(unsigned long current);
 unsigned long acpi_fill_srat(unsigned long current); 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt);
 
@@ -294,11 +313,14 @@
 
 int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic);
 int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32 flags);
+int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end);
 unsigned long acpi_create_srat_lapics(unsigned long current);
 void acpi_create_srat(acpi_srat_t *srat);
 
 void acpi_create_hpet(acpi_hpet_t *hpet);
 
+void acpi_create_mcfg(acpi_mcfg_t *mcfg);
+
 void acpi_create_facs(acpi_facs_t *facs);
 
 void acpi_write_rsdt(acpi_rsdt_t *rsdt);




From info at coresystems.de  Sat Nov  3 14:28:56 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sat, 03 Nov 2007 14:28:56 +0100
Subject: [LinuxBIOS] r2936 build service
Message-ID: <E1IoJ3Y-00052j-Sw@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2936 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
This patch adds support for MCFG table, which allows OS to find the
MMCONFIG for memory mapped PCIe config.

However this patch is not enough to enable it on Linux, Linux do not trust
BIOSes too much, so a small patch to kernel to disable the check if this
region is e820 reserved.

PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
PCI: Not using MMCONFIG.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma has been broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2936&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah has been broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2936&device=serengeti_cheetah&vendor=amd
Configuration of asus:a8v-e_se is still broken
Compilation of intel:xe7501devkit has been broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2936&device=xe7501devkit&vendor=intel
Compilation of iwill:dk8_htx has been broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2936&device=dk8_htx&vendor=iwill
Compilation of via:epia-m has been broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2936&device=epia-m&vendor=via


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Sat Nov  3 14:32:51 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Nov 2007 14:32:51 +0100
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <472BC9EE.1010200@gmx.net>
References: <001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>	<20071004025851.GA32267@greenwood>	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>	<20071029210629.GB3642@coresystems.de>	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>	<4727205B.2040406@gmx.net>	<005501c81c82$23b72330$0200a8c0@sis.com.tw>	<20071101200216.GL21220@cosmic.amd.com>	<009201c81d05$27559020$0200a8c0@sis.com.tw>
	<472BC9EE.1010200@gmx.net>
Message-ID: <472C7882.2060109@gmx.net>

Dear Morgan,

please disregard my last patch. This patch is more complete and applies
to current svn HEAD.

* Change one PCI vendor ID from Nvidia to SiS
* Remove dead code
* Remove unused variables
* Fix bug where array was one element too small
* Fix error value truncation, the old code never entered the error path
* Remove warnings

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c	(Arbeitskopie)
@@ -72,7 +72,6 @@
 {
         uint8_t *base;
         struct resource *res;
-        uint32_t temp32;
 
         print_debug("USB 2.0 INIT:---------->\n");
 
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c	(Arbeitskopie)
@@ -29,6 +29,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <arch/io.h>
+#include <delay.h>
 #include "sis966.h"
 
 uint8_t	SiS_SiS7502_init[7][3]={
@@ -236,13 +237,8 @@
 
 static void codecs_init(uint8_t *base, uint32_t codec_mask)
 {
-	int i;
 	codec_init(base, 0);
 	return;
-	for(i=2; i>=0; i--) {
-		if( codec_mask & (1<<i) )
-			codec_init(base, i);
-	}
 }
 
 static void aza_init(struct device *dev)
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c	(Arbeitskopie)
@@ -234,7 +234,6 @@
 static void sis966_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
-	unsigned long index;
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	(Arbeitskopie)
@@ -23,7 +23,7 @@
 
 #define SMBUS0_IO_BASE	0x8D0
 
-static const uint8_t SiS_LPC_init[33][3]={
+static const uint8_t SiS_LPC_init[34][3]={
 {0x04, 0xF8, 0x07},					//Reg 0x04
 {0x45, 0x00, 0x00},					//Reg 0x45			//Enable Rom Flash
 {0x46, 0x00, 0x3D},					//Reg 0x46
@@ -444,7 +444,6 @@
   	device_t dev;
   	msr_t	msr;
 	int	i;
-	uint32_t j;
 	uint8_t temp8;
 	uint16_t temp16;
 
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c	(Arbeitskopie)
@@ -111,13 +111,9 @@
 
 static void sata_init(struct device *dev)
 {
-	uint32_t dword;
 	struct southbridge_sis_sis966_config *conf;
 
 
-struct resource *res;
-uint16_t base;
-uint8_t temp8;
 
 	conf = dev->chip_info;
         print_debug("SATA_INIT:---------->\n");
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c	(Arbeitskopie)
@@ -102,7 +102,6 @@
 
 static void sis966_sm_read_resources(device_t dev)
 {
-	struct resource *res;
 	unsigned long index;
 
 	/* Get the normal pci resources of this device */
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	(Arbeitskopie)
@@ -23,14 +23,12 @@
 {
 	device_t dev;
 
-	/* Find the device.
-	 */
+	/* Find the device. */
 	dev = pci_locate_device_on_bus(
-		PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_SIS_SIS966_HT),
+		PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_HT),
 		bus);
 
 	return (dev>>15) & 0x1f;
-
 }
 
 static void hard_reset(void)
@@ -41,6 +39,7 @@
 	outb(0x0a, 0x0cf9);
 	outb(0x0e, 0x0cf9);
 }
+
 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
 /* default value for sis966 is good */
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	(Arbeitskopie)
@@ -93,9 +93,7 @@
 
 static void set_apc(struct device *dev)
 {
-    uint32_t tmp;
     uint16_t addr;
-    uint32_t idx;
     uint16_t i;
     uint8_t   bTmp;
 
@@ -139,7 +137,7 @@
 #define LoopNum 200
 static  unsigned long ReadEEprom( struct device *dev,  uint32_t base,  uint32_t Reg)
 {
-    uint16_t 	data;
+    uint32_t 	data;
     uint32_t 	i;
     uint32_t 	ulValue;
 
@@ -165,7 +163,7 @@
     if(i==LoopNum)   data=0x10000;
     else{
     	ulValue=readl(base+0x3c);
-    	data = (uint16_t)((ulValue & 0xffff0000) >> 16);
+    	data = ((ulValue & 0xffff0000) >> 16);
     }
 
     return data;
@@ -174,11 +172,9 @@
 static int phy_read(uint32_t  base, unsigned phy_addr, unsigned phy_reg)
 {
     uint32_t   ulValue;
-    unsigned  loop = 0x100;
     uint32_t   Read_Cmd;
     uint16_t   usData;
 
-    uint16_t   tmp;
 
 
 	   Read_Cmd = ((phy_reg << 11) |
@@ -188,16 +184,13 @@
 
            // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
           writel( Read_Cmd,base+0x44);
-          //outl( Read_Cmd,tmp+0x44);
 
            // Polling SMI_REQ bit to be deasserted indicated read command completed
            do
            {
 	       // Wait 20 usec before checking status
-    	       //StallAndWait(20);
 		   mdelay(20);
     	       ulValue = readl(base+0x44);
-    	       //ulValue = inl(tmp+0x44);
            } while((ulValue & SMI_REQUEST) != 0);
             //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
            usData=(ulValue>>16);
@@ -213,7 +206,6 @@
 static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect()
 {
     int	              bFoundPhy = FALSE;
-    uint32_t		Read_Cmd;
     uint16_t		usData;
     int		       PhyAddress = 0;
 
@@ -246,16 +238,10 @@
 
 static void nic_init(struct device *dev)
 {
-        uint32_t dword, old;
-        uint32_t mac_h, mac_l;
-        int eeprom_valid = 0;
         int val;
         uint16_t  PhyAddr;
-        struct southbridge_sis_sis966_config *conf;
-        static uint32_t nic_index = 0;
         uint32_t base;
         struct resource *res;
-        uint32_t reg;
 
 
         print_debug("NIC_INIT:---------->\n");
@@ -353,68 +339,7 @@
 print_debug("NIC_INIT:<----------\n");
 return;
 
-#define RegStationMgtInf	0x44
-#define PHY_RGMII	0x10000000
 
-	writel(PHY_RGMII, base + RegStationMgtInf);
-	conf = dev->chip_info;
-
-	if(conf->mac_eeprom_smbus != 0) {
-//	read MAC address from EEPROM at first
-
-		struct device *dev_eeprom;
-		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
-
-		if(dev_eeprom) {
-		//	if that is valid we will use that
-			unsigned char dat[6];
-			int status;
-			int i;
-			for(i=0;i<6;i++) {
-				status = smbus_read_byte(dev_eeprom, i);
-				if(status < 0) break;
-				dat[i] = status & 0xff;
-			}
-			if(status >= 0) {
-				mac_l = 0;
-				for(i=3;i>=0;i--) {
-					mac_l <<= 8;
-					mac_l += dat[i];
-				}
-				if(mac_l != 0xffffffff) {
-					mac_l += nic_index;
-					mac_h = 0;
-					for(i=5;i>=4;i--) {
-						mac_h <<= 8;
-						mac_h += dat[i];
-					}
-					eeprom_valid = 1;
-				}
-			}
-		}
-	}
-
-// if that is invalid we will read that from romstrap
-	if(!eeprom_valid) {
-		unsigned long mac_pos;
-		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
-		mac_l = readl(mac_pos) + nic_index; // overflow?
-		mac_h = readl(mac_pos + 4);
-
-	}
-
-// set that into NIC MMIO
-#define NvRegMacAddrA	0xA8
-#define NvRegMacAddrB	0xAC
-	writel(mac_l, base + NvRegMacAddrA);
-	writel(mac_h, base + NvRegMacAddrB);
-
-	nic_index++;
-
-#if CONFIG_PCI_ROM_RUN == 1
-	pci_dev_init(dev);// it will init option rom
-#endif
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -436,6 +361,7 @@
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
+
 static const struct pci_driver nic_driver __pci_driver = {
 	.ops	= &nic_ops,
 	.vendor	= PCI_VENDOR_ID_SIS,
Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
===================================================================
--- LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	(Revision 2935)
+++ LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	(Arbeitskopie)
@@ -77,8 +77,6 @@
 
 static void sis761_read_resources(device_t dev)
 {
-	struct resource *resource;
-	unsigned char iommu;
 	/* Read the generic PCI resources */
 	printk_debug("sis761_read_resources\n");
 	pci_dev_read_resources(dev);
@@ -91,56 +89,13 @@
 
 	return;
 
-	iommu = 1;
-	get_option(&iommu, "iommu");
-
-	if (iommu) {
-		/* Add a Gart apeture resource */
-		resource = new_resource(dev, 0x94);
-		resource->size = iommu?AGP_APERTURE_SIZE:1;
-		resource->align = log2(resource->size);
-		resource->gran  = log2(resource->size);
-		resource->limit = 0xffffffff; /* 4G */
-		resource->flags = IORESOURCE_MEM;
-	}
 }
 
 static void set_agp_aperture(device_t dev)
 {
-	struct resource *resource;
 
 	return;
 
-	resource = probe_resource(dev, 0x94);
-	if (resource) {
-		device_t pdev;
-		uint32_t gart_base, gart_acr;
-
-		/* Remember this resource has been stored */
-		resource->flags |= IORESOURCE_STORED;
-
-		/* Find the size of the GART aperture */
-		gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
-
-		/* Get the base address */
-		gart_base = ((resource->base) >> 25) & 0x00007fff;
-
-		/* Update the other northbriges */
-		pdev = 0;
-		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
-			/* Store the GART size but don't enable it */
-			pci_write_config32(pdev, 0x90, gart_acr);
-
-			/* Store the GART base address */
-			pci_write_config32(pdev, 0x94, gart_base);
-
-			/* Don't set the GART Table base address */
-			pci_write_config32(pdev, 0x98, 0);
-
-			/* Report the resource has been stored... */
-			report_resource_stored(pdev, resource, " <gart>");
-		}
-	}
 }
 
 static void sis761_set_resources(device_t dev)
@@ -156,9 +111,7 @@
 
 static void sis761_init(struct device *dev)
 {
-	uint32_t cmd, cmd_ref;
 	int needs_reset;
-	struct device *f0_dev, *f2_dev;
 	msr_t	msr;
 
 





From svn at openbios.org  Sat Nov  3 19:45:42 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sat,  3 Nov 2007 19:45:42 +0100
Subject: [LinuxBIOS] r2937 - in trunk/LinuxBIOSv2/src: include
	southbridge/via/vt8237r
Message-ID: <mailman.832.1355071196.16123.coreboot@coreboot.org>

Author: cozzie
Date: 2007-11-03 19:45:42 +0100 (Sat, 03 Nov 2007)
New Revision: 2937

Modified:
   trunk/LinuxBIOSv2/src/include/spd.h
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c
Log:
This patch is some small changes to the vt8237r to prepare it for
the Jetway J7F2 patch that should be coming soon, and also moves most
defines into vt8237r.h. I've changed some of the values from u32 to u8,
because that's all they should ever need to be. Also includes
doxygenized comments!

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de> 



Modified: trunk/LinuxBIOSv2/src/include/spd.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/spd.h	2007-11-03 12:50:26 UTC (rev 2936)
+++ trunk/LinuxBIOSv2/src/include/spd.h	2007-11-03 18:45:42 UTC (rev 2937)
@@ -105,6 +105,7 @@
 #define SPD_MEMORY_TYPE_SGRAM_DDR        6
 #define SPD_MEMORY_TYPE_SDRAM_DDR        7
 #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
+#define SPD_MEMORY_TYPE_SDRAM_DDR3       0xb
 
 /* SPD_MODULE_VOLTAGE values. */
 #define SPD_VOLTAGE_TTL                  0 /* 5.0 Volt/TTL */

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h	2007-11-03 12:50:26 UTC (rev 2936)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h	2007-11-03 18:45:42 UTC (rev 2937)
@@ -30,4 +30,42 @@
 #define VT8237R_HPET_ADDR	0xfed00000ULL
 #define VT8237R_APIC_BASE	0xfec00000ULL
 
+/* IDE specific defines */
+#define IDE_CS		0x40
+#define IDE_CONF_I	0x41
+#define IDE_CONF_II	0x42
+#define IDE_CONF_FIFO	0x43
+#define IDE_MISC_I	0x44
+#define IDE_MISC_II	0x45
+#define IDE_UDMA	0x50
+
+/* SMBus specific */
+#define VT8237R_POWER_WELL		0x94
+#define VT8237R_SMBUS_IO_BASE_REG	0xd0
+#define VT8237R_SMBUS_HOST_CONF		0xd2
+
+#define SMBHSTSTAT	(VT8237R_SMBUS_IO_BASE + 0x0)
+#define SMBSLVSTAT	(VT8237R_SMBUS_IO_BASE + 0x1)
+#define SMBHSTCTL	(VT8237R_SMBUS_IO_BASE + 0x2)
+#define SMBHSTCMD	(VT8237R_SMBUS_IO_BASE + 0x3)
+#define SMBXMITADD	(VT8237R_SMBUS_IO_BASE + 0x4)
+#define SMBHSTDAT0	(VT8237R_SMBUS_IO_BASE + 0x5)
+
+#define HOST_RESET 		0xff
+/* 1 in the 0 bit of SMBHSTADD states to READ. */
+#define READ_CMD		0x01
+#define SMBUS_TIMEOUT		(100 * 1000 * 10)
+#define I2C_TRANS_CMD		0x40
+#define CLOCK_SLAVE_ADDRESS	0x69
+
+#if DEBUG_SMBUS == 1
+#define PRINT_DEBUG(x)		print_debug(x)
+#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
+#else
+#define PRINT_DEBUG(x)
+#define PRINT_DEBUG_HEX16(x)
 #endif
+
+#define SMBUS_DELAY() inb(0x80)
+
+#endif

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2007-11-03 12:50:26 UTC (rev 2936)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2007-11-03 18:45:42 UTC (rev 2937)
@@ -20,41 +20,21 @@
  */
 
 #include <device/pci_ids.h>
+#include <spd.h>
 #include "vt8237r.h"
 
-#define VT8237R_POWER_WELL		0x94
-#define VT8237R_SMBUS_IO_BASE_REG	0xd0
-#define VT8237R_SMBUS_HOST_CONF		0xd2
-
-#define SMBHSTSTAT	(VT8237R_SMBUS_IO_BASE + 0x0)
-#define SMBSLVSTAT	(VT8237R_SMBUS_IO_BASE + 0x1)
-#define SMBHSTCTL	(VT8237R_SMBUS_IO_BASE + 0x2)
-#define SMBHSTCMD	(VT8237R_SMBUS_IO_BASE + 0x3)
-#define SMBXMITADD	(VT8237R_SMBUS_IO_BASE + 0x4)
-#define SMBHSTDAT0	(VT8237R_SMBUS_IO_BASE + 0x5)
-
-#define HOST_RESET 		0xff
-/* 1 in the 0 bit of SMBHSTADD states to READ. */
-#define READ_CMD		0x01
-#define SMBUS_TIMEOUT		(100 * 1000 * 10)
-#define I2C_TRANS_CMD		0x40
-#define CLOCK_SLAVE_ADDRESS	0x69
-
-#if DEBUG_SMBUS == 1
-#define PRINT_DEBUG(x)		print_debug(x)
-#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
-#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
-#endif
-
-#define SMBUS_DELAY() inb(0x80)
-
+/**
+ * Print an error, should it occur. If no error, just exit.
+ *
+ * @param host_status The data returned on the host status register after a
+ * transaction is processed.
+ * @param loops The number of times a transaction was attempted.
+ */
 static void smbus_print_error(u8 host_status, int loops)
 {
 	/* Check if there actually was an error. */
-	if (host_status == 0x00 || host_status == 0x40 ||
-	    host_status == 0x42)
+	if ((host_status == 0x00 || host_status == 0x40 ||
+	    host_status == 0x42) && (loops < SMBUS_TIMEOUT))
 		return;
 
 	if (loops >= SMBUS_TIMEOUT)
@@ -66,11 +46,14 @@
 	if (host_status & (1 << 2))
 		print_err("Device error\r\n");
 	if (host_status & (1 << 1))
-		print_err("Interrupt/SMI# was Successful Completion\r\n");
+		print_debug("Interrupt/SMI# Completed Successfully\r\n");
 	if (host_status & (1 << 0))
 		print_err("Host busy\r\n");
 }
 
+/**
+ * Wait for the smbus to become ready to process the next transaction
+ */
 static void smbus_wait_until_ready(void)
 {
 	int loops;
@@ -79,11 +62,14 @@
 
 	loops = 0;
 	/* Yes, this is a mess, but it's the easiest way to do it. */
-	while ((inb(SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT)
+	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
 		++loops;
 	smbus_print_error(inb(SMBHSTSTAT), loops);
 }
 
+/**
+ * Reset and take ownership of the smbus
+ */
 static void smbus_reset(void)
 {
 	outb(HOST_RESET, SMBHSTSTAT);
@@ -95,9 +81,15 @@
 	PRINT_DEBUG("\r\n");
 }
 
-u8 smbus_read_byte(u32 dimm, u32 offset)
+/**
+ * Read a byte from the smbus
+ *
+ * @param dimm The address location of the dimm on the smbus
+ * @param offset The offset the data is located at
+ */
+u8 smbus_read_byte(u8 dimm, u8 offset)
 {
-	u32 val;
+	u8 val;
 
 	PRINT_DEBUG("DIMM ");
 	PRINT_DEBUG_HEX16(dimm);
@@ -131,10 +123,12 @@
 	/* Probably don't have to do this, but it can't hurt. */
 	smbus_reset();
 
-	/* Can I just "return inb(SMBHSTDAT0)"? */
 	return val;
 }
 
+/**
+ * Enable the smbus on vt8237r-based systems
+ */
 void enable_smbus(void)
 {
 	device_t dev;
@@ -166,3 +160,45 @@
 	/* Reset the internal pointer. */
 	inb(SMBHSTCTL);
 }
+
+/**
+ * A fixup for some systems that need time for the smbus to "warm up". This is 
+ * needed on some vt823x based systems, where the smbus spurts out bad data for 
+ * a short time after power on. This has been seen on the Via Epia-series and 
+ * Jetway J7F2-series. It reads the ID byte from SMBus, looking for 
+ * known-good data from a slot/address. Exits on either good data or a timeout.
+ *
+ * This should probably go into some global file, but one would need to be 
+ * created just for it. If some other chip needs/wants it, we can worry about it
+ * then.
+ *
+ * @param ctrl The memory controller and smbus addresses
+ */
+void smbus_fixup(const struct mem_controller *ctrl)
+{
+	int i, ram_slots, current_slot = 0;
+	u8 result = 0;
+
+	ram_slots = ARRAY_SIZE(ctrl->channel0);
+	if (!ram_slots) {
+		print_err("smbus_fixup thinks there are no ram slots!\r\n");
+		return;
+	}
+	
+	PRINT_DEBUG("Waiting for smbus to warm up");
+		
+	/* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for the
+	 * ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
+	 * vt8237r has only been seen on DDR and DDR2 based systems, so far */
+	for(i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || 
+			(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++)
+	{
+		if (current_slot > ram_slots) current_slot = 0;
+		result = smbus_read_byte(ctrl->channel0[current_slot], 
+							SPD_MEMORY_TYPE);
+		current_slot++;
+		PRINT_DEBUG(".");
+	}
+	if (i >= SMBUS_TIMEOUT)	print_err("SMBus timed out while warming up\r\n");
+	else PRINT_DEBUG("Done\r\n");	
+}

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c	2007-11-03 12:50:26 UTC (rev 2936)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c	2007-11-03 18:45:42 UTC (rev 2937)
@@ -27,14 +27,6 @@
 #include "vt8237r.h"
 #include "chip.h"
 
-#define IDE_CS		0x40
-#define IDE_CONF_I	0x41
-#define IDE_CONF_II	0x42
-#define IDE_CONF_FIFO	0x43
-#define IDE_MISC_I	0x44
-#define IDE_MISC_II	0x45
-#define IDE_UDMA	0x50
-
 /**
  * No native mode. Interrupts from unconnected HDDs might occur if
  * IRQ14/15 is used for PCI. Therefore no native mode support.




From corey.osgood at gmail.com  Sat Nov  3 19:46:35 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 03 Nov 2007 14:46:35 -0400
Subject: [LinuxBIOS] [PATCH] vt8237r fixes/improvements (LBv2)
In-Reply-To: <20071103124004.GA12713@greenwood>
References: <472ABD76.9020705@gmail.com> <472ABDA6.4000602@gmail.com>
	<20071102155603.GA25764@greenwood> <472B52B4.9050801@gmail.com>
	<20071102171555.GE25764@greenwood> <472B5EB1.6000100@gmail.com>
	<20071103124004.GA12713@greenwood>
Message-ID: <472CC20B.7050301@gmail.com>

Uwe Hermann wrote:
> On Fri, Nov 02, 2007 at 01:30:25PM -0400, Corey Osgood wrote:
>   
>> Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
>>     
>
>   
>> according to micron), just in case. I've left the function in vt8237r
>> because there's no file that it would really fit into right now. If
>> someone else wants/needs to use it in the future, it should be moved.
>>     
>
> Yeah, we can move it later.
>
> For the latest version with Peter's suggestions:
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Thanks, r2937, and I didn't even break anything!

-Corey



From info at coresystems.de  Sat Nov  3 20:33:34 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sat, 03 Nov 2007 20:33:34 +0100
Subject: [LinuxBIOS] r2937 build service
Message-ID: <E1IoOkQ-0003Uk-4A@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "cozzie" checked in revision 2937 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
This patch is some small changes to the vt8237r to prepare it for
the Jetway J7F2 patch that should be coming soon, and also moves most
defines into vt8237r.h. I've changed some of the values from u32 to u8,
because that's all they should ever need to be. Also includes
doxygenized comments!

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2937&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2937&device=serengeti_cheetah&vendor=amd
Configuration of asus:a8v-e_se is still broken
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2937&device=xe7501devkit&vendor=intel
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2937&device=dk8_htx&vendor=iwill
Compilation of via:epia-m is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2937&device=epia-m&vendor=via


If something broke during this checkin please be a pain 
in cozzie's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Sun Nov  4 04:21:37 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  4 Nov 2007 04:21:37 +0100
Subject: [LinuxBIOS] r2938 - in trunk/LinuxBIOSv2/src: include/device
	mainboard/dell/s1850 mainboard/intel/jarrell
	mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2
	mainboard/supermicro/x6dhr_ig mainboard/supermicro/x6dhr_ig2
	southbridge/intel/i82801ca southbridge/intel/i82801db
	southbridge/intel/i82801dbm southbridge/intel/i82801er
Message-ID: <mailman.833.1355071196.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-11-04 04:21:37 +0100 (Sun, 04 Nov 2007)
New Revision: 2938

Modified:
   trunk/LinuxBIOSv2/src/include/device/pci_ids.h
   trunk/LinuxBIOSv2/src/mainboard/dell/s1850/reset.c
   trunk/LinuxBIOSv2/src/mainboard/intel/jarrell/reset.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/reset.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/reset.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/reset.c
   trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/reset.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_usb.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_uhci.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ide.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_pci.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_sata.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_sata.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_uhci.c
Log:
Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements.

Use human-readable names for the PCI ID #defines.
Rename *_ISA to *_LPC as per datasheet.
The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error.

The fixes in southbridge code are only to keep the build working for now,
any real improvements will only go into the 82801xx code in future.

This is abuild-tested so it shouldn't break anything.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-11-04 03:21:37 UTC (rev 2938)
@@ -1829,36 +1829,136 @@
 #define PCI_DEVICE_ID_INTEL_82371AB_USB		0x7112
 #define PCI_DEVICE_ID_INTEL_82371AB_ACPI	0x7113 /* Same as SMB */
 #define PCI_DEVICE_ID_INTEL_82371AB_SMB		0x7113 /* Same as ACPI */
-#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
-#define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
-#define PCI_DEVICE_ID_INTEL_82801AA_2	0x2412
-#define PCI_DEVICE_ID_INTEL_82801AA_3	0x2413
-#define PCI_DEVICE_ID_INTEL_82801AA_5	0x2415
-#define PCI_DEVICE_ID_INTEL_82801AA_6	0x2416
-#define PCI_DEVICE_ID_INTEL_82801AA_8	0x2418
-#define PCI_DEVICE_ID_INTEL_82801AB_0	0x2420
-#define PCI_DEVICE_ID_INTEL_82801AB_1	0x2421
-#define PCI_DEVICE_ID_INTEL_82801AB_2	0x2422
-#define PCI_DEVICE_ID_INTEL_82801AB_3	0x2423
-#define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
-#define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
-#define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
-#define PCI_DEVICE_ID_INTEL_82801BA_1E0       0x244e
-#define PCI_DEVICE_ID_INTEL_82801BA_1F0       0x2440
-#define PCI_DEVICE_ID_INTEL_82801BA_1F1       0x244b
-#define PCI_DEVICE_ID_INTEL_82801BA_1F2       0x2442
-#define PCI_DEVICE_ID_INTEL_82801BA_1F3       0x2443
-#define PCI_DEVICE_ID_INTEL_82801BA_1F4       0x2444
-#define PCI_DEVICE_ID_INTEL_82801BA_1F5       0x2445
-#define PCI_DEVICE_ID_INTEL_82801CA_1E0       0x244e
-#define PCI_DEVICE_ID_INTEL_82801CA_1F0       0x2480
-#define PCI_DEVICE_ID_INTEL_82801CA_1F1 0x248b
-#define PCI_DEVICE_ID_INTEL_82801CA_1D0 0x2482
-#define PCI_DEVICE_ID_INTEL_82801CA_1F3 0x2483
-#define PCI_DEVICE_ID_INTEL_82801CA_1D1 0x2484
-#define PCI_DEVICE_ID_INTEL_82801CA_1F5 0x2485
-#define PCI_DEVICE_ID_INTEL_82801CA_1F6 0x2486
-#define PCI_DEVICE_ID_INTEL_82801CA_1D2 0x2487
+
+/* Intel 82801AA (ICH) */
+#define PCI_DEVICE_ID_INTEL_82801AA_LPC		0x2410
+#define PCI_DEVICE_ID_INTEL_82801AA_IDE		0x2411
+#define PCI_DEVICE_ID_INTEL_82801AA_USB		0x2412
+#define PCI_DEVICE_ID_INTEL_82801AA_SMB		0x2413
+#define PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO	0x2415
+#define PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM	0x2416
+#define PCI_DEVICE_ID_INTEL_82801AA_PCI		0x2418
+
+/* Intel 82801AB (ICH0) */
+#define PCI_DEVICE_ID_INTEL_82801AB_LPC		0x2420
+#define PCI_DEVICE_ID_INTEL_82801AB_IDE		0x2421
+#define PCI_DEVICE_ID_INTEL_82801AB_USB		0x2422
+#define PCI_DEVICE_ID_INTEL_82801AB_SMB		0x2423
+#define PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO	0x2425
+#define PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM	0x2426
+#define PCI_DEVICE_ID_INTEL_82801AB_PCI		0x2428
+
+/* Intel 82801BA (ICH2) */
+#define PCI_DEVICE_ID_INTEL_82801BA_LPC		0x2440
+#define PCI_DEVICE_ID_INTEL_82801BA_USB_FN2	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BA_SMB		0x2443
+#define PCI_DEVICE_ID_INTEL_82801BA_USB_FN4	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO	0x2445
+#define PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM	0x2446
+#define PCI_DEVICE_ID_INTEL_82801BA_LAN		0x2449
+#define PCI_DEVICE_ID_INTEL_82801BA_IDE		0x244b
+#define PCI_DEVICE_ID_INTEL_82801BA_PCI		0x244e
+
+/* Intel 82801BAM (ICH2-M) */
+#define PCI_DEVICE_ID_INTEL_82801BAM_USB_FN2	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BAM_SMB	0x2443
+#define PCI_DEVICE_ID_INTEL_82801BAM_USB_FN4	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BAM_AC97_AUDIO	0x2445
+#define PCI_DEVICE_ID_INTEL_82801BAM_AC97_MODEM	0x2446
+#define PCI_DEVICE_ID_INTEL_82801BAM_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801BAM_LAN	0x2449
+#define PCI_DEVICE_ID_INTEL_82801BAM_IDE	0x244a
+#define PCI_DEVICE_ID_INTEL_82801BAM_LPC	0x244c
+
+/* Intel 82801CA (ICH3-S) */
+#define PCI_DEVICE_ID_INTEL_82801CA_LAN		0x2449
+#define PCI_DEVICE_ID_INTEL_82801CA_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801CA_LPC		0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_USB1	0x2482
+#define PCI_DEVICE_ID_INTEL_82801CA_SMB		0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_USB2	0x2484
+#define PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO	0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM	0x2486
+#define PCI_DEVICE_ID_INTEL_82801CA_USB3	0x2487
+#define PCI_DEVICE_ID_INTEL_82801CA_IDE		0x248b
+
+/* Intel 82801CAM (ICH3-M) */
+#define PCI_DEVICE_ID_INTEL_82801CAM_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801CAM_LAN	0x2449
+#define PCI_DEVICE_ID_INTEL_82801CAM_USB1	0x2482
+#define PCI_DEVICE_ID_INTEL_82801CAM_SMB	0x2483
+#define PCI_DEVICE_ID_INTEL_82801CAM_USB2	0x2484
+#define PCI_DEVICE_ID_INTEL_82801CAM_AC97_AUDIO	0x2485
+#define PCI_DEVICE_ID_INTEL_82801CAM_AC97_MODEM	0x2486
+#define PCI_DEVICE_ID_INTEL_82801CAM_USB3	0x2487
+#define PCI_DEVICE_ID_INTEL_82801CAM_IDE	0x248a
+#define PCI_DEVICE_ID_INTEL_82801CAM_LPC	0x248c
+
+/* Intel 82801DB (ICH4) */
+#define PCI_DEVICE_ID_INTEL_82801DB_LAN		0x103a
+#define PCI_DEVICE_ID_INTEL_82801DB_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801DB_LPC		0x24c0
+#define PCI_DEVICE_ID_INTEL_82801DB_USB1	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DB_SMB		0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DB_USB2	0x24c4
+#define PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DB_USB3	0x24c7
+#define PCI_DEVICE_ID_INTEL_82801DB_IDE		0x24cb
+#define PCI_DEVICE_ID_INTEL_82801DB_EHCI	0x24cd
+
+/* Intel 82801DBM (ICH4-M) */
+#define PCI_DEVICE_ID_INTEL_82801DBM_LAN	0x103a
+#define PCI_DEVICE_ID_INTEL_82801DBM_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801DBM_USB1	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DBM_SMB	0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DBM_USB2	0x24c4
+#define PCI_DEVICE_ID_INTEL_82801DBM_AC97_AUDIO	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DBM_AC97_MODEM	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DBM_USB3	0x24c7
+#define PCI_DEVICE_ID_INTEL_82801DBM_IDE	0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DBM_LPC	0x24cc
+#define PCI_DEVICE_ID_INTEL_82801DBM_EHCI	0x24cd
+
+/* Intel 82801EB (ICH5) */
+#define PCI_DEVICE_ID_INTEL_82801EB_LAN		0x1051
+#define PCI_DEVICE_ID_INTEL_82801EB_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801EB_LPC		0x24d0
+#define PCI_DEVICE_ID_INTEL_82801EB_SATA	0x24d1
+#define PCI_DEVICE_ID_INTEL_82801EB_USB1	0x24d2
+#define PCI_DEVICE_ID_INTEL_82801EB_SMB		0x24d3
+#define PCI_DEVICE_ID_INTEL_82801EB_USB2	0x24d4
+#define PCI_DEVICE_ID_INTEL_82801EB_AC97_AUDIO	0x24d5
+#define PCI_DEVICE_ID_INTEL_82801EB_AC97_MODEM	0x24d6
+#define PCI_DEVICE_ID_INTEL_82801EB_USB3	0x24d7
+#define PCI_DEVICE_ID_INTEL_82801EB_IDE		0x24db
+#define PCI_DEVICE_ID_INTEL_82801EB_EHCI	0x24dd
+#define PCI_DEVICE_ID_INTEL_82801EB_USB4	0x24de
+
+/* Intel 82801ER (ICH5R) */
+#define PCI_DEVICE_ID_INTEL_82801ER_LAN		0x1051
+#define PCI_DEVICE_ID_INTEL_82801ER_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801ER_LPC		0x24d0
+#define PCI_DEVICE_ID_INTEL_82801ER_USB1	0x24d2
+#define PCI_DEVICE_ID_INTEL_82801ER_SMB		0x24d3
+#define PCI_DEVICE_ID_INTEL_82801ER_USB2	0x24d4
+#define PCI_DEVICE_ID_INTEL_82801ER_AC97_AUDIO	0x24d5
+#define PCI_DEVICE_ID_INTEL_82801ER_AC97_MODEM	0x24d6
+#define PCI_DEVICE_ID_INTEL_82801ER_USB3	0x24d7
+#define PCI_DEVICE_ID_INTEL_82801ER_IDE		0x24db
+#define PCI_DEVICE_ID_INTEL_82801ER_EHCI	0x24dd
+#define PCI_DEVICE_ID_INTEL_82801ER_USB4	0x24de
+#define PCI_DEVICE_ID_INTEL_82801ER_SATA	0x24df
+
+/* Intel 82801E (C-ICH) */
+#define PCI_DEVICE_ID_INTEL_82801E_LPC		0x2450
+#define PCI_DEVICE_ID_INTEL_82801E_USB		0x2452
+#define PCI_DEVICE_ID_INTEL_82801E_SMB		0x2453
+#define PCI_DEVICE_ID_INTEL_82801E_LAN1		0x2459
+#define PCI_DEVICE_ID_INTEL_82801E_IDE		0x245b
+#define PCI_DEVICE_ID_INTEL_82801E_LAN2		0x245d
+#define PCI_DEVICE_ID_INTEL_82801E_PCI		0x245e
+
 #define PCI_DEVICE_ID_INTEL_82870_1E0 0x1461
 #define PCI_DEVICE_ID_INTEL_82870_1F0 0x1460
 #define PCI_DEVICE_ID_INTEL_82820FW_0 0x2440
@@ -1868,63 +1968,7 @@
 #define PCI_DEVICE_ID_INTEL_82820FW_4 0x2449
 #define PCI_DEVICE_ID_INTEL_82820FW_5 0x244b
 #define PCI_DEVICE_ID_INTEL_82820FW_6 0x244e
-#define PCI_DEVICE_ID_INTEL_82801BA_0	0x2440
-#define PCI_DEVICE_ID_INTEL_82801BA_1	0x2442
-#define PCI_DEVICE_ID_INTEL_82801BA_2	0x2443
-#define PCI_DEVICE_ID_INTEL_82801BA_3	0x2444
-#define PCI_DEVICE_ID_INTEL_82801BA_4	0x2445
-#define PCI_DEVICE_ID_INTEL_82801BA_5	0x2446
-#define PCI_DEVICE_ID_INTEL_82801BA_6	0x2448
-#define PCI_DEVICE_ID_INTEL_82801BA_7	0x2449
-#define PCI_DEVICE_ID_INTEL_82801BA_8	0x244a
-#define PCI_DEVICE_ID_INTEL_82801BA_9	0x244b
-#define PCI_DEVICE_ID_INTEL_82801BA_10	0x244c
-#define PCI_DEVICE_ID_INTEL_82801BA_11	0x244e
-#define PCI_DEVICE_ID_INTEL_82801E_0	0x2450
-#define PCI_DEVICE_ID_INTEL_82801E_2	0x2452
-#define PCI_DEVICE_ID_INTEL_82801E_3	0x2453
-#define PCI_DEVICE_ID_INTEL_82801E_9	0x2459
-#define PCI_DEVICE_ID_INTEL_82801E_11	0x245b
-#define PCI_DEVICE_ID_INTEL_82801E_13	0x245d
-#define PCI_DEVICE_ID_INTEL_82801E_14	0x245e
-#define PCI_DEVICE_ID_INTEL_82801CA_LAN  0x2449
-#define PCI_DEVICE_ID_INTEL_82801CA_PCI  0x244e		// Same as 82801ER
-#define PCI_DEVICE_ID_INTEL_82801CA_LPC	0x2480
-#define PCI_DEVICE_ID_INTEL_82801CA_USB	0x2482
-#define PCI_DEVICE_ID_INTEL_82801CA_SMB 0x2483
-#define PCI_DEVICE_ID_INTEL_82801CA_USB2 0x2484
-#define PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO	0x2485
-#define PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM	0x2486
-#define PCI_DEVICE_ID_INTEL_82801CA_USB3 0x2487
-#define PCI_DEVICE_ID_INTEL_82801CA_10	0x248a
-#define PCI_DEVICE_ID_INTEL_82801CA_IDE	0x248b
-#define PCI_DEVICE_ID_INTEL_82801CA_12	0x248c
-#define PCI_DEVICE_ID_INTEL_82801DB_0	0x24c0
-#define PCI_DEVICE_ID_INTEL_82801DB_2	0x24c2
-#define PCI_DEVICE_ID_INTEL_82801DB_3	0x24c3
-#define PCI_DEVICE_ID_INTEL_82801DB_4	0x24c4
-#define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
-#define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
-#define PCI_DEVICE_ID_INTEL_82801DB_7	0x24c7
-#define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
-#define PCI_DEVICE_ID_INTEL_82801DB_13	0x24cd
-#define PCI_DEVICE_ID_INTEL_82801EB_0   0x24d0
-#define PCI_DEVICE_ID_INTEL_82801EB_USB 0x24d2
-#define PCI_DEVICE_ID_INTEL_82801EB_4   0x24d4
-#define PCI_DEVICE_ID_INTEL_82801EB_D   0x24dd
-#define PCI_DEVICE_ID_INTEL_82801EB_E   0x24de
-#define PCI_DEVICE_ID_INTEL_82801EB_IDE 0x24db
-#define PCI_DEVICE_ID_INTEL_82801ER_PCI  0x244e
-#define PCI_DEVICE_ID_INTEL_82801ER_ISA  0x24d0
-#define PCI_DEVICE_ID_INTEL_82801ER_USB  0x24d2
-#define PCI_DEVICE_ID_INTEL_82801ER_SMB  0x24d3
-#define PCI_DEVICE_ID_INTEL_82801ER_USB2 0x24d4
-#define PCI_DEVICE_ID_INTEL_82801ER_AC97_AUDIO 0x24d5
-#define PCI_DEVICE_ID_INTEL_82801ER_AC97_MODEM 0x24d6
-#define PCI_DEVICE_ID_INTEL_82801ER_USB3 0x24d7
-#define PCI_DEVICE_ID_INTEL_82801ER_EHCI 0x24dd
-#define PCI_DEVICE_ID_INTEL_82801ER_IDE  0x24db
-#define PCI_DEVICE_ID_INTEL_82801ER_SATA 0x24df
+
 #define PCI_DEVICE_ID_INTEL_6300ESB_ISA  0x25a1
 #define PCI_DEVICE_ID_INTEL_6300ESB_AC97_AUDIO 0x25a6
 #define PCI_DEVICE_ID_INTEL_6300ESB_AC97_MODEM 0x25a7
@@ -1966,31 +2010,6 @@
 #define PCI_DEVICE_ID_INTEL_PCIE_PB	0x3597
 #define PCI_DEVICE_ID_INTEL_PCIE_PC	0x3599
 
-#define PCI_DEVICE_ID_INTEL_82801DBM_1E0 0x2448
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F0 0x24cc
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F1 0x24ca
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F3 0x24c3
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F5 0x24c5
-#define PCI_DEVICE_ID_INTEL_82801DBM_1F6 0x24c6
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D0 0x24c2
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D1 0x24c4
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D2 0x24c7
-#define PCI_DEVICE_ID_INTEL_82801DBM_1D7 0x24cd
-
-#define PCI_DEVICE_ID_INTEL_82801ER_1E0 0x244e
-#define PCI_DEVICE_ID_INTEL_82801ER_1F0 0x24d0
-#define PCI_DEVICE_ID_INTEL_82801ER_1F1 0x24db
-#define PCI_DEVICE_ID_INTEL_82801ER_1F2 0x24d1
-#define PCI_DEVICE_ID_INTEL_82801ER_1F2_R 0x24df
-#define PCI_DEVICE_ID_INTEL_82801ER_1F3 0x24d3
-#define PCI_DEVICE_ID_INTEL_82801ER_1F5 0x24d5
-#define PCI_DEVICE_ID_INTEL_82801ER_1F6 0x24d6
-#define PCI_DEVICE_ID_INTEL_82801ER_1D0 0x24d2
-#define PCI_DEVICE_ID_INTEL_82801ER_1D1 0x24d4
-#define PCI_DEVICE_ID_INTEL_82801ER_1D2 0x24d7
-#define PCI_DEVICE_ID_INTEL_82801ER_1D3 0x24de
-#define PCI_DEVICE_ID_INTEL_82801ER_1D7 0x24dd
-
 #define PCI_VENDOR_ID_COMPUTONE		0x8e0e
 #define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
 #define PCI_DEVICE_ID_COMPUTONE_PG	0x0302

Modified: trunk/LinuxBIOSv2/src/mainboard/dell/s1850/reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/dell/s1850/reset.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/mainboard/dell/s1850/reset.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -26,7 +26,7 @@
 {
 	device_t dev;
 	/* Enable power on after power fail... */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
 	if (dev != PCI_DEV_INVALID) {
 		unsigned byte;
 		byte = pci_read_config8(dev, 0xa4);

Modified: trunk/LinuxBIOSv2/src/mainboard/intel/jarrell/reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/intel/jarrell/reset.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/mainboard/intel/jarrell/reset.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -26,7 +26,7 @@
 {
 	device_t dev;
 	/* Enable power on after power fail... */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
 	if (dev != PCI_DEV_INVALID) {
 		unsigned byte;
 		byte = pci_read_config8(dev, 0xa4);

Modified: trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/reset.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g/reset.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -26,7 +26,7 @@
 {
 	device_t dev;
 	/* Enable power on after power fail... */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
 	if (dev != PCI_DEV_INVALID) {
 		unsigned byte;
 		byte = pci_read_config8(dev, 0xa4);

Modified: trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/reset.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhe_g2/reset.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -26,7 +26,7 @@
 {
 	device_t dev;
 	/* Enable power on after power fail... */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
 	if (dev != PCI_DEV_INVALID) {
 		unsigned byte;
 		byte = pci_read_config8(dev, 0xa4);

Modified: trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/reset.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig/reset.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -26,7 +26,7 @@
 {
 	device_t dev;
 	/* Enable power on after power fail... */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
 	if (dev != PCI_DEV_INVALID) {
 		unsigned byte;
 		byte = pci_read_config8(dev, 0xa4);

Modified: trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/reset.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dhr_ig2/reset.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -26,7 +26,7 @@
 {
 	device_t dev;
 	/* Enable power on after power fail... */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
 	if (dev != PCI_DEV_INVALID) {
 		unsigned byte;
 		byte = pci_read_config8(dev, 0xa4);

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_usb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_usb.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_usb.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -34,7 +34,7 @@
 static const struct pci_driver usb_driver_1 __pci_driver = {
 	.ops    = &usb_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801CA_USB,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_USB1,
 };
 static const struct pci_driver usb_driver_2 __pci_driver = {
         .ops    = &usb_ops,

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_lpc.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_lpc.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -412,5 +412,5 @@
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops    = &lpc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DB_ISA,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_uhci.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_uhci.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801db/i82801db_uhci.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -54,21 +54,21 @@
 	.ops_pci          = &lops_pci,
 };
 
-static const struct pci_driver uhci_driver __pci_driver = {
+static const struct pci_driver usb1_driver __pci_driver = {
 	.ops    = &uhci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DB_USB0,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
 };
 
 static const struct pci_driver usb2_driver __pci_driver = {
 	.ops    = &uhci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
 };
 
 static const struct pci_driver usb3_driver __pci_driver = {
 	.ops    = &uhci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB3,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -21,7 +21,7 @@
 static const struct pci_driver ac97audio_driver __pci_driver = {
 	.ops    = &ac97audio_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_1F5,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_AC97_AUDIO,
 };
 
 
@@ -37,5 +37,5 @@
 static const struct pci_driver ac97modem_driver __pci_driver = {
 	.ops    = &ac97modem_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_1F6,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_AC97_MODEM,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ide.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ide.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_ide.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -48,6 +48,6 @@
 static const struct pci_driver ide_driver __pci_driver = {
 	.ops    = &ide_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_1F1,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_IDE,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -211,5 +211,5 @@
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops    = &lpc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_1F0,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_pci.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_pci.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_pci.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -28,6 +28,6 @@
 static const struct pci_driver pci_driver __pci_driver = {
 	.ops    = &pci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_1E0,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_sata.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_sata.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -70,6 +70,6 @@
 static const struct pci_driver stat_driver __pci_driver = {
 	.ops    = &sata_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_1F2_R,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_SATA,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -35,21 +35,15 @@
 static const struct pci_driver usb_driver_1 __pci_driver = {
 	.ops    = &usb_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_1D0,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB1,
 };
 static const struct pci_driver usb_driver_2 __pci_driver = {
         .ops    = &usb_ops,
         .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82801ER_1D1,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB2,
 };
 static const struct pci_driver usb_driver_3 __pci_driver = {
         .ops    = &usb_ops,
         .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82801ER_1D2,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB3,
 };
-static const struct pci_driver usb_driver_4 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82801ER_1D3,
-};
-

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -36,5 +36,5 @@
 static const struct pci_driver usb2_driver __pci_driver = {
 	.ops    = &usb2_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_1D7,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_EHCI,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -22,11 +22,11 @@
 		return;
 	}
 	if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
-		(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_ISA)) {
+		(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) {
 		uint32_t id;
 		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
 		if (id != (PCI_VENDOR_ID_INTEL | 
-				(PCI_DEVICE_ID_INTEL_82801ER_ISA << 16))) {
+				(PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) {
 			return;
 		}
 	}

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_lpc.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_lpc.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -388,5 +388,5 @@
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops    = &lpc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_ISA,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_LPC,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_sata.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_sata.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -52,12 +52,12 @@
 static const struct pci_driver sata_driver __pci_driver = {
 	.ops    = &sata_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_1F2_R,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_SATA,
 };
 
 static const struct pci_driver sata_driver_nr __pci_driver = {
 	.ops    = &sata_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_1F2,
+	.device = PCI_DEVICE_ID_INTEL_82801EB_SATA,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_uhci.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_uhci.c	2007-11-03 18:45:42 UTC (rev 2937)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801er/i82801er_uhci.c	2007-11-04 03:21:37 UTC (rev 2938)
@@ -39,7 +39,7 @@
 static const struct pci_driver uhci_driver __pci_driver = {
 	.ops    = &uhci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_USB,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_USB1,
 };
 
 static const struct pci_driver usb2_driver __pci_driver = {




From info at coresystems.de  Sun Nov  4 05:00:15 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 04 Nov 2007 05:00:15 +0100
Subject: [LinuxBIOS] r2938 build service
Message-ID: <E1IoWel-0000kU-RW@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2938 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements.

Use human-readable names for the PCI ID #defines.
Rename *_ISA to *_LPC as per datasheet.
The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error.

The fixes in southbridge code are only to keep the build working for now,
any real improvements will only go into the 82801xx code in future.

This is abuild-tested so it shouldn't break anything.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2938&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2938&device=serengeti_cheetah&vendor=amd
Configuration of asus:a8v-e_se is still broken
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2938&device=xe7501devkit&vendor=intel
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2938&device=dk8_htx&vendor=iwill
Compilation of via:epia-m is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2938&device=epia-m&vendor=via


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Sun Nov  4 05:04:01 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  4 Nov 2007 05:04:01 +0100
Subject: [LinuxBIOS] r2939 - trunk/LinuxBIOSv2/src/southbridge/via/vt8237r
Message-ID: <mailman.834.1355071196.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-11-04 05:04:01 +0100 (Sun, 04 Nov 2007)
New Revision: 2939

Modified:
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c
Log:
Various cosmetics, coding style fixes, constifications (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h	2007-11-04 04:04:01 UTC (rev 2939)
@@ -52,6 +52,7 @@
 
 	int ide0_enable:1;
 	int ide1_enable:1;
+
 	/* 1 = 80-pin cable */
 	int ide0_80pin_cable:1;
 	int ide1_80pin_cable:1;

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c	2007-11-04 04:04:01 UTC (rev 2939)
@@ -65,8 +65,7 @@
 	for (i = 0; i < 256; i += 16) {
 		printk_debug("%02x: ", i);
 		for (j = 0; j < 16; j++) {
-			printk_debug("%02x ",
-				     pci_read_config8(dev, i + j));
+			printk_debug("%02x ", pci_read_config8(dev, i + j));
 		}
 		printk_debug("\n");
 	}
@@ -75,7 +74,7 @@
 static void vt8237r_enable(struct device *dev)
 {
 	struct southbridge_via_vt8237r_config *sb =
-	(struct southbridge_via_vt8237r_config *) dev->chip_info;
+	    (struct southbridge_via_vt8237r_config *)dev->chip_info;
 
 	pci_write_config8(dev, 0x50, sb->fn_ctrl_lo);
 	pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h	2007-11-04 04:04:01 UTC (rev 2939)
@@ -20,43 +20,43 @@
 #ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
 #define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
 
-/* Static resources for the VT8237R southbridge. */
+/* Static resources for the VT8237R southbridge */
 
-#define VT8237R_APIC_ID		0x2
-#define VT8237R_ACPI_IO_BASE	0x500
-#define VT8237R_SMBUS_IO_BASE	0x400
+#define VT8237R_APIC_ID			0x2
+#define VT8237R_ACPI_IO_BASE		0x500
+#define VT8237R_SMBUS_IO_BASE		0x400
 /* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */
-#define VT8237R_ACPI_IRQ	0x9
-#define VT8237R_HPET_ADDR	0xfed00000ULL
-#define VT8237R_APIC_BASE	0xfec00000ULL
+#define VT8237R_ACPI_IRQ		0x9
+#define VT8237R_HPET_ADDR		0xfed00000ULL
+#define VT8237R_APIC_BASE		0xfec00000ULL
 
-/* IDE specific defines */
-#define IDE_CS		0x40
-#define IDE_CONF_I	0x41
-#define IDE_CONF_II	0x42
-#define IDE_CONF_FIFO	0x43
-#define IDE_MISC_I	0x44
-#define IDE_MISC_II	0x45
-#define IDE_UDMA	0x50
+/* IDE */
+#define IDE_CS				0x40
+#define IDE_CONF_I			0x41
+#define IDE_CONF_II			0x42
+#define IDE_CONF_FIFO			0x43
+#define IDE_MISC_I			0x44
+#define IDE_MISC_II			0x45
+#define IDE_UDMA			0x50
 
-/* SMBus specific */
+/* SMBus */
 #define VT8237R_POWER_WELL		0x94
 #define VT8237R_SMBUS_IO_BASE_REG	0xd0
 #define VT8237R_SMBUS_HOST_CONF		0xd2
 
-#define SMBHSTSTAT	(VT8237R_SMBUS_IO_BASE + 0x0)
-#define SMBSLVSTAT	(VT8237R_SMBUS_IO_BASE + 0x1)
-#define SMBHSTCTL	(VT8237R_SMBUS_IO_BASE + 0x2)
-#define SMBHSTCMD	(VT8237R_SMBUS_IO_BASE + 0x3)
-#define SMBXMITADD	(VT8237R_SMBUS_IO_BASE + 0x4)
-#define SMBHSTDAT0	(VT8237R_SMBUS_IO_BASE + 0x5)
+#define SMBHSTSTAT			(VT8237R_SMBUS_IO_BASE + 0x0)
+#define SMBSLVSTAT			(VT8237R_SMBUS_IO_BASE + 0x1)
+#define SMBHSTCTL			(VT8237R_SMBUS_IO_BASE + 0x2)
+#define SMBHSTCMD			(VT8237R_SMBUS_IO_BASE + 0x3)
+#define SMBXMITADD			(VT8237R_SMBUS_IO_BASE + 0x4)
+#define SMBHSTDAT0			(VT8237R_SMBUS_IO_BASE + 0x5)
 
-#define HOST_RESET 		0xff
+#define HOST_RESET 			0xff
 /* 1 in the 0 bit of SMBHSTADD states to READ. */
-#define READ_CMD		0x01
-#define SMBUS_TIMEOUT		(100 * 1000 * 10)
-#define I2C_TRANS_CMD		0x40
-#define CLOCK_SLAVE_ADDRESS	0x69
+#define READ_CMD			0x01
+#define SMBUS_TIMEOUT			(100 * 1000 * 10)
+#define I2C_TRANS_CMD			0x40
+#define CLOCK_SLAVE_ADDRESS		0x69
 
 #if DEBUG_SMBUS == 1
 #define PRINT_DEBUG(x)		print_debug(x)

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c	2007-11-04 04:04:01 UTC (rev 2939)
@@ -40,18 +40,18 @@
 	dump_south(dev);
 }
 
-static struct device_operations bridge_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.enable = bridge_enable,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = 0,
+static const struct device_operations bridge_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.enable			= bridge_enable,
+	.scan_bus		= pci_scan_bridge,
+	.reset_bus		= pci_bus_reset,
+	.ops_pci		= 0,
 };
 
-static struct pci_driver northbridge_driver __pci_driver = {
-	.ops = &bridge_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
+static const struct pci_driver northbridge_driver __pci_driver = {
+	.ops	= &bridge_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8T890CE_BR,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2007-11-04 04:04:01 UTC (rev 2939)
@@ -26,15 +26,15 @@
 /**
  * Print an error, should it occur. If no error, just exit.
  *
- * @param host_status The data returned on the host status register after a
- * transaction is processed.
+ * @param host_status The data returned on the host status register after
+ *		      a transaction is processed.
  * @param loops The number of times a transaction was attempted.
  */
 static void smbus_print_error(u8 host_status, int loops)
 {
 	/* Check if there actually was an error. */
 	if ((host_status == 0x00 || host_status == 0x40 ||
-	    host_status == 0x42) && (loops < SMBUS_TIMEOUT))
+	     host_status == 0x42) && (loops < SMBUS_TIMEOUT))
 		return;
 
 	if (loops >= SMBUS_TIMEOUT)
@@ -46,13 +46,13 @@
 	if (host_status & (1 << 2))
 		print_err("Device error\r\n");
 	if (host_status & (1 << 1))
-		print_debug("Interrupt/SMI# Completed Successfully\r\n");
+		print_debug("Interrupt/SMI# completed successfully\r\n");
 	if (host_status & (1 << 0))
 		print_err("Host busy\r\n");
 }
 
 /**
- * Wait for the smbus to become ready to process the next transaction
+ * Wait for the SMBus to become ready to process the next transaction.
  */
 static void smbus_wait_until_ready(void)
 {
@@ -64,15 +64,17 @@
 	/* Yes, this is a mess, but it's the easiest way to do it. */
 	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
 		++loops;
+
 	smbus_print_error(inb(SMBHSTSTAT), loops);
 }
 
 /**
- * Reset and take ownership of the smbus
+ * Reset and take ownership of the SMBus.
  */
 static void smbus_reset(void)
 {
 	outb(HOST_RESET, SMBHSTSTAT);
+
 	/* Datasheet says we have to read it to take ownership of SMBus. */
 	inb(SMBHSTSTAT);
 
@@ -82,10 +84,10 @@
 }
 
 /**
- * Read a byte from the smbus
+ * Read a byte from the SMBus.
  *
- * @param dimm The address location of the dimm on the smbus
- * @param offset The offset the data is located at
+ * @param dimm The address location of the DIMM on the SMBus.
+ * @param offset The offset the data is located at.
  */
 u8 smbus_read_byte(u8 dimm, u8 offset)
 {
@@ -98,6 +100,7 @@
 	PRINT_DEBUG("\r\n");
 
 	smbus_reset();
+
 	/* Clear host data port. */
 	outb(0x00, SMBHSTDAT0);
 	SMBUS_DELAY();
@@ -108,11 +111,10 @@
 	dimm |= 1;
 	outb(dimm, SMBXMITADD);
 	outb(offset, SMBHSTCMD);
+
 	/* Start transaction, byte data read. */
 	outb(0x48, SMBHSTCTL);
-
 	SMBUS_DELAY();
-
 	smbus_wait_until_ready();
 
 	val = inb(SMBHSTDAT0);
@@ -138,18 +140,18 @@
 				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
 
 	if (dev == PCI_DEV_INVALID)
-		die("Power Management Controller not found\r\n");
+		die("Power management controller not found\r\n");
 
 	/* 7 = SMBus Clock from RTC 32.768KHz
 	 * 5 = Internal PLL reset from susp
 	 */
 	pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0);
 
-	/* Enable SMBus */
+	/* Enable SMBus. */
 	pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG,
-				VT8237R_SMBUS_IO_BASE | 0x1);
+			   VT8237R_SMBUS_IO_BASE | 0x1);
 
-	/* SMBus Host Configuration, enable */
+	/* SMBus Host Configuration, enable. */
 	pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01);
 
 	/* Make it work for I/O. */
@@ -162,17 +164,17 @@
 }
 
 /**
- * A fixup for some systems that need time for the smbus to "warm up". This is 
- * needed on some vt823x based systems, where the smbus spurts out bad data for 
- * a short time after power on. This has been seen on the Via Epia-series and 
+ * A fixup for some systems that need time for the SMBus to "warm up". This is 
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for 
+ * a short time after power on. This has been seen on the VIA Epia series and 
  * Jetway J7F2-series. It reads the ID byte from SMBus, looking for 
  * known-good data from a slot/address. Exits on either good data or a timeout.
  *
- * This should probably go into some global file, but one would need to be 
- * created just for it. If some other chip needs/wants it, we can worry about it
- * then.
+ * TODO: This should probably go into some global file, but one would need to
+ *       be created just for it. If some other chip needs/wants it, we can
+ *       worry about it then.
  *
- * @param ctrl The memory controller and smbus addresses
+ * @param ctrl The memory controller and SMBus addresses.
  */
 void smbus_fixup(const struct mem_controller *ctrl)
 {
@@ -181,24 +183,31 @@
 
 	ram_slots = ARRAY_SIZE(ctrl->channel0);
 	if (!ram_slots) {
-		print_err("smbus_fixup thinks there are no ram slots!\r\n");
+		print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
 		return;
 	}
-	
-	PRINT_DEBUG("Waiting for smbus to warm up");
-		
-	/* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for the
-	 * ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
-	 * vt8237r has only been seen on DDR and DDR2 based systems, so far */
-	for(i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || 
-			(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++)
-	{
-		if (current_slot > ram_slots) current_slot = 0;
-		result = smbus_read_byte(ctrl->channel0[current_slot], 
-							SPD_MEMORY_TYPE);
+
+	PRINT_DEBUG("Waiting for SMBus to warm up");
+
+	/*
+	 * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
+	 * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
+	 * VT8237R has only been seen on DDR and DDR2 based systems, so far.
+	 */
+	for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
+				(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
+
+		if (current_slot > ram_slots)
+			current_slot = 0;
+
+		result = smbus_read_byte(ctrl->channel0[current_slot],
+					 SPD_MEMORY_TYPE);
 		current_slot++;
 		PRINT_DEBUG(".");
 	}
-	if (i >= SMBUS_TIMEOUT)	print_err("SMBus timed out while warming up\r\n");
-	else PRINT_DEBUG("Done\r\n");	
+
+	if (i >= SMBUS_TIMEOUT)
+		print_err("SMBus timed out while warming up\r\n");
+	else
+		PRINT_DEBUG("Done\r\n");
 }

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c	2007-11-04 04:04:01 UTC (rev 2939)
@@ -34,7 +34,7 @@
 static void ide_init(struct device *dev)
 {
 	struct southbridge_via_vt8237r_config *sb =
-	(struct southbridge_via_vt8237r_config *) dev->chip_info;
+	    (struct southbridge_via_vt8237r_config *)dev->chip_info;
 
 	u8 enables;
 	u32 cablesel;
@@ -52,7 +52,7 @@
 	/* Enable only compatibility mode. */
 	enables = pci_read_config8(dev, IDE_CONF_II);
 	enables &= ~0xc0;
-	pci_write_config8(dev,IDE_CONF_II, enables);
+	pci_write_config8(dev, IDE_CONF_II, enables);
 	enables = pci_read_config8(dev, IDE_CONF_II);
 	printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
 
@@ -84,7 +84,7 @@
 
 	/* Cable guy... */
 	cablesel = pci_read_config32(dev, IDE_UDMA);
-	cablesel &= ~((1 << 28) | (1 << 20) | (1 <<12) | (1 << 4));
+	cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
 	cablesel |= (sb->ide0_80pin_cable << 28) |
 		    (sb->ide0_80pin_cable << 20) |
 		    (sb->ide1_80pin_cable << 12) |
@@ -92,17 +92,17 @@
 	pci_write_config32(dev, IDE_UDMA, cablesel);
 }
 
-static struct device_operations ide_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = ide_init,
-	.enable = 0,
-	.ops_pci = 0,
+static const struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.enable			= 0,
+	.ops_pci		= 0,
 };
 
-static struct pci_driver northbridge_driver __pci_driver = {
-	.ops = &ide_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_82C586_1,
+static const struct pci_driver northbridge_driver __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_82C586_1,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2007-11-04 04:04:01 UTC (rev 2939)
@@ -90,7 +90,7 @@
 
 	/* All delivered to CPU0. */
 	ioapic_table[0].value_high = (lapicid()) << (56 - 32);
-	l = (unsigned long *) ioapic_base;
+	l = (unsigned long *)ioapic_base;
 
 	/* Set APIC to FSB message bus. */
 	l[0] = 0x3;
@@ -335,16 +335,16 @@
 	init_keyboard(dev);
 }
 
-static struct device_operations vt8237r_lpc_ops = {
-	.read_resources = vt8237r_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = vt8237r_enable_resources,
-	.init = &southbridge_init,
-	.scan_bus = scan_static_bus,
+static const struct device_operations vt8237r_lpc_ops = {
+	.read_resources		= vt8237r_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= vt8237r_enable_resources,
+	.init			= &southbridge_init,
+	.scan_bus		= scan_static_bus,
 };
 
-static struct pci_driver lpc_driver __pci_driver = {
-	.ops = &vt8237r_lpc_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_VT8237R_LPC,
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops	= &vt8237r_lpc_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT8237R_LPC,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c	2007-11-04 03:21:37 UTC (rev 2938)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c	2007-11-04 04:04:01 UTC (rev 2939)
@@ -42,17 +42,17 @@
 	pci_write_config8(dev, SATA_MISC_CTRL, reg);
 }
 
-static struct device_operations sata_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = sata_init,
-	.enable = 0,
-	.ops_pci = 0,
+static const struct device_operations sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= sata_init,
+	.enable			= 0,
+	.ops_pci		= 0,
 };
 
-static struct pci_driver northbridge_driver __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_VT6420_SATA,
+static const struct pci_driver northbridge_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT6420_SATA,
 };




From info at coresystems.de  Sun Nov  4 05:42:31 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 04 Nov 2007 05:42:31 +0100
Subject: [LinuxBIOS] r2939 build service
Message-ID: <E1IoXJf-0007nc-JP@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "uwe" checked in revision 2939 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Various cosmetics, coding style fixes, constifications (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2939&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2939&device=serengeti_cheetah&vendor=amd
Configuration of asus:a8v-e_se is still broken
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2939&device=xe7501devkit&vendor=intel
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2939&device=dk8_htx&vendor=iwill
Compilation of via:epia-m is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2939&device=epia-m&vendor=via


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From rminnich at gmail.com  Sun Nov  4 07:37:07 2007
From: rminnich at gmail.com (ron minnich)
Date: Sat, 3 Nov 2007 23:37:07 -0700
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <472C7882.2060109@gmx.net>
References: <001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw> <4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
	<009201c81d05$27559020$0200a8c0@sis.com.tw> <472BC9EE.1010200@gmx.net>
	<472C7882.2060109@gmx.net>
Message-ID: <13426df10711032337r7eb3b21at63745d6cd11d669c@mail.gmail.com>

I find myself, once again, very happy to see the LinuxBIOS community
jumping in and helping with the integration of this new mainboard into
the LinuxBIOS code base.

I always enjoy watching this process once it takes off, and, with the
contributions you have all started to make, we can see that this board
is going to be one of the best in our list of supported boards.

Thanks to SiS for creating this board. Thanks to AMD for their
continuing support. Thanks to Gigabyte for selling it (we'll buy them
as soon as they are available -- I already have a case waiting!).

Thanks to you all. Great work everyone!

Ron



From svn at openbios.org  Sun Nov  4 17:25:05 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  4 Nov 2007 17:25:05 +0100
Subject: [LinuxBIOS] r2940 - trunk/LinuxBIOSv2/src/mainboard/agami/aruma
Message-ID: <mailman.835.1355071196.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-04 17:25:05 +0100 (Sun, 04 Nov 2007)
New Revision: 2940

Modified:
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c
Log:
merge changes to match agami's production environment

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb	2007-11-04 04:04:01 UTC (rev 2939)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb	2007-11-04 16:25:05 UTC (rev 2940)
@@ -247,8 +247,8 @@
 #default TTYS0_BAUD=115200
 #default TTYS0_BAUD=57600
 #default TTYS0_BAUD=38400
-default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=19200
+default TTYS0_BAUD=9600
 #default TTYS0_BAUD=4800
 #default TTYS0_BAUD=2400
 #default TTYS0_BAUD=1200

Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c	2007-11-04 04:04:01 UTC (rev 2939)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c	2007-11-04 16:25:05 UTC (rev 2940)
@@ -1,4 +1,5 @@
 #define ASSEMBLY 1
+#define ASM_CONSOLE_LOGLEVEL 3
 #define __ROMCC__
 
 #define RAMINIT_SYSINFO 0




From svn at openbios.org  Sun Nov  4 17:50:27 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  4 Nov 2007 17:50:27 +0100
Subject: [LinuxBIOS] r2941 - in trunk/LinuxBIOSv2/src: mainboard/agami/aruma
	mainboard/amd/serengeti_cheetah mainboard/intel/xe7501devkit
	mainboard/iwill/dk8_htx mainboard/via/epia-m northbridge/via/vt8623
Message-ID: <mailman.836.1355071196.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-04 17:50:27 +0100 (Sun, 04 Nov 2007)
New Revision: 2941

Modified:
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables.c
   trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
   trunk/LinuxBIOSv2/src/mainboard/intel/xe7501devkit/acpi_tables.c
   trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c
   trunk/LinuxBIOSv2/src/mainboard/via/epia-m/acpi_tables.c
   trunk/LinuxBIOSv2/src/northbridge/via/vt8623/northbridge.c
Log:
Add dummy function for MCFG on those mainboards that provide ACPI but don't 
have PCIe MMCONFIG.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables.c	2007-11-04 16:25:05 UTC (rev 2940)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables.c	2007-11-04 16:50:27 UTC (rev 2941)
@@ -65,6 +65,11 @@
 extern unsigned hcdn[];
 extern unsigned sbdnx[7];	// for all 8131
 
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
 
 unsigned long acpi_fill_madt(unsigned long current)
 {

Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	2007-11-04 16:25:05 UTC (rev 2940)
+++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	2007-11-04 16:50:27 UTC (rev 2941)
@@ -48,6 +48,12 @@
 
 #define IO_APIC_ADDR	0xfec00000UL
 
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
 unsigned long acpi_fill_madt(unsigned long current)
 {
 	unsigned int gsi_base=0x18;

Modified: trunk/LinuxBIOSv2/src/mainboard/intel/xe7501devkit/acpi_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/intel/xe7501devkit/acpi_tables.c	2007-11-04 16:25:05 UTC (rev 2940)
+++ trunk/LinuxBIOSv2/src/mainboard/intel/xe7501devkit/acpi_tables.c	2007-11-04 16:50:27 UTC (rev 2941)
@@ -14,10 +14,16 @@
 #include "bus.h"
 #include "ioapic.h"
 
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
 unsigned long acpi_fill_srat(unsigned long current)
 {
 	// Not implemented
-	return 0;
+	return current;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)

Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c	2007-11-04 16:25:05 UTC (rev 2940)
+++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c	2007-11-04 16:50:27 UTC (rev 2941)
@@ -49,6 +49,13 @@
 
 #define IO_APIC_ADDR	0xfec00000UL
 
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+
 unsigned long acpi_fill_madt(unsigned long current)
 {
 	unsigned int gsi_base=0x18;

Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/acpi_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/acpi_tables.c	2007-11-04 16:25:05 UTC (rev 2940)
+++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/acpi_tables.c	2007-11-04 16:50:27 UTC (rev 2941)
@@ -13,14 +13,23 @@
 
 extern unsigned char AmlCode[];
 
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Nothing to do */
+	return current;
+}
+
+
 unsigned long acpi_fill_madt(unsigned long current)
 {
 	/* Nothing to do */
+	return current;
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
 	/* No NUMA, no SRAT */
+	return current;
 }
 
 unsigned long write_acpi_tables(unsigned long start)

Modified: trunk/LinuxBIOSv2/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/via/vt8623/northbridge.c	2007-11-04 16:25:05 UTC (rev 2940)
+++ trunk/LinuxBIOSv2/src/northbridge/via/vt8623/northbridge.c	2007-11-04 16:50:27 UTC (rev 2941)
@@ -20,6 +20,7 @@
  * slower than normal, ethernet drops packets).
  * Apparently these registers govern some sort of bus master behavior.
  */
+#if 0
 static void dump_dev(device_t dev)
 {
 	int i,j;
@@ -32,6 +33,8 @@
 		printk_debug("\n");
 	}
 }
+#endif
+
 static void northbridge_init(device_t dev) 
 {
 	device_t fb_dev;




From info at coresystems.de  Sun Nov  4 18:04:18 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 04 Nov 2007 18:04:18 +0100
Subject: [LinuxBIOS] r2940 build service
Message-ID: <E1IoitW-0005My-Cr@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2940 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
merge changes to match agami's production environment

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2940&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2940&device=serengeti_cheetah&vendor=amd
Configuration of asus:a8v-e_se is still broken
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2940&device=xe7501devkit&vendor=intel
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2940&device=dk8_htx&vendor=iwill
Compilation of via:epia-m is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2940&device=epia-m&vendor=via


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Sun Nov  4 18:29:02 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  4 Nov 2007 18:29:02 +0100
Subject: [LinuxBIOS] r2942 - trunk/LinuxBIOSv2/targets/asus/a8v-e_se
Message-ID: <mailman.837.1355071196.16123.coreboot@coreboot.org>

Author: cozzie
Date: 2007-11-04 18:29:01 +0100 (Sun, 04 Nov 2007)
New Revision: 2942

Modified:
   trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb
Log:
Small fix to make abuild happy on the asus/a8v-e_se (trivial)

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Modified: trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb	2007-11-04 16:50:27 UTC (rev 2941)
+++ trunk/LinuxBIOSv2/targets/asus/a8v-e_se/Config.lb	2007-11-04 17:29:01 UTC (rev 2942)
@@ -17,7 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-target a8v-e_se
+target asus_a8v-e_se
 mainboard asus/a8v-e_se
 
 romimage "normal"




From r.marek at assembler.cz  Sun Nov  4 19:27:08 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 04 Nov 2007 19:27:08 +0100
Subject: [LinuxBIOS] [PATCH] Add ACPI MCFG table (resend)
In-Reply-To: <472B9C4A.2010309@assembler.cz>
References: <472B9C4A.2010309@assembler.cz>
Message-ID: <472E0EFC.2040803@assembler.cz>

Hi all,

This seems to be already in SVN, but breaks the build, because on other boards
acpi_fill_mcfg is not defined.

Following patch solves that.

I declared it weak symbol, so it works even if it is not there. Its only compile
tested for VIA epia-m and ASUS a8v-e se.

Perhaps this function should be only a wrapper in mb code for some kind of
chipset specific mmconfig fill function.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>


Rudolf
-------------- next part --------------
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From info at coresystems.de  Sun Nov  4 19:49:57 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 04 Nov 2007 19:49:57 +0100
Subject: [LinuxBIOS] r2941 build service
Message-ID: <E1IokXl-0000K9-2w@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2941 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Add dummy function for MCFG on those mainboards that provide ACPI but don't
have PCIe MMCONFIG.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2941&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah has been fixed
Configuration of asus:a8v-e_se is still broken
Compilation of intel:xe7501devkit has been fixed
Compilation of iwill:dk8_htx has been fixed
Compilation of via:epia-m has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Sun Nov  4 20:03:43 2007
From: svn at openbios.org (svn at openbios.org)
Date: Sun,  4 Nov 2007 20:03:43 +0100
Subject: [LinuxBIOS] r2943 - trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se
Message-ID: <mailman.838.1355071196.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-04 20:03:42 +0100 (Sun, 04 Nov 2007)
New Revision: 2943

Modified:
   trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb
Log:
another small abuild fix.. add payload compression "uses" for the a8v-e-se

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb	2007-11-04 17:29:01 UTC (rev 2942)
+++ trunk/LinuxBIOSv2/src/mainboard/asus/a8v-e_se/Options.lb	2007-11-04 19:03:42 UTC (rev 2943)
@@ -95,6 +95,9 @@
 #bx_b005+
 uses SB_HT_CHAIN_ON_BUS0
 
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes
 default ROM_SIZE=512 * 1024




From juergen127 at kreuzholzen.de  Sun Nov  4 20:12:39 2007
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Sun, 4 Nov 2007 20:12:39 +0100
Subject: [LinuxBIOS] [PATCH] Adding AXUS TC320 LinuxBIOSv2 support
In-Reply-To: <20071026145413.GB7454@greenwood>
References: <200710242115.47691.juergen127@kreuzholzen.de>
	<20071026145413.GB7454@greenwood>
Message-ID: <200711042012.40361.juergen127@kreuzholzen.de>

Hi Uwe,

On Friday 26 October 2007 16:54, Uwe Hermann wrote:
> On Wed, Oct 24, 2007 at 09:15:47PM +0200, Juergen Beisert wrote:
> > This patch adds the AXUS TC320 to LinuxBIOSv2. This board uses nearly the
> > same devices than the BCOM Winnet100, so most of the new code here is
> > from the BCOM Winnet100. They differ in the IRQ routing table only.
> >
> > BTW: The AXUS board uses standard DIMM memory and can be run at 100MHz
> > SDRAM clock speed (it runs reliably here since month).
> >
> > Signed-off-by: Juergen Beisert <juergen at kreuzholzen.de>
>
> Thanks, committed in r2898 with some minor changes.
> Please let me know if I broke something ;)

Currently I cannot check your changes in LB because the TC320 is a "production 
system". It works as my main fileserver...

> Can you please post the output of 'lspci -tvnn' here (as well as update
> the wiki page with that info, instead of 'lspci -tv').
>
> I'd also like to check and compare the 'superiotool -dV' output from the
> regular BIOS and LinuxBIOS on this board, but the PC97317 is not yet
> supported... Feel free to add support if you have some spare time, or
> maybe I'll do it one of these days, we'll see.
>
> > +chip northbridge/amd/gx1
> > +  device pci_domain 0 on
> > +    device pci 0.0 on end
> > +      chip southbridge/amd/cs5530
> > +        device pci 12.0 on
>
> No NIC on this board? 0f.0 seem to be the onboard NIC, it should also be
> listed here.

Yes, NIC is on board. But 0e.0 is the correct one. I'm not sure why my system 
works with this setting...

> > +          chip superio/nsc/pc97317
> > +            device pnp 2e.0 on		# PS/2 keyboard
> > +              io 0x60 = 0x60
> > +              io 0x62 = 0x64
> > +              irq 0x70 = 1
> > +            end
> > +            device pnp 2e.1 on		# PS/2 mouse
> > +              irq 0x70 = 12
> > +            end
> > +            device pnp 2e.2 on		# RTC
> > +              io 0x60 = 0x70
> > +              irq 0x70 = 8
> > +            end
> > +            device pnp 2e.3 off		# Floppy
> > +            end
>
> No connector, correct?

Yes.

> > +            device pnp 2e.4 on		# Parallel port
> > +              io 0x60 = 0x378
> > +              irq 0x70 = 7
> > +            end
> > +            device pnp 2e.5 off		# COM2
>
> Why off? No connector on the board? Is it used for a smartcard reader or
> similar like on the BCOM WinNET100? If so, we should enable it.

Ups, both COMs are present at the backplane. So both should be on.

> > +              io 0x60 = 0x2f8
> > +              irq 0x70 = 3
> > +            end
> > +            device pnp 2e.6 on		# COM1
> > +              io 0x60 = 0x3f8
> > +              irq 0x70 = 4
> > +            end
> > +            device pnp 2e.7 on		# GPIO
> > +              io 0x60 = 0xe0
>
> Is 0xe0 correct? (superiotool -dV is useful for this type of info).

Don't know how to check the GPIO feature.

> > +            end
> > +            device pnp 2e.8 on		# Power management
> > +               io 0x60 = 0xe800
>
> Dito here. I'm not sure if it should be 0xe800 or 0x00e8, check
> superiotool if possible.

No superiotool, no check... ;.)

> > +            end
> > +            register "com1" = "{115200}"
> > +            register "com2" = "{38400}"
>
> I dropped this, likely not needed.
>
> > +          end
> > +        device pci 12.1 off end		# SMI
> > +        device pci 12.2 off end		# IDE
>
> IMO we should enable both SMI and IDE.
>
> Is there audio on this board, i.e. will SMI be needed? Any IDE
> connectors (be it 2.5" or 3.5" or CF)? If so it should be enabled here.

Yes. 2mm 2.5" 44 pin connector. Audio also, but works only with an SMI polling 
driver. Is someone interested in testing my new shiny SMI polling Audio on 
GX1 (currently audio out only)?

> Please also re-check the wiki page for copy-paste remainders from the
> BCOM WinNET100 page, some of the status entries might not be correct (e.g.
> the 'Tested with 2.5" drive' is from me on the BCOM, not sure if it's
> valid for the AXUS TC320.

Mostly done.

Juergen



From info at coresystems.de  Sun Nov  4 20:38:46 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 04 Nov 2007 20:38:46 +0100
Subject: [LinuxBIOS] r2942 build service
Message-ID: <E1IolJ0-00083B-FM@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "cozzie" checked in revision 2942 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
Small fix to make abuild happy on the asus/a8v-e_se (trivial)

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2942&device=aruma&vendor=agami
Configuration of asus:a8v-e_se is still broken


If something broke during this checkin please be a pain 
in cozzie's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From info at coresystems.de  Sun Nov  4 21:23:21 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Sun, 04 Nov 2007 21:23:21 +0100
Subject: [LinuxBIOS] r2943 build service
Message-ID: <E1Iom09-0006jR-Ig@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2943 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
another small abuild fix.. add payload compression "uses" for the a8v-e-se

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2943&device=aruma&vendor=agami
Configuration of asus:a8v-e_se has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From svn at openbios.org  Mon Nov  5 00:37:44 2007
From: svn at openbios.org (svn at openbios.org)
Date: Mon,  5 Nov 2007 00:37:44 +0100
Subject: [LinuxBIOS] r2944 - trunk/LinuxBIOSv2/src/mainboard/agami/aruma
Message-ID: <mailman.839.1355071196.16123.coreboot@coreboot.org>

Author: stepan
Date: 2007-11-05 00:37:44 +0100 (Mon, 05 Nov 2007)
New Revision: 2944

Modified:
   trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c
Log:
make agami aruma compile again. 

Rudolf's suggestion making the symbol weak is elegant, but let's allow
some more discussion.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c	2007-11-04 19:03:42 UTC (rev 2943)
+++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c	2007-11-04 23:37:44 UTC (rev 2944)
@@ -14,6 +14,13 @@
 
 extern unsigned char AmlCode[];
 
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+
 #define IO_APIC_ADDR	0xfec00000UL
 
 unsigned long acpi_fill_madt(unsigned long current)




From info at coresystems.de  Mon Nov  5 01:20:38 2007
From: info at coresystems.de (LinuxBIOS information)
Date: Mon, 05 Nov 2007 01:20:38 +0100
Subject: [LinuxBIOS] r2944 build service
Message-ID: <E1Iophm-0002Xk-E4@khepri.openbios.org>

Dear LinuxBIOS readers!

This is the automated build check service of LinuxBIOS.

The developer "stepan" checked in revision 2944 to
the LinuxBIOS source repository and caused the following 
changes:

Change Log:
make agami aruma compile again.

Rudolf's suggestion making the symbol weak is elegant, but let's allow
some more discussion.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     LinuxBIOS automatic build system





From my_tsai at sis.com  Mon Nov  5 11:46:56 2007
From: my_tsai at sis.com (Morgan Tsai /SiS)
Date: Mon, 5 Nov 2007 18:46:56 +0800
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
References: <13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>
	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>
	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
	<009201c81d05$27559020$0200a8c0@sis.com.tw>
	<20071103022138.331.qmail@stuge.se>
Message-ID: <008f01c81f99$31d04810$0200a8c0@sis.com.tw>

Dear Peter,

Thanks for your opinion. The build number I wrote means the latest revision 
when I mail to mailing list.



Morgan

----- Original Message ----- 
From: "Peter Stuge" <peter at stuge.se>
To: "Morgan Tsai /SiS" <my_tsai at sis.com>
Cc: "Dennis Chang /SiS" <ktchang at sis.com>; "Ray Wang /SiS" 
<ray_wang at sis.com>; "Eric Lin /SiS" <ericlin at sis.com>; 
<linuxbios at linuxbios.org>
Sent: Saturday, November 03, 2007 10:21 AM
Subject: Re: [LinuxBIOS] GIGABYTE GA-2761GXDK


> Hi Morgan!
>
>
> On Fri, Nov 02, 2007 at 12:02:06PM +0800, Morgan Tsai /SiS wrote:
>> Here is the redone patch by TortoiseSVN, please try it again.
>
> Thanks! I think most of these changes have been committed from your
> previous patch already.
>
>
>> The newest I have is 2925.
>
> I don't know if you already have a lot of experience with SVN, but it
> can merge your changes in your working copy with whatever changes
> that have been committed already in the svn update command. Note that
> it will never overwrite the changes you have made, only combine what
> can be combined, and mark conflicts where changes can not be
> combined.
>
> If you do an update as the last step (and resolving any conflicts)
> before generating a patch you have made sure that your patch is
> against the latest revision.
>
> Please do an update if there have already been changes made in the
> repo that affect the same files as your patch.
>
> Please confirm that you are subscribed to the mailing list by the
> way? Then I will only post to the list from now on.
>
>
> //Peter 




From my_tsai at sis.com  Mon Nov  5 11:53:56 2007
From: my_tsai at sis.com (Morgan Tsai /SiS)
Date: Mon, 5 Nov 2007 18:53:56 +0800
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
References: <001d01c8062e$4cdbbab0$0200a8c0@sis.com.tw>	<20071004025851.GA32267@greenwood>	<13426df10710101359h187e361cy696d168873bacd76@mail.gmail.com>	<004e01c80ca5$2551e3c0$dc00a8c0@sis.com.tw>	<Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>	<20071029210629.GB3642@coresystems.de>	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>	<4727205B.2040406@gmx.net>	<005501c81c82$23b72330$0200a8c0@sis.com.tw>	<20071101200216.GL21220@cosmic.amd.com>	<009201c81d05$27559020$0200a8c0@sis.com.tw>
	<472BC9EE.1010200@gmx.net> <472C7882.2060109@gmx.net>
Message-ID: <009401c81f9a$2ad49a60$0200a8c0@sis.com.tw>

Dear Carl-Daniel,

Code for 2761GXDK is ported from gigabyle/m57sli. There are many
dead code/function and find/replace error needed to clean up.

Thanks for your contribution.



Morgan

----- Original Message ----- 
From: "Carl-Daniel Hailfinger" <c-d.hailfinger.devel.2006 at gmx.net>
To: "Morgan Tsai /SiS" <my_tsai at sis.com>
Cc: "ron minnich" <rminnich at gmail.com>; "Stefan Reinauer" 
<stepan at coresystems.de>; "Dennis Chang /SiS" <ktchang at sis.com>; "Jordan 
Crouse" <jordan.crouse at amd.com>; "Ray Wang /SiS" <ray_wang at sis.com>; "Eric 
Lin /SiS" <ericlin at sis.com>; <linuxbios at linuxbios.org>
Sent: Saturday, November 03, 2007 9:32 PM
Subject: Re: [LinuxBIOS] GIGABYTE GA-2761GXDK


> Dear Morgan,
>
> please disregard my last patch. This patch is more complete and applies
> to current svn HEAD.
>
> * Change one PCI vendor ID from Nvidia to SiS
> * Remove dead code
> * Remove unused variables
> * Fix bug where array was one element too small
> * Fix error value truncation, the old code never entered the error path
> * Remove warnings
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c (Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c (Arbeitskopie)
> @@ -72,7 +72,6 @@
> {
>         uint8_t *base;
>         struct resource *res;
> -        uint32_t temp32;
>
>         print_debug("USB 2.0 INIT:---------->\n");
>
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c (Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c (Arbeitskopie)
> @@ -29,6 +29,7 @@
> #include <device/pci_ids.h>
> #include <device/pci_ops.h>
> #include <arch/io.h>
> +#include <delay.h>
> #include "sis966.h"
>
> uint8_t SiS_SiS7502_init[7][3]={
> @@ -236,13 +237,8 @@
>
> static void codecs_init(uint8_t *base, uint32_t codec_mask)
> {
> - int i;
>  codec_init(base, 0);
>  return;
> - for(i=2; i>=0; i--) {
> - if( codec_mask & (1<<i) )
> - codec_init(base, i);
> - }
> }
>
> static void aza_init(struct device *dev)
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c (Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c (Arbeitskopie)
> @@ -234,7 +234,6 @@
> static void sis966_lpc_read_resources(device_t dev)
> {
>  struct resource *res;
> - unsigned long index;
>
>  /* Get the normal pci resources of this device */
>  pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c (Revision 
> 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c 
> (Arbeitskopie)
> @@ -23,7 +23,7 @@
>
> #define SMBUS0_IO_BASE 0x8D0
>
> -static const uint8_t SiS_LPC_init[33][3]={
> +static const uint8_t SiS_LPC_init[34][3]={
> {0x04, 0xF8, 0x07}, //Reg 0x04
> {0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash
> {0x46, 0x00, 0x3D}, //Reg 0x46
> @@ -444,7 +444,6 @@
>   device_t dev;
>   msr_t msr;
>  int i;
> - uint32_t j;
>  uint8_t temp8;
>  uint16_t temp16;
>
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c (Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c (Arbeitskopie)
> @@ -111,13 +111,9 @@
>
> static void sata_init(struct device *dev)
> {
> - uint32_t dword;
>  struct southbridge_sis_sis966_config *conf;
>
>
> -struct resource *res;
> -uint16_t base;
> -uint8_t temp8;
>
>  conf = dev->chip_info;
>         print_debug("SATA_INIT:---------->\n");
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c (Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c (Arbeitskopie)
> @@ -102,7 +102,6 @@
>
> static void sis966_sm_read_resources(device_t dev)
> {
> - struct resource *res;
>  unsigned long index;
>
>  /* Get the normal pci resources of this device */
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c (Revision 
> 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c 
> (Arbeitskopie)
> @@ -23,14 +23,12 @@
> {
>  device_t dev;
>
> - /* Find the device.
> - */
> + /* Find the device. */
>  dev = pci_locate_device_on_bus(
> - PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_SIS_SIS966_HT),
> + PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_HT),
>  bus);
>
>  return (dev>>15) & 0x1f;
> -
> }
>
> static void hard_reset(void)
> @@ -41,6 +39,7 @@
>  outb(0x0a, 0x0cf9);
>  outb(0x0e, 0x0cf9);
> }
> +
> static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
> {
> /* default value for sis966 is good */
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c (Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c (Arbeitskopie)
> @@ -93,9 +93,7 @@
>
> static void set_apc(struct device *dev)
> {
> -    uint32_t tmp;
>     uint16_t addr;
> -    uint32_t idx;
>     uint16_t i;
>     uint8_t   bTmp;
>
> @@ -139,7 +137,7 @@
> #define LoopNum 200
> static  unsigned long ReadEEprom( struct device *dev,  uint32_t base, 
> uint32_t Reg)
> {
> -    uint16_t data;
> +    uint32_t data;
>     uint32_t i;
>     uint32_t ulValue;
>
> @@ -165,7 +163,7 @@
>     if(i==LoopNum)   data=0x10000;
>     else{
>     ulValue=readl(base+0x3c);
> -    data = (uint16_t)((ulValue & 0xffff0000) >> 16);
> +    data = ((ulValue & 0xffff0000) >> 16);
>     }
>
>     return data;
> @@ -174,11 +172,9 @@
> static int phy_read(uint32_t  base, unsigned phy_addr, unsigned phy_reg)
> {
>     uint32_t   ulValue;
> -    unsigned  loop = 0x100;
>     uint32_t   Read_Cmd;
>     uint16_t   usData;
>
> -    uint16_t   tmp;
>
>
>     Read_Cmd = ((phy_reg << 11) |
> @@ -188,16 +184,13 @@
>
>            // SmiMgtInterface Reg is the SMI management interface 
> register(offset 44h) of MAC
>           writel( Read_Cmd,base+0x44);
> -          //outl( Read_Cmd,tmp+0x44);
>
>            // Polling SMI_REQ bit to be deasserted indicated read command 
> completed
>            do
>            {
>         // Wait 20 usec before checking status
> -           //StallAndWait(20);
>     mdelay(20);
>            ulValue = readl(base+0x44);
> -           //ulValue = inl(tmp+0x44);
>            } while((ulValue & SMI_REQUEST) != 0);
>             //printk_debug("base %x cmd %lx ret val %lx\n", 
> tmp,Read_Cmd,ulValue);
>            usData=(ulValue>>16);
> @@ -213,7 +206,6 @@
> static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect()
> {
>     int               bFoundPhy = FALSE;
> -    uint32_t Read_Cmd;
>     uint16_t usData;
>     int        PhyAddress = 0;
>
> @@ -246,16 +238,10 @@
>
> static void nic_init(struct device *dev)
> {
> -        uint32_t dword, old;
> -        uint32_t mac_h, mac_l;
> -        int eeprom_valid = 0;
>         int val;
>         uint16_t  PhyAddr;
> -        struct southbridge_sis_sis966_config *conf;
> -        static uint32_t nic_index = 0;
>         uint32_t base;
>         struct resource *res;
> -        uint32_t reg;
>
>
>         print_debug("NIC_INIT:---------->\n");
> @@ -353,68 +339,7 @@
> print_debug("NIC_INIT:<----------\n");
> return;
>
> -#define RegStationMgtInf 0x44
> -#define PHY_RGMII 0x10000000
>
> - writel(PHY_RGMII, base + RegStationMgtInf);
> - conf = dev->chip_info;
> -
> - if(conf->mac_eeprom_smbus != 0) {
> -// read MAC address from EEPROM at first
> -
> - struct device *dev_eeprom;
> - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, 
> conf->mac_eeprom_addr);
> -
> - if(dev_eeprom) {
> - // if that is valid we will use that
> - unsigned char dat[6];
> - int status;
> - int i;
> - for(i=0;i<6;i++) {
> - status = smbus_read_byte(dev_eeprom, i);
> - if(status < 0) break;
> - dat[i] = status & 0xff;
> - }
> - if(status >= 0) {
> - mac_l = 0;
> - for(i=3;i>=0;i--) {
> - mac_l <<= 8;
> - mac_l += dat[i];
> - }
> - if(mac_l != 0xffffffff) {
> - mac_l += nic_index;
> - mac_h = 0;
> - for(i=5;i>=4;i--) {
> - mac_h <<= 8;
> - mac_h += dat[i];
> - }
> - eeprom_valid = 1;
> - }
> - }
> - }
> - }
> -
> -// if that is invalid we will read that from romstrap
> - if(!eeprom_valid) {
> - unsigned long mac_pos;
> - mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
> - mac_l = readl(mac_pos) + nic_index; // overflow?
> - mac_h = readl(mac_pos + 4);
> -
> - }
> -
> -// set that into NIC MMIO
> -#define NvRegMacAddrA 0xA8
> -#define NvRegMacAddrB 0xAC
> - writel(mac_l, base + NvRegMacAddrA);
> - writel(mac_h, base + NvRegMacAddrB);
> -
> - nic_index++;
> -
> -#if CONFIG_PCI_ROM_RUN == 1
> - pci_dev_init(dev);// it will init option rom
> -#endif
> -
> }
>
> static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned 
> device)
> @@ -436,6 +361,7 @@
> // .enable = sis966_enable,
>  .ops_pci = &lops_pci,
> };
> +
> static const struct pci_driver nic_driver __pci_driver = {
>  .ops = &nic_ops,
>  .vendor = PCI_VENDOR_ID_SIS,
> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c (Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c (Arbeitskopie)
> @@ -77,8 +77,6 @@
>
> static void sis761_read_resources(device_t dev)
> {
> - struct resource *resource;
> - unsigned char iommu;
>  /* Read the generic PCI resources */
>  printk_debug("sis761_read_resources\n");
>  pci_dev_read_resources(dev);
> @@ -91,56 +89,13 @@
>
>  return;
>
> - iommu = 1;
> - get_option(&iommu, "iommu");
> -
> - if (iommu) {
> - /* Add a Gart apeture resource */
> - resource = new_resource(dev, 0x94);
> - resource->size = iommu?AGP_APERTURE_SIZE:1;
> - resource->align = log2(resource->size);
> - resource->gran  = log2(resource->size);
> - resource->limit = 0xffffffff; /* 4G */
> - resource->flags = IORESOURCE_MEM;
> - }
> }
>
> static void set_agp_aperture(device_t dev)
> {
> - struct resource *resource;
>
>  return;
>
> - resource = probe_resource(dev, 0x94);
> - if (resource) {
> - device_t pdev;
> - uint32_t gart_base, gart_acr;
> -
> - /* Remember this resource has been stored */
> - resource->flags |= IORESOURCE_STORED;
> -
> - /* Find the size of the GART aperture */
> - gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
> -
> - /* Get the base address */
> - gart_base = ((resource->base) >> 25) & 0x00007fff;
> -
> - /* Update the other northbriges */
> - pdev = 0;
> - while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
> - /* Store the GART size but don't enable it */
> - pci_write_config32(pdev, 0x90, gart_acr);
> -
> - /* Store the GART base address */
> - pci_write_config32(pdev, 0x94, gart_base);
> -
> - /* Don't set the GART Table base address */
> - pci_write_config32(pdev, 0x98, 0);
> -
> - /* Report the resource has been stored... */
> - report_resource_stored(pdev, resource, " <gart>");
> - }
> - }
> }
>
> static void sis761_set_resources(device_t dev)
> @@ -156,9 +111,7 @@
>
> static void sis761_init(struct device *dev)
> {
> - uint32_t cmd, cmd_ref;
>  int needs_reset;
> - struct device *f0_dev, *f2_dev;
>  msr_t msr;
>
>
>
> 




From stepan at coresystems.de  Mon Nov  5 11:59:10 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 5 Nov 2007 11:59:10 +0100
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <472C7882.2060109@gmx.net>
References: <Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
	<009201c81d05$27559020$0200a8c0@sis.com.tw>
	<472BC9EE.1010200@gmx.net> <472C7882.2060109@gmx.net>
Message-ID: <20071105105910.GA29370@coresystems.de>

* Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [071103 14:32]:
> Dear Morgan,
> 
> please disregard my last patch. This patch is more complete and applies
> to current svn HEAD.
> 
> * Change one PCI vendor ID from Nvidia to SiS
> * Remove dead code
> * Remove unused variables
> * Fix bug where array was one element too small
> * Fix error value truncation, the old code never entered the error path
> * Remove warnings

Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/



From duwe at lst.de  Mon Nov  5 12:04:11 2007
From: duwe at lst.de (Torsten Duwe)
Date: Mon, 5 Nov 2007 12:04:11 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
Message-ID: <200711051204.12118.duwe@lst.de>

This patch makes both PCI slots and the primary PCIe work for me, sort of.
The only downsides are that under heavy usage I lose an interrupt once in a 
while, but this might be due to irqpoll.

The other issue is that the graphics card still only initialises under X, and 
still very slowly.

Looking at mptable.c I get the impression it was copied almost verbatim from 
another board and not adopted to the M57SLI. Yinghai, where did you get the 
routing info from?

Another scary thing is that the wiring seems to differ when the board is set 
up via LinuxBIOS; legacy BIOS puts the PCIe 16x int A on the same line with 
bus 1 device 8, while LinuxBIOS does that with bus 1 device 7 ! Can anyone 
with a datasheet shed some light on this?

Anyway, here's the patch that improves things quite a lot on my machine.

please SVN-quote only below this line :-)
------------------------------------------------------------------------------------------
Fix the M57SLI routing table, as apparently  set up from LinuxBIOS on that 
board. Shift PCIe pin numbers downwards, and PCI int pins upwards. This puts 
both PCI slots' int A and PCIe 16x int A into the right position.

Signed-off-by: Torsten Duwe <duwe at lst.de>
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From Marc.Jones at amd.com  Mon Nov  5 18:21:00 2007
From: Marc.Jones at amd.com (Marc Jones)
Date: Mon, 05 Nov 2007 10:21:00 -0700
Subject: [LinuxBIOS] r2944 build service
In-Reply-To: <E1Iophm-0002Xk-E4@khepri.openbios.org>
References: <E1Iophm-0002Xk-E4@khepri.openbios.org>
Message-ID: <472F50FC.8050607@AMD.com>

LinuxBIOS information wrote:
> Dear LinuxBIOS readers!
>
> This is the automated build check service of LinuxBIOS.
>
> The developer "stepan" checked in revision 2944 to
> the LinuxBIOS source repository and caused the following 
> changes:
>
> Change Log:
> make agami aruma compile again.
>
> Rudolf's suggestion making the symbol weak is elegant, but let's allow
> some more discussion.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
>
>
>
> Build Log:
> Compilation of agami:aruma has been fixed
>
>
> If something broke during this checkin please be a pain 
> in stepan's neck until the issue is fixed.
>
> If this issue is not fixed within 24h the revision should 
> be backed out.
>
>    Best regards,
>      LinuxBIOS automatic build system
>
>
>
>   
All platforms building without errors.
Stefan ++!!!!

Good job,
Marc



-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors 






From uwe at hermann-uwe.de  Mon Nov  5 21:09:45 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 5 Nov 2007 21:09:45 +0100
Subject: [LinuxBIOS] GIGABYTE GA-2761GXDK
In-Reply-To: <472C7882.2060109@gmx.net>
References: <Pine.LNX.4.64.0710120217120.5341@bigred.russwhit.org>
	<004801c81176$1d5c23d0$0200a8c0@sis.com.tw>
	<20071029210629.GB3642@coresystems.de>
	<005401c81ab9$3c139f50$0200a8c0@sis.com.tw>
	<4727205B.2040406@gmx.net>
	<005501c81c82$23b72330$0200a8c0@sis.com.tw>
	<20071101200216.GL21220@cosmic.amd.com>
	<009201c81d05$27559020$0200a8c0@sis.com.tw>
	<472BC9EE.1010200@gmx.net> <472C7882.2060109@gmx.net>
Message-ID: <20071105200944.GA10444@greenwood>

On Sat, Nov 03, 2007 at 02:32:51PM +0100, Carl-Daniel Hailfinger wrote:
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Looks good, just one more hint:


> Index: LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
> ===================================================================
> --- LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	(Revision 2935)
> +++ LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	(Arbeitskopie)
> @@ -77,8 +77,6 @@
>  
>  static void sis761_read_resources(device_t dev)
>  {
> -	struct resource *resource;
> -	unsigned char iommu;
>  	/* Read the generic PCI resources */
>  	printk_debug("sis761_read_resources\n");
>  	pci_dev_read_resources(dev);
> @@ -91,56 +89,13 @@
>  
>  	return;
>  
> -	iommu = 1;
> -	get_option(&iommu, "iommu");
> -
> -	if (iommu) {
> -		/* Add a Gart apeture resource */
> -		resource = new_resource(dev, 0x94);
> -		resource->size = iommu?AGP_APERTURE_SIZE:1;
> -		resource->align = log2(resource->size);
> -		resource->gran  = log2(resource->size);
> -		resource->limit = 0xffffffff; /* 4G */
> -		resource->flags = IORESOURCE_MEM;
> -	}
>  }
>  
>  static void set_agp_aperture(device_t dev)
>  {
> -	struct resource *resource;
>  
>  	return;
>  
> -	resource = probe_resource(dev, 0x94);
> -	if (resource) {
> -		device_t pdev;
> -		uint32_t gart_base, gart_acr;
> -
> -		/* Remember this resource has been stored */
> -		resource->flags |= IORESOURCE_STORED;
> -
> -		/* Find the size of the GART aperture */
> -		gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
> -
> -		/* Get the base address */
> -		gart_base = ((resource->base) >> 25) & 0x00007fff;
> -
> -		/* Update the other northbriges */
> -		pdev = 0;
> -		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
> -			/* Store the GART size but don't enable it */
> -			pci_write_config32(pdev, 0x90, gart_acr);
> -
> -			/* Store the GART base address */
> -			pci_write_config32(pdev, 0x94, gart_base);
> -
> -			/* Don't set the GART Table base address */
> -			pci_write_config32(pdev, 0x98, 0);
> -
> -			/* Report the resource has been stored... */
> -			report_resource_stored(pdev, resource, " <gart>");
> -		}
> -	}
>  }
>  
>  static void sis761_set_resources(device_t dev)
> @@ -156,9 +111,7 @@
>  
>  static void sis761_init(struct device *dev)
>  {
> -	uint32_t cmd, cmd_ref;
>  	int needs_reset;
> -	struct device *f0_dev, *f2_dev;
>  	msr_t	msr;

After all the above stuff is dropped almost no code is left in the file,
and what's left is pretty trivial. So please drop the following lines

----
 * written in 2003 by Eric Biederman
 *
 *  - Athlon64 workarounds by Stefan Reinauer
 *  - "reset once" logic by Yinghai Lu
----

(which don't really apply anymore) and only leave the (C) SiS in the file.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Mon Nov  5 21:12:49 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 5 Nov 2007 21:12:49 +0100
Subject: [LinuxBIOS] Stale payloads
In-Reply-To: <035401c81d7c$c78e6f90$1223040a@chimp>
References: <035401c81d7c$c78e6f90$1223040a@chimp>
Message-ID: <20071105201249.GB10444@greenwood>

On Fri, Nov 02, 2007 at 12:18:33PM -0600, Myles Watson wrote:
> I've been spinning my wheels because of a stale payload.
> 
> In the fallback directory, the payload file depends on the
> ../{../}*/payload.elf file.  If you change that to ../../payload.lzma.elf to
> retry, it won't get the new file if payload is newer than payload.lzma.elf.
> 
> 
> It seems like there are several possible fixes, but the one I like is
> changing buildtarget to remove the payload* files from normal, fallback,
> etc.  The problem is that it doesn't look like buildtarget knows about those
> directories.
> 
> Is there a better way?

If I understand you right, you want to change something in the code and
then rebuild an image? If so, I recommend to _always_ 'rm -rf BUILDDIR'
and re-do the "./buildtarget foo/bar" etc.

That's the safest thing to do, you can then be sure that no old stuff
is still left around and being incorrectly re-used. Yes, it's not really
elegant or fast, but it's the one thing that works for sure.


HTH, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Mon Nov  5 21:20:45 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 5 Nov 2007 21:20:45 +0100
Subject: [LinuxBIOS] r2926
	-	trunk/LinuxBIOSv2/src/mainboard/newisys/khepri
In-Reply-To: <E1Int8Z-0003yE-Fl@mi028.mc1.hosteurope.de>
References: <E1Int8Z-0003yE-Fl@mi028.mc1.hosteurope.de>
Message-ID: <20071105202045.GC10444@greenwood>

On Fri, Nov 02, 2007 at 10:48:15AM +0100, svn at openbios.org wrote:
> This patch fixes the superio of the khepri 2100e as detected:
> > superiotool r2922
> > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e

Just a small note:

Please don't trust superiotool entirely, it's better to cross-check with
sensors-detect and/or by actually looking at the board. Superiotool had
misdetection bugs in the past and may still have some left.


> -						chip superio/nsc/pc87360
> +						chip superio/winbond/w83627hf

OK, this is unlikely to be a bug in this case, it might happen that superiotool
misdetects the specific Winbond variant (I think such a bug still
exists at the moment), but misdetecting an NSC as Winbond sounds
unlikely. But please check the actual hardware if you can, just to be sure.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Mon Nov  5 21:23:30 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 5 Nov 2007 21:23:30 +0100
Subject: [LinuxBIOS] patch 2:corrected alix1c memory size
In-Reply-To: <13426df10710261010p75fac3f8n2df06b0eb1175d02@mail.gmail.com>
References: <13426df10710252055v35237b52kef97d995ade06034@mail.gmail.com>
	<20071026152032.GE7454@greenwood>
	<13426df10710260906l2782bn8aa0b80c2474436@mail.gmail.com>
	<13426df10710261010p75fac3f8n2df06b0eb1175d02@mail.gmail.com>
Message-ID: <20071105202330.GD10444@greenwood>

On Fri, Oct 26, 2007 at 10:10:37AM -0700, ron minnich wrote:
> Index: src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
> ===================================================================
> --- src/mainboard/pcengines/alix1c/cache_as_ram_auto.c  (revision 2899)
> +++ src/mainboard/pcengines/alix1c/cache_as_ram_auto.c  (working copy)
> @@ -86,7 +86,7 @@
>         [SPD_tRRD] = 10,
>  };
> 
> -static u8 spd_read_byte(unsigned device, unsigned address)
> +static u8 spd_read_byte(u8 device, u8 address)
>  {
>         print_debug("spd_read_byte dev ");
>         print_debug_hex8(device);

Looks good IMO. This was committed as r2924.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From myles at pel.cs.byu.edu  Mon Nov  5 21:25:26 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Mon, 5 Nov 2007 13:25:26 -0700
Subject: [LinuxBIOS] Stale payloads
In-Reply-To: <20071105201249.GB10444@greenwood>
References: <035401c81d7c$c78e6f90$1223040a@chimp>
	<20071105201249.GB10444@greenwood>
Message-ID: <005f01c81fea$00655b70$2402a8c0@chimp>



> On Fri, Nov 02, 2007 at 12:18:33PM -0600, Myles Watson wrote:
> > I've been spinning my wheels because of a stale payload.
> >
> > In the fallback directory, the payload file depends on the
> > ../{../}*/payload.elf file.  If you change that to
> ../../payload.lzma.elf to
> > retry, it won't get the new file if payload is newer than
> payload.lzma.elf.
> >
> >
> > It seems like there are several possible fixes, but the one I like is
> > changing buildtarget to remove the payload* files from normal, fallback,
> > etc.  The problem is that it doesn't look like buildtarget knows about
> those
> > directories.
> >
> > Is there a better way?
> 
> If I understand you right, you want to change something in the code and
> then rebuild an image? If so, I recommend to _always_ 'rm -rf BUILDDIR'
> and re-do the "./buildtarget foo/bar" etc.

Not just a change in the code, sometimes just a different payload (ADLO vs.
FILO), but it's the same dependency issue.

Given that you recommend _always_ removing the BUILDDIR, I think the best
thing to do is to put the 'rm -rf BUILDDIR' into buildtarget.  There's no
reason to make it two steps.  It makes sense that when you run buildtarget
that it takes care of the details to make it build.

> That's the safest thing to do, you can then be sure that no old stuff
> is still left around and being incorrectly re-used. Yes, it's not really
> elegant or fast, but it's the one thing that works for sure.

Is that on the wake?

Thanks,
Myles





From myles at pel.cs.byu.edu  Mon Nov  5 21:27:07 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Mon, 5 Nov 2007 13:27:07 -0700
Subject: [LinuxBIOS] Stale payloads
In-Reply-To: <005f01c81fea$00655b70$2402a8c0@chimp>
References: <035401c81d7c$c78e6f90$1223040a@chimp><20071105201249.GB10444@greenwood>
	<005f01c81fea$00655b70$2402a8c0@chimp>
Message-ID: <006601c81fea$3c905780$2402a8c0@chimp>

> Is that on the wake?
I meant Wiki. Spell check did me in.
Myles





From hanoi.santos at gmail.com  Mon Nov  5 21:45:55 2007
From: hanoi.santos at gmail.com (Hanoi Santos Hung)
Date: Mon, 5 Nov 2007 15:45:55 -0500
Subject: [LinuxBIOS] Problems with elfboot
Message-ID: <b25e2a480711051245h32b24485j869a774e258a0a60@mail.gmail.com>

Hi :
I'm working with this hardware configuration :
North  : vt8605
South  : vt82C686B
RAM : 128 MB SODIMM

I begin modifying the code from vt8601 and LinuxBIOS V1.0 version of
vt82c686 and I have my system working until it tries to load the
payload (filo). I think the problem was the memory, but
ram_check(0x00000000, 0xA0000);
ram_check(0x00100000, 0x8000000);

works perfectly, another symptom : when the board make a cold start it
freeze at "Jumping  to  LinuxBIOS".

I'll apreciate any help

Best Regards
  Ing. Hanoi Santos Hung
  Instituto Central de Investigaci?n Digital



From janek_listy at wp.pl  Mon Nov  5 22:04:59 2007
From: janek_listy at wp.pl (Janek Kozicki)
Date: Mon, 5 Nov 2007 22:04:59 +0100
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
Message-ID: <20071105220459.6e32496d@absurd>

Hi,

I just wanted to let you know about Phoenix company (news from slashdot).

My point is - we could check if they use LinuxBIOS and if so - do
they respect the license?

 "Phoenix Technologies, a developer of BIOS software, is working on a
  new technology called Hyperspace that will allow you to instantly
  load certain applications like email, web browser and media player,
  without loading windows. It could even lead to tailoring of computers
  to even more specific demographics, like a student laptop preloaded
  with word processor, email and an IM all available at the press of a
  button."

URL: http://www.phoenix.com/en/Home/default.htm

best regards
-- 
Janek Kozicki



From phs at deadc0.de  Mon Nov  5 22:25:29 2007
From: phs at deadc0.de (Philip Schulz)
Date: Mon, 05 Nov 2007 22:25:29 +0100
Subject: [LinuxBIOS] LinuxBIOS and FreeBSD
In-Reply-To: <20071025165440.GE28802@greenwood>
References: <4720ABCC.1000407@deadc0.de> <20071025165440.GE28802@greenwood>
Message-ID: <472F8A49.5020103@deadc0.de>

Hi,

On 10/25/07 18:54, Uwe Hermann wrote:
> On Thu, Oct 25, 2007 at 04:44:28PM +0200, Philip Schulz wrote:

[...]

>> Unfortunately, I have no idea how to detect FreeBSD from a Makefile or a 
>> Python script. But maybe someone on this list knows and wants enhance 
>> the patches so they can be included in the LinuxBIOS tree.
> 

[...]

> 
> Most of your patch is just make -> gmake, so it should be easy to use
> $(MAKE) everywhere and set that to "gmake" on FreeBSD and "make"
> everywhere else.
> 

It seems that on FreeBSD, ${MAKE} is set to the name of the binary you 
invoke (gnumake is a hard-link to gmake in this example):

[phs at thinkpad ~]$ cat Makefile
all:
        echo ${MAKE}

[phs at thinkpad ~]$ make
echo make
make
[phs at thinkpad ~]$ gmake
echo gmake
gmake
[phs at thinkpad ~]$ gnumake
echo gnumake
gnumake

Anyways, attached is an updated version of the initial patch. It hopefully 
doesn't brake builds on Linux and makes LinuxBIOS (and ADLO) compile on 
FreeBSD. Also, this uses "domainname" instead of "dnsdomainname" on FreeBSD.

Signed-off-by: Philip Schulz <phs at deadc0.de>

I hope this is the correct way to post a patch.

Regards,

  Philip



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From dhendrix at google.com  Mon Nov  5 23:02:48 2007
From: dhendrix at google.com (David Hendricks)
Date: Mon, 5 Nov 2007 14:02:48 -0800
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
In-Reply-To: <20071105220459.6e32496d@absurd>
References: <20071105220459.6e32496d@absurd>
Message-ID: <ec9b26620711051402v738fa891wb88d913fa0f13190@mail.gmail.com>

I haven't checked into this much, but one thing is for sure -- "instant on"
and EFI are oxymorons.

On Nov 5, 2007 1:04 PM, Janek Kozicki <janek_listy at wp.pl> wrote:

> Hi,
>
> I just wanted to let you know about Phoenix company (news from slashdot).
>
> My point is - we could check if they use LinuxBIOS and if so - do
> they respect the license?
>
>  "Phoenix Technologies, a developer of BIOS software, is working on a
>  new technology called Hyperspace that will allow you to instantly
>  load certain applications like email, web browser and media player,
>  without loading windows. It could even lead to tailoring of computers
>  to even more specific demographics, like a student laptop preloaded
>  with word processor, email and an IM all available at the press of a
>  button."
>
> URL: http://www.phoenix.com/en/Home/default.htm
>
> best regards
> --
> Janek Kozicki
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>
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From dhendrix at google.com  Mon Nov  5 23:05:00 2007
From: dhendrix at google.com (David Hendricks)
Date: Mon, 5 Nov 2007 14:05:00 -0800
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
In-Reply-To: <ec9b26620711051402v738fa891wb88d913fa0f13190@mail.gmail.com>
References: <20071105220459.6e32496d@absurd>
	<ec9b26620711051402v738fa891wb88d913fa0f13190@mail.gmail.com>
Message-ID: <ec9b26620711051405p4c612feaoc6a69bed178748d7@mail.gmail.com>

bleh

s/are oxymorons/is an oxymoron

On Nov 5, 2007 2:02 PM, David Hendricks <dhendrix at google.com> wrote:

> I haven't checked into this much, but one thing is for sure -- "instant
> on" and EFI are oxymorons.
>
>
> On Nov 5, 2007 1:04 PM, Janek Kozicki < janek_listy at wp.pl> wrote:
>
> > Hi,
> >
> > I just wanted to let you know about Phoenix company (news from
> > slashdot).
> >
> > My point is - we could check if they use LinuxBIOS and if so - do
> > they respect the license?
> >
> >  "Phoenix Technologies, a developer of BIOS software, is working on a
> >  new technology called Hyperspace that will allow you to instantly
> >  load certain applications like email, web browser and media player,
> >  without loading windows. It could even lead to tailoring of computers
> >  to even more specific demographics, like a student laptop preloaded
> >  with word processor, email and an IM all available at the press of a
> >  button."
> >
> > URL: http://www.phoenix.com/en/Home/default.htm
> >
> > best regards
> > --
> > Janek Kozicki
> >
> > --
> > linuxbios mailing list
> > linuxbios at linuxbios.org
> > http://www.linuxbios.org/mailman/listinfo/linuxbios
> >
>
>
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From svn at openbios.org  Mon Nov  5 23:21:27 2007
From: svn at openbios.org (svn at openbios.org)
Date: Mon,  5 Nov 2007 23:21:27 +0100
Subject: [LinuxBIOS] r2945 - trunk/LinuxBIOSv2/src/southbridge/sis/sis966
Message-ID: <mailman.840.1355071197.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2007-11-05 23:21:27 +0100 (Mon, 05 Nov 2007)
New Revision: 2945

Modified:
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c
Log:
* Change one PCI vendor ID from Nvidia to SiS
* Remove dead code
* Remove unused variables
* Fix bug where array was one element too small
* Fix error value truncation, the old code never entered the error path
* Remove warnings

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis761.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -77,8 +77,6 @@
 
 static void sis761_read_resources(device_t dev)
 {
-	struct resource *resource;
-	unsigned char iommu;
 	/* Read the generic PCI resources */
 	printk_debug("sis761_read_resources\n");
 	pci_dev_read_resources(dev);
@@ -91,56 +89,13 @@
 
 	return;
 
-	iommu = 1;
-	get_option(&iommu, "iommu");
-
-	if (iommu) {
-		/* Add a Gart apeture resource */
-		resource = new_resource(dev, 0x94);
-		resource->size = iommu?AGP_APERTURE_SIZE:1;
-		resource->align = log2(resource->size);
-		resource->gran  = log2(resource->size);
-		resource->limit = 0xffffffff; /* 4G */
-		resource->flags = IORESOURCE_MEM;
-	}
 }
 
 static void set_agp_aperture(device_t dev)
 {
-	struct resource *resource;
 
 	return;
 
-	resource = probe_resource(dev, 0x94);
-	if (resource) {
-		device_t pdev;
-		uint32_t gart_base, gart_acr;
-
-		/* Remember this resource has been stored */
-		resource->flags |= IORESOURCE_STORED;
-
-		/* Find the size of the GART aperture */
-		gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
-
-		/* Get the base address */
-		gart_base = ((resource->base) >> 25) & 0x00007fff;
-
-		/* Update the other northbriges */
-		pdev = 0;
-		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
-			/* Store the GART size but don't enable it */
-			pci_write_config32(pdev, 0x90, gart_acr);
-
-			/* Store the GART base address */
-			pci_write_config32(pdev, 0x94, gart_base);
-
-			/* Don't set the GART Table base address */
-			pci_write_config32(pdev, 0x98, 0);
-
-			/* Report the resource has been stored... */
-			report_resource_stored(pdev, resource, " <gart>");
-		}
-	}
 }
 
 static void sis761_set_resources(device_t dev)
@@ -156,9 +111,7 @@
 
 static void sis761_init(struct device *dev)
 {
-	uint32_t cmd, cmd_ref;
 	int needs_reset;
-	struct device *f0_dev, *f2_dev;
 	msr_t	msr;
 
 

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -29,6 +29,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <arch/io.h>
+#include <delay.h>
 #include "sis966.h"
 
 uint8_t	SiS_SiS7502_init[7][3]={
@@ -236,13 +237,8 @@
 
 static void codecs_init(uint8_t *base, uint32_t codec_mask)
 {
-	int i;
 	codec_init(base, 0);
 	return;
-	for(i=2; i>=0; i--) {
-		if( codec_mask & (1<<i) )
-			codec_init(base, i);
-	}
 }
 
 static void aza_init(struct device *dev)

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_ctrl.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -23,14 +23,12 @@
 {
 	device_t dev;
 
-	/* Find the device.
-	 */
+	/* Find the device. */
 	dev = pci_locate_device_on_bus(
-		PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_SIS_SIS966_HT),
+		PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_HT),
 		bus);
 
 	return (dev>>15) & 0x1f;
-
 }
 
 static void hard_reset(void)
@@ -41,6 +39,7 @@
 	outb(0x0a, 0x0cf9);
 	outb(0x0e, 0x0cf9);
 }
+
 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
 /* default value for sis966 is good */

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -23,7 +23,7 @@
 
 #define SMBUS0_IO_BASE	0x8D0
 
-static const uint8_t SiS_LPC_init[33][3]={
+static const uint8_t SiS_LPC_init[34][3]={
 {0x04, 0xF8, 0x07},					//Reg 0x04
 {0x45, 0x00, 0x00},					//Reg 0x45			//Enable Rom Flash
 {0x46, 0x00, 0x3D},					//Reg 0x46
@@ -444,7 +444,6 @@
   	device_t dev;
   	msr_t	msr;
 	int	i;
-	uint32_t j;
 	uint8_t temp8;
 	uint16_t temp16;
 

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -234,7 +234,6 @@
 static void sis966_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
-	unsigned long index;
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -93,9 +93,7 @@
 
 static void set_apc(struct device *dev)
 {
-    uint32_t tmp;
     uint16_t addr;
-    uint32_t idx;
     uint16_t i;
     uint8_t   bTmp;
 
@@ -139,7 +137,7 @@
 #define LoopNum 200
 static  unsigned long ReadEEprom( struct device *dev,  uint32_t base,  uint32_t Reg)
 {
-    uint16_t 	data;
+    uint32_t 	data;
     uint32_t 	i;
     uint32_t 	ulValue;
 
@@ -165,7 +163,7 @@
     if(i==LoopNum)   data=0x10000;
     else{
     	ulValue=readl(base+0x3c);
-    	data = (uint16_t)((ulValue & 0xffff0000) >> 16);
+    	data = ((ulValue & 0xffff0000) >> 16);
     }
 
     return data;
@@ -174,11 +172,9 @@
 static int phy_read(uint32_t  base, unsigned phy_addr, unsigned phy_reg)
 {
     uint32_t   ulValue;
-    unsigned  loop = 0x100;
     uint32_t   Read_Cmd;
     uint16_t   usData;
 
-    uint16_t   tmp;
 
 
 	   Read_Cmd = ((phy_reg << 11) |
@@ -188,16 +184,13 @@
 
            // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
           writel( Read_Cmd,base+0x44);
-          //outl( Read_Cmd,tmp+0x44);
 
            // Polling SMI_REQ bit to be deasserted indicated read command completed
            do
            {
 	       // Wait 20 usec before checking status
-    	       //StallAndWait(20);
 		   mdelay(20);
     	       ulValue = readl(base+0x44);
-    	       //ulValue = inl(tmp+0x44);
            } while((ulValue & SMI_REQUEST) != 0);
             //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
            usData=(ulValue>>16);
@@ -213,7 +206,6 @@
 static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect()
 {
     int	              bFoundPhy = FALSE;
-    uint32_t		Read_Cmd;
     uint16_t		usData;
     int		       PhyAddress = 0;
 
@@ -246,16 +238,10 @@
 
 static void nic_init(struct device *dev)
 {
-        uint32_t dword, old;
-        uint32_t mac_h, mac_l;
-        int eeprom_valid = 0;
         int val;
         uint16_t  PhyAddr;
-        struct southbridge_sis_sis966_config *conf;
-        static uint32_t nic_index = 0;
         uint32_t base;
         struct resource *res;
-        uint32_t reg;
 
 
         print_debug("NIC_INIT:---------->\n");
@@ -353,68 +339,7 @@
 print_debug("NIC_INIT:<----------\n");
 return;
 
-#define RegStationMgtInf	0x44
-#define PHY_RGMII	0x10000000
 
-	writel(PHY_RGMII, base + RegStationMgtInf);
-	conf = dev->chip_info;
-
-	if(conf->mac_eeprom_smbus != 0) {
-//	read MAC address from EEPROM at first
-
-		struct device *dev_eeprom;
-		dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
-
-		if(dev_eeprom) {
-		//	if that is valid we will use that
-			unsigned char dat[6];
-			int status;
-			int i;
-			for(i=0;i<6;i++) {
-				status = smbus_read_byte(dev_eeprom, i);
-				if(status < 0) break;
-				dat[i] = status & 0xff;
-			}
-			if(status >= 0) {
-				mac_l = 0;
-				for(i=3;i>=0;i--) {
-					mac_l <<= 8;
-					mac_l += dat[i];
-				}
-				if(mac_l != 0xffffffff) {
-					mac_l += nic_index;
-					mac_h = 0;
-					for(i=5;i>=4;i--) {
-						mac_h <<= 8;
-						mac_h += dat[i];
-					}
-					eeprom_valid = 1;
-				}
-			}
-		}
-	}
-
-// if that is invalid we will read that from romstrap
-	if(!eeprom_valid) {
-		unsigned long mac_pos;
-		mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
-		mac_l = readl(mac_pos) + nic_index; // overflow?
-		mac_h = readl(mac_pos + 4);
-
-	}
-
-// set that into NIC MMIO
-#define NvRegMacAddrA	0xA8
-#define NvRegMacAddrB	0xAC
-	writel(mac_l, base + NvRegMacAddrA);
-	writel(mac_h, base + NvRegMacAddrB);
-
-	nic_index++;
-
-#if CONFIG_PCI_ROM_RUN == 1
-	pci_dev_init(dev);// it will init option rom
-#endif
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -436,6 +361,7 @@
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
+
 static const struct pci_driver nic_driver __pci_driver = {
 	.ops	= &nic_ops,
 	.vendor	= PCI_VENDOR_ID_SIS,

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -111,13 +111,9 @@
 
 static void sata_init(struct device *dev)
 {
-	uint32_t dword;
 	struct southbridge_sis_sis966_config *conf;
 
 
-struct resource *res;
-uint16_t base;
-uint8_t temp8;
 
 	conf = dev->chip_info;
         print_debug("SATA_INIT:---------->\n");

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -102,7 +102,6 @@
 
 static void sis966_sm_read_resources(device_t dev)
 {
-	struct resource *res;
 	unsigned long index;
 
 	/* Get the normal pci resources of this device */

Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c	2007-11-04 23:37:44 UTC (rev 2944)
+++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c	2007-11-05 22:21:27 UTC (rev 2945)
@@ -72,7 +72,6 @@
 {
         uint8_t *base;
         struct resource *res;
-        uint32_t temp32;
 
         print_debug("USB 2.0 INIT:---------->\n");
 




From svn at openbios.org  Mon Nov  5 23:35:02 2007
From: svn at openbios.org (svn at openbios.org)
Date: Mon,  5 Nov 2007 23:35:02 +0100
Subject: [LinuxBIOS] r2946 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
Message-ID: <mailman.841.1355071197.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2007-11-05 23:35:01 +0100 (Mon, 05 Nov 2007)
New Revision: 2946

Modified:
   trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
Log:
Fix the M57SLI routing table, as apparently set up from LinuxBIOS on
that board. Shift PCIe pin numbers downwards, and PCI int pins upwards.
This puts both PCI slots' int A and PCIe 16x int A into the right
position.

Signed-off-by: Torsten Duwe <duwe at lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c	2007-11-05 22:21:27 UTC (rev 2945)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c	2007-11-05 22:35:01 UTC (rev 2946)
@@ -129,13 +129,13 @@
 	for(j=7; j>=2; j--) {
 		if(!bus_mcp55[j]) continue;
 	        for(i=0;i<4;i++) {
-        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (1+j+i)%4);
         	}
 	}
 
 	for(j=0; j<2; j++) 
 	        for(i=0;i<4;i++) {
-        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06+j)<<2)|i, apicid_mcp55, 0x10 + (2+i+j)%4);
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x07+j)<<2)|i, apicid_mcp55, 0x10 + (3+i+j)%4);
 	        }
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/




From c-d.hailfinger.devel.2006 at gmx.net  Mon Nov  5 23:38:28 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 05 Nov 2007 23:38:28 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <200711051204.12118.duwe@lst.de>
References: <200711051204.12118.duwe@lst.de>
Message-ID: <472F9B64.1040809@gmx.net>

On 05.11.2007 12:04, Torsten Duwe wrote:
> This patch makes both PCI slots and the primary PCIe work for me, sort of.
> The only downsides are that under heavy usage I lose an interrupt once in a 
> while, but this might be due to irqpoll.
>
> The other issue is that the graphics card still only initialises under X, and 
> still very slowly.
>
> Looking at mptable.c I get the impression it was copied almost verbatim from 
> another board and not adopted to the M57SLI. Yinghai, where did you get the 
> routing info from?
>
> Another scary thing is that the wiring seems to differ when the board is set 
> up via LinuxBIOS; legacy BIOS puts the PCIe 16x int A on the same line with 
> bus 1 device 8, while LinuxBIOS does that with bus 1 device 7 ! Can anyone 
> with a datasheet shed some light on this?
>
> Anyway, here's the patch that improves things quite a lot on my machine.
>
> please SVN-quote only below this line :-)
> ------------------------------------------------------------------------------------------
> Fix the M57SLI routing table, as apparently  set up from LinuxBIOS on that 
> board. Shift PCIe pin numbers downwards, and PCI int pins upwards. This puts 
> both PCI slots' int A and PCIe 16x int A into the right position.
>
> Signed-off-by: Torsten Duwe <duwe at lst.de>
>   

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Thanks, Torsten. Checked in in r2946.

What issues remain for the board now that this has been checked in? Do
you still need irqpoll?

Regards,
Carl-Daniel



From dsedrich at violin-memory.com  Mon Nov  5 23:42:32 2007
From: dsedrich at violin-memory.com (David Edrich)
Date: Mon, 5 Nov 2007 16:42:32 -0600
Subject: [LinuxBIOS] looking for a LinuxBIOS port of a 4 socket Opteron
	based SuperMicro board with HTX slot
Message-ID: <003301c81ffd$288bd9e0$79a38da0$@com>

Is anyone working on a Linux BIOS port for any 4 socket Opteron based SuperMicro board with an HTX slot?

There are none noted in the  supported Motherboards page.

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From peter at stuge.se  Mon Nov  5 23:47:44 2007
From: peter at stuge.se (Peter Stuge)
Date: Mon, 5 Nov 2007 23:47:44 +0100
Subject: [LinuxBIOS] Problems with elfboot
In-Reply-To: <b25e2a480711051245h32b24485j869a774e258a0a60@mail.gmail.com>
References: <b25e2a480711051245h32b24485j869a774e258a0a60@mail.gmail.com>
Message-ID: <20071105224744.15870.qmail@stuge.se>

On Mon, Nov 05, 2007 at 03:45:55PM -0500, Hanoi Santos Hung wrote:
> Hi :
> I'm working with this hardware configuration :
> North  : vt8605
> South  : vt82C686B
> RAM : 128 MB SODIMM
> 
> I begin modifying the code from vt8601 and LinuxBIOS V1.0 version
> of vt82c686

Wow, 1.0 is really old. Was there no board in 2.0 that was similar to
your board? Perhaps one of the EPIA boards?


> and I have my system working until it tries to load the payload
> (filo). I think the problem was the memory, but
> ram_check(0x00000000, 0xA0000);
> ram_check(0x00100000, 0x8000000);
> 
> works perfectly,

ram_check() is a _VERY_ simplistic memory test, RAM is not
neccessarily working properly just because it does not fail.

Please try to use memtest86 as payload before FILO or anything else.


> another symptom : when the board make a cold start it
> freeze at "Jumping  to  LinuxBIOS".
> 
> I'll apreciate any help

Please send the full serial output you get from the board.


//Peter



From peter at stuge.se  Mon Nov  5 23:51:04 2007
From: peter at stuge.se (Peter Stuge)
Date: Mon, 5 Nov 2007 23:51:04 +0100
Subject: [LinuxBIOS] r2946 -
	trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
Message-ID: <20071105225104.16524.qmail@stuge.se>

On Mon, Nov 05, 2007 at 11:35:02PM +0100, svn at openbios.org wrote:
> Log:
> Fix the M57SLI routing table,

Is this correct for all revisions of the board?


//Peter



From peter at stuge.se  Mon Nov  5 23:52:27 2007
From: peter at stuge.se (Peter Stuge)
Date: Mon, 5 Nov 2007 23:52:27 +0100
Subject: [LinuxBIOS] looking for a LinuxBIOS port of a 4 socket Opteron
	based SuperMicro board with HTX slot
In-Reply-To: <003301c81ffd$288bd9e0$79a38da0$@com>
References: <003301c81ffd$288bd9e0$79a38da0$@com>
Message-ID: <20071105225227.16774.qmail@stuge.se>

On Mon, Nov 05, 2007 at 04:42:32PM -0600, David Edrich wrote:
> Is anyone working on a Linux BIOS port for any 4 socket Opteron
> based SuperMicro board with an HTX slot?

I don't think so.


//Peter



From duwe at lst.de  Tue Nov  6 00:32:40 2007
From: duwe at lst.de (Torsten Duwe)
Date: Tue, 6 Nov 2007 00:32:40 +0100
Subject: [LinuxBIOS] r2946 -
	trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
In-Reply-To: <20071105225104.16524.qmail@stuge.se>
References: <20071105225104.16524.qmail@stuge.se>
Message-ID: <200711060032.40497.duwe@lst.de>

On Monday 05 November 2007, Peter Stuge wrote:
> On Mon, Nov 05, 2007 at 11:35:02PM +0100, svn at openbios.org wrote:
> > Log:
> > Fix the M57SLI routing table,
>
> Is this correct for all revisions of the board?

Good question. is there any revision for which the old code worked?
Hint: lspci will surely look different, since INTs were assigned to 01:06 and 
01:07, not slots 7 and 8.

Anyone with devices 6 and 7 shall speak up now, or remain silent forever ;-)

The BIOSes gigabyte offers are different, most likely due to SPI code :-(

	Torsten



From duwe at lst.de  Tue Nov  6 00:40:31 2007
From: duwe at lst.de (Torsten Duwe)
Date: Tue, 6 Nov 2007 00:40:31 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <472F9B64.1040809@gmx.net>
References: <200711051204.12118.duwe@lst.de> <472F9B64.1040809@gmx.net>
Message-ID: <200711060040.31696.duwe@lst.de>

On Monday 05 November 2007, Carl-Daniel Hailfinger wrote:

> What issues remain for the board now that this has been checked in?

* the MTRR problem
* my ATI "atom BIOS" still does not init the GFX card, X startup slow
* other INTs (B, C, D) mostly untested
* FireWire untested
* assumed write protect lines to the flash chips
* more possible issues due to GPIO and INT route programming...

> Do you still need irqpoll?

Rebuilding and rebooting right after this mail ... :-)

	Torsten



From c-d.hailfinger.devel.2006 at gmx.net  Tue Nov  6 00:47:03 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 06 Nov 2007 00:47:03 +0100
Subject: [LinuxBIOS] r2946
	-	trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
In-Reply-To: <200711060032.40497.duwe@lst.de>
References: <20071105225104.16524.qmail@stuge.se>
	<200711060032.40497.duwe@lst.de>
Message-ID: <472FAB77.4020204@gmx.net>

On 06.11.2007 00:32, Torsten Duwe wrote:
> On Monday 05 November 2007, Peter Stuge wrote:
>   
>> On Mon, Nov 05, 2007 at 11:35:02PM +0100, svn at openbios.org wrote:
>>     
>>> Log:
>>> Fix the M57SLI routing table,
>>>       
>> Is this correct for all revisions of the board?
>>     
>
> Good question. is there any revision for which the old code worked?
> Hint: lspci will surely look different, since INTs were assigned to 01:06 and 
> 01:07, not slots 7 and 8.
>
> Anyone with devices 6 and 7 shall speak up now, or remain silent forever ;-)
>
> The BIOSes gigabyte offers are different, most likely due to SPI code :-(
>   

I'm still trying to find out whether we can determine the board type
from querying any onboard device. Comparing the output of superiotool
for PLCC and SPI revisions of the board, running exactly the same LB
version, would probably help a lot to solve that mystery.


Carl-Daniel




From c-d.hailfinger.devel.2006 at gmx.net  Tue Nov  6 00:51:46 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 06 Nov 2007 00:51:46 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <200711060040.31696.duwe@lst.de>
References: <200711051204.12118.duwe@lst.de> <472F9B64.1040809@gmx.net>
	<200711060040.31696.duwe@lst.de>
Message-ID: <472FAC92.30708@gmx.net>

On 06.11.2007 00:40, Torsten Duwe wrote:
> On Monday 05 November 2007, Carl-Daniel Hailfinger wrote:
>   
>> What issues remain for the board now that this has been checked in?
>>     
> [...]
> * assumed write protect lines to the flash chips
>   

IIRC we can flash PLCC boards under LB just fine, the SPI variants need
to set one bit and allocate a port range in the SuperIO. Once I know how
to tell board types apart, I can post a patch to fix that issue
automatically.

> * more possible issues due to GPIO and INT route programming...
>   

This would be a lot easier with proper documentation.


Carl-Daniel



From duwe at lst.de  Tue Nov  6 01:25:28 2007
From: duwe at lst.de (Torsten Duwe)
Date: Tue, 6 Nov 2007 01:25:28 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <200711060040.31696.duwe@lst.de>
References: <200711051204.12118.duwe@lst.de> <472F9B64.1040809@gmx.net>
	<200711060040.31696.duwe@lst.de>
Message-ID: <200711060125.28594.duwe@lst.de>

On Tuesday 06 November 2007 00:40, Torsten Duwe wrote:
> On Monday 05 November 2007, Carl-Daniel Hailfinger wrote:
> > Do you still need irqpoll?
>
> Rebuilding and rebooting right after this mail ... :-)

...now posting from it.

No more irqpoll, glxgears at full performance, both PCI slots' INT A working.
PCIe 16x INT A working. No more lost interrupts.

Save for the untested FireWire, interrupts are basically working now for me.

	Torsten



From duwe at lst.de  Tue Nov  6 01:31:58 2007
From: duwe at lst.de (Torsten Duwe)
Date: Tue, 6 Nov 2007 01:31:58 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <472FAC92.30708@gmx.net>
References: <200711051204.12118.duwe@lst.de> <200711060040.31696.duwe@lst.de>
	<472FAC92.30708@gmx.net>
Message-ID: <200711060131.58180.duwe@lst.de>

On Tuesday 06 November 2007 00:51, Carl-Daniel Hailfinger wrote:
> On 06.11.2007 00:40, Torsten Duwe wrote:
> > On Monday 05 November 2007, Carl-Daniel Hailfinger wrote:
> >> What issues remain for the board now that this has been checked in?
> >
> > [...]
> > * assumed write protect lines to the flash chips
>
> IIRC we can flash PLCC boards under LB just fine, the SPI variants need
> to set one bit and allocate a port range in the SuperIO. Once I know how
> to tell board types apart, I can post a patch to fix that issue
> automatically.

Nope, flash erase fails reliably for me. I suggest we call it SPI flashing vs. 
LPC flashing for consistency's sake; there might be SPI chips in a PLCC 
housing out there?

My original idea was to say that gigabyte has one flash image for all board 
revisions, but SPI flashing alone will make them different, bit-wise.

> > * more possible issues due to GPIO and INT route programming...
> This would be a lot easier with proper documentation.

Amen, brother!

'night
	Torsten



From yinghailu at gmail.com  Tue Nov  6 02:49:31 2007
From: yinghailu at gmail.com (yhlu)
Date: Mon, 5 Nov 2007 17:49:31 -0800
Subject: [LinuxBIOS] looking for a LinuxBIOS port of a 4 socket Opteron
	based SuperMicro board with HTX slot
In-Reply-To: <003301c81ffd$288bd9e0$79a38da0$@com>
References: <003301c81ffd$288bd9e0$79a38da0$@com>
Message-ID: <2ea3fae10711051749o4631a5a0odca8328f3d32b6cb@mail.gmail.com>

On 11/5/07, David Edrich <dsedrich at violin-memory.com> wrote:
>
>
>
>
> Is anyone working on a Linux BIOS port for any 4 socket Opteron based
> SuperMicro board with an HTX slot?
>

that would be very similar to tyans 2912...

you could talk to your supermicro account about it.

YH



From yinghailu at gmail.com  Tue Nov  6 02:54:09 2007
From: yinghailu at gmail.com (yhlu)
Date: Mon, 5 Nov 2007 17:54:09 -0800
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <200711051204.12118.duwe@lst.de>
References: <200711051204.12118.duwe@lst.de>
Message-ID: <2ea3fae10711051754k4d64048x5290dc83ebea4895@mail.gmail.com>

On 11/5/07, Torsten Duwe <duwe at lst.de> wrote:
> This patch makes both PCI slots and the primary PCIe work for me, sort of.
> The only downsides are that under heavy usage I lose an interrupt once in a
> while, but this might be due to irqpoll.
>
> The other issue is that the graphics card still only initialises under X, and
> still very slowly.
>
> Looking at mptable.c I get the impression it was copied almost verbatim from
> another board and not adopted to the M57SLI. Yinghai, where did you get the
> routing info from?

these are all belonging to MCP internal devices esp pcie.

when set the pci irq routing in pci conf space carefully, the mptable
entry could be computed via some simple equation.

YH



From rminnich at gmail.com  Tue Nov  6 06:08:24 2007
From: rminnich at gmail.com (ron minnich)
Date: Mon, 5 Nov 2007 21:08:24 -0800
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
In-Reply-To: <20071105220459.6e32496d@absurd>
References: <20071105220459.6e32496d@absurd>
Message-ID: <13426df10711052108g4aac411n8a6e53211a36e7cf@mail.gmail.com>

I don't think we need to waste our time chasing these companies down.
Let's just put our efforts into making linuxbios better and better.

ron



From patrick at georgi-clan.de  Tue Nov  6 07:47:12 2007
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 06 Nov 2007 07:47:12 +0100
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
In-Reply-To: <20071105220459.6e32496d@absurd>
References: <20071105220459.6e32496d@absurd>
Message-ID: <fgp662$oru$1@ger.gmane.org>

Janek Kozicki schrieb:
> I just wanted to let you know about Phoenix company (news from slashdot).
> 
> My point is - we could check if they use LinuxBIOS and if so - do
> they respect the license?
I doubt phoenix needs linuxbios to pull such a stunt - they're the major
x86 firmware maker, after all.


Regards,
Patrick Georgi




From duwe at lst.de  Tue Nov  6 10:56:51 2007
From: duwe at lst.de (Torsten Duwe)
Date: Tue, 6 Nov 2007 10:56:51 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <2ea3fae10711051754k4d64048x5290dc83ebea4895@mail.gmail.com>
References: <200711051204.12118.duwe@lst.de>
	<2ea3fae10711051754k4d64048x5290dc83ebea4895@mail.gmail.com>
Message-ID: <200711061056.51462.duwe@lst.de>

On Tuesday 06 November 2007, yhlu wrote:
> On 11/5/07, Torsten Duwe <duwe at lst.de> wrote:
> > Yinghai, where did you
> > get the routing info from?
>
> these are all belonging to MCP internal devices esp pcie.

Documented where?

> when set the pci irq routing in pci conf space carefully, the mptable
> entry could be computed via some simple equation.

Which did not match my hardware. Can you tell us how the setup is done?

	Torsten



From bari at onelabs.com  Tue Nov  6 15:42:30 2007
From: bari at onelabs.com (bari)
Date: Tue, 06 Nov 2007 08:42:30 -0600
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
In-Reply-To: <13426df10711052108g4aac411n8a6e53211a36e7cf@mail.gmail.com>
References: <20071105220459.6e32496d@absurd>
	<13426df10711052108g4aac411n8a6e53211a36e7cf@mail.gmail.com>
Message-ID: <47307D56.8090109@onelabs.com>

Recently the "Splashtop" by DeviceVM

http://www.linuxdevices.com/news/NS4383814601.html
http://blog.wired.com/business/2007/10/devicevm-launch.html

followed by "Hyperspace" by Phoenix have been getting attention in the 
press.

I'm not sure if their investors and management feel that a closed source 
BIOS has the only hope of success in the market or if they are unaware 
of LinuxBIOS.

The LinuxBIOS with X Server video
http://youtube.com/watch?v=nuzRsXKm_NQ
has been viewed over 160K times.

Why doesn't someone with time here put together a short and clear video 
demo of LinuxBIOS with the same capabilities of splashtop or hyperspace 
and more?

Ron's OLPC + LinuxBIOS and Pete's CarPC/mp3 videos only show a boot to a 
shell.
http://www.youtube.com/watch?v=Ig8vW5ACP-k
http://www.youtube.com/watch?v=kl1OWxbWCkA

-Bari

ron minnich wrote:
> I don't think we need to waste our time chasing these companies down.
> Let's just put our efforts into making linuxbios better and better.
> 
> ron
> 




From rminnich at gmail.com  Tue Nov  6 17:03:15 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 6 Nov 2007 08:03:15 -0800
Subject: [LinuxBIOS] Stale payloads
In-Reply-To: <20071105201249.GB10444@greenwood>
References: <035401c81d7c$c78e6f90$1223040a@chimp>
	<20071105201249.GB10444@greenwood>
Message-ID: <13426df10711060803k78756147rf0c4c8ff3c28dde8@mail.gmail.com>

On 11/5/07, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> If I understand you right, you want to change something in the code and
> then rebuild an image? If so, I recommend to _always_ 'rm -rf BUILDDIR'
> and re-do the "./buildtarget foo/bar" etc.

no, this is a sign that our makefiles are broken and need fixing.

I will try to look at this bug tonight.

ron



From rminnich at gmail.com  Tue Nov  6 17:04:07 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 6 Nov 2007 08:04:07 -0800
Subject: [LinuxBIOS] Stale payloads
In-Reply-To: <035401c81d7c$c78e6f90$1223040a@chimp>
References: <035401c81d7c$c78e6f90$1223040a@chimp>
Message-ID: <13426df10711060804v9c4f7d5k40314a95a45415cb@mail.gmail.com>

On 11/2/07, Myles Watson <myles at pel.cs.byu.edu> wrote:
> I've been spinning my wheels because of a stale payload.
>
> In the fallback directory, the payload file depends on the
> ../{../}*/payload.elf file.  If you change that to ../../payload.lzma.elf to
> retry, it won't get the new file if payload is newer than payload.lzma.elf.

Right. This is a bug in the makefile design.

Will try to fix.

ron



From svn at openbios.org  Tue Nov  6 17:23:38 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue,  6 Nov 2007 17:23:38 +0100
Subject: [LinuxBIOS] r53 - buildrom-devel/config/platforms
Message-ID: <mailman.842.1355071197.16123.coreboot@coreboot.org>

Author: ward
Date: 2007-11-06 17:23:38 +0100 (Tue, 06 Nov 2007)
New Revision: 53

Modified:
   buildrom-devel/config/platforms/platforms.conf
Log:

Fix m57sli board name in config/platforms/platforms.conf to match new
consistent naming scheme used elsewhere in buildrom (trivial).

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: buildrom-devel/config/platforms/platforms.conf
===================================================================
--- buildrom-devel/config/platforms/platforms.conf	2007-10-31 00:09:41 UTC (rev 52)
+++ buildrom-devel/config/platforms/platforms.conf	2007-11-06 16:23:38 UTC (rev 53)
@@ -11,10 +11,13 @@
 PLATFORM-$(CONFIG_PLATFORM_ALIX1C) = alix1c.conf
 PLATFORM-$(CONFIG_PLATFORM_DB800) = db800.conf
 PLATFORM-$(CONFIG_PLATFORM_DBE61) = dbe61.conf
-PLATFORM-$(CONFIG_PLATFORM_M57SLI) = m57sli.conf
+PLATFORM-$(CONFIG_PLATFORM_GA_M57SLI_S4) = m57sli.conf
 PLATFORM-$(CONFIG_PLATFORM_TYAN_S2882) = tyan-s2882.conf
 PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf
 PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH) = serengeti_cheetah.conf
 PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf
 
+$(warning $(PLATFORM-y))
+$(warning $(CONFIG_PLATFORM_GA_M57SLI_S4))
+
 include $(CONFIG_DIR)/platforms/$(PLATFORM-y)




From dsedrich at violin-memory.com  Tue Nov  6 17:20:05 2007
From: dsedrich at violin-memory.com (David Edrich)
Date: Tue, 6 Nov 2007 10:20:05 -0600
Subject: [LinuxBIOS] looking for a LinuxBIOS port of a 4 socket Opteron
	based SuperMicro board with HTX slot
In-Reply-To: <2ea3fae10711051749o4631a5a0odca8328f3d32b6cb@mail.gmail.com>
References: <003301c81ffd$288bd9e0$79a38da0$@com>
	<2ea3fae10711051749o4631a5a0odca8328f3d32b6cb@mail.gmail.com>
Message-ID: <005a01c82090$e69e1b80$b3da5280$@com>



> -----Original Message-----
> From: yhlu [mailto:yinghailu at gmail.com]
> Sent: Monday, November 05, 2007 7:50 PM
> To: David Edrich
> Cc: linuxbios at linuxbios.org
> Subject: Re: [LinuxBIOS] looking for a LinuxBIOS port of a 4 socket Opteron based SuperMicro board
> with HTX slot
> 
> On 11/5/07, David Edrich <dsedrich at violin-memory.com> wrote:
> >
> >
> >
> >
> > Is anyone working on a Linux BIOS port for any 4 socket Opteron based
> > SuperMicro board with an HTX slot?
> >
> 
> that would be very similar to tyans 2912...
> 
> you could talk to your supermicro account about it.
> 
> YH
[David Edrich] I need a LinuxBIOS for any 4 socket Opteron (Rev F socket) system with 1 preferably 2 HTX slots. I'm getting the idea
that there are no boards like that with LinuxBIOS yet.


Is there another list of LinuxBIOS ports in progress or is it all contained in:
http://linuxbios.org/index.php/Supported_Motherboards#Motherboards_supported_in_LinuxBIOSv2 ?


If I have to consider doing this myself are there publically available manuals for chipsets like the mcp55 ?


Is it generally difficult to get board documentation?







From stepan at coresystems.de  Tue Nov  6 17:30:54 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 6 Nov 2007 17:30:54 +0100
Subject: [LinuxBIOS] looking for a LinuxBIOS port of a 4 socket
	Opteron	based SuperMicro board with HTX slot
In-Reply-To: <005a01c82090$e69e1b80$b3da5280$@com>
References: <003301c81ffd$288bd9e0$79a38da0$@com>
	<2ea3fae10711051749o4631a5a0odca8328f3d32b6cb@mail.gmail.com>
	<005a01c82090$e69e1b80$b3da5280$@com>
Message-ID: <20071106163054.GA6953@coresystems.de>

* David Edrich <dsedrich at violin-memory.com> [071106 17:20]:
> [David Edrich] I need a LinuxBIOS for any 4 socket Opteron (Rev F socket) system with 1 preferably 2 HTX slots. I'm getting the idea
> that there are no boards like that with LinuxBIOS yet.

The Agami Aruma is such a board.. It's the board used in the Agami
Fileservers (www.agami.com) 

> If I have to consider doing this myself are there publically available manuals for chipsets like the mcp55 ?

Nvidia does not release any chipset documentation to the public.

> Is it generally difficult to get board documentation?

If you have a company, and a business case, it can be done.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From patrick at georgi-clan.de  Tue Nov  6 18:34:37 2007
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 06 Nov 2007 18:34:37 +0100
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
In-Reply-To: <47307D56.8090109@onelabs.com>
References: <20071105220459.6e32496d@absurd>	<13426df10711052108g4aac411n8a6e53211a36e7cf@mail.gmail.com>
	<47307D56.8090109@onelabs.com>
Message-ID: <fgq8ju$g3f$1@ger.gmane.org>

bari schrieb:
> I'm not sure if their investors and management feel that a closed source 
> BIOS has the only hope of success in the market or if they are unaware 
> of LinuxBIOS.
In case of Phoenix it's probably because they have most of the necessary
code lying around already, and seem to do quite well with their closed
source business model.


Regards,
Patrick Georgi




From ward at gnu.org  Tue Nov  6 20:21:26 2007
From: ward at gnu.org (Ward Vandewege)
Date: Tue, 6 Nov 2007 14:21:26 -0500
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <200711060125.28594.duwe@lst.de>
References: <200711051204.12118.duwe@lst.de> <472F9B64.1040809@gmx.net>
	<200711060040.31696.duwe@lst.de> <200711060125.28594.duwe@lst.de>
Message-ID: <20071106192126.GA17520@localdomain>

On Tue, Nov 06, 2007 at 01:25:28AM +0100, Torsten Duwe wrote:
> On Tuesday 06 November 2007 00:40, Torsten Duwe wrote:
> > On Monday 05 November 2007, Carl-Daniel Hailfinger wrote:
> > > Do you still need irqpoll?
> >
> > Rebuilding and rebooting right after this mail ... :-)
> 
> ...now posting from it.
> 
> No more irqpoll, glxgears at full performance, both PCI slots' INT A working.
> PCIe 16x INT A working. No more lost interrupts.
> 
> Save for the untested FireWire, interrupts are basically working now for me.

Yeah, thanks! Your patch also seems to have fixed the flashrom problem I saw
under LB (http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87). I'm going
to give it some more testing because it *sometimes* would work before, but
it's looking good so far.

Are you using NoDCC2 in xorg.conf to get X to start up fast? Seems I still
need that.

Thanks!
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From andi.mundt at web.de  Tue Nov  6 20:28:06 2007
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Tue, 6 Nov 2007 20:28:06 +0100
Subject: [LinuxBIOS] compile error on debian lenny (AMD64)
Message-ID: <20071106192806.GA9247@flashgordon>

Hi,

after some time of abstinence I tried to build linuxbios (m57sli) on debian-lenny 
(AMD64) but failed:  

gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o  mcp55_aza.o mcp55_ht.o mcp55_pci.o uart8250_console.o mcp55_ide.o vga_console.o mainboard.o mcp55_lpc.o mcp55_nic.o mcp55_pcie.o mcp55_usb2.o mcp55_sata.o mcp55.o mcp55_usb.o misc_control.o model_fxx_init.o mcp55_smbus.o linuxbios.a /usr/lib/gcc/x86_64-linux-gnu/4.2.3/libgcc.a
gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T /home/andi/freeBIOS/LinuxBIOSv2/src/config/linuxbios_ram.ld linuxbios_ram.o
linuxbios_ram.o: In function `div_long':
(.text+0x11615): undefined reference to `__umoddi3'
linuxbios_ram.o: In function `div_long':
(.text+0x11633): undefined reference to `__udivdi3'
linuxbios_ram.o: In function `idiv_long':
(.text+0x11775): undefined reference to `__moddi3'
linuxbios_ram.o: In function `idiv_long':
(.text+0x11793): undefined reference to `__divdi3'
collect2: ld returned 1 exit status
make[1]: *** [linuxbios_ram] Error 1
make[1]: Leaving directory `/home/andi/freeBIOS/LinuxBIOSv2/targets/gigabyte/m57sli/m57sli/normal'
make: *** [normal/linuxbios.rom] Error 1



From svn at openbios.org  Tue Nov  6 20:58:52 2007
From: svn at openbios.org (svn at openbios.org)
Date: Tue,  6 Nov 2007 20:58:52 +0100
Subject: [LinuxBIOS] r54 - buildrom-devel/config/platforms
Message-ID: <mailman.844.1355071197.16123.coreboot@coreboot.org>

Author: ward
Date: 2007-11-06 20:58:52 +0100 (Tue, 06 Nov 2007)
New Revision: 54

Modified:
   buildrom-devel/config/platforms/platforms.conf
Log:

Remove debug output that slipped in during my last trivial patch (trivial).

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: buildrom-devel/config/platforms/platforms.conf
===================================================================
--- buildrom-devel/config/platforms/platforms.conf	2007-11-06 16:23:38 UTC (rev 53)
+++ buildrom-devel/config/platforms/platforms.conf	2007-11-06 19:58:52 UTC (rev 54)
@@ -17,7 +17,4 @@
 PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH) = serengeti_cheetah.conf
 PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf
 
-$(warning $(PLATFORM-y))
-$(warning $(CONFIG_PLATFORM_GA_M57SLI_S4))
-
 include $(CONFIG_DIR)/platforms/$(PLATFORM-y)




From rmh at aybabtu.com  Tue Nov  6 21:25:04 2007
From: rmh at aybabtu.com (Robert Millan)
Date: Tue, 6 Nov 2007 21:25:04 +0100
Subject: [LinuxBIOS] compile error on debian lenny (AMD64)
In-Reply-To: <20071106192806.GA9247@flashgordon>
References: <20071106192806.GA9247@flashgordon>
Message-ID: <20071106202504.GA28780@thorin>

On Tue, Nov 06, 2007 at 08:28:06PM +0100, Andreas B. Mundt wrote:
> Hi,
> 
> after some time of abstinence I tried to build linuxbios (m57sli) on debian-lenny 
> (AMD64) but failed:  
> 
> gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o  mcp55_aza.o mcp55_ht.o mcp55_pci.o uart8250_console.o mcp55_ide.o vga_console.o mainboard.o mcp55_lpc.o mcp55_nic.o mcp55_pcie.o mcp55_usb2.o mcp55_sata.o mcp55.o mcp55_usb.o misc_control.o model_fxx_init.o mcp55_smbus.o linuxbios.a /usr/lib/gcc/x86_64-linux-gnu/4.2.3/libgcc.a
> gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T /home/andi/freeBIOS/LinuxBIOSv2/src/config/linuxbios_ram.ld linuxbios_ram.o
> linuxbios_ram.o: In function `div_long':
> (.text+0x11615): undefined reference to `__umoddi3'
> linuxbios_ram.o: In function `div_long':
> (.text+0x11633): undefined reference to `__udivdi3'
> linuxbios_ram.o: In function `idiv_long':
> (.text+0x11775): undefined reference to `__moddi3'
> linuxbios_ram.o: In function `idiv_long':
> (.text+0x11793): undefined reference to `__divdi3'
> collect2: ld returned 1 exit status
> make[1]: *** [linuxbios_ram] Error 1
> make[1]: Leaving directory `/home/andi/freeBIOS/LinuxBIOSv2/targets/gigabyte/m57sli/m57sli/normal'
> make: *** [normal/linuxbios.rom] Error 1
> 
> 
> >From a short google-investigation I suspect some missing 32-bit libs. 
> Does anybody have an idea what's missing/changed?

Try installing gcc-multilib package.

(Btw, it works for me on amd64 etch)

-- 
Robert Millan

<GPLv2> I know my rights; I want my phone call!
<DRM> What use is a phone call, if you are unable to speak?
(as seen on /.)



From rmh at aybabtu.com  Tue Nov  6 21:28:43 2007
From: rmh at aybabtu.com (Robert Millan)
Date: Tue, 6 Nov 2007 21:28:43 +0100
Subject: [LinuxBIOS] memory table address
Message-ID: <20071106202843.GB28780@thorin>


Hi!

Rudolf reported that GRUB doesn't start on LBv2 because it attempts to find
the memory map table at 0x500, and it isn't always there.  For him it is at
0x530, but looking at the code it seems not to be hardcoded, but instead
right after a GDT that does live at 0x500.  See:

  http://grub.enbug.org/LinuxBIOS

Is there a spec on something on what should payloads do about this?  Probe
0x500 and 0x530 or ... ?

TIA

-- 
Robert Millan

<GPLv2> I know my rights; I want my phone call!
<DRM> What use is a phone call, if you are unable to speak?
(as seen on /.)



From andi.mundt at web.de  Tue Nov  6 21:33:54 2007
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Tue, 6 Nov 2007 21:33:54 +0100
Subject: [LinuxBIOS] compile error on debian lenny (AMD64)
In-Reply-To: <20071106202504.GA28780@thorin>
References: <20071106192806.GA9247@flashgordon> <20071106202504.GA28780@thorin>
Message-ID: <20071106203354.GA10966@flashgordon>

Great! This fixed the issue.

Thanks,

	Andi



On Tue, Nov 06, 2007 at 09:25:04PM +0100, Robert Millan wrote:
> > Does anybody have an idea what's missing/changed?
> 
> Try installing gcc-multilib package.
> 
> (Btw, it works for me on amd64 etch)
> 
> -- 
> Robert Millan
> 
> <GPLv2> I know my rights; I want my phone call!
> <DRM> What use is a phone call, if you are unable to speak?
> (as seen on /.)
> 
> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios




From andi.mundt at web.de  Tue Nov  6 22:02:05 2007
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Tue, 6 Nov 2007 22:02:05 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <20071106192126.GA17520@localdomain>
References: <200711051204.12118.duwe@lst.de> <472F9B64.1040809@gmx.net>
	<200711060040.31696.duwe@lst.de> <200711060125.28594.duwe@lst.de>
	<20071106192126.GA17520@localdomain>
Message-ID: <20071106210205.GA3713@flashgordon>

Hello,

unfortunately, for me flashrom still fails (I've never seen it working 
on my bord with LB, factory bios works).   

I still need "NoDCC2". 

Regards,

	Andi


On Tue, Nov 06, 2007 at 02:21:26PM -0500, Ward Vandewege wrote:
> 
> Yeah, thanks! Your patch also seems to have fixed the flashrom problem I saw
> under LB (http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87). I'm going
> to give it some more testing because it *sometimes* would work before, but
> it's looking good so far.
> 
> Are you using NoDCC2 in xorg.conf to get X to start up fast? Seems I still
> need that.
> 
> Thanks!
> Ward.
> 





From ward at gnu.org  Tue Nov  6 22:12:59 2007
From: ward at gnu.org (Ward Vandewege)
Date: Tue, 6 Nov 2007 16:12:59 -0500
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <20071106210205.GA3713@flashgordon>
References: <200711051204.12118.duwe@lst.de> <472F9B64.1040809@gmx.net>
	<200711060040.31696.duwe@lst.de> <200711060125.28594.duwe@lst.de>
	<20071106192126.GA17520@localdomain>
	<20071106210205.GA3713@flashgordon>
Message-ID: <20071106211259.GA19605@localdomain>

Hi Andi,

On Tue, Nov 06, 2007 at 10:02:05PM +0100, Andreas B. Mundt wrote:
> unfortunately, for me flashrom still fails (I've never seen it working 
> on my bord with LB, factory bios works).   

Yeah, same here, I was wrong :/

However, I'm glad you also see the problem - it's not just my board then
(which had the plcc chip removed and a socket soldered on).

Did you also modify your board?

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From bari at onelabs.com  Tue Nov  6 22:14:38 2007
From: bari at onelabs.com (bari)
Date: Tue, 06 Nov 2007 15:14:38 -0600
Subject: [LinuxBIOS] From slashdot - a company possibly using linuxbios.
In-Reply-To: <fgq8ju$g3f$1@ger.gmane.org>
References: <20071105220459.6e32496d@absurd>	<13426df10711052108g4aac411n8a6e53211a36e7cf@mail.gmail.com>	<47307D56.8090109@onelabs.com>
	<fgq8ju$g3f$1@ger.gmane.org>
Message-ID: <4730D93E.3090106@onelabs.com>

Patrick Georgi wrote:
> bari schrieb:
>> I'm not sure if their investors and management feel that a closed source 
>> BIOS has the only hope of success in the market or if they are unaware 
>> of LinuxBIOS.
> In case of Phoenix it's probably because they have most of the necessary
> code lying around already, and seem to do quite well with their closed
> source business model.
> 
Phoenix is now publicizing a "we have it to" since DeviceVM made their 
announcement. Is it just catch up in case they are missing anything? Is 
there a real demand for near instant boot to email, browser and 
multimedia players? If so LinuxBIOS easily supports this.

Up to a few years ago a PC BIOS still needed to support OS's that rely 
on BIOS calls. That need has and is still dwindling. Is this still a 
major reason for the popularity of the closed source BIOS?

Intel has been pushing their own agenda with EFI (and TCPA) and ignores 
LinuxBIOS. Is this another reason why closed source BIOS is still going 
strong?

Back in 2003 Slashdot had an interview with an AMI developer:
http://interviews.slashdot.org/article.pl?sid=03/01/17/1430214
where he brought up the issues of NDA's on chipsets. I'm sure everyone 
can understand why a chipset vendor would want to keep information 
secret about a chipset before it is released into the market. But after 
it is released (even after several months), why all the secrecy?

All the LinuxBIOS community basically needs in order to port a BIOS are 
register settings and the order in which they should be set. Are the 
concerns of violating patents on chipset IP or fixing engineering 
mistakes in silicon with BIOS that great a problem?

Motherboard schematics are another issue.  Interrupt routing and use of 
GPIO's are not big secrets. Obfuscated FLASH write enables have always 
been hacked by end users when really needed. What are the "secrets" in 
typical motherboard schematics?

Are ideologies or the need to have control of information the reasons 
closed source BIOS is still so popular?

Do vendors really feel that they will have tech support nightmares if 
they release accurate and unsupported BIOS specifications?

-Bari







From svn at openbios.org  Tue Nov  6 22:38:09 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 06 Nov 2007 21:38:09 -0000
Subject: [LinuxBIOS] #80: serial console in grub2 works
In-Reply-To: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
References: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
Message-ID: <053.3024cc8ee22ac4a65a206fc4f8b2d971@openbios.org>

#80: serial console in grub2 works
----------------------------+-----------------------------------------------
    Reporter:  oxygene      |         Owner:  oxygene                
        Type:  enhancement  |        Status:  closed                 
    Priority:  major        |     Milestone:  Port GRUB2 to LinuxBIOS
   Component:  code         |       Version:  v3                     
  Resolution:  fixed        |      Keywords:                         
Dependencies:               |   Patchstatus:  patch needs review     
----------------------------+-----------------------------------------------
Comment (by rmh at aybabtu.com):

 Not necessary.  We'll fix this by hardcoding 0x3f8 / 0x2f8 like LinuxBIOS
 is doing.  Thanks for the pointer.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/80#comment:3>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Wed Nov  7 00:20:50 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 06 Nov 2007 23:20:50 -0000
Subject: [LinuxBIOS] #80: serial console in grub2 works
In-Reply-To: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
References: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
Message-ID: <053.95ce4931074f68c22b78d14de37d6344@openbios.org>

#80: serial console in grub2 works
----------------------------+-----------------------------------------------
    Reporter:  oxygene      |         Owner:  oxygene                
        Type:  enhancement  |        Status:  closed                 
    Priority:  major        |     Milestone:  Port GRUB2 to LinuxBIOS
   Component:  code         |       Version:  v3                     
  Resolution:  fixed        |      Keywords:                         
Dependencies:               |   Patchstatus:  patch needs review     
----------------------------+-----------------------------------------------
Comment (by stuge):

 Is that really good enough? Isn't the console serial port in the LinuxBIOS
 table? If not, it should be. I guess it can and will change, especially
 for v3.

 This touches on the previous discussion about LB->payload interface specs.

 As long as GRUB2 has abstraction for LB I'm happy with whatever for now,
 but assuming that LB will always behave/provide like legacy BIOS is
 certainly not the way I would like it to work.

 Is this really closed?

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/80#comment:4>
LinuxBIOS <http://www.linuxbios.org/>

From svn at openbios.org  Wed Nov  7 00:42:32 2007
From: svn at openbios.org (LinuxBIOS)
Date: Tue, 06 Nov 2007 23:42:32 -0000
Subject: [LinuxBIOS] #80: serial console in grub2 works
In-Reply-To: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
References: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
Message-ID: <053.fafac86c2f999338c94fe333e42e0510@openbios.org>

#80: serial console in grub2 works
----------------------------+-----------------------------------------------
    Reporter:  oxygene      |         Owner:  oxygene                
        Type:  enhancement  |        Status:  reopened               
    Priority:  major        |     Milestone:  Port GRUB2 to LinuxBIOS
   Component:  code         |       Version:  v3                     
  Resolution:               |      Keywords:                         
Dependencies:               |   Patchstatus:  patch needs review     
----------------------------+-----------------------------------------------
Changes (by stepan):

  * status:  closed => reopened
  * resolution:  fixed =>

Comment:

 Peter is right here. In fact, the serial port is by no means hard coded in
 LinuxBIOS. Instead it is a CONFIG_ variable. This should indeed be
 exported via the LinuxBIOS table. This should be easy to do in v2 and v3.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/80#comment:5>
LinuxBIOS <http://www.linuxbios.org/>

From stepan at coresystems.de  Wed Nov  7 00:55:25 2007
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 7 Nov 2007 00:55:25 +0100
Subject: [LinuxBIOS] memory table address
In-Reply-To: <20071106202843.GB28780@thorin>
References: <20071106202843.GB28780@thorin>
Message-ID: <20071106235525.GA22963@coresystems.de>

* Robert Millan <rmh at aybabtu.com> [071106 21:28]:
> 
> Hi!
> 
> Rudolf reported that GRUB doesn't start on LBv2 because it attempts to find
> the memory map table at 0x500, and it isn't always there.  For him it is at
> 0x530, but looking at the code it seems not to be hardcoded, but instead
> right after a GDT that does live at 0x500.  See:
> 
>   http://grub.enbug.org/LinuxBIOS
> 
> Is there a spec on something on what should payloads do about this?  Probe
> 0x500 and 0x530 or ... ?

See LinuxBIOSv2/util/lxbios/lbtable.c - The table can be anywhere in
(low?) memory, at a 16byte aligned memory address. It can be probed by
looking for the LBIO signature and the checksum.

v2 may use different places for the LB table, while v3 always puts it at
0x500 so far. This is not gonna stay like that, though, as we might want
to enhance bios compatibility by filling the EBDA at 0x500 (after the
BDA at 0x400) at some point.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866



From peter at stuge.se  Wed Nov  7 01:12:27 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 7 Nov 2007 01:12:27 +0100
Subject: [LinuxBIOS] BIOS compatibility [was: memory table address]
In-Reply-To: <20071106235525.GA22963@coresystems.de>
References: <20071106202843.GB28780@thorin>
	<20071106235525.GA22963@coresystems.de>
Message-ID: <20071107001227.19106.qmail@stuge.se>

On Wed, Nov 07, 2007 at 12:55:25AM +0100, Stefan Reinauer wrote:
> bios compatibility

I would like any BIOS compatibility to be opt-in, and to be
uninteresting because of new shinyness offered by LB and
understood by all. :)


//Peter



From svn at openbios.org  Wed Nov  7 01:19:42 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed,  7 Nov 2007 01:19:42 +0100
Subject: [LinuxBIOS] r2947 - in trunk/LinuxBIOSv2/src: include/device
	mainboard/supermicro/x6dai_g southbridge/intel/esb6300
Message-ID: <mailman.845.1355071197.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-11-07 01:19:42 +0100 (Wed, 07 Nov 2007)
New Revision: 2947

Modified:
   trunk/LinuxBIOSv2/src/include/device/pci_ids.h
   trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/reset.c
   trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300.c
   trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_bridge1c.c
   trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_pic.c
   trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_sata.c
   trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_uhci.c
Log:
Add PCI IDs for most Intel southbridges of the 82801 series
(ICH/ICH0 up to the ICH9 family) in preparation for further
code improvements for the i82801xx southbridge code.

Small fixes in the 6300ESB PCI IDs.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h	2007-11-07 00:19:42 UTC (rev 2947)
@@ -1850,9 +1850,9 @@
 
 /* Intel 82801BA (ICH2) */
 #define PCI_DEVICE_ID_INTEL_82801BA_LPC		0x2440
-#define PCI_DEVICE_ID_INTEL_82801BA_USB_FN2	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BA_USB1	0x2442
 #define PCI_DEVICE_ID_INTEL_82801BA_SMB		0x2443
-#define PCI_DEVICE_ID_INTEL_82801BA_USB_FN4	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BA_USB2	0x2444
 #define PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO	0x2445
 #define PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM	0x2446
 #define PCI_DEVICE_ID_INTEL_82801BA_LAN		0x2449
@@ -1860,9 +1860,9 @@
 #define PCI_DEVICE_ID_INTEL_82801BA_PCI		0x244e
 
 /* Intel 82801BAM (ICH2-M) */
-#define PCI_DEVICE_ID_INTEL_82801BAM_USB_FN2	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BAM_USB1	0x2442
 #define PCI_DEVICE_ID_INTEL_82801BAM_SMB	0x2443
-#define PCI_DEVICE_ID_INTEL_82801BAM_USB_FN4	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BAM_USB2	0x2444
 #define PCI_DEVICE_ID_INTEL_82801BAM_AC97_AUDIO	0x2445
 #define PCI_DEVICE_ID_INTEL_82801BAM_AC97_MODEM	0x2446
 #define PCI_DEVICE_ID_INTEL_82801BAM_PCI	0x2448
@@ -1907,6 +1907,18 @@
 #define PCI_DEVICE_ID_INTEL_82801DB_IDE		0x24cb
 #define PCI_DEVICE_ID_INTEL_82801DB_EHCI	0x24cd
 
+/* Intel 82801DBL (ICH4-L) */
+#define PCI_DEVICE_ID_INTEL_82801DBL_LAN	0x103a
+#define PCI_DEVICE_ID_INTEL_82801DBL_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801DBL_LPC	0x24c0
+#define PCI_DEVICE_ID_INTEL_82801DBL_IDE	0x24c1
+#define PCI_DEVICE_ID_INTEL_82801DBL_USB1	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DBL_SMB	0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DBL_USB2	0x24c4
+#define PCI_DEVICE_ID_INTEL_82801DBL_AC97_AUDIO	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DBL_AC97_MODEM	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DBL_USB3	0x24c7
+
 /* Intel 82801DBM (ICH4-M) */
 #define PCI_DEVICE_ID_INTEL_82801DBM_LAN	0x103a
 #define PCI_DEVICE_ID_INTEL_82801DBM_PCI	0x2448
@@ -1950,6 +1962,325 @@
 #define PCI_DEVICE_ID_INTEL_82801ER_USB4	0x24de
 #define PCI_DEVICE_ID_INTEL_82801ER_SATA	0x24df
 
+/* Intel 82801FB (ICH6) */
+#define PCI_DEVICE_ID_INTEL_82801FB_LAN		0x1065
+#define PCI_DEVICE_ID_INTEL_82801FB_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801FB_LPC		0x2640
+#define PCI_DEVICE_ID_INTEL_82801FB_SATA	0x2651
+#define PCI_DEVICE_ID_INTEL_82801FB_USB1	0x2658
+#define PCI_DEVICE_ID_INTEL_82801FB_USB2	0x2659
+#define PCI_DEVICE_ID_INTEL_82801FB_USB3	0x265a
+#define PCI_DEVICE_ID_INTEL_82801FB_USB4	0x265b
+#define PCI_DEVICE_ID_INTEL_82801FB_EHCI	0x265c
+#define PCI_DEVICE_ID_INTEL_82801FB_PCIE1	0x2660
+#define PCI_DEVICE_ID_INTEL_82801FB_PCIE2	0x2662
+#define PCI_DEVICE_ID_INTEL_82801FB_PCIE3	0x2664
+#define PCI_DEVICE_ID_INTEL_82801FB_PCIE4	0x2666
+#define PCI_DEVICE_ID_INTEL_82801FB_HD_AUDIO	0x2668
+#define PCI_DEVICE_ID_INTEL_82801FB_SMB		0x266a
+#define PCI_DEVICE_ID_INTEL_82801FB_AC97_MODEM	0x266d
+#define PCI_DEVICE_ID_INTEL_82801FB_AC97_AUDIO	0x266e
+#define PCI_DEVICE_ID_INTEL_82801FB_IDE		0x266f
+
+/* Intel 82801FR (ICH6R) */
+#define PCI_DEVICE_ID_INTEL_82801FR_LAN		0x1065
+#define PCI_DEVICE_ID_INTEL_82801FR_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801FR_LPC		0x2640
+#define PCI_DEVICE_ID_INTEL_82801FR_SATA	0x2652
+#define PCI_DEVICE_ID_INTEL_82801FR_USB1	0x2658
+#define PCI_DEVICE_ID_INTEL_82801FR_USB2	0x2659
+#define PCI_DEVICE_ID_INTEL_82801FR_USB3	0x265a
+#define PCI_DEVICE_ID_INTEL_82801FR_USB4	0x265b
+#define PCI_DEVICE_ID_INTEL_82801FR_EHCI	0x265c
+#define PCI_DEVICE_ID_INTEL_82801FR_PCIE1	0x2660
+#define PCI_DEVICE_ID_INTEL_82801FR_PCIE2	0x2662
+#define PCI_DEVICE_ID_INTEL_82801FR_PCIE3	0x2664
+#define PCI_DEVICE_ID_INTEL_82801FR_PCIE4	0x2666
+#define PCI_DEVICE_ID_INTEL_82801FR_HD_AUDIO	0x2668
+#define PCI_DEVICE_ID_INTEL_82801FR_SMB		0x266a
+#define PCI_DEVICE_ID_INTEL_82801FR_AC97_MODEM	0x266d
+#define PCI_DEVICE_ID_INTEL_82801FR_AC97_AUDIO	0x266e
+#define PCI_DEVICE_ID_INTEL_82801FR_IDE		0x266f
+
+/* Intel 82801FW (ICH6W) */
+#define PCI_DEVICE_ID_INTEL_82801FW_LAN		0x1065
+#define PCI_DEVICE_ID_INTEL_82801FW_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801FW_LPC		0x2642
+#define PCI_DEVICE_ID_INTEL_82801FW_SATA	0x2651
+#define PCI_DEVICE_ID_INTEL_82801FW_USB1	0x2658
+#define PCI_DEVICE_ID_INTEL_82801FW_USB2	0x2659
+#define PCI_DEVICE_ID_INTEL_82801FW_USB3	0x265a
+#define PCI_DEVICE_ID_INTEL_82801FW_USB4	0x265b
+#define PCI_DEVICE_ID_INTEL_82801FW_EHCI	0x265c
+#define PCI_DEVICE_ID_INTEL_82801FW_PCIE1	0x2660
+#define PCI_DEVICE_ID_INTEL_82801FW_PCIE2	0x2662
+#define PCI_DEVICE_ID_INTEL_82801FW_PCIE3	0x2664
+#define PCI_DEVICE_ID_INTEL_82801FW_PCIE4	0x2666
+#define PCI_DEVICE_ID_INTEL_82801FW_HD_AUDIO	0x2668
+#define PCI_DEVICE_ID_INTEL_82801FW_SMB		0x266a
+#define PCI_DEVICE_ID_INTEL_82801FW_AC97_MODEM	0x266d
+#define PCI_DEVICE_ID_INTEL_82801FW_AC97_AUDIO	0x266e
+#define PCI_DEVICE_ID_INTEL_82801FW_IDE		0x266f
+
+/* Intel 82801FRW (ICH6RW) */
+#define PCI_DEVICE_ID_INTEL_82801FRW_LAN	0x1065
+#define PCI_DEVICE_ID_INTEL_82801FRW_PCI	0x244e
+#define PCI_DEVICE_ID_INTEL_82801FRW_LPC	0x2642
+#define PCI_DEVICE_ID_INTEL_82801FRW_SATA	0x2652
+#define PCI_DEVICE_ID_INTEL_82801FRW_USB1	0x2658
+#define PCI_DEVICE_ID_INTEL_82801FRW_USB2	0x2659
+#define PCI_DEVICE_ID_INTEL_82801FRW_USB3	0x265a
+#define PCI_DEVICE_ID_INTEL_82801FRW_USB4	0x265b
+#define PCI_DEVICE_ID_INTEL_82801FRW_EHCI	0x265c
+#define PCI_DEVICE_ID_INTEL_82801FRW_PCIE1	0x2660
+#define PCI_DEVICE_ID_INTEL_82801FRW_PCIE2	0x2662
+#define PCI_DEVICE_ID_INTEL_82801FRW_PCIE3	0x2664
+#define PCI_DEVICE_ID_INTEL_82801FRW_PCIE4	0x2666
+#define PCI_DEVICE_ID_INTEL_82801FRW_HD_AUDIO	0x2668
+#define PCI_DEVICE_ID_INTEL_82801FRW_SMB	0x266a
+#define PCI_DEVICE_ID_INTEL_82801FRW_AC97_MODEM	0x266d
+#define PCI_DEVICE_ID_INTEL_82801FRW_AC97_AUDIO	0x266e
+#define PCI_DEVICE_ID_INTEL_82801FRW_IDE	0x266f
+
+/* Intel 82801FBM (ICH6-M) */
+#define PCI_DEVICE_ID_INTEL_82801FBM_LAN	0x1065
+#define PCI_DEVICE_ID_INTEL_82801FBM_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801FBM_LPC	0x2641
+#define PCI_DEVICE_ID_INTEL_82801FBM_SATA	0x2653
+#define PCI_DEVICE_ID_INTEL_82801FBM_USB1	0x2658
+#define PCI_DEVICE_ID_INTEL_82801FBM_USB2	0x2659
+#define PCI_DEVICE_ID_INTEL_82801FBM_USB3	0x265a
+#define PCI_DEVICE_ID_INTEL_82801FBM_USB4	0x265b
+#define PCI_DEVICE_ID_INTEL_82801FBM_EHCI	0x265c
+#define PCI_DEVICE_ID_INTEL_82801FBM_PCIE1	0x2660
+#define PCI_DEVICE_ID_INTEL_82801FBM_PCIE2	0x2662
+#define PCI_DEVICE_ID_INTEL_82801FBM_PCIE3	0x2664
+#define PCI_DEVICE_ID_INTEL_82801FBM_PCIE4	0x2666
+#define PCI_DEVICE_ID_INTEL_82801FBM_HD_AUDIO	0x2668
+#define PCI_DEVICE_ID_INTEL_82801FBM_SMB	0x266a
+#define PCI_DEVICE_ID_INTEL_82801FBM_AC97_MODEM	0x266d
+#define PCI_DEVICE_ID_INTEL_82801FBM_AC97_AUDIO	0x266e
+#define PCI_DEVICE_ID_INTEL_82801FBM_IDE	0x266f
+
+/* Intel 82801GB (ICH7) */
+#define PCI_DEVICE_ID_INTEL_82801GB_LAN		0x27dc
+#define PCI_DEVICE_ID_INTEL_82801GB_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801GB_LPC		0x27b8
+#define PCI_DEVICE_ID_INTEL_82801GB_SATA	0x27c0
+#define PCI_DEVICE_ID_INTEL_82801GB_SATA_AHCI	0x27c1
+#define PCI_DEVICE_ID_INTEL_82801GB_SATA_RAID	0x27c3
+#define PCI_DEVICE_ID_INTEL_82801GB_USB1	0x27c8
+#define PCI_DEVICE_ID_INTEL_82801GB_USB2	0x27c9
+#define PCI_DEVICE_ID_INTEL_82801GB_USB3	0x27ca
+#define PCI_DEVICE_ID_INTEL_82801GB_USB4	0x27cb
+#define PCI_DEVICE_ID_INTEL_82801GB_EHCI	0x27cc
+#define PCI_DEVICE_ID_INTEL_82801GB_PCIE1	0x27d0
+#define PCI_DEVICE_ID_INTEL_82801GB_PCIE2	0x27d2
+#define PCI_DEVICE_ID_INTEL_82801GB_PCIE3	0x27d4
+#define PCI_DEVICE_ID_INTEL_82801GB_PCIE4	0x27d6
+#define PCI_DEVICE_ID_INTEL_82801GB_HD_AUDIO	0x27d8
+#define PCI_DEVICE_ID_INTEL_82801GB_SMB		0x27da
+#define PCI_DEVICE_ID_INTEL_82801GB_AC97_MODEM	0x27de
+#define PCI_DEVICE_ID_INTEL_82801GB_AC97_AUDIO	0x27dd
+#define PCI_DEVICE_ID_INTEL_82801GB_IDE		0x27df
+
+/* Intel 82801GR (ICH7R) */
+#define PCI_DEVICE_ID_INTEL_82801GR_LAN		0x27dc
+#define PCI_DEVICE_ID_INTEL_82801GR_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801GR_LPC		0x27b8
+#define PCI_DEVICE_ID_INTEL_82801GR_SATA	0x27c0
+#define PCI_DEVICE_ID_INTEL_82801GR_SATA_AHCI	0x27c1
+#define PCI_DEVICE_ID_INTEL_82801GR_SATA_RAID	0x27c3
+#define PCI_DEVICE_ID_INTEL_82801GR_USB1	0x27c8
+#define PCI_DEVICE_ID_INTEL_82801GR_USB2	0x27c9
+#define PCI_DEVICE_ID_INTEL_82801GR_USB3	0x27ca
+#define PCI_DEVICE_ID_INTEL_82801GR_USB4	0x27cb
+#define PCI_DEVICE_ID_INTEL_82801GR_EHCI	0x27cc
+#define PCI_DEVICE_ID_INTEL_82801GR_PCIE1	0x27d0
+#define PCI_DEVICE_ID_INTEL_82801GR_PCIE2	0x27d2
+#define PCI_DEVICE_ID_INTEL_82801GR_PCIE3	0x27d4
+#define PCI_DEVICE_ID_INTEL_82801GR_PCIE4	0x27d6
+#define PCI_DEVICE_ID_INTEL_82801GR_PCIE5	0x27e0
+#define PCI_DEVICE_ID_INTEL_82801GR_PCIE6	0x27e2
+#define PCI_DEVICE_ID_INTEL_82801GR_HD_AUDIO	0x27d8
+#define PCI_DEVICE_ID_INTEL_82801GR_SMB		0x27da
+#define PCI_DEVICE_ID_INTEL_82801GR_AC97_MODEM	0x27de
+#define PCI_DEVICE_ID_INTEL_82801GR_AC97_AUDIO	0x27dd
+#define PCI_DEVICE_ID_INTEL_82801GR_IDE		0x27df
+
+/* Intel 82801GDH (ICH7DH) */
+#define PCI_DEVICE_ID_INTEL_82801GDH_LAN	0x27dc
+#define PCI_DEVICE_ID_INTEL_82801GDH_PCI	0x244e
+#define PCI_DEVICE_ID_INTEL_82801GDH_LPC	0x27b8
+#define PCI_DEVICE_ID_INTEL_82801GDH_SATA	0x27c0
+#define PCI_DEVICE_ID_INTEL_82801GDH_SATA_AHCI	0x27c1
+#define PCI_DEVICE_ID_INTEL_82801GDH_SATA_RAID	0x27c3
+#define PCI_DEVICE_ID_INTEL_82801GDH_USB1	0x27c8
+#define PCI_DEVICE_ID_INTEL_82801GDH_USB2	0x27c9
+#define PCI_DEVICE_ID_INTEL_82801GDH_USB3	0x27ca
+#define PCI_DEVICE_ID_INTEL_82801GDH_USB4	0x27cb
+#define PCI_DEVICE_ID_INTEL_82801GDH_EHCI	0x27cc
+#define PCI_DEVICE_ID_INTEL_82801GDH_PCIE1	0x27d0
+#define PCI_DEVICE_ID_INTEL_82801GDH_PCIE2	0x27d2
+#define PCI_DEVICE_ID_INTEL_82801GDH_PCIE3	0x27d4
+#define PCI_DEVICE_ID_INTEL_82801GDH_PCIE4	0x27d6
+#define PCI_DEVICE_ID_INTEL_82801GDH_PCIE5	0x27e0
+#define PCI_DEVICE_ID_INTEL_82801GDH_PCIE6	0x27e2
+#define PCI_DEVICE_ID_INTEL_82801GDH_HD_AUDIO	0x27d8
+#define PCI_DEVICE_ID_INTEL_82801GDH_SMB	0x27da
+#define PCI_DEVICE_ID_INTEL_82801GDH_AC97_MODEM	0x27de
+#define PCI_DEVICE_ID_INTEL_82801GDH_AC97_AUDIO	0x27dd
+#define PCI_DEVICE_ID_INTEL_82801GDH_IDE	0x27df
+
+/* Intel 82801GBM (ICH7-M) */
+#define PCI_DEVICE_ID_INTEL_82801GBM_LAN	0x27dc
+#define PCI_DEVICE_ID_INTEL_82801GBM_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801GBM_LPC	0x27b9
+#define PCI_DEVICE_ID_INTEL_82801GBM_SATA	0x27c4
+#define PCI_DEVICE_ID_INTEL_82801GBM_SATA_AHCI	0x27c5
+#define PCI_DEVICE_ID_INTEL_82801GBM_USB1	0x27c8
+#define PCI_DEVICE_ID_INTEL_82801GBM_USB2	0x27c9
+#define PCI_DEVICE_ID_INTEL_82801GBM_USB3	0x27ca
+#define PCI_DEVICE_ID_INTEL_82801GBM_USB4	0x27cb
+#define PCI_DEVICE_ID_INTEL_82801GBM_EHCI	0x27cc
+#define PCI_DEVICE_ID_INTEL_82801GBM_PCIE1	0x27d0
+#define PCI_DEVICE_ID_INTEL_82801GBM_PCIE2	0x27d2
+#define PCI_DEVICE_ID_INTEL_82801GBM_PCIE3	0x27d4
+#define PCI_DEVICE_ID_INTEL_82801GBM_PCIE4	0x27d6
+#define PCI_DEVICE_ID_INTEL_82801GBM_HD_AUDIO	0x27d8
+#define PCI_DEVICE_ID_INTEL_82801GBM_SMB	0x27da
+#define PCI_DEVICE_ID_INTEL_82801GBM_AC97_MODEM	0x27de
+#define PCI_DEVICE_ID_INTEL_82801GBM_AC97_AUDIO	0x27dd
+#define PCI_DEVICE_ID_INTEL_82801GBM_IDE	0x27df
+
+/* Intel 82801GHM (ICH7-M DH) */
+#define PCI_DEVICE_ID_INTEL_82801GHM_LAN	0x27dc
+#define PCI_DEVICE_ID_INTEL_82801GHM_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801GHM_LPC	0x27bd
+#define PCI_DEVICE_ID_INTEL_82801GHM_SATA	0x27c4
+#define PCI_DEVICE_ID_INTEL_82801GHM_SATA_AHCI	0x27c5
+#define PCI_DEVICE_ID_INTEL_82801GHM_SATA_RAID	0x27c6
+#define PCI_DEVICE_ID_INTEL_82801GHM_USB1	0x27c8
+#define PCI_DEVICE_ID_INTEL_82801GHM_USB2	0x27c9
+#define PCI_DEVICE_ID_INTEL_82801GHM_USB3	0x27ca
+#define PCI_DEVICE_ID_INTEL_82801GHM_USB4	0x27cb
+#define PCI_DEVICE_ID_INTEL_82801GHM_EHCI	0x27cc
+#define PCI_DEVICE_ID_INTEL_82801GHM_PCIE1	0x27d0
+#define PCI_DEVICE_ID_INTEL_82801GHM_PCIE2	0x27d2
+#define PCI_DEVICE_ID_INTEL_82801GHM_PCIE3	0x27d4
+#define PCI_DEVICE_ID_INTEL_82801GHM_PCIE4	0x27d6
+#define PCI_DEVICE_ID_INTEL_82801GHM_PCIE5	0x27e0
+#define PCI_DEVICE_ID_INTEL_82801GHM_PCIE6	0x27e2
+#define PCI_DEVICE_ID_INTEL_82801GHM_HD_AUDIO	0x27d8
+#define PCI_DEVICE_ID_INTEL_82801GHM_SMB	0x27da
+#define PCI_DEVICE_ID_INTEL_82801GHM_AC97_MODEM	0x27de
+#define PCI_DEVICE_ID_INTEL_82801GHM_AC97_AUDIO	0x27dd
+#define PCI_DEVICE_ID_INTEL_82801GHM_IDE	0x27df
+
+/* Intel 82801GU (ICH7-U) */
+#define PCI_DEVICE_ID_INTEL_82801GU_PCI		0x2448
+#define PCI_DEVICE_ID_INTEL_82801GU_LPC		0x27b9
+#define PCI_DEVICE_ID_INTEL_82801GU_USB1	0x27c8
+#define PCI_DEVICE_ID_INTEL_82801GU_USB2	0x27c9
+#define PCI_DEVICE_ID_INTEL_82801GU_USB3	0x27ca
+#define PCI_DEVICE_ID_INTEL_82801GU_USB4	0x27cb
+#define PCI_DEVICE_ID_INTEL_82801GU_EHCI	0x27cc
+#define PCI_DEVICE_ID_INTEL_82801GU_HD_AUDIO	0x27d8
+#define PCI_DEVICE_ID_INTEL_82801GU_SMB		0x27da
+#define PCI_DEVICE_ID_INTEL_82801GU_IDE		0x27df
+
+/* Intel 82801HB (ICH8) */
+#define PCI_DEVICE_ID_INTEL_82801HB_LAN		0x104b
+#define PCI_DEVICE_ID_INTEL_82801HB_LPC		0x2810
+#define PCI_DEVICE_ID_INTEL_82801HB_SATA1	0x2820
+#define PCI_DEVICE_ID_INTEL_82801HB_SATA_AHCI_6	0x2821 /* 6 ports */
+#define PCI_DEVICE_ID_INTEL_82801HB_SATA_RAID	0x2822
+#define PCI_DEVICE_ID_INTEL_82801HB_SATA_AHCI_4	0x2824 /* 4 ports */
+#define PCI_DEVICE_ID_INTEL_82801HB_SATA2	0x2825
+#define PCI_DEVICE_ID_INTEL_82801HB_SMB		0x283e
+#define PCI_DEVICE_ID_INTEL_82801HB_THERMAL	0x284f
+#define PCI_DEVICE_ID_INTEL_82801HB_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_82801HB_USB1	0x2830
+#define PCI_DEVICE_ID_INTEL_82801HB_USB2	0x2831
+#define PCI_DEVICE_ID_INTEL_82801HB_USB3	0x2832
+#define PCI_DEVICE_ID_INTEL_82801HB_EHCI1	0x2836
+#define PCI_DEVICE_ID_INTEL_82801HB_USB4	0x2834
+#define PCI_DEVICE_ID_INTEL_82801HB_USB5	0x2835
+#define PCI_DEVICE_ID_INTEL_82801HB_EHCI2	0x283a
+#define PCI_DEVICE_ID_INTEL_82801HB_PCIE1	0x283f
+#define PCI_DEVICE_ID_INTEL_82801HB_PCIE2	0x2841
+#define PCI_DEVICE_ID_INTEL_82801HB_PCIE3	0x2843
+#define PCI_DEVICE_ID_INTEL_82801HB_PCIE4	0x2845
+#define PCI_DEVICE_ID_INTEL_82801HB_PCIE5	0x2847
+#define PCI_DEVICE_ID_INTEL_82801HB_PCIE6	0x2849
+#define PCI_DEVICE_ID_INTEL_82801HB_HD_AUDIO	0x284b
+
+/* Intel 82801HR/HH/HO (ICH8R/ICH8DH/ICH8DO), only difference to ICH8: LPC */
+#define PCI_DEVICE_ID_INTEL_82801HR_LPC		0x2810
+#define PCI_DEVICE_ID_INTEL_82801HH_LPC		0x2812
+#define PCI_DEVICE_ID_INTEL_82801HO_LPC		0x2814
+
+/* Intel 82801HBM/HEM (ICH8M/ICH8M-E) */
+#define PCI_DEVICE_ID_INTEL_82801HBM_LAN	0x104b
+#define PCI_DEVICE_ID_INTEL_82801HBM_LPC	0x2815
+#define PCI_DEVICE_ID_INTEL_82801HBM_SATA	0x2828
+#define PCI_DEVICE_ID_INTEL_82801HBM_SATA_AHCI	0x2829
+#define PCI_DEVICE_ID_INTEL_82801HBM_SATA_RAID	0x282a
+#define PCI_DEVICE_ID_INTEL_82801HBM_SMB	0x283e
+#define PCI_DEVICE_ID_INTEL_82801HBM_THERMAL	0x284f
+#define PCI_DEVICE_ID_INTEL_82801HBM_PCI	0x2448
+#define PCI_DEVICE_ID_INTEL_82801HBM_IDE	0x2850 /* TODO: Also ICH8M-E? */
+#define PCI_DEVICE_ID_INTEL_82801HBM_USB1	0x2830
+#define PCI_DEVICE_ID_INTEL_82801HBM_USB2	0x2831
+#define PCI_DEVICE_ID_INTEL_82801HBM_USB3	0x2832
+#define PCI_DEVICE_ID_INTEL_82801HBM_EHCI1	0x2836
+#define PCI_DEVICE_ID_INTEL_82801HBM_USB4	0x2834
+#define PCI_DEVICE_ID_INTEL_82801HBM_USB5	0x2835
+#define PCI_DEVICE_ID_INTEL_82801HBM_EHCI2	0x283a
+#define PCI_DEVICE_ID_INTEL_82801HBM_PCIE1	0x283f
+#define PCI_DEVICE_ID_INTEL_82801HBM_PCIE2	0x2841
+#define PCI_DEVICE_ID_INTEL_82801HBM_PCIE3	0x2843
+#define PCI_DEVICE_ID_INTEL_82801HBM_PCIE4	0x2845
+#define PCI_DEVICE_ID_INTEL_82801HBM_PCIE5	0x2847
+#define PCI_DEVICE_ID_INTEL_82801HBM_PCIE6	0x2849
+#define PCI_DEVICE_ID_INTEL_82801HBM_HD_AUDIO	0x284b
+
+/* Intel 82801HEM (ICH8M-E), only difference to ICH8M: LPC */
+#define PCI_DEVICE_ID_INTEL_82801HEM_LPC	0x2811
+
+/* Intel 82801IB (ICH9) */
+#define PCI_DEVICE_ID_INTEL_82801IB_LPC		0x2918
+#define PCI_DEVICE_ID_INTEL_82801IB_SATA_P0123	0x2920 /* Ports 0 - 3 */
+#define PCI_DEVICE_ID_INTEL_82801IB_SATA_P01	0x2921 /* Ports 0 - 1 */
+#define PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI1	0x2922 /* Ports 0 - 5 */
+#define PCI_DEVICE_ID_INTEL_82801IB_SATA_AHCI2	0x2923 /* Ports 0, 1, 4, 5 */
+#define PCI_DEVICE_ID_INTEL_82801IB_SATA_RAID	0x2822 /* RAID */
+#define PCI_DEVICE_ID_INTEL_82801IB_SATA_P45	0x2926 /* Ports 4 - 5 */
+#define PCI_DEVICE_ID_INTEL_82801IB_SMB		0x2930
+#define PCI_DEVICE_ID_INTEL_82801IB_THERMAL	0x2932
+#define PCI_DEVICE_ID_INTEL_82801IB_PCI		0x244e /* DMI to PCI bridge */
+#define PCI_DEVICE_ID_INTEL_82801IB_USB1	0x2934
+#define PCI_DEVICE_ID_INTEL_82801IB_USB2	0x2935
+#define PCI_DEVICE_ID_INTEL_82801IB_USB3	0x2936
+#define PCI_DEVICE_ID_INTEL_82801IB_EHCI1	0x293a
+#define PCI_DEVICE_ID_INTEL_82801IB_USB4	0x2937
+#define PCI_DEVICE_ID_INTEL_82801IB_USB5	0x2938
+#define PCI_DEVICE_ID_INTEL_82801IB_USB6	0x2939
+#define PCI_DEVICE_ID_INTEL_82801IB_EHCI2	0x293c
+#define PCI_DEVICE_ID_INTEL_82801IB_HD_AUDIO	0x293e
+#define PCI_DEVICE_ID_INTEL_82801IB_PCIE1	0x2940
+#define PCI_DEVICE_ID_INTEL_82801IB_PCIE2	0x2942
+#define PCI_DEVICE_ID_INTEL_82801IB_PCIE3	0x2944
+#define PCI_DEVICE_ID_INTEL_82801IB_PCIE4	0x2946
+#define PCI_DEVICE_ID_INTEL_82801IB_PCIE5	0x2948
+#define PCI_DEVICE_ID_INTEL_82801IB_PCIE6	0x294a
+#define PCI_DEVICE_ID_INTEL_82801IB_LAN		0x29c4
+
+/* Intel 82801IR/IH/IO (ICH9R/ICH9DH/ICH9DO), only difference to ICH9: LPC */
+#define PCI_DEVICE_ID_INTEL_82801IR_LPC		0x2916
+#define PCI_DEVICE_ID_INTEL_82801IO_LPC		0x2914
+#define PCI_DEVICE_ID_INTEL_82801IH_LPC		0x2912
+
 /* Intel 82801E (C-ICH) */
 #define PCI_DEVICE_ID_INTEL_82801E_LPC		0x2450
 #define PCI_DEVICE_ID_INTEL_82801E_USB		0x2452
@@ -1969,20 +2300,22 @@
 #define PCI_DEVICE_ID_INTEL_82820FW_5 0x244b
 #define PCI_DEVICE_ID_INTEL_82820FW_6 0x244e
 
-#define PCI_DEVICE_ID_INTEL_6300ESB_ISA  0x25a1
-#define PCI_DEVICE_ID_INTEL_6300ESB_AC97_AUDIO 0x25a6
-#define PCI_DEVICE_ID_INTEL_6300ESB_AC97_MODEM 0x25a7
-#define PCI_DEVICE_ID_INTEL_6300ESB_EHCI 0x25ad
-#define PCI_DEVICE_ID_INTEL_6300ESB_IDE  0x25a2
-#define PCI_DEVICE_ID_INTEL_6300ESB_PCI  0x244e
-#define PCI_DEVICE_ID_INTEL_6300ESB_USB  0x25a9
-#define PCI_DEVICE_ID_INTEL_6300ESB_SMB  0x25a4
-#define PCI_DEVICE_ID_INTEL_6300ESB_USB2 0x25aa
-#define PCI_DEVICE_ID_INTEL_6300ESB_USB3 0x25ad
-#define PCI_DEVICE_ID_INTEL_6300ESB_SATA 0x25a3
-#define PCI_DEVICE_ID_INTEL_6300ESB_SATA_R 0x25b0
-#define PCI_DEVICE_ID_INTEL_6300ESB_PIC1 0x25ac
-#define PCI_DEVICE_ID_INTEL_6300ESB_BRIDGE1C 0x25ae
+/* Intel 6300ESB */
+#define PCI_DEVICE_ID_INTEL_6300ESB_LPC		0x25a1
+#define PCI_DEVICE_ID_INTEL_6300ESB_AC97_AUDIO	0x25a6
+#define PCI_DEVICE_ID_INTEL_6300ESB_AC97_MODEM	0x25a7
+#define PCI_DEVICE_ID_INTEL_6300ESB_EHCI	0x25ad
+#define PCI_DEVICE_ID_INTEL_6300ESB_IDE		0x25a2
+#define PCI_DEVICE_ID_INTEL_6300ESB_PCI		0x244e
+#define PCI_DEVICE_ID_INTEL_6300ESB_USB1	0x25a9
+#define PCI_DEVICE_ID_INTEL_6300ESB_SMB		0x25a4
+#define PCI_DEVICE_ID_INTEL_6300ESB_USB2	0x25aa
+#define PCI_DEVICE_ID_INTEL_6300ESB_SATA	0x25a3
+#define PCI_DEVICE_ID_INTEL_6300ESB_SATA_RAID	0x25b0
+#define PCI_DEVICE_ID_INTEL_6300ESB_APIC1	0x25ac
+#define PCI_DEVICE_ID_INTEL_6300ESB_PCI_X	0x25ae
+#define PCI_DEVICE_ID_INTEL_6300ESB_WDT		0x25ab
+
 #define PCI_DEVICE_ID_INTEL_80310	0x530d
 #define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
 #define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121

Modified: trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/reset.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/reset.c	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/mainboard/supermicro/x6dai_g/reset.c	2007-11-07 00:19:42 UTC (rev 2947)
@@ -26,7 +26,7 @@
 {
 	device_t dev;
 	/* Enable power on after power fail... */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_6300ESB_ISA), 0);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_6300ESB_LPC), 0);
 	if (dev != PCI_DEV_INVALID) {
 		unsigned byte;
 		byte = pci_read_config8(dev, 0xa4);

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300.c	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300.c	2007-11-07 00:19:42 UTC (rev 2947)
@@ -22,11 +22,11 @@
 		return;
 	}
 	if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
-		(lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_ISA)) {
+		(lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_LPC)) {
 		uint32_t id;
 		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
 		if (id != (PCI_VENDOR_ID_INTEL | 
-				(PCI_DEVICE_ID_INTEL_6300ESB_ISA << 16))) {
+				(PCI_DEVICE_ID_INTEL_6300ESB_LPC << 16))) {
 			return;
 		}
 	}

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_bridge1c.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_bridge1c.c	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_bridge1c.c	2007-11-07 00:19:42 UTC (rev 2947)
@@ -46,6 +46,6 @@
 static const struct pci_driver pci_driver __pci_driver = {
 	.ops    = &pci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_6300ESB_BRIDGE1C,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_PCI_X,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_lpc.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_lpc.c	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_lpc.c	2007-11-07 00:19:42 UTC (rev 2947)
@@ -406,5 +406,5 @@
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops    = &lpc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_6300ESB_ISA,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_LPC,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_pic.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_pic.c	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_pic.c	2007-11-07 00:19:42 UTC (rev 2947)
@@ -104,6 +104,6 @@
 static const struct pci_driver pci_driver __pci_driver = {
 	.ops    = &pci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_6300ESB_PIC1,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_APIC1,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_sata.c	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_sata.c	2007-11-07 00:19:42 UTC (rev 2947)
@@ -72,6 +72,6 @@
 static const struct pci_driver sata_driver_nr __pci_driver = {
         .ops    = &sata_ops,
         .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA_R,
+        .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA_RAID,
 };
 

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_uhci.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_uhci.c	2007-11-05 22:35:01 UTC (rev 2946)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/esb6300/esb6300_uhci.c	2007-11-07 00:19:42 UTC (rev 2947)
@@ -36,10 +36,10 @@
 	.ops_pci          = &lops_pci,
 };
 
-static const struct pci_driver uhci_driver __pci_driver = {
+static const struct pci_driver usb1_driver __pci_driver = {
 	.ops    = &uhci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB1,
 };
 
 static const struct pci_driver usb2_driver __pci_driver = {
@@ -48,9 +48,10 @@
 	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB2,
 };
 
-static const struct pci_driver usb3_driver __pci_driver = {
+/* Note: May or may not need different init than UHCI. */
+static const struct pci_driver ehci_driver __pci_driver = {
 	.ops    = &uhci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB3,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI,
 };
 




From jordan.crouse at amd.com  Wed Nov  7 01:19:31 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 6 Nov 2007 17:19:31 -0700
Subject: [LinuxBIOS] BIOS compatibility [was: memory table address]
In-Reply-To: <20071107001227.19106.qmail@stuge.se>
References: <20071106202843.GB28780@thorin>
	<20071106235525.GA22963@coresystems.de>
	<20071107001227.19106.qmail@stuge.se>
Message-ID: <20071107001931.GA5607@cosmic.amd.com>

On 07/11/07 01:12 +0100, Peter Stuge wrote:
> On Wed, Nov 07, 2007 at 12:55:25AM +0100, Stefan Reinauer wrote:
> > bios compatibility
> 
> I would like any BIOS compatibility to be opt-in, and to be
> uninteresting because of new shinyness offered by LB and
> understood by all. :)

Except of course, the e820 table parser in the kernel... :)

> 
> //Peter
> 
> -- 
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
> 
> 

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From peter at stuge.se  Wed Nov  7 01:54:56 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 7 Nov 2007 01:54:56 +0100
Subject: [LinuxBIOS] BIOS compatibility [was: memory table address]
In-Reply-To: <20071107001931.GA5607@cosmic.amd.com>
References: <20071106202843.GB28780@thorin>
	<20071106235525.GA22963@coresystems.de>
	<20071107001227.19106.qmail@stuge.se>
	<20071107001931.GA5607@cosmic.amd.com>
Message-ID: <20071107005456.26779.qmail@stuge.se>

On Tue, Nov 06, 2007 at 05:19:31PM -0700, Jordan Crouse wrote:
> > I would like any BIOS compatibility to be opt-in, and to be
> > uninteresting because of new shinyness offered by LB and
> > understood by all. :)
> 
> Except of course, the e820 table parser in the kernel... :)

Not neccessarily. Only if that really is a plenty good interface for
the task. And maybe not even then, if there are enough other things
that shall be passed to the payload.

What is the status of the OFW device tree parser in x86 Linux?

Do we still want to go with that or roll our own LB->payload
interface?

Yes - we are re-inventing the wheel, but maybe we can improve it.


//Peter



From peter at stuge.se  Wed Nov  7 01:56:25 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 7 Nov 2007 01:56:25 +0100
Subject: [LinuxBIOS] Thinkpad EC reveng
Message-ID: <20071107005625.27144.qmail@stuge.se>

Yeah. Too bad I no longer have the T43p. :(

http://forum.thinkpads.com/viewtopic.php?t=20958


//Peter



From jordan.crouse at amd.com  Wed Nov  7 03:32:19 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 6 Nov 2007 19:32:19 -0700
Subject: [LinuxBIOS] BIOS compatibility [was: memory table address]
In-Reply-To: <20071107005456.26779.qmail@stuge.se>
References: <20071106202843.GB28780@thorin>
	<20071106235525.GA22963@coresystems.de>
	<20071107001227.19106.qmail@stuge.se>
	<20071107001931.GA5607@cosmic.amd.com>
	<20071107005456.26779.qmail@stuge.se>
Message-ID: <20071107023219.GA7509@cosmic.amd.com>

On 07/11/07 01:54 +0100, Peter Stuge wrote:
> On Tue, Nov 06, 2007 at 05:19:31PM -0700, Jordan Crouse wrote:
> > > I would like any BIOS compatibility to be opt-in, and to be
> > > uninteresting because of new shinyness offered by LB and
> > > understood by all. :)
> > 
> > Except of course, the e820 table parser in the kernel... :)
> 
> Not neccessarily. Only if that really is a plenty good interface for
> the task. And maybe not even then, if there are enough other things
> that shall be passed to the payload.
> 
> What is the status of the OFW device tree parser in x86 Linux?

Its in the OLPC tree - I don't know if its made it all the way up
stream yet - there was unpleasantness last year some time when they
tried to push it, I think that stalled then.

> Do we still want to go with that or roll our own LB->payload
> interface?

OFW device tree gets my vote.

Jordan
-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From rminnich at gmail.com  Wed Nov  7 04:30:18 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 6 Nov 2007 19:30:18 -0800
Subject: [LinuxBIOS] ALIX 1c final
Message-ID: <13426df10711061930o7baff79j7d4624152b28749e@mail.gmail.com>

Well, I hope this is it. My alix1c now works very well. I think the
IRQs are right.

Thanks again to Marc Jones for clearing me up on IRQ tables.

Attached.

ron
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From rminnich at gmail.com  Wed Nov  7 04:42:49 2007
From: rminnich at gmail.com (ron minnich)
Date: Tue, 6 Nov 2007 19:42:49 -0800
Subject: [LinuxBIOS] buildrom tyan s2891 and LAB
Message-ID: <13426df10711061942y62075150x2f34c9b1aa2f5c90@mail.gmail.com>

I did a config for the 2891 with LAB, but all I see in deploy is this:
ls -l deploy/
total 7280
-rw-r--r-- 1 rminnich rminnich  905680 2007-11-06 19:36 bzImage
-rw-rw-r-- 1 rminnich rminnich  272384 2007-11-06 19:38 initrd.uncompressed
-rw-rw-r-- 1 rminnich rminnich  879963 2007-11-06 19:38 lab-payload.elf.lzma
-rw-r--r-- 1 rminnich rminnich 2108666 2007-11-06 19:38
lab-payload-uncompressed.elf
-rw-rw-r-- 1 rminnich rminnich 1011712 2007-11-06 19:38 tyan-s2891.rom
-rw-r--r-- 1 rminnich rminnich 2242990 2007-11-06 19:36 vmlinux

And the  only linuxbios.rom I see is this:
ls -l ./work/linuxbios/svn/targets/tyan/s2891/s2891/linuxbios.rom
-rw-rw-r-- 1 rminnich rminnich 1011712 2007-11-06 19:38
./work/linuxbios/svn/targets/tyan/s2891/s2891/linuxbios.rom


So where is the romimage? What am I missing?

ron



From Marc.Jones at AMD.com  Wed Nov  7 06:41:37 2007
From: Marc.Jones at AMD.com (Marc Jones)
Date: Tue, 06 Nov 2007 22:41:37 -0700
Subject: [LinuxBIOS] ALIX 1c final
In-Reply-To: <13426df10711061930o7baff79j7d4624152b28749e@mail.gmail.com>
References: <13426df10711061930o7baff79j7d4624152b28749e@mail.gmail.com>
Message-ID: <47315011.9010203@AMD.com>



ron minnich wrote:
> Well, I hope this is it. My alix1c now works very well. I think the
> IRQs are right.
>
> Thanks again to Marc Jones for clearing me up on IRQ tables.
>
> Attached.
>
> ron
>   

-default IRQ_SLOT_COUNT=9
+default IRQ_SLOT_COUNT=7

This should be IRQ_SLOT_COUNT=5
Otherwise it looks good to me. 

Acked-by: Marc Jones <marc.jones at amd.com>

-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors






From svn at openbios.org  Wed Nov  7 11:09:59 2007
From: svn at openbios.org (LinuxBIOS)
Date: Wed, 07 Nov 2007 10:09:59 -0000
Subject: [LinuxBIOS] #87: flashrom issues on m57sli-s4
In-Reply-To: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>
References: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>
Message-ID: <050.4b0884382e80b9c6cef0e3233e2a68ae@openbios.org>

#87: flashrom issues on m57sli-s4
-------------------------+--------------------------------------------------
    Reporter:  ward      |         Owner:  somebody         
        Type:  defect    |        Status:  new              
    Priority:  major     |     Milestone:                   
   Component:  flashrom  |       Version:  v2               
  Resolution:            |      Keywords:                   
Dependencies:            |   Patchstatus:  there is no patch
-------------------------+--------------------------------------------------
Comment (by hailfinger):

 Two possible reasons:

 * Differing LPC bus frequency.[[BR]]

 * Differing GPIO configuration, which may result in uninitialized #WP
 and/or #WE on the flash chip.

 You may want to verify both settings with an oscilloscope or any other
 tool you have handy. In case you want to verify correct settings from the
 software side, you have to make sure BIOS shadowing is disabled, then run
 a few timing trials of flash readout both under LB and proprietary. The
 speed should not differ. For GPIO configuration, check superiotool output
 differences and MCP55 GPIO registers (the latter may require a NDA to get
 a map of meanings).

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:2>
LinuxBIOS <http://www.linuxbios.org/>

From myles at pel.cs.byu.edu  Wed Nov  7 15:21:33 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 7 Nov 2007 07:21:33 -0700
Subject: [LinuxBIOS] buildrom tyan s2891 and LAB
In-Reply-To: <13426df10711061942y62075150x2f34c9b1aa2f5c90@mail.gmail.com>
References: <13426df10711061942y62075150x2f34c9b1aa2f5c90@mail.gmail.com>
Message-ID: <00f901c82149$7f9ca280$2402a8c0@chimp>


> I did a config for the 2891 with LAB, but all I see in deploy is this:
> ls -l deploy/
> total 7280
> -rw-r--r-- 1 rminnich rminnich  905680 2007-11-06 19:36 bzImage
> -rw-rw-r-- 1 rminnich rminnich  272384 2007-11-06 19:38
> initrd.uncompressed
> -rw-rw-r-- 1 rminnich rminnich  879963 2007-11-06 19:38 lab-
> payload.elf.lzma
> -rw-r--r-- 1 rminnich rminnich 2108666 2007-11-06 19:38
> lab-payload-uncompressed.elf
> -rw-rw-r-- 1 rminnich rminnich 1011712 2007-11-06 19:38 tyan-s2891.rom
> -rw-r--r-- 1 rminnich rminnich 2242990 2007-11-06 19:36 vmlinux
> 
> And the  only linuxbios.rom I see is this:
> ls -l ./work/linuxbios/svn/targets/tyan/s2891/s2891/linuxbios.rom
> -rw-rw-r-- 1 rminnich rminnich 1011712 2007-11-06 19:38
> ./work/linuxbios/svn/targets/tyan/s2891/s2891/linuxbios.rom
> 
> 
> So where is the romimage? What am I missing?
> ron

Check s2891deploy/

I think the s2891 config makes its own directory.

Myles> 





From ward at gnu.org  Wed Nov  7 15:31:30 2007
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 7 Nov 2007 09:31:30 -0500
Subject: [LinuxBIOS] buildrom tyan s2891 and LAB
In-Reply-To: <00f901c82149$7f9ca280$2402a8c0@chimp>
References: <13426df10711061942y62075150x2f34c9b1aa2f5c90@mail.gmail.com>
	<00f901c82149$7f9ca280$2402a8c0@chimp>
Message-ID: <20071107143130.GA8078@localdomain>

On Wed, Nov 07, 2007 at 07:21:33AM -0700, Myles Watson wrote:
> 
> > I did a config for the 2891 with LAB, but all I see in deploy is this:
> > ls -l deploy/
> > total 7280
> > -rw-r--r-- 1 rminnich rminnich  905680 2007-11-06 19:36 bzImage
> > -rw-rw-r-- 1 rminnich rminnich  272384 2007-11-06 19:38
> > initrd.uncompressed
> > -rw-rw-r-- 1 rminnich rminnich  879963 2007-11-06 19:38 lab-
> > payload.elf.lzma
> > -rw-r--r-- 1 rminnich rminnich 2108666 2007-11-06 19:38
> > lab-payload-uncompressed.elf
> > -rw-rw-r-- 1 rminnich rminnich 1011712 2007-11-06 19:38 tyan-s2891.rom
> > -rw-r--r-- 1 rminnich rminnich 2242990 2007-11-06 19:36 vmlinux
> > 
> > And the  only linuxbios.rom I see is this:
> > ls -l ./work/linuxbios/svn/targets/tyan/s2891/s2891/linuxbios.rom
> > -rw-rw-r-- 1 rminnich rminnich 1011712 2007-11-06 19:38
> > ./work/linuxbios/svn/targets/tyan/s2891/s2891/linuxbios.rom
> > 
> > 
> > So where is the romimage? What am I missing?

The tyan-s2891.rom file in deploy/ is the image; it expects you to prepend
the 36K vga rom to make it a full megabyte. The 36K vga rom is identical
across S2881, S2882 and S2891 (and possibly other Tyan servers; those are the
three models I have access to).

I really need to make work of that kconfig option for 'add vga bios after
compile'.

> Check s2891deploy/
> 
> I think the s2891 config makes its own directory.

Uhm, no :)

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From jordan.crouse at amd.com  Wed Nov  7 16:48:52 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 7 Nov 2007 08:48:52 -0700
Subject: [LinuxBIOS] buildrom tyan s2891 and LAB
In-Reply-To: <20071107143130.GA8078@localdomain>
References: <13426df10711061942y62075150x2f34c9b1aa2f5c90@mail.gmail.com>
	<00f901c82149$7f9ca280$2402a8c0@chimp>
	<20071107143130.GA8078@localdomain>
Message-ID: <20071107154851.GB5607@cosmic.amd.com>

On 07/11/07 09:31 -0500, Ward Vandewege wrote:
> I really need to make work of that kconfig option for 'add vga bios after
> compile'.

I'm assuming its not freely distributable?  If it is, then we can wget
it and prepend it automagically.  If its not, then we have two courses
of action:

1) user manually copies a file into deploy, calling it vga.bin.  buildrom
automatically prepends any file called vga.bin to the ROM (to further make
it configurable, each platform could specify the filename to prepend).

2) User specifies the location of the file with a config option, buildrom
grabs the file from there and prepends it (like we do with the "custom
payload" right now).

Thoughts?

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From corey.osgood at gmail.com  Wed Nov  7 17:27:49 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 11:27:49 -0500
Subject: [LinuxBIOS] buildrom tyan s2891 and LAB
In-Reply-To: <20071107154851.GB5607@cosmic.amd.com>
References: <13426df10711061942y62075150x2f34c9b1aa2f5c90@mail.gmail.com>	<00f901c82149$7f9ca280$2402a8c0@chimp>	<20071107143130.GA8078@localdomain>
	<20071107154851.GB5607@cosmic.amd.com>
Message-ID: <4731E785.60807@gmail.com>

Jordan Crouse wrote:
> On 07/11/07 09:31 -0500, Ward Vandewege wrote:
>   
>> I really need to make work of that kconfig option for 'add vga bios after
>> compile'.
>>     
>
> I'm assuming its not freely distributable?  If it is, then we can wget
> it and prepend it automagically.  If its not, then we have two courses
> of action:
>
> 1) user manually copies a file into deploy, calling it vga.bin.  buildrom
> automatically prepends any file called vga.bin to the ROM (to further make
> it configurable, each platform could specify the filename to prepend).
>
> 2) User specifies the location of the file with a config option, buildrom
> grabs the file from there and prepends it (like we do with the "custom
> payload" right now).
>
> Thoughts?
>
> Jordan
>   

3) wget the stock bios and amideco/awardeco, and extract/prepend the vga
bios automatically

-Corey



From myles at pel.cs.byu.edu  Wed Nov  7 17:38:30 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 7 Nov 2007 09:38:30 -0700
Subject: [LinuxBIOS] [PATCH] trivial Options.lb patch for serengeti-cheetah
Message-ID: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>

This patch adds this line to src/mainboard/amd/serengeti_cheetah/Options.lb:

uses CONFIG_PRECOMPRESSED_PAYLOAD
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From jordan.crouse at amd.com  Wed Nov  7 17:44:39 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 7 Nov 2007 09:44:39 -0700
Subject: [LinuxBIOS] buildrom tyan s2891 and LAB
In-Reply-To: <4731E785.60807@gmail.com>
References: <13426df10711061942y62075150x2f34c9b1aa2f5c90@mail.gmail.com>
	<00f901c82149$7f9ca280$2402a8c0@chimp>
	<20071107143130.GA8078@localdomain>
	<20071107154851.GB5607@cosmic.amd.com> <4731E785.60807@gmail.com>
Message-ID: <20071107164439.GC5607@cosmic.amd.com>

On 07/11/07 11:27 -0500, Corey Osgood wrote:
> Jordan Crouse wrote:
> > On 07/11/07 09:31 -0500, Ward Vandewege wrote:
> >   
> >> I really need to make work of that kconfig option for 'add vga bios after
> >> compile'.
> >>     
> >
> > I'm assuming its not freely distributable?  If it is, then we can wget
> > it and prepend it automagically.  If its not, then we have two courses
> > of action:
> >
> > 1) user manually copies a file into deploy, calling it vga.bin.  buildrom
> > automatically prepends any file called vga.bin to the ROM (to further make
> > it configurable, each platform could specify the filename to prepend).
> >
> > 2) User specifies the location of the file with a config option, buildrom
> > grabs the file from there and prepends it (like we do with the "custom
> > payload" right now).
> >
> > Thoughts?
> >
> > Jordan
> >   
> 
> 3) wget the stock bios and amideco/awardeco, and extract/prepend the vga
> bios automatically

That scares me a little.  Obviously, using the VGA BIOS from the stock
BIOS is fair use, but to me, exercising fair use dictates that the user
know and chose to excercise their rights.  Automating the process seems
a little dodgy to me - the user will end up with a VGA BIOS by methods
uknown.  Its a gray area, but I think we don't really want to be in this
business.  With the lack of a clear distribution policy (and this is where
we should all thank SiS again for getting the ball rolling and providing
a good example), then I think its not to much to ask the user to explicity
chose to excercise their rights to fair use.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.





From ward at gnu.org  Wed Nov  7 17:57:55 2007
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 7 Nov 2007 11:57:55 -0500
Subject: [LinuxBIOS] [PATCH] trivial Options.lb patch
	for	serengeti-cheetah
In-Reply-To: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>
References: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>
Message-ID: <20071107165755.GA9454@localdomain>

On Wed, Nov 07, 2007 at 09:38:30AM -0700, Myles Watson wrote:
> This patch adds this line to src/mainboard/amd/serengeti_cheetah/Options.lb:
> 
> uses CONFIG_PRECOMPRESSED_PAYLOAD

Please add a signed-off-by line. When you do that:

Acked-by: Ward Vandewege <ward at gnu.org>

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From corey.osgood at gmail.com  Wed Nov  7 17:57:53 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 11:57:53 -0500
Subject: [LinuxBIOS] [PATCH] trivial Options.lb patch for
	serengeti-cheetah
In-Reply-To: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>
References: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>
Message-ID: <4731EE91.4040108@gmail.com>

Myles Watson wrote:
> This patch adds this line to src/mainboard/amd/serengeti_cheetah/Options.lb:
>
> uses CONFIG_PRECOMPRESSED_PAYLOAD
>   
For what purpose? abuild or buildrom? Needs a signed-off-by line as
well, no matter how trivial.

-Corey



From ward at gnu.org  Wed Nov  7 18:00:25 2007
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 7 Nov 2007 12:00:25 -0500
Subject: [LinuxBIOS] [PATCH] trivial Options.lb patch
	for	serengeti-cheetah
In-Reply-To: <4731EE91.4040108@gmail.com>
References: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>
	<4731EE91.4040108@gmail.com>
Message-ID: <20071107170025.GA9514@localdomain>

On Wed, Nov 07, 2007 at 11:57:53AM -0500, Corey Osgood wrote:
> Myles Watson wrote:
> > This patch adds this line to src/mainboard/amd/serengeti_cheetah/Options.lb:
> >
> > uses CONFIG_PRECOMPRESSED_PAYLOAD
> >   
> For what purpose? abuild or buildrom? Needs a signed-off-by line as

Presumably to make the LZMA compression option work in buildrom. I've had to
add the same to the boards I've added to buildrom.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From myles at pel.cs.byu.edu  Wed Nov  7 18:05:40 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 7 Nov 2007 10:05:40 -0700
Subject: [LinuxBIOS] [PATCH] trivial Options.lb patch for
	serengeti-cheetah
In-Reply-To: <20071107170025.GA9514@localdomain>
References: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>
	<4731EE91.4040108@gmail.com> <20071107170025.GA9514@localdomain>
Message-ID: <2831fecf0711070905n9777203j2ded2384203d3f36@mail.gmail.com>

On 11/7/07, Ward Vandewege <ward at gnu.org> wrote:
> On Wed, Nov 07, 2007 at 11:57:53AM -0500, Corey Osgood wrote:
> > For what purpose? abuild or buildrom? Needs a signed-off-by line as
>
> Presumably to make the LZMA compression option work in buildrom. I've had to
> add the same to the boards I've added to buildrom.

Yes. Here it is again.
Is there some reason to economize uses statements?  It seems like this
one should be in all the Options.lb files.

Signed-off-by: Myles Watson <myles at pel.cs.byu.edu>
Thanks,
Myles
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From andi.mundt at web.de  Wed Nov  7 18:30:05 2007
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Wed, 7 Nov 2007 18:30:05 +0100
Subject: [LinuxBIOS] [patch] Fix M57SLI interrupt routing
In-Reply-To: <20071106211259.GA19605@localdomain>
References: <200711051204.12118.duwe@lst.de> <472F9B64.1040809@gmx.net>
	<200711060040.31696.duwe@lst.de> <200711060125.28594.duwe@lst.de>
	<20071106192126.GA17520@localdomain>
	<20071106210205.GA3713@flashgordon>
	<20071106211259.GA19605@localdomain>
Message-ID: <20071107173004.GA3820@flashgordon>

On Tue, Nov 06, 2007 at 04:12:59PM -0500, Ward Vandewege wrote:
> Hi Andi,
> 
> On Tue, Nov 06, 2007 at 10:02:05PM +0100, Andreas B. Mundt wrote:
> > unfortunately, for me flashrom still fails (I've never seen it working 
> > on my bord with LB, factory bios works).   
> 
> Yeah, same here, I was wrong :/
> 
> However, I'm glad you also see the problem - it's not just my board then
> (which had the plcc chip removed and a socket soldered on).
> 
> Did you also modify your board?
> 

Hi Ward, 

I used ST's approach with the socket soldered on the free patches:

http://private.vlsi.informatik.tu-darmstadt.de/st/instructions.html

Up to now, I just checked the new (socketed) BIOS chip with LB flashing 
because I have the proprietary BIOS still on the soldered chip. 
I could flip this if it turns out to cause the failure. 
But I don't think so.  

Regards,

	Andi



From andi.mundt at web.de  Wed Nov  7 18:47:34 2007
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Wed, 7 Nov 2007 18:47:34 +0100
Subject: [LinuxBIOS]  #87: flashrom issues on m57sli-s4
Message-ID: <20071107174734.GA4415@flashgordon>

Hi all,

I checked the delay loop calibration for proprietary and Linux BIOS with:

flashrom -V --read test.rom

Proprietary: 460, 261, 638, 260, 272, 669, 274, 664, 610, 484, 274 M loops per second.

Linux BIOS: 668, 675, 655, 675, 662, 662, 662, 675 M loops per second.

The speed varies much more for the proprietary BIOS, where flashrom works!? 
The results are independent of the chip I am reading from (the original or the socketed one). 

Andi



From corey.osgood at gmail.com  Wed Nov  7 18:48:35 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 12:48:35 -0500
Subject: [LinuxBIOS] [PATCH] Hide stdlib.h prototypes from ROMCC
Message-ID: <4731FA73.5020908@gmail.com>

See patch. This one needs an abuild test to make sure it doesn't break
anything.
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From corey.osgood at gmail.com  Wed Nov  7 18:49:59 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 12:49:59 -0500
Subject: [LinuxBIOS] [PATCH] More vt8237r fixes
Message-ID: <4731FAC7.6060301@gmail.com>

See patch. Rudolf, can you test this one to make sure it works correctly
on your board?

Thanks,
Corey
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From corey.osgood at gmail.com  Wed Nov  7 18:50:32 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 12:50:32 -0500
Subject: [LinuxBIOS] [PATCH] Add Via C7 support
Message-ID: <4731FAE8.9090000@gmail.com>

See patch
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From rminnich at gmail.com  Wed Nov  7 19:49:03 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 7 Nov 2007 10:49:03 -0800
Subject: [LinuxBIOS] [PATCH] Add Via C7 support
In-Reply-To: <4731FAE8.9090000@gmail.com>
References: <4731FAE8.9090000@gmail.com>
Message-ID: <13426df10711071049ya293b89sa4f1154c3bac61b3@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>


On Nov 7, 2007 9:50 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
> See patch
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>



From svn at openbios.org  Wed Nov  7 19:55:06 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed,  7 Nov 2007 19:55:06 +0100
Subject: [LinuxBIOS] r2948 - trunk/LinuxBIOSv2/src/cpu/via/model_centaur
Message-ID: <mailman.846.1355071197.16123.coreboot@coreboot.org>

Author: cozzie
Date: 2007-11-07 19:55:06 +0100 (Wed, 07 Nov 2007)
New Revision: 2948

Modified:
   trunk/LinuxBIOSv2/src/cpu/via/model_centaur/model_centaur_init.c
Log:
This patch adds the pci ids of c7 cpus to the existing model_centaur. c3 
and c7 init are identical, according to the datasheets, so there's no 
need for another folder. As the comment says, some of these model IDs 
may never be produced, but they are reserved by Via for the c7.

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/LinuxBIOSv2/src/cpu/via/model_centaur/model_centaur_init.c
===================================================================
--- trunk/LinuxBIOSv2/src/cpu/via/model_centaur/model_centaur_init.c	2007-11-07 00:19:42 UTC (rev 2947)
+++ trunk/LinuxBIOSv2/src/cpu/via/model_centaur/model_centaur_init.c	2007-11-07 18:55:06 UTC (rev 2948)
@@ -48,6 +48,16 @@
 	{ X86_VENDOR_CENTAUR, 0x0698 },		// VIA C3 Nehemiah
 	{ X86_VENDOR_CENTAUR, 0x0699 },		// VIA C3 Nehemiah
 	{ X86_VENDOR_CENTAUR, 0x069A },		// VIA C3 Nehemiah
+	/* Some of these may not actually exist */
+	{ X86_VENDOR_CENTAUR, 0x06A0 },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06A8 },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06A9 },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06AA },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06AB },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06AC },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06AD },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06AE },		// VIA C7 Esther
+	{ X86_VENDOR_CENTAUR, 0x06AF },		// VIA C7 Esther
 	{ 0, 0 },
 };
 




From corey.osgood at gmail.com  Wed Nov  7 19:55:05 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 13:55:05 -0500
Subject: [LinuxBIOS] [PATCH] Add Via C7 support
In-Reply-To: <13426df10711071049ya293b89sa4f1154c3bac61b3@mail.gmail.com>
References: <4731FAE8.9090000@gmail.com>
	<13426df10711071049ya293b89sa4f1154c3bac61b3@mail.gmail.com>
Message-ID: <47320A09.1030302@gmail.com>

r2948, thanks

-Corey

ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
>
> On Nov 7, 2007 9:50 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
>   
>> See patch
>>
>> --
>> linuxbios mailing list
>> linuxbios at linuxbios.org
>> http://www.linuxbios.org/mailman/listinfo/linuxbios
>>
>>     
>
>   




From svn at openbios.org  Wed Nov  7 20:02:35 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed,  7 Nov 2007 20:02:35 +0100
Subject: [LinuxBIOS] r2949 - in trunk/LinuxBIOSv2/src: include
	southbridge/via/vt8237r
Message-ID: <mailman.847.1355071197.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-11-07 20:02:35 +0100 (Wed, 07 Nov 2007)
New Revision: 2949

Modified:
   trunk/LinuxBIOSv2/src/include/stdlib.h
   trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
Log:
This patch masks the function prototypes in stdlib.h from ROMCC, so that
ARRAY_SIZE() can be used on ROMCC-dependent systems. Also adds stdlib.h
to vt8237r_early_smbus.c, so it'll build on those systems.

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/include/stdlib.h
===================================================================
--- trunk/LinuxBIOSv2/src/include/stdlib.h	2007-11-07 18:55:06 UTC (rev 2948)
+++ trunk/LinuxBIOSv2/src/include/stdlib.h	2007-11-07 19:02:35 UTC (rev 2949)
@@ -5,6 +5,7 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
+#ifndef __ROMCC__
 extern void *malloc(size_t size);
 void free(void *ptr);
 
@@ -12,5 +13,6 @@
 typedef size_t malloc_mark_t;
 void malloc_mark(malloc_mark_t *place);
 void malloc_release(malloc_mark_t *place);
+#endif
 
 #endif /* STDLIB_H */

Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2007-11-07 18:55:06 UTC (rev 2948)
+++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2007-11-07 19:02:35 UTC (rev 2949)
@@ -21,6 +21,7 @@
 
 #include <device/pci_ids.h>
 #include <spd.h>
+#include <stdlib.h>
 #include "vt8237r.h"
 
 /**




From uwe at hermann-uwe.de  Wed Nov  7 20:03:23 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 7 Nov 2007 20:03:23 +0100
Subject: [LinuxBIOS] [PATCH] Hide stdlib.h prototypes from ROMCC
In-Reply-To: <4731FA73.5020908@gmail.com>
References: <4731FA73.5020908@gmail.com>
Message-ID: <20071107190323.GA15728@greenwood>

On Wed, Nov 07, 2007 at 12:48:35PM -0500, Corey Osgood wrote:
> See patch. This one needs an abuild test to make sure it doesn't break
> anything.

> This patch masks the function prototypes in stdlib.h from ROMCC, so that
> ARRAY_SIZE() can be used on ROMCC-dependent systems. Also adds stdlib.h to
> vt8237r_early_smbus, so it'll build on those systems.
> 
> Signed-off-by: Corey Osgood <corey.osgood at gmail.com>

Looks good, r2949. abuild-tested by me, so nothing should break.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Wed Nov  7 20:07:18 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed,  7 Nov 2007 20:07:18 +0100
Subject: [LinuxBIOS] r2950 -
	trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah
Message-ID: <mailman.848.1355071197.16123.coreboot@coreboot.org>

Author: ward
Date: 2007-11-07 20:07:17 +0100 (Wed, 07 Nov 2007)
New Revision: 2950

Modified:
   trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb
Log:

Make the LZMA compression option work in buildrom.

Signed-off-by: Myles Watson <myles at pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb	2007-11-07 19:02:35 UTC (rev 2949)
+++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah/Options.lb	2007-11-07 19:07:17 UTC (rev 2950)
@@ -24,6 +24,7 @@
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses PAYLOAD_SIZE
 uses _ROMBASE
 uses XIP_ROM_SIZE




From ward at gnu.org  Wed Nov  7 20:10:05 2007
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 7 Nov 2007 14:10:05 -0500
Subject: [LinuxBIOS] [PATCH] trivial Options.lb patch
	for	serengeti-cheetah
In-Reply-To: <2831fecf0711070905n9777203j2ded2384203d3f36@mail.gmail.com>
References: <2831fecf0711070838w2adfc675j635b6b47dc54d557@mail.gmail.com>
	<4731EE91.4040108@gmail.com> <20071107170025.GA9514@localdomain>
	<2831fecf0711070905n9777203j2ded2384203d3f36@mail.gmail.com>
Message-ID: <20071107191005.GA10647@localdomain>

On Wed, Nov 07, 2007 at 10:05:40AM -0700, Myles Watson wrote:
> On 11/7/07, Ward Vandewege <ward at gnu.org> wrote:
> > On Wed, Nov 07, 2007 at 11:57:53AM -0500, Corey Osgood wrote:
> > > For what purpose? abuild or buildrom? Needs a signed-off-by line as
> >
> > Presumably to make the LZMA compression option work in buildrom. I've had to
> > add the same to the boards I've added to buildrom.
> 
> Yes. Here it is again.
> Is there some reason to economize uses statements?  It seems like this
> one should be in all the Options.lb files.

I can't see why not. Any other opinions?

> Signed-off-by: Myles Watson <myles at pel.cs.byu.edu>

Acked-by: Ward Vandewege <ward at gnu.org>

committed in r2950.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From corey.osgood at gmail.com  Wed Nov  7 20:13:06 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 14:13:06 -0500
Subject: [LinuxBIOS] Superiotool output on fintek f71805f
Message-ID: <47320E42.2060400@gmail.com>

Sorry, Thunderbird dumps emails more than a month old, so I don't have
the original message to respond to.

carpc:~/superiotool# superiotool
superiotool r2922
Found Fintek F71805F/FG (vid=0x3419, id=0x0604) at 0x4e
carpc:~/superiotool# superiotool -v
superiotool r2922
carpc:~/superiotool# superiotool -V
superiotool r2922
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
Found Fintek F71805F/FG (vid=0x3419, id=0x0604) at 0x4e
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0x0406, rev=0x3
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0x04/0x0f, rev=0x06
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
carpc:~/superiotool# superiotool -d
superiotool r2922
Found Fintek F71805F/FG (vid=0x3419, id=0x0604) at 0x4e
Register dump:
idx 07 20 21 23 24 25 26 27 28 29
val 03 04 06 19 34 00 03 20 08 00
def NA 04 06 19 34 00 00 3f 08 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f2 f4
val 01 03 f2 06 02 0e ff 00
def 01 03 f0 06 02 0e 03 00
LDN 0x01 (COM1)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1
val 01 02 f8 03 00 44
def 01 02 f8 03 00 04
LDN 0x03 (Parallel port)
idx 30 60 61 70 74 f0
val 01 03 78 07 04 00
def 01 03 78 07 03 42
LDN 0x04 (Hardware monitor)
idx 30 60 61 70
val 01 02 95 00
def 00 02 95 00
LDN 0x06 (GPIO)
idx 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f3 f4
val 00 00 00 60 00 00 00 00 00 00 9f 00 00 00 00
def 00 00 00 NA 00 00 00 00 00 00 00 00 NA 00 NA
LDN 0x0a (PME)
idx 30 f0 f1
val 01 00 07
def 00 00 00



From vladc6 at yahoo.com  Wed Nov  7 21:13:05 2007
From: vladc6 at yahoo.com (Vlad)
Date: Wed, 7 Nov 2007 12:13:05 -0800 (PST)
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 + VT8237R Chipset),
	PC2500E
Message-ID: <516173.21801.qm@web54403.mail.yahoo.com>

Hi,

Walmart has chosen to pre-install Linux on their least expensive
computer, the Everex TC2502 Green gPC w/ Via C7-D Processor [1], which
costs $199.

The fact that Walmart is intent on outdoing all of their competitors
by aggressively cutting costs wherever they can -- especially on this
model -- bodes well for LinuxBIOS. I'm sure Walmart would be ecstatic
to find out that they can save $15-$30 per board (7.5%-15% of the
total cost of the computer) by dropping the proprietary BIOS and using
the free/open-source LinuxBIOS.

Has anyone looked into supporting the motherboard that powers the
Everex TC2502 Green gPC? The makers of gOS [2] point to the
development kit motherboard with part number PC2500E, available from
ClubIT.com [3]. Is it already supported by the vt8237r and Via C7 code
checked into the LinuxBIOS SVN recently?

Also, has anyone tried contacting Walmart, Everex, and/or gOS people
about LinuxBIOS? They might not yet be aware of its cost-saving
advantages :)

Vlad

[1] http://www.walmart.com/catalog/product.do?product_id=7754614
[2] http://www.ThinkGOS.com
[3] http://www.clubit.com/product_detail.cfm?itemno=A4842001

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 



From svn at openbios.org  Wed Nov  7 21:32:58 2007
From: svn at openbios.org (LinuxBIOS)
Date: Wed, 07 Nov 2007 20:32:58 -0000
Subject: [LinuxBIOS] #80: serial console in grub2 works
In-Reply-To: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
References: <044.91a7bb7f03ea6b51b9f169cc4abb5027@openbios.org>
Message-ID: <053.6a6d69d1bf001c19c7a3a33705970323@openbios.org>

#80: serial console in grub2 works
----------------------------+-----------------------------------------------
    Reporter:  oxygene      |         Owner:  oxygene                
        Type:  enhancement  |        Status:  reopened               
    Priority:  major        |     Milestone:  Port GRUB2 to LinuxBIOS
   Component:  code         |       Version:  v3                     
  Resolution:               |      Keywords:                         
Dependencies:               |   Patchstatus:  patch needs review     
----------------------------+-----------------------------------------------
Comment (by rmh at aybabtu.com):

 I was assuming that LinuxBIOS table would export a port number rather than
 an IO address.  That sounds more portable to me.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/80#comment:6>
LinuxBIOS <http://www.linuxbios.org/>

From corey.osgood at gmail.com  Wed Nov  7 21:34:46 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 15:34:46 -0500
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 + VT8237R
 Chipset), PC2500E
In-Reply-To: <516173.21801.qm@web54403.mail.yahoo.com>
References: <516173.21801.qm@web54403.mail.yahoo.com>
Message-ID: <47322166.1070908@gmail.com>

And CN700 will be supported very soon, once I can free up a few more
registers. Only problem is, it only supports a single dimm for now. Wish
I could afford $60 to buy the board.

-Corey

Vlad wrote:
> Hi,
>
> Walmart has chosen to pre-install Linux on their least expensive
> computer, the Everex TC2502 Green gPC w/ Via C7-D Processor [1], which
> costs $199.
>
> The fact that Walmart is intent on outdoing all of their competitors
> by aggressively cutting costs wherever they can -- especially on this
> model -- bodes well for LinuxBIOS. I'm sure Walmart would be ecstatic
> to find out that they can save $15-$30 per board (7.5%-15% of the
> total cost of the computer) by dropping the proprietary BIOS and using
> the free/open-source LinuxBIOS.
>
> Has anyone looked into supporting the motherboard that powers the
> Everex TC2502 Green gPC? The makers of gOS [2] point to the
> development kit motherboard with part number PC2500E, available from
> ClubIT.com [3]. Is it already supported by the vt8237r and Via C7 code
> checked into the LinuxBIOS SVN recently?
>
> Also, has anyone tried contacting Walmart, Everex, and/or gOS people
> about LinuxBIOS? They might not yet be aware of its cost-saving
> advantages :)
>
> Vlad
>
> [1] http://www.walmart.com/catalog/product.do?product_id=7754614
> [2] http://www.ThinkGOS.com
> [3] http://www.clubit.com/product_detail.cfm?itemno=A4842001
>
> __________________________________________________
> Do You Yahoo!?
> Tired of spam?  Yahoo! Mail has the best spam protection around 
> http://mail.yahoo.com 
>   



From myles at pel.cs.byu.edu  Wed Nov  7 21:37:35 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 7 Nov 2007 13:37:35 -0700
Subject: [LinuxBIOS] ADLO and Kexec pathway questions
Message-ID: <012801c8217e$076a9300$2402a8c0@chimp>

I'm trying to use Linux-As-Bootloader for ADLO, so that I can let Linux
initialize the hardware.

 

I'm booting into Linux with Kexec, but Kexec complains that ADLO's memory
address 0x7c00 is not page aligned.  There's a comment in the Kexec code
that says that needs to be fixed, but hasn't been so far.

 

Is there another pathway that makes more sense?

 

Thanks,
Myles

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From r.marek at assembler.cz  Wed Nov  7 21:45:36 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 07 Nov 2007 21:45:36 +0100
Subject: [LinuxBIOS] [PATCH] More vt8237r fixes
In-Reply-To: <4731FAC7.6060301@gmail.com>
References: <4731FAC7.6060301@gmail.com>
Message-ID: <473223F0.6020709@assembler.cz>

Corey Osgood wrote:
> See patch. Rudolf, can you test this one to make sure it works correctly
> on your board?

Hi,

Your patch seems not so solve KBD and RTC correct? This could be implemented in 
superio on other board for example. Also the clock gating for Ethernet should be 
made programmable.

index = PCI_FUNC(dev->path.u.pci.devfn);

This is not very user friendly, index is quite confusing, in fact I was staring 
to the code quite long time to get how it works. Perhaps two variables would be 
more handy???

I would suggest some lookup table to make it more elegant???? Plus we will need 
at least for RTC and KBD some? variables, just like enable_internal_RTC....
or something shorter.

More over you cant enable just UHCI function 2 and not enable function zero and 
one. Plus you cant disable all UHCIs when EHCI is enabled. (you would violate 
PCI specs not having fn0)

The lookup table could be:

u8/u16 enable_bits[dev-15][fn=6] = { { 0xb , 0x0}, { c, d, a, 8, 9} ....

Or alternatively we could store the bitmask which would allow to enable usb fn0 
when someone wants fn1 for example...

The table would be 4*6*2 bytes so 48B, this is not so much contrary to the big 
if else if code...

Rudolf





From bari at onelabs.com  Wed Nov  7 22:00:49 2007
From: bari at onelabs.com (bari)
Date: Wed, 07 Nov 2007 15:00:49 -0600
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 + VT8237R
 Chipset), PC2500E
In-Reply-To: <516173.21801.qm@web54403.mail.yahoo.com>
References: <516173.21801.qm@web54403.mail.yahoo.com>
Message-ID: <47322781.9050402@onelabs.com>

Vlad wrote:

> The fact that Walmart is intent on outdoing all of their competitors
> by aggressively cutting costs wherever they can -- especially on this
> model -- bodes well for LinuxBIOS. I'm sure Walmart would be ecstatic
> to find out that they can save $15-$30 per board (7.5%-15% of the
> total cost of the computer) by dropping the proprietary BIOS and using
> the free/open-source LinuxBIOS.

I'm sure the BIOS vendor wished they were getting $15-$30 per license 
sticker/BIOS copy. They are in reality getting only <<$1 per copy of the 
closed source BIOS.

Every penny saved does count in high volume.

-Bari



From myles at pel.cs.byu.edu  Wed Nov  7 22:02:16 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 7 Nov 2007 14:02:16 -0700
Subject: [LinuxBIOS] [PATCH] many trivial patches
Message-ID: <2831fecf0711071302k2b18417fxbeccb0be4a92cfa0@mail.gmail.com>

This adds the same line (uses CONFIG_PRECOMPRESSED_PAYLOAD) to every
Options.lb file that already had a "uses
CONFIG_COMPRESSED_PAYLOAD_LZMA" line in it.

I figure that only adding it to the files that already have support
for LZMA payloads makes sure I don't break anything.

Myles

Signed-off-by: Myles Watson <myles at pel.cs.byu.edu>
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From corey.osgood at gmail.com  Wed Nov  7 22:04:31 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 16:04:31 -0500
Subject: [LinuxBIOS] [PATCH] More vt8237r fixes
In-Reply-To: <473223F0.6020709@assembler.cz>
References: <4731FAC7.6060301@gmail.com> <473223F0.6020709@assembler.cz>
Message-ID: <4732285F.8000906@gmail.com>

Rudolf Marek wrote:
> Corey Osgood wrote:
>> See patch. Rudolf, can you test this one to make sure it works correctly
>> on your board?
>
> Hi,
>
> Your patch seems not so solve KBD and RTC correct?

Correct, kbc/rtc init should handle things their own way. I thought
about doing that when we come to the lpc controller, but IIRC that's
already taken care of in vt8237r_lpc, so I figured I'd leave it alone.

> This could be implemented in superio on other board for example. Also
> the clock gating for Ethernet should be made programmable.

Yep, it should.

>
> index = PCI_FUNC(dev->path.u.pci.devfn);
>
> This is not very user friendly, index is quite confusing, in fact I
> was staring to the code quite long time to get how it works. Perhaps
> two variables would be more handy???
>
> I would suggest some lookup table to make it more elegant???? Plus we
> will need at least for RTC and KBD some? variables, just like
> enable_internal_RTC....
> or something shorter.

Uwe and I discussed this on IRC. I'm working on it (among other things) now.

>
> More over you cant enable just UHCI function 2 and not enable function
> zero and one. Plus you cant disable all UHCIs when EHCI is enabled.
> (you would violate PCI specs not having fn0)

Very good point! I'll keep it in mind. And you need at least one UHCI
controller for EHCI to work.

> The lookup table could be:
>
> u8/u16 enable_bits[dev-15][fn=6] = { { 0xb , 0x0}, { c, d, a, 8, 9} ....
>
> Or alternatively we could store the bitmask which would allow to
> enable usb fn0 when someone wants fn1 for example...
>
> The table would be 4*6*2 bytes so 48B, this is not so much contrary to
> the big if else if code...
>
> Rudolf

-Corey




From talbotx at comcast.net  Wed Nov  7 22:35:54 2007
From: talbotx at comcast.net (Adam Talbot)
Date: Wed, 07 Nov 2007 13:35:54 -0800
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 + VT8237R
 Chipset), PC2500E
In-Reply-To: <47322781.9050402@onelabs.com>
References: <516173.21801.qm@web54403.mail.yahoo.com>
	<47322781.9050402@onelabs.com>
Message-ID: <47322FBA.7090403@comcast.net>

I have two of these motherboard. 
Purchased under then name PCChips V21G V1.0C
Have been looking for some time to load linuxbios on them. All the
hardware information is below.  Any one playing around with these, be
careful, flashrom hangs on these boards, and I have had no luck at
tracking down the reason why.
Hope this helps
-Adam


v21g ~ # lspci -vvv
00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
Host Bridge
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR+
        Latency: 8
        Region 0: Memory at e8000000 (32-bit, prefetchable) [size=128M]
        Capabilities: [80] AGP version 3.5
                Status: RQ=8 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64-
HTrans- 64bit- FW- AGP3+ Rate=x4,x8
                Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW-
Rate=<none>
        Capabilities: [50] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:00.1 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
Host Bridge
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0             
                               
00:00.2 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
Host Bridge
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0             
                               
00:00.3 Host bridge: VIA Technologies, Inc. PT890 Host Bridge
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0             
                               
00:00.4 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
Host Bridge
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0

00:00.7 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
Host Bridge
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0

00:01.0 PCI bridge: VIA Technologies, Inc. VT8237 PCI Bridge (prog-if 00
[Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
        I/O behind bridge: 0000d000-0000dfff
        Memory behind bridge: fb000000-fcffffff
        Prefetchable memory behind bridge: f4000000-f7ffffff
        Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- <SERR+ <PERR+
        BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-
        Capabilities: [70] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0f.0 IDE interface: VIA Technologies, Inc. VIA VT6420 SATA RAID
Controller (rev 80) (prog-if 8f [Master SecP SecO PriP PriO])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin B routed to IRQ 11
        Region 0: I/O ports at ff00 [size=8]
        Region 1: I/O ports at fe00 [size=4]
        Region 2: I/O ports at fd00 [size=8]
        Region 3: I/O ports at fc00 [size=4]
        Region 4: I/O ports at fb00 [size=16]
        Region 5: I/O ports at f400 [size=256]
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0f.1 IDE interface: VIA Technologies, Inc.
VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06)
(prog-if 8a [Master SecP P    
riP])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Interrupt: pin A routed to IRQ 18
        Region 0: [virtual] Memory at 000001f0 (32-bit,
non-prefetchable) [size=8]
        Region 1: [virtual] Memory at 000003f0 (type 3,
non-prefetchable) [size=1]
        Region 2: [virtual] Memory at 00000170 (32-bit,
non-prefetchable) [size=8]
        Region 3: [virtual] Memory at 00000370 (type 3,
non-prefetchable) [size=1]
        Region 4: I/O ports at fa00 [size=16]
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81) (prog-if 00 [UHCI])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 64, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 19
        Region 4: I/O ports at f900 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81) (prog-if 00 [UHCI])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 64, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 19
        Region 4: I/O ports at f800 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81) (prog-if 00 [UHCI])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 64, Cache Line Size: 64 bytes
        Interrupt: pin B routed to IRQ 19
        Region 4: I/O ports at f700 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:10.3 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller (rev 81) (prog-if 00 [UHCI])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 64, Cache Line Size: 64 bytes
        Interrupt: pin B routed to IRQ 19
        Region 4: I/O ports at f600 [size=32]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86) (prog-if
20 [EHCI])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 64, Cache Line Size: 64 bytes
        Interrupt: pin C routed to IRQ 19
        Region 0: Memory at fdfff000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [80] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge
[KT600/K8T800/K8T890 South]
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping+ SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:11.5 Multimedia audio controller: VIA Technologies, Inc.
VT8233/A/8235/8237 AC97 Audio Controller (rev 60)
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Interrupt: pin C routed to IRQ 20
        Region 0: I/O ports at f200 [size=256]
        Capabilities: [c0] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II]
(rev 78)
        Subsystem: Elitegroup Computer Systems Unknown device 0102
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping+ SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 64 (750ns min, 2000ns max), Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 17
        Region 0: I/O ports at ee00 [size=256]
        Region 1: Memory at fdffe000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-

01:00.0 VGA compatible controller: VIA Technologies, Inc. UniChrome Pro
IGP (rev 01) (prog-if 00 [VGA])
        Subsystem: Elitegroup Computer Systems Unknown device aa51
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0 (500ns min)
        Interrupt: pin A routed to IRQ 16
        Region 0: Memory at f4000000 (32-bit, prefetchable) [size=64M]
        Region 1: Memory at fb000000 (32-bit, non-prefetchable) [size=16M]
        [virtual] Expansion ROM at fc000000 [disabled] [size=64K]
        Capabilities: [60] Power Management version 2
                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [70] AGP version 3.0
                Status: RQ=256 Iso- ArqSz=0 Cal=7 SBA+ ITACoh- GART64-
HTrans- 64bit- FW- AGP3+ Rate=x4,x8
                Command: RQ=1 ArqSz=0 Cal=0 SBA+ AGP- GART64- 64bit- FW-
Rate=<none>


bari wrote:
> Vlad wrote:
>
>   
>> The fact that Walmart is intent on outdoing all of their competitors
>> by aggressively cutting costs wherever they can -- especially on this
>> model -- bodes well for LinuxBIOS. I'm sure Walmart would be ecstatic
>> to find out that they can save $15-$30 per board (7.5%-15% of the
>> total cost of the computer) by dropping the proprietary BIOS and using
>> the free/open-source LinuxBIOS.
>>     
>
> I'm sure the BIOS vendor wished they were getting $15-$30 per license 
> sticker/BIOS copy. They are in reality getting only <<$1 per copy of the 
> closed source BIOS.
>
> Every penny saved does count in high volume.
>
> -Bari
>
>   




From corey.osgood at gmail.com  Wed Nov  7 22:35:30 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 16:35:30 -0500
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 + VT8237R
 Chipset), PC2500E
In-Reply-To: <516173.21801.qm@web54403.mail.yahoo.com>
References: <516173.21801.qm@web54403.mail.yahoo.com>
Message-ID: <47322FA2.8050303@gmail.com>

Vlad wrote:
> Has anyone looked into supporting the motherboard that powers the
> Everex TC2502 Green gPC? The makers of gOS [2] point to the
> development kit motherboard with part number PC2500E, available from
> ClubIT.com [3]. Is it already supported by the vt8237r and Via C7 code
> checked into the LinuxBIOS SVN recently?


I have emailed their development contact (about gettting one of these on
the cheap), hope to have a response soon. The biggest problems with the
port will lie in interrupt routing. Thanks for bringing this to our
attention, should make a nice slashdot article when it's done.

-Corey



From r.marek at assembler.cz  Wed Nov  7 22:36:26 2007
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 07 Nov 2007 22:36:26 +0100
Subject: [LinuxBIOS] [PATCH] More vt8237r fixes
In-Reply-To: <4732285F.8000906@gmail.com>
References: <4731FAC7.6060301@gmail.com> <473223F0.6020709@assembler.cz>
	<4732285F.8000906@gmail.com>
Message-ID: <47322FDA.5020808@assembler.cz>

> Very good point! I'll keep it in mind. And you need at least one UHCI
> controller for EHCI to work.

And if you have UHCI fn2 enabled you need to have fn0 and fn1 too... (check VIA 
docs)

Rudolf



From peter at stuge.se  Wed Nov  7 22:36:42 2007
From: peter at stuge.se (Peter Stuge)
Date: Wed, 7 Nov 2007 22:36:42 +0100
Subject: [LinuxBIOS] [PATCH] many trivial patches
In-Reply-To: <2831fecf0711071302k2b18417fxbeccb0be4a92cfa0@mail.gmail.com>
References: <2831fecf0711071302k2b18417fxbeccb0be4a92cfa0@mail.gmail.com>
Message-ID: <20071107213642.27851.qmail@stuge.se>

On Wed, Nov 07, 2007 at 02:02:16PM -0700, Myles Watson wrote:
> This adds the same line (uses CONFIG_PRECOMPRESSED_PAYLOAD) to every
> Options.lb file that already had a "uses
> CONFIG_COMPRESSED_PAYLOAD_LZMA" line in it.

If I understood correctly there should be a corresponding
default CONFIG_PRECOMPRESSED_PAYLOAD x

line in the target/ Options.lb files.


//Peter



From myles at pel.cs.byu.edu  Wed Nov  7 22:47:43 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Wed, 7 Nov 2007 14:47:43 -0700
Subject: [LinuxBIOS] [PATCH] many trivial patches
In-Reply-To: <20071107213642.27851.qmail@stuge.se>
References: <2831fecf0711071302k2b18417fxbeccb0be4a92cfa0@mail.gmail.com>
	<20071107213642.27851.qmail@stuge.se>
Message-ID: <014201c82187$d53ee6b0$2402a8c0@chimp>

> > This adds the same line (uses CONFIG_PRECOMPRESSED_PAYLOAD) to every
> > Options.lb file that already had a "uses
> > CONFIG_COMPRESSED_PAYLOAD_LZMA" line in it.
> 
> If I understood correctly there should be a corresponding
> default CONFIG_PRECOMPRESSED_PAYLOAD x
> 
> line in the target/ Options.lb files.

None of the architectures have a default CONFIG_PRECOMPRESSED_PAYLOAD.

Since "uses CONFIG_PRECOMPRESSED_PAYLOAD" allows you to use the option, but
doesn't force it, I don't think you need the default line.  It might be
better style. There are a lot of CONFIG_... options that don't have defaults
in the Options.lb files, though.

Myles




From bari at onelabs.com  Wed Nov  7 23:06:27 2007
From: bari at onelabs.com (bari)
Date: Wed, 07 Nov 2007 16:06:27 -0600
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 + VT8237R
 Chipset), PC2500E
In-Reply-To: <47322166.1070908@gmail.com>
References: <516173.21801.qm@web54403.mail.yahoo.com>
	<47322166.1070908@gmail.com>
Message-ID: <473236E3.7000603@onelabs.com>

Corey Osgood wrote:
> And CN700 will be supported very soon, once I can free up a few more
> registers. Only problem is, it only supports a single dimm for now. Wish
> I could afford $60 to buy the board.
> 

Another inexpensive option with higher performance are the SiS760GX 
mainboards. Now with new LinuxBIOS support!

Still no x11, dri, OpenGL drivers yet though (hint, hint SiS).

761GXM-M V1.0
http://www.ecsusa.com

SiS760GX maniboard + Sempron CPU for $50.
ECS GOAL3+ AMD Sempron 3000+ 754 SiS 761 GX Micro ATX Motherboard/CPU Combo
http://www.newegg.com/Product/Product.aspx?Item=N82E16813135060

only socket 754 but the AM2's versions are out soon.

-Bari





From svn at openbios.org  Wed Nov  7 23:09:03 2007
From: svn at openbios.org (svn at openbios.org)
Date: Wed,  7 Nov 2007 23:09:03 +0100
Subject: [LinuxBIOS] r2951 - trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx
Message-ID: <mailman.849.1355071198.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-11-07 23:09:02 +0100 (Wed, 07 Nov 2007)
New Revision: 2951

Modified:
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c
   trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
Log:
Add initial support for all known ICH* southbridges to the
i82801xx code for the following parts:

 - AC97 audio/modem
 - Onboard network interface cards (NICs)
 - USB 1.1 controllers
 - SMBus controllers

Some other parts are still missing and will be added later.

Use PCI ID #defines from pci_ids.h everywhere. Constify various structs.
Also, fix some random cosmetic issues in the code.

All of this is relatively trivial and tested by manually building
all boards which currently use the i82801xx code.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb	2007-11-07 22:09:02 UTC (rev 2951)
@@ -17,6 +17,7 @@
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
+
 driver i82801xx.o
 driver i82801xx_usb.o
 driver i82801xx_lpc.o

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -30,7 +30,7 @@
 	unsigned int index = 0;
 	uint16_t cur_disable_mask, new_disable_mask;
 
-	/* All 82801 devices should be on bus 0. */
+	/* All 82801xx devices should be on bus 0. */
 	unsigned int devfn = PCI_DEVFN(0x1f, 0);	// LPC
 	device_t lpc_dev = dev_find_slot(0, devfn);	// 0
 	if (!lpc_dev)
@@ -50,10 +50,11 @@
 	if (index == 0) {
 		index = 14;
 	}
+
 	cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
-	new_disable_mask = cur_disable_mask & ~(1 << index);	// enable it
+	new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */
 	if (!dev->enabled) {
-		new_disable_mask |= (1 << index); // disable it, if desired
+		new_disable_mask |= (1 << index); /* Disable it, if desired. */
 	}
 	if (new_disable_mask != cur_disable_mask) {
 		pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
@@ -61,6 +62,6 @@
 }
 
 struct chip_operations southbridge_intel_i82801xx_ops = {
-	CHIP_NAME("Intel i82801 Series Southbridge")
+	CHIP_NAME("Intel 82801 Series Southbridge")
 	.enable_dev = i82801xx_enable,
 };

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -19,13 +19,15 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+/* This code should work for all ICH* southbridges with AC97 audio/modem. */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include "i82801xx.h"
 
-static struct device_operations ac97_ops = {
+static const struct device_operations ac97_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -34,80 +36,109 @@
 	.enable			= i82801xx_enable,
 };
 
-/* 82801AA */
+/* 82801AA (ICH) */
 static const struct pci_driver i82801aa_ac97_audio __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2415,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO,
 };
 
 static const struct pci_driver i82801aa_ac97_modem __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2416,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM,
 };
 
-/* 82801AB */
+/* 82801AB (ICH0) */
 static const struct pci_driver i82801ab_ac97_audio __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2425,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO,
 };
 
 static const struct pci_driver i82801ab_ac97_modem __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2426,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM,
 };
 
-/* 82801BA */
+/* 82801BA/BAM (ICH2/ICH2-M) */
 static const struct pci_driver i82801ba_ac97_audio __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2445,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO,
 };
 
 static const struct pci_driver i82801ba_ac97_modem __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2446,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM,
 };
 
-/* 82801CA */
+/* 82801CA/CAM (ICH3-S/ICH3-M) */
 static const struct pci_driver i82801ca_ac97_audio __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2485,
+	.device	= PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO,
 };
 
 static const struct pci_driver i82801ca_ac97_modem __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2486,
+	.device	= PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM,
 };
 
-/* 82801DB & 82801DBM */
+/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
 static const struct pci_driver i82801db_ac97_audio __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24c5,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
 };
 
 static const struct pci_driver i82801db_ac97_modem __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24c6,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
 };
 
-/* 82801EB & 82801ER */
-static const struct pci_driver i82801ex_ac97_audio __pci_driver = {
+/* 82801EB/ER (ICH5/ICH5R) */
+static const struct pci_driver i82801eb_ac97_audio __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24d5,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_AC97_AUDIO,
 };
 
-static const struct pci_driver i82801ex_ac97_modem __pci_driver = {
+static const struct pci_driver i82801eb_ac97_modem __pci_driver = {
 	.ops	= &ac97_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24d6,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_AC97_MODEM,
 };
+
+/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
+static const struct pci_driver i82801fb_ac97_audio __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801fb_ac97_modem __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_AC97_MODEM,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+/* Note: 82801GU (ICH7-U) doesn't have AC97 audio/modem. */
+static const struct pci_driver i82801gb_ac97_audio __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801gb_ac97_modem __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_AC97_MODEM,
+};
+
+/* Note: There's no AC97 audio/modem on ICH8/ICH9/C-ICH. */

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -29,7 +29,7 @@
 	device_t dev;
 	uint16_t device_id;
 
-	/* Set the SMBus device staticly. */
+	/* Set the SMBus device statically. */
 	dev = PCI_DEV(0x0, 0x1f, 0x3);
 
 	/* Check to make sure we've got the right device. */

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -18,12 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+/* This code should work for all ICH* southbridges with a NIC. */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 
-static struct device_operations nic_ops = {
+static const struct device_operations nic_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -31,14 +33,68 @@
 	.scan_bus		= 0,
 };
 
-static const struct pci_driver i82801dbm_nic __pci_driver = {
+/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */
+
+/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */
+static const struct pci_driver i82801ba_nic __pci_driver = {
 	.ops	= &nic_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x103a,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_LAN,
 };
 
-static const struct pci_driver i82801ex_nic __pci_driver = {
+/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
+static const struct pci_driver i82801db_nic __pci_driver = {
 	.ops	= &nic_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x1051,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_LAN,
 };
+
+/* 82801EB/ER (ICH5/ICH5R) */
+static const struct pci_driver i82801eb_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_LAN,
+};
+
+/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
+static const struct pci_driver i82801fb_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_LAN,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+/* Note: 82801GU (ICH7-U) doesn't have a NIC. */
+static const struct pci_driver i82801gb_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_LAN,
+};
+
+/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */
+static const struct pci_driver i82801hb_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801HB_LAN,
+};
+
+/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */
+static const struct pci_driver i82801ib_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_LAN,
+};
+
+/* 82801E (C-ICH) */
+static const struct pci_driver i82801e_nic1 __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801E_LAN1,
+};
+
+static const struct pci_driver i82801e_nic2 __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801E_LAN2,
+};
+

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -23,7 +23,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <device/pci_ops.h>
 #include "i82801xx.h"
 
 /* TODO: Set dynamically, if the user only wants one SATA channel or none

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -18,16 +18,18 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+/* TODO: Check datasheets if this will work for all ICH* southbridges. */
+
+#include <stdint.h>
 #include <smbus.h>
 #include <pci.h>
 #include <arch/io.h>
-#include "i82801_model_specific.h"
 #include "i82801xx.h"
 #include "i82801_smbus.h"
 
-static int smbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
+static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
 {
-	unsigned device;
+	unsigned device;	/* TODO: u16? */
 	struct resource *res;
 
 	device = dev->path.u.i2c.device;
@@ -36,11 +38,11 @@
 	return do_smbus_read_byte(res->base, device, address);
 }
 
-static struct smbus_bus_operations lops_smbus_bus = {
+static const struct smbus_bus_operations lops_smbus_bus = {
 	.read_byte	= smbus_read_byte,
 };
 
-static struct device_operations smbus_ops = {
+static const struct device_operations smbus_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -50,44 +52,79 @@
 	.ops_smbus_bus		= &lops_smbus_bus,
 };
 
-/* 82801AA */
-static const struct pci_driver smbus_driver __pci_driver = {
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_smb __pci_driver = {
 	.ops	= &smbus_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2413,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_SMB,
 };
 
-/* 82801AB */
-static const struct pci_driver smbus_driver __pci_driver = {
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_smb __pci_driver = {
 	.ops	= &smbus_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2423,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_SMB,
 };
 
-/* 82801BA */
-static const struct pci_driver smbus_driver __pci_driver = {
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801ba_smb __pci_driver = {
 	.ops	= &smbus_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2443,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_SMB,
 };
 
-/* 82801CA */
-static const struct pci_driver smbus_driver __pci_driver = {
+/* 82801CA/CAM (ICH3-S/ICH3-M) */
+static const struct pci_driver i82801ca_smb __pci_driver = {
 	.ops	= &smbus_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2483,
+	.device	= PCI_DEVICE_ID_INTEL_82801CA_SMB,
 };
 
-/* 82801DB and 82801DBM */
-static const struct pci_driver smbus_driver __pci_driver = {
+/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
+static const struct pci_driver i82801db_smb __pci_driver = {
 	.ops	= &smbus_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24c3,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_SMB,
 };
 
-/* 82801EB and 82801ER */
-static const struct pci_driver smbus_driver __pci_driver = {
+/* 82801EB/ER (ICH5/ICH5R) */
+static const struct pci_driver i82801eb_smb __pci_driver = {
 	.ops	= &smbus_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24d3,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_SMB,
 };
+
+/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
+static const struct pci_driver i82801fb_smb __pci_driver = {
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_SMB,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_smb __pci_driver = {
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_SMB,
+};
+
+/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */
+static const struct pci_driver i82801hb_smb __pci_driver = {
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801HB_LAN,
+};
+
+/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */
+static const struct pci_driver i82801ib_smb __pci_driver = {
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_SMB,
+};
+
+/* 82801E (C-ICH) */
+static const struct pci_driver i82801e_smb __pci_driver = {
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801E_SMB,
+};

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -18,11 +18,12 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+/* This code should work for all ICH* southbridges with USB. */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <device/pci_ops.h>
 #include "i82801xx.h"
 
 static void usb_init(struct device *dev)
@@ -30,7 +31,7 @@
 	/* TODO: Any init needed? Some ports have it, others don't. */
 }
 
-static struct device_operations usb_ops = {
+static const struct device_operations usb_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -39,92 +40,217 @@
 	.enable			= i82801xx_enable,
 };
 
-/* 82801AA */
-static const struct pci_driver i82801aa_usb_1 __pci_driver = {
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_usb1 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2412,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_USB,
 };
 
-/* 82801AB */
-static const struct pci_driver i82801ab_usb_1 __pci_driver = {
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_usb1 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2422,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_USB,
 };
 
-/* 82801BA */
-static const struct pci_driver i82801ba_usb_1 __pci_driver = {
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801ba_usb1 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2442,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB1,
 };
 
-static const struct pci_driver i82801ba_usb_2 __pci_driver = {
+static const struct pci_driver i82801ba_usb2 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2444,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB2,
 };
 
-/* 82801CA */
-static const struct pci_driver i82801ca_usb_1 __pci_driver = {
+/* 82801CA/CAM (ICH3-S/ICH3-M) */
+static const struct pci_driver i82801ca_usb1 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2482,
+	.device	= PCI_DEVICE_ID_INTEL_82801CA_USB1,
 };
 
-static const struct pci_driver i82801ca_usb_2 __pci_driver = {
+static const struct pci_driver i82801ca_usb2 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2484,
+	.device	= PCI_DEVICE_ID_INTEL_82801CA_USB2,
 };
 
-static const struct pci_driver i82801ca_usb_3 __pci_driver = {
+static const struct pci_driver i82801ca_usb3 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2487,
+	.device	= PCI_DEVICE_ID_INTEL_82801CA_USB3,
 };
 
-/* 82801DB and 82801DBM */
-static const struct pci_driver i82801db_usb_1 __pci_driver = {
+/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
+static const struct pci_driver i82801db_usb1 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24c2,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_USB1,
 };
 
-static const struct pci_driver i82801db_usb_2 __pci_driver = {
+static const struct pci_driver i82801db_usb2 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24c4,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_USB2,
 };
 
-static const struct pci_driver i82801db_usb_3 __pci_driver = {
+static const struct pci_driver i82801db_usb3 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24c7,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_USB3,
 };
 
-/* 82801EB and 82801ER */
-static const struct pci_driver i82801ex_usb_1 __pci_driver = {
+/* 82801EB/ER (ICH5/ICH5R) */
+static const struct pci_driver i82801eb_usb1 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24d2,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB1,
 };
 
-static const struct pci_driver i82801ex_usb_2 __pci_driver = {
+static const struct pci_driver i82801eb_usb2 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24d4,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB2,
 };
 
-static const struct pci_driver i82801ex_usb_3 __pci_driver = {
+static const struct pci_driver i82801eb_usb3 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24d7,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB3,
 };
 
-static const struct pci_driver i82801ex_usb_4 __pci_driver = {
+static const struct pci_driver i82801eb_usb4 __pci_driver = {
 	.ops	= &usb_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x24de,
+	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB4,
 };
+
+/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
+static const struct pci_driver i82801fb_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB1,
+};
+
+static const struct pci_driver i82801fb_usb2 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB2,
+};
+
+static const struct pci_driver i82801fb_usb3 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB3,
+};
+
+static const struct pci_driver i82801fb_usb4 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB4,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB1,
+};
+
+static const struct pci_driver i82801gb_usb2 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB2,
+};
+
+static const struct pci_driver i82801gb_usb3 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB3,
+};
+
+static const struct pci_driver i82801gb_usb4 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB4,
+};
+
+/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */
+static const struct pci_driver i82801hb_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB1,
+};
+
+static const struct pci_driver i82801hb_usb2 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB2,
+};
+
+static const struct pci_driver i82801hb_usb3 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB3,
+};
+
+static const struct pci_driver i82801hb_usb4 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB4,
+};
+
+static const struct pci_driver i82801hb_usb5 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB5,
+};
+
+/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */
+static const struct pci_driver i82801ib_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB1,
+};
+
+static const struct pci_driver i82801ib_usb2 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB2,
+};
+
+static const struct pci_driver i82801ib_usb3 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB3,
+};
+
+static const struct pci_driver i82801ib_usb4 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB4,
+};
+
+static const struct pci_driver i82801ib_usb5 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB5,
+};
+
+static const struct pci_driver i82801ib_usb6 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB6,
+};
+
+/* 82801E (C-ICH) */
+static const struct pci_driver i82801e_usb __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801E_USB,
+};

Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
===================================================================
--- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c	2007-11-07 19:07:17 UTC (rev 2950)
+++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c	2007-11-07 22:09:02 UTC (rev 2951)
@@ -23,7 +23,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <device/pci_ops.h>
 #include "i82801xx.h"
 
 static void usb_ehci_init(struct device *dev)




From uwe at hermann-uwe.de  Wed Nov  7 23:21:26 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 7 Nov 2007 23:21:26 +0100
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 +
	VT8237R	Chipset), PC2500E
In-Reply-To: <473236E3.7000603@onelabs.com>
References: <516173.21801.qm@web54403.mail.yahoo.com>
	<47322166.1070908@gmail.com> <473236E3.7000603@onelabs.com>
Message-ID: <20071107222126.GB15728@greenwood>

On Wed, Nov 07, 2007 at 04:06:27PM -0600, bari wrote:
> 761GXM-M V1.0
> http://www.ecsusa.com

Yep.


> ECS GOAL3+ AMD Sempron 3000+ 754 SiS 761 GX Micro ATX Motherboard/CPU Combo
> http://www.newegg.com/Product/Product.aspx?Item=N82E16813135060

This uses SiS 965L, which may or may not be supported by the SiS 966(L)
code in svn.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Wed Nov  7 23:23:07 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 7 Nov 2007 23:23:07 +0100
Subject: [LinuxBIOS] Superiotool output on fintek f71805f
In-Reply-To: <47320E42.2060400@gmail.com>
References: <47320E42.2060400@gmail.com>
Message-ID: <20071107222307.GC15728@greenwood>

On Wed, Nov 07, 2007 at 02:13:06PM -0500, Corey Osgood wrote:
> carpc:~/superiotool# superiotool -d
> superiotool r2922
> Found Fintek F71805F/FG (vid=0x3419, id=0x0604) at 0x4e
> Register dump:
> idx 07 20 21 23 24 25 26 27 28 29
> val 03 04 06 19 34 00 03 20 08 00
> def NA 04 06 19 34 00 00 3f 08 00
> LDN 0x00 (Floppy)
> idx 30 60 61 70 74 f0 f2 f4
> val 01 03 f2 06 02 0e ff 00
> def 01 03 f0 06 02 0e 03 00
> LDN 0x01 (COM1)
> idx 30 60 61 70 f0
> val 01 03 f8 04 00
> def 01 03 f8 04 00
> LDN 0x02 (COM2)
> idx 30 60 61 70 f0 f1
> val 01 02 f8 03 00 44
> def 01 02 f8 03 00 04
> LDN 0x03 (Parallel port)
> idx 30 60 61 70 74 f0
> val 01 03 78 07 04 00
> def 01 03 78 07 03 42
> LDN 0x04 (Hardware monitor)
> idx 30 60 61 70
> val 01 02 95 00
> def 00 02 95 00
> LDN 0x06 (GPIO)
> idx 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f3 f4
> val 00 00 00 60 00 00 00 00 00 00 9f 00 00 00 00
> def 00 00 00 NA 00 00 00 00 00 00 00 00 NA 00 NA
> LDN 0x0a (PME)
> idx 30 f0 f1
> val 01 00 07
> def 00 00 00

Thanks, added to the wiki.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at openbios.org  Wed Nov  7 23:26:35 2007
From: svn at openbios.org (LinuxBIOS)
Date: Wed, 07 Nov 2007 22:26:35 -0000
Subject: [LinuxBIOS] #6: Add support for 10 cheap,
 mainstream motherboards
In-Reply-To: <040.54c1a3f7da015b6b821a7551cbbb5e54@openbios.org>
References: <040.54c1a3f7da015b6b821a7551cbbb5e54@openbios.org>
Message-ID: <049.2162a57a0cb082ac6158e3bdd15555b7@openbios.org>

#6: Add support for 10 cheap, mainstream motherboards
----------------------+-----------------------------------------------------
    Reporter:  uwe    |         Owner:  somebody         
        Type:  task   |        Status:  closed           
    Priority:  major  |     Milestone:  Going mainstream 
   Component:  code   |       Version:  v2               
  Resolution:  fixed  |      Keywords:                   
Dependencies:         |   Patchstatus:  there is no patch
----------------------+-----------------------------------------------------
Changes (by uwe):

  * status:  new => closed
  * resolution:  => fixed

Comment:

 This issue can be closed, we easily support more than 10 desktop-style
 motherboards in v2 now.

 This does not mean we'll stop adding more boards, of course.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/6#comment:7>
LinuxBIOS <http://www.linuxbios.org/>

From zigamlinar at gmail.com  Wed Nov  7 23:29:10 2007
From: zigamlinar at gmail.com (Ziga Mlinar)
Date: Wed, 7 Nov 2007 23:29:10 +0100
Subject: [LinuxBIOS] [PATCH] v2: AZZA PT-6IBD support
In-Reply-To: <200710311757.10111.zigamlinar@gmail.com>
References: <20071025192517.GF28802@greenwood>
	<20071025193502.GK28802@greenwood>
	<200710311757.10111.zigamlinar@gmail.com>
Message-ID: <6a60142f0711071429u7721d6c1l9b035173d6710117@mail.gmail.com>

On 10/31/07, ?iga Mlinar <zigamlinar at gmail.com> wrote:
>
> Working things:
> - 3dfx voodoo3 VGA board
> - old IDE harddrive
> - RTL-8169 Gigabit Ethernet
>
> I'll check other things, too, as they come.


Parallel port is also recognized by kernel, and a device node is created. I
didn't use it yet, though

 # dmesg | grep par
parport0: PC-style at 0x378 (0x778) [PCSPP(,...)]
parport0: irq 7 detected

?iga Mlinar
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From svn at openbios.org  Thu Nov  8 00:13:43 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  8 Nov 2007 00:13:43 +0100
Subject: [LinuxBIOS] r2952 - in trunk/LinuxBIOSv2:
	src/mainboard/pcengines/alix1c src/northbridge/amd/lx
	targets/pcengines/alix1c
Message-ID: <mailman.850.1355071198.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2007-11-08 00:13:43 +0100 (Thu, 08 Nov 2007)
New Revision: 2952

Modified:
   trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
   trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c
   trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c
   trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb
Log:
Final set of changes to make Alix1c work.

Fix IRQ tables (Thanks to Marc Jones)

Fix IRQ SLOT #

Comment out ram test in early startup. 

make the debug print in lx/raminit.c a debug print, not emerg print

Set the default console log level to 3, but leave in the possibility of 
running with more info (leave maximum at 11)

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Marc Jones <marc.jones at amd.com>


Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb	2007-11-07 22:09:02 UTC (rev 2951)
+++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb	2007-11-07 23:13:43 UTC (rev 2952)
@@ -103,7 +103,7 @@
 ## Build code to export a programmable irq routing table
 ##
 default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default IRQ_SLOT_COUNT=5
 #object irq_tables.o
 
 ##

Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	2007-11-07 22:09:02 UTC (rev 2951)
+++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	2007-11-07 23:13:43 UTC (rev 2952)
@@ -169,7 +169,8 @@
 	sdram_initialize(1, memctrl);
 
 	/* Check memory */
-	ram_check(0x00000000, 640 * 1024);
+	/* enable this only if you are having questions */
+	/* ram_check(0x00000000, 640 * 1024);*/
 
 	/* Switch from Cache as RAM to real RAM 
 	 * There are two ways we could think about this.  

Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c	2007-11-07 22:09:02 UTC (rev 2951)
+++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c	2007-11-07 23:13:43 UTC (rev 2952)
@@ -1,21 +1,21 @@
 /*
- * This file is part of the LinuxBIOS project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
 
 #include <arch/pirq_routing.h>
 #include <console/console.h>
@@ -25,83 +25,120 @@
 
 /* Platform IRQs */
 #define PIRQA 11
-#define PIRQB 5
-#define PIRQC 10
-#define PIRQD 10
+#define PIRQB 10
+#define PIRQC 11
+#define PIRQD 9
 
 /* Map */
-#define M_PIRQA (1 << PIRQA)  /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB)  /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC)  /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD)  /* Bitmap of supported IRQs */
+#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
 
 /* Link */
-#define L_PIRQA  1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB  2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC  3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD  4 /* Means Slot INTx# Connects To Chipset INTD# */
+#define L_PIRQA 1		/* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2		/* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3		/* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4		/* Means Slot INTx# Connects To Chipset INTD# */
 
+/* ALIX 1c interrupt wiring. Devices are:
+ * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
+ * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
+ * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
+ * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
+ * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
+ * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
+ * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
+ * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
+ * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
+ * The only devices that interrupt are:
+ * What         device  IRQ     PIN     PIN WIRED TO
+ * AES          00:01.2 0a      01      A       A
+ * 3VPCI        00:0c.0 0a      01      A       A
+ * eth0 	00:0d.0 0b      01      A       B
+ * mpci 	00:0e.0 0a      01      A       A
+ * usb          00:0f.3 0b      02      B       B
+ * usb          00:0f.4 0b      04      D       D
+ * usb          00:0f.5 0b      04      D       D
+ *
+ * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B
+*/
 const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	 /* There can be total IRQ_SLOT_COUNT devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x0f<<3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x100b,		 /* Vendor */
-	0x2b,		 /* Device */
-	0,		 /* Crap (miniport) */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xe,		 /* u8 checksum. This has to be set to some
-			    value that would give 0 after the sum of all
-			    bytes for this structure (including checksum) */
-	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
-		{0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
-		{0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
-		{0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
-		{0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
+PIRQ_SIGNATURE,		/* u32 signature */
+PIRQ_VERSION,		/* u16 version   */
+32 + 16 * IRQ_SLOT_COUNT,
+0x00,			/* Where the interrupt router lies (bus) */
+(0x0F << 3) | 0x0,      /* Where the interrupt router lies (dev) */
+0x00,			/* IRQs devoted exclusively to PCI usage */
+0x100B,			/* Vendor */
+0x002B,			/* Device */
+0,			/* Crap (miniport) */
+{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
+0x00,			/* u8 checksum , this has to set to 
+			 * some value that would give 0 
+			 * after the sum of all bytes 
+			 * for this structure 
+			 * (including checksum) 
+			 */
+{
+	/* If you change the number of entries, 
+	 * change the IRQ_SLOT_COUNT above! 
+	 */
+	/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
+	{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+		/* PCI SLOT */
+		{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},	/* slot1 */
+		/* ONBOARD ETHER */
+		{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
+		/* MINI PCI */
+		{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},	/* mini slot2 */
+		/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D */
+		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	}
 };
 
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	int i, j, k, num_entries;
+	unsigned char pirq[4];
+	uint16_t chipset_irq_map;
+	uint32_t pciAddr, pirtable_end;
+	struct irq_routing_table *pirq_tbl;
 
-unsigned long write_pirq_routing_table(unsigned long addr){
-       int i, j, k, num_entries;
-       unsigned int pirq[4];
-       uint16_t chipset_irq_map;
-       uint32_t pciAddr, pirtable_end;
-       struct irq_routing_table *pirq_tbl;
+	pirtable_end = copy_pirq_routing_table(addr);
 
-       pirtable_end = copy_pirq_routing_table(addr);
+	/* Set up chipset IRQ steering. */
+	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
+	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
+		     chipset_irq_map);
+	outl(pciAddr & ~3, 0xCF8);
+	outl(chipset_irq_map, 0xCFC);
 
-       /* Set up chipset IRQ steering */
-       pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-       chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10);
-       printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
-       outl(pciAddr & ~3, 0xCF8);
-       outl(chipset_irq_map, 0xCFC);
+	pirq_tbl = (struct irq_routing_table *) (addr);
+	num_entries = (pirq_tbl->size - 32) / 16;
 
-       pirq_tbl = (struct irq_routing_table *)(addr);
-       num_entries = (pirq_tbl->size - 32)/16;
+	/* Set PCI IRQs. */
+	for (i = 0; i < num_entries; i++) {
+		printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
+			     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
+		for (j = 0; j < 4; j++) {
+			printk_debug("INT: %c bitmap: %x ", 'A' + j,
+				     pirq_tbl->slots[i].irq[j].bitmap);
+			/* Finds lsb in bitmap to IRQ#. */
+			for (k = 0; 
+			     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) 
+				     && (pirq_tbl->slots[i].irq[j].bitmap != 0);
+			     k++);
+			pirq[j] = k;
+			printk_debug("PIRQ: %d\n", k);
+		}
 
-       /* Set PCI IRQs */
-       for (i=0; i < num_entries; i++){
-               printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
-               for (j = 0; j < 4; j++){
-               printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
-                       for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
-                       pirq[j] = k;
-                       printk_debug("PIRQ: %d\n", k);
-               }
-               pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq);        /* bus, device, slots IRQs for {A,B,C,D} */
-       }
+		/* Bus, device, slots IRQs for {A,B,C,D}. */
+		pci_assign_irqs(pirq_tbl->slots[i].bus,
+				pirq_tbl->slots[i].devfn >> 3, pirq);
+	}
 
-       /* put the PIR table in memory and checksum */
-       return pirtable_end;
+	/* Put the PIR table in memory and checksum. */
+	return pirtable_end;
 }
-

Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c
===================================================================
--- trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c	2007-11-07 22:09:02 UTC (rev 2951)
+++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c	2007-11-07 23:13:43 UTC (rev 2952)
@@ -29,9 +29,9 @@
 
 void banner(char *s)
 {
-	print_emerg("===========================");
-	print_emerg(s);
-	print_emerg("======================================\r\n");
+	print_debug("===========================");
+	print_debug(s);
+	print_debug("======================================\r\n");
 }
 void hcf(void)
 {

Modified: trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb	2007-11-07 22:09:02 UTC (rev 2951)
+++ trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb	2007-11-07 23:13:43 UTC (rev 2952)
@@ -15,7 +15,7 @@
 
 option FALLBACK_SIZE = ROM_SIZE
 
-option DEFAULT_CONSOLE_LOGLEVEL = 11
+option DEFAULT_CONSOLE_LOGLEVEL = 3
 option MAXIMUM_CONSOLE_LOGLEVEL = 11
 romimage "fallback" 
 	option USE_FALLBACK_IMAGE=1




From svn at openbios.org  Thu Nov  8 00:28:47 2007
From: svn at openbios.org (LinuxBIOS)
Date: Wed, 07 Nov 2007 23:28:47 -0000
Subject: [LinuxBIOS] #87: flashrom issues on m57sli-s4
In-Reply-To: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>
References: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>
Message-ID: <050.577d791642e16015d96f24bbbe1da038@openbios.org>

#87: flashrom issues on m57sli-s4
-------------------------+--------------------------------------------------
    Reporter:  ward      |         Owner:  somebody         
        Type:  defect    |        Status:  new              
    Priority:  major     |     Milestone:                   
   Component:  flashrom  |       Version:  v2               
  Resolution:            |      Keywords:                   
Dependencies:            |   Patchstatus:  there is no patch
-------------------------+--------------------------------------------------
Comment (by hailfinger):

 For timing tests of flash readout, make sure CPU frequency scaling and
 power management are disabled. Then run

 time flashrom -V --read test.rom; md5sum test.rom

 on an idle system a few times in a row. If the "delay loops per second"
 value varies a lot, either the system is under load or CPU frequency
 scaling is active. If the md5sum is not constant, something fishy is going
 on.

 The real/user/sys time needed for the command is what I'm interested in.
 The delay loop value is useless for LPC bus frequency measurement.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:3>
LinuxBIOS <http://www.linuxbios.org/>

From corey.osgood at gmail.com  Thu Nov  8 02:45:39 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 20:45:39 -0500
Subject: [LinuxBIOS] [PATCH] More vt8237r fixes (new patch)
In-Reply-To: <47322FDA.5020808@assembler.cz>
References: <4731FAC7.6060301@gmail.com> <473223F0.6020709@assembler.cz>
	<4732285F.8000906@gmail.com> <47322FDA.5020808@assembler.cz>
Message-ID: <47326A43.1050508@gmail.com>

Updated patch attached, thanks for the suggestions. I think I've done
this right, can you have a look at it/test it? I can't test on hardware
ATM because of some work I'm doing on ram init.

Rudolf Marek wrote:
>> Very good point! I'll keep it in mind. And you need at least one UHCI
>> controller for EHCI to work.
>
> And if you have UHCI fn2 enabled you need to have fn0 and fn1 too...
> (check VIA docs)
>
> Rudolf
>
I'm not seeing that anywhere, is it in the porting guide? All I have is
the datasheet.

Thanks,
Corey
-------------- next part --------------
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From corey.osgood at gmail.com  Thu Nov  8 03:22:15 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 07 Nov 2007 21:22:15 -0500
Subject: [LinuxBIOS] [PATCH] More vt8237r fixes (new patch)
In-Reply-To: <47326A43.1050508@gmail.com>
References: <4731FAC7.6060301@gmail.com> <473223F0.6020709@assembler.cz>
	<4732285F.8000906@gmail.com> <47322FDA.5020808@assembler.cz>
	<47326A43.1050508@gmail.com>
Message-ID: <473272D7.5040008@gmail.com>

Corey Osgood wrote:
> Updated patch attached, thanks for the suggestions. I think I've done
> this right, can you have a look at it/test it? I can't test on hardware
> ATM because of some work I'm doing on ram init.
>   
Oops, little mistake. This line:

> +	if (disable_bit == 0x4) enabled = 0;

should have been

+	if (disable_bit == 0x4) enabled = !enabled;


-Corey




From svn at openbios.org  Thu Nov  8 03:28:43 2007
From: svn at openbios.org (svn at openbios.org)
Date: Thu,  8 Nov 2007 03:28:43 +0100
Subject: [LinuxBIOS] r2953 - in trunk/LinuxBIOSv2: src/mainboard/msi/ms6178
	targets/msi/ms6178
Message-ID: <mailman.851.1355071198.16123.coreboot@coreboot.org>

Author: uwe
Date: 2007-11-08 03:28:43 +0100 (Thu, 08 Nov 2007)
New Revision: 2953

Added:
   trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/irq_tables.c
Modified:
   trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Config.lb
   trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Options.lb
   trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/chip.h
   trunk/LinuxBIOSv2/targets/msi/ms6178/Config.lb
Log:
Fix up totally broken Super I/O config on the MS-6178. Add
PIRQ table to make most devices work. Random small fixes (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Config.lb	2007-11-07 23:13:43 UTC (rev 2952)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Config.lb	2007-11-08 02:28:43 UTC (rev 2953)
@@ -28,7 +28,7 @@
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 65536
+default XIP_ROM_SIZE = 64 * 1024
 default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
 arch i386 end
 driver mainboard.o
@@ -78,6 +78,11 @@
 config chip.h
 
 chip northbridge/intel/i82810			# Northbridge
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/intel/socket_PGA370		# CPU
+      device apic 0 on end			# APIC
+    end
+  end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
     device pci 1.0 off				# Onboard video
@@ -87,47 +92,54 @@
       # end
     end
     chip southbridge/intel/i82801xx		# Southbridge
-      device pci 1e.0 on			# PCI bridge
-        # chip drivers/pci/onboard
-        #   device pci 1.0 on end
-        #   register "rom_address" = "0xfff80000"
-        # end
-      end
-      device pci 1f.0 on			# ISA bridge
-        chip superio/winbond/w83627hf
-          device pnp 2e.8 on			# Floppy
-            # io 0x60 = 0x3f0
-            io 0x60 = 0x3f2
+      device pci 1e.0 on end			# PCI bridge
+      device pci 1f.0 on			# ISA/LPC bridge
+        chip superio/winbond/w83627hf		# Super I/O
+          device pnp 2e.0 on			# Floppy
+            io 0x60 = 0x3f0
             irq 0x70 = 6
             drq 0x74 = 2
           end
-          device pnp 2e.9 on			# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.a on			# Parallel port
+          device pnp 2e.1 on			# Parallel port
             io 0x60 = 0x378
             irq 0x70 = 7
             drq 0x74 = 3
           end
-          device pnp 2e.b on			# PS/2 keyboard/mouse
+          device pnp 2e.2 on			# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 on			# Com2 (only header on board)
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.5 on			# PS/2 keyboard/mouse
             io 0x60 = 0x60
             io 0x62 = 0x64
             irq 0x70 = 1			# Keyboard interrupt
             irq 0x72 = 12			# Mouse interrupt
           end
-          device pnp 2e.c on end		# Game port
-          device pnp 2e.d on end		# MIDI / MPU401
+          device pnp 2e.6 on end		# Consumer IR (TODO)
+          device pnp 2e.7 on			# Game port / MIDI / GPIO 1
+            io 0x60 = 0x201
+            io 0x62 = 0x330
+            irq 0x70 = 9
+          end
+          device pnp 2e.8 on end		# GPIO 2
+          device pnp 2e.9 on end		# GPIO 3
+          device pnp 2e.a on end		# ACPI
+          device pnp 2e.b on			# Hardware monitor
+            io 0x60 = 0x290
+            irq 0x70 = 5
+          end
         end
       end
       device pci 1f.1 on end			# IDE
       device pci 1f.2 on end			# USB
       device pci 1f.3 on end			# SMBus
       device pci 1f.5 on end			# AC'97 audio
-      device pci 1f.6 off end			# AC'97 modem
+      device pci 1f.6 on end			# AC'97 modem
     end
   end
-  chip cpu/intel/socket_PGA370			# CPU
-  end
 end
 

Modified: trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Options.lb
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Options.lb	2007-11-07 23:13:43 UTC (rev 2952)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/Options.lb	2007-11-08 02:28:43 UTC (rev 2953)
@@ -67,15 +67,17 @@
 default HAVE_FALLBACK_BOOT = 1
 default HAVE_MP_TABLE = 0
 default HAVE_HARD_RESET = 0
-default HAVE_PIRQ_TABLE = 0	# FIXME
-default IRQ_SLOT_COUNT = 4	# FIXME
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 16 * 1024
 default HAVE_OPTION_TABLE = 0
 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 default USE_OPTION_TABLE = 0
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 0x2000
-default HEAP_SIZE = 0x4000
 default _RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
 default CROSS_COMPILE = ""
@@ -84,7 +86,7 @@
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default TTYS0_BAUD = 115200
 default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3
+default TTYS0_LCS = 0x3			# 8n1
 default DEFAULT_CONSOLE_LOGLEVEL = 9
 default MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_UDELAY_TSC = 1
@@ -93,4 +95,3 @@
 default CONFIG_PCI_ROM_RUN = 1
 
 end
-

Modified: trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/chip.h
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/chip.h	2007-11-07 23:13:43 UTC (rev 2952)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/chip.h	2007-11-08 02:28:43 UTC (rev 2953)
@@ -21,5 +21,4 @@
 extern struct chip_operations mainboard_msi_ms6178_ops;
 
 struct mainboard_msi_ms6178_config {
-	int nothing;
 };

Added: trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/irq_tables.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/irq_tables.c	                        (rev 0)
+++ trunk/LinuxBIOSv2/src/mainboard/msi/ms6178/irq_tables.c	2007-11-08 02:28:43 UTC (rev 2953)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router device */
+	0x1c00,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x7000,			/* Device */
+	0,			/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x1a,			/* Checksum */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x1e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
+		{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+		{0x00,(0x1f<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

Modified: trunk/LinuxBIOSv2/targets/msi/ms6178/Config.lb
===================================================================
--- trunk/LinuxBIOSv2/targets/msi/ms6178/Config.lb	2007-11-07 23:13:43 UTC (rev 2952)
+++ trunk/LinuxBIOSv2/targets/msi/ms6178/Config.lb	2007-11-08 02:28:43 UTC (rev 2953)
@@ -24,6 +24,17 @@
 option ROM_SIZE = 512 * 1024
 # option ROM_SIZE = (512 * 1024) - (32 * 1024)
 
+option MAINBOARD_VENDOR = "MSI"
+option MAINBOARD_PART_NUMBER = "MS-6178"
+
+option IRQ_SLOT_COUNT = 4
+
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+option CONFIG_CONSOLE_VGA = 1
+option CONFIG_PCI_ROM_RUN = 1
+
 romimage "normal"
 	option USE_FALLBACK_IMAGE = 0
 	option LINUXBIOS_EXTRA_VERSION = ".0Normal"




From my_tsai at sis.com  Thu Nov  8 03:52:19 2007
From: my_tsai at sis.com (Morgan Tsai /SiS)
Date: Thu, 8 Nov 2007 10:52:19 +0800
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 +
	VT8237RChipset), PC2500E
References: <516173.21801.qm@web54403.mail.yahoo.com>
	<47322166.1070908@gmail.com> <473236E3.7000603@onelabs.com>
	<20071107222126.GB15728@greenwood>
Message-ID: <000601c821b2$6241e4c0$0200a8c0@sis.com.tw>

SiS965(L) vs 966(L)

Identical device ID: LAN, USB
Different device ID: SATA, Audio(966 has HD Audio, but still reserved AC97)

Although they are funtionally alike, such like register map.
There is somewhare different value to be filled for bug fix.

For SATA, their IDs are 0x0182, 0x0184, 0x1183, 0x1184, 0x1185, 
0x1186...etc,..
It has long long story, sorry I'm not familiar with SATA device.


Morgan

----- Original Message ----- 
From: "Uwe Hermann" <uwe at hermann-uwe.de>
To: "bari" <bari at onelabs.com>
Cc: "Corey Osgood" <corey.osgood at gmail.com>; <linuxbios at linuxbios.org>; 
"Morgan Tsai" <my_tsai at sis.com>
Sent: Thursday, November 08, 2007 6:21 AM
Subject: Re: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 + 
VT8237RChipset), PC2500E

On Wed, Nov 07, 2007 at 04:06:27PM -0600, bari wrote:
> 761GXM-M V1.0
> http://www.ecsusa.com

Yep.


> ECS GOAL3+ AMD Sempron 3000+ 754 SiS 761 GX Micro ATX Motherboard/CPU 
> Combo
> http://www.newegg.com/Product/Product.aspx?Item=N82E16813135060

This uses SiS 965L, which may or may not be supported by the SiS 966(L)
code in svn.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org




From hansolofalcon at worldnet.att.net  Thu Nov  8 06:31:51 2007
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Thu, 8 Nov 2007 00:31:51 -0500
Subject: [LinuxBIOS] Booting from USB
Message-ID: <004401c821c8$ac1719b0$6401a8c0@who8>

Hello!
I have a project taking shape that would eventually have a system booting a
file-system from USB.

I remember that we had a method of doing something of a sort from USB, using
the contents of the v1 release. To be honest I am not even sure I remember
the details behind it, or the individual who was the developer behind it,
just that it was possible. Up to a point of course.

Now the project, essentially it would be an EPIA type board with a USB
device a file-system, when booted we'd have a Linux prompt and all of the
usual features thusly. The networking card would be a commodity wireless
one. 

The problem is that of selecting the board, and then configuring it to do
that. I would like recommendations. The problem is of course money I would
like it to be under 100 dollars US for the board. Preferably below 60
dollars US for it.

Currently the file-system I've chosen is that of RUNT Linux, the fact that
is a UMSDOS based arrangement built using Slackware Linux is that of the
reason.

And naturally when the thing came up and started the classic doing something
specific phase, that's where I'd be ending up with designing a gizmo to do
most of that. And coding the programs behind it. 
--
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you always." Obi-Wan Kenobi
? 






From rminnich at gmail.com  Thu Nov  8 06:34:37 2007
From: rminnich at gmail.com (ron minnich)
Date: Wed, 7 Nov 2007 21:34:37 -0800
Subject: [LinuxBIOS] Booting from USB
In-Reply-To: <004401c821c8$ac1719b0$6401a8c0@who8>
References: <004401c821c8$ac1719b0$6401a8c0@who8>
Message-ID: <13426df10711072134t6935279ft4cd43b34f719186@mail.gmail.com>

on your costs, are you considering all the costs? The Thincan or the
alix1c are more like $140 or so, but they run off 1 power supply and
don't require the messy PC power supply and case. Does  your
application require standard PC attributes? What's the end
environment?

ron



From hansolofalcon at worldnet.att.net  Thu Nov  8 06:48:11 2007
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Thu, 8 Nov 2007 00:48:11 -0500
Subject: [LinuxBIOS] Booting from USB
In-Reply-To: <13426df10711072134t6935279ft4cd43b34f719186@mail.gmail.com>
Message-ID: <004601c821ca$f314dbc0$6401a8c0@who8>

Hello!
I will be pleased to answer your questions Ron, but in reverse order.

My end environment has not been decided. It will probably something working
in a normal room one. (If that's what you are curious about.)

Regarding the application here you are asking the obvious, which is good,
however it hasn't even been written. I would rather get my hardware working
and the system responding to its environment rather then worry about the
application before its target works.

And as regards my costs, quoting yourself here: 
"on your costs, are you considering all the costs? The Thincan or the alix1c
are more like $140 or so, but they run off 1 power supply and don't require
the messy PC power supply and case."

Can you point me to a location for the Thincan, or the alix1c devices?

Oh and the commodity wireless networking card is going to be a WPC11 from
one of the better known firms.

To be honest I do not even have a proper budget for the entire project, let
alone the specific board. I am currently in the bouncing ideas phase at the
moment.
--
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you always." Obi-Wan Kenobi
? 


> -----Original Message-----
> From: linuxbios-bounces at linuxbios.org
[mailto:linuxbios-bounces at linuxbios.org] On
> Behalf Of ron minnich
> Sent: Thursday, November 08, 2007 12:35 AM
> To: Gregg C Levine
> Cc: LinuxBIOS Mailing List
> Subject: Re: [LinuxBIOS] Booting from USB
> 
> on your costs, are you considering all the costs? The Thincan or the
> alix1c are more like $140 or so, but they run off 1 power supply and
> don't require the messy PC power supply and case. Does  your
> application require standard PC attributes? What's the end
> environment?
> 
> ron
> 
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios




From corey.osgood at gmail.com  Thu Nov  8 06:47:21 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 08 Nov 2007 00:47:21 -0500
Subject: [LinuxBIOS] Booting from USB
In-Reply-To: <004401c821c8$ac1719b0$6401a8c0@who8>
References: <004401c821c8$ac1719b0$6401a8c0@who8>
Message-ID: <4732A2E9.2000002@gmail.com>

Gregg C Levine wrote:
> Hello!
> I have a project taking shape that would eventually have a system booting a
> file-system from USB.
>   

Sweet! I look forward to your results!

> I remember that we had a method of doing something of a sort from USB, using
> the contents of the v1 release. To be honest I am not even sure I remember
> the details behind it, or the individual who was the developer behind it,
> just that it was possible. Up to a point of course.
>   

FILO has support for USB, but unfortunately UHCI is broken and EHCI is
unsupported. OHCI works AFAIK, but I can't even confirm that much. I
started some hacking on FILO to use a USB interface similar to the linux
kernel, so that EHCI could be put in place easier, but gave up. I'm no
expert on USB (or IDE, or SCSI, or ATAPI), so I was in over my head.

> Now the project, essentially it would be an EPIA type board with a USB
> device a file-system, when booted we'd have a Linux prompt and all of the
> usual features thusly. The networking card would be a commodity wireless
> one. 
>
> The problem is that of selecting the board, and then configuring it to do
> that. I would like recommendations. The problem is of course money I would
> like it to be under 100 dollars US for the board. Preferably below 60
> dollars US for it.
>   

Take a look at the Jetway J7F2WE. I'm working on the last stages of
bringing it in to LB as I'm writing this. I think the cost is ~$150 USD.
Other options include the ALIX.1C, ~$140 and fully supported, and this
Elite C7VCM, seen here:
http://www.mini-box.com/Elite-C7-1-5G?sc=8&category=99 which is
unsupported, but shouldn't be too hard once the CN700 stuff is in for
the Jetway. I'm not an expert, but I'd say from the looks of things
Elite is another PCChips brand, so I'd be cautious. Each has its own
advantages/disadvantages, all the features are listed on mini-box.com.
There are of course other options (an ebay Epia-M, for instance), but
these boards are all still in production.

-Corey

> Currently the file-system I've chosen is that of RUNT Linux, the fact that
> is a UMSDOS based arrangement built using Slackware Linux is that of the
> reason.
>
> And naturally when the thing came up and started the classic doing something
> specific phase, that's where I'd be ending up with designing a gizmo to do
> most of that. And coding the programs behind it. 
> --
> Gregg C Levine hansolofalcon at worldnet.att.net
> "The Force will be with you always." Obi-Wan Kenobi



From joe at smittys.pointclark.net  Thu Nov  8 06:50:19 2007
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Thu, 08 Nov 2007 00:50:19 -0500
Subject: [LinuxBIOS] r2951
	-	trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx
In-Reply-To: <20071107220908.1952C36C07A@smittys.pointclark.net>
References: <20071107220908.1952C36C07A@smittys.pointclark.net>
Message-ID: <20071108005019.6rnnn4evi8g0ws8o@www.smittys.pointclark.net>

Little confused by this. Isn't this supposed to be posted to the list  
first for review, before being commited? Is it ok for the same person  
to "Signed-off-by:" and "Acked-by:"?? See comments below...

Thanks - Joe

Quoting svn at openbios.org:

> Author: uwe
> Date: 2007-11-07 23:09:02 +0100 (Wed, 07 Nov 2007)
> New Revision: 2951
>
> Modified:
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c
>    trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
> Log:
> Add initial support for all known ICH* southbridges to the
> i82801xx code for the following parts:
>
>  - AC97 audio/modem
>  - Onboard network interface cards (NICs)
>  - USB 1.1 controllers
>  - SMBus controllers
>
> Some other parts are still missing and will be added later.
>
> Use PCI ID #defines from pci_ids.h everywhere. Constify various structs.
> Also, fix some random cosmetic issues in the code.
>
> All of this is relatively trivial and tested by manually building
> all boards which currently use the i82801xx code.
>
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
>
>
>
> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb	2007-11-07   
> 19:07:17 UTC (rev 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb	2007-11-07   
> 22:09:02 UTC (rev 2951)
> @@ -17,6 +17,7 @@
>  ## along with this program; if not, write to the Free Software
>  ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>  ##
> +
>  driver i82801xx.o
>  driver i82801xx_usb.o
>  driver i82801xx_lpc.o
>
> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c	2007-11-07   
> 19:07:17 UTC (rev 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c	2007-11-07   
> 22:09:02 UTC (rev 2951)
> @@ -30,7 +30,7 @@
>  	unsigned int index = 0;
>  	uint16_t cur_disable_mask, new_disable_mask;
>
> -	/* All 82801 devices should be on bus 0. */
> +	/* All 82801xx devices should be on bus 0. */
>  	unsigned int devfn = PCI_DEVFN(0x1f, 0);	// LPC
>  	device_t lpc_dev = dev_find_slot(0, devfn);	// 0
>  	if (!lpc_dev)
> @@ -50,10 +50,11 @@
>  	if (index == 0) {
>  		index = 14;
>  	}

All devices are not on Bus 0. The NIC and PCI Cards are on Bus 1 down  
from the PCI Bus.

> +
>  	cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
> -	new_disable_mask = cur_disable_mask & ~(1 << index);	// enable it
> +	new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */
>  	if (!dev->enabled) {
> -		new_disable_mask |= (1 << index); // disable it, if desired
> +		new_disable_mask |= (1 << index); /* Disable it, if desired. */
>  	}
>  	if (new_disable_mask != cur_disable_mask) {
>  		pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
> @@ -61,6 +62,6 @@
>  }
>
>  struct chip_operations southbridge_intel_i82801xx_ops = {
> -	CHIP_NAME("Intel i82801 Series Southbridge")
> +	CHIP_NAME("Intel 82801 Series Southbridge")
>  	.enable_dev = i82801xx_enable,
>  };
>
> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c	2007-11-07   
> 19:07:17 UTC (rev 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c	2007-11-07   
> 22:09:02 UTC (rev 2951)
> @@ -19,13 +19,15 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>
> +/* This code should work for all ICH* southbridges with AC97 audio/modem. */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
>  #include <device/pci_ids.h>
>  #include "i82801xx.h"
>
> -static struct device_operations ac97_ops = {
> +static const struct device_operations ac97_ops = {
>  	.read_resources		= pci_dev_read_resources,
>  	.set_resources		= pci_dev_set_resources,
>  	.enable_resources	= pci_dev_enable_resources,
> @@ -34,80 +36,109 @@
>  	.enable			= i82801xx_enable,
>  };
>
> -/* 82801AA */
> +/* 82801AA (ICH) */
>  static const struct pci_driver i82801aa_ac97_audio __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2415,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO,
>  };
>
>  static const struct pci_driver i82801aa_ac97_modem __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2416,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM,
>  };
>
> -/* 82801AB */
> +/* 82801AB (ICH0) */
>  static const struct pci_driver i82801ab_ac97_audio __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2425,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO,
>  };
>
>  static const struct pci_driver i82801ab_ac97_modem __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2426,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM,
>  };
>
> -/* 82801BA */
> +/* 82801BA/BAM (ICH2/ICH2-M) */
>  static const struct pci_driver i82801ba_ac97_audio __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2445,
> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO,
>  };
>
>  static const struct pci_driver i82801ba_ac97_modem __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2446,
> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM,
>  };
>
> -/* 82801CA */
> +/* 82801CA/CAM (ICH3-S/ICH3-M) */
>  static const struct pci_driver i82801ca_ac97_audio __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2485,
> +	.device	= PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO,
>  };
>
>  static const struct pci_driver i82801ca_ac97_modem __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2486,
> +	.device	= PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM,
>  };
>
> -/* 82801DB & 82801DBM */
> +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
>  static const struct pci_driver i82801db_ac97_audio __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24c5,
> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
>  };
>
>  static const struct pci_driver i82801db_ac97_modem __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24c6,
> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
>  };
>
> -/* 82801EB & 82801ER */
> -static const struct pci_driver i82801ex_ac97_audio __pci_driver = {
> +/* 82801EB/ER (ICH5/ICH5R) */
> +static const struct pci_driver i82801eb_ac97_audio __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24d5,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_AC97_AUDIO,
>  };
>
> -static const struct pci_driver i82801ex_ac97_modem __pci_driver = {
> +static const struct pci_driver i82801eb_ac97_modem __pci_driver = {
>  	.ops	= &ac97_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24d6,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_AC97_MODEM,
>  };
> +
> +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
> +static const struct pci_driver i82801fb_ac97_audio __pci_driver = {
> +	.ops	= &ac97_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_AC97_AUDIO,
> +};
> +
> +static const struct pci_driver i82801fb_ac97_modem __pci_driver = {
> +	.ops	= &ac97_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_AC97_MODEM,
> +};
> +
> +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
> +/* Note: 82801GU (ICH7-U) doesn't have AC97 audio/modem. */
> +static const struct pci_driver i82801gb_ac97_audio __pci_driver = {
> +	.ops	= &ac97_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_AC97_AUDIO,
> +};
> +
> +static const struct pci_driver i82801gb_ac97_modem __pci_driver = {
> +	.ops	= &ac97_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_AC97_MODEM,
> +};
> +
> +/* Note: There's no AC97 audio/modem on ICH8/ICH9/C-ICH. */
>
> Modified:   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c	2007-11-07 19:07:17 UTC (rev   
> 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c	2007-11-07 22:09:02 UTC (rev   
> 2951)
> @@ -29,7 +29,7 @@
>  	device_t dev;
>  	uint16_t device_id;
>
> -	/* Set the SMBus device staticly. */
> +	/* Set the SMBus device statically. */
>  	dev = PCI_DEV(0x0, 0x1f, 0x3);
>
>  	/* Check to make sure we've got the right device. */
>
> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c	2007-11-07   
> 19:07:17 UTC (rev 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c	2007-11-07   
> 22:09:02 UTC (rev 2951)
> @@ -18,12 +18,14 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>
> +/* This code should work for all ICH* southbridges with a NIC. */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
>  #include <device/pci_ids.h>
>
> -static struct device_operations nic_ops = {
> +static const struct device_operations nic_ops = {
>  	.read_resources		= pci_dev_read_resources,
>  	.set_resources		= pci_dev_set_resources,
>  	.enable_resources	= pci_dev_enable_resources,
> @@ -31,14 +33,68 @@
>  	.scan_bus		= 0,
>  };
>
> -static const struct pci_driver i82801dbm_nic __pci_driver = {
> +/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */
> +
> +/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */
> +static const struct pci_driver i82801ba_nic __pci_driver = {
>  	.ops	= &nic_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x103a,
> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_LAN,
>  };
>
> -static const struct pci_driver i82801ex_nic __pci_driver = {
> +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
> +static const struct pci_driver i82801db_nic __pci_driver = {
>  	.ops	= &nic_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x1051,
> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_LAN,
>  };

My NIC on the 82801DB is .device = 0x103a, this is also what is in the  
datasheet.
> +
> +/* 82801EB/ER (ICH5/ICH5R) */
> +static const struct pci_driver i82801eb_nic __pci_driver = {
> +	.ops	= &nic_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_LAN,
> +};
> +
> +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
> +static const struct pci_driver i82801fb_nic __pci_driver = {
> +	.ops	= &nic_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_LAN,
> +};
> +
> +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
> +/* Note: 82801GU (ICH7-U) doesn't have a NIC. */
> +static const struct pci_driver i82801gb_nic __pci_driver = {
> +	.ops	= &nic_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_LAN,
> +};
> +
> +/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */
> +static const struct pci_driver i82801hb_nic __pci_driver = {
> +	.ops	= &nic_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801HB_LAN,
> +};
> +
> +/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */
> +static const struct pci_driver i82801ib_nic __pci_driver = {
> +	.ops	= &nic_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_LAN,
> +};
> +
> +/* 82801E (C-ICH) */
> +static const struct pci_driver i82801e_nic1 __pci_driver = {
> +	.ops	= &nic_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801E_LAN1,
> +};
> +
> +static const struct pci_driver i82801e_nic2 __pci_driver = {
> +	.ops	= &nic_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801E_LAN2,
> +};
> +
>
> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07   
> 19:07:17 UTC (rev 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07   
> 22:09:02 UTC (rev 2951)
> @@ -23,7 +23,6 @@
>  #include <device/device.h>
>  #include <device/pci.h>
>  #include <device/pci_ids.h>
> -#include <device/pci_ops.h>
>  #include "i82801xx.h"
>
>  /* TODO: Set dynamically, if the user only wants one SATA channel or none

This should be setup to only work with ICH's that support sata.

>
> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c	2007-11-07  
>  19:07:17 UTC (rev 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c	2007-11-07  
>  22:09:02 UTC (rev 2951)
> @@ -18,16 +18,18 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>
> +/* TODO: Check datasheets if this will work for all ICH* southbridges. */
> +
> +#include <stdint.h>
>  #include <smbus.h>
>  #include <pci.h>
>  #include <arch/io.h>
> -#include "i82801_model_specific.h"
>  #include "i82801xx.h"
>  #include "i82801_smbus.h"
>
> -static int smbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
> +static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
>  {
> -	unsigned device;
> +	unsigned device;	/* TODO: u16? */
>  	struct resource *res;
>
>  	device = dev->path.u.i2c.device;
> @@ -36,11 +38,11 @@
>  	return do_smbus_read_byte(res->base, device, address);
>  }
>
> -static struct smbus_bus_operations lops_smbus_bus = {
> +static const struct smbus_bus_operations lops_smbus_bus = {
>  	.read_byte	= smbus_read_byte,
>  };
>
> -static struct device_operations smbus_ops = {
> +static const struct device_operations smbus_ops = {
>  	.read_resources		= pci_dev_read_resources,
>  	.set_resources		= pci_dev_set_resources,
>  	.enable_resources	= pci_dev_enable_resources,
> @@ -50,44 +52,79 @@
>  	.ops_smbus_bus		= &lops_smbus_bus,
>  };
>
> -/* 82801AA */
> -static const struct pci_driver smbus_driver __pci_driver = {
> +/* 82801AA (ICH) */
> +static const struct pci_driver i82801aa_smb __pci_driver = {
>  	.ops	= &smbus_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2413,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AA_SMB,
>  };
>
> -/* 82801AB */
> -static const struct pci_driver smbus_driver __pci_driver = {
> +/* 82801AB (ICH0) */
> +static const struct pci_driver i82801ab_smb __pci_driver = {
>  	.ops	= &smbus_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2423,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AB_SMB,
>  };
>
> -/* 82801BA */
> -static const struct pci_driver smbus_driver __pci_driver = {
> +/* 82801BA/BAM (ICH2/ICH2-M) */
> +static const struct pci_driver i82801ba_smb __pci_driver = {
>  	.ops	= &smbus_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2443,
> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_SMB,
>  };
>
> -/* 82801CA */
> -static const struct pci_driver smbus_driver __pci_driver = {
> +/* 82801CA/CAM (ICH3-S/ICH3-M) */
> +static const struct pci_driver i82801ca_smb __pci_driver = {
>  	.ops	= &smbus_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2483,
> +	.device	= PCI_DEVICE_ID_INTEL_82801CA_SMB,
>  };
>
> -/* 82801DB and 82801DBM */
> -static const struct pci_driver smbus_driver __pci_driver = {
> +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
> +static const struct pci_driver i82801db_smb __pci_driver = {
>  	.ops	= &smbus_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24c3,
> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_SMB,
>  };
>
> -/* 82801EB and 82801ER */
> -static const struct pci_driver smbus_driver __pci_driver = {
> +/* 82801EB/ER (ICH5/ICH5R) */
> +static const struct pci_driver i82801eb_smb __pci_driver = {
>  	.ops	= &smbus_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24d3,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_SMB,
>  };
> +
> +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
> +static const struct pci_driver i82801fb_smb __pci_driver = {
> +	.ops	= &smbus_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_SMB,
> +};
> +
> +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
> +static const struct pci_driver i82801gb_smb __pci_driver = {
> +	.ops	= &smbus_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_SMB,
> +};
> +
> +/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */
> +static const struct pci_driver i82801hb_smb __pci_driver = {
> +	.ops	= &smbus_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801HB_LAN,
> +};
> +
> +/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */
> +static const struct pci_driver i82801ib_smb __pci_driver = {
> +	.ops	= &smbus_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_SMB,
> +};
> +
> +/* 82801E (C-ICH) */
> +static const struct pci_driver i82801e_smb __pci_driver = {
> +	.ops	= &smbus_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801E_SMB,
> +};
>
> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c	2007-11-07   
> 19:07:17 UTC (rev 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c	2007-11-07   
> 22:09:02 UTC (rev 2951)
> @@ -18,11 +18,12 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>
> +/* This code should work for all ICH* southbridges with USB. */
> +
>  #include <console/console.h>
>  #include <device/device.h>
>  #include <device/pci.h>
>  #include <device/pci_ids.h>
> -#include <device/pci_ops.h>
>  #include "i82801xx.h"
>
>  static void usb_init(struct device *dev)
> @@ -30,7 +31,7 @@
>  	/* TODO: Any init needed? Some ports have it, others don't. */
>  }
>
> -static struct device_operations usb_ops = {
> +static const struct device_operations usb_ops = {
>  	.read_resources		= pci_dev_read_resources,
>  	.set_resources		= pci_dev_set_resources,
>  	.enable_resources	= pci_dev_enable_resources,
> @@ -39,92 +40,217 @@
>  	.enable			= i82801xx_enable,
>  };
>
> -/* 82801AA */
> -static const struct pci_driver i82801aa_usb_1 __pci_driver = {
> +/* 82801AA (ICH) */
> +static const struct pci_driver i82801aa_usb1 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2412,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AA_USB,
>  };
>
> -/* 82801AB */
> -static const struct pci_driver i82801ab_usb_1 __pci_driver = {
> +/* 82801AB (ICH0) */
> +static const struct pci_driver i82801ab_usb1 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2422,
> +	.device	= PCI_DEVICE_ID_INTEL_82801AB_USB,
>  };
>
> -/* 82801BA */
> -static const struct pci_driver i82801ba_usb_1 __pci_driver = {
> +/* 82801BA/BAM (ICH2/ICH2-M) */
> +static const struct pci_driver i82801ba_usb1 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2442,
> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB1,
>  };
>
> -static const struct pci_driver i82801ba_usb_2 __pci_driver = {
> +static const struct pci_driver i82801ba_usb2 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2444,
> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB2,
>  };
>
> -/* 82801CA */
> -static const struct pci_driver i82801ca_usb_1 __pci_driver = {
> +/* 82801CA/CAM (ICH3-S/ICH3-M) */
> +static const struct pci_driver i82801ca_usb1 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2482,
> +	.device	= PCI_DEVICE_ID_INTEL_82801CA_USB1,
>  };
>
> -static const struct pci_driver i82801ca_usb_2 __pci_driver = {
> +static const struct pci_driver i82801ca_usb2 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2484,
> +	.device	= PCI_DEVICE_ID_INTEL_82801CA_USB2,
>  };
>
> -static const struct pci_driver i82801ca_usb_3 __pci_driver = {
> +static const struct pci_driver i82801ca_usb3 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x2487,
> +	.device	= PCI_DEVICE_ID_INTEL_82801CA_USB3,
>  };
>
> -/* 82801DB and 82801DBM */
> -static const struct pci_driver i82801db_usb_1 __pci_driver = {
> +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
> +static const struct pci_driver i82801db_usb1 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24c2,
> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_USB1,
>  };
>
> -static const struct pci_driver i82801db_usb_2 __pci_driver = {
> +static const struct pci_driver i82801db_usb2 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24c4,
> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_USB2,
>  };
>
> -static const struct pci_driver i82801db_usb_3 __pci_driver = {
> +static const struct pci_driver i82801db_usb3 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24c7,
> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_USB3,
>  };
>
> -/* 82801EB and 82801ER */
> -static const struct pci_driver i82801ex_usb_1 __pci_driver = {
> +/* 82801EB/ER (ICH5/ICH5R) */
> +static const struct pci_driver i82801eb_usb1 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24d2,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB1,
>  };
>
> -static const struct pci_driver i82801ex_usb_2 __pci_driver = {
> +static const struct pci_driver i82801eb_usb2 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24d4,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB2,
>  };
>
> -static const struct pci_driver i82801ex_usb_3 __pci_driver = {
> +static const struct pci_driver i82801eb_usb3 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24d7,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB3,
>  };
>
> -static const struct pci_driver i82801ex_usb_4 __pci_driver = {
> +static const struct pci_driver i82801eb_usb4 __pci_driver = {
>  	.ops	= &usb_ops,
>  	.vendor	= PCI_VENDOR_ID_INTEL,
> -	.device	= 0x24de,
> +	.device	= PCI_DEVICE_ID_INTEL_82801EB_USB4,
>  };
> +
> +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
> +static const struct pci_driver i82801fb_usb1 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB1,
> +};
> +
> +static const struct pci_driver i82801fb_usb2 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB2,
> +};
> +
> +static const struct pci_driver i82801fb_usb3 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB3,
> +};
> +
> +static const struct pci_driver i82801fb_usb4 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801FB_USB4,
> +};
> +
> +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
> +static const struct pci_driver i82801gb_usb1 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB1,
> +};
> +
> +static const struct pci_driver i82801gb_usb2 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB2,
> +};
> +
> +static const struct pci_driver i82801gb_usb3 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB3,
> +};
> +
> +static const struct pci_driver i82801gb_usb4 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801GB_USB4,
> +};
> +
> +/* 82801HB/HR/HDH/HDO/HBM/HEM (ICH8/ICH8R/ICH8DH/ICH8DO/ICH8M/ICH8M-E) */
> +static const struct pci_driver i82801hb_usb1 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB1,
> +};
> +
> +static const struct pci_driver i82801hb_usb2 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB2,
> +};
> +
> +static const struct pci_driver i82801hb_usb3 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB3,
> +};
> +
> +static const struct pci_driver i82801hb_usb4 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB4,
> +};
> +
> +static const struct pci_driver i82801hb_usb5 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801HB_USB5,
> +};
> +
> +/* 82801IB/IR/IH/IO (ICH9/ICH9R/ICH9DH/ICH9DO) */
> +static const struct pci_driver i82801ib_usb1 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB1,
> +};
> +
> +static const struct pci_driver i82801ib_usb2 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB2,
> +};
> +
> +static const struct pci_driver i82801ib_usb3 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB3,
> +};
> +
> +static const struct pci_driver i82801ib_usb4 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB4,
> +};
> +
> +static const struct pci_driver i82801ib_usb5 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB5,
> +};
> +
> +static const struct pci_driver i82801ib_usb6 __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801IB_USB6,
> +};
> +
> +/* 82801E (C-ICH) */
> +static const struct pci_driver i82801e_usb __pci_driver = {
> +	.ops	= &usb_ops,
> +	.vendor	= PCI_VENDOR_ID_INTEL,
> +	.device	= PCI_DEVICE_ID_INTEL_82801E_USB,
> +};
>
> Modified:   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
> ===================================================================
> ---   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c	2007-11-07 19:07:17 UTC (rev   
> 2950)
> +++   
> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c	2007-11-07 22:09:02 UTC (rev   
> 2951)
> @@ -23,7 +23,6 @@
>  #include <device/device.h>
>  #include <device/pci.h>
>  #include <device/pci_ids.h>
> -#include <device/pci_ops.h>
>  #include "i82801xx.h"
>
>  static void usb_ehci_init(struct device *dev)
>
>
> --
> linuxbios mailing list
> linuxbios at linuxbios.org
> http://www.linuxbios.org/mailman/listinfo/linuxbios
>







From corey.osgood at gmail.com  Thu Nov  8 07:09:16 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 08 Nov 2007 01:09:16 -0500
Subject: [LinuxBIOS]
	r2951	-	trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx
In-Reply-To: <20071108005019.6rnnn4evi8g0ws8o@www.smittys.pointclark.net>
References: <20071107220908.1952C36C07A@smittys.pointclark.net>
	<20071108005019.6rnnn4evi8g0ws8o@www.smittys.pointclark.net>
Message-ID: <4732A80C.8000901@gmail.com>

joe at smittys.pointclark.net wrote:
> Little confused by this. Isn't this supposed to be posted to the list  
> first for review, before being commited? Is it ok for the same person  
> to "Signed-off-by:" and "Acked-by:"?? See comments below...
>   

This qualifies as a "trivial" patch, in other words the only changes are
to improve comments and fix possible whitespace errors (I think using
defined PCI IDs also qualifies as trivial). There are no real changes to
the actual code, so nothing should be broken in the process. Hence the
normal process is forgone.

>> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c
>> ===================================================================
>> ---   
>> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c	2007-11-07   
>> 19:07:17 UTC (rev 2950)
>> +++   
>> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c	2007-11-07   
>> 22:09:02 UTC (rev 2951)
>> @@ -30,7 +30,7 @@
>>  	unsigned int index = 0;
>>  	uint16_t cur_disable_mask, new_disable_mask;
>>
>> -	/* All 82801 devices should be on bus 0. */
>> +	/* All 82801xx devices should be on bus 0. */
>>  	unsigned int devfn = PCI_DEVFN(0x1f, 0);	// LPC
>>  	device_t lpc_dev = dev_find_slot(0, devfn);	// 0
>>  	if (!lpc_dev)
>> @@ -50,10 +50,11 @@
>>  	if (index == 0) {
>>  		index = 14;
>>  	}
>>     
>
> All devices are not on Bus 0. The NIC and PCI Cards are on Bus 1 down  
> from the PCI Bus.
>   

Interesting, I'll have a look at that tomorrow. This isn't a change in
the code in any way though, just fixing a comment.

>> -static const struct pci_driver i82801dbm_nic __pci_driver = {
>> +/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */
>> +
>> +/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */
>> +static const struct pci_driver i82801ba_nic __pci_driver = {
>>  	.ops	= &nic_ops,
>>  	.vendor	= PCI_VENDOR_ID_INTEL,
>> -	.device	= 0x103a,
>> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_LAN,
>>  };
>>
>> -static const struct pci_driver i82801ex_nic __pci_driver = {
>> +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
>> +static const struct pci_driver i82801db_nic __pci_driver = {
>>  	.ops	= &nic_ops,
>>  	.vendor	= PCI_VENDOR_ID_INTEL,
>> -	.device	= 0x1051,
>> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_LAN,
>>  };
>>     
>
> My NIC on the 82801DB is .device = 0x103a, this is also what is in the  
> datasheet.

It's because of the way the patch got set up. For some reason, it's
replacing the lines where the i82801ex driver was with the i82801db
(which is a few lines up). Since PCI_DEVICE_ID_INTEL_82801DB_LAN =
0x103a, it should be fine.

>> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c
>> ===================================================================
>> ---   
>> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07   
>> 19:07:17 UTC (rev 2950)
>> +++   
>> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07   
>> 22:09:02 UTC (rev 2951)
>> @@ -23,7 +23,6 @@
>>  #include <device/device.h>
>>  #include <device/pci.h>
>>  #include <device/pci_ids.h>
>> -#include <device/pci_ops.h>
>>  #include "i82801xx.h"
>>
>>  /* TODO: Set dynamically, if the user only wants one SATA channel or none
>>     
>
> This should be setup to only work with ICH's that support sata.

And it does. The driver is included per default, but will only load/run
when LB comes across a device ID for an SATA device. No ID, the driver
doesn't do anything. It should probably be somehow fixed to only build
for SATA-supporting chipsets, but alas the world isn't perfect ;)

-Corey



From vladc6 at yahoo.com  Thu Nov  8 07:12:27 2007
From: vladc6 at yahoo.com (Vlad)
Date: Wed, 7 Nov 2007 22:12:27 -0800 (PST)
Subject: [LinuxBIOS] Booting from USB
In-Reply-To: <4732A2E9.2000002@gmail.com>
Message-ID: <236595.56770.qm@web54407.mail.yahoo.com>

--- Corey Osgood <corey.osgood at gmail.com> wrote: 
> FILO has support for USB, but unfortunately UHCI is broken and EHCI
> is
> unsupported.

GRUB 2 is also supported as a LinuxBIOS payload now.[1] Can GRUB 2
boot from USB?

Vlad

[1] http://www.linuxbios.org/pipermail/linuxbios/2007-November/026636.html

__________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 



From corey.osgood at gmail.com  Thu Nov  8 07:31:49 2007
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 08 Nov 2007 01:31:49 -0500
Subject: [LinuxBIOS] Booting from USB
In-Reply-To: <236595.56770.qm@web54407.mail.yahoo.com>
References: <236595.56770.qm@web54407.mail.yahoo.com>
Message-ID: <4732AD55.9040406@gmail.com>

Vlad wrote:
> --- Corey Osgood <corey.osgood at gmail.com> wrote: 
>   
>> FILO has support for USB, but unfortunately UHCI is broken and EHCI
>> is
>> unsupported.
>>     
>
> GRUB 2 is also supported as a LinuxBIOS payload now.[1] Can GRUB 2
> boot from USB?
>
> Vlad
>
> [1] http://www.linuxbios.org/pipermail/linuxbios/2007-November/026636.html
>   

Afaics, no:
http://lists.gnu.org/archive/html/grub-devel/2006-04/msg00047.html
Yes, it's old, but it's the most relevent/recent thing the search picked
up. Grub/grub2 relies on the bios' USB support, it doesn't have its own
drivers.

-Corey



From svn at openbios.org  Thu Nov  8 15:05:16 2007
From: svn at openbios.org (LinuxBIOS)
Date: Thu, 08 Nov 2007 14:05:16 -0000
Subject: [LinuxBIOS] #87: flashrom issues on m57sli-s4
In-Reply-To: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>
References: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>
Message-ID: <050.50315c692bf3d7bfe25914de406e14e9@openbios.org>

#87: flashrom issues on m57sli-s4
-------------------------+--------------------------------------------------
    Reporter:  ward      |         Owner:  hailfinger       
        Type:  defect    |        Status:  new              
    Priority:  major     |     Milestone:                   
   Component:  flashrom  |       Version:  v2               
  Resolution:            |      Keywords:                   
Dependencies:            |   Patchstatus:  there is no patch
-------------------------+--------------------------------------------------
Changes (by hailfinger):

  * owner:  somebody => hailfinger

Comment:

 I need superiotool output for a board with parallel flash running under
 LB. NOW.

 AFAICS the flash configuration is totally botched on LB with floating
 GPIOs, wrong timing etc.

 I have a patch pending which will solve the flashing problem on all M57SLI
 boards, but I refuse to send it to the list before I have superiotool
 output to verify.

-- 
Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:4>
LinuxBIOS <http://www.linuxbios.org/>

From ward at gnu.org  Thu Nov  8 16:22:25 2007
From: ward at gnu.org (Ward Vandewege)
Date: Thu, 8 Nov 2007 10:22:25 -0500
Subject: [LinuxBIOS] #87: flashrom issues on m57sli-s4
In-Reply-To: <050.50315c692bf3d7bfe25914de406e14e9@openbios.org>
References: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>
	<050.50315c692bf3d7bfe25914de406e14e9@openbios.org>
Message-ID: <20071108152225.GA17023@localdomain>

Hi Carl-Daniel,

On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
> #87: flashrom issues on m57sli-s4
> -------------------------+--------------------------------------------------
>     Reporter:  ward      |         Owner:  hailfinger       
>         Type:  defect    |        Status:  new              
>     Priority:  major     |     Milestone:                   
>    Component:  flashrom  |       Version:  v2               
>   Resolution:            |      Keywords:                   
> Dependencies:            |   Patchstatus:  there is no patch
> -------------------------+--------------------------------------------------
> Changes (by hailfinger):
> 
>   * owner:  somebody => hailfinger
> 
> Comment:
> 
>  I need superiotool output for a board with parallel flash running under
>  LB. NOW.

LinuxBIOS:          http://ward.vandewege.net/superiotool-lb.m57sli.dump
Proprietary BIOS:   http://ward.vandewege.net/superiotool-prop.m57sli.dump

>  AFAICS the flash configuration is totally botched on LB with floating
>  GPIOs, wrong timing etc.
> 
>  I have a patch pending which will solve the flashing problem on all M57SLI
>  boards, but I refuse to send it to the list before I have superiotool
>  output to verify.

Looking forward to that patch!

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From c-d.hailfinger.devel.2006 at gmx.net  Thu Nov  8 16:51:33 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 08 Nov 2007 16:51:33 +0100
Subject: [LinuxBIOS] #87: flashrom issues on m57sli-s4
In-Reply-To: <20071108152225.GA17023@localdomain>
References: <041.ecf9a38049d8bbbe15bbb6ff0a642599@openbios.org>	<050.50315c692bf3d7bfe25914de406e14e9@openbios.org>
	<20071108152225.GA17023@localdomain>
Message-ID: <47333085.2010600@gmx.net>

Hi Ward,

On 08.11.2007 16:22, Ward Vandewege wrote:
> On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
>   
>> #87: flashrom issues on m57sli-s4
>>
>>  I need superiotool output for a board with parallel flash running under
>>  LB. NOW.
>>     
>
> LinuxBIOS:          http://ward.vandewege.net/superiotool-lb.m57sli.dump
> Proprietary BIOS:   http://ward.vandewege.net/superiotool-prop.m57sli.dump
>   

Thanks!

ldn any
idx 07 20 21 22 23 24 2b 
val 06 87 16 00 01 00 00 plcc lb
                xx
val 0a 87 16 00 11 00 00 plcc prop
                   xx
val 0a 87 16 00 11 1a 00 soic prop
                xx xx
def NA 87 16 01 00 00 00
 
ldn 0x7 
idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd
val 00 00 00 00 00 00 1f 00 00 00 00 00 00 00 01 20 38 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32 00 plcc lb
       xx xx    xx             xx                xx                         xx          xx       xx xx          xx                         xx                xx
val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 plcc prop
                                     xx xx    xx
val 00 43 20 00 81 00 1f 00 00 08 00 08 20 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 soic prop
    xx xx xx xx xx    xx       xx    xx xx       xx                                     xx    xx xx xx xx    xx xx    xx                   xx xx             xx
def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 

The patch below will NOT work, I have yet to figure out how to tell
Config.lb that I want to set a 8-bit value (which is a simple value
and not irq/drq/io) in a superio section. But it should be enough to
base a real patch on it.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb	(Revision 2953)
+++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb	(Arbeitskopie)
@@ -239,7 +239,9 @@
 					device pci 0.0 on end   # HT
                 			device pci 1.0 on # LPC
 						chip superio/ite/it8716f
-							device pnp 2e.0 off #  Floppy
+							device pnp 2e.0 off #  Floppy and anyLDN
+								0x23 = 0x11 # watchdog from CLKIN, CLKIN = 24 MHz
+								#0x24 = 0x1a # serial flash (SPI only)
                 	                 			io 0x60 = 0x3f0
                 	                			irq 0x70 = 6
                 	                			drq 0x74 = 2
@@ -269,6 +271,30 @@
                 	        			device pnp 2e.6 on #  Mouse
                 	                			irq 0x70 = 12
 							end
+                	        			device pnp 2e.7 on #  GPIO, SPI flash
+								0x25 = 0x0 # pin 84 is not GP10
+								0x26 = 0x43 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
+								0x27 = 0x20 # pin 13 is GP35
+								#0x28 = 0x0 # pin 70 is not GP46
+								0x29 = 0x81 # pin 6,3,128,127,126 is GP63,64,65,66,67
+								#0x2c = 0x1f # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
+								io 0x62 = 0x800 # simple i/o base
+                	                			#io 0x64 = 0x820 # serial flash io (SPI only)
+								#0x71 = 0x1 # watch dog force timeout (parallel flash only)
+								irq 0x72 = 0x0 # no WDT interrupt
+								0xb8 = 0x0 # GPIO pin set 1 disable internal pullup
+								0xbc = 0x01 # GPIO pin set 5 enable internal pullup
+								#0xc0 = 0x0 # SIO pin set 1 alternate function
+								0xc1 = 0x43 # SIO pin set 2 mixed function
+								0xc2 = 0x20 # SIO pin set 3 mixed function
+								#0xc3 = 0x0 # SIO pin set 4 alternate function
+								#0xc8 = 0x0 # SIO pin set 1 input mode
+								0xc9 = 0x0 # SIO pin set 2 mixed input/output mode
+								#0xcb = 0x0 # SIO pin set 4 input mode
+								#0xf0 = 0x10 # generate SMI# on EC IRQ
+								#0xf1 = 0x40 # SMI# level trigger
+								0xf6 = 0x28 # HWMON alert beep pin location
+							end
                 	        			device pnp 2e.8 off #  MIDI
 								io 0x60 = 0x300
 								irq 0x70 = 10
@@ -305,6 +331,7 @@
                                                         device i2c 57 on end
                                                 end 
 					end # SM
+#wtf?!? we already have device pci 1.1 in the section above
                                         device pci 1.1 on # SM 1
 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 #                                                chip drivers/generic/generic #PCIXA Slot1


The "wtf?!?" comment is intentional and designates another bug. However,
I have no idea which device number we need here.

Regards,
Carl-Daniel




From hansolofalcon at worldnet.att.net  Thu Nov  8 17:23:37 2007
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Thu, 8 Nov 2007 11:23:37 -0500
Subject: [LinuxBIOS] MSI supported boards
Message-ID: <004201c82223$b978ca80$6401a8c0@who8>

Hello!
Would any of the MSI family of motherboards be supported? And where in the
wiki would I go looking for this information?

Last night after our interesting discussions concerning my project of USB
booting, I checked the NewEgg site ( www.newegg.com ) for clews and found a
good collection, practically a baker's dozen there. I seem to recall that
MSI was an interesting target for one version of LinuxBIOS of course I could
be mixing up my facts.
--
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you always." Obi-Wan Kenobi
? 






From andi.mundt at web.de  Thu Nov  8 18:42:31 2007
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Thu, 8 Nov 2007 18:42:31 +0100
Subject: [LinuxBIOS]  #87: flashrom issues on m57sli-s4
Message-ID: <20071108174231.GA3741@flashgordon>

Hi,

I have no idea if this is of any use or interest, but my superiotool output
differs slightly from ward's:


$diff andi_LB ward_LB

14c14
< val 07 87 16 00 01 00 00
---
> val 06 87 16 00 01 00 00
34c34
< val 01 02 90 02 30 09 80 00 0a 00 80 00 ff
---
> val 01 02 90 02 30 09 80 00 0a 00 80 00 e7

 
$diff andi_prop ward_prop

34c34
< val 01 02 90 00 00 00 80 00 0a 00 80 00 ff
---
> val 01 02 90 00 00 00 80 00 0a 00 80 00 e7
42c42
< val 00 00 02 00
---
> val 01 0c 02 00
46c46
< val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00
---
> val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00



Regards,

	Andi



From uwe at hermann-uwe.de  Thu Nov  8 19:05:16 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 8 Nov 2007 19:05:16 +0100
Subject: [LinuxBIOS] r2951
	-	trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx
In-Reply-To: <4732A80C.8000901@gmail.com>
References: <20071107220908.1952C36C07A@smittys.pointclark.net>
	<20071108005019.6rnnn4evi8g0ws8o@www.smittys.pointclark.net>
	<4732A80C.8000901@gmail.com>
Message-ID: <20071108180515.GA8607@greenwood>

On Thu, Nov 08, 2007 at 01:09:16AM -0500, Corey Osgood wrote:
> >> -	/* All 82801 devices should be on bus 0. */
> >> +	/* All 82801xx devices should be on bus 0. */
> >>  	unsigned int devfn = PCI_DEVFN(0x1f, 0);	// LPC
> >>  	device_t lpc_dev = dev_find_slot(0, devfn);	// 0
> >>  	if (!lpc_dev)
> >> @@ -50,10 +50,11 @@
> >>  	if (index == 0) {
> >>  		index = 14;
> >>  	}
> >>     
> >
> > All devices are not on Bus 0. The NIC and PCI Cards are on Bus 1 down  
> > from the PCI Bus.
> 
> Interesting, I'll have a look at that tomorrow. This isn't a change in
> the code in any way though, just fixing a comment.

Yep. But Joe is correct, the code probably needs fixing.


> >> -static const struct pci_driver i82801dbm_nic __pci_driver = {
> >> +/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */
> >> +
> >> +/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */
> >> +static const struct pci_driver i82801ba_nic __pci_driver = {
> >>  	.ops	= &nic_ops,
> >>  	.vendor	= PCI_VENDOR_ID_INTEL,
> >> -	.device	= 0x103a,
> >> +	.device	= PCI_DEVICE_ID_INTEL_82801BA_LAN,
> >>  };
> >>
> >> -static const struct pci_driver i82801ex_nic __pci_driver = {
> >> +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
> >> +static const struct pci_driver i82801db_nic __pci_driver = {
> >>  	.ops	= &nic_ops,
> >>  	.vendor	= PCI_VENDOR_ID_INTEL,
> >> -	.device	= 0x1051,
> >> +	.device	= PCI_DEVICE_ID_INTEL_82801DB_LAN,
> >>  };
> >>     
> >
> > My NIC on the 82801DB is .device = 0x103a, this is also what is in the  
> > datasheet.
> 
> It's because of the way the patch got set up. For some reason, it's
> replacing the lines where the i82801ex driver was with the i82801db
> (which is a few lines up). Since PCI_DEVICE_ID_INTEL_82801DB_LAN =
> 0x103a, it should be fine.

Yes, the IDs are correct, I think.

When there are multiple ICH* southbridges with the same PCI device IDs,
I always used the "first" one, but you could really use any of them.

Example:

#define PCI_DEVICE_ID_INTEL_82801FB_IDE         0x266f
#define PCI_DEVICE_ID_INTEL_82801FR_IDE         0x266f
#define PCI_DEVICE_ID_INTEL_82801FW_IDE         0x266f
#define PCI_DEVICE_ID_INTEL_82801FRW_IDE        0x266f
#define PCI_DEVICE_ID_INTEL_82801FBM_IDE        0x266f

It doesn't matter which of the above you use, they're all the same.

 
> >> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c
> >> ===================================================================
> >> ---   
> >> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07   
> >> 19:07:17 UTC (rev 2950)
> >> +++   
> >> trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c	2007-11-07   
> >> 22:09:02 UTC (rev 2951)
> >> @@ -23,7 +23,6 @@
> >>  #include <device/device.h>
> >>  #include <device/pci.h>
> >>  #include <device/pci_ids.h>
> >> -#include <device/pci_ops.h>
> >>  #include "i82801xx.h"
> >>
> >>  /* TODO: Set dynamically, if the user only wants one SATA channel or none
> >>     
> >
> > This should be setup to only work with ICH's that support sata.

That, _and_ the code probably needs fixing to work with all the
different SATA devices on different ICH* southbridges. I haven't yet
checked which differences (if any) there are, though.

 
> And it does. The driver is included per default, but will only load/run
> when LB comes across a device ID for an SATA device. No ID, the driver
> doesn't do anything.

Yep.


> It should probably be somehow fixed to only build
> for SATA-supporting chipsets, but alas the world isn't perfect ;)

Yeah, we could do that, but it's not really high on the (my) priority
list, as the overhead is minimal. If I'm not mistaken such a struct
contains two 16bit values and a pointer. We have _way_ more critical
stuff to care about than this, IHMO.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Nov  8 19:10:40 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 8 Nov 2007 19:10:40 +0100
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700
	+	VT8237RChipset), PC2500E
In-Reply-To: <000601c821b2$6241e4c0$0200a8c0@sis.com.tw>
References: <516173.21801.qm@web54403.mail.yahoo.com>
	<47322166.1070908@gmail.com> <473236E3.7000603@onelabs.com>
	<20071107222126.GB15728@greenwood>
	<000601c821b2$6241e4c0$0200a8c0@sis.com.tw>
Message-ID: <20071108181040.GB8607@greenwood>

Hi Morgan!

On Thu, Nov 08, 2007 at 10:52:19AM +0800, Morgan Tsai /SiS wrote:
> SiS965(L) vs 966(L)
>
> Identical device ID: LAN, USB
> Different device ID: SATA, Audio(966 has HD Audio, but still reserved AC97)
>
> Although they are funtionally alike, such like register map.
> There is somewhare different value to be filled for bug fix.

That doesn't sound too bad, IMHO. If the only real differences are PCI
IDs of some devices and small changes in some registers, then the 966(L)
code could easily be adapted to also work with 965(L), correct?

Adding more PCI IDs is trivial and we can do that without datasheet
access I think, but the "different value to be filled for bug fix"
could be a problem if it's not documented publically...

Is there some errata sheet we can look at and/or do you know how to fix
the 966(L) code in svn to make it work for 965(L), too?


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From uwe at hermann-uwe.de  Thu Nov  8 19:17:38 2007
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 8 Nov 2007 19:17:38 +0100
Subject: [LinuxBIOS] MSI supported boards
In-Reply-To: <004201c82223$b978ca80$6401a8c0@who8>
References: <004201c82223$b978ca80$6401a8c0@who8>
Message-ID: <20071108181738.GC8607@greenwood>

On Thu, Nov 08, 2007 at 11:23:37AM -0500, Gregg C Levine wrote:
> Would any of the MSI family of motherboards be supported? And where in the
> wiki would I go looking for this information?

http://linuxbios.org/Supported_Motherboards


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From c-d.hailfinger.devel.2006 at gmx.net  Thu Nov  8 19:29:29 2007
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 08 Nov 2007 19:29:29 +0100
Subject: [LinuxBIOS] #87: flashrom issues on m57sli-s4
In-Reply-To: <20071108174231.GA3741@flashgordon>
References: <20071108174231.GA3741@flashgordon>
Message-ID: <47335589.60805@gmx.net>

On 08.11.2007 18:42, Andreas B. Mundt wrote:
> Hi,
>
> I have no idea if this is of any use or interest, but my superiotool output
> differs slightly from ward's:
>   

Thanks for the info.

> $diff andi_LB ward_LB
>
> 14c14
> < val 07 87 16 00 01 00 00
> ---
>   
>> val 06 87 16 00 01 00 00
>>     

OK, undefined register.

> 34c34
> < val 01 02 90 02 30 09 80 00 0a 00 80 00 ff
> ---
>   
>> val 01 02 90 02 30 09 80 00 0a 00 80 00 e7
>>     

OK, undefined register.

> $diff andi_prop ward_prop
>
> 34c34
> < val 01 02 90 00 00 00 80 00 0a 00 80 00 ff
> ---
>   
>> val 01 02 90 00 00 00 80 00 0a 00 80 00 e7
>>     

OK, undefined register.

> 42c42
> < val 00 00 02 00
> ---
>   
>> val 01 0c 02 00
>>     

OK, mouse disabled on one board.

> 46c46
> < val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00
> ---
>   
>> val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00
>>     

OK, watchdog timer disabled on one board.


So there is nothing to worry about and my analysis is now backed on
results for two boards.

Regards,
Carl-Daniel



From peter at stuge.se  Thu Nov  8 22:31:43 2007
From: peter at stuge.se (Peter Stuge)
Date: Thu, 8 Nov 2007 22:31:43 +0100
Subject: [LinuxBIOS] Booting from USB
In-Reply-To: <4732AD55.9040406@gmail.com>
References: <236595.56770.qm@web54407.mail.yahoo.com>
	<4732AD55.9040406@gmail.com>
Message-ID: <20071108213143.12888.qmail@stuge.se>

On Thu, Nov 08, 2007 at 01:31:49AM -0500, Corey Osgood wrote:
> Grub/grub2 relies on the bios' USB support, it doesn't have its own
> drivers.

Maybe we should try to change that. Does anyone know if GRUB has
block drivers at all? It must - for IDE at least, yes?


//Peter



From ward at gnu.org  Thu Nov  8 23:03:12 2007
From: ward at gnu.org (Ward Vandewege)
Date: Thu, 8 Nov 2007 17:03:12 -0500
Subject: [LinuxBIOS] [PATCH] buildrom support for booting Xen from LAB
Message-ID: <20071108220312.GA20553@localdomain>

This code is not very elegant, so if there are suggestions to improve it,
please shoot!

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator
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From my_tsai at sis.com  Fri Nov  9 12:18:16 2007
From: my_tsai at sis.com (Morgan Tsai /SiS)
Date: Fri, 9 Nov 2007 19:18:16 +0800
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700
	+VT8237RChipset), PC2500E
References: <516173.21801.qm@web54403.mail.yahoo.com>
	<47322166.1070908@gmail.com> <473236E3.7000603@onelabs.com>
	<20071107222126.GB15728@greenwood>
	<000601c821b2$6241e4c0$0200a8c0@sis.com.tw>
	<20071108181040.GB8607@greenwood>
Message-ID: <001501c822c2$3e7f5070$0200a8c0@sis.com.tw>

Dear Uwe,

Sorry for there is no errata sheet. Maybe I can add more PCI IDs
for our chipset first. I can provide some recommend setting written
at internal document, if needed.



Morgan


----- Original Message ----- 
From: "Uwe Hermann" <uwe at hermann-uwe.de>
To: "Morgan Tsai /SiS" <my_tsai at sis.com>
Cc: "bari" <bari at onelabs.com>; "Corey Osgood" <corey.osgood at gmail.com>; 
<linuxbios at linuxbios.org>
Sent: Friday, November 09, 2007 2:10 AM
Subject: Re: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 
+VT8237RChipset), PC2500E

Hi Morgan!

On Thu, Nov 08, 2007 at 10:52:19AM +0800, Morgan Tsai /SiS wrote:
> SiS965(L) vs 966(L)
>
> Identical device ID: LAN, USB
> Different device ID: SATA, Audio(966 has HD Audio, but still reserved 
> AC97)
>
> Although they are funtionally alike, such like register map.
> There is somewhare different value to be filled for bug fix.

That doesn't sound too bad, IMHO. If the only real differences are PCI
IDs of some devices and small changes in some registers, then the 966(L)
code could easily be adapted to also work with 965(L), correct?

Adding more PCI IDs is trivial and we can do that without datasheet
access I think, but the "different value to be filled for bug fix"
could be a problem if it's not documented publically...

Is there some errata sheet we can look at and/or do you know how to fix
the 966(L) code in svn to make it work for 965(L), too?


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org




From bari at onelabs.com  Fri Nov  9 15:40:45 2007
From: bari at onelabs.com (bari)
Date: Fri, 09 Nov 2007 08:40:45 -0600
Subject: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700
 +VT8237RChipset), PC2500E
In-Reply-To: <001501c822c2$3e7f5070$0200a8c0@sis.com.tw>
References: <516173.21801.qm@web54403.mail.yahoo.com>
	<47322166.1070908@gmail.com> <473236E3.7000603@onelabs.com>
	<20071107222126.GB15728@greenwood>
	<000601c821b2$6241e4c0$0200a8c0@sis.com.tw>
	<20071108181040.GB8607@greenwood>
	<001501c822c2$3e7f5070$0200a8c0@sis.com.tw>
Message-ID: <4734716D.1010808@onelabs.com>

I have programming guides and older boards, but aren't the 965 and 964 
getting old?

How about focusing on new boards with the 968?
For example: 
http://www.foxconnchannel.com/product/Motherboards/detail_spec.aspx?ID=en-us0000336
AM2 + 761GX + 968

-Bari

Morgan Tsai /SiS wrote:
> Dear Uwe,
> 
> Sorry for there is no errata sheet. Maybe I can add more PCI IDs
> for our chipset first. I can provide some recommend setting written
> at internal document, if needed.
> 
> 
> 
> Morgan
> 
> 
> ----- Original Message ----- From: "Uwe Hermann" <uwe at hermann-uwe.de>
> To: "Morgan Tsai /SiS" <my_tsai at sis.com>
> Cc: "bari" <bari at onelabs.com>; "Corey Osgood" <corey.osgood at gmail.com>; 
> <linuxbios at linuxbios.org>
> Sent: Friday, November 09, 2007 2:10 AM
> Subject: Re: [LinuxBIOS] Walmart/Everex GPC TC2502 (VIA CN700 
> +VT8237RChipset), PC2500E
> 
> Hi Morgan!
> 
> On Thu, Nov 08, 2007 at 10:52:19AM +0800, Morgan Tsai /SiS wrote:
>> SiS965(L) vs 966(L)
>>
>> Identical device ID: LAN, USB
>> Different device ID: SATA, Audio(966 has HD Audio, but still reserved 
>> AC97)
>>
>> Although they are funtionally alike, such like register map.
>> There is somewhare different value to be filled for bug fix.
> 
> That doesn't sound too bad, IMHO. If the only real differences are PCI
> IDs of some devices and small changes in some registers, then the 966(L)
> code could easily be adapted to also work with 965(L), correct?
> 
> Adding more PCI IDs is trivial and we can do that without datasheet
> access I think, but the "different value to be filled for bug fix"
> could be a problem if it's not documented publically...
> 
> Is there some errata sheet we can look at and/or do you know how to fix
> the 966(L) code in svn to make it work for 965(L), too?
> 
> 
> Thanks, Uwe.




From jadisse at gmail.com  Fri Nov  9 17:25:27 2007
From: jadisse at gmail.com (Edvaldo Artmann de Oliveira)
Date: Fri, 9 Nov 2007 14:25:27 -0200
Subject: [LinuxBIOS] M2N-E sli is supported?
Message-ID: <ad629b3a0711090825x53d0cc3ao845d5279c078e3f1@mail.gmail.com>

The Asus M2N-E SLI is supported by Linux Bios?

Thanks.

I?m a Brazilian and my english is bad. Sorry.
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From jordan.crouse at amd.com  Fri Nov  9 19:46:17 2007
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 9 Nov 2007 11:46:17 -0700
Subject: [LinuxBIOS] [BUILDROM] Add support for the AMD SimNow (TM) simulator
Message-ID: <20071109184617.GF15628@cosmic.amd.com>

By popular request, this is a patch to buildrom adding support for
the AMD SimNow simulator.  Basically, it patches LinuxBIOS to work
around a few SimNow related quirks that are currently in the 
public version of SimNow.  The quirks themselves have been reported,
and hopefully will be fixed in future releases.

What is SimNow, and why does it rock, you might ask?  SimNow (TM) is
a processor simulator that we have developed at AMD.  Its a great way
to simulate the processor / chipset boot process and develop LinuxBIOS
and payloads, because it features an integrated debugger, and its easy
to fix when you brick the thing (just hit reset).  There is a public 
version here:

http://developer.amd.com/simnow.jsp

For the more commercial customers out there, there is also a NDA 
version that has support for more processors (contact your friendly
AMD representative for more information).  I'll put this information
on the wiki as well, for posterity.

Myles and other SimNow users - let me know if this works.

Thanks,
Jordan



-------------- next part --------------
[BUILDROM] Add support for the AMD SimNow (TM) simulator

Add a build option and a patch against LinuxBIOS to allow the 
Serengeti-Cheetah platform to come up on its emulated self in 
the SimNow simulator.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>

Index: buildrom-devel/config/platforms/Config.in
===================================================================
--- buildrom-devel.orig/config/platforms/Config.in
+++ buildrom-devel/config/platforms/Config.in
@@ -81,4 +81,13 @@ config PLATFORM_SERENGETI_CHEETAH
        depends VENDOR_AMD
        select PLATFORM
 endchoice
+
+config SIMNOW
+	bool "Build for the AMD SimNow (TM) emulator"
+	depends PLATFORM_SERENGETI_CHEETAH
+	default n
+	help
+	  Say 'y' here to patch the build to work on an
+	  emulated platform in the AMD SimNow (TM) simulator
+
 endmenu
Index: buildrom-devel/packages/linuxbios/generic-linuxbios.mk
===================================================================
--- buildrom-devel.orig/packages/linuxbios/generic-linuxbios.mk
+++ buildrom-devel/packages/linuxbios/generic-linuxbios.mk
@@ -21,6 +21,10 @@ endif
 
 LINUXBIOS_PATCHES += $(PACKAGE_DIR)/linuxbios/patches/s-c-buildrom-payload.patch
 
+ifeq ($(CONFIG_SIMNOW),y)
+LINUXBIOS_PATCHES += $(PACKAGE_DIR)/linuxbios/patches/simnow.patch
+endif
+
 include $(PACKAGE_DIR)/linuxbios/linuxbios.inc
 
 $(SOURCE_DIR)/$(LINUXBIOS_TARBALL): 
Index: buildrom-devel/packages/linuxbios/patches/simnow.patch
===================================================================
--- /dev/null
+++ buildrom-devel/packages/linuxbios/patches/simnow.patch
@@ -0,0 +1,59 @@
+Index: svn/src/northbridge/amd/amdk8/raminit_f_dqs.c
+===================================================================
+--- svn.orig/src/northbridge/amd/amdk8/raminit_f_dqs.c
++++ svn/src/northbridge/amd/amdk8/raminit_f_dqs.c
+@@ -1987,6 +1987,16 @@ static inline void train_ram_on_node(uns
+ 	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ 	wait_till_sysinfo_in_ram(); // use pci to get it
+ 
++	/* In SimNow, when we get to this point, CAR is disabled, so
++	 * our stack pointer points to never-never land, andjust it.
++	 */
++
++	__asm__ volatile (
++		"subl   %0, %%ebp\n\t"
++		"subl   %0, %%esp\n\t"
++		::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
++	);
++
+ 	if(sysinfox->mem_trained[nodeid] == 0x80) {
+ 	#if 0
+ 		sysinfo->tom_k = sysinfox->tom_k;
+Index: svn/src/mainboard/amd/serengeti_cheetah/Options.lb
+===================================================================
+--- svn.orig/src/mainboard/amd/serengeti_cheetah/Options.lb
++++ svn/src/mainboard/amd/serengeti_cheetah/Options.lb
+@@ -218,7 +218,7 @@ default CONFIG_USE_INIT=0
+ ##
+ ## for rev F training on AP purpose
+ ##
+-default CONFIG_AP_CODE_IN_CAR=1
++default CONFIG_AP_CODE_IN_CAR=0
+ default MEM_TRAIN_SEQ=1
+ default WAIT_BEFORE_CPUS_INIT=1
+ 
+Index: svn/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
+===================================================================
+--- svn.orig/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
++++ svn/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
+@@ -338,16 +338,18 @@ void real_main(unsigned long bist, unsig
+         }
+ #endif
+ 
+-#if 1
+ 	needs_reset = optimize_link_coherent_ht();
++#if 0
++	/* On SimNow, this causes issues - remove it for now */
+ 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
++#endif
+ 
+         // fidvid change will issue one LDTSTOP and the HT change will be effective too
+         if (needs_reset) {
+                 print_info("ht reset -\r\n");
+                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
+         }
+-#endif
++
+ 	allow_all_aps_stop(bsp_apicid);
+ 
+         //It's the time to set ctrl in sysinfo now;

From coquelicot408 at gmail.com  Fri Nov  9 19:52:24 2007
From: coquelicot408 at gmail.com (Coquelicot)
Date: Fri, 9 Nov 2007 19:52:24 +0100
Subject: [LinuxBIOS] Which svn revision works with VIA EPIA M-II?
Message-ID: <524ae2b70711091052k5dc07987s55e910c2fa09d7e6@mail.gmail.com>

Hi guys,

I finally have spare ROM chips to play with and I am ready to put
LinuxBIOS on them - I have problems with compiling the beast, however.
I have checkied out the latest revision from SVN and here's what I'm
getting when trying to compile:



--------------- CUT --------------------

gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T
/home/luke/src/carpc-project/LinuxBIOSv2/src/config/linuxbios_ram.ld
linuxbios_ram.o
nm -n linuxbios_ram | sort > linuxbios_ram.map
objcopy --gap-fill 0xff -O binary linuxbios_ram linuxbios_ram.bin
gcc -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32
-DENDIAN=0 /home/luke/src/carpc-project/LinuxBIOSv2/util/nrv2b/nrv2b.c
-o nrv2b
./nrv2b e linuxbios_ram.bin linuxbios_ram.nrv2b
input/output = 64748/29627 = 2.185
cp linuxbios_ram.nrv2b linuxbios_ram.rom
echo '/*ldoptions*/' > ldscript.ld; cat ldoptions >> ldscript.ld ; for
file in  /home/luke/src/carpc-project/LinuxBIOSv2/src/arch/i386/init/ldscript_fallback.lb
/home/luke/src/carpc-project/LinuxBIOSv2/src//cpu/x86/16bit/entry16.lds
/home/luke/src/carpc-project/LinuxBIOSv2/src//cpu/x86/32bit/entry32.lds
/home/luke/src/carpc-project/LinuxBIOSv2/src//cpu/x86/16bit/reset16.lds
/home/luke/src/carpc-project/LinuxBIOSv2/src//arch/i386/lib/id.lds
/home/luke/src/carpc-project/LinuxBIOSv2/src//arch/i386/lib/failover.lds
; do echo /\* $file \*/ >> ldscript.ld; cat $file >> ldscript.ld ;
done
gcc -m32 -nostdlib -nostartfiles -static -o linuxbios -T ldscript.ld crt0.o
/usr/bin/ld: warning: dot moved backwards before `.reset'
/usr/bin/ld: warning: dot moved backwards before `.id'
/usr/bin/ld: warning: dot moved backwards before `.id'
/usr/bin/ld: warning: dot moved backwards before `.id'
/usr/bin/ld: section .id [00000000ffffffd9 -> 00000000ffffffef]
overlaps section .rom [00000000ffffb3bf -> 000000010000192f]
/usr/bin/ld: linuxbios: section .id lma 0xffffffd9 overlaps previous sections
collect2: ld returned 1 exit status
make[1]: *** [linuxbios] Error 1
make[1]: Leaving directory
`/home/luke/src/carpc-project/LinuxBIOSv2/targets/via/epia-m/epia-m/fallback'
make: *** [fallback/linuxbios.rom] Error 1

--------------- CUT --------------------

Here's my Config.lb:


--------------- CUT --------------------

# Sample config file for EPIA-M
# This will make a target directory of ./epia-m

target epia-m

mainboard via/epia-m

option  MAXIMUM_CONSOLE_LOGLEVEL=8
option  DEFAULT_CONSOLE_LOGLEVEL=8
option  CONFIG_CONSOLE_SERIAL8250=1

option ROM_SIZE=256*1024
option HAVE_OPTION_TABLE=1
option CONFIG_ROM_PAYLOAD=1
option HAVE_FALLBACK_BOOT=1

###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=0x18000

## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00004000

###
### Compute the start location and size size of
### The linuxBIOS bootloader.
###

#
# EPIA-M
#
romimage "normal"
        option USE_FALLBACK_IMAGE=0
        option ROM_IMAGE_SIZE=0xc000
        option ROM_SECTION_OFFSET=0x10000
        option ROM_SECTION_SIZE=0x18000
        option LINUXBIOS_EXTRA_VERSION=".0-Normal"
        payload $(HOME)/src/carpc-project/filo-0.5/filo.elf
end

romimage "fallback"
        option USE_FALLBACK_IMAGE=1
        option ROM_IMAGE_SIZE=0xc000
        option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
        payload $(HOME)/src/carpc-project/filo-0.5/filo.elf
end

#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
buildrom ./linuxbios.rom ROM_SIZE "fallback"


--------------- CUT --------------------

I have commented out the normal build because I want to prepend
original VGA BIOS from the board to LinuxBIOS and I guess the fallback
one is the right one to use (at least according to LinuxBIOS
documentation (documentation/HOWTO/EPIA-M-howto). This file also
states how to get the VGA bios:

dd if=/dev/mem of=/video.bios.bin \
                   bs=1 count=65536 skip=790528

while Confirmed working SVN revisions at

  http://www.linuxbios.org/index.php/Confirmed_working_svn_revisions

says something different:

dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12

(I have checked that generated files differ)

Big thanks,


-- 
Coquelicot



From myles at pel.cs.byu.edu  Fri Nov  9 20:46:41 2007
From: myles at pel.cs.byu.edu (Myles Watson)
Date: Fri, 9 Nov 2007 12:46:41 -0700
Subject: [LinuxBIOS] [BUILDROM] Add support for the AMD SimNow (TM)
	simulator
In-Reply-To: <20071109184617.GF15628@cosmic.amd.com>
References: <20071109184617.GF15628@cosmic.amd.com>
Message-ID: <2831fecf0711091146i6f7bdc9bmb19f1ef69d3b7e6e@mail.gmail.com>

On 11/9/07, Jordan Crouse <jordan.crouse at amd.com> wrote:
> By popular request, this is a patch to buildrom adding support for
> the AMD SimNow simulator.  Basically, it patches LinuxBIOS to work
> around a few SimNow related quirks that are currently in the
> public version of SimNow.  The quirks themselves have been reported,
> and hopefully will be fixed in future releases.
>
> What is SimNow, and why does it rock, you might ask?  SimNow (TM) is
> a processor simulator that we have developed at AMD.  Its a great way
> to simulate the processor / chipset boot process and develop LinuxBIOS
> and payloads, because it features an integrated debugger, and its easy
> to fix when you brick the thing (just hit reset).  There is a public
> version here:
>
> http://developer.amd.com/simnow.jsp
>
> For the more commercial customers out there, there is also a NDA
> version that has support for more processors (contact your friendly
> AMD representative for more information).  I'll put this information
> on the wiki as well, for posterity.
>
> Myles and other SimNow users - let me know if this works.

It doesn't work for me yet.
1. It still resets (I comment out the actual soft reset, not the
needs_reset calculation when I do it)
2. You modify generic-linuxbios.mk instead of a specific one for the
target (see my earlier patch)
3.  I'd like it if it depended on either serengeti-cheetah config
option (also in the earlier patch)

I also commented inline with the patch if it's more clear.

I haven't run into the other issues (beside the reset), so I don't
know how to test them.

Thanks,
Myles

> Thanks,
> Jordan
>
>
>
>
> [BUILDROM] Add support for the AMD SimNow (TM) simulator
>
> Add a build option and a patch against LinuxBIOS to allow the
> Serengeti-Cheetah platform to come up on its emulated self in
> the SimNow simulator.
>
> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
>
> Index: buildrom-devel/config/platforms/Config.in
> ===================================================================
> --- buildrom-devel.orig/config/platforms/Config.in
> +++ buildrom-devel/config/platforms/Config.in
> @@ -81,4 +81,13 @@ config PLATFORM_SERENGETI_CHEETAH
>         depends VENDOR_AMD
>         select PLATFORM
>  endchoice
> +
> +config SIMNOW
> +       bool "Build for the AMD SimNow (TM) emulator"
> +       depends PLATFORM_SERENGETI_CHEETAH

How about:
+       depends PLATFORM_SERENGETI_CHEETAH | PLATFORM_SERENGETI_CHEETAH_64
To let mine use the same option

> +       default n
> +       help
> +         Say 'y' here to patch the build to work on an
> +         emulated platform in the AMD SimNow (TM) simulator
> +
>  endmenu
> Index: buildrom-devel/packages/linuxbios/generic-linuxbios.mk

Should modify specific linuxbios.mk file

===================================================================
> --- buildrom-devel.orig/packages/linuxbios/generic-linuxbios.mk
> +++ buildrom-devel/packages/linuxbios/generic-linuxbios.mk
> @@ -21,6 +21,10 @@ endif
>
>  LINUXBIOS_PATCHES += $(PACKAGE_DIR)/linuxbios/patches/s-c-buildrom-payload.patch
>
> +ifeq ($(CONFIG_SIMNOW),y)
> +LINUXBIOS_PATCHES += $(PACKAGE_DIR)/linuxbios/patches/simnow.patch
> +endif
> +
>  include $(PACKAGE_DIR)/linuxbios/linuxbios.inc
>
>  $(SOURCE_DIR)/$(LINUXBIOS_TARBALL):
> Index: buildrom-devel/packages/linuxbios/patches/simnow.patch
> ===================================================================
> --- /dev/null
> +++ buildrom-devel/packages/linuxbios/patches/simnow.patch
> @@ -0,0 +1,59 @@
> +Index: svn/src/northbridge/amd/amdk8/raminit_f_dqs.c
> +===================================================================
> +--- svn.orig/src/northbridge/amd/amdk8/raminit_f_dqs.c
> ++++ svn/src/northbridge/amd/amdk8/raminit_f_dqs.c
> +@@ -1987,6 +1987,16 @@ static inline void train_ram_on_node(uns
> +       struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
> +       wait_till_sysinfo_in_ram(); // use pci to get it
> +
> ++      /* In SimNow, when we get to this point, CAR is disabled, so
> ++       * our stack pointer points to never-never land, andjust it.
> ++       */
> ++
> ++      __asm__ volatile (
> ++              "subl   %0, %%ebp\n\t"
> ++              "subl   %0, %%esp\n\t"
> ++              ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
> ++      );
> ++
> +       if(sysinfox->mem_trained[nodeid] == 0x80) {
> +       #if 0
> +               sysinfo->tom_k = sysinfox->tom_k;
> +Index: svn/src/mainboard/amd/serengeti_cheetah/Options.lb
> +===================================================================
> +--- svn.orig/src/mainboard/amd/serengeti_cheetah/Options.lb
> ++++ svn/src/mainboard/amd/serengeti_cheetah/Options.lb
> +@@ -218,7 +218,7 @@ default CONFIG_USE_INIT=0
> + ##
> + ## for rev F training on AP purpose
> + ##
> +-default CONFIG_AP_CODE_IN_CAR=1
> ++default CONFIG_AP_CODE_IN_CAR=0
> + default MEM_TRAIN_SEQ=1
> + default WAIT_BEFORE_CPUS_INIT=1
> +
> +Index: svn/src/mainb