[LinuxBIOS] #87: flashrom issues on m57sli-s4
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Tue Nov 13 02:27:21 CET 2007
On 12.11.2007 22:45, Harald Gutmann wrote:
> Am Montag, 12. November 2007 22:41:05 schrieb Harald Gutmann:
>
>>> To be able to autodetect presence of serial flash, I'd like full
>>> superiotool output for
>>> * board with parallel flash
>>> * board with serial flash
>>>
>> here is the output form superiotool for a board with serial flash.
>> flashrom under lb fails on detecting the SPI part. (sry, but i don't know
>> the detailed error message any more.)
>>
> sry, but i hit the wron button, so i attach the necessary informations here.
>
Thanks!
Found ITE IT8716F (id=0x8716, rev=0x0) at 0x2e
Register dump:
idx 07 20 21 22 23 24 2b
-val 01 0a
+val 0a 87 16 00 11 1a 00
def NA 87 16 01 00 00 00
23: Clock Selection
24: Software Suspend and Flash
LDN 0x00
idx 30 60 61 70 74 f0 f1
-val 00 00
+val 01 03 f0 06 02 00 80
def 00 03 f0 06 02 00 00
30: FDC Enable
f1: FDC Special Config 2
LDN 0x02
idx 30 60 61 70 f0 f1 f2 f3
-val 02 f8 03
+val 00 00 00 00 00 50 00 7f
def 00 02 f8 03 00 50 00 7f
60+61: Serial Port 2 Base Addr
70: Serial Port 2 IRQ
LDN 0x03
idx 30 60 61 62 63 70 74 f0
-val 00 07 78
+val 01 03 78 00 00 07 04 08
def 00 03 78 07 78 07 03 03
30: Parallel Port Enable
62+63: Parallel Port Secondary Base Addr
LDN 0x04
idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6
-val 02 30 09
+val 01 02 90 00 00 00 80 00 0a 00 81 00 1d
def 00 02 90 02 30 09 00 00 00 00 00 NA NA
62+63: PME Direct Access Base Addr
70: Environment Controller IRQ
LDN 0x05
idx 30 60 61 62 63 70 71 f0
-val 48
+val 01 00 60 00 64 01 02 68
def 01 00 60 00 64 01 02 00
f0: KBC Special Config
LDN 0x06
idx 30 70 71 f0
-val 01 0c
+val 00 00 02 00
def 00 0c 02 00
30: KBC Mouse Enable
70: KBC Mouse IRQ
LDN 0x07
idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd
-val 00 00 01 00 00 00
+val 00 43 20 00 81 00 1f 00 00 08 00 08 20 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00
def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00
64+65: Serial Flash Base Addr
71: Watch Dog Timer
c9: Simple I/O Set 2
f0+f1: SMI Control
We have to change
* NOLDN idx 0x24 (Flash)
* LDN 0x07 idx 0x64+0x65 (Flash), 0xc9 (Simple I/O)
The rest of the differences is either "don't care" at the moment or
changing is actively harmful.
If we ever decide to support automatic fan control and stuff like that,
we have to revisit LDN 0x04.
If we ever decide to NOT support EPP/ECP parallel port modes, we have to
revisit LDN 0x03.
Regards,
Carl-Daniel
Try this patch:
Autodetect presence of serial flash and set up the board accordingly.
This enables us to have only one configuration and one set of code for
all revisions of the Gigabyte GA-M57SLI-S2.
Remaining issues: Fan/environment control
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
---
Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2955)
+++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie)
@@ -310,7 +310,7 @@
# SIO pin set 1 input mode
#irq 0xc8 = 0x0
# SIO pin set 2 mixed input/output mode
- irq 0xc9 = 0x0
+ irq 0xc9 = 0x40
# SIO pin set 4 input mode
#irq 0xcb = 0x0
# Generate SMI# on EC IRQ
Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c (Revision 2955)
+++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c (Arbeitskopie)
@@ -93,6 +93,7 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
@@ -265,13 +266,27 @@
int needs_reset = 0;
unsigned bsp_apicid = 0;
+ uint8_t tmp = 0;
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pnp_enter_ext_func_mode(SERIAL_DEV);
- pnp_write_config(SERIAL_DEV, 0x23, 1);
+ /* The following line will set CLKIN to 24 MHz */
+ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 1);
+ tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
+ /* Is serial flash enabled? Then enable writing to serial flash. */
+ if (tmp & 0x0e) {
+ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
+ pnp_set_logical_device(GPIO_DEV);
+ /* Set Serial Flash interface to 0x0820 */
+ pnp_write_config(GPIO_DEV, 0x64, 0x08);
+ pnp_write_config(GPIO_DEV, 0x65, 0x20);
+ /* We can get away with not resetting the logical device because
+ * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that.
+ */
+ }
it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
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