[LinuxBIOS] Setup of Memory Controller

Arne Georg Gleditsch argggh at dolphinics.no
Tue Nov 20 10:52:55 CET 2007

Linux Bios <linux.bios at yahoo.com> writes:
> Thanks Ron, I'm from the Air Force Institute of Technology in Ohio. I admit I
> am very simple minded. I am unable to see where I would change the routing in
> early setup. So far I have found myself in
> src >> northbridge >> amd >> amdk8 >> raminit.c
> This appears to be where northbridge is setup and where I would route memory
> requests to my memory conrtoller. However it looks to be coded by node_id. My
> FPGA would not be recognized necessarily as a node because its not an opteron.
> right?

That depends on whether the DRC is seen as a coherent device or a
non-coherent one.  In the first case you would map it as DRAM (toward
a node id), in the second as MMIO (toward a node:link).  I'm not
familiar with the DRC -- what kind of PCI Id is it assigned to?  I'm
not sure you can bypass the Opteron memory controller (in terms of
cache controller etc) completely, but not using the Opteron-connected
DRAM at all shouldn't be too hard.  Not sure how it would react to
having all of its memory mapped as MMIO, though...


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