[LinuxBIOS] Setup of Memory Controller

[Arne Georg Gleditsch]

Nate wrote:
> As it is in the Tyan motherboard now, the FPGA is seen as a non-coherent
> HT cave device.
> 
>>I'm not familiar with the DRC -- what kind of PCI Id is it assigned to?
> 
> The "supported" intent of the DRC system is to use the FPGA as an
> application accelerator. Lspci output looks like this:
> 
> 0000:40:01.0 Co-processor: DRC Computer Corp.: Unknown device 4200 (rev a1)
> 0000:40:01.1 Co-processor: DRC Computer Corp.: Unknown device 4201
> 0000:40:01.2 Co-processor: DRC Computer Corp.: Unknown device 4202
> 0000:40:01.3 Co-processor: DRC Computer Corp.: Unknown device 4203

Yeah, definitely non-coherent.

> Hmm... Your right. I dont want to use the Opteron connected DRAM and Im
> not looking to replace all of northbridge. I had thought about mapping
> all addresses to memory-mapped IO of the FPGA as the AMD docs say that
> "An address that maps to both DRAM and memory-mapped I/O will be routed
> to MMIO".  An avenue definitely worth testing. However I would rather
> the system see my memory controller as the gate to the sytems DRAM.
> 
> Im currently looking at the resourcemap.c for the tyan s2891 and looking
> at simply changing the hex value for the DRAM Limit and Base address for
> offset 44 and 40 to point to node 1 rather than node 0 and cross my
> fingers.

By all means try it, but I'd be more than a little surprised if it
works.  As long as the DRC is a non-coherent device, there's no "node 1"
on your system -- that's a coherent term.  I believe your best bet is to
populate one of the MMIO mapping register pairs with the relevant range
and point that towards the link where the DRC resides.  Depending on how
the DRC is put together, you might also need to configure its BAR to
make it respond to the same address range.  Additionally, you'll
probably need to adjust or short-circuit the PCI enumeration pass later
on, to make sure no overlapping MMIO mappings are defined and that the
DRC BAR is not reconfigured.  (Actually, you might need to set up more
than one MMIO map toward the DRC link, since you probably want to leave
a gap for your video memory and friends.)

Ok, perhaps it doesn't sound quite hassle free, but I still think it
should be fairly straight forward.  Good luck anyway, make sure to tell
us how it works out. :)

-- 
							Arne.