[LinuxBIOS] alix1c for v3 update

Corey Osgood corey.osgood at gmail.com
Tue Nov 27 18:17:57 CET 2007


Carl-Daniel Hailfinger wrote:
> On 27.11.2007 17:45, Corey Osgood wrote:
>   
>> ron minnich wrote:
>>   
>>     
>>> On Nov 27, 2007 8:24 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
>>>
>>>   
>>>     
>>>       
>>>>> +     [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
>>>>>
>>>>>       
>>>>>         
>>>>>           
>>>> This looks like it's wrong, a normal DDR400 dimm is 0x50 or so.
>>>>
>>>>     
>>>>       
>>>>         
>>>>> +     [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
>>>>>
>>>>>       
>>>>>         
>>>>>           
>>>> 0x20 for an unbuffered dimm, 0x26 for registered.
>>>>     
>>>>       
>>>>         
>>> So I'm going to ask a favor. I am going from the data sheets and could
>>> not find this info. Can you look and tell me? I got lost in the
>>> numbers ...
>>>   
>>>     
>>>       
>> I cheated ;) Here's a micron datasheet for a DDR400 CL3 Dimm:
>> http://download.micron.com/pdf/datasheets/modules/ddr/DDA9C16_32_64x72AG.pdf
>>
>> And what should be known as the best idiot's guide to SPD out there:
>> http://www.simmtester.com/page/news/showpubnews.asp?num=101
>>
>> I have the JEDEC datasheet on this, but I have so damn many JEDEC
>> datasheets I simply can't figure out which one it is. The
>> "SPD_ACCEPTABLE_CAS_LATENCIES" also should be 0x50 (5ns).
>>   
>>     
>
> Can you add these links to the wiki, probably to a page about SPD or RAM?
>
> Regards,
> Carl-Daniel

I don't have wiki access (care to help with that Ron?). The second one's
already in the developer manual, but there are corresponding guides for
sdram, ddr2, and ddr3 which should be added, along with more datasheet
links. I'll also add links to the JEDEC docs if I can find them, I think
everyone could use them for reference.

-Corey




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