[LinuxBIOS] [PATCH v3] v2, v3: Bug? in CAR setup with CacheSize!={4k, 8k, 16k}

Marc Jones marc.jones at amd.com
Thu Nov 29 00:50:15 CET 2007

Carl-Daniel Hailfinger wrote:
> On 28.11.2007 23:52, Marc Jones wrote:
>> Carl-Daniel Hailfinger wrote:
>>> Marc?
>>> This has been sitting in my tree for a while now.
>>> On 16.11.2007 16:00, Carl-Daniel Hailfinger wrote:
>>>> Hi,
>>>> v2 and v3 have almost identical CAR setup code with identical bugs for
>>>> CAR sizes != {4k,8k,16k}. In v3, the erroneous code paths are not
>>>> triggered and the bug is latent, but we have at a few boards in v2
>>>> which
>>>> trigger these bugs, resulting in holes and/or smaller size of the
>>>> CAR area.
>> Sorry, I have been very busy and I have been putting this off.
>> I think you are correct that CAR expects power of 2 cache sizes. How
>> about just error if the size isn't power of 2 between 4K and 64K? If
>> you wanted to support non power of 2 you should round up otherwise you
>> might write off the end.
> OK, will prepare an updated patch.
> What about the bugs which cause 32k CAR to end up as 16k and 64k CAR to
> have a hole between 16k and 32k?

I am not very familiar with the code but it looks like the size is 
growing from 0xCFFFF down to 0xC0000. I don't see a gap. The movl 
%eax, %edx make the entire MSR 0x0606060606060606 which would be 32K and 
then setting that in both 0x269 and 0x268 would be 64K. But I could be 
misunderstanding the code.


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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