[LinuxBIOS] hdama compile error

Marc Jones marc.jones at amd.com
Wed Oct 3 00:28:48 CEST 2007



kevint wrote:
> Hello,
> 
> I am trying to build an hdama target with LinuxBIOSv2 and came across 
> this compile error:
> 
> [...]
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %ecx
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %edx
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %esi
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %edi
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %ebp
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %esp
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %edx:%eax
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47: warning: 
> used: %dx:%ax
> coherent_ht.c:1752.25: coherent_ht.c:1836.41: auto.c:193.47:
> too few registers
> make[1]: *** [auto.inc] Error 1
> make[1]: Leaving directory 
> `/tmp/LinuxBIOSv2/targets/arima/hdama/hdama/normal'
> make: *** [normal/linuxbios.rom] Error 1
> 
> I noticed this was mentioned in a 2004 mailing list post by Eric 
> Biederman.  The final message, from YhLu, included what appeared to be 
> the fix.  I looked at coherent_ht.c and it looks like it was applied.
> 
> Also, Arima has a new revision to the hdama board that changes the pci 
> layout slightly.  The newest revision is:
> 
> (lspci -n)
> 
> 00:18.0 Class 0600: 1022:1100
> 00:18.1 Class 0600: 1022:1101
> 00:18.2 Class 0600: 1022:1102
> 00:18.3 Class 0600: 1022:1103
> 00:19.0 Class 0600: 1022:1100
> 00:19.1 Class 0600: 1022:1101
> 00:19.2 Class 0600: 1022:1102
> 00:19.3 Class 0600: 1022:1103
> 01:01.0 Class 0604: 1022:7450 (rev 12)
> 01:01.1 Class 0800: 1022:7451 (rev 01)
> 01:02.0 Class 0604: 1022:7450 (rev 12)
> 01:02.1 Class 0800: 1022:7451 (rev 01)
> 01:03.0 Class 0604: 1022:7460 (rev 07)
> 01:04.0 Class 0601: 1022:7468 (rev 05)
> 01:04.1 Class 0101: 1022:7469 (rev 03)
> 01:04.2 Class 0c05: 1022:746a (rev 02)
> 01:04.3 Class 0680: 1022:746b (rev 05)
> 01:04.6 Class 0703: 1022:746e (rev 03)
> 02:03.0 Class 0200: 14e4:1648 (rev 10)
> 02:03.1 Class 0200: 14e4:1648 (rev 10)
> 03:01.0 Class 0280: 14c1:8043 (rev 04)
> 04:00.0 Class 0c03: 1022:7464 (rev 0b)
> 04:00.1 Class 0c03: 1022:7464 (rev 0b)
> 04:06.0 Class 0300: 1002:4752 (rev 27)
> 04:07.0 Class 0180: 1095:3114 (rev 02)
> 
> The last line is the SATA controller, which is optional on the new 
> board.  The broadcom chips are now on 2:03.0/1 instead of 2:03.0/2:04.0.
> 
> The previous board revisions had the following pci layout:
> 
> 00:18.0 Class 0600: 1022:1100
> 00:18.1 Class 0600: 1022:1101
> 00:18.2 Class 0600: 1022:1102
> 00:18.3 Class 0600: 1022:1103
> 00:19.0 Class 0600: 1022:1100
> 00:19.1 Class 0600: 1022:1101
> 00:19.2 Class 0600: 1022:1102
> 00:19.3 Class 0600: 1022:1103
> 01:01.0 Class 0604: 1022:7450 (rev 12)
> 01:01.1 Class 0800: 1022:7451 (rev 01)
> 01:02.0 Class 0604: 1022:7450 (rev 12)
> 01:02.1 Class 0800: 1022:7451 (rev 01)
> 01:03.0 Class 0604: 1022:7460 (rev 07)
> 01:04.0 Class 0601: 1022:7468 (rev 05)
> 01:04.1 Class 0101: 1022:7469 (rev 03)
> 01:04.2 Class 0c05: 1022:746a (rev 02)
> 01:04.3 Class 0000: 1022:746b (rev 05)
> 02:03.0 Class 0200: 14e4:16a6 (rev 02)
> 02:04.0 Class 0200: 14e4:16a6 (rev 02)
> 03:01.0 Class 0280: 14c1:8043 (rev 04)
> 04:00.0 Class 0c03: 1022:7464 (rev 0b)
> 04:00.1 Class 0c03: 1022:7464 (rev 0b)
> 04:00.2 Class 0c03: 1022:7463 (rev 02)
> 04:06.0 Class 0300: 1002:4752 (rev 27)
> 
> Will this require a new mainboard target?  I would appreciate any help 
> you can provide!
> 
> Thanks,
> 
> ********************************************
> Kevin Tegtmeier
> HPC-3 Scientific Computing Resources
> Los Alamos National Laboratory
> email:  kevint at lanl dot gov
> ********************************************
> 
> 
> 

Kevin,

I am no expert, but it looks like this platform is still using ROMCC and 
needs to be ported to CAR.

PCI should just work since it is based off of the device ID and not the 
physical location.


Question to others: Shouldn't the abuild be catching this?

Marc


-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors






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