[LinuxBIOS] [PATCH] Initial support for the MSI MS-6178 (i810-based)

popkonserve popkonserve at gmx.de
Sat Sep 1 08:28:54 CEST 2007

>>- the refresh (offset 53h) should be 15,6µs instead of 7,8µs which
>>should only be used for high density rams (>256MB)
> No, 0x20 is correct, bit 5 is the only bit flipped.

oops, sorry, you are right...

>>- CL, SRCD and SRP (offset 53h) are unconfigured. either read them from
>>the spd or configure them by performing read/write tests
> No, they're configured to the slowest and safest possible timings. I
> haven't gotten to optimizing it yet.

yeah, that's what i thought, too. but if you're able to read the values 
from the spd it should be no problem setting them!?

>>page 7:
>>line 473ff
> I'll look into these later, but I suspect x86_enable_cache() does
> something similar.

hmm, no. actually x86_enable_cache() just emits a post code, prints some 
info and calls enable_cache() which is an inline in cache.h which just 
enables L1 cache by flipping a bit in the processor configuration 
register 0 (CR0). that's all.
it should be renamed to enable_L1_cache() to avoid confusion.
the L2 cache can not be enabled in CR0. just take a look at the code and 
you'll see.

More information about the coreboot mailing list