[LinuxBIOS] Epia MII, Compact Flash and device nodes

Peter Stuge peter at stuge.se
Thu Sep 20 13:40:28 CEST 2007

On Thu, Sep 20, 2007 at 09:44:42AM +0300, Markus Tornqvist wrote:
> >> So the driver is broken wrt irq handling?
> >
> >Yeah. It doesn't matter if the Ricoh controller has it's own
> >interrupt and/or if you only ever have either CF or PCMCIA but not
> >both. I don't remember if there's a shared IRQ on the MII.
> Grim.

The ide-cs is bitrotting since there's a new shiny pata_pcmcia.

The new sata/pata code is presumably much better than old ide anyway.

> >pcmcia-cs is deprecated. Only useful for old 2.4 kernels.
> Seems one of the most difficult things in this project of mine
> is knowing what really is deprecated...

Going into embedded means knowing many things. :)

> >> >1. If FILO is to load the kernel from the Ricoh slot #1, the
> >> I'm actually thinking about skipping FILO if possible, so I have
> >> the kernel and and a small-enough initrd as the payload.
> >Not possible.
> I got a different impression on IRC, but this is something to get
> back to.
> >> Have to admit I haven't really checked sizes yet, but the via
> >> spec said the bios is 2/4Mbit, so 4Mbit should fit pretty much...
> >4Mbit == 512kb
> harrumph, yes, in this modern day and age of extreme storage it's
> easy to say du -sk and think "yay kilobits" :P

And this is why I say not possible. Kernel+initramfs doesn't fit in
512kb. (Or has someone managed this now? That would be sweet!)

> Do you know if the SST49LF160C (the 2MB one from the kdrive demo
> video) works on an Epia though the specs say 2/4Mbit?

It does not.

> (I guess this is general theoretics, is there a single mbr-style
> entry point on every flash chip that gets accessed so the size
> doesn't matter :)

Not so unfortunately. There is the matter of the bus that the flash
chip is connected to. The MII uses parallel flash which is basically
connected to an ISA bus. There's only room for 19 address lines on
the 32-pin flash chips so 512kb is the ceiling.

Newer systems connect the boot flash through LPC or SPI, which are
both basically serial buses, and then the limit becomes a matter of
what the serial protocol supports and what the chip on the other side
of the bus supports.

The largest common NOR flash for LPC is currently 16Mbit and the
chipsets already support 16, 32 or 64 Mbit so there's still some
room to grow.

Until LB or EFI really takes off I don't think there will be any
larger flash parts readily available.

> >There were issues when using ide-cs. pata_pcmcia wasn't ready yet.
> >MANY changes especially for ATA/IDE went into 2.6.18 and it took some
> >time to stabilize. I needed to get the board running and went for the
> Then it's only a good thing I'm on 2.6.18 now and nothing stops
> me from using a later one.

Get the latest possible. 2.6.18 is a year old and not so hot. Grab

> >> That's almost the same type of defeat-admission as using a separate
> >> cf-ide adapter, which I'd rather pass up on.
> >These are the cards we are dealt as cutting edge early adopters and
> >developers. We will always get screwed out of something. But we gain
> >other things.
> Indeed this is so, but there is also an old saying "if you beat your
> head to the wall long enough, the wall will eventually give up." ;)

Unless time runs out or the head breaks first. :(


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