From eswierk at arastra.com  Tue Apr  1 01:38:34 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Mon, 31 Mar 2008 16:38:34 -0700
Subject: [coreboot] [PATCH] Disable integrated Intel 3100 devices properly
Message-ID: <e6c711510803311638y2b224697h6b701665d21ebd70@mail.gmail.com>

Setting an integrated southbridge device (like SATA or USB2.0) to
"off" in Config.lb should cause the PCI device not to respond to
configuration requests. The code that takes care of this for the Intel
3100 is in src/southbridge/intel/i3100/i3100.c. Unfortunately I copied
the esb6300 implementation without noticing that it makes no sense at
all on the Intel 3100. The attached patch implements this properly for
the Intel 3100.

--Ed
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From uwe at hermann-uwe.de  Tue Apr  1 02:41:47 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Apr 2008 02:41:47 +0200
Subject: [coreboot] [PATCH] Disable integrated Intel 3100
	devices	properly
In-Reply-To: <e6c711510803311638y2b224697h6b701665d21ebd70@mail.gmail.com>
References: <e6c711510803311638y2b224697h6b701665d21ebd70@mail.gmail.com>
Message-ID: <20080401004147.GA26546@greenwood>

On Mon, Mar 31, 2008 at 04:38:34PM -0700, Ed Swierk wrote:
> Setting an integrated southbridge device (like SATA or USB2.0) to
> "off" in Config.lb should cause the PCI device not to respond to
> configuration requests. The code that takes care of this for the Intel
> 3100 is in src/southbridge/intel/i3100/i3100.c. Unfortunately I copied
> the esb6300 implementation without noticing that it makes no sense at
> all on the Intel 3100. The attached patch implements this properly for
> the Intel 3100.

You forgot the Signed-off-by.


> +	/* Temporarily enable the root complex register block at 0xa0000000 */
> +	lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0));
> +	pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0));
> +	disable = (volatile u32 *) 0xa0003418;
> +	func = PCI_FUNC(dev->path.u.pci.devfn);
> +	switch (PCI_SLOT(dev->path.u.pci.devfn)) {
> +	case 0x1f:
> +		*disable |= (1 << (func == 0x0 ? 14 : func));
> +		break;
> +	case 0x1d:
> +		*disable |= (1 << (func + 8));
> +		break;
> +	case 0x1c:
> +		*disable |= (1 << (func + 16));
> +		break;

This part could use a small comment about what exactly is disabled in
each "case".


Rest of the patch looks good. Is this build-tested and tested on
hardware? If so, I can ack and commit if you resend with a Signed-off-by.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From eswierk at arastra.com  Tue Apr  1 04:01:52 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Mon, 31 Mar 2008 19:01:52 -0700
Subject: [coreboot] [PATCH] Disable integrated Intel 3100 devices
	properly
In-Reply-To: <20080401004147.GA26546@greenwood>
References: <e6c711510803311638y2b224697h6b701665d21ebd70@mail.gmail.com>
	<20080401004147.GA26546@greenwood>
Message-ID: <e6c711510803311901p70538127v51449a2b24b55048@mail.gmail.com>

On Mon, Mar 31, 2008 at 5:41 PM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
>  Rest of the patch looks good. Is this build-tested and tested on
>  hardware? If so, I can ack and commit if you resend with a Signed-off-by.

Yes, I tested it on a Mt. Arvon board.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From svn at coreboot.org  Tue Apr  1 04:37:00 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  1 Apr 2008 04:37:00 +0200
Subject: [coreboot] r3205 - in trunk/coreboot-v2/src/southbridge/intel:
	esb6300 i3100 i82801ca i82801db i82801dbm i82801er
Message-ID: <mailman.1354.1355071292.16123.coreboot@coreboot.org>

Author: eswierk
Date: 2008-04-01 04:36:59 +0200 (Tue, 01 Apr 2008)
New Revision: 3205

Modified:
   trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c
Log:
The early init code of several Intel southbridge chipsets calls
pci_locate_device() to locate the SMBus controller and LPC bridge
devices on the PCI bus. Since these devices are always located at a
fixed PCI bus:device:function, the code can be simplified by
hardcoding the devices.

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c	2008-03-31 21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c	2008-04-01 02:36:59 UTC (rev 3205)
@@ -4,12 +4,8 @@
 
 static void enable_smbus(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(0x8086, 0x25a4), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
-	}
-	uint8_t enable;
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
 	print_spew("SMBus controller enabled\r\n");
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	pci_write_config8(dev, 0x40, 1);
@@ -19,11 +15,6 @@
 	
 	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-	dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("ISA bridge not found\r\n");
-	}
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-03-31 21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-04-01 02:36:59 UTC (rev 3205)
@@ -20,12 +20,7 @@
 
 static void i3100_enable_superio(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
-				       PCI_DEVICE_ID_INTEL_3100_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("LPC bridge not found\r\n");
-	}
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
 
 	/* Enable decoding of I/O locations for SuperIO devices */
 	pci_write_config16(dev, 0x82, 0x340f);
@@ -33,12 +28,7 @@
 
 static void i3100_halt_tco_timer(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
-				       PCI_DEVICE_ID_INTEL_3100_LPC), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("LPC bridge not found\r\n");
-	}
+	device_t dev = PCI_DEV(0, 0x1f, 0);
 
 	/* Temporarily enable the ACPI I/O range at 0x4000 */
 	pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c	2008-03-31 21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c	2008-04-01 02:36:59 UTC (rev 3205)
@@ -24,12 +24,8 @@
 
 static void enable_smbus(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
-				       PCI_DEVICE_ID_INTEL_3100_SMB), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBus controller not found\r\n");
-	}
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
 	print_spew("SMBus controller enabled\r\n");
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	pci_write_config8(dev, 0x40, 1);

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	2008-03-31 21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	2008-04-01 02:36:59 UTC (rev 3205)
@@ -3,12 +3,8 @@
 
 static void enable_smbus(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_SMB), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
-	}
-	
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
 	print_debug("SMBus controller enabled\r\n");
 	/* set smbus iobase */
 	pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c	2008-03-31 21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c	2008-04-01 02:36:59 UTC (rev 3205)
@@ -22,13 +22,10 @@
 
 static void enable_smbus(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
-	}
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
 	print_spew("SMBus controller enabled\r\n");
-	
+
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	/* Set smbus enable */
 	pci_write_config8(dev, 0x40, 1);
@@ -36,19 +33,12 @@
 	pci_write_config8(dev, 0x4, 1);
 	/* SMBALERT_DIS */
 	pci_write_config8(dev, 0x11, 4);
-	
+
 	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-#if 0	// It's unlikely that half the southbridge suddenly vanishes?
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("ISA bridge not found\r\n");
-	}
-#endif
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c	2008-03-31 21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c	2008-04-01 02:36:59 UTC (rev 3205)
@@ -21,12 +21,8 @@
 
 static void enable_smbus(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24c3), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
-	}
-	
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
 	print_debug("SMBus controller enabled\r\n");
 	/* set smbus iobase */
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c	2008-03-31 21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c	2008-04-01 02:36:59 UTC (rev 3205)
@@ -4,13 +4,10 @@
 
 static void enable_smbus(void)
 {
-	device_t dev;
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
-	}
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
 	print_spew("SMBus controller enabled\r\n");
-	
+
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	/* Set smbus enable */
 	pci_write_config8(dev, 0x40, 1);
@@ -18,19 +15,12 @@
 	pci_write_config8(dev, 0x4, 1);
 	/* SMBALERT_DIS */
 	pci_write_config8(dev, 0x11, 4);
-	
+
 	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-#if 0	// It's unlikely that half the southbridge suddenly vanishes?
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("ISA bridge not found\r\n");
-	}
-#endif
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)




From svn at coreboot.org  Tue Apr  1 04:42:52 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  1 Apr 2008 04:42:52 +0200
Subject: [coreboot] r3206 - trunk/coreboot-v2/src/southbridge/intel/i82801db
Message-ID: <mailman.1355.1355071292.16123.coreboot@coreboot.org>

Author: eswierk
Date: 2008-04-01 04:42:52 +0200 (Tue, 01 Apr 2008)
New Revision: 3206

Removed:
   trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb
   trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h
   trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
Log:
Removal of i82801DB (ICH4)

There are no boards that use the i82801DB (ICH4). The code does NOT work.

Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Ed Swierk <eswierk at arastra.com>



Deleted: trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb	2008-04-01 02:36:59 UTC (rev 3205)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb	2008-04-01 02:42:52 UTC (rev 3206)
@@ -1,11 +0,0 @@
-config chip.h
-driver i82801db.o
-driver i82801db_uhci.o
-driver i82801db_lpc.o
-driver i82801db_ide.o
-driver i82801db_ehci.o
-driver i82801db_smbus.o
-driver i82801db_pci.o
-driver i82801db_ac97.o
-object i82801db_watchdog.o
-object i82801db_reset.o

Deleted: trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h	2008-04-01 02:36:59 UTC (rev 3205)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h	2008-04-01 02:42:52 UTC (rev 3206)
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
- 
-#ifndef I82801DB_CHIP_H
-#define I82801DB_CHIP_H
-
-struct southbridge_intel_i82801db_config 
-{
-
-#define ICH5R_GPIO_USE_MASK      0x03
-#define ICH5R_GPIO_USE_DEFAULT   0x00
-#define ICH5R_GPIO_USE_AS_NATIVE 0x01
-#define ICH5R_GPIO_USE_AS_GPIO   0x02
-
-#define ICH5R_GPIO_SEL_MASK      0x0c
-#define ICH5R_GPIO_SEL_DEFAULT   0x00
-#define ICH5R_GPIO_SEL_OUTPUT    0x04
-#define ICH5R_GPIO_SEL_INPUT     0x08
-
-#define ICH5R_GPIO_LVL_MASK      0x30
-#define ICH5R_GPIO_LVL_DEFAULT   0x00
-#define ICH5R_GPIO_LVL_LOW       0x10
-#define ICH5R_GPIO_LVL_HIGH      0x20
-#define ICH5R_GPIO_LVL_BLINK     0x30
-
-#define ICH5R_GPIO_INV_MASK      0xc0
-#define ICH5R_GPIO_INV_DEFAULT   0x00
-#define ICH5R_GPIO_INV_OFF       0x40
-#define ICH5R_GPIO_INV_ON        0x80
-
-	/* GPIO use select */
-	unsigned char gpio[64];
-	unsigned int  pirq_a_d;
-	unsigned int  pirq_e_h;
-	int enable_native_ide;
-};
-extern struct chip_operations southbridge_intel_i82801db_ops;
-
-#endif /* I82801DB_CHIP_H */
-

Deleted: trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c	2008-04-01 02:36:59 UTC (rev 3205)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c	2008-04-01 02:42:52 UTC (rev 3206)
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-//kind of cmos_err for ich5
-#define RTC_FAILED    (1 <<2)
-#define GEN_PMCON_3     0xa4
-static void check_cmos_failed(void) 
-{
-
-                uint8_t byte;
-                byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
-                if( byte & RTC_FAILED){
-//clear bit 1 and bit 2
-                        byte = cmos_read(RTC_BOOT_BYTE);
-                        byte &= 0x0c;
-                        byte |= MAX_REBOOT_CNT << 4;
-                        cmos_write(byte, RTC_BOOT_BYTE);
-                }
-}

Deleted: trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c	2008-04-01 02:36:59 UTC (rev 3205)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c	2008-04-01 02:42:52 UTC (rev 3206)
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801db.h"
-
-void i82801db_enable(device_t dev)
-{
-	device_t lpc_dev;
-	uint16_t word;
-
-	printk_debug("Entering %s\n", __FUNCTION__);
-	/* See if we are behind the i82801db pci bridge 
-	lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
-	*/
-	lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-	if (!lpc_dev) {
-		return;
-	}
-	
-	word = 0x0040;
-	pci_write_config16(lpc_dev, 0xf2, word);
-	/*
-	if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
-		index = dev->path.u.pci.devfn & 7;
-	}
-	else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
-		index = (dev->path.u.pci.devfn & 7) +8;
-	}
-
-	reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
-	reg &= ~(1 << index);
-	if (!dev->enabled) {
-		reg |= (1 << index);
-	}
-	if (reg != reg_old) {
-		printk_debug("Trying to enable device, [0:1f:0] reg 0xf2 <- %04x\n", reg);
-		pci_write_config16(lpc_dev, 0xf2, reg);
-	}
-	*/	
-}
-
-struct chip_operations southbridge_intel_i82801db_ops = {
-	CHIP_NAME("Intel 82801DB Southbridge")
-	.enable_dev = i82801db_enable,
-};

Deleted: trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c	2008-04-01 02:36:59 UTC (rev 3205)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c	2008-04-01 02:42:52 UTC (rev 3206)
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801db.h"
-
-static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
-	/* Write the subsystem vendor and device id */
-	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, 
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = ac97_set_subsystem,
-};
-static struct device_operations ac97_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = 0,
-	.enable           = i82801db_enable,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver ac97_audio_driver __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
-};
-static const struct pci_driver ac97_modem_driver __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
-};

Deleted: trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c	2008-04-01 02:36:59 UTC (rev 3205)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c	2008-04-01 02:42:52 UTC (rev 3206)
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include "i82801db_smbus.h"
-
-#define SMBUS_IO_BASE 0x0f00
-
-static void enable_smbus(void)
-{
-	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
-
-	print_spew("SMBus controller enabled\r\n");
-
-	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
-	/* Set smbus enable */
-	pci_write_config8(dev, 0x40, 1);
-	/* Set smbus iospace enable */
-	pci_write_config8(dev, 0x4, 1);
-	/* SMBALERT_DIS */
-	pci_write_config8(dev, 0x11, 4);
-
-	/* Disable interrupt generation */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-}
-
-static int smbus_read_byte(unsigned device, unsigned address)
-{
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
-{
-	if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
-		return;
-	}
-	
-	print_debug("Unimplemented smbus_write_byte() called.\r\n");
-
-#if 0
-	/* setup transaction */
-	/* disable interrupts */
-	outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
-			SMBUS_IO_BASE + SMBGCTL);
-	/* set the device I'm talking too */
-	outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
-	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-	/* set up for a byte data write */ /* FIXME */
-	outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
-	/* clear any lingering errors, so the transaction will run */
-	/* Do I need to write the bits to a 1 to clear an error? */
-	outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
-
-	/* clear the data word...*/
-	outw(val, SMBUS_IO_BASE + SMBHSTDAT);
-
-	/* start the command */
-	outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
-
-	/* poll for transaction completion */
-	smbus_wait_until_done(SMBUS_IO_BASE);
-#endif	
-	return;
-}
-
-static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, 
-		 unsigned data1, unsigned data2)
-{
-	unsigned char global_control_register;
-	unsigned char global_status_register;
-	unsigned char byte;
-	unsigned char stat;
-	int i;
-
-	/* chear the PM timeout flags, SECOND_TO_STS */
-	outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
-	
-	if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
-		return -2;
-	}
-	
-	/* setup transaction */
-	/* Obtain ownership */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	for(stat=0;(stat&0x40)==0;) {
-	stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-	/* clear the done bit */
-	outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
-	/* disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-	
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-	
-	/* set the command address */
-	outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-	
-	/* set the block length */
-	outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
-	
-	/* try sending out the first byte of data here */
-	byte=(data1>>(0))&0x0ff;
-	outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-	/* issue a block write command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, 
-			SMBUS_IO_BASE + SMBHSTCTL);
-
-	for(i=0;i<length;i++) {
-		
-		/* poll for transaction completion */
-		if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
-			return -3;
-		}
-		
-		/* load the next byte */
-		if(i>3)
-			byte=(data2>>(i%4))&0x0ff;
-		else
-			byte=(data1>>(i))&0x0ff;
-		outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-		
-		/* clear the done bit */
-		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 
-				SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-
-	print_debug("SMBUS Block complete\r\n");
-	return 0;
-}
-




From svn at coreboot.org  Tue Apr  1 04:48:12 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  1 Apr 2008 04:48:12 +0200
Subject: [coreboot] r3207 - trunk/coreboot-v2/src/southbridge/intel/i3100
Message-ID: <mailman.1356.1355071292.16123.coreboot@coreboot.org>

Author: eswierk
Date: 2008-04-01 04:48:12 +0200 (Tue, 01 Apr 2008)
New Revision: 3207

Modified:
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
Log:
Tiny style fix for consistency (trivial).

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Acked-by: Ed Swierk <eswierk at arastra.com>



Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-04-01 02:42:52 UTC (rev 3206)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-04-01 02:48:12 UTC (rev 3207)
@@ -28,7 +28,7 @@
 
 static void i3100_halt_tco_timer(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
 
 	/* Temporarily enable the ACPI I/O range at 0x4000 */
 	pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));




From stepan at coresystems.de  Tue Apr  1 07:12:08 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 01 Apr 2008 07:12:08 +0200
Subject: [coreboot] [PATCH] Hardcode PCI devices in Intel southbridge
 early init code
In-Reply-To: <dd3c80060803311343i4bb938b1s88b04b4bfdacbe8@mail.gmail.com>
References: <e6c711510803310850g21d20f0y172efc8c54f0707@mail.gmail.com>	<20080331131600.krvfjp2agwsowkw0@www.smittys.pointclark.net>	<dd3c80060803311204u4314d19l9325928fa94fb485@mail.gmail.com>	<20080331160459.999kw5gmiokgk4oc@www.smittys.pointclark.net>	<20080331202756.GB6215@greenwood>	<20080331163249.q2jeca3j4kwk8ws4@www.smittys.pointclark.net>	<dd3c80060803311337r78255d50q83185764c024967c@mail.gmail.com>
	<dd3c80060803311343i4bb938b1s88b04b4bfdacbe8@mail.gmail.com>
Message-ID: <47F1C428.1090302@coresystems.de>

Corey Osgood wrote:

>
> Yep, it's the digitallogic/adl855pc. I think it was Ron that said the 
> 855 never worked, but that was a long time ago, and I can't be sure.  
> Perhaps we should just leave it kicking around, and focus on not 
> letting this happen to v3.

I can confirm that code does nothing good. I have a mostly ready 855 
port sitting somewhere that I wrote from flash. I will look into this 
when/if I get the machine again I was originally writing it for.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From darmawan.salihun at gmail.com  Tue Apr  1 08:40:25 2008
From: darmawan.salihun at gmail.com (Darmawan Salihun)
Date: Tue, 1 Apr 2008 13:40:25 +0700
Subject: [coreboot] Alix2c3 MB support (Geode LX800)
Message-ID: <46893e740803312340p72227573t23c40456450332da@mail.gmail.com>

Hi Guys,

I saw that Alix1.c is supported by Coreboot v3. Is it hard to port the
support for Alix2c3?
The chipset is the same with Alix1.c. Or is it better to port Coreboot
v2 to this board?

The board comes with tinyBIOS but if I couldn't handle the current
problem with tinyBIOS,
I might port coreboot instead.


Regards,

Darmawan Salihun
--------------------------------------------------------------------
-= Human knowledge belongs to the world =-



From klaus123 at ibnoetzold.de  Tue Apr  1 13:55:34 2008
From: klaus123 at ibnoetzold.de (Klaus Stammermann)
Date: Tue, 1 Apr 2008 13:55:34 +0200 (CEST)
Subject: [coreboot] Device mapping problem
Message-ID: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>

Hi there

At first I can't boot my system with coreboot yet. I changed kernel params
so initrd now will be loaded. Used kernel params are now same as in lilo
of original system.

But I logged booting my system with original bios and coreboot. So I hope
we will find the problem.

There are two differences I think that could be a problem. At first there
are two different size of memory detected:
coreboot: 222822k/229376k
origianl bios: 222384k/229312k

And of course on original bios system DMI 2.2 is started. On coreboot DMI
is not present or is invalid.

Some ideas what seems to be problem at coreboot starting on my system?

Klaus

Here log of coreboot booting out of ttyS0:
-----------------------------------------------------------------------------
0

coreboot-2.0.0.0-Fallback Mo 31. M?r 14:41:14 CEST 2008 starting...
 Enabling mainboard devices
 Enabling shadow ram
vt8623 init starting
Detecting Memory
Number of Banks 04
Number of Rows 0d
Priamry DRAM width08
No Columns 0a
MA type e0
Bank 0 (*16 Mb) 10
No Physical Banks 01
Total Memory (*16 Mb) 10
CAS Supported 2.5 3
Cycle time at CL X     (nS)50
Cycle time at CL X-0.5 (nS)60
Cycle time at CL X-1   (nS)00
Starting at CAS 3
We can do CAS 2.5
tRP 3c
tRCD 3c
tRAS 28
Low Bond 03  High Bondd2  Setting DQS delay8dvt8623 done
00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00
10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00
20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00
50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00
60:02 ff 00 30 62 32 01 20 42 2d 43 58 00 44 00 00
70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 10
80:0f 60 00 00 80 00 00 00 02 00 00 00 00 00 00 00
90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00
b0:00 00 00 00 80 00 00 00 88 00 00 04 00 00 00 00
c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00
f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00
AGP
 Doing MTRR init.
Copying coreboot to RAM.
Jumping to coreboot.
coreboot-2.0.0.0-Fallback Mo 31. M?r 14:58:07 CEST 2008 booting...
clocks_per_usec: 1378
Enumerating buses...
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0001 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1106/3123] enabled
PCI: 00:01.0 [1106/b091] enabled
PCI: 00:0d.0 [1106/3044] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.0 [1106/3038] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.1 [1106/3038] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.2 [1106/3038] enabled
In vt8235_enable ffff ffff.
Disabling static device: PCI: 00:10.3
In vt8235_enable 1106 3177.
Initialising Devices
Keyboard init...
PCI: 00:11.0 [1106/3177] enabled
In vt8235_enable 1106 0571.
PCI: 00:11.1 [1106/0571] enabled
In vt8235_enable 1106 3059.
PCI: 00:11.5 [1106/3059] enabled
In vt8235_enable 1106 3068.
PCI: 00:11.6 [1106/3068] disabled
In vt8235_enable 1106 3065.
PCI: 00:12.0 [1106/3065] enabled
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1106/3122] enabled
PCI: pci_scan_bus returning with max=001
vt1211 enabling PNP devices.
PNP: 002e.0 enabled
vt1211 enabling PNP devices.
PNP: 002e.1 enabled
vt1211 enabling PNP devices.
PNP: 002e.2 enabled
vt1211 enabling PNP devices.
PNP: 002e.3 enabled
vt1211 enabling PNP devices.
PNP: 002e.b enabled
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1106/3123] enabled
PCI: 00:01.0 [1106/b091] enabled
PCI: 00:0d.0 [1106/3044] enabled
PCI: 00:10.0 [1106/3038] enabled
PCI: 00:10.1 [1106/3038] enabled
PCI: 00:10.2 [1106/3038] enabled
PCI: 00:10.3 [1106/3104] enabled
PCI: 00:11.0 [1106/3177] enabled
PCI: 00:11.1 [1106/0571] enabled
PCI: 00:11.5 [1106/3059] enabled
PCI: 00:11.6 [1106/3068] enabled
PCI: 00:12.0 [1106/3065] enabled
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [1106/3122] enabled
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus returning with max=002
done
Allocating resources...
Reading resources...
Done reading resources.
Allocating VGA resource PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0001
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
I would set ram size to 0x40000 Kbytes
PCI: 00:0d.0 10 <- [0x00febfc000 - 0x00febfc7ff] size 0x00000800 gran 0x0b
mem
PCI: 00:0d.0 14 <- [0x0000002400 - 0x000000247f] size 0x00000080 gran 0x07 io
PCI: 00:10.0 20 <- [0x0000002800 - 0x000000281f] size 0x00000020 gran 0x05 io
PCI: 00:10.1 20 <- [0x0000002820 - 0x000000283f] size 0x00000020 gran 0x05 io
PCI: 00:10.2 20 <- [0x0000002840 - 0x000000285f] size 0x00000020 gran 0x05 io
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io
PCI: 00:11.1 20 <- [0x00000028c0 - 0x00000028cf] size 0x00000010 gran 0x04 io
PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 14 <- [0x00febfe000 - 0x00febfe0ff] size 0x00000100 gran 0x08
mem
I would set ram size to 0x40000 Kbytes
PCI: 00:0d.0 10 <- [0x00febfd000 - 0x00febfd7ff] size 0x00000800 gran 0x0b
mem
PCI: 00:0d.0 14 <- [0x0000002480 - 0x00000024ff] size 0x00000080 gran 0x07 io
PCI: 00:10.0 20 <- [0x0000002860 - 0x000000287f] size 0x00000020 gran 0x05 io
PCI: 00:10.1 20 <- [0x0000002880 - 0x000000289f] size 0x00000020 gran 0x05 io
PCI: 00:10.2 20 <- [0x00000028a0 - 0x00000028bf] size 0x00000020 gran 0x05 io
PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] size 0x00000100 gran 0x08
mem
PCI: 00:11.1 20 <- [0x00000028d0 - 0x00000028df] size 0x00000010 gran 0x04 io
PCI: 00:11.5 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
PCI: 00:11.6 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] size 0x00000100 gran 0x08
mem
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000f
PCI: 00:01.0 cmd <- 07
PCI: 01:00.0 cmd <- ffff
PCI: 00:0d.0 cmd <- 83
PCI: 00:10.0 subsystem <- 00/00
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 subsystem <- 00/00
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 subsystem <- 00/00
PCI: 00:10.2 cmd <- 01
PCI: 00:11.0 cmd <- 07
PNP: 002e.0 - enabling
PNP: 002e.1 - enabling
PNP: 002e.2 - enabling
PNP: 002e.3 - enabling
PNP: 002e.b - enabling
PCI: 00:11.1 cmd <- 81
PCI: 00:11.5 subsystem <- 00/00
PCI: 00:11.5 cmd <- 01
PCI: 00:12.0 cmd <- 83
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000f
PCI: 00:01.0 cmd <- 07
PCI: 02:00.0 cmd <- 03
PCI: 00:0d.0 cmd <- 83
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 cmd <- 01
PCI: 00:10.3 cmd <- 02
PCI: 00:11.0 cmd <- 07
PCI: 00:11.1 cmd <- 81
PCI: 00:11.5 cmd <- 01
PCI: 00:11.6 cmd <- 01
PCI: 00:12.0 cmd <- 83
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Centaur device 698
CPU: family 06, model 09, stepping 08
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  128MB, type WB
Setting variable MTRR 1, base:  128MB, range:   64MB, type WB
Setting variable MTRR 2, base:  192MB, range:   32MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Disabling local apic...done.
CPU #0 Initialized
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:11.0 init
vt8235 init
RTC Init
Invalid CMOS LB checksum
pci_routing_fixup: dev is 000114c0
setting firewire
Assigning IRQ 9 to 0:d.0
  Readback = 9
setting usb
Assigning IRQ 5 to 0:10.0
  Readback = 5
Assigning IRQ 9 to 0:10.1
  Readback = 9
Assigning IRQ 9 to 0:10.2
  Readback = 9
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting vt8235
Assigning IRQ 5 to 0:11.1
  Readback = 5
Assigning IRQ 9 to 0:11.5
  Readback = 9
Assigning IRQ 9 to 0:11.6
  Readback = 9
setting ethernet
Assigning IRQ 5 to 0:12.0
  Readback = 5
setting vga
setting pci slot
setting cardbus slot
setting riser slot
PNP: 002e.0 init
PNP: 002e.1 init
PNP: 002e.2 init
PNP: 002e.3 init
PNP: 002e.b init
PCI: 00:11.1 init
Enabling VIA IDE.
ide_init: enabling compatibility IDE addresses
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
enables in reg 0x40 0x18
enables in reg 0x40 read back as 0x1b
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x81
command in reg 0x4 reads back as 0x7
PCI: 00:11.5 init
PCI: 00:12.0 init
Configuring VIA Rhine LAN
PCI: 00:00.0 init
VT8623 random fixup ...
Frame buffer at d0000000
PCI: 00:00.0 init
VT8623 random fixup ...
Frame buffer at d0000000
PCI: 00:01.0 init
VT8623 AGP random fixup ...
PCI: 00:0d.0 init
PCI: 01:00.0 init
VGA random fixup ...
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3122
rom base, size: fffc0000
write_protect_vgabios
bus/devfn = 0x100
biosint: INT# 0x15
biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1a7d4
biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1a7d4
biosint:  ip 0x641c   cs 0xc000  flags 0x46
biosint: INT# 0x1a
biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b
biosint:  ip 0x40f0   cs 0xc000  flags 0x46
0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5
biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1a7d4
biosint:  ip 0x651b   cs 0xc000  flags 0x87
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1a7d4
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112
biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1a7d4
biosint:  ip 0x6533   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112
biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6479   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6485   cs 0xc000  flags 0x202
PCI: 00:01.0 init
VT8623 AGP random fixup ...
PCI: 00:0d.0 init
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:10.3 init
PCI: 00:11.0 init
vt8235 init
RTC Init
Invalid CMOS LB checksum
pci_routing_fixup: dev is 0001ba18
setting firewire
Assigning IRQ 9 to 0:d.0
  Readback = 9
setting usb
Assigning IRQ 5 to 0:10.0
  Readback = 5
Assigning IRQ 9 to 0:10.1
  Readback = 9
Assigning IRQ 9 to 0:10.2
  Readback = 9
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting vt8235
Assigning IRQ 5 to 0:11.1
  Readback = 5
Assigning IRQ 9 to 0:11.5
  Readback = 9
Assigning IRQ 9 to 0:11.6
  Readback = 9
setting ethernet
Assigning IRQ 5 to 0:12.0
  Readback = 5
setting vga
setting pci slot
setting cardbus slot
setting riser slot
PCI: 00:11.1 init
Enabling VIA IDE.
ide_init: enabling compatibility IDE addresses
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
enables in reg 0x40 0x1b
enables in reg 0x40 read back as 0x1b
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8f
command in reg 0x4 0x7
command in reg 0x4 reads back as 0x7
PCI: 00:11.5 init
PCI: 00:11.6 init
PCI: 00:12.0 init
Configuring VIA Rhine LAN
PCI: 02:00.0 init
VGA random fixup ...
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3122
rom base, size: fffc0000
write_protect_vgabios
bus/devfn = 0x100
biosint: INT# 0x15
biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1c724
biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1c724
biosint:  ip 0x641c   cs 0xc000  flags 0x46
biosint: INT# 0x1a
biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b
biosint:  ip 0x40f0   cs 0xc000  flags 0x46
0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5
biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1c724
biosint:  ip 0x651b   cs 0xc000  flags 0x87
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c724
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112
biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1c724
biosint:  ip 0x6533   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112
biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6479   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6485   cs 0xc000  flags 0x202
Devices initialized
Copying IRQ routing tables to 0xf0000...done.
Verifing copy of IRQ routing tables at 0xf0000...done
Checking IRQ routing table consistency...
check_pirq_routing_table() - irq_routing_table located at: 0x000f0000
done.
ACPI: Writing ACPI tables at f0400...
ACPI:     * FACS
ACPI:     * DSDT @ 000f04aa Length 3f0
ACPI:     * FADT
ACPI: added table 1/8 Length now 40
ACPI: done.
Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0c00 to 0x00100000
Wrote coreboot table at: 00000530 - 00000c0c  checksum 8039

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

rom_stream: 0xfffd0000 - 0xfffd814f
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0x100000 size 0x22080 offset 0xc0 filesize 0x7ea8
(cleaned up) New segment addr 0x100000 size 0x22080 offset 0xc0 filesize
0x7ea8
New segment addr 0x122080 size 0x48 offset 0x7f80 filesize 0x48
(cleaned up) New segment addr 0x122080 size 0x48 offset 0x7f80 filesize 0x48
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000022080
filesz: 0x0000000000007ea8
Clearing Segment: addr: 0x0000000000107ea8 memsz: 0x000000000001a1d8
Loading Segment: addr: 0x0000000000122080 memsz: 0x0000000000000048
filesz: 0x0000000000000048
Jumping to boot code at 0x106224
FILO version 0.5 (klausst at thor) Mon Mar 31 14:56:38 CEST 2008
No sound device found
boot: hda1:/boot/vmlinuz root=/dev/sda1 initrd=/boot/initrd.splash
console=tty0 console=ttyS0,115200
hda: LBA 2049MB: SanDisk SDCFX-2048
Mounted ext2fs
Found Linux version 2.6.18.2-34-default (geeko at buildhost) #1 SMP Mon Nov
27 11:46:27 UTC 2006 bzImage.
Loading kernel... ok
Loading initrd... ok
Jumping to entry point...
Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
 BIOS-e820: 0000000000100000 - 000000000e000000 (usable)
0MB HIGHMEM available.
224MB LOWMEM available.
DMI not present or invalid.
Using APIC driver default
IO/L-APIC disabled because your old system seems to be old
overwrite with "apic"
ACPI: Disabling ACPI support
Allocating PCI resources starting at 10000000 (gap: 0e000000:f2000000)
Detected 599.732 MHz processor.
Built 1 zonelists.  Total pages: 57344
Kernel command line: root=/dev/sda1 console=tty0 console=ttyS0,115200
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
PID hash table entries: 1024 (order: 10, 4096 bytes)
Console: colour VGA+ 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 222892k/229376k available (1697k kernel code, 6008k reserved, 968k
data, 196k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 1201.25 BogoMIPS
(lpj=2402512)
Security Framework v1.0.0 initialized
Mount-cache hash table entries: 512
CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line)
CPU: L2 Cache: 64K (32 bytes/line)
Compat vDSO mapped to ffffe000.
Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
Freeing SMP alternatives: 16k freed
checking if image is initramfs...it isn't (bad gzip magic numbers); looks
like an initrd
Freeing initrd memory: 622k freed
CPU0: Centaur VIA Nehemiah stepping 08
SMP motherboard not detected.
Local APIC not detected. Using dummy APIC emulation.
Brought up 1 CPUs
migration_cost=0
NET: Registered protocol family 16
PCI: Using configuration type 1
Setting up standard PCI resources
ACPI: Interpreter disabled.
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI: disabled
PnPBIOS: Scanning system for PnP BIOS support...
PnPBIOS: PnP BIOS support was not detected.
PCI: Probing PCI hardware
PCI quirk: region 0400-047f claimed by vt8235 PM
PCI quirk: region 0f00-0f0f claimed by vt8235 SMB
PCI: Using IRQ router default [1106/3123] at 0000:00:00.0
PCI: Bridge: 0000:00:01.0
  IO window: disabled.
  MEM window: dc000000-ddffffff
  PREFETCH window: d8000000-dbffffff
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 4096)
TCP reno registered
apm: BIOS not found.
audit: initializing netlink socket (disabled)
audit(1206977338.596:1): initialized
Total HugeTLB memory allocated, 0
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
isapnp: Scanning for PnP cards...
isapnp: No Plug & Play device found
Real Time Clock Driver v1.12ac
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
PNP: No PS/2 controller found. Probing ports directly.
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
mice: PS/2 mouse device common for all mice
input: PC Speaker as /class/input/input0
input: AT Translated Set 2 keyboard as /class/input/input1
input: ImExPS/2 Generic Explorer Mouse as /class/input/input2
md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
md: bitmap version 4.39
NET: Registered protocol family 1
Using IPI No-Shortcut mode
md: Autodetecting RAID arrays.
Time: tsc clocksource has been installed.
md: autorun ...
md: ... autorun DONE.
RAMDISK: Couldn't find valid RAM disk image starting at 0.
VFS: Cannot open root device "sda1" or unknown-block(0,0)
Please append a correct "root=" boot option
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(0,0)

-----------------------------------------------------------------------------

And here /var/log/messages with original bios:
-----------------------------------------------------------------------------
Apr  1 11:37:13 (none) syslogd 1.4.1: restart.
Apr  1 11:37:13 (none) kernel: klogd 1.4.1, log source = /proc/kmsg started.
Apr  1 11:37:13 (none) kernel: Linux version 2.6.22.9 (root at zenwalk) (gcc
version 4.1.2) #1 SMP PREEMPT Sat Sep 29 22:22:07 CEST 2007
Apr  1 11:37:13 (none) kernel: BIOS-provided physical RAM map:
Apr  1 11:37:13 (none) kernel: 0MB HIGHMEM available.
Apr  1 11:37:13 (none) kernel: 223MB LOWMEM available.
Apr  1 11:37:13 (none) kernel: DMI 2.2 present.
Apr  1 11:37:13 (none) kernel: ACPI: PM-Timer IO Port: 0x408
Apr  1 11:37:13 (none) kernel: Kernel command line: BOOT_IMAGE=Zenwalk ro
root=801 splash=silent
Apr  1 11:37:13 (none) kernel: bootsplash: silent mode.
Apr  1 11:37:13 (none) kernel: No local APIC present or hardware disabled
Apr  1 11:37:13 (none) kernel: Enabling fast FPU save and restore... done.
Apr  1 11:37:13 (none) kernel: Enabling unmasked SIMD FPU exception
support... done.
Apr  1 11:37:13 (none) kernel: Initializing CPU#0
Apr  1 11:37:13 (none) kernel: Memory: 222384k/229312k available (2583k
kernel code, 6476k reserved, 727k data, 228k init, 0k highmem)
Apr  1 11:37:13 (none) kernel: SLUB: Genslabs=22, HWalign=32, Order=0-1,
MinObjects=4, CPUs=1, Nodes=1
Apr  1 11:37:13 (none) kernel: CPU: L1 I Cache: 64K (32 bytes/line), D
cache 64K (32 bytes/line)
Apr  1 11:37:13 (none) kernel: CPU: L2 Cache: 64K (32 bytes/line)
Apr  1 11:37:13 (none) kernel: Checking 'hlt' instruction... OK.
Apr  1 11:37:13 (none) kernel: SMP alternatives: switching to UP code
Apr  1 11:37:13 (none) kernel: Freeing SMP alternatives: 14k freed
Apr  1 11:37:13 (none) kernel: ACPI: Core revision 20070126
Apr  1 11:37:13 (none) kernel: SMP motherboard not detected.
Apr  1 11:37:13 (none) kernel: Local APIC not detected. Using dummy APIC
emulation.
Apr  1 11:37:13 (none) kernel: Brought up 1 CPUs
Apr  1 11:37:13 (none) kernel: NET: Registered protocol family 16
Apr  1 11:37:13 (none) kernel: ACPI: bus type pci registered
Apr  1 11:37:13 (none) kernel: PCI: PCI BIOS revision 2.10 entry at
0xfb260, last bus=1
Apr  1 11:37:13 (none) kernel: PCI: Using configuration type 1
Apr  1 11:37:13 (none) kernel: ACPI: Interpreter enabled
Apr  1 11:37:13 (none) kernel: ACPI: (supports S0 S1 S4 S5)
Apr  1 11:37:13 (none) kernel: ACPI: Using PIC for interrupt routing
Apr  1 11:37:13 (none) kernel: ACPI: PCI Root Bridge [PCI0] (0000:00)
Apr  1 11:37:13 (none) kernel: Linux Plug and Play Support v0.97 (c) Adam
Belay
Apr  1 11:37:13 (none) kernel: pnp: PnP ACPI init
Apr  1 11:37:13 (none) kernel: ACPI: bus type pnp registered
Apr  1 11:37:13 (none) kernel: pnp: PnP ACPI: found 14 devices
Apr  1 11:37:13 (none) kernel: ACPI: ACPI bus type pnp unregistered
Apr  1 11:37:13 (none) kernel: SCSI subsystem initialized
Apr  1 11:37:13 (none) kernel: usbcore: registered new interface driver usbfs
Apr  1 11:37:13 (none) kernel: usbcore: registered new interface driver hub
Apr  1 11:37:13 (none) kernel: usbcore: registered new device driver usb
Apr  1 11:37:13 (none) kernel: PCI: Using ACPI for IRQ routing
Apr  1 11:37:13 (none) kernel: PCI: If a device doesn't work, try
"pci=routeirq".  If it helps, post a report
Apr  1 11:37:13 (none) kernel: pnp: 00:00: iomem range 0xda000-0xdbfff has
been reserved
Apr  1 11:37:13 (none) kernel: pnp: 00:00: iomem range 0xf0000-0xf7fff
could not be reserved
Apr  1 11:37:13 (none) kernel: pnp: 00:00: iomem range 0xf8000-0xfbfff
could not be reserved
Apr  1 11:37:13 (none) kernel: pnp: 00:00: iomem range 0xfc000-0xfffff
could not be reserved
Apr  1 11:37:13 (none) kernel: pnp: 00:02: ioport range 0x400-0x47f has
been reserved
Apr  1 11:37:13 (none) kernel: pnp: 00:02: ioport range 0x500-0x50f has
been reserved
Apr  1 11:37:13 (none) kernel: Time: tsc clocksource has been installed.
Apr  1 11:37:13 (none) kernel: PCI: Bridge: 0000:00:01.0
Apr  1 11:37:13 (none) kernel:   IO window: disabled.
Apr  1 11:37:13 (none) kernel:   MEM window: dc000000-ddffffff
Apr  1 11:37:13 (none) kernel:   PREFETCH window: d8000000-dbffffff
Apr  1 11:37:13 (none) kernel: NET: Registered protocol family 2
Apr  1 11:37:13 (none) kernel: TCP: Hash tables configured (established
8192 bind 8192)
Apr  1 11:37:13 (none) kernel: TCP reno registered
Apr  1 11:37:13 (none) kernel: checking if image is initramfs...it isn't
(bad gzip magic numbers); looks like an initrd
Apr  1 11:37:13 (none) kernel: Freeing initrd memory: 622k freed
Apr  1 11:37:13 (none) kernel: SGI XFS with no debug enabled
Apr  1 11:37:13 (none) kernel: SGI XFS Quota Management subsystem
Apr  1 11:37:13 (none) kernel: io scheduler noop registered
Apr  1 11:37:13 (none) kernel: io scheduler cfq registered (default)
Apr  1 11:37:13 (none) kernel: PCI: VIA PCI bridge detected. Disabling DAC.
Apr  1 11:37:13 (none) kernel: vesafb: framebuffer at 0xd8000000, mapped
to 0xce880000, using 10240k, total 32768k
Apr  1 11:37:13 (none) kernel: vesafb: mode is 1280x1024x16,
linelength=2560, pages=11
Apr  1 11:37:13 (none) kernel: vesafb: protected mode interface info at
c000:8846
Apr  1 11:37:13 (none) kernel: vesafb: pmi: set display start = c00c8897,
set palette = c00c88f7
Apr  1 11:37:13 (none) kernel: vesafb: pmi: ports = b4c3 b503 d403 d503
cc03 d703 d803 d903 ff03
Apr  1 11:37:13 (none) kernel: vesafb: scrolling: redraw
Apr  1 11:37:13 (none) kernel: vesafb: Truecolor: size=0:5:6:5,
shift=0:11:5:0
Apr  1 11:37:13 (none) kernel: bootsplash 3.1.6-2004/03/31: looking for
picture...<6> silentjpeg size 166473 bytes,<6>Switched to high resolution
mode on CPU 0
Apr  1 11:37:13 (none) kernel: ...found (1280x1024, 140485 bytes, v3).
Apr  1 11:37:13 (none) kernel: fb0: VESA VGA frame buffer device
Apr  1 11:37:13 (none) kernel: isapnp: Scanning for PnP cards...
Apr  1 11:37:13 (none) kernel: isapnp: No Plug & Play device found
Apr  1 11:37:13 (none) kernel: VIA RNG detected
Apr  1 11:37:13 (none) kernel: Serial: 8250/16550 driver $Revision: 1.90 $
4 ports, IRQ sharing enabled
Apr  1 11:37:13 (none) kernel: serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is
a 16550A
Apr  1 11:37:13 (none) kernel: serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is
a 16550A
Apr  1 11:37:13 (none) kernel: 00:09: ttyS0 at I/O 0x3f8 (irq = 4) is a
16550A
Apr  1 11:37:13 (none) kernel: 00:0a: ttyS1 at I/O 0x2f8 (irq = 3) is a
16550A
Apr  1 11:37:13 (none) kernel: Floppy drive(s): fd0 is 1.44M
Apr  1 11:37:13 (none) kernel: FDC 0 is a post-1991 82077
Apr  1 11:37:13 (none) kernel: PPP generic driver version 2.4.2
Apr  1 11:37:13 (none) kernel: ACPI: PCI Interrupt 0000:00:11.1[A] -> Link
[LNKA] -> GSI 11 (level, low) -> IRQ 11
Apr  1 11:37:13 (none) kernel: PCI: VIA VLink IRQ fixup for 0000:00:11.1,
from 255 to 11
Apr  1 11:37:14 (none) kernel: scsi0 : pata_via
Apr  1 11:37:14 (none) kernel: scsi1 : pata_via
Apr  1 11:37:14 (none) kernel: ata1: PATA max UDMA/133 cmd 0x000101f0 ctl
0x000103f6 bmdma 0x0001e000 irq 14
Apr  1 11:37:14 (none) kernel: ata2: PATA max UDMA/133 cmd 0x00010170 ctl
0x00010376 bmdma 0x0001e008 irq 15
Apr  1 11:37:14 (none) kernel: ata1.00: CFA: SanDisk SDCFX-2048, HDX 4.04,
max UDMA/66
Apr  1 11:37:14 (none) kernel: ata1.00: 4001760 sectors, multi 0: LBA
Apr  1 11:37:14 (none) kernel: ata1.00: configured for UDMA/33
Apr  1 11:37:14 (none) kernel: scsi 0:0:0:0: Direct-Access     ATA     
SanDisk SDCFX-20 HDX  PQ: 0 ANSI: 5
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] 4001760 512-byte hardware
sectors (2049 MB)
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write Protect is off
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write cache: disabled,
read cache: enabled, doesn't support DPO or FUA
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] 4001760 512-byte hardware
sectors (2049 MB)
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write Protect is off
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write cache: disabled,
read cache: enabled, doesn't support DPO or FUA
Apr  1 11:37:14 (none) kernel:  sda: sda1
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Attached SCSI removable disk
Apr  1 11:37:14 (none) kernel: usbcore: registered new interface driver
libusual
Apr  1 11:37:14 (none) kernel: PNP: PS/2 Controller
[PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
Apr  1 11:37:14 (none) kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
Apr  1 11:37:14 (none) kernel: serio: i8042 AUX port at 0x60,0x64 irq 12
Apr  1 11:37:14 (none) kernel: mice: PS/2 mouse device common for all mice
Apr  1 11:37:14 (none) kernel: input: AT Translated Set 2 keyboard as
/class/input/input0
Apr  1 11:37:14 (none) kernel: md: linear personality registered for level -1
Apr  1 11:37:14 (none) kernel: md: raid0 personality registered for level 0
Apr  1 11:37:14 (none) kernel: md: raid1 personality registered for level 1
Apr  1 11:37:14 (none) kernel: md: raid10 personality registered for level 10
Apr  1 11:37:14 (none) kernel: md: raid6 personality registered for level 6
Apr  1 11:37:14 (none) kernel: md: raid5 personality registered for level 5
Apr  1 11:37:14 (none) kernel: md: raid4 personality registered for level 4
Apr  1 11:37:14 (none) kernel: raid5: automatically using best
checksumming function: pIII_sse
Apr  1 11:37:14 (none) kernel: md: multipath personality registered for
level -4
Apr  1 11:37:14 (none) kernel: device-mapper: ioctl: 4.11.0-ioctl
(2006-10-12) initialised: dm-devel at redhat.com
Apr  1 11:37:14 (none) kernel: device-mapper: multipath: version 1.0.5 loaded
Apr  1 11:37:14 (none) kernel: device-mapper: multipath round-robin:
version 1.0.0 loaded
Apr  1 11:37:14 (none) kernel: usbcore: registered new interface driver
hiddev
Apr  1 11:37:14 (none) kernel: usbcore: registered new interface driver
usbhid
Apr  1 11:37:14 (none) kernel: drivers/hid/usbhid/hid-core.c: v2.6:USB HID
core driver
Apr  1 11:37:14 (none) kernel: TCP cubic registered
Apr  1 11:37:14 (none) kernel: NET: Registered protocol family 1
Apr  1 11:37:14 (none) kernel: NET: Registered protocol family 17
Apr  1 11:37:14 (none) kernel: input: ImExPS/2 Generic Explorer Mouse as
/class/input/input1
Apr  1 11:37:14 (none) kernel: md: Autodetecting RAID arrays.
Apr  1 11:37:14 (none) kernel: md: autorun ...
Apr  1 11:37:14 (none) kernel: md: ... autorun DONE.
Apr  1 11:37:14 (none) kernel: RAMDISK: Couldn't find valid RAM disk image
starting at 0.
Apr  1 11:37:14 (none) kernel: Freeing unused kernel memory: 228k freed
Apr  1 11:37:14 (none) kernel: Linux agpgart interface v0.102 (c) Dave Jones
Apr  1 11:37:14 (none) kernel: agpgart: Detected VIA CLE266 chipset
Apr  1 11:37:14 (none) kernel: agpgart: AGP aperture is 128M @ 0xd0000000
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: Attached scsi generic sg0 type 0
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:00:0d.0[A] -> Link
[LNKB] -> GSI 5 (level, low) -> IRQ 5
Apr  1 11:37:14 (none) kernel: ohci1394: fw-host0: OHCI-1394 1.1 (PCI):
IRQ=[5]  MMIO=[de000000-de0007ff]  Max Packet=[2048]  IR/IT contexts=[4/8]
Apr  1 11:37:14 (none) kernel: USB Universal Host Controller Interface
driver v3.0
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:00:10.0[A] -> Link
[LNKA] -> GSI 11 (level, low) -> IRQ 11
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.0: UHCI Host Controller
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.0: new USB bus
registered, assigned bus number 1
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.0: irq 11, io base
0x0000d400
Apr  1 11:37:14 (none) kernel: usb usb1: configuration #1 chosen from 1
choice
Apr  1 11:37:14 (none) kernel: hub 1-0:1.0: USB hub found
Apr  1 11:37:14 (none) kernel: hub 1-0:1.0: 2 ports detected
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:00:10.3[D] -> Link
[LNKD] -> GSI 11 (level, low) -> IRQ 11
Apr  1 11:37:14 (none) kernel: ehci_hcd 0000:00:10.3: EHCI Host Controller
Apr  1 11:37:14 (none) kernel: ehci_hcd 0000:00:10.3: new USB bus
registered, assigned bus number 2
Apr  1 11:37:14 (none) kernel: ehci_hcd 0000:00:10.3: irq 11, io mem
0xde001000
Apr  1 11:37:14 (none) kernel: ehci_hcd 0000:00:10.3: USB 2.0 started,
EHCI 1.00, driver 10 Dec 2004
Apr  1 11:37:14 (none) kernel: usb usb2: configuration #1 chosen from 1
choice
Apr  1 11:37:14 (none) kernel: hub 2-0:1.0: USB hub found
Apr  1 11:37:14 (none) kernel: hub 2-0:1.0: 6 ports detected
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:00:10.1[B] -> Link
[LNKB] -> GSI 5 (level, low) -> IRQ 5
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.1: UHCI Host Controller
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.1: new USB bus
registered, assigned bus number 3
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.1: irq 5, io base
0x0000d800
Apr  1 11:37:14 (none) kernel: usb usb3: configuration #1 chosen from 1
choice
Apr  1 11:37:14 (none) kernel: hub 3-0:1.0: USB hub found
Apr  1 11:37:14 (none) kernel: hub 3-0:1.0: 2 ports detected
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:00:10.2[C] -> Link
[LNKC] -> GSI 10 (level, low) -> IRQ 10
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.2: UHCI Host Controller
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.2: new USB bus
registered, assigned bus number 4
Apr  1 11:37:14 (none) kernel: uhci_hcd 0000:00:10.2: irq 10, io base
0x0000dc00
Apr  1 11:37:14 (none) kernel: usb usb4: configuration #1 chosen from 1
choice
Apr  1 11:37:14 (none) kernel: hub 4-0:1.0: USB hub found
Apr  1 11:37:14 (none) kernel: hub 4-0:1.0: 2 ports detected
Apr  1 11:37:14 (none) kernel: usb 3-1: new full speed USB device using
uhci_hcd and address 2
Apr  1 11:37:14 (none) kernel: usb 3-1: configuration #1 chosen from 1 choice
Apr  1 11:37:14 (none) kernel: input: ITUNER INC USB-LCD-20x2 as
/class/input/input2
Apr  1 11:37:14 (none) kernel: input,hiddev0: USB HID v1.01 Device [ITUNER
INC USB-LCD-20x2] on usb-0000:00:10.1-1
Apr  1 11:37:14 (none) kernel: via-rhine.c:v1.10-LK1.4.3 2007-03-06
Written by Donald Becker
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:00:12.0[A] -> Link
[LNKA] -> GSI 11 (level, low) -> IRQ 11
Apr  1 11:37:14 (none) kernel: eth0: VIA Rhine II at 0xde002000,
00:40:63:ec:5d:7a, IRQ 11.
Apr  1 11:37:14 (none) kernel: eth0: MII PHY found at address 1, status
0x7849 advertising 05e1 Link 0000.
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:01:00.0[A] -> Link
[LNKA] -> GSI 11 (level, low) -> IRQ 11
Apr  1 11:37:14 (none) kernel: ACPI: PCI Interrupt 0000:00:11.5[C] -> Link
[LNKC] -> GSI 10 (level, low) -> IRQ 10
Apr  1 11:37:14 (none) kernel: input: Power Button (FF) as
/class/input/input3
Apr  1 11:37:14 (none) kernel: ACPI: Power Button (FF) [PWRF]
Apr  1 11:37:14 (none) kernel: input: Power Button (CM) as
/class/input/input4
Apr  1 11:37:14 (none) kernel: ACPI: Power Button (CM) [PWRB]
Apr  1 11:37:14 (none) kernel: ACPI: CPU0 (power states: C1[C1] C2[C2])
Apr  1 11:37:14 (none) kernel: ACPI: Processor [CPU0] (supports 2
throttling states)
Apr  1 11:37:14 (none) kernel: Time: acpi_pm clocksource has been installed.
Apr  1 11:37:14 (none) kernel: ata1: soft resetting port
Apr  1 11:37:14 (none) kernel: ata1.00: configured for UDMA/33
Apr  1 11:37:14 (none) kernel: ata1: EH complete
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] 4001760 512-byte hardware
sectors (2049 MB)
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write Protect is off
Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write cache: disabled,
read cache: enabled, doesn't support DPO or FUA
Apr  1 11:37:14 (none) kernel: ata2: soft resetting port
Apr  1 11:37:14 (none) kernel: ata2: EH complete
Apr  1 11:37:15 (none) kernel: ata2: soft resetting port
Apr  1 11:37:15 (none) logger: /etc/rc.d/rc.inet1:  /sbin/ifconfig lo
127.0.0.1
Apr  1 11:37:15 (none) logger: /etc/rc.d/rc.inet1:  /sbin/route add -net
127.0.0.0 netmask 255.0.0.0 lo
Apr  1 11:37:15 (none) kernel: ata2: EH complete
Apr  1 11:37:16 (none) uwd: pattern0=sr[0-9]
Apr  1 11:37:16 (none) uwd: watching
Apr  1 11:37:16 (none) uwd: watching
Apr  1 11:37:19 (none) kernel: [drm] Initialized drm 1.1.0 20060810
Apr  1 11:37:19 (none) kernel: [drm] Initialized via 2.11.1 20070202 on
minor 0
Apr  1 11:37:19 (none) kernel: agpgart: Found an AGP 2.0 compliant device
at 0000:00:00.0.
Apr  1 11:37:19 (none) kernel: agpgart: Putting AGP V2 device at
0000:00:00.0 into 4x mode
Apr  1 11:37:19 (none) kernel: agpgart: Putting AGP V2 device at
0000:01:00.0 into 4x mode
Apr  1 11:37:33 (none) shutdown[1110]: shutting down for system halt
Apr  1 11:37:34 (none) init: Switching to runlevel: 0
Apr  1 11:37:35 (none) shutdown[1368]: shutting down for system halt
Apr  1 11:37:40 (none) logger: /etc/rc.d/rc.inet1:  /sbin/ifconfig eth0 down
Apr  1 11:37:41 (none) logger: /etc/rc.d/rc.inet1:  /sbin/ifconfig lo down
Apr  1 11:37:41 (none) exiting on signal 15

-----------------------------------------------------------------------------




From joe at smittys.pointclark.net  Tue Apr  1 14:15:19 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Tue, 01 Apr 2008 08:15:19 -0400
Subject: [coreboot] r3206
	-	trunk/coreboot-v2/src/southbridge/intel/i82801db
In-Reply-To: <20080401024800.4D3C836C07C@smittys.pointclark.net>
References: <20080401024800.4D3C836C07C@smittys.pointclark.net>
Message-ID: <20080401081519.9ey56hr94w08ssc4@www.smittys.pointclark.net>

Quoting svn at coreboot.org:

> Author: eswierk
> Date: 2008-04-01 04:42:52 +0200 (Tue, 01 Apr 2008)
> New Revision: 3206
>
> Removed:
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
> Log:
> Removal of i82801DB (ICH4)
>
> There are no boards that use the i82801DB (ICH4). The code does NOT work.
>
> Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
> Acked-by: Corey Osgood <corey.osgood at gmail.com>
> Acked-by: Ed Swierk <eswierk at arastra.com>
>
>
Thanks Ed :-)

Thanks - Joe



From joe at smittys.pointclark.net  Tue Apr  1 14:33:04 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Tue, 01 Apr 2008 08:33:04 -0400
Subject: [coreboot] [PATCH] Hardcode PCI devices in Intel
	southbridge	early init code
In-Reply-To: <47F1C428.1090302@coresystems.de>
References: <e6c711510803310850g21d20f0y172efc8c54f0707@mail.gmail.com>
	<20080331131600.krvfjp2agwsowkw0@www.smittys.pointclark.net>
	<dd3c80060803311204u4314d19l9325928fa94fb485@mail.gmail.com>
	<20080331160459.999kw5gmiokgk4oc@www.smittys.pointclark.net>
	<20080331202756.GB6215@greenwood>
	<20080331163249.q2jeca3j4kwk8ws4@www.smittys.pointclark.net>
	<dd3c80060803311337r78255d50q83185764c024967c@mail.gmail.com>
	<dd3c80060803311343i4bb938b1s88b04b4bfdacbe8@mail.gmail.com>
	<47F1C428.1090302@coresystems.de>
Message-ID: <20080401083304.nresk4c77ockc0wk@www.smittys.pointclark.net>

Quoting Stefan Reinauer <stepan at coresystems.de>:

> Corey Osgood wrote:
>
>>
>> Yep, it's the digitallogic/adl855pc. I think it was Ron that said   
>> the 855 never worked, but that was a long time ago, and I can't be   
>> sure.  Perhaps we should just leave it kicking around, and focus on  
>>  not letting this happen to v3.
>
> I can confirm that code does nothing good. I have a mostly ready 855
> port sitting somewhere that I wrote from flash. I will look into this
> when/if I get the machine again I was originally writing it for.
>
No worries, I will be working on a board in the near future that uses  
the i82801dbm (ICH4-M) and I will verify it works with the i82801xx  
code. If everything works ok, I will submit a patch to switch over the  
digitallogic/adl855pc and remove the i82801dbm code.

Thanks - Joe



From fainshf at gmail.com  Tue Apr  1 14:37:28 2008
From: fainshf at gmail.com (Fridel Fainshtein)
Date: Tue, 1 Apr 2008 15:37:28 +0300
Subject: [coreboot] [LinuxBIOS] FILO with the USB
In-Reply-To: <20080329202429.f6mpob4hkwkcog8g@www.smittys.pointclark.net>
References: <478C40DE.7020606@gmail.com>
	<d59bbe420803281455q3f3ed70bte3fc2ba586278618@mail.gmail.com>
	<20080328180800.ea2qjm2gacco8sow@www.smittys.pointclark.net>
	<dd3c80060803281825j531f6785m7d771858f2fe8f05@mail.gmail.com>
	<20080329020815.GD24943@greenwood>
	<20080328221200.ujm8u686skww0ck8@www.smittys.pointclark.net>
	<dd3c80060803281925w2601a516jbe6cf79c45401ff2@mail.gmail.com>
	<20080329125637.d9dpj92k2skkgwcs@www.smittys.pointclark.net>
	<d59bbe420803291654t572c1ed6m853c3e5b3589b4b8@mail.gmail.com>
	<20080329202429.f6mpob4hkwkcog8g@www.smittys.pointclark.net>
Message-ID: <d59bbe420804010537t5f15d608pe55d7972673671b8@mail.gmail.com>

Anyway, working output is as in the attached file. I use Kingston
DataTraveler 512M

On Sun, Mar 30, 2008 at 3:24 AM,  <joe at smittys.pointclark.net> wrote:
> Quoting Fridel Fainshtein <fainshf at gmail.com>:
>
>
> > Observing the UHCI code I can see the following issue (see usb.c and uhci.c):
>  >
>  > 1) uhc_init(dev);
>  > ...
>  > 2) uhci_init();
>  >
>  Hmm....
>
> >
>  > The first function uses " frame_list[num_controllers] ".
>  > The second function initializes the frame_list by init_framelist(i);
>  >
>  Depend on the value of (i), correct?
>
> >
>  > May be if the order will be different it will works. I am not sure,
>  > though. It is 3 o'clock, may be I just dreaming.
>  >
>  Thanks for the insite Fridel, I will look into this deeper.
>
>
> >
>  >> > Fridel's code, in patch form and with the non-USB bits removed.
>  >>
>  >>  Well,
>  >>  I tested this patch and it does nothing for UHCI :-( It might work
>  >>  great for OHCI but someone else will need to test it.
>  >>
>  >>  > It should fall back, but not everything does that properly. Just for
>  >>  > checking the basic functioning, any old USB 1.1 device (keyboard, mouse,
>  >>  > hub) will do to at least see that it was recognized and configured.
>  >>  >
>  >>  > IIRC, the sequence is:
>  >>  > 1. detect that a device is connected to the port
>  >>  > 2. enable the port
>  >>  > 3. Assign a USB ID with a setup packet
>  >>  > 4. query for device type and strings
>  >>  > 5. If a suitable block device, load the payload.
>  >>  >
>  >>  > 5 used to be a stream object (like in the old LinuxBIOS code) handed to
>  >>  > a copy of the the ELF loader. the read method set up the request and
>  >>  > called into the USB polling loop. I'm guessing that's
>  >>  >
>  >>  > One potential issue there is that control of the physical port between
>  >>  > UHCI or OHCI (for 1.1) and EHCI (for 2.0) is determined by a bit in a
>  >>  > register. I'm not sure what happens if it's set wrong, but I suspect it
>  >>  > could look like your debug output.
>  >>  >
>  >>  > was this exact setup working before r54? One possability is that the USB
>  >>  > code always had a bug that wasn't visible when allocations were quietly
>  >>  > double the requested size.
>  >>
>  >>  So I tried a low speed device (old usb mouse) and it did something
>  >>  different, it still errored out of course (because it is not a drive)
>  >>  but I think it was working the way it is supposed to??? Anyways I also
>  >>  tried a USB 2.0 flash drive with no success. I think what is happening
>  >>  here is, it is not falling back to low speed UHCI......see
>  >>  attachment....I don't know where to go from here....
>  >>
>
>  Thanks - Joe
>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: USB_output.txt
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20080401/41f36766/attachment.txt>

From uwe at hermann-uwe.de  Tue Apr  1 17:10:55 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Apr 2008 17:10:55 +0200
Subject: [coreboot] [PATCH] Disable integrated Intel 3100
	devices	properly
In-Reply-To: <e6c711510803311901p70538127v51449a2b24b55048@mail.gmail.com>
References: <e6c711510803311638y2b224697h6b701665d21ebd70@mail.gmail.com>
	<20080401004147.GA26546@greenwood>
	<e6c711510803311901p70538127v51449a2b24b55048@mail.gmail.com>
Message-ID: <20080401151055.GC19364@greenwood>

On Mon, Mar 31, 2008 at 07:01:52PM -0700, Ed Swierk wrote:
> +	/* To disable an integrated southbridge device, set the corresponding
> +	   flag in the Function Disable register */

Please use this format for multi-line comments as per coding guidelines:

/*
 * To disable an integrated southbridge device, set the corresponding
 * flag in the Function Disable register.
 */

Also, please end all sentences in code comments with a full stop, here...


> +	/* Temporarily enable the root complex register block at 0xa0000000 */

here,


> +	lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0));
> +	pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0));
> +	disable = (volatile u32 *) 0xa0003418;
> +	func = PCI_FUNC(dev->path.u.pci.devfn);
> +	switch (PCI_SLOT(dev->path.u.pci.devfn)) {
> +	case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */
> +		*disable |= (1 << (func == 0x0 ? 14 : func));
> +		break;
> +	case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */
> +		*disable |= (1 << (func + 8));
> +		break;
> +	case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */
> +		*disable |= (1 << (func + 16));
> +		break;
>  	}
> +	/* Disable the root complex register block */

and here.


Rest looks good.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Tue Apr  1 17:45:56 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Apr 2008 17:45:56 +0200
Subject: [coreboot] Device mapping problem
In-Reply-To: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
Message-ID: <20080401154556.GD19364@greenwood>

Hi,

On Tue, Apr 01, 2008 at 01:55:34PM +0200, Klaus Stammermann wrote:
> At first I can't boot my system with coreboot yet. I changed kernel params
> so initrd now will be loaded. Used kernel params are now same as in lilo
> of original system.

What does 'cat /proc/cmdline' on the same disk (but booted with the
original BIOS) say?


> There are two differences I think that could be a problem. At first there
> are two different size of memory detected:
> coreboot: 222822k/229376k
> origianl bios: 222384k/229312k

Not a problem, I think.


> And of course on original bios system DMI 2.2 is started. On coreboot DMI
> is not present or is invalid.

Not a problem, either. coreboot doesn't provide DMI (not needed).


> I would set ram size to 0x40000 Kbytes

Do you have 256MB of RAM, is that correct?


> Enabling VIA IDE.
> ide_init: enabling compatibility IDE addresses

Looks ok.


> FILO version 0.5 (klausst at thor) Mon Mar 31 14:56:38 CEST 2008

Looks ok.


> boot: hda1:/boot/vmlinuz root=/dev/sda1 initrd=/boot/initrd.splash
> console=tty0 console=ttyS0,115200

This is the interesting part. Are you sure FILO views your disk
(CF card?) as hda1? Is your /boot an extra partition (mount point) or is
it part of the "/" filesystem on hda1?

Are you sure Linux views your disk (CF card?) as /dev/sda1? Did you try
/dev/sdb1?

The dmesg from below says:
  Kernel command line: BOOT_IMAGE=Zenwalk ro root=801 splash=silent
which is quite different. Where does this stuff come from?

I'd also use "splash=silent" in FILO for now, btw.

Have you tried "root=801" instead of "root=/dev/sda1" in FILO (no idea
what 801 is)?


> hda: LBA 2049MB: SanDisk SDCFX-2048
> Mounted ext2fs
> Found Linux version 2.6.18.2-34-default (geeko at buildhost) #1 SMP Mon Nov
> 27 11:46:27 UTC 2006 bzImage.
> Loading kernel... ok
> Loading initrd... ok
> Jumping to entry point...
> Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
> 20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006

Looks good in theory.


> RAMDISK: Couldn't find valid RAM disk image starting at 0.

Hm, doesn't look too good, but this also contradicts the
"Loading initrd... ok" above.


> VFS: Cannot open root device "sda1" or unknown-block(0,0)
> Please append a correct "root=" boot option
> Kernel panic - not syncing: VFS: Unable to mount root fs on
> unknown-block(0,0)

This is your problem. The "root=" line seems to be wrong, thus Linux
cannot find/mount the "/" filesystem.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Tue Apr  1 17:51:53 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Apr 2008 17:51:53 +0200
Subject: [coreboot] r3206
	-	trunk/coreboot-v2/src/southbridge/intel/i82801db
In-Reply-To: <E1JgWSy-0005Bx-PA@mi015.mc1.hosteurope.de>
References: <E1JgWSy-0005Bx-PA@mi015.mc1.hosteurope.de>
Message-ID: <20080401155153.GE19364@greenwood>

On Tue, Apr 01, 2008 at 04:42:52AM +0200, svn at coreboot.org wrote:
> Author: eswierk
> Date: 2008-04-01 04:42:52 +0200 (Tue, 01 Apr 2008)
> New Revision: 3206
> 
> Removed:
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c

This looks incomplete, there are a lot of files left:

i82801db_ehci.c
i82801db.h
i82801db_ide.c
i82801db_lpc.c
i82801db_pci.c
i82801db_reset.c
i82801db_smbus.c
i82801db_smbus.h
i82801db_uhci.c
i82801db_watchdog.c


Unless I'm missing something, please do another 'svn rm' on the whole
directory, i.e.

 $ svn rm src/southbridge/intel/i82801db
 $ svn ci src/southbridge/intel/i82801db

with the same Signed-off-by's and Acked-by's.


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From svn at coreboot.org  Tue Apr  1 17:56:20 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 15:56:20 -0000
Subject: [coreboot]  #93: Add a gcc wrapper script
Message-ID: <039.a6fac295e9c6dfed6753504a0e1757ce@coreboot.org>

#93: Add a gcc wrapper script
---------------------------------+------------------------------------------
   Reporter:  uwe                |          Owner:  somebody
       Type:  defect             |         Status:  new     
   Priority:  major              |      Milestone:          
  Component:  libpayload         |        Version:          
   Keywords:                     |   Dependencies:          
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 libpayload should have a gcc wrapper script which simplifies compilation
 of libpayload-based payloads a lot. From a user's (payload writer's)
 perspective compiling a payload should be as simple as replacing "CC=gcc"
 with "CC=lpgcc" in the Makefile, everything else should be handled by the
 script (include paths, linker options, etc).

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/93>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:08:30 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:08:30 -0000
Subject: [coreboot] #7: Doesn't seem to be able to write on ICH-2 (maybe
 other ICH-x) mainboards
In-Reply-To: <039.d9cd67cad69f9ca45056f706b0d02e56@coreboot.org>
References: <039.d9cd67cad69f9ca45056f706b0d02e56@coreboot.org>
Message-ID: <048.19bfb34aacdf2b6a6546b6ca0c3b01ed@coreboot.org>

#7: Doesn't seem to be able to write on ICH-2 (maybe other ICH-x) mainboards
-------------------------+--------------------------------------------------
    Reporter:  uwe       |         Owner:  uwe              
        Type:  defect    |        Status:  new              
    Priority:  critical  |     Milestone:                   
   Component:  flashrom  |       Version:                   
  Resolution:            |      Keywords:                   
Dependencies:            |   Patchstatus:  there is no patch
-------------------------+--------------------------------------------------
Changes (by uwe):

  * patchstatus:  => there is no patch
  * version:  v2 =>
  * summary:  flashrom: Doesn't seem to be able to write on ICH-2 (maybe
              other ICH-x) mainboards => Doesn't seem to be
              able to write on ICH-2 (maybe other ICH-x)
              mainboards

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/7#comment:4>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:10:57 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:10:57 -0000
Subject: [coreboot] #75: xslt error with trunk
In-Reply-To: <064.57f92317fab3e0a3bdda679cb9b080dd@coreboot.org>
References: <064.57f92317fab3e0a3bdda679cb9b080dd@coreboot.org>
Message-ID: <073.c1becf2d113c61126e73f8141d21c78a@coreboot.org>

#75: xslt error with trunk
---------------------------------------------+------------------------------
    Reporter:  twisti at complang.tuwien.ac.at  |         Owner:  somebody         
        Type:  defect                        |        Status:  reopened         
    Priority:  major                         |     Milestone:                   
   Component:  toolchain                     |       Version:  v2               
  Resolution:                                |      Keywords:                   
Dependencies:                                |   Patchstatus:  there is no patch
---------------------------------------------+------------------------------
Changes (by uwe):

  * component:  code => toolchain

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/75#comment:3>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:13:00 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:13:00 -0000
Subject: [coreboot] #17: clean up linuxbios table handling
In-Reply-To: <042.4293d2966ab6d77c8dfc146e8375611e@coreboot.org>
References: <042.4293d2966ab6d77c8dfc146e8375611e@coreboot.org>
Message-ID: <051.298bc806cd6e11ad966e3ea809ad2578@coreboot.org>

#17: clean up linuxbios table handling
-----------------------+----------------------------------------------------
    Reporter:  stepan  |         Owner:  stepan          
        Type:  task    |        Status:  new             
    Priority:  major   |     Milestone:                  
   Component:  code    |       Version:  v2              
  Resolution:          |      Keywords:  lbtable         
Dependencies:          |   Patchstatus:  patch needs work
-----------------------+----------------------------------------------------
Changes (by uwe):

  * patchstatus:  => patch needs work

Comment:

 What's the status of this patch? Is it still needed?

 It needs an update for (at least) s/LinuxBIOS/coreboot/ and it needs a
 Signed-off-by.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/17#comment:1>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:14:16 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:14:16 -0000
Subject: [coreboot] #12: Make LinuxBIOS work on a laptop
In-Reply-To: <039.22f37b7604388563f8bf993f91062156@coreboot.org>
References: <039.22f37b7604388563f8bf993f91062156@coreboot.org>
Message-ID: <048.786dd5b94489434445ad7891b3e73573@coreboot.org>

#12: Make LinuxBIOS work on a laptop
----------------------+-----------------------------------------------------
    Reporter:  uwe    |         Owner:  somebody         
        Type:  task   |        Status:  new              
    Priority:  major  |     Milestone:  Going mainstream 
   Component:  code   |       Version:                   
  Resolution:         |      Keywords:                   
Dependencies:         |   Patchstatus:  there is no patch
----------------------+-----------------------------------------------------
Changes (by uwe):

  * patchstatus:  => there is no patch
  * component:  misc => code
  * version:  v2 =>

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/12#comment:2>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:14:38 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:14:38 -0000
Subject: [coreboot] #80: serial console in grub2 works
In-Reply-To: <043.299c51cc9688868e047901396ec61592@coreboot.org>
References: <043.299c51cc9688868e047901396ec61592@coreboot.org>
Message-ID: <052.e18a2963d2b4040db91ad89190066398@coreboot.org>

#80: serial console in grub2 works
----------------------------+-----------------------------------------------
    Reporter:  oxygene      |         Owner:  oxygene               
        Type:  enhancement  |        Status:  reopened              
    Priority:  major        |     Milestone:  Port GRUB2 to coreboot
   Component:  grub2        |       Version:                        
  Resolution:               |      Keywords:                        
Dependencies:               |   Patchstatus:  patch needs review    
----------------------------+-----------------------------------------------
Changes (by uwe):

  * version:  v3 =>
  * component:  code => grub2

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/80#comment:7>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:15:31 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:15:31 -0000
Subject: [coreboot] #23: Use Doxygen-style comments
In-Reply-To: <039.caac1314ab6bf455b33410aad11404fc@coreboot.org>
References: <039.caac1314ab6bf455b33410aad11404fc@coreboot.org>
Message-ID: <048.612578805cba42be9a9ac01c62d9f7c5@coreboot.org>

#23: Use Doxygen-style comments
----------------------------+-----------------------------------------------
    Reporter:  uwe          |         Owner:  somebody         
        Type:  enhancement  |        Status:  new              
    Priority:  minor        |     Milestone:  Cosmetic fixes   
   Component:  code         |       Version:                   
  Resolution:               |      Keywords:                   
Dependencies:               |   Patchstatus:  there is no patch
----------------------------+-----------------------------------------------
Changes (by uwe):

  * patchstatus:  => there is no patch
  * version:  v2 =>

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/23#comment:3>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:15:46 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:15:46 -0000
Subject: [coreboot] #65: Unify SuperIO code?
In-Reply-To: <042.4c35da7f5849433efc493d628888131d@coreboot.org>
References: <042.4c35da7f5849433efc493d628888131d@coreboot.org>
Message-ID: <051.f525bf5aff2abfc6dbf988b300f21a02@coreboot.org>

#65: Unify SuperIO code?
----------------------------+-----------------------------------------------
    Reporter:  stepan       |         Owner:  somebody         
        Type:  enhancement  |        Status:  new              
    Priority:  major        |     Milestone:  Cosmetic fixes   
   Component:  code         |       Version:                   
  Resolution:               |      Keywords:                   
Dependencies:               |   Patchstatus:  there is no patch
----------------------------+-----------------------------------------------
Changes (by uwe):

  * priority:  minor => major
  * version:  v2 =>

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/65#comment:2>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:18:05 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:18:05 -0000
Subject: [coreboot] #48: Ready-made,
 downloadable QEMU images with various payloads
In-Reply-To: <039.0282e3171a966f5fdae756200803e9c0@coreboot.org>
References: <039.0282e3171a966f5fdae756200803e9c0@coreboot.org>
Message-ID: <048.f1a43fe24ced38a8d5c8428ad4e3407b@coreboot.org>

#48: Ready-made, downloadable QEMU images with various payloads
-------------------------------------+--------------------------------------
    Reporter:  uwe                   |         Owner:  uwe              
        Type:  enhancement           |        Status:  assigned         
    Priority:  critical              |     Milestone:  Going mainstream 
   Component:  wiki/website/tracker  |       Version:                   
  Resolution:                        |      Keywords:                   
Dependencies:                        |   Patchstatus:  there is no patch
-------------------------------------+--------------------------------------
Changes (by uwe):

  * owner:  somebody => uwe
  * status:  new => assigned
  * version:  v2 =>

Comment:

 Partly done, see http://www.coreboot.org/QEMU#Ready-made_QEMU_images.

 When we have a few more QEMU images on that page (with FILO, Linux, GRUB2,
 etc) we can close this issue.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/48#comment:2>
coreboot <http://www.coreboot.org/>

From svn at coreboot.org  Tue Apr  1 18:20:53 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 16:20:53 -0000
Subject: [coreboot] #76: LinuxBIOS messages should be accessible in dmesg
In-Reply-To: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
References: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
Message-ID: <051.2423ea89b804a1ca5e26c322b5ce4df1@coreboot.org>

#76: LinuxBIOS messages should be accessible in dmesg
-------------------------+--------------------------------------------------
    Reporter:  stepan    |         Owner:  rminnich               
        Type:  defect    |        Status:  new                    
    Priority:  major     |     Milestone:  Setting up LinuxBIOS v3
   Component:  coreboot  |       Version:  v3                     
  Resolution:            |      Keywords:                         
Dependencies:            |   Patchstatus:  there is no patch      
-------------------------+--------------------------------------------------
Comment (by uwe):

 Untested yet by me, but it looks like this is (partly?) implemented in
 r590.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/76#comment:1>
coreboot <http://www.coreboot.org/>

From uwe at hermann-uwe.de  Tue Apr  1 18:48:06 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 1 Apr 2008 18:48:06 +0200
Subject: [coreboot] Issue tracker -- list issues by component
Message-ID: <20080401164806.GA32299@greenwood>

Hi,

I've added a new "report" to trac which allows you to view issues sorted
by component:

  http://tracker.coreboot.org/trac/coreboot/report/10

I've also re-assigned a few issues to their proper component as good as I
could, but some may still need to be re-arranged. There are now
components for pretty much all relevant parts of the coreboot "family",
including filo, grub2, coreinfo, libpayload, coreboot (v2 or v3),
mkelfimage, flashrom, superiotool, wiki/website/tracker, toolchain etc.

If you think a component is missing, please let me know so I can add it.


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From eswierk at arastra.com  Tue Apr  1 18:53:13 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Tue, 1 Apr 2008 09:53:13 -0700
Subject: [coreboot] r3206 -
	trunk/coreboot-v2/src/southbridge/intel/i82801db
In-Reply-To: <20080401155153.GE19364@greenwood>
References: <E1JgWSy-0005Bx-PA@mi015.mc1.hosteurope.de>
	<20080401155153.GE19364@greenwood>
Message-ID: <e6c711510804010953l342a91bfof831bfb71262e94b@mail.gmail.com>

On Tue, Apr 1, 2008 at 8:51 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
>  This looks incomplete, there are a lot of files left:
>
>  i82801db_ehci.c
>  i82801db.h
>  i82801db_ide.c
>  i82801db_lpc.c
>  i82801db_pci.c
>  i82801db_reset.c
>  i82801db_smbus.c
>  i82801db_smbus.h
>  i82801db_uhci.c
>  i82801db_watchdog.c

Oops! I need to put my svn hat on again.

--Ed



From peter at stuge.se  Tue Apr  1 19:05:10 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 1 Apr 2008 19:05:10 +0200
Subject: [coreboot] Device mapping problem
In-Reply-To: <20080401154556.GD19364@greenwood>
	<39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
	<20080401154556.GD19364@greenwood>
	<39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
Message-ID: <20080401170510.4888.qmail@stuge.se>

On Tue, Apr 01, 2008 at 01:55:34PM +0200, Klaus Stammermann wrote:
> At first I can't boot my system with coreboot yet.

The initrd is still not found or loaded correctly.


> Here log of coreboot booting out of ttyS0:
..
> FILO version 0.5 (klausst at thor) Mon Mar 31 14:56:38 CEST 2008
> No sound device found
> boot: hda1:/boot/vmlinuz root=/dev/sda1 initrd=/boot/initrd.splash
> console=tty0 console=ttyS0,115200
> hda: LBA 2049MB: SanDisk SDCFX-2048
> Mounted ext2fs
> Found Linux version 2.6.18.2-34-default (geeko at buildhost) #1 SMP Mon Nov
> 27 11:46:27 UTC 2006 bzImage.
> Loading kernel... ok
> Loading initrd... ok
> Jumping to entry point...
> Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
> 20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006

This output shows FILO booting the kernel /boot/vmlinuz, and
supposedly loading /boot/initrd.splash as initrd, on the first
partition of the 2GB CF card.

..

> md: Autodetecting RAID arrays.
> Time: tsc clocksource has been installed.
> md: autorun ...
> md: ... autorun DONE.
> RAMDISK: Couldn't find valid RAM disk image starting at 0.

However that kernel does not consider the initrd to be valid.


> VFS: Cannot open root device "sda1" or unknown-block(0,0)

And since there is no ATA driver built-in to your kernel, the kernel
can't find the root partition.


> And here /var/log/messages with original bios:

This is much like comparing apples with oranges. Please always use
the same method to collect debugging information. In this case that
means logging serial output also when booting with the factory BIOS.

syslog does not get all relevant output.


> Apr  1 11:37:13 (none) kernel: klogd 1.4.1, log source = /proc/kmsg started.
> Apr  1 11:37:13 (none) kernel: Linux version 2.6.22.9 (root at zenwalk) (gcc
> version 4.1.2) #1 SMP PREEMPT Sat Sep 29 22:22:07 CEST 2007

This is a different kernel from the one that FILO is trying to boot.


..
> Apr  1 11:37:13 (none) kernel: TCP reno registered
> Apr  1 11:37:13 (none) kernel: checking if image is initramfs...it isn't
> (bad gzip magic numbers); looks like an initrd
> Apr  1 11:37:13 (none) kernel: Freeing initrd memory: 622k freed

Now the initrd starts exeucting.


..
> Apr  1 11:37:13 (none) kernel: PPP generic driver version 2.4.2
> Apr  1 11:37:13 (none) kernel: ACPI: PCI Interrupt 0000:00:11.1[A] -> Link
> [LNKA] -> GSI 11 (level, low) -> IRQ 11
> Apr  1 11:37:13 (none) kernel: PCI: VIA VLink IRQ fixup for 0000:00:11.1,
> from 255 to 11
> Apr  1 11:37:14 (none) kernel: scsi0 : pata_via
> Apr  1 11:37:14 (none) kernel: scsi1 : pata_via
> Apr  1 11:37:14 (none) kernel: ata1: PATA max UDMA/133 cmd 0x000101f0 ctl
> 0x000103f6 bmdma 0x0001e000 irq 14
> Apr  1 11:37:14 (none) kernel: ata2: PATA max UDMA/133 cmd 0x00010170 ctl
> 0x00010376 bmdma 0x0001e008 irq 15

And during that time the pata_via driver is loaded, which finds your
PATA controller..


> Apr  1 11:37:14 (none) kernel: ata1.00: CFA: SanDisk SDCFX-2048, HDX 4.04,
> max UDMA/66
> Apr  1 11:37:14 (none) kernel: ata1.00: 4001760 sectors, multi 0: LBA
> Apr  1 11:37:14 (none) kernel: ata1.00: configured for UDMA/33

..which has the CF card connected..


> Apr  1 11:37:14 (none) kernel: scsi 0:0:0:0: Direct-Access     ATA     
> SanDisk SDCFX-20 HDX  PQ: 0 ANSI: 5
> Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] 4001760 512-byte hardware
> sectors (2049 MB)
> Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write Protect is off
> Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write cache: disabled,
> read cache: enabled, doesn't support DPO or FUA
> Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] 4001760 512-byte hardware
> sectors (2049 MB)
> Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write Protect is off
> Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Write cache: disabled,
> read cache: enabled, doesn't support DPO or FUA
> Apr  1 11:37:14 (none) kernel:  sda: sda1
> Apr  1 11:37:14 (none) kernel: sd 0:0:0:0: [sda] Attached SCSI removable disk

..which is made available as /dev/sda using this particular kernel.


..
> Apr  1 11:37:14 (none) kernel: md: Autodetecting RAID arrays.
> Apr  1 11:37:14 (none) kernel: md: autorun ...
> Apr  1 11:37:14 (none) kernel: md: ... autorun DONE.
> Apr  1 11:37:14 (none) kernel: RAMDISK: Couldn't find valid RAM disk image
> starting at 0.
> Apr  1 11:37:14 (none) kernel: Freeing unused kernel memory: 228k freed
> Apr  1 11:37:14 (none) kernel: Linux agpgart interface v0.102 (c) Dave Jones

This last line shows that the root partition was mounted correctly.


..
> Apr  1 11:37:15 (none) logger: /etc/rc.d/rc.inet1:  /sbin/ifconfig lo
> 127.0.0.1

..and this is way into the boot scripts, which are irrelevant for the
problem.


On Tue, Apr 01, 2008 at 05:45:56PM +0200, Uwe Hermann wrote:
> > There are two differences I think that could be a problem.
> > At first there are two different size of memory detected:
> > coreboot: 222822k/229376k
> > origianl bios: 222384k/229312k
> 
> Not a problem, I think.

Correct, this is not a problem. Slightly more RAM is available using
coreboot. This is intentional and expected.


> > boot: hda1:/boot/vmlinuz root=/dev/sda1 initrd=/boot/initrd.splash
> > console=tty0 console=ttyS0,115200
> 
> This is the interesting part. Are you sure FILO views your disk
> (CF card?) as hda1?

Yes, his FILO does, according to the hda: blurb below.


> Is your /boot an extra partition (mount point) or is it part of the
> "/" filesystem on hda1?

Any way, the kernel FILO is booting is not the same kernel that gets
started when booting the factory BIOS.


> Are you sure Linux views your disk (CF card?) as /dev/sda1? Did you
> try /dev/sdb1?

/dev/sda1 will be correct but neither of the two kernels he has shown
logs from have the pata_via driver built-in and will never be able
to boot his system without the help of an initrd.


> Have you tried "root=801" instead of "root=/dev/sda1" in FILO (no
> idea what 801 is)?

The root kernel parameter accepts both device number and name.

0801 == major 8 minor 1 == /dev/sda1


> > Loading initrd... ok
..
> > RAMDISK: Couldn't find valid RAM disk image starting at 0.
> 
> Hm, doesn't look too good, but this also contradicts the
> "Loading initrd... ok" above.

The initrd loading does not check the initrd in any way, "ok" means
that the file was loaded successfully from the ATA device and nothing
more.


> > VFS: Cannot open root device "sda1" or unknown-block(0,0)
> 
> This is your problem. The "root=" line seems to be wrong, thus
> Linux cannot find/mount the "/" filesystem.

I now suggest for the third or fourth time that the problem is that
the kernel that is booted by FILO does not have the neccessary
drivers for the kernel to find and mount the root partition.

The way I prefer to accomplish this is the simplest method available
and therefore also what I consider the most most reliable and
deterministic:

Please please build a custom kernel with zero modules and make sure
to include the pata_via driver, so that your ATA device is found
without the help of a silly ramdisk. Expect to spend a few hours
going through the kernel configuration if you have never done so
before.


Another option is to make sure that FILO loads exactly the same
kernel and initrd as when you're booting with the factory BIOS.
Please investigate how the bootloader that is used then is
configured. For LILO a copy of the configuration is usually stored in
/etc/lilo.conf, for GRUB I don't know; I don't like GRUB. :)


//Peter



From svn at coreboot.org  Tue Apr  1 19:05:23 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  1 Apr 2008 19:05:23 +0200
Subject: [coreboot] r3208 - trunk/coreboot-v2/src/southbridge/intel
Message-ID: <mailman.1357.1355071293.16123.coreboot@coreboot.org>

Author: eswierk
Date: 2008-04-01 19:05:22 +0200 (Tue, 01 Apr 2008)
New Revision: 3208

Removed:
   trunk/coreboot-v2/src/southbridge/intel/i82801db/
Log:
Remove i82801DB files that I meant to delete in r3206.

Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Ed Swierk <eswierk at arastra.com>






From peter at stuge.se  Tue Apr  1 19:08:21 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 1 Apr 2008 19:08:21 +0200
Subject: [coreboot] #76: LinuxBIOS messages should be accessible in dmesg
In-Reply-To: <051.2423ea89b804a1ca5e26c322b5ce4df1@coreboot.org>
References: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
	<051.2423ea89b804a1ca5e26c322b5ce4df1@coreboot.org>
Message-ID: <20080401170821.6406.qmail@stuge.se>

On Tue, Apr 01, 2008 at 04:20:53PM -0000, coreboot wrote:
> Comment (by uwe):
> 
>  Untested yet by me, but it looks like this is (partly?) implemented in
>  r590.

I believe Ron has code to do a special trick in order to make this
happen.


//Peter



From svn at coreboot.org  Tue Apr  1 19:14:57 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  1 Apr 2008 19:14:57 +0200
Subject: [coreboot] r3209 - trunk/coreboot-v2/src/southbridge/intel/i3100
Message-ID: <mailman.1358.1355071293.16123.coreboot@coreboot.org>

Author: eswierk
Date: 2008-04-01 19:14:57 +0200 (Tue, 01 Apr 2008)
New Revision: 3209

Modified:
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c
Log:
Setting an integrated southbridge device (like SATA or USB2.0) to
"off" in Config.lb should cause the PCI device not to respond to
configuration requests.

Replace the existing code that I naively copied from esb6300 with
something that actually works on the 3100.

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c	2008-04-01 17:05:22 UTC (rev 3208)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c	2008-04-01 17:14:57 UTC (rev 3209)
@@ -18,52 +18,45 @@
  *
  */
 
-/* This code is based on src/southbridge/intel/esb6300/esb6300.c */
-
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include "i3100.h"
 
 void i3100_enable(device_t dev)
 {
 	device_t lpc_dev;
-	u32 index = 0;
-	u16 reg_old, reg;
+	u8 func;
+	volatile u32 *disable;
 
-	/* See if we are behind the i3100 PCI bridge */
-	lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
-	if ((dev->path.u.pci.devfn & 0xf8) == 0xf8) {
-		index = dev->path.u.pci.devfn & 7;
-	}
-	else if ((dev->path.u.pci.devfn & 0xf8) == 0xe8) {
-		index = (dev->path.u.pci.devfn & 7) + 8;
-	}
-	if ((!lpc_dev) || (index >= 16) || ((1 << index) & 0x3091)) {
+	if (dev->enabled)
 		return;
-	}
-	if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
-		(lpc_dev->device != PCI_DEVICE_ID_INTEL_3100_LPC)) {
-		u32 id;
-		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
-		if (id != (PCI_VENDOR_ID_INTEL |
-				(PCI_DEVICE_ID_INTEL_3100_LPC << 16))) {
-			return;
-		}
-	}
 
-	reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
-	reg &= ~(1 << index);
-	if (!dev->enabled) {
-		reg |= (1 << index);
+	/*
+	 * To disable an integrated southbridge device, set the corresponding
+	 * flag in the Function Disable register.
+	 */
+
+	/* Temporarily enable the root complex register block at 0xa0000000. */
+	lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0));
+	pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0));
+	disable = (volatile u32 *) 0xa0003418;
+	func = PCI_FUNC(dev->path.u.pci.devfn);
+	switch (PCI_SLOT(dev->path.u.pci.devfn)) {
+	case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */
+		*disable |= (1 << (func == 0x0 ? 14 : func));
+		break;
+	case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */
+		*disable |= (1 << (func + 8));
+		break;
+	case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */
+		*disable |= (1 << (func + 16));
+		break;
 	}
-	if (reg != reg_old) {
-		pci_write_config16(lpc_dev, 0xf2, reg);
-	}
+	/* Disable the root complex register block. */
+	pci_write_config32(lpc_dev, 0xf0, 0);
 }
 
 struct chip_operations southbridge_intel_i3100_ops = {
 	CHIP_NAME("Intel 3100 Southbridge")
-	.enable_dev = i3100_enable,
 };

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c	2008-04-01 17:05:22 UTC (rev 3208)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c	2008-04-01 17:14:57 UTC (rev 3209)
@@ -72,18 +72,19 @@
 	.enable_resources = pci_dev_enable_resources,
 	.init             = sata_init,
 	.scan_bus         = 0,
+	.enable           = i3100_enable,
 	.ops_pci          = &lops_pci,
 };
 
 static struct pci_driver sata_driver __pci_driver = {
-        .ops    = &sata_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_3100_SATA,
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_SATA,
 };
 
 static struct pci_driver sata_driver_nr __pci_driver = {
-        .ops    = &sata_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_3100_SATA_R,
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_SATA_R,
 };
 




From svn at coreboot.org  Tue Apr  1 19:30:53 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 17:30:53 -0000
Subject: [coreboot] #76: LinuxBIOS messages should be accessible in dmesg
In-Reply-To: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
References: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
Message-ID: <051.dfe560d4dbd489481e58a5124add7d96@coreboot.org>

#76: LinuxBIOS messages should be accessible in dmesg
----------------------------+-----------------------------------------------
    Reporter:  stepan       |         Owner:  rminnich               
        Type:  enhancement  |        Status:  new                    
    Priority:  major        |     Milestone:  Setting up LinuxBIOS v3
   Component:  coreboot     |       Version:  v3                     
  Resolution:               |      Keywords:                         
Dependencies:               |   Patchstatus:  there is no patch      
----------------------------+-----------------------------------------------
Changes (by hailfinger):

  * type:  defect => enhancement

Comment:

 I implemented the buffer in r590, but the payload has to know a hardcoded
 buffer address to read the message buffer.
 There is no explicit mechanism for passing the log buffer address to a
 payload.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/76#comment:2>
coreboot <http://www.coreboot.org/>

From joe at smittys.pointclark.net  Tue Apr  1 21:32:58 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Tue, 01 Apr 2008 15:32:58 -0400
Subject: [coreboot] #7: Doesn't seem to be able to write on ICH-2	(maybe
	other ICH-x) mainboards
In-Reply-To: <048.19bfb34aacdf2b6a6546b6ca0c3b01ed@coreboot.org>
References: <039.d9cd67cad69f9ca45056f706b0d02e56@coreboot.org>
	<048.19bfb34aacdf2b6a6546b6ca0c3b01ed@coreboot.org>
Message-ID: <20080401153258.60fmafuk0skk84ws@www.smittys.pointclark.net>

Quoting coreboot <svn at coreboot.org>:

> #7: Doesn't seem to be able to write on ICH-2 (maybe other ICH-x) mainboards
> -------------------------+--------------------------------------------------
>     Reporter:  uwe       |         Owner:  uwe
>         Type:  defect    |        Status:  new
>     Priority:  critical  |     Milestone:
>    Component:  flashrom  |       Version:
>   Resolution:            |      Keywords:
> Dependencies:            |   Patchstatus:  there is no patch
> -------------------------+--------------------------------------------------
> Changes (by uwe):
>
>   * patchstatus:  => there is no patch
>   * version:  v2 =>
>   * summary:  flashrom: Doesn't seem to be able to write on ICH-2 (maybe
>               other ICH-x) mainboards => Doesn't seem to be
>               able to write on ICH-2 (maybe other ICH-x)
>               mainboards
>
> --
> Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/7#comment:4>
>
I have flashrom working in the ICH4 just fine....the problem I  
encountered was with the fimware chip itself, not the southbridge.  
Maybe that helps someone?

Thanks - Joe



From svn at coreboot.org  Wed Apr  2 01:20:01 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 01 Apr 2008 23:20:01 -0000
Subject: [coreboot]  #94: Need getch_timeout() function in libpayload
Message-ID: <043.f42852caf92595083545f38a71f89c44@coreboot.org>

#94: Need getch_timeout() function in libpayload
---------------------------------+------------------------------------------
   Reporter:  jcrouse            |          Owner:  jcrouse
       Type:  defect             |         Status:  new    
   Priority:  major              |      Milestone:         
  Component:  libpayload         |        Version:  v2     
   Keywords:                     |   Dependencies:         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 libpayload needs a getch_timeout() function that will gracefully return
 after a certain amount of time if a keypress isn't received.  This is used
 to update the screen at constant intervals.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/94>
coreboot <http://www.coreboot.org/>

From klaus123 at ibnoetzold.de  Wed Apr  2 08:39:28 2008
From: klaus123 at ibnoetzold.de (Klaus Stammermann)
Date: Wed, 2 Apr 2008 08:39:28 +0200 (CEST)
Subject: [coreboot] Device mapping problem
In-Reply-To: <20080401154556.GD19364@greenwood>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
	<20080401154556.GD19364@greenwood>
Message-ID: <4991.213.61.222.30.1207118368.squirrel@www.ibnoetzold.de>

Hi

> On Tue, Apr 01, 2008 at 01:55:34PM +0200, Klaus Stammermann wrote:
>> At first I can't boot my system with coreboot yet. I changed kernel
>> params
>> so initrd now will be loaded. Used kernel params are now same as in lilo
>> of original system.
>
> What does 'cat /proc/cmdline' on the same disk (but booted with the
> original BIOS) say?
On Monday I will look at this. Now I can't try anything because I am away
on business.

>> There are two differences I think that could be a problem. At first
>> there
>> are two different size of memory detected:
>> coreboot: 222822k/229376k
>> origianl bios: 222384k/229312k
>
> Not a problem, I think.
>
I think it looks not normal. But ok maybe other changes will solve my
problem.

>> And of course on original bios system DMI 2.2 is started. On coreboot
>> DMI
>> is not present or is invalid.
>
> Not a problem, either. coreboot doesn't provide DMI (not needed).
>
OK

>> I would set ram size to 0x40000 Kbytes
>
> Do you have 256MB of RAM, is that correct?
>
Yes, I have 256MB.

>> Enabling VIA IDE.
>> ide_init: enabling compatibility IDE addresses
>
> Looks ok.
>
>
>> FILO version 0.5 (klausst at thor) Mon Mar 31 14:56:38 CEST 2008
>
> Looks ok.
>
>
>> boot: hda1:/boot/vmlinuz root=/dev/sda1 initrd=/boot/initrd.splash
>> console=tty0 console=ttyS0,115200
>
> This is the interesting part. Are you sure FILO views your disk
> (CF card?) as hda1? Is your /boot an extra partition (mount point) or is
> it part of the "/" filesystem on hda1?
>
> Are you sure Linux views your disk (CF card?) as /dev/sda1? Did you try
> /dev/sdb1?
>
I think the CF card on an IDE adapter is hda1. First parameter
(hda1:/boot/vmlinuz) shows where kernel is. Because of loading it I think
this should be the correct device name.

> The dmesg from below says:
>   Kernel command line: BOOT_IMAGE=Zenwalk ro root=801 splash=silent
> which is quite different. Where does this stuff come from?
>
> I'd also use "splash=silent" in FILO for now, btw.
>
> Have you tried "root=801" instead of "root=/dev/sda1" in FILO (no idea
> what 801 is)?
>
I didn't try that but I will do it. I wondered about this parameter, too.
Of course I should look for this and what this is for.

>> hda: LBA 2049MB: SanDisk SDCFX-2048
>> Mounted ext2fs
>> Found Linux version 2.6.18.2-34-default (geeko at buildhost) #1 SMP Mon Nov
>> 27 11:46:27 UTC 2006 bzImage.
>> Loading kernel... ok
>> Loading initrd... ok
>> Jumping to entry point...
>> Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
>> 20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006
>
> Looks good in theory.
>
>
>> RAMDISK: Couldn't find valid RAM disk image starting at 0.
>
> Hm, doesn't look too good, but this also contradicts the
> "Loading initrd... ok" above.
>
>
>> VFS: Cannot open root device "sda1" or unknown-block(0,0)
>> Please append a correct "root=" boot option
>> Kernel panic - not syncing: VFS: Unable to mount root fs on
>> unknown-block(0,0)
>
> This is your problem. The "root=" line seems to be wrong, thus Linux
> cannot find/mount the "/" filesystem.
>
Thank you for your help. I know that this is my problem, but I don't know
what is wrong and how I should configure this. I will try your tips and
post the results here.

Greeting
Klaus



From nikolaypetukhov at gmail.com  Wed Apr  2 08:51:16 2008
From: nikolaypetukhov at gmail.com (Nikolay Petukhov)
Date: Wed, 2 Apr 2008 12:51:16 +0600
Subject: [coreboot] PCI irq routing
In-Reply-To: <47EE8113.3060009@gmx.net>
References: <e24af7500803140353i1b5e1d2bu24d971c9eb362bd@mail.gmail.com>
	<20080314170606.GC24454@greenwood>
	<e24af7500803170034t7cf08af7x278ccf26977e423@mail.gmail.com>
	<20080329170051.GD10794@greenwood> <47EE8113.3060009@gmx.net>
Message-ID: <e24af7500804012351w13860a2cy2a164a9ce2437d18@mail.gmail.com>

2008/3/29, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>:
> What's the PCI IRQ routing status of v2 and v3? Does one of them have an
>  advantage over the other?
>
>  Regards,
>
> Carl-Daniel
>


PCI IRQ routing of v2 support two platforms - AMD/LX and AMD/GX1.
PCI IRQ routing of v3 support only one platform - AMD/LX.

-- 
Nikolay



From svn at coreboot.org  Wed Apr  2 12:20:33 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 02 Apr 2008 10:20:33 -0000
Subject: [coreboot] #76: LinuxBIOS messages should be accessible in dmesg
In-Reply-To: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
References: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
Message-ID: <051.ab5ece6ea056599616b3c1c41a3b8b66@coreboot.org>

#76: LinuxBIOS messages should be accessible in dmesg
----------------------------+-----------------------------------------------
    Reporter:  stepan       |         Owner:  rminnich               
        Type:  enhancement  |        Status:  new                    
    Priority:  major        |     Milestone:  Setting up LinuxBIOS v3
   Component:  coreboot     |       Version:  v3                     
  Resolution:               |      Keywords:                         
Dependencies:               |   Patchstatus:  there is no patch      
----------------------------+-----------------------------------------------
Comment (by anonymous):

 No. The code in r590 only creates infrastructure within coreboot. Someone
 on the uboot mailing list stated that you have to change the linux kernel
 to know where to look for the buffer (and potentially check the format,
 not sure). This (at least a pointer to the log) should be passed in the
 coreboot table.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/76#comment:3>
coreboot <http://www.coreboot.org/>

From stepan at coresystems.de  Wed Apr  2 12:29:51 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 02 Apr 2008 04:29:51 -0600
Subject: [coreboot] Device mapping problem
In-Reply-To: <20080401154556.GD19364@greenwood>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
	<20080401154556.GD19364@greenwood>
Message-ID: <47F3601F.3060706@coresystems.de>

Uwe Hermann wrote:
>> And of course on original bios system DMI 2.2 is started. On coreboot DMI
>> is not present or is invalid.
>>     
>
> Not a problem, either. coreboot doesn't provide DMI (not needed).
>
>   
That's not entirely true anymore. Nowadays Linux disables ACPI if DMI is 
not present. That results mostl likely in interrupts not working anymore.

Klaus, can you try acpi=force on the kernel command line and see if that 
helps?

I have a DMI implementation in one of my trees that will be merged with 
the next major patch.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From klaus123 at ibnoetzold.de  Wed Apr  2 12:42:11 2008
From: klaus123 at ibnoetzold.de (Klaus Stammermann)
Date: Wed, 2 Apr 2008 12:42:11 +0200 (CEST)
Subject: [coreboot] Device mapping problem
In-Reply-To: <47F3601F.3060706@coresystems.de>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
	<20080401154556.GD19364@greenwood> <47F3601F.3060706@coresystems.de>
Message-ID: <4241.213.61.222.30.1207132931.squirrel@www.ibnoetzold.de>


> Uwe Hermann wrote:
>>> And of course on original bios system DMI 2.2 is started. On coreboot
>>> DMI
>>> is not present or is invalid.
>>>
>>
>> Not a problem, either. coreboot doesn't provide DMI (not needed).
>>
>>
> That's not entirely true anymore. Nowadays Linux disables ACPI if DMI is
> not present. That results mostl likely in interrupts not working anymore.
>
> Klaus, can you try acpi=force on the kernel command line and see if that
> helps?
>
> I have a DMI implementation in one of my trees that will be merged with
> the next major patch.
>
> Stefan
>
> --
> coresystems GmbH ??? Brahmsstr. 16 ??? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ??? Fax: +49 761 7664613
> Email: info at coresystems.de  ??? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ??? HRB 7656
> Gesch??ftsf??hrer: Stefan Reinauer ??? Ust-IdNr.: DE245674866
>
That's no problem. I will try that kernel parameter and post my results.

Greetings
Klaus



From svn at coreboot.org  Wed Apr  2 14:35:45 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  2 Apr 2008 14:35:45 +0200
Subject: [coreboot] r3210 - in trunk/payloads/libpayload: . include libc
Message-ID: <mailman.1359.1355071293.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-02 14:35:45 +0200 (Wed, 02 Apr 2008)
New Revision: 3210

Modified:
   trunk/payloads/libpayload/LICENSES
   trunk/payloads/libpayload/include/libpayload.h
   trunk/payloads/libpayload/libc/printf.c
Log:
Add missing snprintf() to libc/printf.c (trivial).
This is also taken from the HelenOS project.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/payloads/libpayload/LICENSES
===================================================================
--- trunk/payloads/libpayload/LICENSES	2008-04-01 17:14:57 UTC (rev 3209)
+++ trunk/payloads/libpayload/LICENSES	2008-04-02 12:35:45 UTC (rev 3210)
@@ -78,6 +78,7 @@
           svn checkout svn://svn.helenos.eu/HelenOS/trunk HelenOS
           http://svn.helenos.eu/chora/browse.php?f=%2Ftrunk%2F
   Original files: kernel/generic/src/printf/printf_core.c
+                  kernel/generic/src/printf/snprintf.c
                   kernel/generic/src/printf/sprintf.c
                   kernel/generic/src/printf/vsnprintf.c
                   kernel/generic/src/printf/vsprintf.c

Modified: trunk/payloads/libpayload/include/libpayload.h
===================================================================
--- trunk/payloads/libpayload/include/libpayload.h	2008-04-01 17:14:57 UTC (rev 3209)
+++ trunk/payloads/libpayload/include/libpayload.h	2008-04-02 12:35:45 UTC (rev 3210)
@@ -110,6 +110,7 @@
 int memcmp(const char *s1, const char *s2, size_t len);
 
 /* libc/printf.c */
+int snprintf(char *str, size_t size, const char *fmt, ...);
 int sprintf(char *str, const char *fmt, ...);
 int vsnprintf(char *str, size_t size, const char *fmt, va_list ap);
 int vsprintf(char *str, const char *fmt, va_list ap);

Modified: trunk/payloads/libpayload/libc/printf.c
===================================================================
--- trunk/payloads/libpayload/libc/printf.c	2008-04-01 17:14:57 UTC (rev 3209)
+++ trunk/payloads/libpayload/libc/printf.c	2008-04-02 12:35:45 UTC (rev 3210)
@@ -694,6 +694,18 @@
 	return counter;
 }
 
+int snprintf(char *str, size_t size, const char *fmt, ...)
+{
+	int ret;
+	va_list args;
+
+	va_start(args, fmt);
+	ret = vsnprintf(str, size, fmt, args);
+	va_end(args);
+
+	return ret;
+}
+
 int sprintf(char *str, const char *fmt, ...)
 {
 	int ret;




From svn at coreboot.org  Wed Apr  2 14:51:42 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 02 Apr 2008 12:51:42 -0000
Subject: [coreboot] #76: coreboot messages should be accessible in dmesg
In-Reply-To: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
References: <042.60a952d667de3c73b7b73cb7609e1d7c@coreboot.org>
Message-ID: <051.e4aa6a51ae7e884338573dd9c32d62b9@coreboot.org>

#76: coreboot messages should be accessible in dmesg
----------------------------+-----------------------------------------------
    Reporter:  stepan       |         Owner:  rminnich               
        Type:  enhancement  |        Status:  new                    
    Priority:  major        |     Milestone:  Setting up LinuxBIOS v3
   Component:  coreboot     |       Version:  v3                     
  Resolution:               |      Keywords:                         
Dependencies:               |   Patchstatus:  there is no patch      
----------------------------+-----------------------------------------------
Changes (by uwe):

  * summary:  LinuxBIOS messages should be accessible in dmesg => coreboot
              messages should be accessible in dmesg

Comment:

 FYI, I'll add a coreinfo module which can display (and scroll through) the
 coreboot "dmesg buffer" as part of GSoC (if I'll get accepted). Actually,
 that code is pretty much finished already and works quite nicely
 (hardcodes the buffer address in RAM though). Will post a patch when GSoC
 officially started.

 I haven't done any work on using it from _Linux_, though.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/76#comment:4>
coreboot <http://www.coreboot.org/>

From jildosfetros at yahoo.com  Wed Apr  2 15:56:54 2008
From: jildosfetros at yahoo.com (Jildos Fetros)
Date: Wed, 2 Apr 2008 06:56:54 -0700 (PDT)
Subject: [coreboot] is my motherboard supported?
Message-ID: <588686.7362.qm@web45802.mail.sp1.yahoo.com>

Hello,
I want to port coreboot to my Desktop PC.

motherboard model: Elitegroup K7S5A
CPU: Amd Athlon 1,4 GHz
probably north and south bridge(taken from boot screen): SIS735

lspci output:
00:00.0 Host bridge: Silicon Integrated Systems [SiS] 735 Host (rev 01)
00:01.0 PCI bridge: Silicon Integrated Systems [SiS] Virtual PCI-to-PCI bridge (AGP)
00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS85C503/5513 (LPC Bridge)00:02.1 SMBus: Silicon Integrated Systems [SiS] SiS961/2 SMBus Controller
00:02.2 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 07)
00:02.3 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 07)
00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] (rev d0)
00:02.7 Multimedia audio controller: Silicon Integrated Systems [SiS] AC'97 Sound Controller (rev a0)
00:0f.0 Ethernet controller: Intel Corporation 82557/8/9 [Ethernet Pro 100] (rev 0c)
01:00.0 VGA compatible controller: nVidia Corporation NV11 [GeForce2 MX/MX 400] (rev b2)

Super I/O chip:  ITE IT8705F 0119-BXA M4B230

Bios: 686 Amibios AU32

Thanks 







      ____________________________________________________________________________________
You rock. That's why Blockbuster's offering you one month of Blockbuster Total Access, No Cost.  
http://tc.deals.yahoo.com/tc/blockbuster/text5.com
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From joe at smittys.pointclark.net  Wed Apr  2 19:48:37 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Wed, 02 Apr 2008 13:48:37 -0400
Subject: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
In-Reply-To: <47EFD2E1.9080200@gmx.net>
References: <e6c711510803290007j4c512a49jfcddc5df0bf197b9@mail.gmail.com>
	<20080329093801.52hprv9su8wswgs0@www.smittys.pointclark.net>
	<e6c711510803291503s628f0706q5bc51eea4b75de6@mail.gmail.com>
	<20080329182303.34dg56si8ccoggo0@www.smittys.pointclark.net>
	<20080329202055.cw5zfcv38k0ok8s8@www.smittys.pointclark.net>
	<e6c711510803292330n78c27d62ia1364e14371ed2f5@mail.gmail.com>
	<20080330101806.3uqz419d4o8owcsk@www.smittys.pointclark.net>
	<47EFD2E1.9080200@gmx.net>
Message-ID: <20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>

Quoting Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>:

> On 30.03.2008 16:18, joe at smittys.pointclark.net wrote:
>> Quoting Ed Swierk <eswierk at arastra.com>:
>>
>>> On Sat, Mar 29, 2008 at 5:20 PM,  <joe at smittys.pointclark.net> wrote:
>>>
>>>> After thinking about it.....
>>>> What are the advantages of disabling the TCO timer (besides
>>>> rebooting)? Doesn't the system need this to run properly? By setting
>>>> the no reboot the timer is still running....does it need to be?
>>>>
>>> The point of the TCO timer is to let a system recover automatically by
>>> sending an interrupt and then rebooting if the OS crashes. While
>>> operating systems can crash for all sorts of reasons, coreboot code
>>> doesn't generally crash unless there's a hardware failure or
>>> misconfiguration that will not correct itself by rebooting. Thus it
>>> makes sense to disable the timer in coreboot and let a TCO-aware
>>> payload re-enable it.
>>>
>>> The TCO timer has no other purpose that I'm aware of, so it doesn't
>>> matter whether coreboot neuters its effect by setting NO_REBOOT or
>>> halts it completely by setting TCO_TMR_HALT. Leaving the timer running
>>> still causes an interrupt to occur on timeout, but I think it's a
>>> no-op unless the OS is paying attention.
>>>
>>> This document explains the TCO timer in more detail:
>>> ftp://download.intel.com/design/chipsets/applnots/29227301.pdf.
>>>
>>>
>> Thanks for the explanation Ed. That makes perfect sense.
>>
>
> Please halt the timer completely if possible. We are not really prepared
> to handle interrupts in coreboot.
>
>
Hmm, this is going to be interesting on the ICH4, I still have to look  
at how the other ICH's are setup. The TCO Timer Halt is acually  
located in I/O space not PCI configuration space. It is ACPIBASE +  
TCOBASE(60h) + TCO1_CNT(08h) bit 11. We'll see.

Thanks - Joe



From dev at stuffit.at  Wed Apr  2 21:16:29 2008
From: dev at stuffit.at (Devils-Hawk)
Date: Wed, 2 Apr 2008 21:16:29 +0200
Subject: [coreboot] v3 qemu and gcc-4.3.0
In-Reply-To: <20080331210342.GD6215@greenwood>
References: <20080321154801.429F3187F588C@dd17914.kasserver.com>
	<200803220447.37104.dev@stuffit.at>
	<20080331210342.GD6215@greenwood>
Message-ID: <200804022116.30177.dev@stuffit.at>

> Thanks, committed in r3204 with some cosmetic changes. Works for me in
> QEMU and on hardware.
>

Sorry for the late response, have been busy with actual studying (scary) :) . 
The committed patch still retains the wrong directions for the last movl 
instruction. As Mr. Crouse pointed out 

>/* Restore the stack pointer from the storage area. */
>-       movl 16(%ebx), %esp
>+       /* Restore old stack. */
>+       movl %esp, %ebx
should really be
>          movl %ebx, %esp

I have a patch that adresses the rest of the raised issues but it mysteriously 
dies somewhere in vga init. Haven't yet had the time to take a closer look.
Attached, maybe somebody knows whats going wrong. ;) No sign-off because the 
patch is not working. ;)

best regards, devh

PS: hopefully ddd gets a new maintainer, this tool rocks! ;)
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From dev at stuffit.at  Wed Apr  2 21:44:20 2008
From: dev at stuffit.at (Devils-Hawk)
Date: Wed, 2 Apr 2008 21:44:20 +0200
Subject: [coreboot] v3 qemu and gcc-4.3.0
In-Reply-To: <200804022116.30177.dev@stuffit.at>
References: <20080321154801.429F3187F588C@dd17914.kasserver.com>
	<20080331210342.GD6215@greenwood>
	<200804022116.30177.dev@stuffit.at>
Message-ID: <200804022144.21113.dev@stuffit.at>

On Wednesday 02 April 2008 21:16:29 Devils-Hawk wrote:

> closer look. Attached, maybe somebody knows whats going wrong. ;) No
> sign-off because the patch is not working. ;)
>
Whoops! One > too many! New patch attached. Hmm ... and i found out whats 
going wrong with qemu. Sometimes a piece of art says more than words. The 
only question is it even supposed to work. I had to work with this really old 
assembly editor once and i think that it did not allow that kind of mov 
instructions, only register - register transfer to %esp.

regards devh

PS: patch still not working
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From uwe at hermann-uwe.de  Wed Apr  2 22:13:33 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 2 Apr 2008 22:13:33 +0200
Subject: [coreboot] v3 qemu and gcc-4.3.0
In-Reply-To: <200804022144.21113.dev@stuffit.at>
References: <20080321154801.429F3187F588C@dd17914.kasserver.com>
	<20080331210342.GD6215@greenwood>
	<200804022116.30177.dev@stuffit.at>
	<200804022144.21113.dev@stuffit.at>
Message-ID: <20080402201333.GA923@greenwood>

On Wed, Apr 02, 2008 at 09:44:20PM +0200, Devils-Hawk wrote:
> Whoops! One > too many! New patch attached. Hmm ... and i found out whats 
> going wrong with qemu. Sometimes a piece of art says more than words. The 
> only question is it even supposed to work. I had to work with this really old 
> assembly editor once and i think that it did not allow that kind of mov 
> instructions, only register - register transfer to %esp.
> 
> regards devh
> 
> PS: patch still not working

Please post _all_ patches with Signed-off-by, whether working or not,
someone else might fix a non-working patch and commit it.

I'll let Jordan review your changes, but one quick question: does the
_current_ svn work for you? It works fine here (QEMU 0.9.1), or well,
at least good enough that it doesn't triple-fault anymore.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From corey.osgood at gmail.com  Wed Apr  2 22:52:13 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 2 Apr 2008 16:52:13 -0400
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc value:
	mask ff"
Message-ID: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>

Working with romcc here, you can drop this block of code into the
auto.c/raminit portion of any board using romcc and reproduce the error (it
compiles fine with CAR, but that's not an option with the c7 cpu, at least
not yet):

u8 reg8, spd_data;

reg8 = pci_read_config8(PCI_DEV(0, 0, 3), 0x62);
spd_data = smbus_read_byte(0x50, 30);
spd_data = spd_data / 10;
if(spd_data < 5)
    spd_data = 5;
else if(spd_data > 20)
    spd_data = 20;

if(spd_data > (reg8 >> 4))
{
   reg8 &= 0xf;
   reg8 |= (spd_data << 4);
}

The error is confirmed on ubuntu 8.04 alpha/beta/? and debian unstable, both
with gcc 4.2.3, and also gentoo with gcc 4.1.2:

dst type: auto unsigned char
dst: %edx:%eax
auto.c:35.1: raminit.c:436.33: raminit.c:615.36: auto.c:218.32:
0x83cbe70 convert    Internal compiler error: failed to trunc value: mask ff
make[1]: *** [auto.inc] Aborted (core dumped)

Commenting out either spd_data/10 or the if/else portion gets rid of the
error, it only happens when all of these statements are in. I also have half
a dozen blocks like this which compile fine:

    reg8 = pci_read_config8(ctrl->d0f3, 0x63);
    j = spd_read_byte(ctrl->channel0[i], SPD_tRRD);//ctrl->channel0[0] =
0x50
    spd_data = ((j >> 2) * 100);
    spd_data |= ((j & 0x3) * 25);
    spd_data = spd_data / (ram_cycle * 100); //ram_cycle in this case = 10
    if(spd_data < 2)
        spd_data = 2;
    else if(spd_data > 5)
        spd_data = 5;

    if((spd_data - 2) > (reg8 >> 6)) {
        reg8 &= 0x3f;
        reg8 |= (spd_data - 2) << 6;
    }

It's just that one instance that fails to compile. I've tried moving it
around, changing the variables, changing the types, modifying the math, etc,
etc, and nothing seems to help. Any suggestions?
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From Marc.Jones at AMD.com  Wed Apr  2 23:07:30 2008
From: Marc.Jones at AMD.com (Marc Jones)
Date: Wed, 02 Apr 2008 15:07:30 -0600
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc
 value: mask ff"
In-Reply-To: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
Message-ID: <47F3F592.4070501@AMD.com>

Cory,
I don't know what the error means. Others might know more but I can make 
some recommendations for you to try.
ROMCC problems are usually a stack depth problem. ROMCC is using 
registers for stack space so every function call uses up registers. The 
code around this code will have a big effect if this code will work. 
First try to inline the code (ROMCC might already be doing this). Next, 
try moving the pci read to after the math so the value doesn't need to 
be stored before it is used.

Marc

Corey Osgood wrote:
> Working with romcc here, you can drop this block of code into the 
> auto.c/raminit portion of any board using romcc and reproduce the 
> error (it compiles fine with CAR, but that's not an option with the c7 
> cpu, at least not yet):
>
> u8 reg8, spd_data;
>
> reg8 = pci_read_config8(PCI_DEV(0, 0, 3), 0x62);
> spd_data = smbus_read_byte(0x50, 30);
> spd_data = spd_data / 10;
> if(spd_data < 5)
>     spd_data = 5;
> else if(spd_data > 20)
>     spd_data = 20;
>
> if(spd_data > (reg8 >> 4))
> {
>    reg8 &= 0xf;
>    reg8 |= (spd_data << 4);
> }
>
> The error is confirmed on ubuntu 8.04 alpha/beta/? and debian 
> unstable, both with gcc 4.2.3, and also gentoo with gcc 4.1.2:
>
> dst type: auto unsigned char
> dst: %edx:%eax
> auto.c:35.1: raminit.c:436.33: raminit.c:615.36: auto.c:218.32:
> 0x83cbe70 convert    Internal compiler error: failed to trunc value: 
> mask ff
> make[1]: *** [auto.inc] Aborted (core dumped)
>
> Commenting out either spd_data/10 or the if/else portion gets rid of 
> the error, it only happens when all of these statements are in. I also 
> have half a dozen blocks like this which compile fine:
>
>     reg8 = pci_read_config8(ctrl->d0f3, 0x63);
>     j = spd_read_byte(ctrl->channel0[i], SPD_tRRD);//ctrl->channel0[0] 
> = 0x50
>     spd_data = ((j >> 2) * 100);
>     spd_data |= ((j & 0x3) * 25);
>     spd_data = spd_data / (ram_cycle * 100); //ram_cycle in this case = 10
>     if(spd_data < 2)
>         spd_data = 2;
>     else if(spd_data > 5)
>         spd_data = 5;
>
>     if((spd_data - 2) > (reg8 >> 6)) {
>         reg8 &= 0x3f;
>         reg8 |= (spd_data - 2) << 6;
>     }
>
> It's just that one instance that fails to compile. I've tried moving 
> it around, changing the variables, changing the types, modifying the 
> math, etc, etc, and nothing seems to help. Any suggestions?

-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From stepan at coresystems.de  Wed Apr  2 23:12:37 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 02 Apr 2008 15:12:37 -0600
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc
 value: mask ff"
In-Reply-To: <47F3F592.4070501@AMD.com>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
	<47F3F592.4070501@AMD.com>
Message-ID: <47F3F6C5.60003@coresystems.de>

In addition, you could try using "unsigned" instead of "u8"... I think 
romcc is kind of bad at handling different data types and it handles all 
sizes equally (ie. using u8 does not gain you the rest of the register 
you are using)

Marc Jones wrote:
> Cory,
> I don't know what the error means. Others might know more but I can make 
> some recommendations for you to try.
> ROMCC problems are usually a stack depth problem. ROMCC is using 
> registers for stack space so every function call uses up registers. The 
> code around this code will have a big effect if this code will work. 
> First try to inline the code (ROMCC might already be doing this). Next, 
> try moving the pci read to after the math so the value doesn't need to 
> be stored before it is used.
>
> Marc
>
> Corey Osgood wrote:
>   
>> Working with romcc here, you can drop this block of code into the 
>> auto.c/raminit portion of any board using romcc and reproduce the 
>> error (it compiles fine with CAR, but that's not an option with the c7 
>> cpu, at least not yet):
>>
>> u8 reg8, spd_data;
>>
>> reg8 = pci_read_config8(PCI_DEV(0, 0, 3), 0x62);
>> spd_data = smbus_read_byte(0x50, 30);
>> spd_data = spd_data / 10;
>> if(spd_data < 5)
>>     spd_data = 5;
>> else if(spd_data > 20)
>>     spd_data = 20;
>>
>> if(spd_data > (reg8 >> 4))
>> {
>>    reg8 &= 0xf;
>>    reg8 |= (spd_data << 4);
>> }
>>
>> The error is confirmed on ubuntu 8.04 alpha/beta/? and debian 
>> unstable, both with gcc 4.2.3, and also gentoo with gcc 4.1.2:
>>
>> dst type: auto unsigned char
>> dst: %edx:%eax
>> auto.c:35.1: raminit.c:436.33: raminit.c:615.36: auto.c:218.32:
>> 0x83cbe70 convert    Internal compiler error: failed to trunc value: 
>> mask ff
>> make[1]: *** [auto.inc] Aborted (core dumped)
>>
>> Commenting out either spd_data/10 or the if/else portion gets rid of 
>> the error, it only happens when all of these statements are in. I also 
>> have half a dozen blocks like this which compile fine:
>>
>>     reg8 = pci_read_config8(ctrl->d0f3, 0x63);
>>     j = spd_read_byte(ctrl->channel0[i], SPD_tRRD);//ctrl->channel0[0] 
>> = 0x50
>>     spd_data = ((j >> 2) * 100);
>>     spd_data |= ((j & 0x3) * 25);
>>     spd_data = spd_data / (ram_cycle * 100); //ram_cycle in this case = 10
>>     if(spd_data < 2)
>>         spd_data = 2;
>>     else if(spd_data > 5)
>>         spd_data = 5;
>>
>>     if((spd_data - 2) > (reg8 >> 6)) {
>>         reg8 &= 0x3f;
>>         reg8 |= (spd_data - 2) << 6;
>>     }
>>
>> It's just that one instance that fails to compile. I've tried moving 
>> it around, changing the variables, changing the types, modifying the 
>> math, etc, etc, and nothing seems to help. Any suggestions?
>>     
>
>   


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From corey.osgood at gmail.com  Wed Apr  2 23:55:01 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 2 Apr 2008 17:55:01 -0400
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc
	value: mask ff"
In-Reply-To: <47F3F592.4070501@AMD.com>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
	<47F3F592.4070501@AMD.com>
Message-ID: <dd3c80060804021455p343a0932xc1e3be5ed099e06c@mail.gmail.com>

On Wed, Apr 2, 2008 at 5:07 PM, Marc Jones <Marc.Jones at amd.com> wrote:

> Cory,
> I don't know what the error means. Others might know more but I can make
> some recommendations for you to try.
> ROMCC problems are usually a stack depth problem. ROMCC is using registers
> for stack space so every function call uses up registers. The code around
> this code will have a big effect if this code will work. First try to inline
> the code (ROMCC might already be doing this). Next, try moving the pci read
> to after the math so the value doesn't need to be stored before it is used.
>
> Marc
>

Thanks, tried all 3, still exactly the same error.

-Corey


> Corey Osgood wrote:
>
> > Working with romcc here, you can drop this block of code into the
> > auto.c/raminit portion of any board using romcc and reproduce the error (it
> > compiles fine with CAR, but that's not an option with the c7 cpu, at least
> > not yet):
> >
> > u8 reg8, spd_data;
> >
> > reg8 = pci_read_config8(PCI_DEV(0, 0, 3), 0x62);
> > spd_data = smbus_read_byte(0x50, 30);
> > spd_data = spd_data / 10;
> > if(spd_data < 5)
> >    spd_data = 5;
> > else if(spd_data > 20)
> >    spd_data = 20;
> >
> > if(spd_data > (reg8 >> 4))
> > {
> >   reg8 &= 0xf;
> >   reg8 |= (spd_data << 4);
> > }
> >
> > The error is confirmed on ubuntu 8.04 alpha/beta/? and debian unstable,
> > both with gcc 4.2.3, and also gentoo with gcc 4.1.2:
> >
> > dst type: auto unsigned char
> > dst: %edx:%eax
> > auto.c:35.1: raminit.c:436.33: raminit.c:615.36: auto.c:218.32:
> > 0x83cbe70 convert    Internal compiler error: failed to trunc value:
> > mask ff
> > make[1]: *** [auto.inc] Aborted (core dumped)
> >
> > Commenting out either spd_data/10 or the if/else portion gets rid of the
> > error, it only happens when all of these statements are in. I also have half
> > a dozen blocks like this which compile fine:
> >
> >    reg8 = pci_read_config8(ctrl->d0f3, 0x63);
> >    j = spd_read_byte(ctrl->channel0[i], SPD_tRRD);//ctrl->channel0[0] =
> > 0x50
> >    spd_data = ((j >> 2) * 100);
> >    spd_data |= ((j & 0x3) * 25);
> >    spd_data = spd_data / (ram_cycle * 100); //ram_cycle in this case =
> > 10
> >    if(spd_data < 2)
> >        spd_data = 2;
> >    else if(spd_data > 5)
> >        spd_data = 5;
> >
> >    if((spd_data - 2) > (reg8 >> 6)) {
> >        reg8 &= 0x3f;
> >        reg8 |= (spd_data - 2) << 6;
> >    }
> >
> > It's just that one instance that fails to compile. I've tried moving it
> > around, changing the variables, changing the types, modifying the math, etc,
> > etc, and nothing seems to help. Any suggestions?
> >
>
> --
> Marc Jones
> Senior Firmware Engineer
> (970) 226-9684 Office
> mailto:Marc.Jones at amd.com
> http://www.amd.com/embeddedprocessors
>
>
>
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From bari at onelabs.com  Wed Apr  2 23:58:11 2008
From: bari at onelabs.com (bari)
Date: Wed, 02 Apr 2008 16:58:11 -0500
Subject: [coreboot] Verify Flashrom for SST-49LF080A
Message-ID: <47F40173.2000902@onelabs.com>

Does anyone know what board was used to verify Flashrom for the 
SST-49LF080A?

-Bari



From corey.osgood at gmail.com  Wed Apr  2 23:59:16 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 2 Apr 2008 17:59:16 -0400
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc
	value: mask ff"
In-Reply-To: <47F3F6C5.60003@coresystems.de>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
	<47F3F592.4070501@AMD.com> <47F3F6C5.60003@coresystems.de>
Message-ID: <dd3c80060804021459l43588d5fg9c831b74d223b49f@mail.gmail.com>

On Wed, Apr 2, 2008 at 5:12 PM, Stefan Reinauer <stepan at coresystems.de>
wrote:

> In addition, you could try using "unsigned" instead of "u8"... I think
> romcc is kind of bad at handling different data types and it handles all
> sizes equally (ie. using u8 does not gain you the rest of the register you
> are using)


Thanks, unsigned int/long, u16/u32, and int/long all still produce the same
error (including the auto unsigned char part).

-Corey


>
> Marc Jones wrote:
>
> > Cory,
> > I don't know what the error means. Others might know more but I can make
> > some recommendations for you to try.
> > ROMCC problems are usually a stack depth problem. ROMCC is using
> > registers for stack space so every function call uses up registers. The code
> > around this code will have a big effect if this code will work. First try to
> > inline the code (ROMCC might already be doing this). Next, try moving the
> > pci read to after the math so the value doesn't need to be stored before it
> > is used.
> >
> > Marc
> >
> > Corey Osgood wrote:
> >
> >
> > > Working with romcc here, you can drop this block of code into the
> > > auto.c/raminit portion of any board using romcc and reproduce the error (it
> > > compiles fine with CAR, but that's not an option with the c7 cpu, at least
> > > not yet):
> > >
> > > u8 reg8, spd_data;
> > >
> > > reg8 = pci_read_config8(PCI_DEV(0, 0, 3), 0x62);
> > > spd_data = smbus_read_byte(0x50, 30);
> > > spd_data = spd_data / 10;
> > > if(spd_data < 5)
> > >    spd_data = 5;
> > > else if(spd_data > 20)
> > >    spd_data = 20;
> > >
> > > if(spd_data > (reg8 >> 4))
> > > {
> > >   reg8 &= 0xf;
> > >   reg8 |= (spd_data << 4);
> > > }
> > >
> > > The error is confirmed on ubuntu 8.04 alpha/beta/? and debian
> > > unstable, both with gcc 4.2.3, and also gentoo with gcc 4.1.2:
> > >
> > > dst type: auto unsigned char
> > > dst: %edx:%eax
> > > auto.c:35.1: raminit.c:436.33: raminit.c:615.36: auto.c:218.32:
> > > 0x83cbe70 convert    Internal compiler error: failed to trunc value:
> > > mask ff
> > > make[1]: *** [auto.inc] Aborted (core dumped)
> > >
> > > Commenting out either spd_data/10 or the if/else portion gets rid of
> > > the error, it only happens when all of these statements are in. I also have
> > > half a dozen blocks like this which compile fine:
> > >
> > >    reg8 = pci_read_config8(ctrl->d0f3, 0x63);
> > >    j = spd_read_byte(ctrl->channel0[i], SPD_tRRD);//ctrl->channel0[0]
> > > = 0x50
> > >    spd_data = ((j >> 2) * 100);
> > >    spd_data |= ((j & 0x3) * 25);
> > >    spd_data = spd_data / (ram_cycle * 100); //ram_cycle in this case =
> > > 10
> > >    if(spd_data < 2)
> > >        spd_data = 2;
> > >    else if(spd_data > 5)
> > >        spd_data = 5;
> > >
> > >    if((spd_data - 2) > (reg8 >> 6)) {
> > >        reg8 &= 0x3f;
> > >        reg8 |= (spd_data - 2) << 6;
> > >    }
> > >
> > > It's just that one instance that fails to compile. I've tried moving
> > > it around, changing the variables, changing the types, modifying the math,
> > > etc, etc, and nothing seems to help. Any suggestions?
> > >
> > >
> >
> >
> >
>
>
> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>     Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
>
>
>
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From r.marek at assembler.cz  Thu Apr  3 00:03:06 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 03 Apr 2008 00:03:06 +0200
Subject: [coreboot] Verify Flashrom for SST-49LF080A
In-Reply-To: <47F40173.2000902@onelabs.com>
References: <47F40173.2000902@onelabs.com>
Message-ID: <47F4029A.2040208@assembler.cz>

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Hash: SHA1

bari wrote:
> Does anyone know what board was used to verify Flashrom for the 
> SST-49LF080A?

Asus A8V-E SE, VT8237R

You need my recent patch (check SVN).

Rudolf
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=1zmA
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From uwe at hermann-uwe.de  Thu Apr  3 00:10:59 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 3 Apr 2008 00:10:59 +0200
Subject: [coreboot] Compile error in coreboot-v2: "failed to
	trunc	value: mask ff"
In-Reply-To: <dd3c80060804021459l43588d5fg9c831b74d223b49f@mail.gmail.com>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
	<47F3F592.4070501@AMD.com> <47F3F6C5.60003@coresystems.de>
	<dd3c80060804021459l43588d5fg9c831b74d223b49f@mail.gmail.com>
Message-ID: <20080402221059.GA11894@greenwood>

On Wed, Apr 02, 2008 at 05:59:16PM -0400, Corey Osgood wrote:
> On Wed, Apr 2, 2008 at 5:12 PM, Stefan Reinauer <stepan at coresystems.de>
> wrote:
> 
> > In addition, you could try using "unsigned" instead of "u8"... I think
> > romcc is kind of bad at handling different data types and it handles all
> > sizes equally (ie. using u8 does not gain you the rest of the register you
> > are using)
> 
> 
> Thanks, unsigned int/long, u16/u32, and int/long all still produce the same
> error (including the auto unsigned char part).

Try -mcpu=p2 (or other values) in romcc, e.g.

  action  "./romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"

That helped last time I had the same problem. Depends on which
CPU/chipset you use, of course.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Thu Apr  3 00:32:22 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 2 Apr 2008 15:32:22 -0700
Subject: [coreboot] patch: geodelx north debug support; PLL setting on dbe62
Message-ID: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>

ah, here in denver, in a coffee shop, debugging coreboot.

I'm in heaven :-)

ron
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From bari at onelabs.com  Thu Apr  3 00:59:35 2008
From: bari at onelabs.com (bari)
Date: Wed, 02 Apr 2008 17:59:35 -0500
Subject: [coreboot] Verify Flashrom for SST-49LF080A
In-Reply-To: <47F4029A.2040208@assembler.cz>
References: <47F40173.2000902@onelabs.com> <47F4029A.2040208@assembler.cz>
Message-ID: <47F40FD7.2050404@onelabs.com>

Rudolf Marek wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> bari wrote:
>   
>> Does anyone know what board was used to verify Flashrom for the 
>> SST-49LF080A?
>>     
>
> Asus A8V-E SE, VT8237R
>
> You need my recent patch (check SVN).
>
> Rudolf
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.6 (GNU/Linux)
> Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
>
> iD8DBQFH9AKa3J9wPJqZRNURAvSyAJ9FXVQziPXEQ3BZT01e/B5w/U8tGQCghJnT
> RuuhX1LjFN8i4kPAX+IXQWU=
> =1zmA
> -----END PGP SIGNATURE-----
>
>   
I've been using the patch. Flashrom only detects SST-49LF080A on some 
boards with vt8237r and not others.

-Bari



From r.marek at assembler.cz  Thu Apr  3 01:05:22 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 03 Apr 2008 01:05:22 +0200
Subject: [coreboot] Verify Flashrom for SST-49LF080A
In-Reply-To: <47F40FD7.2050404@onelabs.com>
References: <47F40173.2000902@onelabs.com> <47F4029A.2040208@assembler.cz>
	<47F40FD7.2050404@onelabs.com>
Message-ID: <47F41132.4020601@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi,

> I've been using the patch. Flashrom only detects SST-49LF080A on some 
> boards with vt8237r and not others.

all with coreboot? If not check register 52

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iD8DBQFH9BEy3J9wPJqZRNURAgAoAKCarLWgLnP7/ytCV0jPrWfh+EIQjwCgz2Vq
jklZUPyW/DDmiZdbh4kE+FU=
=Xsb4
-----END PGP SIGNATURE-----



From bari at onelabs.com  Thu Apr  3 01:16:08 2008
From: bari at onelabs.com (bari)
Date: Wed, 02 Apr 2008 18:16:08 -0500
Subject: [coreboot] Verify Flashrom for SST-49LF080A
In-Reply-To: <47F41132.4020601@assembler.cz>
References: <47F40173.2000902@onelabs.com> <47F4029A.2040208@assembler.cz>
	<47F40FD7.2050404@onelabs.com> <47F41132.4020601@assembler.cz>
Message-ID: <47F413B8.1030204@onelabs.com>

Rudolf Marek wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Hi,
>
>   
>> I've been using the patch. Flashrom only detects SST-49LF080A on some 
>> boards with vt8237r and not others.
>>     
>
> all with coreboot? If not check register 52
>
> Rudolf
>   
With coreboot or with factory BIOS.

-Bari



From svn at coreboot.org  Thu Apr  3 01:39:12 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 02 Apr 2008 23:39:12 -0000
Subject: [coreboot]  #95: Run coreboot in VirtualBox
Message-ID: <039.8e5fad36b203068bd3071c0f2771ba88@coreboot.org>

#95: Run coreboot in VirtualBox
---------------------------------+------------------------------------------
   Reporter:  uwe                |          Owner:  somebody
       Type:  defect             |         Status:  new     
   Priority:  minor              |      Milestone:          
  Component:  misc               |        Version:          
   Keywords:                     |   Dependencies:          
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 It would be nice if we could test coreboot images in VirtualBox, see
 http://virtualbox.org/.

 VirtualBox does not (yet) provide a simple mechanism to use a different
 BIOS in their emulated machines (something like "-L" in qemu). Instead the
 BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code
 (an array of bytes, or the like) and merged into the VirtualBox
 executable.

 The relevant files are
 {{{
  src/VBox/Devices/PC/DevPcBios.cpp
  bldprogs/bin2c.c
 }}}
 if someone want to hack VirtualBox to easily support using coreboot images
 instead of their usual BIOS.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95>
coreboot <http://www.coreboot.org/>

From corey.osgood at gmail.com  Thu Apr  3 05:12:29 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 2 Apr 2008 23:12:29 -0400
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc
	value: mask ff"
In-Reply-To: <20080402221059.GA11894@greenwood>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
	<47F3F592.4070501@AMD.com> <47F3F6C5.60003@coresystems.de>
	<dd3c80060804021459l43588d5fg9c831b74d223b49f@mail.gmail.com>
	<20080402221059.GA11894@greenwood>
Message-ID: <dd3c80060804022012r2e468260g270e6271ba58b010@mail.gmail.com>

On Wed, Apr 2, 2008 at 6:10 PM, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> On Wed, Apr 02, 2008 at 05:59:16PM -0400, Corey Osgood wrote:
> > On Wed, Apr 2, 2008 at 5:12 PM, Stefan Reinauer <stepan at coresystems.de>
> > wrote:
> >
> > > In addition, you could try using "unsigned" instead of "u8"... I think
> > > romcc is kind of bad at handling different data types and it handles
> all
> > > sizes equally (ie. using u8 does not gain you the rest of the register
> you
> > > are using)
> >
> >
> > Thanks, unsigned int/long, u16/u32, and int/long all still produce the
> same
> > error (including the auto unsigned char part).
>
> Try -mcpu=p2 (or other values) in romcc, e.g.
>
>  action  "./romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS)
> $(MAINBOARD)/auto.c -o $@"
>
> That helped last time I had the same problem. Depends on which
> CPU/chipset you use, of course.
>
>
> Uwe.


c3, c3-2, p2, p3, and p4 all give the same error. Same applies when -mmmx
and/or -msse are added. -fdebug-all gives the same error too, no more info

Thanks,
Corey
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From segher at kernel.crashing.org  Thu Apr  3 05:35:54 2008
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Thu, 3 Apr 2008 05:35:54 +0200
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc
	value: mask ff"
In-Reply-To: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
Message-ID: <880daa67fabd830e1d1e7c64bc8d7a68@kernel.crashing.org>

> The error is confirmed on ubuntu 8.04 alpha/beta/? and debian 
> unstable, both with gcc 4.2.3, and also gentoo with gcc 4.1.2:
>
> dst type: auto unsigned char
> dst: %edx:%eax
> auto.c:35.1: raminit.c:436.33: raminit.c:615.36: auto.c:218.32:
> 0x83cbe70 convert??? Internal compiler error: failed to trunc value: 
> mask ff
> make[1]: *** [auto.inc] Aborted (core dumped)

Please try with FSF GCC 4.3.0, and report any failures at
http://gcc.gnu.org/bugzilla .  If 4.3.0 works, try 4.2.3 and
maybe 4.1.2.  Thanks!


Segher




From corey.osgood at gmail.com  Thu Apr  3 05:50:55 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 2 Apr 2008 23:50:55 -0400
Subject: [coreboot] Compile error in coreboot-v2: "failed to trunc
	value: mask ff"
In-Reply-To: <dd3c80060804022012r2e468260g270e6271ba58b010@mail.gmail.com>
References: <dd3c80060804021352u61135d6dyb99a82b76b3a609c@mail.gmail.com>
	<47F3F592.4070501@AMD.com> <47F3F6C5.60003@coresystems.de>
	<dd3c80060804021459l43588d5fg9c831b74d223b49f@mail.gmail.com>
	<20080402221059.GA11894@greenwood>
	<dd3c80060804022012r2e468260g270e6271ba58b010@mail.gmail.com>
Message-ID: <dd3c80060804022050p5a2bb1c2ga1ee1c4bef094799@mail.gmail.com>

On undefined, Corey Osgood <corey.osgood at gmail.com> wrote:

> On Wed, Apr 2, 2008 at 6:10 PM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
>
> > On Wed, Apr 02, 2008 at 05:59:16PM -0400, Corey Osgood wrote:
> > > On Wed, Apr 2, 2008 at 5:12 PM, Stefan Reinauer <stepan at coresystems.de
> > >
> > > wrote:
> > >
> > > > In addition, you could try using "unsigned" instead of "u8"... I
> > think
> > > > romcc is kind of bad at handling different data types and it handles
> > all
> > > > sizes equally (ie. using u8 does not gain you the rest of the
> > register you
> > > > are using)
> > >
> > >
> > > Thanks, unsigned int/long, u16/u32, and int/long all still produce the
> > same
> > > error (including the auto unsigned char part).
> >
> > Try -mcpu=p2 (or other values) in romcc, e.g.
> >
> >  action  "./romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS)
> > $(MAINBOARD)/auto.c -o $@"
> >
> > That helped last time I had the same problem. Depends on which
> > CPU/chipset you use, of course.
> >
> >
> > Uwe.
>
>
> c3, c3-2, p2, p3, and p4 all give the same error. Same applies when -mmmx
> and/or -msse are added. -fdebug-all gives the same error too, no more info
>
> Thanks,
> Corey
>

Huh, well, the problem's gone now. I have no idea why it worked, but I
changed the smbus functions along with the spd_read_byte wrapper from
returning a u8 to an int. Makes no sense, but it works.

-Corey
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From svn at coreboot.org  Thu Apr  3 06:07:43 2008
From: svn at coreboot.org (coreboot)
Date: Thu, 03 Apr 2008 04:07:43 -0000
Subject: [coreboot] #95: Run coreboot in VirtualBox
In-Reply-To: <039.8e5fad36b203068bd3071c0f2771ba88@coreboot.org>
References: <039.8e5fad36b203068bd3071c0f2771ba88@coreboot.org>
Message-ID: <048.af48773b3d1d593dc0975c8c0b973f65@coreboot.org>

#95: Run coreboot in VirtualBox
----------------------------+-----------------------------------------------
    Reporter:  uwe          |         Owner:  somebody         
        Type:  enhancement  |        Status:  new              
    Priority:  minor        |     Milestone:                   
   Component:  misc         |       Version:                   
  Resolution:               |      Keywords:                   
Dependencies:               |   Patchstatus:  there is no patch
----------------------------+-----------------------------------------------
Changes (by stepan):

  * type:  defect => enhancement

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95#comment:1>
coreboot <http://www.coreboot.org/>

From Marc.Jones at amd.com  Thu Apr  3 06:12:46 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Wed, 02 Apr 2008 22:12:46 -0600
Subject: [coreboot] patch: geodelx north debug support;
 PLL setting on dbe62
In-Reply-To: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
References: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
Message-ID: <47F4593E.8030809@AMD.com>



ron minnich wrote:
> ah, here in denver, in a coffee shop, debugging coreboot.
>
> I'm in heaven :-)
>
> ron
>   
> Set manual settings for dbe62; the auto settings are giving slightly wrong values
>
> Add call to dumplxmsr in dbe62 initram main()
>
> Add dumplxmsrs function to geodelx raminit support code
>
> Correct spelling of CAS
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   

Looks good.
Acked-by: Marc Jones (marc.jones at amd.com)

-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From malateshkamat at gmail.com  Thu Apr  3 07:59:14 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Thu, 3 Apr 2008 11:29:14 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
Message-ID: <fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>

Hi all..

     I have worked with PM49fl00x.diff patch ,its worked fine and i got the
output as below

[root at localhost ~]# flashrom

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

Pm49FL004 found at physical address 0xfff80000.

Flash part is Pm49FL004 (512 KB).

No operations were specified.


[root at localhost ~]# flashrom -r backup.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

Pm49FL004 found at physical address 0xfff80000.

Flash part is Pm49FL004 (512 KB).

Reading Flash...done


[root at localhost ~]# flashrom -E

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

Pm49FL004 found at physical address 0xfff80000.

Flash part is Pm49FL004 (512 KB).

Erasing flash chip

Erasing page: 0007 at address: 0x00070000


[root at localhost ~]# flashrom -w backup.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

Pm49FL004 found at physical address 0xfff80000.

Flash part is Pm49FL004 (512 KB).

Flash image seems to be a legacy BIOS. Disabling checks.

Programming page: 0007 at address: 0x00070000


[root at localhost ~]# flashrom -v backup.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

Pm49FL004 found at physical address 0xfff80000.

Flash part is Pm49FL004 (512 KB).

Flash image seems to be a legacy BIOS. Disabling checks.

Verifying flash... VERIFIED.

**************************************************************************************************************************************


  Now i am working on SST49LF004B
                                   33-4C-NHE
                                   0710022-CA   with the  motherboard
K8Upgrade-VM800

  The flashrom detect flash device on this board, But the erasing and
writting operation is not happening properly
   hier flashrom output :

[root at localhost ~]# flashrom

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

No operations were specified.


[root at localhost ~]# flashrom -E

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

Erasing flash chip


[root at localhost ~]# flashrom -w backup.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

Flash image seems to be a legacy BIOS. Disabling checks.

Programming page: 0007 at address: 0x00070000


[root at localhost ~]# flashrom -v backup.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

Flash image seems to be a legacy BIOS. Disabling checks.

Verifying flash... FAILED!

Now we are analysing the code but we are not getting idea...

 please guide us  how to change the code ..we are ready to fix the things.

Thanks in advance........

with regards,

Malatesh kamatad..
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From rminnich at gmail.com  Thu Apr  3 08:04:14 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 2 Apr 2008 23:04:14 -0700
Subject: [coreboot] patch: dbe62 boots to FILO!
Message-ID: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>

now how do we get a disk to boot? All we have is USB :-)

ron
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From corey.osgood at gmail.com  Thu Apr  3 08:41:40 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 3 Apr 2008 02:41:40 -0400
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
Message-ID: <dd3c80060804022341k3fdfecfdk304ef8faa8cc6126@mail.gmail.com>

On undefined, ron minnich <rminnich at gmail.com> wrote:

> now how do we get a disk to boot? All we have is USB :-)
>
> ron
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

That's OHCI isn't it? Try my patch of Fridel's code!

-Corey
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From paulepanter at users.sourceforge.net  Thu Apr  3 08:54:17 2008
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 03 Apr 2008 08:54:17 +0200
Subject: [coreboot] patch: geodelx north debug support;
	PLL setting on	dbe62
In-Reply-To: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
References: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
Message-ID: <1207205657.6591.5.camel@mattotaupa.home.familie-menzel.de>

Dear Ron,


there is a typo.

Am Mittwoch, den 02.04.2008, 15:32 -0700 schrieb ron minnich:
> +/** 
> + * Dump key MSR values for ram init. You can call this function and then use it to 
> + * compare to a fuctory bios setting.

s/fuctory/factory/

> + * @param level printk level
> + */


Thanks,

Paul




From corey.osgood at gmail.com  Thu Apr  3 09:27:15 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 3 Apr 2008 03:27:15 -0400
Subject: [coreboot] patch: geodelx north debug support;
	PLL setting on dbe62
In-Reply-To: <1207205657.6591.5.camel@mattotaupa.home.familie-menzel.de>
References: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
	<1207205657.6591.5.camel@mattotaupa.home.familie-menzel.de>
Message-ID: <dd3c80060804030027n5d0b94e4i410eb21a98654d26@mail.gmail.com>

On Thu, Apr 3, 2008 at 2:54 AM, Paul Menzel <
paulepanter at users.sourceforge.net> wrote:

> Dear Ron,
>
>
> there is a typo.
>
> Am Mittwoch, den 02.04.2008, 15:32 -0700 schrieb ron minnich:
> > +/**
> > + * Dump key MSR values for ram init. You can call this function and
> then use it to
> > + * compare to a fuctory bios setting.
>
> s/fuctory/factory/


Not a typo ;)

-Corey


>
>
> > + * @param level printk level
> > + */
>
>
> Thanks,
>
> Paul
>
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From paulepanter at users.sourceforge.net  Thu Apr  3 09:39:49 2008
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 03 Apr 2008 09:39:49 +0200
Subject: [coreboot] patch: geodelx north debug support;
	PLL setting on	dbe62
In-Reply-To: <dd3c80060804030027n5d0b94e4i410eb21a98654d26@mail.gmail.com>
References: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
	<1207205657.6591.5.camel@mattotaupa.home.familie-menzel.de>
	<dd3c80060804030027n5d0b94e4i410eb21a98654d26@mail.gmail.com>
Message-ID: <1207208389.6591.15.camel@mattotaupa.home.familie-menzel.de>

Am Donnerstag, den 03.04.2008, 03:27 -0400 schrieb Corey Osgood:
> On Thu, Apr 3, 2008 at 2:54 AM, Paul Menzel
> <paulepanter at users.sourceforge.net> wrote:

>         s/fuctory/factory/
> 
> Not a typo ;)

??? I am lost.


Paul





From corey.osgood at gmail.com  Thu Apr  3 10:03:47 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 3 Apr 2008 04:03:47 -0400
Subject: [coreboot] patch: geodelx north debug support;
	PLL setting on dbe62
In-Reply-To: <1207208389.6591.15.camel@mattotaupa.home.familie-menzel.de>
References: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
	<1207205657.6591.5.camel@mattotaupa.home.familie-menzel.de>
	<dd3c80060804030027n5d0b94e4i410eb21a98654d26@mail.gmail.com>
	<1207208389.6591.15.camel@mattotaupa.home.familie-menzel.de>
Message-ID: <dd3c80060804030103x15a226a0qd51e5edf67ca0144@mail.gmail.com>

On Thu, Apr 3, 2008 at 3:39 AM, Paul Menzel <
paulepanter at users.sourceforge.net> wrote:

> Am Donnerstag, den 03.04.2008, 03:27 -0400 schrieb Corey Osgood:
> > On Thu, Apr 3, 2008 at 2:54 AM, Paul Menzel
> > <paulepanter at users.sourceforge.net> wrote:
>
> >         s/fuctory/factory/
> >
> > Not a typo ;)
>
> ??? I am lost.
>
>
> Paul
>

http://coreboot.org/pipermail/coreboot/2006-November/017012.html
http://coreboot.org/pipermail/coreboot/2006-June/014905.html
http://linuxbios.org/pipermail/linuxbios/2004-August/008734.html
http://www.mail-archive.com/linuxbios at clustermatic.org/msg06979.html

It's exactly what he meant to say

-Corey
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From paulepanter at users.sourceforge.net  Thu Apr  3 10:12:36 2008
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 03 Apr 2008 10:12:36 +0200
Subject: [coreboot] patch: geodelx north debug support;
	PLL setting on	dbe62
In-Reply-To: <dd3c80060804030103x15a226a0qd51e5edf67ca0144@mail.gmail.com>
References: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>
	<1207205657.6591.5.camel@mattotaupa.home.familie-menzel.de>
	<dd3c80060804030027n5d0b94e4i410eb21a98654d26@mail.gmail.com>
	<1207208389.6591.15.camel@mattotaupa.home.familie-menzel.de>
	<dd3c80060804030103x15a226a0qd51e5edf67ca0144@mail.gmail.com>
Message-ID: <1207210356.6591.18.camel@mattotaupa.home.familie-menzel.de>

Am Donnerstag, den 03.04.2008, 04:03 -0400 schrieb Corey Osgood:
> On Thu, Apr 3, 2008 at 3:39 AM, Paul Menzel
> <paulepanter at users.sourceforge.net> wrote:
>         Am Donnerstag, den 03.04.2008, 03:27 -0400 schrieb Corey
>         Osgood:
>         > On Thu, Apr 3, 2008 at 2:54 AM, Paul Menzel
>         > <paulepanter at users.sourceforge.net> wrote:
>         
>         
>         >         s/fuctory/factory/
>         >
>         > Not a typo ;)
>         
>         
>         ??? I am lost.
>         
>         
>         
>         Paul
> 
> http://coreboot.org/pipermail/coreboot/2006-November/017012.html
> http://coreboot.org/pipermail/coreboot/2006-June/014905.html
> http://linuxbios.org/pipermail/linuxbios/2004-August/008734.html
> http://www.mail-archive.com/linuxbios at clustermatic.org/msg06979.html
> 
> It's exactly what he meant to say

Ok, I did not say anything. Would be interesting though where this word
comes from. But maybe I am a little slow today.


Paul





From c-d.hailfinger.devel.2006 at gmx.net  Thu Apr  3 11:24:18 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 03 Apr 2008 11:24:18 +0200
Subject: [coreboot] patch: geodelx north debug support;
 PLL setting on dbe62
In-Reply-To: <1207210356.6591.18.camel@mattotaupa.home.familie-menzel.de>
References: <13426df10804021532g20f50badsf6c67efaa939c57f@mail.gmail.com>	<1207205657.6591.5.camel@mattotaupa.home.familie-menzel.de>	<dd3c80060804030027n5d0b94e4i410eb21a98654d26@mail.gmail.com>	<1207208389.6591.15.camel@mattotaupa.home.familie-menzel.de>	<dd3c80060804030103x15a226a0qd51e5edf67ca0144@mail.gmail.com>
	<1207210356.6591.18.camel@mattotaupa.home.familie-menzel.de>
Message-ID: <47F4A242.5060806@gmx.net>

On 03.04.2008 10:12, Paul Menzel wrote:
> Am Donnerstag, den 03.04.2008, 04:03 -0400 schrieb Corey Osgood:
>   
>> On Thu, Apr 3, 2008 at 3:39 AM, Paul Menzel wrote:
>>> Am Donnerstag, den 03.04.2008, 03:27 -0400 schrieb Corey
>>> Osgood:
>>>
>>>> s/fuctory/factory/
>>>>
>>>> Not a typo ;)
>>>         
>>>         
>>> ??? I am lost.
>>>
>>
>> http://coreboot.org/pipermail/coreboot/2006-November/017012.html
>> http://coreboot.org/pipermail/coreboot/2006-June/014905.html
>> http://linuxbios.org/pipermail/linuxbios/2004-August/008734.html
>> http://www.mail-archive.com/linuxbios at clustermatic.org/msg06979.html
>>
>> It's exactly what he meant to say
>>     
>
> Ok, I did not say anything. Would be interesting though where this word
> comes from. But maybe I am a little slow today.
>   

The factory BIOS is often so broken that we call it FUC(K)tory instead
of factory.


Regards,
Carl-Daniel



From Qingpei.Wang at amd.com  Thu Apr  3 11:41:51 2008
From: Qingpei.Wang at amd.com (Wang, Qingpei)
Date: Thu, 3 Apr 2008 17:41:51 +0800
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <dd3c80060804022341k3fdfecfdk304ef8faa8cc6126@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
	<dd3c80060804022341k3fdfecfdk304ef8faa8cc6126@mail.gmail.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B172A3513@sbjgexmb1.amd.com>

It the code downloaded from "http://openbios.org/viewvc/trunk/?root=FILO
"can be used?

I have tried, but still failed, the message says:

"dma_to_td:can not find td"

 

 

 

Jason Wang

Intern

Electronic Engineering Lab

Peking University 

Beijing Technology Development Center

Advanced Micro Devices(AMD)

E-mail: Qingpei.Wang at amd.com <mailto:Qingpei.Wang at amd.com> 

     wangqingpei at hotmail.com

Phone:13426369984

<mailto:i at hotmail.com> 

 

________________________________

From: coreboot-bounces+qingpei.wang=amd.com at coreboot.org
[mailto:coreboot-bounces+qingpei.wang=amd.com at coreboot.org] On Behalf Of
Corey Osgood
Sent: Thursday, April 03, 2008 2:42 PM
To: ron minnich
Cc: Coreboot
Subject: Re: [coreboot] patch: dbe62 boots to FILO!

 

On undefined, ron minnich <rminnich at gmail.com> wrote:

	now how do we get a disk to boot? All we have is USB :-)
	
	ron
	
	--
	coreboot mailing list
	coreboot at coreboot.org
	http://www.coreboot.org/mailman/listinfo/coreboot


That's OHCI isn't it? Try my patch of Fridel's code!

-Corey

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From c-d.hailfinger.devel.2006 at gmx.net  Thu Apr  3 12:26:11 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 03 Apr 2008 12:26:11 +0200
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
Message-ID: <47F4B0C3.40901@gmx.net>

Great!

On 03.04.2008 08:04, ron minnich wrote:
> now how do we get a disk to boot? All we have is USB :-)
>   

> With this set of changes dbe62 gets to a FILO prompt. 
>
> Set manual settings for dbe62 PLL; the auto settings are giving 
> slightly wrong values
>
> Add call to dumplxmsr in dbe62 initram main()
>
> Add dumplxmsrs function to geodelx raminit support code
>
> Correct spelling of CAS. 
>
> The big one: set spd variables correctly. 
>
> The not so big one: there is a bug in com2 enable I don't understand.
> For now comment out two offending lines. The cs5536 debug prints
> should be reduced later. 
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   

The patch looks nice, but there are a few small problems.


> Index: southbridge/amd/cs5536/cs5536.c
> ===================================================================
> --- southbridge/amd/cs5536/cs5536.c	(revision 637)
> +++ southbridge/amd/cs5536/cs5536.c	(working copy)
> @@ -258,6 +258,7 @@
>  
>  	/* COM1 */
>  	if (sb->com1_enable) {
> +		printk(BIOS_SPEW, "uarts_init: enable com1\n");
>  		/* Set the address. */
>  		switch (sb->com1_address) {
>  		case 0x3F8:
> @@ -308,6 +309,7 @@
>  		wrmsr(MDD_UART1_CONF, msr);
>  	} else {
>  		/* Reset and disable COM1. */
> +		printk(BIOS_SPEW, "uarts_init: disable com1\n");
>  		msr = rdmsr(MDD_UART1_CONF);
>  		msr.lo = 1;			/* Reset */
>  		wrmsr(MDD_UART1_CONF, msr);
> @@ -322,6 +324,7 @@
>  
>  	/* COM2 */
>  	if (sb->com2_enable) {
> +		printk(BIOS_SPEW, "uarts_init: enable com2\n");
>  		switch (sb->com2_address) {
>  		case 0x3F8:
>  			addr = 7;
> @@ -339,28 +342,31 @@
>  		msr = rdmsr(MDD_LEG_IO);
>  		msr.lo |= addr << 20;
>  		wrmsr(MDD_LEG_IO, msr);
> +		printk(BIOS_SPEW, "uarts_init: wrote com2 address 0x%x\n", sb->com2_address);
>  
>  		/* Set the IRQ. */
>  		msr = rdmsr(MDD_IRQM_YHIGH);
>  		msr.lo |= sb->com2_irq << 28;
>  		wrmsr(MDD_IRQM_YHIGH, msr);
> -

Empty line removed. Intentional?

> +		printk(BIOS_SPEW, "uarts_init: set com2 irq\n");
>  		/* GPIO3 - UART2_RX */
>  		/* Set: Output Enable (0x4) */
>  		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
> +		printk(BIOS_SPEW, "uarts_init: set output enable\n");
>  		/* Set: OUTAUX1 Select (0x10) */
>  		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
> -

Same here.

> +		printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");
>  		/* GPIO4 - UART2_TX */
>  		/* Set: Input Enable (0x20) */
>  		outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
> +		printk(BIOS_SPEW, "uarts_init: set com2 input enable\n");
>  		/* Set: INAUX1 Select (0x34) */
> -		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
> -

Same here.

> +//		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT);
> +//		printk(BIOS_SPEW, "uarts_init: set INAUX2 for com2\n");
>  		/* Set: GPIO 3 + 3 Pull Up (0x18) */
>  		outl(GPIOL_3_SET | GPIOL_4_SET,
>  		     gpio_addr + GPIOL_PULLUP_ENABLE);
> -

Same here.

> +		printk(BIOS_SPEW, "uarts_init: set pullup com2\n");
>  		/* Enable COM2.
>  		 *
>  		 * Bit 1 = device enable
> @@ -369,7 +375,9 @@
>  		msr.lo = (1 << 4) | (1 << 1);
>  		msr.hi = 0;
>  		wrmsr(MDD_UART2_CONF, msr);
> +		printk(BIOS_SPEW, "uarts_init: com2 enabled\n");
>  	} else {
> +		printk(BIOS_SPEW, "uarts_init: disable com2\n");
>  		/* Reset and disable COM2. */
>  		msr = rdmsr(MDD_UART2_CONF);
>  		msr.lo = 1;			/* Reset */
> @@ -619,12 +627,15 @@
>  	setup_i8259();
>  	lpc_init(sb);
>  	uarts_init(sb);
> -

Same here.

> +	printk(BIOS_SPEW, "cs5536: done uarts_init\n");
>  	if (sb->enable_gpio_int_route) {
> +		printk(BIOS_SPEW, "cs5536: call vr_write\n");
>  		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
>  			 (sb->enable_gpio_int_route & 0xFFFF));
> +		printk(BIOS_SPEW, "cs5536: done first call vr_write\n");
>  		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
>  			 (sb->enable_gpio_int_route >> 16));
> +		printk(BIOS_SPEW, "cs5536: done second call vr_write\n");
>  	}
>  
>  	printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
> Index: mainboard/artecgroup/dbe62/initram.c
> ===================================================================
> --- mainboard/artecgroup/dbe62/initram.c	(revision 637)
> +++ mainboard/artecgroup/dbe62/initram.c	(working copy)
> @@ -33,9 +33,9 @@
>  #include <northbridge/amd/geodelx/raminit.h>
>  #include <spd.h>
>  
> -#define MANUALCONF 0		/* Do automatic strapped PLL config */
> -#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
> -#define PLLMSRLO 0x02000030
> +#define MANUALCONF 1		/* Do automatic strapped PLL config */

Change the comment to "...manual strapped..."

> +#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
> +#define PLLMSRLO 0x07de0080	/* from factory bios */

Hey, where did the fuctory go?

>  #define DIMM0 ((u8) 0xA0)
>  #define DIMM1 ((u8) 0xA2)
>  
> @@ -50,20 +50,68 @@
>  	u8 address;
>  	u8 data;
>  };
> +/*
> +ok, This is what I came up with. I would be interested in the results.

Please explain that comment.

> +spd : value(hex)
> +4: 8
> +5: 1
> +9: <= 7
> +12: 82
> +17: 4
> +31: 40
> +18: 10
> +23: 0
> +25: 0
> +27: 58
> +28: 3c
> +29: 58
> +30: 2d
> +42:4b
>  
> +I may have missed one so let me know. Also you might find this document helpful.
> +*/
> +
>  /* Save space by using a short list of SPD values used by Geode LX Memory init */
>  static const struct spd_entry spd_table[] = {
> +#if 1
> +	/* these were missing too :-) */
> +	{SPD_MEMORY_TYPE, 7},
> +	{SPD_NUM_ROWS, 13},
> +	/* from marc */
> +	{42, 0x4b},

42 is SPD_tRFC.

> +	{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
> +	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40},
> +	{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x2d},

This is SPD_tRAS.

> +	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
> +	{SPD_MIN_RAS_TO_CAS_DELAY, 0x58},
> +	{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x3c},

This is SPD_tRRD.

> +	{SPD_MIN_ROW_PRECHARGE_TIME, 0x58},

This is SPD_tRP.

> +	{SPD_NUM_BANKS_PER_SDRAM, 0x4},
> +	{SPD_NUM_COLUMNS, 0x8},
> +	{SPD_NUM_DIMM_BANKS, 0x1},
> +	{SPD_REFRESH, 0x82},
> +	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
> +	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
> +	/* these were missing and kind of important */
> +	{SPD_tRAS, 40},

Here SPD_tRAS is set again, but never used.

> +	{SPD_tRCD, 15},
> +	{SPD_tRFC, 70},

Here SPD_tRFC is set again, but this second value is never used.

> +	{SPD_tRP, 15},

Same for SPD_tRP.

> +	{SPD_tRRD, 10},

Same for SPD_tRRD.

> +
> +#endif
> +#if 0
>  	{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
>  	{SPD_BANK_DENSITY, 0x40},
>  	{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
>  	{SPD_MEMORY_TYPE, 7},
> -	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
> -	{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
> +	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10},
> +	{SPD_MODULE_ATTRIBUTES, 0xff},
>  	{SPD_NUM_BANKS_PER_SDRAM, 4},
> -	{SPD_PRIMARY_SDRAM_WIDTH, 8},
> +	{SPD_NUM_COLUMNS, 0xa},
>  	{SPD_NUM_DIMM_BANKS, 1},
> -	{SPD_NUM_COLUMNS, 0xa},
>  	{SPD_NUM_ROWS, 13},
> +	{SPD_PRIMARY_SDRAM_WIDTH, 8},
>  	{SPD_REFRESH, 0x3a},
>  	{SPD_SDRAM_CYCLE_TIME_2ND, 60},
>  	{SPD_SDRAM_CYCLE_TIME_3RD, 75},
> @@ -72,6 +120,7 @@
>  	{SPD_tRFC, 70},
>  	{SPD_tRP, 15},
>  	{SPD_tRRD, 10},
> +#endif

Can't we just merge the SPD array variants above? Introducing #if 0 is
not really something we can explain later.


>  };
>  
>  /**
> @@ -124,6 +173,8 @@
>    */
>  int main(void)
>  {
> +	void dumplxmsrs(int level);

Please remove the level argument.

> +
>  	u8 smb_devices[] =  {
>  		DIMM0, DIMM1
>  	};
> @@ -151,8 +202,11 @@
>  	sdram_enable(DIMM0, DIMM1);
>  	printk(BIOS_DEBUG, "done sdram enable\n");
>  
> +	dumplxmsrs(BIOS_DEBUG);
>  	/* Check low memory */
> -	ram_check(0x00000000, 640*1024);
> +	/* passed. Don't bother any more */
> +	/* Note that the range 0x87000 will fail; that's the stack! */
> +	/*	ram_check(0x00000000, 640*1024);*/
>  
>  	printk(BIOS_DEBUG, "stage1 returns\n");
>  	return 0;
> Index: northbridge/amd/geodelx/raminit.c
> ===================================================================
> --- northbridge/amd/geodelx/raminit.c	(revision 637)
> +++ northbridge/amd/geodelx/raminit.c	(working copy)
> @@ -35,6 +35,42 @@
>  
>  u8 spd_read_byte(u16 device, u8 address);
>  
> +
> +/** 
> + * Dump key MSR values for ram init. You can call this function and then use it to 
> + * compare to a fuctory bios setting.
> + * @param level printk level
> + */
> +
> +void dumplxmsrs(int level)

level should be hardcoded.

> +{
> +	static unsigned long msrs[] = {
> +        	MC_CF07_DATA, 
> +        	MC_CF8F_DATA, 
> +        	MC_CF1017_DATA, 
> +        	GLCP_DELAY_CONTROLS, 
> +        	MC_CFCLK_DBUG, 
> +        	MC_CF_PMCTR,
> +		GLCP_SYS_RSTPLL
> +	};
> +	static char *msrnames[] = {
> +        	"MC_CF07_DATA", 
> +        	"MC_CF8F_DATA", 
> +        	"MC_CF1017_DATA", 
> +        	"GLCP_DELAY_CONTROLS", 
> +        	"MC_CFCLK_DBUG", 
> +        	"MC_CF_PMCTR",
> +		"PLL reg"
> +	};
> +	int i;
> +
> +	for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){

Use ARRAY_SIZE instead.

> +		struct msr msr;
> +		msr = rdmsr(msrs[i]);
> +		printk(level, "(%lx): %x.%x\n",  msrs[i], msr.hi, msr.lo);
> +	}
> +
> +}
>  /**
>   * Halt and Catch Fire. Print an error, then loop, sending NULLs on serial port, 
>   * to ensure the message is visible. 
> @@ -389,7 +425,7 @@
>  		hlt();
>  	}
>  
> -	printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
> +	printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
>  	msr = rdmsr(MC_CF8F_DATA);
>  	msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
>  	msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;

Otherwise, the patch looks fine.

Reworked patch follows. It should be identical from a code point of
view, but it would be great if you could test anyway.
Please note that the patch is against HEAD. Same patch is also attached.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Index: LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c
===================================================================
--- LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Arbeitskopie)
@@ -258,6 +258,7 @@
 
 	/* COM1 */
 	if (sb->com1_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable com1\n");
 		/* Set the address. */
 		switch (sb->com1_address) {
 		case 0x3F8:
@@ -308,6 +309,7 @@
 		wrmsr(MDD_UART1_CONF, msr);
 	} else {
 		/* Reset and disable COM1. */
+		printk(BIOS_SPEW, "uarts_init: disable com1\n");
 		msr = rdmsr(MDD_UART1_CONF);
 		msr.lo = 1;			/* Reset */
 		wrmsr(MDD_UART1_CONF, msr);
@@ -322,6 +324,7 @@
 
 	/* COM2 */
 	if (sb->com2_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable com2\n");
 		switch (sb->com2_address) {
 		case 0x3F8:
 			addr = 7;
@@ -339,27 +342,33 @@
 		msr = rdmsr(MDD_LEG_IO);
 		msr.lo |= addr << 20;
 		wrmsr(MDD_LEG_IO, msr);
+		printk(BIOS_SPEW, "uarts_init: wrote com2 address 0x%x\n", sb->com2_address);
 
 		/* Set the IRQ. */
 		msr = rdmsr(MDD_IRQM_YHIGH);
 		msr.lo |= sb->com2_irq << 28;
 		wrmsr(MDD_IRQM_YHIGH, msr);
+		printk(BIOS_SPEW, "uarts_init: set com2 irq\n");
 
 		/* GPIO3 - UART2_RX */
 		/* Set: Output Enable (0x4) */
 		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set output enable\n");
 		/* Set: OUTAUX1 Select (0x10) */
 		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+		printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");
 
 		/* GPIO4 - UART2_TX */
 		/* Set: Input Enable (0x20) */
 		outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set com2 input enable\n");
 		/* Set: INAUX1 Select (0x34) */
-		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
-
+//		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT);
+//		printk(BIOS_SPEW, "uarts_init: set INAUX2 for com2\n");
 		/* Set: GPIO 3 + 3 Pull Up (0x18) */
 		outl(GPIOL_3_SET | GPIOL_4_SET,
 		     gpio_addr + GPIOL_PULLUP_ENABLE);
+		printk(BIOS_SPEW, "uarts_init: set pullup com2\n");
 
 		/* Enable COM2.
 		 *
@@ -369,7 +378,9 @@
 		msr.lo = (1 << 4) | (1 << 1);
 		msr.hi = 0;
 		wrmsr(MDD_UART2_CONF, msr);
+		printk(BIOS_SPEW, "uarts_init: com2 enabled\n");
 	} else {
+		printk(BIOS_SPEW, "uarts_init: disable com2\n");
 		/* Reset and disable COM2. */
 		msr = rdmsr(MDD_UART2_CONF);
 		msr.lo = 1;			/* Reset */
@@ -620,11 +631,15 @@
 	lpc_init(sb);
 	uarts_init(sb);
 
+	printk(BIOS_SPEW, "cs5536: done uarts_init\n");
 	if (sb->enable_gpio_int_route) {
+		printk(BIOS_SPEW, "cs5536: call vr_write\n");
 		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
 			 (sb->enable_gpio_int_route & 0xFFFF));
+		printk(BIOS_SPEW, "cs5536: done first call vr_write\n");
 		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
 			 (sb->enable_gpio_int_route >> 16));
+		printk(BIOS_SPEW, "cs5536: done second call vr_write\n");
 	}
 
 	printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",
Index: LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c
===================================================================
--- LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Arbeitskopie)
@@ -33,9 +33,9 @@
 #include <northbridge/amd/geodelx/raminit.h>
 #include <spd.h>
 
-#define MANUALCONF 0		/* Do automatic strapped PLL config */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
-#define PLLMSRLO 0x02000030
+#define MANUALCONF 1		/* Do manual strapped PLL config */
+#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
+#define PLLMSRLO 0x07de0080	/* from fuctory bios */
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)
 
@@ -50,28 +50,45 @@
 	u8 address;
 	u8 data;
 };
+/*
+ok, This is what I came up with. I would be interested in the results.
+spd : value(hex)
+4: 8
+5: 1
+9: <= 7
+12: 82
+17: 4
+31: 40
+18: 10
+23: 0
+25: 0
+27: 58
+28: 3c
+29: 58
+30: 2d
+42:4b
 
+I may have missed one so let me know. Also you might find this document helpful.
+*/
+
 /* Save space by using a short list of SPD values used by Geode LX Memory init */
 static const struct spd_entry spd_table[] = {
-	{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
-	{SPD_BANK_DENSITY, 0x40},
-	{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
+	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40}, /* SPD_BANK_DENSITY */
+	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
+	{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
 	{SPD_MEMORY_TYPE, 7},
-	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
-	{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
 	{SPD_NUM_BANKS_PER_SDRAM, 4},
-	{SPD_PRIMARY_SDRAM_WIDTH, 8},
 	{SPD_NUM_DIMM_BANKS, 1},
-	{SPD_NUM_COLUMNS, 0xa},
+	{SPD_NUM_COLUMNS, 0x8},
 	{SPD_NUM_ROWS, 13},
-	{SPD_REFRESH, 0x3a},
-	{SPD_SDRAM_CYCLE_TIME_2ND, 60},
-	{SPD_SDRAM_CYCLE_TIME_3RD, 75},
-	{SPD_tRAS, 40},
-	{SPD_tRCD, 15},
-	{SPD_tRFC, 70},
-	{SPD_tRP, 15},
-	{SPD_tRRD, 10},
+	{SPD_REFRESH, 0x82},
+	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
+	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
+	{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x2d}, /* SPD_tRAS */
+	{SPD_MIN_RAS_TO_CAS_DELAY, 0x58}, /* SPD_tRCD */
+	{SPD_tRFC, 0x4b},
+	{SPD_MIN_ROW_PRECHARGE_TIME, 0x58}, /* SPD_tRP */
+	{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x3c}, /* SPD_tRRD */
 };
 
 /**
@@ -124,6 +141,8 @@
   */
 int main(void)
 {
+	void dumplxmsrs(void);
+
 	u8 smb_devices[] =  {
 		DIMM0, DIMM1
 	};
@@ -151,8 +170,11 @@
 	sdram_enable(DIMM0, DIMM1);
 	printk(BIOS_DEBUG, "done sdram enable\n");
 
+	dumplxmsrs();
 	/* Check low memory */
-	ram_check(0x00000000, 640*1024);
+	/* passed. Don't bother any more */
+	/* Note that the range 0x87000 will fail; that's the stack! */
+	/*	ram_check(0x00000000, 640*1024);*/
 
 	printk(BIOS_DEBUG, "stage1 returns\n");
 	return 0;
Index: LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Revision 647)
+++ LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Arbeitskopie)
@@ -35,6 +35,43 @@
 
 u8 spd_read_byte(u16 device, u8 address);
 
+
+/** 
+ * Dump key MSR values for ram init. You can call this function and then use it to 
+ * compare to a fuctory bios setting.
+ * @param level printk level
+ */
+void dumplxmsrs(void)
+{
+	static unsigned long msrs[] = {
+        	MC_CF07_DATA, 
+        	MC_CF8F_DATA, 
+        	MC_CF1017_DATA, 
+        	GLCP_DELAY_CONTROLS, 
+        	MC_CFCLK_DBUG, 
+        	MC_CF_PMCTR,
+		GLCP_SYS_RSTPLL
+	};
+	static char *msrnames[] = {
+        	"MC_CF07_DATA", 
+        	"MC_CF8F_DATA", 
+        	"MC_CF1017_DATA", 
+        	"GLCP_DELAY_CONTROLS", 
+        	"MC_CFCLK_DBUG", 
+        	"MC_CF_PMCTR",
+		"PLL reg"
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(msrs); i++) {
+		struct msr msr;
+		msr = rdmsr(msrs[i]);
+		printk(BIOS_DEBUG, "%s (%lx): %x.%x\n",  msrnames[i], msrs[i],
+			msr.hi, msr.lo);
+	}
+
+}
+
 /**
  * Halt and Catch Fire. Print an error, then loop, sending NULLs on
  * serial port, to ensure the message is visible.
@@ -387,7 +424,7 @@
 		hlt();
 	}
 
-	printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
+	printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
 	msr = rdmsr(MC_CF8F_DATA);
 	msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
 	msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;


-------------- next part --------------
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Name: linuxbios3_dbe62_ron_reworked.diff
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20080403/b8beb1af/attachment.ksh>

From uwe at hermann-uwe.de  Thu Apr  3 14:09:36 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 3 Apr 2008 14:09:36 +0200
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <47F4B0C3.40901@gmx.net>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
	<47F4B0C3.40901@gmx.net>
Message-ID: <20080403120935.GA21945@greenwood>

On Thu, Apr 03, 2008 at 12:26:11PM +0200, Carl-Daniel Hailfinger wrote:
> The patch looks nice, but there are a few small problems.
> Otherwise, the patch looks fine.
> 
> Reworked patch follows. It should be identical from a code point of
> view, but it would be great if you could test anyway.
> Please note that the patch is against HEAD. Same patch is also attached.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Please keep the Signed-off-by from Ron, i.e. the commit message (and
follow-up patches) should have _both_ Signed-off-by's.


> Index: LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c
> ===================================================================
> --- LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Revision 647)
> +++ LinuxBIOSv3-dbe62/southbridge/amd/cs5536/cs5536.c	(Arbeitskopie)
> @@ -258,6 +258,7 @@
>  
>  	/* COM1 */
>  	if (sb->com1_enable) {
> +		printk(BIOS_SPEW, "uarts_init: enable com1\n");

com1 -> COM1 maybe.


>  		/* Set the address. */
>  		switch (sb->com1_address) {
>  		case 0x3F8:
> @@ -308,6 +309,7 @@
>  		wrmsr(MDD_UART1_CONF, msr);
>  	} else {
>  		/* Reset and disable COM1. */
> +		printk(BIOS_SPEW, "uarts_init: disable com1\n");

Ditto (and in various other places).


> Index: LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c
> ===================================================================
> --- LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Revision 647)
> +++ LinuxBIOSv3-dbe62/mainboard/artecgroup/dbe62/initram.c	(Arbeitskopie)
> @@ -33,9 +33,9 @@
>  #include <northbridge/amd/geodelx/raminit.h>
>  #include <spd.h>
>  
> -#define MANUALCONF 0		/* Do automatic strapped PLL config */
> -#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
> -#define PLLMSRLO 0x02000030
> +#define MANUALCONF 1		/* Do manual strapped PLL config */
> +#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
> +#define PLLMSRLO 0x07de0080	/* from fuctory bios */
>  #define DIMM0 ((u8) 0xA0)
>  #define DIMM1 ((u8) 0xA2)
>  
> @@ -50,28 +50,45 @@
>  	u8 address;
>  	u8 data;
>  };
> +/*
> +ok, This is what I came up with. I would be interested in the results.
> +spd : value(hex)
> +4: 8
> +5: 1
> +9: <= 7
> +12: 82
> +17: 4
> +31: 40
> +18: 10
> +23: 0
> +25: 0
> +27: 58
> +28: 3c
> +29: 58
> +30: 2d
> +42:4b
>  
> +I may have missed one so let me know. Also you might find this document helpful.
> +*/

Yep, needs a more verbose comment IMO. Also, please use the standard
commenting style

/*
 * Foo.
 * Bar.
 */

(or Doxygen-style if it should end up in Doxygen's output)


> +	dumplxmsrs();
>  	/* Check low memory */
> -	ram_check(0x00000000, 640*1024);
> +	/* passed. Don't bother any more */

This comment doesn't make much sense.


> +	/* Note that the range 0x87000 will fail; that's the stack! */
> +	/*	ram_check(0x00000000, 640*1024);*/
>  
>  	printk(BIOS_DEBUG, "stage1 returns\n");
>  	return 0;
> Index: LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c
> ===================================================================
> --- LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Revision 647)
> +++ LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Arbeitskopie)
> @@ -35,6 +35,43 @@
>  
>  u8 spd_read_byte(u16 device, u8 address);
>  
> +
> +/** 
> + * Dump key MSR values for ram init. You can call this function and then use it to 

ram -> RAM.


> + * compare to a fuctory bios setting.

bios -> BIOS


> + * @param level printk level
> + */
> +void dumplxmsrs(void)
> +{
> +	static unsigned long msrs[] = {
> +        	MC_CF07_DATA, 
> +        	MC_CF8F_DATA, 
> +        	MC_CF1017_DATA, 
> +        	GLCP_DELAY_CONTROLS, 
> +        	MC_CFCLK_DBUG, 
> +        	MC_CF_PMCTR,
> +		GLCP_SYS_RSTPLL
> +	};
> +	static char *msrnames[] = {

Can be 'const' too, I guess.

(same for the other file)


> +        	"MC_CF07_DATA", 
> +        	"MC_CF8F_DATA", 
> +        	"MC_CF1017_DATA", 
> +        	"GLCP_DELAY_CONTROLS", 
> +        	"MC_CFCLK_DBUG", 
> +        	"MC_CF_PMCTR",
> +		"PLL reg"
> +	};
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(msrs); i++) {
> +		struct msr msr;
> +		msr = rdmsr(msrs[i]);
> +		printk(BIOS_DEBUG, "%s (%lx): %x.%x\n",  msrnames[i], msrs[i],
                                                       ^^
                                                only one space

(same for the other file)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From bari at onelabs.com  Thu Apr  3 15:29:27 2008
From: bari at onelabs.com (bari)
Date: Thu, 03 Apr 2008 08:29:27 -0500
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
Message-ID: <47F4DBB7.4050100@onelabs.com>

malatesh kamatad wrote:
>
> Hi all..
>  
>      I have worked with PM49fl00x.diff patch ,its worked fine and i 
> got the output as below
>     
The PM49fl00x can work in LPC and FWH modes. Do you know which mode is 
being used?
What mainboard did you test this in?
>                   
>   Now i am working on SST49LF004B 
>                                    33-4C-NHE
>                                    0710022-CA   with the  motherboard  
> K8Upgrade-VM800
>                  
>   The flashrom detect flash device on this board, But the erasing and 
> writting operation is not happening properly
>    hier flashrom output :             
>
Is this the board by ASRock?

-Bari





From c-d.hailfinger.devel.2006 at gmx.net  Thu Apr  3 17:19:15 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 03 Apr 2008 17:19:15 +0200
Subject: [coreboot] Summit recordings/live stream
Message-ID: <47F4F573.6050008@gmx.net>

Hi,

could someone please record the various talks at the summit, preferably
both video and audio. Having audio available would help immensely even
if no video is provided.

In case nobody has equipment for that, any standard headset for VoIP
calls has a pretty decent microphone which can be used to record audio
with a laptop. One hour of 44 kHz, 16bit mono recording needs ~300 MB as
uncompressed Wave file.

Regards,
Carl-Daniel



From eswierk at arastra.com  Thu Apr  3 18:13:50 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 3 Apr 2008 09:13:50 -0700
Subject: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
In-Reply-To: <20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>
References: <e6c711510803290007j4c512a49jfcddc5df0bf197b9@mail.gmail.com>
	<20080329093801.52hprv9su8wswgs0@www.smittys.pointclark.net>
	<e6c711510803291503s628f0706q5bc51eea4b75de6@mail.gmail.com>
	<20080329182303.34dg56si8ccoggo0@www.smittys.pointclark.net>
	<20080329202055.cw5zfcv38k0ok8s8@www.smittys.pointclark.net>
	<e6c711510803292330n78c27d62ia1364e14371ed2f5@mail.gmail.com>
	<20080330101806.3uqz419d4o8owcsk@www.smittys.pointclark.net>
	<47EFD2E1.9080200@gmx.net>
	<20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>
Message-ID: <e6c711510804030913t2e6f1701y144db0a5ade2ebe@mail.gmail.com>

On Wed, Apr 2, 2008 at 10:48 AM,  <joe at smittys.pointclark.net> wrote:
>  Hmm, this is going to be interesting on the ICH4, I still have to look at
> how the other ICH's are setup. The TCO Timer Halt is acually located in I/O
> space not PCI configuration space. It is ACPIBASE + TCOBASE(60h) +
> TCO1_CNT(08h) bit 11. We'll see.

This is exactly how it works on the Intel 3100; see
i3100_halt_tco_timer() in my patch
(http://qa.coreboot.org/log_commit.php?revision=3198).

--Ed



From joe at smittys.pointclark.net  Thu Apr  3 18:34:04 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Thu, 03 Apr 2008 12:34:04 -0400
Subject: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
In-Reply-To: <e6c711510804030913t2e6f1701y144db0a5ade2ebe@mail.gmail.com>
References: <e6c711510803290007j4c512a49jfcddc5df0bf197b9@mail.gmail.com>
	<20080329093801.52hprv9su8wswgs0@www.smittys.pointclark.net>
	<e6c711510803291503s628f0706q5bc51eea4b75de6@mail.gmail.com>
	<20080329182303.34dg56si8ccoggo0@www.smittys.pointclark.net>
	<20080329202055.cw5zfcv38k0ok8s8@www.smittys.pointclark.net>
	<e6c711510803292330n78c27d62ia1364e14371ed2f5@mail.gmail.com>
	<20080330101806.3uqz419d4o8owcsk@www.smittys.pointclark.net>
	<47EFD2E1.9080200@gmx.net>
	<20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>
	<e6c711510804030913t2e6f1701y144db0a5ade2ebe@mail.gmail.com>
Message-ID: <20080403123404.v9110uws0s848wsg@www.smittys.pointclark.net>

Quoting Ed Swierk <eswierk at arastra.com>:

> On Wed, Apr 2, 2008 at 10:48 AM,  <joe at smittys.pointclark.net> wrote:
>>  Hmm, this is going to be interesting on the ICH4, I still have to look at
>> how the other ICH's are setup. The TCO Timer Halt is acually located in I/O
>> space not PCI configuration space. It is ACPIBASE + TCOBASE(60h) +
>> TCO1_CNT(08h) bit 11. We'll see.
>
> This is exactly how it works on the Intel 3100; see
> i3100_halt_tco_timer() in my patch
> (http://qa.coreboot.org/log_commit.php?revision=3198).
>
> --Ed
>
Wow your right:-) Looks like the only difference is the I/O Base  
address is 0x00000500 on the ICH series, this should be simple than.  
Thanks for laying down the base code Ed :-)

Thanks - Joe



From rminnich at gmail.com  Thu Apr  3 18:47:21 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 3 Apr 2008 09:47:21 -0700
Subject: [coreboot] Summit recordings/live stream
In-Reply-To: <47F4F573.6050008@gmx.net>
References: <47F4F573.6050008@gmx.net>
Message-ID: <13426df10804030947m5ae5d9b6h8dbbaa0a17916ed1@mail.gmail.com>

well, we may do recording if we have enough people to give talks to :-)

I'm going to have a camera courtesy the conference.

ron



From eswierk at arastra.com  Thu Apr  3 18:50:16 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 3 Apr 2008 09:50:16 -0700
Subject: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
In-Reply-To: <20080403123404.v9110uws0s848wsg@www.smittys.pointclark.net>
References: <e6c711510803290007j4c512a49jfcddc5df0bf197b9@mail.gmail.com>
	<e6c711510803291503s628f0706q5bc51eea4b75de6@mail.gmail.com>
	<20080329182303.34dg56si8ccoggo0@www.smittys.pointclark.net>
	<20080329202055.cw5zfcv38k0ok8s8@www.smittys.pointclark.net>
	<e6c711510803292330n78c27d62ia1364e14371ed2f5@mail.gmail.com>
	<20080330101806.3uqz419d4o8owcsk@www.smittys.pointclark.net>
	<47EFD2E1.9080200@gmx.net>
	<20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>
	<e6c711510804030913t2e6f1701y144db0a5ade2ebe@mail.gmail.com>
	<20080403123404.v9110uws0s848wsg@www.smittys.pointclark.net>
Message-ID: <e6c711510804030950r2bd0ecd4ya2f380435036518@mail.gmail.com>

On Thu, Apr 3, 2008 at 9:34 AM,  <joe at smittys.pointclark.net> wrote:
>  Wow your right:-) Looks like the only difference is the I/O Base address is
> 0x00000500 on the ICH series, this should be simple than. Thanks for laying
> down the base code Ed :-)

I'm not sure what you mean--you get to choose the base address for the
ACPI I/O registers, and you program that into the ACPIBASE register
(offset 0x40 in the LPC device's config space). The  choice is fairly
arbitrary, as this code runs very early during the boot process, well
before most other I/O regions are allocated. Just don't overlap some
important I/O address like 0x3f8 (owned by the serial port).

--Ed



From joe at smittys.pointclark.net  Thu Apr  3 18:52:40 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Thu, 03 Apr 2008 12:52:40 -0400
Subject: [coreboot] Summit recordings/live stream
In-Reply-To: <13426df10804030947m5ae5d9b6h8dbbaa0a17916ed1@mail.gmail.com>
References: <47F4F573.6050008@gmx.net>
	<13426df10804030947m5ae5d9b6h8dbbaa0a17916ed1@mail.gmail.com>
Message-ID: <20080403125240.d96hayfhss4gw0cc@www.smittys.pointclark.net>

Quoting ron minnich <rminnich at gmail.com>:

> well, we may do recording if we have enough people to give talks to :-)
>
> I'm going to have a camera courtesy the conference.
>
> ron
>
SWEET! This works out great for people (me) that arn't able to make  
it, I can't wait to see it :-)

Thanks - Joe



From joe at smittys.pointclark.net  Thu Apr  3 19:06:34 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Thu, 03 Apr 2008 13:06:34 -0400
Subject: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
In-Reply-To: <e6c711510804030950r2bd0ecd4ya2f380435036518@mail.gmail.com>
References: <e6c711510803290007j4c512a49jfcddc5df0bf197b9@mail.gmail.com>
	<e6c711510803291503s628f0706q5bc51eea4b75de6@mail.gmail.com>
	<20080329182303.34dg56si8ccoggo0@www.smittys.pointclark.net>
	<20080329202055.cw5zfcv38k0ok8s8@www.smittys.pointclark.net>
	<e6c711510803292330n78c27d62ia1364e14371ed2f5@mail.gmail.com>
	<20080330101806.3uqz419d4o8owcsk@www.smittys.pointclark.net>
	<47EFD2E1.9080200@gmx.net>
	<20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>
	<e6c711510804030913t2e6f1701y144db0a5ade2ebe@mail.gmail.com>
	<20080403123404.v9110uws0s848wsg@www.smittys.pointclark.net>
	<e6c711510804030950r2bd0ecd4ya2f380435036518@mail.gmail.com>
Message-ID: <20080403130634.tqeuhy3yo8k8wg8g@www.smittys.pointclark.net>

Quoting Ed Swierk <eswierk at arastra.com>:

> On Thu, Apr 3, 2008 at 9:34 AM,  <joe at smittys.pointclark.net> wrote:
>>  Wow your right:-) Looks like the only difference is the I/O Base address is
>> 0x00000500 on the ICH series, this should be simple than. Thanks for laying
>> down the base code Ed :-)
>
> I'm not sure what you mean--you get to choose the base address for the
> ACPI I/O registers, and you program that into the ACPIBASE register
> (offset 0x40 in the LPC device's config space). The  choice is fairly
> arbitrary, as this code runs very early during the boot process, well
> before most other I/O regions are allocated. Just don't overlap some
> important I/O address like 0x3f8 (owned by the serial port).
>
> --Ed
>
I'm not sure what you mean?? I can't just pick any old base address  
for the ACPI I/O registers, it is already pre-determined in  
i82801xx_lpc.c at 0x00000500. So all I need to do is set  
ACPIBASE(00000500h) +
TCOBASE(60h) + TCO1_CNT(08h) = 0x00000568 bit 11 to 1, it's that  
simple. I know this will run early before i82801xx_lpc.c but we don't  
want any conflicts do we?

Thanks - Joe



From eswierk at arastra.com  Thu Apr  3 19:19:22 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Thu, 3 Apr 2008 10:19:22 -0700
Subject: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
In-Reply-To: <20080403130634.tqeuhy3yo8k8wg8g@www.smittys.pointclark.net>
References: <e6c711510803290007j4c512a49jfcddc5df0bf197b9@mail.gmail.com>
	<20080329202055.cw5zfcv38k0ok8s8@www.smittys.pointclark.net>
	<e6c711510803292330n78c27d62ia1364e14371ed2f5@mail.gmail.com>
	<20080330101806.3uqz419d4o8owcsk@www.smittys.pointclark.net>
	<47EFD2E1.9080200@gmx.net>
	<20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>
	<e6c711510804030913t2e6f1701y144db0a5ade2ebe@mail.gmail.com>
	<20080403123404.v9110uws0s848wsg@www.smittys.pointclark.net>
	<e6c711510804030950r2bd0ecd4ya2f380435036518@mail.gmail.com>
	<20080403130634.tqeuhy3yo8k8wg8g@www.smittys.pointclark.net>
Message-ID: <e6c711510804031019m62edd06dm12e340718daadf57@mail.gmail.com>

On Thu, Apr 3, 2008 at 10:06 AM,  <joe at smittys.pointclark.net> wrote:
>  I'm not sure what you mean?? I can't just pick any old base address
>  for the ACPI I/O registers, it is already pre-determined in
>  i82801xx_lpc.c at 0x00000500. So all I need to do is set
>  ACPIBASE(00000500h) +
>  TCOBASE(60h) + TCO1_CNT(08h) = 0x00000568 bit 11 to 1, it's that
>  simple. I know this will run early before i82801xx_lpc.c but we don't
>  want any conflicts do we?

As long as the early code disables the I/O region when it's finished
using it (as i3100_halt_tco_timer() does), there's no possibility of a
conflict. But I think we're in violent agreement that 0x0500 will work
just fine.

--Ed



From joe at smittys.pointclark.net  Thu Apr  3 21:29:44 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Thu, 03 Apr 2008 15:29:44 -0400
Subject: [coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset
In-Reply-To: <e6c711510804031019m62edd06dm12e340718daadf57@mail.gmail.com>
References: <e6c711510803290007j4c512a49jfcddc5df0bf197b9@mail.gmail.com>
	<20080329202055.cw5zfcv38k0ok8s8@www.smittys.pointclark.net>
	<e6c711510803292330n78c27d62ia1364e14371ed2f5@mail.gmail.com>
	<20080330101806.3uqz419d4o8owcsk@www.smittys.pointclark.net>
	<47EFD2E1.9080200@gmx.net>
	<20080402134837.hc3zvq4aow8cc4w4@www.smittys.pointclark.net>
	<e6c711510804030913t2e6f1701y144db0a5ade2ebe@mail.gmail.com>
	<20080403123404.v9110uws0s848wsg@www.smittys.pointclark.net>
	<e6c711510804030950r2bd0ecd4ya2f380435036518@mail.gmail.com>
	<20080403130634.tqeuhy3yo8k8wg8g@www.smittys.pointclark.net>
	<e6c711510804031019m62edd06dm12e340718daadf57@mail.gmail.com>
Message-ID: <20080403152944.d7jliyuvscc48oso@www.smittys.pointclark.net>

Quoting Ed Swierk <eswierk at arastra.com>:

> On Thu, Apr 3, 2008 at 10:06 AM,  <joe at smittys.pointclark.net> wrote:
>>  I'm not sure what you mean?? I can't just pick any old base address
>>  for the ACPI I/O registers, it is already pre-determined in
>>  i82801xx_lpc.c at 0x00000500. So all I need to do is set
>>  ACPIBASE(00000500h) +
>>  TCOBASE(60h) + TCO1_CNT(08h) = 0x00000568 bit 11 to 1, it's that
>>  simple. I know this will run early before i82801xx_lpc.c but we don't
>>  want any conflicts do we?
>
> As long as the early code disables the I/O region when it's finished
> using it (as i3100_halt_tco_timer() does), there's no possibility of a
> conflict. But I think we're in violent agreement that 0x0500 will work
> just fine.
>
No need for a violent agreement Ed. As you may already know, sometimes  
I like to debate things to make sure I understand them properly. This  
is how I learn :-)

Thanks - Joe



From peter at stuge.se  Thu Apr  3 22:10:55 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 3 Apr 2008 22:10:55 +0200
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
Message-ID: <20080403201055.31710.qmail@stuge.se>

On Wed, Apr 02, 2008 at 11:04:14PM -0700, ron minnich wrote:
> now how do we get a disk to boot? All we have is USB :-)

Go LAB. I tried on the alix but never got the full 4MByte out of the
Artec dongle. I probably did not enable address decode in 5536
properly.


//Peter



From peter at stuge.se  Thu Apr  3 22:12:40 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 3 Apr 2008 22:12:40 +0200
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
Message-ID: <20080403201240.32517.qmail@stuge.se>

On Thu, Apr 03, 2008 at 11:29:14AM +0530, malatesh kamatad wrote:
>   Now i am working on SST49LF004B
..

> [root at localhost ~]# flashrom -E
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> SST49LF004A/B found at physical address 0xfff80000.
> Flash part is SST49LF004A/B (512 KB).
> Erasing flash chip

Please try reading back the flash chip contents after the erase.
Maybe the file contents can give some hints.


//Peter



From uwe at hermann-uwe.de  Thu Apr  3 23:22:20 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 3 Apr 2008 23:22:20 +0200
Subject: [coreboot] [PATCH] coreinfo: Build system fixes
Message-ID: <20080403212220.GA26504@greenwood>

See patch.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From jordan.crouse at amd.com  Thu Apr  3 23:30:49 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 3 Apr 2008 15:30:49 -0600
Subject: [coreboot] coreinfo: Build system fixes
In-Reply-To: <20080403212220.GA26504@greenwood>
References: <20080403212220.GA26504@greenwood>
Message-ID: <20080403213049.GG21011@cosmic.amd.com>

On 03/04/08 23:22 +0200, Uwe Hermann wrote:
> See patch.
> 
> 
> Uwe.
> -- 
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

> Doing another 'make' after a 'make clean' was broken until now. Fix it
> by not deleting build/config.h during 'make clean' (only in 'make distclean').
> 
> Also, change the default behaviour of 'make' from asking the user to
> run 'make config' (or similar) to actually _run_ 'make config' without
> asking questions. It's always possible to explicitly invoke
> 'make menuconfig' or 'make xconfig' and so on, of course.
> 
> Finally, make _all_ targets (allyesconfig, randconfig, and so on)
> generate a build/config.h file, as we always #include it.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

> Index: Makefile
> ===================================================================
> --- Makefile	(Revision 3210)
> +++ Makefile	(Arbeitskopie)
> @@ -59,8 +59,7 @@
>  
>  ifeq ($(strip $(HAVE_DOTCONFIG)),)
>  
> -all:
> -	$(Q)printf "Please run make config/menuconfig/xconfig/gconfig first.\n"
> +all: config
>  
>  else
>  
> @@ -91,9 +90,10 @@
>  	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
>  
>  clean:
> -	$(Q)rm -rf build
> +	$(Q)rm -rf build/util build/*.conf build/*.cmd build/*.elf build/*.o
>  
>  distclean: clean
> +	$(Q)rm -rf build
>  	$(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
>  
>  include util/kconfig/Makefile
> Index: util/kconfig/confdata.c
> ===================================================================
> --- util/kconfig/confdata.c	(Revision 3210)
> +++ util/kconfig/confdata.c	(Arbeitskopie)
> @@ -679,8 +679,10 @@
>  
>  	file_write_dep("build/auto.conf.cmd");
>  
> +#if 0
>  	if (conf_split_config())
>  		return 1;
> +#endif
>  
>  	out = fopen(".tmpconfig", "w");
>  	if (!out)
> Index: util/kconfig/conf.c
> ===================================================================
> --- util/kconfig/conf.c	(Revision 3210)
> +++ util/kconfig/conf.c	(Arbeitskopie)
> @@ -624,6 +624,10 @@
>  		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
>  		return 1;
>  	}
> +	if (conf_write_autoconf()) {
> +		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
> +		return 1;
> +	}
>  skip_check:
>  	if (input_mode == ask_silent && conf_write_autoconf()) {
>  		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));

> -- 
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From c-d.hailfinger.devel.2006 at gmx.net  Thu Apr  3 23:54:48 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 03 Apr 2008 23:54:48 +0200
Subject: [coreboot] [PATCH] add unconditional fake 512kByte flash chip match
Message-ID: <47F55228.2090002@gmx.net>

Add unconditional fake 512kByte flash chip match. For debugging purposes
only. Not for merge.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flash.h
===================================================================
--- flash.h	(Revision 3210)
+++ flash.h	(Arbeitskopie)
@@ -316,6 +316,7 @@
 
 /* flashrom.c */
 int map_flash_registers(struct flashchip *flash);
+int probe_fake(struct flashchip *flash);
 
 /* layout.c */
 int show_id(uint8_t *bios, int size);
Index: flashchips.c
===================================================================
--- flashchips.c	(Revision 3210)
+++ flashchips.c	(Arbeitskopie)
@@ -137,6 +137,7 @@
 	{"PMC",		"unknown SPI chip",	PMC_ID,		GENERIC_DEVICE_ID,	0,	0,		probe_spi,		NULL,				NULL},
 	{"SST",		"unknown SPI chip",	SST_ID,		GENERIC_DEVICE_ID,	0,	0,		probe_spi,		NULL,				NULL},
 	{"ST",		"unknown SPI chip",	ST_ID,		GENERIC_DEVICE_ID,	0,	0,		probe_spi,		NULL,				NULL},
+	{"Fake",	"Fake flash chip",	0,		0,			512,	0,		probe_fake,		NULL,				NULL},
 
 	{NULL,}
 };
Index: flashrom.c
===================================================================
--- flashrom.c	(Revision 3210)
+++ flashrom.c	(Arbeitskopie)
@@ -99,6 +99,11 @@
 	return 0;
 }
 
+int probe_fake(struct flashchip *flash)
+{
+	return 1;
+}
+
 struct flashchip *probe_flash(struct flashchip *flash)
 {
 	volatile uint8_t *bios;





From uwe at hermann-uwe.de  Fri Apr  4 00:18:37 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Apr 2008 00:18:37 +0200
Subject: [coreboot] [PATCH] libpayload: SHA-1 implementation
Message-ID: <20080403221837.GB26504@greenwood>

See patch.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at coreboot.org  Fri Apr  4 00:20:36 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 00:20:36 +0200
Subject: [coreboot] r3211 - in trunk/payloads/coreinfo: . util/kconfig
Message-ID: <mailman.1360.1355071294.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-04 00:20:35 +0200 (Fri, 04 Apr 2008)
New Revision: 3211

Modified:
   trunk/payloads/coreinfo/Makefile
   trunk/payloads/coreinfo/util/kconfig/conf.c
   trunk/payloads/coreinfo/util/kconfig/confdata.c
Log:
Doing another 'make' after a 'make clean' was broken until now. Fix it
by not deleting build/config.h during 'make clean' (only in 'make distclean').

Also, change the default behaviour of 'make' from asking the user to
run 'make config' (or similar) to actually _run_ 'make config' without
asking questions. It's always possible to explicitly invoke
'make menuconfig' or 'make xconfig' and so on, of course.

Finally, make _all_ targets (allyesconfig, randconfig, and so on)
generate a build/config.h file, as we always #include it.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Modified: trunk/payloads/coreinfo/Makefile
===================================================================
--- trunk/payloads/coreinfo/Makefile	2008-04-02 12:35:45 UTC (rev 3210)
+++ trunk/payloads/coreinfo/Makefile	2008-04-03 22:20:35 UTC (rev 3211)
@@ -59,8 +59,7 @@
 
 ifeq ($(strip $(HAVE_DOTCONFIG)),)
 
-all:
-	$(Q)printf "Please run make config/menuconfig/xconfig/gconfig first.\n"
+all: config
 
 else
 
@@ -91,9 +90,10 @@
 	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
 
 clean:
-	$(Q)rm -rf build
+	$(Q)rm -rf build/util build/*.conf build/*.cmd build/*.elf build/*.o
 
 distclean: clean
+	$(Q)rm -rf build
 	$(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
 
 include util/kconfig/Makefile

Modified: trunk/payloads/coreinfo/util/kconfig/conf.c
===================================================================
--- trunk/payloads/coreinfo/util/kconfig/conf.c	2008-04-02 12:35:45 UTC (rev 3210)
+++ trunk/payloads/coreinfo/util/kconfig/conf.c	2008-04-03 22:20:35 UTC (rev 3211)
@@ -624,6 +624,10 @@
 		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
 		return 1;
 	}
+	if (conf_write_autoconf()) {
+		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
+		return 1;
+	}
 skip_check:
 	if (input_mode == ask_silent && conf_write_autoconf()) {
 		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));

Modified: trunk/payloads/coreinfo/util/kconfig/confdata.c
===================================================================
--- trunk/payloads/coreinfo/util/kconfig/confdata.c	2008-04-02 12:35:45 UTC (rev 3210)
+++ trunk/payloads/coreinfo/util/kconfig/confdata.c	2008-04-03 22:20:35 UTC (rev 3211)
@@ -679,8 +679,10 @@
 
 	file_write_dep("build/auto.conf.cmd");
 
+#if 0
 	if (conf_split_config())
 		return 1;
+#endif
 
 	out = fopen(".tmpconfig", "w");
 	if (!out)




From uwe at hermann-uwe.de  Fri Apr  4 00:22:38 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Apr 2008 00:22:38 +0200
Subject: [coreboot] coreinfo: Build system fixes
In-Reply-To: <20080403213049.GG21011@cosmic.amd.com>
References: <20080403212220.GA26504@greenwood>
	<20080403213049.GG21011@cosmic.amd.com>
Message-ID: <20080403222238.GA30751@greenwood>

On Thu, Apr 03, 2008 at 03:30:49PM -0600, Jordan Crouse wrote:
> > Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Thanks, r3211.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From peter at stuge.se  Fri Apr  4 00:24:11 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 00:24:11 +0200
Subject: [coreboot] [PATCH] libpayload: SHA-1 implementation
In-Reply-To: <20080403221837.GB26504@greenwood>
References: <20080403221837.GB26504@greenwood>
Message-ID: <20080403222411.13763.qmail@stuge.se>

On Fri, Apr 04, 2008 at 12:18:37AM +0200, Uwe Hermann wrote:
> Add a SHA-1 implementation to libpayload.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Acked-by: Peter Stuge <peter at stuge.se>


> Index: include/libpayload.h
> ===================================================================
> --- include/libpayload.h	(Revision 3210)
> +++ include/libpayload.h	(Arbeitskopie)
> @@ -41,6 +41,14 @@
>  #define MAX(a,b) ((a) > (b) ? (a) : (b))
>  #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
>  
> +#define LITTLE_ENDIAN	1234
> +#define BIG_ENDIAN	4321
> +#ifdef CONFIG_TARGET_I386
> +#define BYTE_ORDER	LITTLE_ENDIAN
> +#else
> +#define BYTE_ORDER	BIG_ENDIAN
> +#endif
> +
>  /* Some NVRAM byte definitions */
>  #define NVRAM_RTC_SECONDS        0
>  #define NVRAM_RTC_MINUTES        2
> @@ -117,6 +125,20 @@
>  int printf(const char *fmt, ...);
>  int vprintf(const char *fmt, va_list ap);
>  
> +/* libc/sha1.c */
> +#define SHA1_BLOCK_LENGTH	64
> +#define SHA1_DIGEST_LENGTH	20
> +typedef struct {
> +        u32 state[5];
> +        u64 count;
> +        u8 buffer[SHA1_BLOCK_LENGTH];
> +} SHA1_CTX;
> +void SHA1Init(SHA1_CTX *context);
> +void SHA1Transform(u32 state[5], const u8 buffer[SHA1_BLOCK_LENGTH]);
> +void SHA1Update(SHA1_CTX *context, const u8 *data, size_t len);
> +void SHA1Final(u8 digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context);
> +u8 *sha1(const u8 *data, size_t len, u8 *buf);
> +
>  /* libc/string.c */
>  size_t strnlen(const char *str, size_t maxlen);
>  size_t strlen(const char *str);
> Index: LICENSES
> ===================================================================
> --- LICENSES	(Revision 3210)
> +++ LICENSES	(Arbeitskopie)
> @@ -86,3 +86,9 @@
>                    kernel/generic/src/printf/vprintf.c
>    Current version we use: r2745
>  
> +* libc/sha1.c: Public domain
> +  Source: OpenBSD
> +          http://www.openbsd.org/cgi-bin/cvsweb/src/lib/libc/hash/sha1.c
> +  Original files: src/lib/libc/hash/sha1.c
> +  Current version we use: CVS revision 1.20 2005/08/08
> +  
> Index: libc/Makefile.inc
> ===================================================================
> --- libc/Makefile.inc	(Revision 3210)
> +++ libc/Makefile.inc	(Arbeitskopie)
> @@ -29,3 +29,4 @@
>  
>  TARGETS-y += libc/malloc.o libc/printf.o libc/console.o libc/string.o
>  TARGETS-y += libc/memory.o libc/ctype.o libc/ipchecksum.o libc/lib.o
> +TARGETS-y += libc/sha1.o
> Index: libc/sha1.c
> ===================================================================
> --- libc/sha1.c	(Revision 0)
> +++ libc/sha1.c	(Revision 0)
> @@ -0,0 +1,211 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * It has originally been taken from the OpenBSD project.
> + */
> +
> +/*	$OpenBSD: sha1.c,v 1.20 2005/08/08 08:05:35 espie Exp $	*/
> +
> +/*
> + * SHA-1 in C
> + * By Steve Reid <steve at edmweb.com>
> + * 100% Public Domain
> + *
> + * Test Vectors (from FIPS PUB 180-1)
> + * "abc"
> + *   A9993E36 4706816A BA3E2571 7850C26C 9CD0D89D
> + * "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
> + *   84983E44 1C3BD26E BAAE4AA1 F95129E5 E54670F1
> + * A million repetitions of "a"
> + *   34AA973C D4C4DAA4 F61EEB2B DBAD2731 6534016F
> + */
> +
> +#include <libpayload.h>
> +
> +typedef u8 u_int8_t;
> +typedef u32 u_int32_t;
> +typedef u64 u_int64_t;
> +typedef unsigned int u_int;
> +
> +#if 0
> +#include <sys/param.h>
> +#include <string.h>
> +#include <sha1.h>
> +#endif
> +
> +#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))
> +
> +/*
> + * blk0() and blk() perform the initial expand.
> + * I got the idea of expanding during the round function from SSLeay
> + */
> +#if BYTE_ORDER == LITTLE_ENDIAN
> +# define blk0(i) (block->l[i] = (rol(block->l[i],24)&0xFF00FF00) \
> +    |(rol(block->l[i],8)&0x00FF00FF))
> +#else
> +# define blk0(i) block->l[i]
> +#endif
> +#define blk(i) (block->l[i&15] = rol(block->l[(i+13)&15]^block->l[(i+8)&15] \
> +    ^block->l[(i+2)&15]^block->l[i&15],1))
> +
> +/*
> + * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
> + */
> +#define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);
> +#define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30);
> +#define R2(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0x6ED9EBA1+rol(v,5);w=rol(w,30);
> +#define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30);
> +#define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30);
> +
> +/*
> + * Hash a single 512-bit block. This is the core of the algorithm.
> + */
> +void
> +SHA1Transform(u_int32_t state[5], const u_int8_t buffer[SHA1_BLOCK_LENGTH])
> +{
> +	u_int32_t a, b, c, d, e;
> +	u_int8_t workspace[SHA1_BLOCK_LENGTH];
> +	typedef union {
> +		u_int8_t c[64];
> +		u_int32_t l[16];
> +	} CHAR64LONG16;
> +	CHAR64LONG16 *block = (CHAR64LONG16 *)workspace;
> +
> +	(void)memcpy(block, buffer, SHA1_BLOCK_LENGTH);
> +
> +	/* Copy context->state[] to working vars */
> +	a = state[0];
> +	b = state[1];
> +	c = state[2];
> +	d = state[3];
> +	e = state[4];
> +
> +	/* 4 rounds of 20 operations each. Loop unrolled. */
> +	R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
> +	R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);
> +	R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);
> +	R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);
> +	R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);
> +	R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);
> +	R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);
> +	R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);
> +	R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);
> +	R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);
> +	R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);
> +	R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);
> +	R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);
> +	R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);
> +	R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);
> +	R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);
> +	R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);
> +	R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);
> +	R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);
> +	R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);
> +
> +	/* Add the working vars back into context.state[] */
> +	state[0] += a;
> +	state[1] += b;
> +	state[2] += c;
> +	state[3] += d;
> +	state[4] += e;
> +
> +	/* Wipe variables */
> +	a = b = c = d = e = 0;
> +}
> +
> +
> +/*
> + * SHA1Init - Initialize new context
> + */
> +void
> +SHA1Init(SHA1_CTX *context)
> +{
> +
> +	/* SHA1 initialization constants */
> +	context->count = 0;
> +	context->state[0] = 0x67452301;
> +	context->state[1] = 0xEFCDAB89;
> +	context->state[2] = 0x98BADCFE;
> +	context->state[3] = 0x10325476;
> +	context->state[4] = 0xC3D2E1F0;
> +}
> +
> +
> +/*
> + * Run your data through this.
> + */
> +void
> +SHA1Update(SHA1_CTX *context, const u_int8_t *data, size_t len)
> +{
> +	size_t i, j;
> +
> +	j = (size_t)((context->count >> 3) & 63);
> +	context->count += (len << 3);
> +	if ((j + len) > 63) {
> +		(void)memcpy(&context->buffer[j], data, (i = 64-j));
> +		SHA1Transform(context->state, context->buffer);
> +		for ( ; i + 63 < len; i += 64)
> +			SHA1Transform(context->state, (u_int8_t *)&data[i]);
> +		j = 0;
> +	} else {
> +		i = 0;
> +	}
> +	(void)memcpy(&context->buffer[j], &data[i], len - i);
> +}
> +
> +
> +/*
> + * Add padding and return the message digest.
> + */
> +void
> +SHA1Pad(SHA1_CTX *context)
> +{
> +	u_int8_t finalcount[8];
> +	u_int i;
> +
> +	for (i = 0; i < 8; i++) {
> +		finalcount[i] = (u_int8_t)((context->count >>
> +		    ((7 - (i & 7)) * 8)) & 255);	/* Endian independent */
> +	}
> +	SHA1Update(context, (u_int8_t *)"\200", 1);
> +	while ((context->count & 504) != 448)
> +		SHA1Update(context, (u_int8_t *)"\0", 1);
> +	SHA1Update(context, finalcount, 8); /* Should cause a SHA1Transform() */
> +}
> +
> +void
> +SHA1Final(u_int8_t digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context)
> +{
> +	u_int i;
> +
> +	SHA1Pad(context);
> +	if (digest) {
> +		for (i = 0; i < SHA1_DIGEST_LENGTH; i++) {
> +			digest[i] = (u_int8_t)
> +			   ((context->state[i>>2] >> ((3-(i & 3)) * 8) ) & 255);
> +		}
> +		memset(context, 0, sizeof(*context));
> +	}
> +}
> +
> +/**
> + * Compute the SHA-1 hash of the given data as specified by the 'data' and
> + * 'len' arguments, and place the result -- 160 bits (20 bytes) -- into the
> + * specified output buffer 'buf'.
> + *
> + * @param data Pointer to the input data that shall be hashed.
> + * @param len Length of the input data (in bytes).
> + * @param buf Buffer which will hold the resulting hash (must be at
> + * 	      least 20 bytes in size).
> + * @return Pointer to the output buffer where the hash is stored.
> + */
> +u8 *sha1(const u8 *data, size_t len, u8 *buf)
> +{
> +	SHA1_CTX ctx;
> +
> +	SHA1Init(&ctx);
> +	SHA1Update(&ctx, data, len);
> +	SHA1Final(buf, &ctx);
> +
> +	return buf;
> +}



From svn at coreboot.org  Fri Apr  4 01:01:23 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 01:01:23 +0200
Subject: [coreboot] r3212 - in trunk/payloads/libpayload: . crypto include
Message-ID: <mailman.1361.1355071294.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-04 01:01:23 +0200 (Fri, 04 Apr 2008)
New Revision: 3212

Added:
   trunk/payloads/libpayload/crypto/
   trunk/payloads/libpayload/crypto/Makefile.inc
   trunk/payloads/libpayload/crypto/sha1.c
Modified:
   trunk/payloads/libpayload/LICENSES
   trunk/payloads/libpayload/Makefile
   trunk/payloads/libpayload/include/libpayload.h
Log:
Add a SHA-1 implementation to libpayload.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: trunk/payloads/libpayload/LICENSES
===================================================================
--- trunk/payloads/libpayload/LICENSES	2008-04-03 22:20:35 UTC (rev 3211)
+++ trunk/payloads/libpayload/LICENSES	2008-04-03 23:01:23 UTC (rev 3212)
@@ -86,3 +86,9 @@
                   kernel/generic/src/printf/vprintf.c
   Current version we use: r2745
 
+* crypto/sha1.c: Public domain
+  Source: OpenBSD
+          http://www.openbsd.org/cgi-bin/cvsweb/src/lib/libc/hash/sha1.c
+  Original files: src/lib/libc/hash/sha1.c
+  Current version we use: CVS revision 1.20 2005/08/08
+  

Modified: trunk/payloads/libpayload/Makefile
===================================================================
--- trunk/payloads/libpayload/Makefile	2008-04-03 22:20:35 UTC (rev 3211)
+++ trunk/payloads/libpayload/Makefile	2008-04-03 23:01:23 UTC (rev 3212)
@@ -54,7 +54,7 @@
 PLATFORM-$(CONFIG_TARGET_I386) += i386/Makefile.inc
 TARGETS-y :=
 
-BUILD-y := libc/Makefile.inc drivers/Makefile.inc
+BUILD-y := crypto/Makefile.inc libc/Makefile.inc drivers/Makefile.inc
 BUILD-$(CONFIG_TINYCURSES) += curses/Makefile.inc
 
 include $(PLATFORM-y) $(BUILD-y)

Added: trunk/payloads/libpayload/crypto/Makefile.inc
===================================================================
--- trunk/payloads/libpayload/crypto/Makefile.inc	                        (rev 0)
+++ trunk/payloads/libpayload/crypto/Makefile.inc	2008-04-03 23:01:23 UTC (rev 3212)
@@ -0,0 +1,30 @@
+##
+## This file is part of the libpayload project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+##    notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+##    notice, this list of conditions and the following disclaimer in the
+##    documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+##    derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+TARGETS-y += crypto/sha1.o

Added: trunk/payloads/libpayload/crypto/sha1.c
===================================================================
--- trunk/payloads/libpayload/crypto/sha1.c	                        (rev 0)
+++ trunk/payloads/libpayload/crypto/sha1.c	2008-04-03 23:01:23 UTC (rev 3212)
@@ -0,0 +1,211 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * It has originally been taken from the OpenBSD project.
+ */
+
+/*	$OpenBSD: sha1.c,v 1.20 2005/08/08 08:05:35 espie Exp $	*/
+
+/*
+ * SHA-1 in C
+ * By Steve Reid <steve at edmweb.com>
+ * 100% Public Domain
+ *
+ * Test Vectors (from FIPS PUB 180-1)
+ * "abc"
+ *   A9993E36 4706816A BA3E2571 7850C26C 9CD0D89D
+ * "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
+ *   84983E44 1C3BD26E BAAE4AA1 F95129E5 E54670F1
+ * A million repetitions of "a"
+ *   34AA973C D4C4DAA4 F61EEB2B DBAD2731 6534016F
+ */
+
+#include <libpayload.h>
+
+typedef u8 u_int8_t;
+typedef u32 u_int32_t;
+typedef u64 u_int64_t;
+typedef unsigned int u_int;
+
+#if 0
+#include <sys/param.h>
+#include <string.h>
+#include <sha1.h>
+#endif
+
+#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))
+
+/*
+ * blk0() and blk() perform the initial expand.
+ * I got the idea of expanding during the round function from SSLeay
+ */
+#if BYTE_ORDER == LITTLE_ENDIAN
+# define blk0(i) (block->l[i] = (rol(block->l[i],24)&0xFF00FF00) \
+    |(rol(block->l[i],8)&0x00FF00FF))
+#else
+# define blk0(i) block->l[i]
+#endif
+#define blk(i) (block->l[i&15] = rol(block->l[(i+13)&15]^block->l[(i+8)&15] \
+    ^block->l[(i+2)&15]^block->l[i&15],1))
+
+/*
+ * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1
+ */
+#define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);
+#define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30);
+#define R2(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0x6ED9EBA1+rol(v,5);w=rol(w,30);
+#define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30);
+#define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30);
+
+/*
+ * Hash a single 512-bit block. This is the core of the algorithm.
+ */
+void
+SHA1Transform(u_int32_t state[5], const u_int8_t buffer[SHA1_BLOCK_LENGTH])
+{
+	u_int32_t a, b, c, d, e;
+	u_int8_t workspace[SHA1_BLOCK_LENGTH];
+	typedef union {
+		u_int8_t c[64];
+		u_int32_t l[16];
+	} CHAR64LONG16;
+	CHAR64LONG16 *block = (CHAR64LONG16 *)workspace;
+
+	(void)memcpy(block, buffer, SHA1_BLOCK_LENGTH);
+
+	/* Copy context->state[] to working vars */
+	a = state[0];
+	b = state[1];
+	c = state[2];
+	d = state[3];
+	e = state[4];
+
+	/* 4 rounds of 20 operations each. Loop unrolled. */
+	R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
+	R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);
+	R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);
+	R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);
+	R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);
+	R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);
+	R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);
+	R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);
+	R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);
+	R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);
+	R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);
+	R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);
+	R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);
+	R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);
+	R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);
+	R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);
+	R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);
+	R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);
+	R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);
+	R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);
+
+	/* Add the working vars back into context.state[] */
+	state[0] += a;
+	state[1] += b;
+	state[2] += c;
+	state[3] += d;
+	state[4] += e;
+
+	/* Wipe variables */
+	a = b = c = d = e = 0;
+}
+
+
+/*
+ * SHA1Init - Initialize new context
+ */
+void
+SHA1Init(SHA1_CTX *context)
+{
+
+	/* SHA1 initialization constants */
+	context->count = 0;
+	context->state[0] = 0x67452301;
+	context->state[1] = 0xEFCDAB89;
+	context->state[2] = 0x98BADCFE;
+	context->state[3] = 0x10325476;
+	context->state[4] = 0xC3D2E1F0;
+}
+
+
+/*
+ * Run your data through this.
+ */
+void
+SHA1Update(SHA1_CTX *context, const u_int8_t *data, size_t len)
+{
+	size_t i, j;
+
+	j = (size_t)((context->count >> 3) & 63);
+	context->count += (len << 3);
+	if ((j + len) > 63) {
+		(void)memcpy(&context->buffer[j], data, (i = 64-j));
+		SHA1Transform(context->state, context->buffer);
+		for ( ; i + 63 < len; i += 64)
+			SHA1Transform(context->state, (u_int8_t *)&data[i]);
+		j = 0;
+	} else {
+		i = 0;
+	}
+	(void)memcpy(&context->buffer[j], &data[i], len - i);
+}
+
+
+/*
+ * Add padding and return the message digest.
+ */
+void
+SHA1Pad(SHA1_CTX *context)
+{
+	u_int8_t finalcount[8];
+	u_int i;
+
+	for (i = 0; i < 8; i++) {
+		finalcount[i] = (u_int8_t)((context->count >>
+		    ((7 - (i & 7)) * 8)) & 255);	/* Endian independent */
+	}
+	SHA1Update(context, (u_int8_t *)"\200", 1);
+	while ((context->count & 504) != 448)
+		SHA1Update(context, (u_int8_t *)"\0", 1);
+	SHA1Update(context, finalcount, 8); /* Should cause a SHA1Transform() */
+}
+
+void
+SHA1Final(u_int8_t digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context)
+{
+	u_int i;
+
+	SHA1Pad(context);
+	if (digest) {
+		for (i = 0; i < SHA1_DIGEST_LENGTH; i++) {
+			digest[i] = (u_int8_t)
+			   ((context->state[i>>2] >> ((3-(i & 3)) * 8) ) & 255);
+		}
+		memset(context, 0, sizeof(*context));
+	}
+}
+
+/**
+ * Compute the SHA-1 hash of the given data as specified by the 'data' and
+ * 'len' arguments, and place the result -- 160 bits (20 bytes) -- into the
+ * specified output buffer 'buf'.
+ *
+ * @param data Pointer to the input data that shall be hashed.
+ * @param len Length of the input data (in bytes).
+ * @param buf Buffer which will hold the resulting hash (must be at
+ * 	      least 20 bytes in size).
+ * @return Pointer to the output buffer where the hash is stored.
+ */
+u8 *sha1(const u8 *data, size_t len, u8 *buf)
+{
+	SHA1_CTX ctx;
+
+	SHA1Init(&ctx);
+	SHA1Update(&ctx, data, len);
+	SHA1Final(buf, &ctx);
+
+	return buf;
+}

Modified: trunk/payloads/libpayload/include/libpayload.h
===================================================================
--- trunk/payloads/libpayload/include/libpayload.h	2008-04-03 22:20:35 UTC (rev 3211)
+++ trunk/payloads/libpayload/include/libpayload.h	2008-04-03 23:01:23 UTC (rev 3212)
@@ -41,6 +41,14 @@
 #define MAX(a,b) ((a) > (b) ? (a) : (b))
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
+#define LITTLE_ENDIAN	1234
+#define BIG_ENDIAN	4321
+#ifdef CONFIG_TARGET_I386
+#define BYTE_ORDER	LITTLE_ENDIAN
+#else
+#define BYTE_ORDER	BIG_ENDIAN
+#endif
+
 /* Some NVRAM byte definitions */
 #define NVRAM_RTC_SECONDS        0
 #define NVRAM_RTC_MINUTES        2
@@ -117,6 +125,20 @@
 int printf(const char *fmt, ...);
 int vprintf(const char *fmt, va_list ap);
 
+/* libc/sha1.c */
+#define SHA1_BLOCK_LENGTH	64
+#define SHA1_DIGEST_LENGTH	20
+typedef struct {
+	u32 state[5];
+	u64 count;
+	u8 buffer[SHA1_BLOCK_LENGTH];
+} SHA1_CTX;
+void SHA1Init(SHA1_CTX *context);
+void SHA1Transform(u32 state[5], const u8 buffer[SHA1_BLOCK_LENGTH]);
+void SHA1Update(SHA1_CTX *context, const u8 *data, size_t len);
+void SHA1Final(u8 digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context);
+u8 *sha1(const u8 *data, size_t len, u8 *buf);
+
 /* libc/string.c */
 size_t strnlen(const char *str, size_t maxlen);
 size_t strlen(const char *str);




From uwe at hermann-uwe.de  Fri Apr  4 01:03:15 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Apr 2008 01:03:15 +0200
Subject: [coreboot] [PATCH] libpayload: SHA-1 implementation
In-Reply-To: <20080403222411.13763.qmail@stuge.se>
References: <20080403221837.GB26504@greenwood>
	<20080403222411.13763.qmail@stuge.se>
Message-ID: <20080403230315.GA32587@greenwood>

On Fri, Apr 04, 2008 at 12:24:11AM +0200, Peter Stuge wrote:
> On Fri, Apr 04, 2008 at 12:18:37AM +0200, Uwe Hermann wrote:
> > Add a SHA-1 implementation to libpayload.
> > 
> > Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> Acked-by: Peter Stuge <peter at stuge.se>

Thanks, r3212. I've taken the freedom to move sha1.c to a crypto/
directory though, as discussed with Jordan on IRC (we'll have more
cryto-related functions later), I hope you don't mind.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From peter at stuge.se  Fri Apr  4 01:21:54 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 01:21:54 +0200
Subject: [coreboot] [PATCH] libpayload: SHA-1 implementation
In-Reply-To: <20080403230315.GA32587@greenwood>
References: <20080403221837.GB26504@greenwood>
	<20080403222411.13763.qmail@stuge.se>
	<20080403230315.GA32587@greenwood>
Message-ID: <20080403232154.31809.qmail@stuge.se>

On Fri, Apr 04, 2008 at 01:03:15AM +0200, Uwe Hermann wrote:
> crypto/
> I hope you don't mind.

That's fine!


//Peter



From stepan at coresystems.de  Fri Apr  4 04:40:47 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 03 Apr 2008 20:40:47 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
Message-ID: <47F5952F.1060803@coresystems.de>

The idea to this patch is from Patrick Georgi but I reimplemented it 
from scratch since I can't reach the other box for a few days. It fixes 
stage0_i586.S assembling on the latest official GNU binutils version. 
Without this patch the compilation fails with:

  AS      build/arch/x86/stage0_i586.o
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler messages:
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
expecting operand after ','; got nothing
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error: 
expecting operand after ','; got nothing


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Fri Apr  4 04:52:22 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 03 Apr 2008 20:52:22 -0600
Subject: [coreboot] [PATCH] fix lar compilation for non-Linux platforms
Message-ID: <47F597E6.5030107@coresystems.de>

This patch allows compilation on non-glibc platforms again.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From rminnich at gmail.com  Fri Apr  4 05:03:44 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 3 Apr 2008 20:03:44 -0700
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <20080403120935.GA21945@greenwood>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
	<47F4B0C3.40901@gmx.net> <20080403120935.GA21945@greenwood>
Message-ID: <13426df10804032003i525026c5r8f8efe282daa2630@mail.gmail.com>

latest version, takes into account all comments to date, works.

ron



From stepan at coresystems.de  Fri Apr  4 05:08:55 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 03 Apr 2008 21:08:55 -0600
Subject: [coreboot] [PATCH] Add subversion number
Message-ID: <47F59BC7.2090908@coresystems.de>

    This patch uses the svn version as the sublevel part of the coreboot
    version string.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From rminnich at gmail.com  Fri Apr  4 05:11:05 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 3 Apr 2008 20:11:05 -0700
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <13426df10804032003i525026c5r8f8efe282daa2630@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
	<47F4B0C3.40901@gmx.net> <20080403120935.GA21945@greenwood>
	<13426df10804032003i525026c5r8f8efe282daa2630@mail.gmail.com>
Message-ID: <13426df10804032011g6c337c4ak8ba1f6388ab3896@mail.gmail.com>

firefox crashed. Message went out, patch did not :-)

ron

On Thu, Apr 3, 2008 at 8:03 PM, ron minnich <rminnich at gmail.com> wrote:
> latest version, takes into account all comments to date, works.
>
>  ron
>
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From stepan at coresystems.de  Fri Apr  4 05:20:11 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 03 Apr 2008 21:20:11 -0600
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <13426df10804032011g6c337c4ak8ba1f6388ab3896@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>	<47F4B0C3.40901@gmx.net>
	<20080403120935.GA21945@greenwood>	<13426df10804032003i525026c5r8f8efe282daa2630@mail.gmail.com>
	<13426df10804032011g6c337c4ak8ba1f6388ab3896@mail.gmail.com>
Message-ID: <47F59E6B.9070408@coresystems.de>

ron minnich wrote:
> firefox crashed. Message went out, patch did not :-)
>
> ron
>
> On Thu, Apr 3, 2008 at 8:03 PM, ron minnich <rminnich at gmail.com> wrote:
>   
>> latest version, takes into account all comments to date, works.
>>
>>  ron
>>
>>     
> With this set of changes dbe62 gets to a FILO prompt.
>
> Set manual settings for dbe62 PLL; the auto settings are giving
> slightly wrong values
>
> Add call to dumplxmsr in dbe62 initram main()
>
> Change dumplxmsr to void parameter
>
> Add dumplxmsrs function to geodelx raminit support code
>
> Correct spelling of CAS.
>
> The big one: set spd variables correctly.
>
> The not so big one: there is a bug in com2 enable I don't understand.
> For now comment out two offending lines. The cs5536 debug prints
> should be reduced later.
>
> Change fuctory to factory. It's funny but confusing. 
>
> This patch also takes into account carl-daniel and uwe's comments.
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
> Index: southbridge/amd/cs5536/cs5536.c
> =================================================
Acked-by: Stefan Reinauer <stepan at coresystems.de>




-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From ward at gnu.org  Fri Apr  4 05:24:46 2008
From: ward at gnu.org (Ward Vandewege)
Date: Thu, 3 Apr 2008 21:24:46 -0600
Subject: [coreboot] [PATCH] Add subversion number
In-Reply-To: <47F59BC7.2090908@coresystems.de>
References: <47F59BC7.2090908@coresystems.de>
Message-ID: <20080404032446.GA16511@localdomain>

On Thu, Apr 03, 2008 at 09:08:55PM -0600, Stefan Reinauer wrote:
>    This patch uses the svn version as the sublevel part of the coreboot
>    version string.
>
>
> -- 
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
>

> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Great!

Acked-by: Ward Vandewege <ward at gnu.org>

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From svn at coreboot.org  Fri Apr  4 05:29:26 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 05:29:26 +0200
Subject: [coreboot] r648 - in coreboot-v3: . arch/x86 device include/device
	util/lar
Message-ID: <mailman.1362.1355071294.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-04-04 05:29:26 +0200 (Fri, 04 Apr 2008)
New Revision: 648

Added:
   coreboot-v3/util/lar/elf.h
Modified:
   coreboot-v3/Makefile
   coreboot-v3/arch/x86/stage0_i586.S
   coreboot-v3/device/device.c
   coreboot-v3/include/device/device.h
   coreboot-v3/util/lar/stream.c
Log:
This patch uses the svn version as the sublevel part of the coreboot
version string.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: coreboot-v3/Makefile
===================================================================
--- coreboot-v3/Makefile	2008-03-27 23:56:36 UTC (rev 647)
+++ coreboot-v3/Makefile	2008-04-04 03:29:26 UTC (rev 648)
@@ -23,7 +23,9 @@
 
 VERSION = 3
 PATCHLEVEL = 0
-SUBLEVEL = 0
+# Set the sublevel version string from the highest revision number
+# of the checked out files.
+SUBLEVEL := "$(shell svnversion -cn . \ | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/")"'
 
 have_dotconfig := $(wildcard .config)
 

Modified: coreboot-v3/arch/x86/stage0_i586.S
===================================================================
--- coreboot-v3/arch/x86/stage0_i586.S	2008-03-27 23:56:36 UTC (rev 647)
+++ coreboot-v3/arch/x86/stage0_i586.S	2008-04-04 03:29:26 UTC (rev 648)
@@ -297,20 +297,20 @@
  *   register we want to use for CAR.
  * reg is the register where the IO type should be stored.
  */
-.macro extractmask segs, reg
-.if \segs <= 0
+.macro extractmask size_segs, reg
+.if \size_segs <= 0
 	/* The xorl here is superfluous because at the point of first execution
 	 * of this macro, %eax and %edx are cleared. Later invocations of this
-	 * macro will have a monotonically increasing segs parameter.
+	 * macro will have a monotonically increasing size_segs parameter.
 	 */
 	xorl \reg, \reg
-.elseif \segs == 1
+.elseif \size_segs == 0x1000
 	movl $0x06000000, \reg
-.elseif \segs == 2
+.elseif \size_segs == 0x2000
 	movl $0x06060000, \reg
-.elseif \segs == 3
+.elseif \size_segs == 0x3000
 	movl $0x06060600, \reg
-.elseif \segs >= 4
+.elseif \size_segs >= 0x4000
 	movl $0x06060606, \reg
 .endif
 .endm
@@ -319,8 +319,8 @@
  * windowoffset is the 32k-aligned window into CAR size
  */
 .macro simplemask carsize, windowoffset
-	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
-	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+	extractmask ((( \carsize - \windowoffset ) ) - 0x4000 ), %eax
+	extractmask ((( \carsize - \windowoffset ) ) ), %edx
 .endm
 
 #if CacheSize > 0x10000

Modified: coreboot-v3/device/device.c
===================================================================
--- coreboot-v3/device/device.c	2008-03-27 23:56:36 UTC (rev 647)
+++ coreboot-v3/device/device.c	2008-04-04 03:29:26 UTC (rev 648)
@@ -130,6 +130,7 @@
 			printk(BIOS_SPEW, "%s: match\n", __func__);
 			return c;
 		}
+		printk(BIOS_SPEW, "no more constructors\n");
 	}
 
 	return NULL;

Modified: coreboot-v3/include/device/device.h
===================================================================
--- coreboot-v3/include/device/device.h	2008-03-27 23:56:36 UTC (rev 647)
+++ coreboot-v3/include/device/device.h	2008-04-04 03:29:26 UTC (rev 648)
@@ -231,7 +231,7 @@
 	/* number of buses attached to the device */
 	unsigned int links;
 
-	struct device_operations *ops;
+	const struct device_operations *ops;
 	void *device_configuration;
 };
 

Added: coreboot-v3/util/lar/elf.h
===================================================================
--- coreboot-v3/util/lar/elf.h	                        (rev 0)
+++ coreboot-v3/util/lar/elf.h	2008-04-04 03:29:26 UTC (rev 648)
@@ -0,0 +1,2637 @@
+/* This file defines standard ELF types, structures, and macros.
+   Copyright (C) 1995-2003,2004,2005,2006,2007 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, write to the Free
+   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307 USA.  */
+
+#ifndef _ELF_H
+#define	_ELF_H 1
+
+#include <stdint.h>
+
+/* Type for a 16-bit quantity.  */
+typedef uint16_t Elf32_Half;
+typedef uint16_t Elf64_Half;
+
+/* Types for signed and unsigned 32-bit quantities.  */
+typedef uint32_t Elf32_Word;
+typedef	int32_t  Elf32_Sword;
+typedef uint32_t Elf64_Word;
+typedef	int32_t  Elf64_Sword;
+
+/* Types for signed and unsigned 64-bit quantities.  */
+typedef uint64_t Elf32_Xword;
+typedef	int64_t  Elf32_Sxword;
+typedef uint64_t Elf64_Xword;
+typedef	int64_t  Elf64_Sxword;
+
+/* Type of addresses.  */
+typedef uint32_t Elf32_Addr;
+typedef uint64_t Elf64_Addr;
+
+/* Type of file offsets.  */
+typedef uint32_t Elf32_Off;
+typedef uint64_t Elf64_Off;
+
+/* Type for section indices, which are 16-bit quantities.  */
+typedef uint16_t Elf32_Section;
+typedef uint16_t Elf64_Section;
+
+/* Type for version symbol information.  */
+typedef Elf32_Half Elf32_Versym;
+typedef Elf64_Half Elf64_Versym;
+
+
+/* The ELF file header.  This appears at the start of every ELF file.  */
+
+#define EI_NIDENT (16)
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf32_Half	e_type;			/* Object file type */
+  Elf32_Half	e_machine;		/* Architecture */
+  Elf32_Word	e_version;		/* Object file version */
+  Elf32_Addr	e_entry;		/* Entry point virtual address */
+  Elf32_Off	e_phoff;		/* Program header table file offset */
+  Elf32_Off	e_shoff;		/* Section header table file offset */
+  Elf32_Word	e_flags;		/* Processor-specific flags */
+  Elf32_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf32_Half	e_phentsize;		/* Program header table entry size */
+  Elf32_Half	e_phnum;		/* Program header table entry count */
+  Elf32_Half	e_shentsize;		/* Section header table entry size */
+  Elf32_Half	e_shnum;		/* Section header table entry count */
+  Elf32_Half	e_shstrndx;		/* Section header string table index */
+} Elf32_Ehdr;
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf64_Half	e_type;			/* Object file type */
+  Elf64_Half	e_machine;		/* Architecture */
+  Elf64_Word	e_version;		/* Object file version */
+  Elf64_Addr	e_entry;		/* Entry point virtual address */
+  Elf64_Off	e_phoff;		/* Program header table file offset */
+  Elf64_Off	e_shoff;		/* Section header table file offset */
+  Elf64_Word	e_flags;		/* Processor-specific flags */
+  Elf64_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf64_Half	e_phentsize;		/* Program header table entry size */
+  Elf64_Half	e_phnum;		/* Program header table entry count */
+  Elf64_Half	e_shentsize;		/* Section header table entry size */
+  Elf64_Half	e_shnum;		/* Section header table entry count */
+  Elf64_Half	e_shstrndx;		/* Section header string table index */
+} Elf64_Ehdr;
+
+/* Fields in the e_ident array.  The EI_* macros are indices into the
+   array.  The macros under each EI_* macro are the values the byte
+   may have.  */
+
+#define EI_MAG0		0		/* File identification byte 0 index */
+#define ELFMAG0		0x7f		/* Magic number byte 0 */
+
+#define EI_MAG1		1		/* File identification byte 1 index */
+#define ELFMAG1		'E'		/* Magic number byte 1 */
+
+#define EI_MAG2		2		/* File identification byte 2 index */
+#define ELFMAG2		'L'		/* Magic number byte 2 */
+
+#define EI_MAG3		3		/* File identification byte 3 index */
+#define ELFMAG3		'F'		/* Magic number byte 3 */
+
+/* Conglomeration of the identification bytes, for easy testing as a word.  */
+#define	ELFMAG		"\177ELF"
+#define	SELFMAG		4
+
+#define EI_CLASS	4		/* File class byte index */
+#define ELFCLASSNONE	0		/* Invalid class */
+#define ELFCLASS32	1		/* 32-bit objects */
+#define ELFCLASS64	2		/* 64-bit objects */
+#define ELFCLASSNUM	3
+
+#define EI_DATA		5		/* Data encoding byte index */
+#define ELFDATANONE	0		/* Invalid data encoding */
+#define ELFDATA2LSB	1		/* 2's complement, little endian */
+#define ELFDATA2MSB	2		/* 2's complement, big endian */
+#define ELFDATANUM	3
+
+#define EI_VERSION	6		/* File version byte index */
+					/* Value must be EV_CURRENT */
+
+#define EI_OSABI	7		/* OS ABI identification */
+#define ELFOSABI_NONE		0	/* UNIX System V ABI */
+#define ELFOSABI_SYSV		0	/* Alias.  */
+#define ELFOSABI_HPUX		1	/* HP-UX */
+#define ELFOSABI_NETBSD		2	/* NetBSD.  */
+#define ELFOSABI_LINUX		3	/* Linux.  */
+#define ELFOSABI_SOLARIS	6	/* Sun Solaris.  */
+#define ELFOSABI_AIX		7	/* IBM AIX.  */
+#define ELFOSABI_IRIX		8	/* SGI Irix.  */
+#define ELFOSABI_FREEBSD	9	/* FreeBSD.  */
+#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX.  */
+#define ELFOSABI_MODESTO	11	/* Novell Modesto.  */
+#define ELFOSABI_OPENBSD	12	/* OpenBSD.  */
+#define ELFOSABI_ARM		97	/* ARM */
+#define ELFOSABI_STANDALONE	255	/* Standalone (embedded) application */
+
+#define EI_ABIVERSION	8		/* ABI version */
+
+#define EI_PAD		9		/* Byte index of padding bytes */
+
+/* Legal values for e_type (object file type).  */
+
+#define ET_NONE		0		/* No file type */
+#define ET_REL		1		/* Relocatable file */
+#define ET_EXEC		2		/* Executable file */
+#define ET_DYN		3		/* Shared object file */
+#define ET_CORE		4		/* Core file */
+#define	ET_NUM		5		/* Number of defined types */
+#define ET_LOOS		0xfe00		/* OS-specific range start */
+#define ET_HIOS		0xfeff		/* OS-specific range end */
+#define ET_LOPROC	0xff00		/* Processor-specific range start */
+#define ET_HIPROC	0xffff		/* Processor-specific range end */
+
+/* Legal values for e_machine (architecture).  */
+
+#define EM_NONE		 0		/* No machine */
+#define EM_M32		 1		/* AT&T WE 32100 */
+#define EM_SPARC	 2		/* SUN SPARC */
+#define EM_386		 3		/* Intel 80386 */
+#define EM_68K		 4		/* Motorola m68k family */
+#define EM_88K		 5		/* Motorola m88k family */
+#define EM_860		 7		/* Intel 80860 */
+#define EM_MIPS		 8		/* MIPS R3000 big-endian */
+#define EM_S370		 9		/* IBM System/370 */
+#define EM_MIPS_RS3_LE	10		/* MIPS R3000 little-endian */
+
+#define EM_PARISC	15		/* HPPA */
+#define EM_VPP500	17		/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18		/* Sun's "v8plus" */
+#define EM_960		19		/* Intel 80960 */
+#define EM_PPC		20		/* PowerPC */
+#define EM_PPC64	21		/* PowerPC 64-bit */
+#define EM_S390		22		/* IBM S390 */
+
+#define EM_V800		36		/* NEC V800 series */
+#define EM_FR20		37		/* Fujitsu FR20 */
+#define EM_RH32		38		/* TRW RH-32 */
+#define EM_RCE		39		/* Motorola RCE */
+#define EM_ARM		40		/* ARM */
+#define EM_FAKE_ALPHA	41		/* Digital Alpha */
+#define EM_SH		42		/* Hitachi SH */
+#define EM_SPARCV9	43		/* SPARC v9 64-bit */
+#define EM_TRICORE	44		/* Siemens Tricore */
+#define EM_ARC		45		/* Argonaut RISC Core */
+#define EM_H8_300	46		/* Hitachi H8/300 */
+#define EM_H8_300H	47		/* Hitachi H8/300H */
+#define EM_H8S		48		/* Hitachi H8S */
+#define EM_H8_500	49		/* Hitachi H8/500 */
+#define EM_IA_64	50		/* Intel Merced */
+#define EM_MIPS_X	51		/* Stanford MIPS-X */
+#define EM_COLDFIRE	52		/* Motorola Coldfire */
+#define EM_68HC12	53		/* Motorola M68HC12 */
+#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
+#define EM_PCP		55		/* Siemens PCP */
+#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
+#define EM_NDR1		57		/* Denso NDR1 microprocessor */
+#define EM_STARCORE	58		/* Motorola Start*Core processor */
+#define EM_ME16		59		/* Toyota ME16 processor */
+#define EM_ST100	60		/* STMicroelectronic ST100 processor */
+#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
+#define EM_X86_64	62		/* AMD x86-64 architecture */
+#define EM_PDSP		63		/* Sony DSP Processor */
+
+#define EM_FX66		66		/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
+#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
+#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
+#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
+#define EM_SVX		73		/* Silicon Graphics SVx */
+#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX		75		/* Digital VAX */
+#define EM_CRIS		76		/* Axis Communications 32-bit embedded processor */
+#define EM_JAVELIN	77		/* Infineon Technologies 32-bit embedded processor */
+#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
+#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX		80		/* Donald Knuth's educational 64-bit processor */
+#define EM_HUANY	81		/* Harvard University machine-independent object files */
+#define EM_PRISM	82		/* SiTera Prism */
+#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		84		/* Fujitsu FR30 */
+#define EM_D10V		85		/* Mitsubishi D10V */
+#define EM_D30V		86		/* Mitsubishi D30V */
+#define EM_V850		87		/* NEC v850 */
+#define EM_M32R		88		/* Mitsubishi M32R */
+#define EM_MN10300	89		/* Matsushita MN10300 */
+#define EM_MN10200	90		/* Matsushita MN10200 */
+#define EM_PJ		91		/* picoJava */
+#define EM_OPENRISC	92		/* OpenRISC 32-bit embedded processor */
+#define EM_ARC_A5	93		/* ARC Cores Tangent-A5 */
+#define EM_XTENSA	94		/* Tensilica Xtensa Architecture */
+#define EM_NUM		95
+
+/* If it is necessary to assign new unofficial EM_* values, please
+   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
+   chances of collision with official or non-GNU unofficial values.  */
+
+#define EM_ALPHA	0x9026
+
+/* Legal values for e_version (version).  */
+
+#define EV_NONE		0		/* Invalid ELF version */
+#define EV_CURRENT	1		/* Current version */
+#define EV_NUM		2
+
+/* Section header.  */
+
+typedef struct
+{
+  Elf32_Word	sh_name;		/* Section name (string tbl index) */
+  Elf32_Word	sh_type;		/* Section type */
+  Elf32_Word	sh_flags;		/* Section flags */
+  Elf32_Addr	sh_addr;		/* Section virtual addr at execution */
+  Elf32_Off	sh_offset;		/* Section file offset */
+  Elf32_Word	sh_size;		/* Section size in bytes */
+  Elf32_Word	sh_link;		/* Link to another section */
+  Elf32_Word	sh_info;		/* Additional section information */
+  Elf32_Word	sh_addralign;		/* Section alignment */
+  Elf32_Word	sh_entsize;		/* Entry size if section holds table */
+} Elf32_Shdr;
+
+typedef struct
+{
+  Elf64_Word	sh_name;		/* Section name (string tbl index) */
+  Elf64_Word	sh_type;		/* Section type */
+  Elf64_Xword	sh_flags;		/* Section flags */
+  Elf64_Addr	sh_addr;		/* Section virtual addr at execution */
+  Elf64_Off	sh_offset;		/* Section file offset */
+  Elf64_Xword	sh_size;		/* Section size in bytes */
+  Elf64_Word	sh_link;		/* Link to another section */
+  Elf64_Word	sh_info;		/* Additional section information */
+  Elf64_Xword	sh_addralign;		/* Section alignment */
+  Elf64_Xword	sh_entsize;		/* Entry size if section holds table */
+} Elf64_Shdr;
+
+/* Special section indices.  */
+
+#define SHN_UNDEF	0		/* Undefined section */
+#define SHN_LORESERVE	0xff00		/* Start of reserved indices */
+#define SHN_LOPROC	0xff00		/* Start of processor-specific */
+#define SHN_BEFORE	0xff00		/* Order section before all others
+					   (Solaris).  */
+#define SHN_AFTER	0xff01		/* Order section after all others
+					   (Solaris).  */
+#define SHN_HIPROC	0xff1f		/* End of processor-specific */
+#define SHN_LOOS	0xff20		/* Start of OS-specific */
+#define SHN_HIOS	0xff3f		/* End of OS-specific */
+#define SHN_ABS		0xfff1		/* Associated symbol is absolute */
+#define SHN_COMMON	0xfff2		/* Associated symbol is common */
+#define SHN_XINDEX	0xffff		/* Index is in extra table.  */
+#define SHN_HIRESERVE	0xffff		/* End of reserved indices */
+
+/* Legal values for sh_type (section type).  */
+
+#define SHT_NULL	  0		/* Section header table entry unused */
+#define SHT_PROGBITS	  1		/* Program data */
+#define SHT_SYMTAB	  2		/* Symbol table */
+#define SHT_STRTAB	  3		/* String table */
+#define SHT_RELA	  4		/* Relocation entries with addends */
+#define SHT_HASH	  5		/* Symbol hash table */
+#define SHT_DYNAMIC	  6		/* Dynamic linking information */
+#define SHT_NOTE	  7		/* Notes */
+#define SHT_NOBITS	  8		/* Program space with no data (bss) */
+#define SHT_REL		  9		/* Relocation entries, no addends */
+#define SHT_SHLIB	  10		/* Reserved */
+#define SHT_DYNSYM	  11		/* Dynamic linker symbol table */
+#define SHT_INIT_ARRAY	  14		/* Array of constructors */
+#define SHT_FINI_ARRAY	  15		/* Array of destructors */
+#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
+#define SHT_GROUP	  17		/* Section group */
+#define SHT_SYMTAB_SHNDX  18		/* Extended section indeces */
+#define	SHT_NUM		  19		/* Number of defined types.  */
+#define SHT_LOOS	  0x60000000	/* Start OS-specific.  */
+#define SHT_GNU_HASH	  0x6ffffff6	/* GNU-style hash table.  */
+#define SHT_GNU_LIBLIST	  0x6ffffff7	/* Prelink library list */
+#define SHT_CHECKSUM	  0x6ffffff8	/* Checksum for DSO content.  */
+#define SHT_LOSUNW	  0x6ffffffa	/* Sun-specific low bound.  */
+#define SHT_SUNW_move	  0x6ffffffa
+#define SHT_SUNW_COMDAT   0x6ffffffb
+#define SHT_SUNW_syminfo  0x6ffffffc
+#define SHT_GNU_verdef	  0x6ffffffd	/* Version definition section.  */
+#define SHT_GNU_verneed	  0x6ffffffe	/* Version needs section.  */
+#define SHT_GNU_versym	  0x6fffffff	/* Version symbol table.  */
+#define SHT_HISUNW	  0x6fffffff	/* Sun-specific high bound.  */
+#define SHT_HIOS	  0x6fffffff	/* End OS-specific type */
+#define SHT_LOPROC	  0x70000000	/* Start of processor-specific */
+#define SHT_HIPROC	  0x7fffffff	/* End of processor-specific */
+#define SHT_LOUSER	  0x80000000	/* Start of application-specific */
+#define SHT_HIUSER	  0x8fffffff	/* End of application-specific */
+
+/* Legal values for sh_flags (section flags).  */
+
+#define SHF_WRITE	     (1 << 0)	/* Writable */
+#define SHF_ALLOC	     (1 << 1)	/* Occupies memory during execution */
+#define SHF_EXECINSTR	     (1 << 2)	/* Executable */
+#define SHF_MERGE	     (1 << 4)	/* Might be merged */
+#define SHF_STRINGS	     (1 << 5)	/* Contains nul-terminated strings */
+#define SHF_INFO_LINK	     (1 << 6)	/* `sh_info' contains SHT index */
+#define SHF_LINK_ORDER	     (1 << 7)	/* Preserve order after combining */
+#define SHF_OS_NONCONFORMING (1 << 8)	/* Non-standard OS specific handling
+					   required */
+#define SHF_GROUP	     (1 << 9)	/* Section is member of a group.  */
+#define SHF_TLS		     (1 << 10)	/* Section hold thread-local data.  */
+#define SHF_MASKOS	     0x0ff00000	/* OS-specific.  */
+#define SHF_MASKPROC	     0xf0000000	/* Processor-specific */
+#define SHF_ORDERED	     (1 << 30)	/* Special ordering requirement
+					   (Solaris).  */
+#define SHF_EXCLUDE	     (1 << 31)	/* Section is excluded unless
+					   referenced or allocated (Solaris).*/
+
+/* Section group handling.  */
+#define GRP_COMDAT	0x1		/* Mark group as COMDAT.  */
+
+/* Symbol table entry.  */
+
+typedef struct
+{
+  Elf32_Word	st_name;		/* Symbol name (string tbl index) */
+  Elf32_Addr	st_value;		/* Symbol value */
+  Elf32_Word	st_size;		/* Symbol size */
+  unsigned char	st_info;		/* Symbol type and binding */
+  unsigned char	st_other;		/* Symbol visibility */
+  Elf32_Section	st_shndx;		/* Section index */
+} Elf32_Sym;
+
+typedef struct
+{
+  Elf64_Word	st_name;		/* Symbol name (string tbl index) */
+  unsigned char	st_info;		/* Symbol type and binding */
+  unsigned char st_other;		/* Symbol visibility */
+  Elf64_Section	st_shndx;		/* Section index */
+  Elf64_Addr	st_value;		/* Symbol value */
+  Elf64_Xword	st_size;		/* Symbol size */
+} Elf64_Sym;
+
+/* The syminfo section if available contains additional information about
+   every dynamic symbol.  */
+
+typedef struct
+{
+  Elf32_Half si_boundto;		/* Direct bindings, symbol bound to */
+  Elf32_Half si_flags;			/* Per symbol flags */
+} Elf32_Syminfo;
+
+typedef struct
+{
+  Elf64_Half si_boundto;		/* Direct bindings, symbol bound to */
+  Elf64_Half si_flags;			/* Per symbol flags */
+} Elf64_Syminfo;
+
+/* Possible values for si_boundto.  */
+#define SYMINFO_BT_SELF		0xffff	/* Symbol bound to self */
+#define SYMINFO_BT_PARENT	0xfffe	/* Symbol bound to parent */
+#define SYMINFO_BT_LOWRESERVE	0xff00	/* Beginning of reserved entries */
+
+/* Possible bitmasks for si_flags.  */
+#define SYMINFO_FLG_DIRECT	0x0001	/* Direct bound symbol */
+#define SYMINFO_FLG_PASSTHRU	0x0002	/* Pass-thru symbol for translator */
+#define SYMINFO_FLG_COPY	0x0004	/* Symbol is a copy-reloc */
+#define SYMINFO_FLG_LAZYLOAD	0x0008	/* Symbol bound to object to be lazy
+					   loaded */
+/* Syminfo version values.  */
+#define SYMINFO_NONE		0
+#define SYMINFO_CURRENT		1
+#define SYMINFO_NUM		2
+
+
+/* How to extract and insert information held in the st_info field.  */
+
+#define ELF32_ST_BIND(val)		(((unsigned char) (val)) >> 4)
+#define ELF32_ST_TYPE(val)		((val) & 0xf)
+#define ELF32_ST_INFO(bind, type)	(((bind) << 4) + ((type) & 0xf))
+
+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */
+#define ELF64_ST_BIND(val)		ELF32_ST_BIND (val)
+#define ELF64_ST_TYPE(val)		ELF32_ST_TYPE (val)
+#define ELF64_ST_INFO(bind, type)	ELF32_ST_INFO ((bind), (type))
+
+/* Legal values for ST_BIND subfield of st_info (symbol binding).  */
+
+#define STB_LOCAL	0		/* Local symbol */
+#define STB_GLOBAL	1		/* Global symbol */
+#define STB_WEAK	2		/* Weak symbol */
+#define	STB_NUM		3		/* Number of defined types.  */
+#define STB_LOOS	10		/* Start of OS-specific */
+#define STB_HIOS	12		/* End of OS-specific */
+#define STB_LOPROC	13		/* Start of processor-specific */
+#define STB_HIPROC	15		/* End of processor-specific */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_NOTYPE	0		/* Symbol type is unspecified */
+#define STT_OBJECT	1		/* Symbol is a data object */
+#define STT_FUNC	2		/* Symbol is a code object */
+#define STT_SECTION	3		/* Symbol associated with a section */
+#define STT_FILE	4		/* Symbol's name is file name */
+#define STT_COMMON	5		/* Symbol is a common data object */
+#define STT_TLS		6		/* Symbol is thread-local data object*/
+#define	STT_NUM		7		/* Number of defined types.  */
+#define STT_LOOS	10		/* Start of OS-specific */
+#define STT_HIOS	12		/* End of OS-specific */
+#define STT_LOPROC	13		/* Start of processor-specific */
+#define STT_HIPROC	15		/* End of processor-specific */
+
+
+/* Symbol table indices are found in the hash buckets and chain table
+   of a symbol hash table section.  This special index value indicates
+   the end of a chain, meaning no further symbols are found in that bucket.  */
+
+#define STN_UNDEF	0		/* End of a chain.  */
+
+
+/* How to extract and insert information held in the st_other field.  */
+
+#define ELF32_ST_VISIBILITY(o)	((o) & 0x03)
+
+/* For ELF64 the definitions are the same.  */
+#define ELF64_ST_VISIBILITY(o)	ELF32_ST_VISIBILITY (o)
+
+/* Symbol visibility specification encoded in the st_other field.  */
+#define STV_DEFAULT	0		/* Default symbol visibility rules */
+#define STV_INTERNAL	1		/* Processor specific hidden class */
+#define STV_HIDDEN	2		/* Sym unavailable in other modules */
+#define STV_PROTECTED	3		/* Not preemptible, not exported */
+
+
+/* Relocation table entry without addend (in section of type SHT_REL).  */
+
+typedef struct
+{
+  Elf32_Addr	r_offset;		/* Address */
+  Elf32_Word	r_info;			/* Relocation type and symbol index */
+} Elf32_Rel;
+
+/* I have seen two different definitions of the Elf64_Rel and
+   Elf64_Rela structures, so we'll leave them out until Novell (or
+   whoever) gets their act together.  */
+/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */
+
+typedef struct
+{
+  Elf64_Addr	r_offset;		/* Address */
+  Elf64_Xword	r_info;			/* Relocation type and symbol index */
+} Elf64_Rel;
+
+/* Relocation table entry with addend (in section of type SHT_RELA).  */
+
+typedef struct
+{
+  Elf32_Addr	r_offset;		/* Address */
+  Elf32_Word	r_info;			/* Relocation type and symbol index */
+  Elf32_Sword	r_addend;		/* Addend */
+} Elf32_Rela;
+
+typedef struct
+{
+  Elf64_Addr	r_offset;		/* Address */
+  Elf64_Xword	r_info;			/* Relocation type and symbol index */
+  Elf64_Sxword	r_addend;		/* Addend */
+} Elf64_Rela;
+
+/* How to extract and insert information held in the r_info field.  */
+
+#define ELF32_R_SYM(val)		((val) >> 8)
+#define ELF32_R_TYPE(val)		((val) & 0xff)
+#define ELF32_R_INFO(sym, type)		(((sym) << 8) + ((type) & 0xff))
+
+#define ELF64_R_SYM(i)			((i) >> 32)
+#define ELF64_R_TYPE(i)			((i) & 0xffffffff)
+#define ELF64_R_INFO(sym,type)		((((Elf64_Xword) (sym)) << 32) + (type))
+
+/* Program segment header.  */
+
+typedef struct
+{
+  Elf32_Word	p_type;			/* Segment type */
+  Elf32_Off	p_offset;		/* Segment file offset */
+  Elf32_Addr	p_vaddr;		/* Segment virtual address */
+  Elf32_Addr	p_paddr;		/* Segment physical address */
+  Elf32_Word	p_filesz;		/* Segment size in file */
+  Elf32_Word	p_memsz;		/* Segment size in memory */
+  Elf32_Word	p_flags;		/* Segment flags */
+  Elf32_Word	p_align;		/* Segment alignment */
+} Elf32_Phdr;
+
+typedef struct
+{
+  Elf64_Word	p_type;			/* Segment type */
+  Elf64_Word	p_flags;		/* Segment flags */
+  Elf64_Off	p_offset;		/* Segment file offset */
+  Elf64_Addr	p_vaddr;		/* Segment virtual address */
+  Elf64_Addr	p_paddr;		/* Segment physical address */
+  Elf64_Xword	p_filesz;		/* Segment size in file */
+  Elf64_Xword	p_memsz;		/* Segment size in memory */
+  Elf64_Xword	p_align;		/* Segment alignment */
+} Elf64_Phdr;
+
+/* Legal values for p_type (segment type).  */
+
+#define	PT_NULL		0		/* Program header table entry unused */
+#define PT_LOAD		1		/* Loadable program segment */
+#define PT_DYNAMIC	2		/* Dynamic linking information */
+#define PT_INTERP	3		/* Program interpreter */
+#define PT_NOTE		4		/* Auxiliary information */
+#define PT_SHLIB	5		/* Reserved */
+#define PT_PHDR		6		/* Entry for header table itself */
+#define PT_TLS		7		/* Thread-local storage segment */
+#define	PT_NUM		8		/* Number of defined types */
+#define PT_LOOS		0x60000000	/* Start of OS-specific */
+#define PT_GNU_EH_FRAME	0x6474e550	/* GCC .eh_frame_hdr segment */
+#define PT_GNU_STACK	0x6474e551	/* Indicates stack executability */
+#define PT_GNU_RELRO	0x6474e552	/* Read-only after relocation */
+#define PT_LOSUNW	0x6ffffffa
+#define PT_SUNWBSS	0x6ffffffa	/* Sun Specific segment */
+#define PT_SUNWSTACK	0x6ffffffb	/* Stack segment */
+#define PT_HISUNW	0x6fffffff
+#define PT_HIOS		0x6fffffff	/* End of OS-specific */
+#define PT_LOPROC	0x70000000	/* Start of processor-specific */
+#define PT_HIPROC	0x7fffffff	/* End of processor-specific */
+
+/* Legal values for p_flags (segment flags).  */
+
+#define PF_X		(1 << 0)	/* Segment is executable */
+#define PF_W		(1 << 1)	/* Segment is writable */
+#define PF_R		(1 << 2)	/* Segment is readable */
+#define PF_MASKOS	0x0ff00000	/* OS-specific */
+#define PF_MASKPROC	0xf0000000	/* Processor-specific */
+
+/* Legal values for note segment descriptor types for core files. */
+
+#define NT_PRSTATUS	1		/* Contains copy of prstatus struct */
+#define NT_FPREGSET	2		/* Contains copy of fpregset struct */
+#define NT_PRPSINFO	3		/* Contains copy of prpsinfo struct */
+#define NT_PRXREG	4		/* Contains copy of prxregset struct */
+#define NT_TASKSTRUCT	4		/* Contains copy of task structure */
+#define NT_PLATFORM	5		/* String from sysinfo(SI_PLATFORM) */
+#define NT_AUXV		6		/* Contains copy of auxv array */
+#define NT_GWINDOWS	7		/* Contains copy of gwindows struct */
+#define NT_ASRS		8		/* Contains copy of asrset struct */
+#define NT_PSTATUS	10		/* Contains copy of pstatus struct */
+#define NT_PSINFO	13		/* Contains copy of psinfo struct */
+#define NT_PRCRED	14		/* Contains copy of prcred struct */
+#define NT_UTSNAME	15		/* Contains copy of utsname struct */
+#define NT_LWPSTATUS	16		/* Contains copy of lwpstatus struct */
+#define NT_LWPSINFO	17		/* Contains copy of lwpinfo struct */
+#define NT_PRFPXREG	20		/* Contains copy of fprxregset struct */
+#define NT_PRXFPREG	0x46e62b7f	/* Contains copy of user_fxsr_struct */
+
+/* Legal values for the note segment descriptor types for object files.  */
+
+#define NT_VERSION	1		/* Contains a version string.  */
+
+
+/* Dynamic section entry.  */
+
+typedef struct
+{
+  Elf32_Sword	d_tag;			/* Dynamic entry type */
+  union
+    {
+      Elf32_Word d_val;			/* Integer value */
+      Elf32_Addr d_ptr;			/* Address value */
+    } d_un;
+} Elf32_Dyn;
+
+typedef struct
+{
+  Elf64_Sxword	d_tag;			/* Dynamic entry type */
+  union
+    {
+      Elf64_Xword d_val;		/* Integer value */
+      Elf64_Addr d_ptr;			/* Address value */
+    } d_un;
+} Elf64_Dyn;
+
+/* Legal values for d_tag (dynamic entry type).  */
+
+#define DT_NULL		0		/* Marks end of dynamic section */
+#define DT_NEEDED	1		/* Name of needed library */
+#define DT_PLTRELSZ	2		/* Size in bytes of PLT relocs */
+#define DT_PLTGOT	3		/* Processor defined value */
+#define DT_HASH		4		/* Address of symbol hash table */
+#define DT_STRTAB	5		/* Address of string table */
+#define DT_SYMTAB	6		/* Address of symbol table */
+#define DT_RELA		7		/* Address of Rela relocs */
+#define DT_RELASZ	8		/* Total size of Rela relocs */
+#define DT_RELAENT	9		/* Size of one Rela reloc */
+#define DT_STRSZ	10		/* Size of string table */
+#define DT_SYMENT	11		/* Size of one symbol table entry */
+#define DT_INIT		12		/* Address of init function */
+#define DT_FINI		13		/* Address of termination function */
+#define DT_SONAME	14		/* Name of shared object */
+#define DT_RPATH	15		/* Library search path (deprecated) */
+#define DT_SYMBOLIC	16		/* Start symbol search here */
+#define DT_REL		17		/* Address of Rel relocs */
+#define DT_RELSZ	18		/* Total size of Rel relocs */
+#define DT_RELENT	19		/* Size of one Rel reloc */
+#define DT_PLTREL	20		/* Type of reloc in PLT */
+#define DT_DEBUG	21		/* For debugging; unspecified */
+#define DT_TEXTREL	22		/* Reloc might modify .text */
+#define DT_JMPREL	23		/* Address of PLT relocs */
+#define	DT_BIND_NOW	24		/* Process relocations of object */
+#define	DT_INIT_ARRAY	25		/* Array with addresses of init fct */
+#define	DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
+#define	DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
+#define	DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
+#define DT_RUNPATH	29		/* Library search path */
+#define DT_FLAGS	30		/* Flags for the object being loaded */
+#define DT_ENCODING	32		/* Start of encoded range */
+#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
+#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
+#define	DT_NUM		34		/* Number used */
+#define DT_LOOS		0x6000000d	/* Start of OS-specific */
+#define DT_HIOS		0x6ffff000	/* End of OS-specific */
+#define DT_LOPROC	0x70000000	/* Start of processor-specific */
+#define DT_HIPROC	0x7fffffff	/* End of processor-specific */
+#define	DT_PROCNUM	DT_MIPS_NUM	/* Most used by any processor */
+
+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
+   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's
+   approach.  */
+#define DT_VALRNGLO	0x6ffffd00
+#define DT_GNU_PRELINKED 0x6ffffdf5	/* Prelinking timestamp */
+#define DT_GNU_CONFLICTSZ 0x6ffffdf6	/* Size of conflict section */
+#define DT_GNU_LIBLISTSZ 0x6ffffdf7	/* Size of library list */
+#define DT_CHECKSUM	0x6ffffdf8
+#define DT_PLTPADSZ	0x6ffffdf9
+#define DT_MOVEENT	0x6ffffdfa
+#define DT_MOVESZ	0x6ffffdfb
+#define DT_FEATURE_1	0x6ffffdfc	/* Feature selection (DTF_*).  */
+#define DT_POSFLAG_1	0x6ffffdfd	/* Flags for DT_* entries, effecting
+					   the following DT_* entry.  */
+#define DT_SYMINSZ	0x6ffffdfe	/* Size of syminfo table (in bytes) */
+#define DT_SYMINENT	0x6ffffdff	/* Entry size of syminfo */
+#define DT_VALRNGHI	0x6ffffdff
+#define DT_VALTAGIDX(tag)	(DT_VALRNGHI - (tag))	/* Reverse order! */
+#define DT_VALNUM 12
+
+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
+   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
+
+   If any adjustment is made to the ELF object after it has been
+   built these entries will need to be adjusted.  */
+#define DT_ADDRRNGLO	0x6ffffe00
+#define DT_GNU_HASH	0x6ffffef5	/* GNU-style hash table.  */
+#define DT_TLSDESC_PLT	0x6ffffef6
+#define DT_TLSDESC_GOT	0x6ffffef7
+#define DT_GNU_CONFLICT	0x6ffffef8	/* Start of conflict section */
+#define DT_GNU_LIBLIST	0x6ffffef9	/* Library list */
+#define DT_CONFIG	0x6ffffefa	/* Configuration information.  */
+#define DT_DEPAUDIT	0x6ffffefb	/* Dependency auditing.  */
+#define DT_AUDIT	0x6ffffefc	/* Object auditing.  */
+#define	DT_PLTPAD	0x6ffffefd	/* PLT padding.  */
+#define	DT_MOVETAB	0x6ffffefe	/* Move table.  */
+#define DT_SYMINFO	0x6ffffeff	/* Syminfo table.  */
+#define DT_ADDRRNGHI	0x6ffffeff
+#define DT_ADDRTAGIDX(tag)	(DT_ADDRRNGHI - (tag))	/* Reverse order! */
+#define DT_ADDRNUM 11
+
+/* The versioning entry types.  The next are defined as part of the
+   GNU extension.  */
+#define DT_VERSYM	0x6ffffff0
+
+#define DT_RELACOUNT	0x6ffffff9
+#define DT_RELCOUNT	0x6ffffffa
+
+/* These were chosen by Sun.  */
+#define DT_FLAGS_1	0x6ffffffb	/* State flags, see DF_1_* below.  */
+#define	DT_VERDEF	0x6ffffffc	/* Address of version definition
+					   table */
+#define	DT_VERDEFNUM	0x6ffffffd	/* Number of version definitions */
+#define	DT_VERNEED	0x6ffffffe	/* Address of table with needed
+					   versions */
+#define	DT_VERNEEDNUM	0x6fffffff	/* Number of needed versions */
+#define DT_VERSIONTAGIDX(tag)	(DT_VERNEEDNUM - (tag))	/* Reverse order! */
+#define DT_VERSIONTAGNUM 16
+
+/* Sun added these machine-independent extensions in the "processor-specific"
+   range.  Be compatible.  */
+#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */
+#define DT_FILTER       0x7fffffff      /* Shared object to get values from */
+#define DT_EXTRATAGIDX(tag)	((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)
+#define DT_EXTRANUM	3
+
+/* Values of `d_un.d_val' in the DT_FLAGS entry.  */
+#define DF_ORIGIN	0x00000001	/* Object may use DF_ORIGIN */
+#define DF_SYMBOLIC	0x00000002	/* Symbol resolutions starts here */
+#define DF_TEXTREL	0x00000004	/* Object contains text relocations */
+#define DF_BIND_NOW	0x00000008	/* No lazy binding for this object */
+#define DF_STATIC_TLS	0x00000010	/* Module uses the static TLS model */
+
+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1
+   entry in the dynamic section.  */
+#define DF_1_NOW	0x00000001	/* Set RTLD_NOW for this object.  */
+#define DF_1_GLOBAL	0x00000002	/* Set RTLD_GLOBAL for this object.  */
+#define DF_1_GROUP	0x00000004	/* Set RTLD_GROUP for this object.  */
+#define DF_1_NODELETE	0x00000008	/* Set RTLD_NODELETE for this object.*/
+#define DF_1_LOADFLTR	0x00000010	/* Trigger filtee loading at runtime.*/
+#define DF_1_INITFIRST	0x00000020	/* Set RTLD_INITFIRST for this object*/
+#define DF_1_NOOPEN	0x00000040	/* Set RTLD_NOOPEN for this object.  */
+#define DF_1_ORIGIN	0x00000080	/* $ORIGIN must be handled.  */
+#define DF_1_DIRECT	0x00000100	/* Direct binding enabled.  */
+#define DF_1_TRANS	0x00000200
+#define DF_1_INTERPOSE	0x00000400	/* Object is used to interpose.  */
+#define DF_1_NODEFLIB	0x00000800	/* Ignore default lib search path.  */
+#define DF_1_NODUMP	0x00001000	/* Object can't be dldump'ed.  */
+#define DF_1_CONFALT	0x00002000	/* Configuration alternative created.*/
+#define DF_1_ENDFILTEE	0x00004000	/* Filtee terminates filters search. */
+#define	DF_1_DISPRELDNE	0x00008000	/* Disp reloc applied at build time. */
+#define	DF_1_DISPRELPND	0x00010000	/* Disp reloc applied at run-time.  */
+
+/* Flags for the feature selection in DT_FEATURE_1.  */
+#define DTF_1_PARINIT	0x00000001
+#define DTF_1_CONFEXP	0x00000002
+
+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */
+#define DF_P1_LAZYLOAD	0x00000001	/* Lazyload following object.  */
+#define DF_P1_GROUPPERM	0x00000002	/* Symbols from next object are not
+					   generally available.  */
+
+/* Version definition sections.  */
+
+typedef struct
+{
+  Elf32_Half	vd_version;		/* Version revision */
+  Elf32_Half	vd_flags;		/* Version information */
+  Elf32_Half	vd_ndx;			/* Version Index */
+  Elf32_Half	vd_cnt;			/* Number of associated aux entries */
+  Elf32_Word	vd_hash;		/* Version name hash value */
+  Elf32_Word	vd_aux;			/* Offset in bytes to verdaux array */
+  Elf32_Word	vd_next;		/* Offset in bytes to next verdef
+					   entry */
+} Elf32_Verdef;
+
+typedef struct
+{
+  Elf64_Half	vd_version;		/* Version revision */
+  Elf64_Half	vd_flags;		/* Version information */
+  Elf64_Half	vd_ndx;			/* Version Index */
+  Elf64_Half	vd_cnt;			/* Number of associated aux entries */
+  Elf64_Word	vd_hash;		/* Version name hash value */
+  Elf64_Word	vd_aux;			/* Offset in bytes to verdaux array */
+  Elf64_Word	vd_next;		/* Offset in bytes to next verdef
+					   entry */
+} Elf64_Verdef;
+
+
+/* Legal values for vd_version (version revision).  */
+#define VER_DEF_NONE	0		/* No version */
+#define VER_DEF_CURRENT	1		/* Current version */
+#define VER_DEF_NUM	2		/* Given version number */
+
+/* Legal values for vd_flags (version information flags).  */
+#define VER_FLG_BASE	0x1		/* Version definition of file itself */
+#define VER_FLG_WEAK	0x2		/* Weak version identifier */
+
+/* Versym symbol index values.  */
+#define	VER_NDX_LOCAL		0	/* Symbol is local.  */
+#define	VER_NDX_GLOBAL		1	/* Symbol is global.  */
+#define	VER_NDX_LORESERVE	0xff00	/* Beginning of reserved entries.  */
+#define	VER_NDX_ELIMINATE	0xff01	/* Symbol is to be eliminated.  */
+
+/* Auxialiary version information.  */
+
+typedef struct
+{
+  Elf32_Word	vda_name;		/* Version or dependency names */
+  Elf32_Word	vda_next;		/* Offset in bytes to next verdaux
+					   entry */
+} Elf32_Verdaux;
+
+typedef struct
+{
+  Elf64_Word	vda_name;		/* Version or dependency names */
+  Elf64_Word	vda_next;		/* Offset in bytes to next verdaux
+					   entry */
+} Elf64_Verdaux;
+
+
+/* Version dependency section.  */
+
+typedef struct
+{
+  Elf32_Half	vn_version;		/* Version of structure */
+  Elf32_Half	vn_cnt;			/* Number of associated aux entries */
+  Elf32_Word	vn_file;		/* Offset of filename for this
+					   dependency */
+  Elf32_Word	vn_aux;			/* Offset in bytes to vernaux array */
+  Elf32_Word	vn_next;		/* Offset in bytes to next verneed
+					   entry */
+} Elf32_Verneed;
+
+typedef struct
+{
+  Elf64_Half	vn_version;		/* Version of structure */
+  Elf64_Half	vn_cnt;			/* Number of associated aux entries */
+  Elf64_Word	vn_file;		/* Offset of filename for this
+					   dependency */
+  Elf64_Word	vn_aux;			/* Offset in bytes to vernaux array */
+  Elf64_Word	vn_next;		/* Offset in bytes to next verneed
+					   entry */
+} Elf64_Verneed;
+
+
+/* Legal values for vn_version (version revision).  */
+#define VER_NEED_NONE	 0		/* No version */
+#define VER_NEED_CURRENT 1		/* Current version */
+#define VER_NEED_NUM	 2		/* Given version number */
+
+/* Auxiliary needed version information.  */
+
+typedef struct
+{
+  Elf32_Word	vna_hash;		/* Hash value of dependency name */
+  Elf32_Half	vna_flags;		/* Dependency specific information */
+  Elf32_Half	vna_other;		/* Unused */
+  Elf32_Word	vna_name;		/* Dependency name string offset */
+  Elf32_Word	vna_next;		/* Offset in bytes to next vernaux
+					   entry */
+} Elf32_Vernaux;
+
+typedef struct
+{
+  Elf64_Word	vna_hash;		/* Hash value of dependency name */
+  Elf64_Half	vna_flags;		/* Dependency specific information */
+  Elf64_Half	vna_other;		/* Unused */
+  Elf64_Word	vna_name;		/* Dependency name string offset */
+  Elf64_Word	vna_next;		/* Offset in bytes to next vernaux
+					   entry */
+} Elf64_Vernaux;
+
+
+/* Legal values for vna_flags.  */
+#define VER_FLG_WEAK	0x2		/* Weak version identifier */
+
+
+/* Auxiliary vector.  */
+
+/* This vector is normally only used by the program interpreter.  The
+   usual definition in an ABI supplement uses the name auxv_t.  The
+   vector is not usually defined in a standard <elf.h> file, but it
+   can't hurt.  We rename it to avoid conflicts.  The sizes of these
+   types are an arrangement between the exec server and the program
+   interpreter, so we don't fully specify them here.  */
+
+typedef struct
+{
+  uint32_t a_type;		/* Entry type */
+  union
+    {
+      uint32_t a_val;		/* Integer value */
+      /* We use to have pointer elements added here.  We cannot do that,
+	 though, since it does not work when using 32-bit definitions
+	 on 64-bit platforms and vice versa.  */
+    } a_un;
+} Elf32_auxv_t;
+
+typedef struct
+{
+  uint64_t a_type;		/* Entry type */
+  union
+    {
+      uint64_t a_val;		/* Integer value */
+      /* We use to have pointer elements added here.  We cannot do that,
+	 though, since it does not work when using 32-bit definitions
+	 on 64-bit platforms and vice versa.  */
+    } a_un;
+} Elf64_auxv_t;
+
+/* Legal values for a_type (entry type).  */
+
+#define AT_NULL		0		/* End of vector */
+#define AT_IGNORE	1		/* Entry should be ignored */
+#define AT_EXECFD	2		/* File descriptor of program */
+#define AT_PHDR		3		/* Program headers for program */
+#define AT_PHENT	4		/* Size of program header entry */
+#define AT_PHNUM	5		/* Number of program headers */
+#define AT_PAGESZ	6		/* System page size */
+#define AT_BASE		7		/* Base address of interpreter */
+#define AT_FLAGS	8		/* Flags */
+#define AT_ENTRY	9		/* Entry point of program */
+#define AT_NOTELF	10		/* Program is not ELF */
+#define AT_UID		11		/* Real uid */
+#define AT_EUID		12		/* Effective uid */
+#define AT_GID		13		/* Real gid */
+#define AT_EGID		14		/* Effective gid */
+#define AT_CLKTCK	17		/* Frequency of times() */
+
+/* Some more special a_type values describing the hardware.  */
+#define AT_PLATFORM	15		/* String identifying platform.  */
+#define AT_HWCAP	16		/* Machine dependent hints about
+					   processor capabilities.  */
+
+/* This entry gives some information about the FPU initialization
+   performed by the kernel.  */
+#define AT_FPUCW	18		/* Used FPU control word.  */
+
+/* Cache block sizes.  */
+#define AT_DCACHEBSIZE	19		/* Data cache block size.  */
+#define AT_ICACHEBSIZE	20		/* Instruction cache block size.  */
+#define AT_UCACHEBSIZE	21		/* Unified cache block size.  */
+
+/* A special ignored value for PPC, used by the kernel to control the
+   interpretation of the AUXV. Must be > 16.  */
+#define AT_IGNOREPPC	22		/* Entry should be ignored.  */
+
+#define	AT_SECURE	23		/* Boolean, was exec setuid-like?  */
+
+/* Pointer to the global system page used for system calls and other
+   nice things.  */
+#define AT_SYSINFO	32
+#define AT_SYSINFO_EHDR	33
+
+/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains
+   log2 of line size; mask those to get cache size.  */
+#define AT_L1I_CACHESHAPE	34
+#define AT_L1D_CACHESHAPE	35
+#define AT_L2_CACHESHAPE	36
+#define AT_L3_CACHESHAPE	37
+
+/* Note section contents.  Each entry in the note section begins with
+   a header of a fixed form.  */
+
+typedef struct
+{
+  Elf32_Word n_namesz;			/* Length of the note's name.  */
+  Elf32_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf32_Word n_type;			/* Type of the note.  */
+} Elf32_Nhdr;
+
+typedef struct
+{
+  Elf64_Word n_namesz;			/* Length of the note's name.  */
+  Elf64_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf64_Word n_type;			/* Type of the note.  */
+} Elf64_Nhdr;
+
+/* Known names of notes.  */
+
+/* Solaris entries in the note section have this name.  */
+#define ELF_NOTE_SOLARIS	"SUNW Solaris"
+
+/* Note entries for GNU systems have this name.  */
+#define ELF_NOTE_GNU		"GNU"
+
+
+/* Defined types of notes for Solaris.  */
+
+/* Value of descriptor (one word) is desired pagesize for the binary.  */
+#define ELF_NOTE_PAGESIZE_HINT	1
+
+
+/* Defined note types for GNU systems.  */
+
+/* ABI information.  The descriptor consists of words:
+   word 0: OS descriptor
+   word 1: major version of the ABI
+   word 2: minor version of the ABI
+   word 3: subminor version of the ABI
+*/
+#define NT_GNU_ABI_TAG	1
+#define ELF_NOTE_ABI	NT_GNU_ABI_TAG /* Old name.  */
+
+/* Known OSes.  These values can appear in word 0 of an
+   NT_GNU_ABI_TAG note section entry.  */
+#define ELF_NOTE_OS_LINUX	0
+#define ELF_NOTE_OS_GNU		1
+#define ELF_NOTE_OS_SOLARIS2	2
+#define ELF_NOTE_OS_FREEBSD	3
+
+/* Synthetic hwcap information.  The descriptor begins with two words:
+   word 0: number of entries
+   word 1: bitmask of enabled entries
+   Then follow variable-length entries, one byte followed by a
+   '\0'-terminated hwcap name string.  The byte gives the bit
+   number to test if enabled, (1U << bit) & bitmask.  */
+#define NT_GNU_HWCAP	2
+
+/* Build ID bits as generated by ld --build-id.
+   The descriptor consists of any nonzero number of bytes.  */
+#define NT_GNU_BUILD_ID	3
+
+
+/* Move records.  */
+typedef struct
+{
+  Elf32_Xword m_value;		/* Symbol value.  */
+  Elf32_Word m_info;		/* Size and index.  */
+  Elf32_Word m_poffset;		/* Symbol offset.  */
+  Elf32_Half m_repeat;		/* Repeat count.  */
+  Elf32_Half m_stride;		/* Stride info.  */
+} Elf32_Move;
+
+typedef struct
+{
+  Elf64_Xword m_value;		/* Symbol value.  */
+  Elf64_Xword m_info;		/* Size and index.  */
+  Elf64_Xword m_poffset;	/* Symbol offset.  */
+  Elf64_Half m_repeat;		/* Repeat count.  */
+  Elf64_Half m_stride;		/* Stride info.  */
+} Elf64_Move;
+
+/* Macro to construct move records.  */
+#define ELF32_M_SYM(info)	((info) >> 8)
+#define ELF32_M_SIZE(info)	((unsigned char) (info))
+#define ELF32_M_INFO(sym, size)	(((sym) << 8) + (unsigned char) (size))
+
+#define ELF64_M_SYM(info)	ELF32_M_SYM (info)
+#define ELF64_M_SIZE(info)	ELF32_M_SIZE (info)
+#define ELF64_M_INFO(sym, size)	ELF32_M_INFO (sym, size)
+
+
+/* Motorola 68k specific definitions.  */
+
+/* Values for Elf32_Ehdr.e_flags.  */
+#define EF_CPU32	0x00810000
+
+/* m68k relocs.  */
+
+#define R_68K_NONE	0		/* No reloc */
+#define R_68K_32	1		/* Direct 32 bit  */
+#define R_68K_16	2		/* Direct 16 bit  */
+#define R_68K_8		3		/* Direct 8 bit  */
+#define R_68K_PC32	4		/* PC relative 32 bit */
+#define R_68K_PC16	5		/* PC relative 16 bit */
+#define R_68K_PC8	6		/* PC relative 8 bit */
+#define R_68K_GOT32	7		/* 32 bit PC relative GOT entry */
+#define R_68K_GOT16	8		/* 16 bit PC relative GOT entry */
+#define R_68K_GOT8	9		/* 8 bit PC relative GOT entry */
+#define R_68K_GOT32O	10		/* 32 bit GOT offset */
+#define R_68K_GOT16O	11		/* 16 bit GOT offset */
+#define R_68K_GOT8O	12		/* 8 bit GOT offset */
+#define R_68K_PLT32	13		/* 32 bit PC relative PLT address */
+#define R_68K_PLT16	14		/* 16 bit PC relative PLT address */
+#define R_68K_PLT8	15		/* 8 bit PC relative PLT address */
+#define R_68K_PLT32O	16		/* 32 bit PLT offset */
+#define R_68K_PLT16O	17		/* 16 bit PLT offset */
+#define R_68K_PLT8O	18		/* 8 bit PLT offset */
+#define R_68K_COPY	19		/* Copy symbol at runtime */
+#define R_68K_GLOB_DAT	20		/* Create GOT entry */
+#define R_68K_JMP_SLOT	21		/* Create PLT entry */
+#define R_68K_RELATIVE	22		/* Adjust by program base */
+/* Keep this the last entry.  */
+#define R_68K_NUM	23
+
+/* Intel 80386 specific definitions.  */
+
+/* i386 relocs.  */
+
+#define R_386_NONE	   0		/* No reloc */
+#define R_386_32	   1		/* Direct 32 bit  */
+#define R_386_PC32	   2		/* PC relative 32 bit */
+#define R_386_GOT32	   3		/* 32 bit GOT entry */
+#define R_386_PLT32	   4		/* 32 bit PLT address */
+#define R_386_COPY	   5		/* Copy symbol at runtime */
+#define R_386_GLOB_DAT	   6		/* Create GOT entry */
+#define R_386_JMP_SLOT	   7		/* Create PLT entry */
+#define R_386_RELATIVE	   8		/* Adjust by program base */
+#define R_386_GOTOFF	   9		/* 32 bit offset to GOT */
+#define R_386_GOTPC	   10		/* 32 bit PC relative offset to GOT */
+#define R_386_32PLT	   11
+#define R_386_TLS_TPOFF	   14		/* Offset in static TLS block */
+#define R_386_TLS_IE	   15		/* Address of GOT entry for static TLS
+					   block offset */
+#define R_386_TLS_GOTIE	   16		/* GOT entry for static TLS block
+					   offset */
+#define R_386_TLS_LE	   17		/* Offset relative to static TLS
+					   block */
+#define R_386_TLS_GD	   18		/* Direct 32 bit for GNU version of
+					   general dynamic thread local data */
+#define R_386_TLS_LDM	   19		/* Direct 32 bit for GNU version of
+					   local dynamic thread local data
+					   in LE code */
+#define R_386_16	   20
+#define R_386_PC16	   21
+#define R_386_8		   22
+#define R_386_PC8	   23
+#define R_386_TLS_GD_32	   24		/* Direct 32 bit for general dynamic
+					   thread local data */
+#define R_386_TLS_GD_PUSH  25		/* Tag for pushl in GD TLS code */
+#define R_386_TLS_GD_CALL  26		/* Relocation for call to
+					   __tls_get_addr() */
+#define R_386_TLS_GD_POP   27		/* Tag for popl in GD TLS code */
+#define R_386_TLS_LDM_32   28		/* Direct 32 bit for local dynamic
+					   thread local data in LE code */
+#define R_386_TLS_LDM_PUSH 29		/* Tag for pushl in LDM TLS code */
+#define R_386_TLS_LDM_CALL 30		/* Relocation for call to
+					   __tls_get_addr() in LDM code */
+#define R_386_TLS_LDM_POP  31		/* Tag for popl in LDM TLS code */
+#define R_386_TLS_LDO_32   32		/* Offset relative to TLS block */
+#define R_386_TLS_IE_32	   33		/* GOT entry for negated static TLS
+					   block offset */
+#define R_386_TLS_LE_32	   34		/* Negated offset relative to static
+					   TLS block */
+#define R_386_TLS_DTPMOD32 35		/* ID of module containing symbol */
+#define R_386_TLS_DTPOFF32 36		/* Offset in TLS block */
+#define R_386_TLS_TPOFF32  37		/* Negated offset in static TLS block */
+/* Keep this the last entry.  */
+#define R_386_NUM	   38
+
+/* SUN SPARC specific definitions.  */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_SPARC_REGISTER	13	/* Global register reserved to app. */
+
+/* Values for Elf64_Ehdr.e_flags.  */
+
+#define EF_SPARCV9_MM		3
+#define EF_SPARCV9_TSO		0
+#define EF_SPARCV9_PSO		1
+#define EF_SPARCV9_RMO		2
+#define EF_SPARC_LEDATA		0x800000 /* little endian data */
+#define EF_SPARC_EXT_MASK	0xFFFF00
+#define EF_SPARC_32PLUS		0x000100 /* generic V8+ features */
+#define EF_SPARC_SUN_US1	0x000200 /* Sun UltraSPARC1 extensions */
+#define EF_SPARC_HAL_R1		0x000400 /* HAL R1 extensions */
+#define EF_SPARC_SUN_US3	0x000800 /* Sun UltraSPARCIII extensions */
+
+/* SPARC relocs.  */
+
+#define R_SPARC_NONE		0	/* No reloc */
+#define R_SPARC_8		1	/* Direct 8 bit */
+#define R_SPARC_16		2	/* Direct 16 bit */
+#define R_SPARC_32		3	/* Direct 32 bit */
+#define R_SPARC_DISP8		4	/* PC relative 8 bit */
+#define R_SPARC_DISP16		5	/* PC relative 16 bit */
+#define R_SPARC_DISP32		6	/* PC relative 32 bit */
+#define R_SPARC_WDISP30		7	/* PC relative 30 bit shifted */
+#define R_SPARC_WDISP22		8	/* PC relative 22 bit shifted */
+#define R_SPARC_HI22		9	/* High 22 bit */
+#define R_SPARC_22		10	/* Direct 22 bit */
+#define R_SPARC_13		11	/* Direct 13 bit */
+#define R_SPARC_LO10		12	/* Truncated 10 bit */
+#define R_SPARC_GOT10		13	/* Truncated 10 bit GOT entry */
+#define R_SPARC_GOT13		14	/* 13 bit GOT entry */
+#define R_SPARC_GOT22		15	/* 22 bit GOT entry shifted */
+#define R_SPARC_PC10		16	/* PC relative 10 bit truncated */
+#define R_SPARC_PC22		17	/* PC relative 22 bit shifted */
+#define R_SPARC_WPLT30		18	/* 30 bit PC relative PLT address */
+#define R_SPARC_COPY		19	/* Copy symbol at runtime */
+#define R_SPARC_GLOB_DAT	20	/* Create GOT entry */
+#define R_SPARC_JMP_SLOT	21	/* Create PLT entry */
+#define R_SPARC_RELATIVE	22	/* Adjust by program base */
+#define R_SPARC_UA32		23	/* Direct 32 bit unaligned */
+
+/* Additional Sparc64 relocs.  */
+
+#define R_SPARC_PLT32		24	/* Direct 32 bit ref to PLT entry */
+#define R_SPARC_HIPLT22		25	/* High 22 bit PLT entry */
+#define R_SPARC_LOPLT10		26	/* Truncated 10 bit PLT entry */
+#define R_SPARC_PCPLT32		27	/* PC rel 32 bit ref to PLT entry */
+#define R_SPARC_PCPLT22		28	/* PC rel high 22 bit PLT entry */
+#define R_SPARC_PCPLT10		29	/* PC rel trunc 10 bit PLT entry */
+#define R_SPARC_10		30	/* Direct 10 bit */
+#define R_SPARC_11		31	/* Direct 11 bit */
+#define R_SPARC_64		32	/* Direct 64 bit */
+#define R_SPARC_OLO10		33	/* 10bit with secondary 13bit addend */
+#define R_SPARC_HH22		34	/* Top 22 bits of direct 64 bit */
+#define R_SPARC_HM10		35	/* High middle 10 bits of ... */
+#define R_SPARC_LM22		36	/* Low middle 22 bits of ... */
+#define R_SPARC_PC_HH22		37	/* Top 22 bits of pc rel 64 bit */
+#define R_SPARC_PC_HM10		38	/* High middle 10 bit of ... */
+#define R_SPARC_PC_LM22		39	/* Low miggle 22 bits of ... */
+#define R_SPARC_WDISP16		40	/* PC relative 16 bit shifted */
+#define R_SPARC_WDISP19		41	/* PC relative 19 bit shifted */
+#define R_SPARC_7		43	/* Direct 7 bit */
+#define R_SPARC_5		44	/* Direct 5 bit */
+#define R_SPARC_6		45	/* Direct 6 bit */
+#define R_SPARC_DISP64		46	/* PC relative 64 bit */
+#define R_SPARC_PLT64		47	/* Direct 64 bit ref to PLT entry */
+#define R_SPARC_HIX22		48	/* High 22 bit complemented */
+#define R_SPARC_LOX10		49	/* Truncated 11 bit complemented */
+#define R_SPARC_H44		50	/* Direct high 12 of 44 bit */
+#define R_SPARC_M44		51	/* Direct mid 22 of 44 bit */
+#define R_SPARC_L44		52	/* Direct low 10 of 44 bit */
+#define R_SPARC_REGISTER	53	/* Global register usage */
+#define R_SPARC_UA64		54	/* Direct 64 bit unaligned */
+#define R_SPARC_UA16		55	/* Direct 16 bit unaligned */
+#define R_SPARC_TLS_GD_HI22	56
+#define R_SPARC_TLS_GD_LO10	57
+#define R_SPARC_TLS_GD_ADD	58
+#define R_SPARC_TLS_GD_CALL	59
+#define R_SPARC_TLS_LDM_HI22	60
+#define R_SPARC_TLS_LDM_LO10	61
+#define R_SPARC_TLS_LDM_ADD	62
+#define R_SPARC_TLS_LDM_CALL	63
+#define R_SPARC_TLS_LDO_HIX22	64
+#define R_SPARC_TLS_LDO_LOX10	65
+#define R_SPARC_TLS_LDO_ADD	66
+#define R_SPARC_TLS_IE_HI22	67
+#define R_SPARC_TLS_IE_LO10	68
+#define R_SPARC_TLS_IE_LD	69
+#define R_SPARC_TLS_IE_LDX	70
+#define R_SPARC_TLS_IE_ADD	71
+#define R_SPARC_TLS_LE_HIX22	72
+#define R_SPARC_TLS_LE_LOX10	73
+#define R_SPARC_TLS_DTPMOD32	74
+#define R_SPARC_TLS_DTPMOD64	75
+#define R_SPARC_TLS_DTPOFF32	76
+#define R_SPARC_TLS_DTPOFF64	77
+#define R_SPARC_TLS_TPOFF32	78
+#define R_SPARC_TLS_TPOFF64	79
+/* Keep this the last entry.  */
+#define R_SPARC_NUM		80
+
+/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */
+
+#define DT_SPARC_REGISTER 0x70000001
+#define DT_SPARC_NUM	2
+
+/* Bits present in AT_HWCAP on SPARC.  */
+
+#define HWCAP_SPARC_FLUSH	1	/* The CPU supports flush insn.  */
+#define HWCAP_SPARC_STBAR	2
+#define HWCAP_SPARC_SWAP	4
+#define HWCAP_SPARC_MULDIV	8
+#define HWCAP_SPARC_V9		16	/* The CPU is v9, so v8plus is ok.  */
+#define HWCAP_SPARC_ULTRA3	32
+#define HWCAP_SPARC_BLKINIT	64	/* Sun4v with block-init/load-twin.  */
+
+/* MIPS R3000 specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_MIPS_NOREORDER   1		/* A .noreorder directive was used */
+#define EF_MIPS_PIC	    2		/* Contains PIC code */
+#define EF_MIPS_CPIC	    4		/* Uses PIC calling sequence */
+#define EF_MIPS_XGOT	    8
+#define EF_MIPS_64BIT_WHIRL 16
+#define EF_MIPS_ABI2	    32
+#define EF_MIPS_ABI_ON32    64
+#define EF_MIPS_ARCH	    0xf0000000	/* MIPS architecture level */
+
+/* Legal values for MIPS architecture level.  */
+
+#define EF_MIPS_ARCH_1	    0x00000000	/* -mips1 code.  */
+#define EF_MIPS_ARCH_2	    0x10000000	/* -mips2 code.  */
+#define EF_MIPS_ARCH_3	    0x20000000	/* -mips3 code.  */
+#define EF_MIPS_ARCH_4	    0x30000000	/* -mips4 code.  */
+#define EF_MIPS_ARCH_5	    0x40000000	/* -mips5 code.  */
+#define EF_MIPS_ARCH_32	    0x60000000	/* MIPS32 code.  */
+#define EF_MIPS_ARCH_64	    0x70000000	/* MIPS64 code.  */
+
+/* The following are non-official names and should not be used.  */
+
+#define E_MIPS_ARCH_1	  0x00000000	/* -mips1 code.  */
+#define E_MIPS_ARCH_2	  0x10000000	/* -mips2 code.  */
+#define E_MIPS_ARCH_3	  0x20000000	/* -mips3 code.  */
+#define E_MIPS_ARCH_4	  0x30000000	/* -mips4 code.  */
+#define E_MIPS_ARCH_5	  0x40000000	/* -mips5 code.  */
+#define E_MIPS_ARCH_32	  0x60000000	/* MIPS32 code.  */
+#define E_MIPS_ARCH_64	  0x70000000	/* MIPS64 code.  */
+
+/* Special section indices.  */
+
+#define SHN_MIPS_ACOMMON    0xff00	/* Allocated common symbols */
+#define SHN_MIPS_TEXT	    0xff01	/* Allocated test symbols.  */
+#define SHN_MIPS_DATA	    0xff02	/* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON    0xff03	/* Small common symbols */
+#define SHN_MIPS_SUNDEFINED 0xff04	/* Small undefined symbols */
+
+/* Legal values for sh_type field of Elf32_Shdr.  */
+
+#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */
+#define SHT_MIPS_MSYM	       0x70000001
+#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */
+#define SHT_MIPS_GPTAB	       0x70000003 /* Global data area sizes */
+#define SHT_MIPS_UCODE	       0x70000004 /* Reserved for SGI/MIPS compilers */
+#define SHT_MIPS_DEBUG	       0x70000005 /* MIPS ECOFF debugging information*/
+#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */
+#define SHT_MIPS_PACKAGE       0x70000007
+#define SHT_MIPS_PACKSYM       0x70000008
+#define SHT_MIPS_RELD	       0x70000009
+#define SHT_MIPS_IFACE         0x7000000b
+#define SHT_MIPS_CONTENT       0x7000000c
+#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */
+#define SHT_MIPS_SHDR	       0x70000010
+#define SHT_MIPS_FDESC	       0x70000011
+#define SHT_MIPS_EXTSYM	       0x70000012
+#define SHT_MIPS_DENSE	       0x70000013
+#define SHT_MIPS_PDESC	       0x70000014
+#define SHT_MIPS_LOCSYM	       0x70000015
+#define SHT_MIPS_AUXSYM	       0x70000016
+#define SHT_MIPS_OPTSYM	       0x70000017
+#define SHT_MIPS_LOCSTR	       0x70000018
+#define SHT_MIPS_LINE	       0x70000019
+#define SHT_MIPS_RFDESC	       0x7000001a
+#define SHT_MIPS_DELTASYM      0x7000001b
+#define SHT_MIPS_DELTAINST     0x7000001c
+#define SHT_MIPS_DELTACLASS    0x7000001d
+#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */
+#define SHT_MIPS_DELTADECL     0x7000001f
+#define SHT_MIPS_SYMBOL_LIB    0x70000020
+#define SHT_MIPS_EVENTS	       0x70000021 /* Event section.  */
+#define SHT_MIPS_TRANSLATE     0x70000022
+#define SHT_MIPS_PIXIE	       0x70000023
+#define SHT_MIPS_XLATE	       0x70000024
+#define SHT_MIPS_XLATE_DEBUG   0x70000025
+#define SHT_MIPS_WHIRL	       0x70000026
+#define SHT_MIPS_EH_REGION     0x70000027
+#define SHT_MIPS_XLATE_OLD     0x70000028
+#define SHT_MIPS_PDR_EXCEPTION 0x70000029
+
+/* Legal values for sh_flags field of Elf32_Shdr.  */
+
+#define SHF_MIPS_GPREL	 0x10000000	/* Must be part of global data area */
+#define SHF_MIPS_MERGE	 0x20000000
+#define SHF_MIPS_ADDR	 0x40000000
+#define SHF_MIPS_STRINGS 0x80000000
+#define SHF_MIPS_NOSTRIP 0x08000000
+#define SHF_MIPS_LOCAL	 0x04000000
+#define SHF_MIPS_NAMES	 0x02000000
+#define SHF_MIPS_NODUPE	 0x01000000
+
+
+/* Symbol tables.  */
+
+/* MIPS specific values for `st_other'.  */
+#define STO_MIPS_DEFAULT		0x0
+#define STO_MIPS_INTERNAL		0x1
+#define STO_MIPS_HIDDEN			0x2
+#define STO_MIPS_PROTECTED		0x3
+#define STO_MIPS_SC_ALIGN_UNUSED	0xff
+
+/* MIPS specific values for `st_info'.  */
+#define STB_MIPS_SPLIT_COMMON		13
+
+/* Entries found in sections of type SHT_MIPS_GPTAB.  */
+
+typedef union
+{
+  struct
+    {
+      Elf32_Word gt_current_g_value;	/* -G value used for compilation */
+      Elf32_Word gt_unused;		/* Not used */
+    } gt_header;			/* First entry in section */
+  struct
+    {
+      Elf32_Word gt_g_value;		/* If this value were used for -G */
+      Elf32_Word gt_bytes;		/* This many bytes would be used */
+    } gt_entry;				/* Subsequent entries in section */
+} Elf32_gptab;
+
+/* Entry found in sections of type SHT_MIPS_REGINFO.  */
+
+typedef struct
+{
+  Elf32_Word	ri_gprmask;		/* General registers used */
+  Elf32_Word	ri_cprmask[4];		/* Coprocessor registers used */
+  Elf32_Sword	ri_gp_value;		/* $gp register value */
+} Elf32_RegInfo;
+
+/* Entries found in sections of type SHT_MIPS_OPTIONS.  */
+
+typedef struct
+{
+  unsigned char kind;		/* Determines interpretation of the
+				   variable part of descriptor.  */
+  unsigned char size;		/* Size of descriptor, including header.  */
+  Elf32_Section section;	/* Section header index of section affected,
+				   0 for global options.  */
+  Elf32_Word info;		/* Kind-specific information.  */
+} Elf_Options;
+
+/* Values for `kind' field in Elf_Options.  */
+
+#define ODK_NULL	0	/* Undefined.  */
+#define ODK_REGINFO	1	/* Register usage information.  */
+#define ODK_EXCEPTIONS	2	/* Exception processing options.  */
+#define ODK_PAD		3	/* Section padding options.  */
+#define ODK_HWPATCH	4	/* Hardware workarounds performed */
+#define ODK_FILL	5	/* record the fill value used by the linker. */
+#define ODK_TAGS	6	/* reserve space for desktop tools to write. */
+#define ODK_HWAND	7	/* HW workarounds.  'AND' bits when merging. */
+#define ODK_HWOR	8	/* HW workarounds.  'OR' bits when merging.  */
+
+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */
+
+#define OEX_FPU_MIN	0x1f	/* FPE's which MUST be enabled.  */
+#define OEX_FPU_MAX	0x1f00	/* FPE's which MAY be enabled.  */
+#define OEX_PAGE0	0x10000	/* page zero must be mapped.  */
+#define OEX_SMM		0x20000	/* Force sequential memory mode?  */
+#define OEX_FPDBUG	0x40000	/* Force floating point debug mode?  */
+#define OEX_PRECISEFP	OEX_FPDBUG
+#define OEX_DISMISS	0x80000	/* Dismiss invalid address faults?  */
+
+#define OEX_FPU_INVAL	0x10
+#define OEX_FPU_DIV0	0x08
+#define OEX_FPU_OFLO	0x04
+#define OEX_FPU_UFLO	0x02
+#define OEX_FPU_INEX	0x01
+
+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */
+
+#define OHW_R4KEOP	0x1	/* R4000 end-of-page patch.  */
+#define OHW_R8KPFETCH	0x2	/* may need R8000 prefetch patch.  */
+#define OHW_R5KEOP	0x4	/* R5000 end-of-page patch.  */
+#define OHW_R5KCVTL	0x8	/* R5000 cvt.[ds].l bug.  clean=1.  */
+
+#define OPAD_PREFIX	0x1
+#define OPAD_POSTFIX	0x2
+#define OPAD_SYMBOL	0x4
+
+/* Entry found in `.options' section.  */
+
+typedef struct
+{
+  Elf32_Word hwp_flags1;	/* Extra flags.  */
+  Elf32_Word hwp_flags2;	/* Extra flags.  */
+} Elf_Options_Hw;
+
+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */
+
+#define OHWA0_R4KEOP_CHECKED	0x00000001
+#define OHWA1_R4KEOP_CLEAN	0x00000002
+
+/* MIPS relocs.  */
+
+#define R_MIPS_NONE		0	/* No reloc */
+#define R_MIPS_16		1	/* Direct 16 bit */
+#define R_MIPS_32		2	/* Direct 32 bit */
+#define R_MIPS_REL32		3	/* PC relative 32 bit */
+#define R_MIPS_26		4	/* Direct 26 bit shifted */
+#define R_MIPS_HI16		5	/* High 16 bit */
+#define R_MIPS_LO16		6	/* Low 16 bit */
+#define R_MIPS_GPREL16		7	/* GP relative 16 bit */
+#define R_MIPS_LITERAL		8	/* 16 bit literal entry */
+#define R_MIPS_GOT16		9	/* 16 bit GOT entry */
+#define R_MIPS_PC16		10	/* PC relative 16 bit */
+#define R_MIPS_CALL16		11	/* 16 bit GOT entry for function */
+#define R_MIPS_GPREL32		12	/* GP relative 32 bit */
+
+#define R_MIPS_SHIFT5		16
+#define R_MIPS_SHIFT6		17
+#define R_MIPS_64		18
+#define R_MIPS_GOT_DISP		19
+#define R_MIPS_GOT_PAGE		20
+#define R_MIPS_GOT_OFST		21
+#define R_MIPS_GOT_HI16		22
+#define R_MIPS_GOT_LO16		23
+#define R_MIPS_SUB		24
+#define R_MIPS_INSERT_A		25
+#define R_MIPS_INSERT_B		26
+#define R_MIPS_DELETE		27
+#define R_MIPS_HIGHER		28
+#define R_MIPS_HIGHEST		29
+#define R_MIPS_CALL_HI16	30
+#define R_MIPS_CALL_LO16	31
+#define R_MIPS_SCN_DISP		32
+#define R_MIPS_REL16		33
+#define R_MIPS_ADD_IMMEDIATE	34
+#define R_MIPS_PJUMP		35
+#define R_MIPS_RELGOT		36
+#define R_MIPS_JALR		37
+#define R_MIPS_TLS_DTPMOD32	38	/* Module number 32 bit */
+#define R_MIPS_TLS_DTPREL32	39	/* Module-relative offset 32 bit */
+#define R_MIPS_TLS_DTPMOD64	40	/* Module number 64 bit */
+#define R_MIPS_TLS_DTPREL64	41	/* Module-relative offset 64 bit */
+#define R_MIPS_TLS_GD		42	/* 16 bit GOT offset for GD */
+#define R_MIPS_TLS_LDM		43	/* 16 bit GOT offset for LDM */
+#define R_MIPS_TLS_DTPREL_HI16	44	/* Module-relative offset, high 16 bits */
+#define R_MIPS_TLS_DTPREL_LO16	45	/* Module-relative offset, low 16 bits */
+#define R_MIPS_TLS_GOTTPREL	46	/* 16 bit GOT offset for IE */
+#define R_MIPS_TLS_TPREL32	47	/* TP-relative offset, 32 bit */
+#define R_MIPS_TLS_TPREL64	48	/* TP-relative offset, 64 bit */
+#define R_MIPS_TLS_TPREL_HI16	49	/* TP-relative offset, high 16 bits */
+#define R_MIPS_TLS_TPREL_LO16	50	/* TP-relative offset, low 16 bits */
+#define R_MIPS_GLOB_DAT		51
+/* Keep this the last entry.  */
+#define R_MIPS_NUM		52
+
+/* Legal values for p_type field of Elf32_Phdr.  */
+
+#define PT_MIPS_REGINFO	0x70000000	/* Register usage information */
+#define PT_MIPS_RTPROC  0x70000001	/* Runtime procedure table. */
+#define PT_MIPS_OPTIONS 0x70000002
+
+/* Special program header types.  */
+
+#define PF_MIPS_LOCAL	0x10000000
+
+/* Legal values for d_tag field of Elf32_Dyn.  */
+
+#define DT_MIPS_RLD_VERSION  0x70000001	/* Runtime linker interface version */
+#define DT_MIPS_TIME_STAMP   0x70000002	/* Timestamp */
+#define DT_MIPS_ICHECKSUM    0x70000003	/* Checksum */
+#define DT_MIPS_IVERSION     0x70000004	/* Version string (string tbl index) */
+#define DT_MIPS_FLAGS	     0x70000005	/* Flags */
+#define DT_MIPS_BASE_ADDRESS 0x70000006	/* Base address */
+#define DT_MIPS_MSYM	     0x70000007
+#define DT_MIPS_CONFLICT     0x70000008	/* Address of CONFLICT section */
+#define DT_MIPS_LIBLIST	     0x70000009	/* Address of LIBLIST section */
+#define DT_MIPS_LOCAL_GOTNO  0x7000000a	/* Number of local GOT entries */
+#define DT_MIPS_CONFLICTNO   0x7000000b	/* Number of CONFLICT entries */
+#define DT_MIPS_LIBLISTNO    0x70000010	/* Number of LIBLIST entries */
+#define DT_MIPS_SYMTABNO     0x70000011	/* Number of DYNSYM entries */
+#define DT_MIPS_UNREFEXTNO   0x70000012	/* First external DYNSYM */
+#define DT_MIPS_GOTSYM	     0x70000013	/* First GOT entry in DYNSYM */
+#define DT_MIPS_HIPAGENO     0x70000014	/* Number of GOT page table entries */
+#define DT_MIPS_RLD_MAP	     0x70000016	/* Address of run time loader map.  */
+#define DT_MIPS_DELTA_CLASS  0x70000017	/* Delta C++ class definition.  */
+#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in
+						DT_MIPS_DELTA_CLASS.  */
+#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */
+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in
+						DT_MIPS_DELTA_INSTANCE.  */
+#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */
+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in
+					     DT_MIPS_DELTA_RELOC.  */
+#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta
+					   relocations refer to.  */
+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in
+					   DT_MIPS_DELTA_SYM.  */
+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the
+					     class declaration.  */
+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in
+						DT_MIPS_DELTA_CLASSSYM.  */
+#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */
+#define DT_MIPS_PIXIE_INIT   0x70000023
+#define DT_MIPS_SYMBOL_LIB   0x70000024
+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025
+#define DT_MIPS_LOCAL_GOTIDX 0x70000026
+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027
+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028
+#define DT_MIPS_OPTIONS	     0x70000029 /* Address of .options.  */
+#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */
+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b
+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */
+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve
+						    function stored in GOT.  */
+#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added
+					   by rld on dlopen() calls.  */
+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */
+#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */
+#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */
+#define DT_MIPS_NUM	     0x32
+
+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */
+
+#define RHF_NONE		   0		/* No flags */
+#define RHF_QUICKSTART		   (1 << 0)	/* Use quickstart */
+#define RHF_NOTPOT		   (1 << 1)	/* Hash size not power of 2 */
+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)	/* Ignore LD_LIBRARY_PATH */
+#define RHF_NO_MOVE		   (1 << 3)
+#define RHF_SGI_ONLY		   (1 << 4)
+#define RHF_GUARANTEE_INIT	   (1 << 5)
+#define RHF_DELTA_C_PLUS_PLUS	   (1 << 6)
+#define RHF_GUARANTEE_START_INIT   (1 << 7)
+#define RHF_PIXIE		   (1 << 8)
+#define RHF_DEFAULT_DELAY_LOAD	   (1 << 9)
+#define RHF_REQUICKSTART	   (1 << 10)
+#define RHF_REQUICKSTARTED	   (1 << 11)
+#define RHF_CORD		   (1 << 12)
+#define RHF_NO_UNRES_UNDEF	   (1 << 13)
+#define RHF_RLD_ORDER_SAFE	   (1 << 14)
+
+/* Entries found in sections of type SHT_MIPS_LIBLIST.  */
+
+typedef struct
+{
+  Elf32_Word l_name;		/* Name (string table index) */
+  Elf32_Word l_time_stamp;	/* Timestamp */
+  Elf32_Word l_checksum;	/* Checksum */
+  Elf32_Word l_version;		/* Interface version */
+  Elf32_Word l_flags;		/* Flags */
+} Elf32_Lib;
+
+typedef struct
+{
+  Elf64_Word l_name;		/* Name (string table index) */
+  Elf64_Word l_time_stamp;	/* Timestamp */
+  Elf64_Word l_checksum;	/* Checksum */
+  Elf64_Word l_version;		/* Interface version */
+  Elf64_Word l_flags;		/* Flags */
+} Elf64_Lib;
+
+
+/* Legal values for l_flags.  */
+
+#define LL_NONE		  0
+#define LL_EXACT_MATCH	  (1 << 0)	/* Require exact match */
+#define LL_IGNORE_INT_VER (1 << 1)	/* Ignore interface version */
+#define LL_REQUIRE_MINOR  (1 << 2)
+#define LL_EXPORTS	  (1 << 3)
+#define LL_DELAY_LOAD	  (1 << 4)
+#define LL_DELTA	  (1 << 5)
+
+/* Entries found in sections of type SHT_MIPS_CONFLICT.  */
+
+typedef Elf32_Addr Elf32_Conflict;
+
+
+/* HPPA specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_PARISC_TRAPNIL	0x00010000 /* Trap nil pointer dereference.  */
+#define EF_PARISC_EXT		0x00020000 /* Program uses arch. extensions. */
+#define EF_PARISC_LSB		0x00040000 /* Program expects little endian. */
+#define EF_PARISC_WIDE		0x00080000 /* Program expects wide mode.  */
+#define EF_PARISC_NO_KABP	0x00100000 /* No kernel assisted branch
+					      prediction.  */
+#define EF_PARISC_LAZYSWAP	0x00400000 /* Allow lazy swapping.  */
+#define EF_PARISC_ARCH		0x0000ffff /* Architecture version.  */
+
+/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */
+
+#define EFA_PARISC_1_0		    0x020b /* PA-RISC 1.0 big-endian.  */
+#define EFA_PARISC_1_1		    0x0210 /* PA-RISC 1.1 big-endian.  */
+#define EFA_PARISC_2_0		    0x0214 /* PA-RISC 2.0 big-endian.  */
+
+/* Additional section indeces.  */
+
+#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tenatively declared
+					      symbols in ANSI C.  */
+#define SHN_PARISC_HUGE_COMMON	0xff01	   /* Common blocks in huge model.  */
+
+/* Legal values for sh_type field of Elf32_Shdr.  */
+
+#define SHT_PARISC_EXT		0x70000000 /* Contains product specific ext. */
+#define SHT_PARISC_UNWIND	0x70000001 /* Unwind information.  */
+#define SHT_PARISC_DOC		0x70000002 /* Debug info for optimized code. */
+
+/* Legal values for sh_flags field of Elf32_Shdr.  */
+
+#define SHF_PARISC_SHORT	0x20000000 /* Section with short addressing. */
+#define SHF_PARISC_HUGE		0x40000000 /* Section far from gp.  */
+#define SHF_PARISC_SBP		0x80000000 /* Static branch prediction code. */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_PARISC_MILLICODE	13	/* Millicode function entry point.  */
+
+#define STT_HP_OPAQUE		(STT_LOOS + 0x1)
+#define STT_HP_STUB		(STT_LOOS + 0x2)
+
+/* HPPA relocs.  */
+
+#define R_PARISC_NONE		0	/* No reloc.  */
+#define R_PARISC_DIR32		1	/* Direct 32-bit reference.  */
+#define R_PARISC_DIR21L		2	/* Left 21 bits of eff. address.  */
+#define R_PARISC_DIR17R		3	/* Right 17 bits of eff. address.  */
+#define R_PARISC_DIR17F		4	/* 17 bits of eff. address.  */
+#define R_PARISC_DIR14R		6	/* Right 14 bits of eff. address.  */
+#define R_PARISC_PCREL32	9	/* 32-bit rel. address.  */
+#define R_PARISC_PCREL21L	10	/* Left 21 bits of rel. address.  */
+#define R_PARISC_PCREL17R	11	/* Right 17 bits of rel. address.  */
+#define R_PARISC_PCREL17F	12	/* 17 bits of rel. address.  */
+#define R_PARISC_PCREL14R	14	/* Right 14 bits of rel. address.  */
+#define R_PARISC_DPREL21L	18	/* Left 21 bits of rel. address.  */
+#define R_PARISC_DPREL14R	22	/* Right 14 bits of rel. address.  */
+#define R_PARISC_GPREL21L	26	/* GP-relative, left 21 bits.  */
+#define R_PARISC_GPREL14R	30	/* GP-relative, right 14 bits.  */
+#define R_PARISC_LTOFF21L	34	/* LT-relative, left 21 bits.  */
+#define R_PARISC_LTOFF14R	38	/* LT-relative, right 14 bits.  */
+#define R_PARISC_SECREL32	41	/* 32 bits section rel. address.  */
+#define R_PARISC_SEGBASE	48	/* No relocation, set segment base.  */
+#define R_PARISC_SEGREL32	49	/* 32 bits segment rel. address.  */
+#define R_PARISC_PLTOFF21L	50	/* PLT rel. address, left 21 bits.  */
+#define R_PARISC_PLTOFF14R	54	/* PLT rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF_FPTR32	57	/* 32 bits LT-rel. function pointer. */
+#define R_PARISC_LTOFF_FPTR21L	58	/* LT-rel. fct ptr, left 21 bits. */
+#define R_PARISC_LTOFF_FPTR14R	62	/* LT-rel. fct ptr, right 14 bits. */
+#define R_PARISC_FPTR64		64	/* 64 bits function address.  */
+#define R_PARISC_PLABEL32	65	/* 32 bits function address.  */
+#define R_PARISC_PLABEL21L	66	/* Left 21 bits of fdesc address.  */
+#define R_PARISC_PLABEL14R	70	/* Right 14 bits of fdesc address.  */
+#define R_PARISC_PCREL64	72	/* 64 bits PC-rel. address.  */
+#define R_PARISC_PCREL22F	74	/* 22 bits PC-rel. address.  */
+#define R_PARISC_PCREL14WR	75	/* PC-rel. address, right 14 bits.  */
+#define R_PARISC_PCREL14DR	76	/* PC rel. address, right 14 bits.  */
+#define R_PARISC_PCREL16F	77	/* 16 bits PC-rel. address.  */
+#define R_PARISC_PCREL16WF	78	/* 16 bits PC-rel. address.  */
+#define R_PARISC_PCREL16DF	79	/* 16 bits PC-rel. address.  */
+#define R_PARISC_DIR64		80	/* 64 bits of eff. address.  */
+#define R_PARISC_DIR14WR	83	/* 14 bits of eff. address.  */
+#define R_PARISC_DIR14DR	84	/* 14 bits of eff. address.  */
+#define R_PARISC_DIR16F		85	/* 16 bits of eff. address.  */
+#define R_PARISC_DIR16WF	86	/* 16 bits of eff. address.  */
+#define R_PARISC_DIR16DF	87	/* 16 bits of eff. address.  */
+#define R_PARISC_GPREL64	88	/* 64 bits of GP-rel. address.  */
+#define R_PARISC_GPREL14WR	91	/* GP-rel. address, right 14 bits.  */
+#define R_PARISC_GPREL14DR	92	/* GP-rel. address, right 14 bits.  */
+#define R_PARISC_GPREL16F	93	/* 16 bits GP-rel. address.  */
+#define R_PARISC_GPREL16WF	94	/* 16 bits GP-rel. address.  */
+#define R_PARISC_GPREL16DF	95	/* 16 bits GP-rel. address.  */
+#define R_PARISC_LTOFF64	96	/* 64 bits LT-rel. address.  */
+#define R_PARISC_LTOFF14WR	99	/* LT-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF14DR	100	/* LT-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF16F	101	/* 16 bits LT-rel. address.  */
+#define R_PARISC_LTOFF16WF	102	/* 16 bits LT-rel. address.  */
+#define R_PARISC_LTOFF16DF	103	/* 16 bits LT-rel. address.  */
+#define R_PARISC_SECREL64	104	/* 64 bits section rel. address.  */
+#define R_PARISC_SEGREL64	112	/* 64 bits segment rel. address.  */
+#define R_PARISC_PLTOFF14WR	115	/* PLT-rel. address, right 14 bits.  */
+#define R_PARISC_PLTOFF14DR	116	/* PLT-rel. address, right 14 bits.  */
+#define R_PARISC_PLTOFF16F	117	/* 16 bits LT-rel. address.  */
+#define R_PARISC_PLTOFF16WF	118	/* 16 bits PLT-rel. address.  */
+#define R_PARISC_PLTOFF16DF	119	/* 16 bits PLT-rel. address.  */
+#define R_PARISC_LTOFF_FPTR64	120	/* 64 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR14WR	123	/* LT-rel. fct. ptr., right 14 bits. */
+#define R_PARISC_LTOFF_FPTR14DR	124	/* LT-rel. fct. ptr., right 14 bits. */
+#define R_PARISC_LTOFF_FPTR16F	125	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR16WF	126	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR16DF	127	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LORESERVE	128
+#define R_PARISC_COPY		128	/* Copy relocation.  */
+#define R_PARISC_IPLT		129	/* Dynamic reloc, imported PLT */
+#define R_PARISC_EPLT		130	/* Dynamic reloc, exported PLT */
+#define R_PARISC_TPREL32	153	/* 32 bits TP-rel. address.  */
+#define R_PARISC_TPREL21L	154	/* TP-rel. address, left 21 bits.  */
+#define R_PARISC_TPREL14R	158	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF_TP21L	162	/* LT-TP-rel. address, left 21 bits. */
+#define R_PARISC_LTOFF_TP14R	166	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP14F	167	/* 14 bits LT-TP-rel. address.  */
+#define R_PARISC_TPREL64	216	/* 64 bits TP-rel. address.  */
+#define R_PARISC_TPREL14WR	219	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_TPREL14DR	220	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_TPREL16F	221	/* 16 bits TP-rel. address.  */
+#define R_PARISC_TPREL16WF	222	/* 16 bits TP-rel. address.  */
+#define R_PARISC_TPREL16DF	223	/* 16 bits TP-rel. address.  */
+#define R_PARISC_LTOFF_TP64	224	/* 64 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP14WR	227	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP14DR	228	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP16F	229	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP16WF	230	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP16DF	231	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_GNU_VTENTRY	232
+#define R_PARISC_GNU_VTINHERIT	233
+#define R_PARISC_TLS_GD21L	234	/* GD 21-bit left.  */
+#define R_PARISC_TLS_GD14R	235	/* GD 14-bit right.  */
+#define R_PARISC_TLS_GDCALL	236	/* GD call to __t_g_a.  */
+#define R_PARISC_TLS_LDM21L	237	/* LD module 21-bit left.  */
+#define R_PARISC_TLS_LDM14R	238	/* LD module 14-bit right.  */
+#define R_PARISC_TLS_LDMCALL	239	/* LD module call to __t_g_a.  */
+#define R_PARISC_TLS_LDO21L	240	/* LD offset 21-bit left.  */
+#define R_PARISC_TLS_LDO14R	241	/* LD offset 14-bit right.  */
+#define R_PARISC_TLS_DTPMOD32	242	/* DTP module 32-bit.  */
+#define R_PARISC_TLS_DTPMOD64	243	/* DTP module 64-bit.  */
+#define R_PARISC_TLS_DTPOFF32	244	/* DTP offset 32-bit.  */
+#define R_PARISC_TLS_DTPOFF64	245	/* DTP offset 32-bit.  */
+#define R_PARISC_TLS_LE21L	R_PARISC_TPREL21L
+#define R_PARISC_TLS_LE14R	R_PARISC_TPREL14R
+#define R_PARISC_TLS_IE21L	R_PARISC_LTOFF_TP21L
+#define R_PARISC_TLS_IE14R	R_PARISC_LTOFF_TP14R
+#define R_PARISC_TLS_TPREL32	R_PARISC_TPREL32
+#define R_PARISC_TLS_TPREL64	R_PARISC_TPREL64
+#define R_PARISC_HIRESERVE	255
+
+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */
+
+#define PT_HP_TLS		(PT_LOOS + 0x0)
+#define PT_HP_CORE_NONE		(PT_LOOS + 0x1)
+#define PT_HP_CORE_VERSION	(PT_LOOS + 0x2)
+#define PT_HP_CORE_KERNEL	(PT_LOOS + 0x3)
+#define PT_HP_CORE_COMM		(PT_LOOS + 0x4)
+#define PT_HP_CORE_PROC		(PT_LOOS + 0x5)
+#define PT_HP_CORE_LOADABLE	(PT_LOOS + 0x6)
+#define PT_HP_CORE_STACK	(PT_LOOS + 0x7)
+#define PT_HP_CORE_SHM		(PT_LOOS + 0x8)
+#define PT_HP_CORE_MMF		(PT_LOOS + 0x9)
+#define PT_HP_PARALLEL		(PT_LOOS + 0x10)
+#define PT_HP_FASTBIND		(PT_LOOS + 0x11)
+#define PT_HP_OPT_ANNOT		(PT_LOOS + 0x12)
+#define PT_HP_HSL_ANNOT		(PT_LOOS + 0x13)
+#define PT_HP_STACK		(PT_LOOS + 0x14)
+
+#define PT_PARISC_ARCHEXT	0x70000000
+#define PT_PARISC_UNWIND	0x70000001
+
+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */
+
+#define PF_PARISC_SBP		0x08000000
+
+#define PF_HP_PAGE_SIZE		0x00100000
+#define PF_HP_FAR_SHARED	0x00200000
+#define PF_HP_NEAR_SHARED	0x00400000
+#define PF_HP_CODE		0x01000000
+#define PF_HP_MODIFY		0x02000000
+#define PF_HP_LAZYSWAP		0x04000000
+#define PF_HP_SBP		0x08000000
+
+
+/* Alpha specific definitions.  */
+
+/* Legal values for e_flags field of Elf64_Ehdr.  */
+
+#define EF_ALPHA_32BIT		1	/* All addresses must be < 2GB.  */
+#define EF_ALPHA_CANRELAX	2	/* Relocations for relaxing exist.  */
+
+/* Legal values for sh_type field of Elf64_Shdr.  */
+
+/* These two are primerily concerned with ECOFF debugging info.  */
+#define SHT_ALPHA_DEBUG		0x70000001
+#define SHT_ALPHA_REGINFO	0x70000002
+
+/* Legal values for sh_flags field of Elf64_Shdr.  */
+
+#define SHF_ALPHA_GPREL		0x10000000
+
+/* Legal values for st_other field of Elf64_Sym.  */
+#define STO_ALPHA_NOPV		0x80	/* No PV required.  */
+#define STO_ALPHA_STD_GPLOAD	0x88	/* PV only used for initial ldgp.  */
+
+/* Alpha relocs.  */
+
+#define R_ALPHA_NONE		0	/* No reloc */
+#define R_ALPHA_REFLONG		1	/* Direct 32 bit */
+#define R_ALPHA_REFQUAD		2	/* Direct 64 bit */
+#define R_ALPHA_GPREL32		3	/* GP relative 32 bit */
+#define R_ALPHA_LITERAL		4	/* GP relative 16 bit w/optimization */
+#define R_ALPHA_LITUSE		5	/* Optimization hint for LITERAL */
+#define R_ALPHA_GPDISP		6	/* Add displacement to GP */
+#define R_ALPHA_BRADDR		7	/* PC+4 relative 23 bit shifted */
+#define R_ALPHA_HINT		8	/* PC+4 relative 16 bit shifted */
+#define R_ALPHA_SREL16		9	/* PC relative 16 bit */
+#define R_ALPHA_SREL32		10	/* PC relative 32 bit */
+#define R_ALPHA_SREL64		11	/* PC relative 64 bit */
+#define R_ALPHA_GPRELHIGH	17	/* GP relative 32 bit, high 16 bits */
+#define R_ALPHA_GPRELLOW	18	/* GP relative 32 bit, low 16 bits */
+#define R_ALPHA_GPREL16		19	/* GP relative 16 bit */
+#define R_ALPHA_COPY		24	/* Copy symbol at runtime */
+#define R_ALPHA_GLOB_DAT	25	/* Create GOT entry */
+#define R_ALPHA_JMP_SLOT	26	/* Create PLT entry */
+#define R_ALPHA_RELATIVE	27	/* Adjust by program base */
+#define R_ALPHA_TLS_GD_HI	28
+#define R_ALPHA_TLSGD		29
+#define R_ALPHA_TLS_LDM		30
+#define R_ALPHA_DTPMOD64	31
+#define R_ALPHA_GOTDTPREL	32
+#define R_ALPHA_DTPREL64	33
+#define R_ALPHA_DTPRELHI	34
+#define R_ALPHA_DTPRELLO	35
+#define R_ALPHA_DTPREL16	36
+#define R_ALPHA_GOTTPREL	37
+#define R_ALPHA_TPREL64		38
+#define R_ALPHA_TPRELHI		39
+#define R_ALPHA_TPRELLO		40
+#define R_ALPHA_TPREL16		41
+/* Keep this the last entry.  */
+#define R_ALPHA_NUM		46
+
+/* Magic values of the LITUSE relocation addend.  */
+#define LITUSE_ALPHA_ADDR	0
+#define LITUSE_ALPHA_BASE	1
+#define LITUSE_ALPHA_BYTOFF	2
+#define LITUSE_ALPHA_JSR	3
+#define LITUSE_ALPHA_TLS_GD	4
+#define LITUSE_ALPHA_TLS_LDM	5
+
+/* Legal values for d_tag of Elf64_Dyn.  */
+#define DT_ALPHA_PLTRO		(DT_LOPROC + 0)
+#define DT_ALPHA_NUM		1
+
+/* PowerPC specific declarations */
+
+/* Values for Elf32/64_Ehdr.e_flags.  */
+#define EF_PPC_EMB		0x80000000	/* PowerPC embedded flag */
+
+/* Cygnus local bits below */
+#define EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag*/
+#define EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib
+						   flag */
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE		0
+#define R_PPC_ADDR32		1	/* 32bit absolute address */
+#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16		3	/* 16bit absolute address */
+#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
+#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN	8
+#define R_PPC_ADDR14_BRNTAKEN	9
+#define R_PPC_REL24		10	/* PC relative 26 bit */
+#define R_PPC_REL14		11	/* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN	12
+#define R_PPC_REL14_BRNTAKEN	13
+#define R_PPC_GOT16		14
+#define R_PPC_GOT16_LO		15
+#define R_PPC_GOT16_HI		16
+#define R_PPC_GOT16_HA		17
+#define R_PPC_PLTREL24		18
+#define R_PPC_COPY		19
+#define R_PPC_GLOB_DAT		20
+#define R_PPC_JMP_SLOT		21
+#define R_PPC_RELATIVE		22
+#define R_PPC_LOCAL24PC		23
+#define R_PPC_UADDR32		24
+#define R_PPC_UADDR16		25
+#define R_PPC_REL32		26
+#define R_PPC_PLT32		27
+#define R_PPC_PLTREL32		28
+#define R_PPC_PLT16_LO		29
+#define R_PPC_PLT16_HI		30
+#define R_PPC_PLT16_HA		31
+#define R_PPC_SDAREL16		32
+#define R_PPC_SECTOFF		33
+#define R_PPC_SECTOFF_LO	34
+#define R_PPC_SECTOFF_HI	35
+#define R_PPC_SECTOFF_HA	36
+
+/* PowerPC relocations defined for the TLS access ABI.  */
+#define R_PPC_TLS		67 /* none	(sym+add)@tls */
+#define R_PPC_DTPMOD32		68 /* word32	(sym+add)@dtpmod */
+#define R_PPC_TPREL16		69 /* half16*	(sym+add)@tprel */
+#define R_PPC_TPREL16_LO	70 /* half16	(sym+add)@tprel at l */
+#define R_PPC_TPREL16_HI	71 /* half16	(sym+add)@tprel at h */
+#define R_PPC_TPREL16_HA	72 /* half16	(sym+add)@tprel at ha */
+#define R_PPC_TPREL32		73 /* word32	(sym+add)@tprel */
+#define R_PPC_DTPREL16		74 /* half16*	(sym+add)@dtprel */
+#define R_PPC_DTPREL16_LO	75 /* half16	(sym+add)@dtprel at l */
+#define R_PPC_DTPREL16_HI	76 /* half16	(sym+add)@dtprel at h */
+#define R_PPC_DTPREL16_HA	77 /* half16	(sym+add)@dtprel at ha */
+#define R_PPC_DTPREL32		78 /* word32	(sym+add)@dtprel */
+#define R_PPC_GOT_TLSGD16	79 /* half16*	(sym+add)@got at tlsgd */
+#define R_PPC_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got at tlsgd@l */
+#define R_PPC_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got at tlsgd@h */
+#define R_PPC_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got at tlsgd@ha */
+#define R_PPC_GOT_TLSLD16	83 /* half16*	(sym+add)@got at tlsld */
+#define R_PPC_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got at tlsld@l */
+#define R_PPC_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got at tlsld@h */
+#define R_PPC_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got at tlsld@ha */
+#define R_PPC_GOT_TPREL16	87 /* half16*	(sym+add)@got at tprel */
+#define R_PPC_GOT_TPREL16_LO	88 /* half16	(sym+add)@got at tprel@l */
+#define R_PPC_GOT_TPREL16_HI	89 /* half16	(sym+add)@got at tprel@h */
+#define R_PPC_GOT_TPREL16_HA	90 /* half16	(sym+add)@got at tprel@ha */
+#define R_PPC_GOT_DTPREL16	91 /* half16*	(sym+add)@got at dtprel */
+#define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got at dtprel@l */
+#define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got at dtprel@h */
+#define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got at dtprel@ha */
+
+/* Keep this the last entry.  */
+#define R_PPC_NUM		95
+
+/* The remaining relocs are from the Embedded ELF ABI, and are not
+   in the SVR4 ELF ABI.  */
+#define R_PPC_EMB_NADDR32	101
+#define R_PPC_EMB_NADDR16	102
+#define R_PPC_EMB_NADDR16_LO	103
+#define R_PPC_EMB_NADDR16_HI	104
+#define R_PPC_EMB_NADDR16_HA	105
+#define R_PPC_EMB_SDAI16	106
+#define R_PPC_EMB_SDA2I16	107
+#define R_PPC_EMB_SDA2REL	108
+#define R_PPC_EMB_SDA21		109	/* 16 bit offset in SDA */
+#define R_PPC_EMB_MRKREF	110
+#define R_PPC_EMB_RELSEC16	111
+#define R_PPC_EMB_RELST_LO	112
+#define R_PPC_EMB_RELST_HI	113
+#define R_PPC_EMB_RELST_HA	114
+#define R_PPC_EMB_BIT_FLD	115
+#define R_PPC_EMB_RELSDA	116	/* 16 bit relative offset in SDA */
+
+/* Diab tool relocations.  */
+#define R_PPC_DIAB_SDA21_LO	180	/* like EMB_SDA21, but lower 16 bit */
+#define R_PPC_DIAB_SDA21_HI	181	/* like EMB_SDA21, but high 16 bit */
+#define R_PPC_DIAB_SDA21_HA	182	/* like EMB_SDA21, adjusted high 16 */
+#define R_PPC_DIAB_RELSDA_LO	183	/* like EMB_RELSDA, but lower 16 bit */
+#define R_PPC_DIAB_RELSDA_HI	184	/* like EMB_RELSDA, but high 16 bit */
+#define R_PPC_DIAB_RELSDA_HA	185	/* like EMB_RELSDA, adjusted high 16 */
+
+/* GNU relocs used in PIC code sequences.  */
+#define R_PPC_REL16		249	/* word32   (sym-.) */
+#define R_PPC_REL16_LO		250	/* half16   (sym-.)@l */
+#define R_PPC_REL16_HI		251	/* half16   (sym-.)@h */
+#define R_PPC_REL16_HA		252	/* half16   (sym-.)@ha */
+
+/* This is a phony reloc to handle any old fashioned TOC16 references
+   that may still be in object files.  */
+#define R_PPC_TOC16		255
+
+/* PowerPC specific values for the Dyn d_tag field.  */
+#define DT_PPC_GOT		(DT_LOPROC + 0)
+#define DT_PPC_NUM		1
+
+/* PowerPC64 relocations defined by the ABIs */
+#define R_PPC64_NONE		R_PPC_NONE
+#define R_PPC64_ADDR32		R_PPC_ADDR32 /* 32bit absolute address */
+#define R_PPC64_ADDR24		R_PPC_ADDR24 /* 26bit address, word aligned */
+#define R_PPC64_ADDR16		R_PPC_ADDR16 /* 16bit absolute address */
+#define R_PPC64_ADDR16_LO	R_PPC_ADDR16_LO	/* lower 16bits of address */
+#define R_PPC64_ADDR16_HI	R_PPC_ADDR16_HI	/* high 16bits of address. */
+#define R_PPC64_ADDR16_HA	R_PPC_ADDR16_HA /* adjusted high 16bits.  */
+#define R_PPC64_ADDR14		R_PPC_ADDR14 /* 16bit address, word aligned */
+#define R_PPC64_ADDR14_BRTAKEN	R_PPC_ADDR14_BRTAKEN
+#define R_PPC64_ADDR14_BRNTAKEN	R_PPC_ADDR14_BRNTAKEN
+#define R_PPC64_REL24		R_PPC_REL24 /* PC-rel. 26 bit, word aligned */
+#define R_PPC64_REL14		R_PPC_REL14 /* PC relative 16 bit */
+#define R_PPC64_REL14_BRTAKEN	R_PPC_REL14_BRTAKEN
+#define R_PPC64_REL14_BRNTAKEN	R_PPC_REL14_BRNTAKEN
+#define R_PPC64_GOT16		R_PPC_GOT16
+#define R_PPC64_GOT16_LO	R_PPC_GOT16_LO
+#define R_PPC64_GOT16_HI	R_PPC_GOT16_HI
+#define R_PPC64_GOT16_HA	R_PPC_GOT16_HA
+
+#define R_PPC64_COPY		R_PPC_COPY
+#define R_PPC64_GLOB_DAT	R_PPC_GLOB_DAT
+#define R_PPC64_JMP_SLOT	R_PPC_JMP_SLOT
+#define R_PPC64_RELATIVE	R_PPC_RELATIVE
+
+#define R_PPC64_UADDR32		R_PPC_UADDR32
+#define R_PPC64_UADDR16		R_PPC_UADDR16
+#define R_PPC64_REL32		R_PPC_REL32
+#define R_PPC64_PLT32		R_PPC_PLT32
+#define R_PPC64_PLTREL32	R_PPC_PLTREL32
+#define R_PPC64_PLT16_LO	R_PPC_PLT16_LO
+#define R_PPC64_PLT16_HI	R_PPC_PLT16_HI
+#define R_PPC64_PLT16_HA	R_PPC_PLT16_HA
+
+#define R_PPC64_SECTOFF		R_PPC_SECTOFF
+#define R_PPC64_SECTOFF_LO	R_PPC_SECTOFF_LO
+#define R_PPC64_SECTOFF_HI	R_PPC_SECTOFF_HI
+#define R_PPC64_SECTOFF_HA	R_PPC_SECTOFF_HA
+#define R_PPC64_ADDR30		37 /* word30 (S + A - P) >> 2 */
+#define R_PPC64_ADDR64		38 /* doubleword64 S + A */
+#define R_PPC64_ADDR16_HIGHER	39 /* half16 #higher(S + A) */
+#define R_PPC64_ADDR16_HIGHERA	40 /* half16 #highera(S + A) */
+#define R_PPC64_ADDR16_HIGHEST	41 /* half16 #highest(S + A) */
+#define R_PPC64_ADDR16_HIGHESTA	42 /* half16 #highesta(S + A) */
+#define R_PPC64_UADDR64		43 /* doubleword64 S + A */
+#define R_PPC64_REL64		44 /* doubleword64 S + A - P */
+#define R_PPC64_PLT64		45 /* doubleword64 L + A */
+#define R_PPC64_PLTREL64	46 /* doubleword64 L + A - P */
+#define R_PPC64_TOC16		47 /* half16* S + A - .TOC */
+#define R_PPC64_TOC16_LO	48 /* half16 #lo(S + A - .TOC.) */
+#define R_PPC64_TOC16_HI	49 /* half16 #hi(S + A - .TOC.) */
+#define R_PPC64_TOC16_HA	50 /* half16 #ha(S + A - .TOC.) */
+#define R_PPC64_TOC		51 /* doubleword64 .TOC */
+#define R_PPC64_PLTGOT16	52 /* half16* M + A */
+#define R_PPC64_PLTGOT16_LO	53 /* half16 #lo(M + A) */
+#define R_PPC64_PLTGOT16_HI	54 /* half16 #hi(M + A) */
+#define R_PPC64_PLTGOT16_HA	55 /* half16 #ha(M + A) */
+
+#define R_PPC64_ADDR16_DS	56 /* half16ds* (S + A) >> 2 */
+#define R_PPC64_ADDR16_LO_DS	57 /* half16ds  #lo(S + A) >> 2 */
+#define R_PPC64_GOT16_DS	58 /* half16ds* (G + A) >> 2 */
+#define R_PPC64_GOT16_LO_DS	59 /* half16ds  #lo(G + A) >> 2 */
+#define R_PPC64_PLT16_LO_DS	60 /* half16ds  #lo(L + A) >> 2 */
+#define R_PPC64_SECTOFF_DS	61 /* half16ds* (R + A) >> 2 */
+#define R_PPC64_SECTOFF_LO_DS	62 /* half16ds  #lo(R + A) >> 2 */
+#define R_PPC64_TOC16_DS	63 /* half16ds* (S + A - .TOC.) >> 2 */
+#define R_PPC64_TOC16_LO_DS	64 /* half16ds  #lo(S + A - .TOC.) >> 2 */
+#define R_PPC64_PLTGOT16_DS	65 /* half16ds* (M + A) >> 2 */
+#define R_PPC64_PLTGOT16_LO_DS	66 /* half16ds  #lo(M + A) >> 2 */
+
+/* PowerPC64 relocations defined for the TLS access ABI.  */
+#define R_PPC64_TLS		67 /* none	(sym+add)@tls */
+#define R_PPC64_DTPMOD64	68 /* doubleword64 (sym+add)@dtpmod */
+#define R_PPC64_TPREL16		69 /* half16*	(sym+add)@tprel */
+#define R_PPC64_TPREL16_LO	70 /* half16	(sym+add)@tprel at l */
+#define R_PPC64_TPREL16_HI	71 /* half16	(sym+add)@tprel at h */
+#define R_PPC64_TPREL16_HA	72 /* half16	(sym+add)@tprel at ha */
+#define R_PPC64_TPREL64		73 /* doubleword64 (sym+add)@tprel */
+#define R_PPC64_DTPREL16	74 /* half16*	(sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO	75 /* half16	(sym+add)@dtprel at l */
+#define R_PPC64_DTPREL16_HI	76 /* half16	(sym+add)@dtprel at h */
+#define R_PPC64_DTPREL16_HA	77 /* half16	(sym+add)@dtprel at ha */
+#define R_PPC64_DTPREL64	78 /* doubleword64 (sym+add)@dtprel */
+#define R_PPC64_GOT_TLSGD16	79 /* half16*	(sym+add)@got at tlsgd */
+#define R_PPC64_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got at tlsgd@l */
+#define R_PPC64_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got at tlsgd@h */
+#define R_PPC64_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got at tlsgd@ha */
+#define R_PPC64_GOT_TLSLD16	83 /* half16*	(sym+add)@got at tlsld */
+#define R_PPC64_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got at tlsld@l */
+#define R_PPC64_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got at tlsld@h */
+#define R_PPC64_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got at tlsld@ha */
+#define R_PPC64_GOT_TPREL16_DS	87 /* half16ds*	(sym+add)@got at tprel */
+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got at tprel@l */
+#define R_PPC64_GOT_TPREL16_HI	89 /* half16	(sym+add)@got at tprel@h */
+#define R_PPC64_GOT_TPREL16_HA	90 /* half16	(sym+add)@got at tprel@ha */
+#define R_PPC64_GOT_DTPREL16_DS	91 /* half16ds*	(sym+add)@got at dtprel */
+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got at dtprel@l */
+#define R_PPC64_GOT_DTPREL16_HI	93 /* half16	(sym+add)@got at dtprel@h */
+#define R_PPC64_GOT_DTPREL16_HA	94 /* half16	(sym+add)@got at dtprel@ha */
+#define R_PPC64_TPREL16_DS	95 /* half16ds*	(sym+add)@tprel */
+#define R_PPC64_TPREL16_LO_DS	96 /* half16ds	(sym+add)@tprel at l */
+#define R_PPC64_TPREL16_HIGHER	97 /* half16	(sym+add)@tprel at higher */
+#define R_PPC64_TPREL16_HIGHERA	98 /* half16	(sym+add)@tprel at highera */
+#define R_PPC64_TPREL16_HIGHEST	99 /* half16	(sym+add)@tprel at highest */
+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16	(sym+add)@tprel at highesta */
+#define R_PPC64_DTPREL16_DS	101 /* half16ds* (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO_DS	102 /* half16ds	(sym+add)@dtprel at l */
+#define R_PPC64_DTPREL16_HIGHER	103 /* half16	(sym+add)@dtprel at higher */
+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel at highera */
+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel at highest */
+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel at highesta */
+
+/* Keep this the last entry.  */
+#define R_PPC64_NUM		107
+
+/* PowerPC64 specific values for the Dyn d_tag field.  */
+#define DT_PPC64_GLINK  (DT_LOPROC + 0)
+#define DT_PPC64_OPD	(DT_LOPROC + 1)
+#define DT_PPC64_OPDSZ	(DT_LOPROC + 2)
+#define DT_PPC64_NUM    3
+
+
+/* ARM specific declarations */
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARM_RELEXEC     0x01
+#define EF_ARM_HASENTRY    0x02
+#define EF_ARM_INTERWORK   0x04
+#define EF_ARM_APCS_26     0x08
+#define EF_ARM_APCS_FLOAT  0x10
+#define EF_ARM_PIC         0x20
+#define EF_ARM_ALIGN8      0x40		/* 8-bit structure alignment is in use */
+#define EF_ARM_NEW_ABI     0x80
+#define EF_ARM_OLD_ABI     0x100
+
+/* Other constants defined in the ARM ELF spec. version B-01.  */
+/* NB. These conflict with values defined above.  */
+#define EF_ARM_SYMSARESORTED	0x04
+#define EF_ARM_DYNSYMSUSESEGIDX 0x08
+#define EF_ARM_MAPSYMSFIRST	0x10
+#define EF_ARM_EABIMASK		0XFF000000
+
+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
+#define EF_ARM_EABI_UNKNOWN  0x00000000
+#define EF_ARM_EABI_VER1     0x01000000
+#define EF_ARM_EABI_VER2     0x02000000
+
+/* Additional symbol types for Thumb */
+#define STT_ARM_TFUNC      0xd
+
+/* ARM-specific values for sh_flags */
+#define SHF_ARM_ENTRYSECT  0x10000000   /* Section contains an entry point */
+#define SHF_ARM_COMDEF     0x80000000   /* Section may be multiply defined
+					   in the input to a link step */
+
+/* ARM-specific program header flags */
+#define PF_ARM_SB          0x10000000   /* Segment contains the location
+					   addressed by the static base */
+
+/* Processor specific values for the Phdr p_type field.  */
+#define PT_ARM_EXIDX	0x70000001	/* .ARM.exidx segment */
+
+/* ARM relocs.  */
+
+#define R_ARM_NONE		0	/* No reloc */
+#define R_ARM_PC24		1	/* PC relative 26 bit branch */
+#define R_ARM_ABS32		2	/* Direct 32 bit  */
+#define R_ARM_REL32		3	/* PC relative 32 bit */
+#define R_ARM_PC13		4
+#define R_ARM_ABS16		5	/* Direct 16 bit */
+#define R_ARM_ABS12		6	/* Direct 12 bit */
+#define R_ARM_THM_ABS5		7
+#define R_ARM_ABS8		8	/* Direct 8 bit */
+#define R_ARM_SBREL32		9
+#define R_ARM_THM_PC22		10
+#define R_ARM_THM_PC8		11
+#define R_ARM_AMP_VCALL9	12
+#define R_ARM_SWI24		13
+#define R_ARM_THM_SWI8		14
+#define R_ARM_XPC25		15
+#define R_ARM_THM_XPC22		16
+#define R_ARM_TLS_DTPMOD32	17	/* ID of module containing symbol */
+#define R_ARM_TLS_DTPOFF32	18	/* Offset in TLS block */
+#define R_ARM_TLS_TPOFF32	19	/* Offset in static TLS block */
+#define R_ARM_COPY		20	/* Copy symbol at runtime */
+#define R_ARM_GLOB_DAT		21	/* Create GOT entry */
+#define R_ARM_JUMP_SLOT		22	/* Create PLT entry */
+#define R_ARM_RELATIVE		23	/* Adjust by program base */
+#define R_ARM_GOTOFF		24	/* 32 bit offset to GOT */
+#define R_ARM_GOTPC		25	/* 32 bit PC relative offset to GOT */
+#define R_ARM_GOT32		26	/* 32 bit GOT entry */
+#define R_ARM_PLT32		27	/* 32 bit PLT address */
+#define R_ARM_ALU_PCREL_7_0	32
+#define R_ARM_ALU_PCREL_15_8	33
+#define R_ARM_ALU_PCREL_23_15	34
+#define R_ARM_LDR_SBREL_11_0	35
+#define R_ARM_ALU_SBREL_19_12	36
+#define R_ARM_ALU_SBREL_27_20	37
+#define R_ARM_GNU_VTENTRY	100
+#define R_ARM_GNU_VTINHERIT	101
+#define R_ARM_THM_PC11		102	/* thumb unconditional branch */
+#define R_ARM_THM_PC9		103	/* thumb conditional branch */
+#define R_ARM_TLS_GD32		104	/* PC-rel 32 bit for global dynamic
+					   thread local data */
+#define R_ARM_TLS_LDM32		105	/* PC-rel 32 bit for local dynamic
+					   thread local data */
+#define R_ARM_TLS_LDO32		106	/* 32 bit offset relative to TLS
+					   block */
+#define R_ARM_TLS_IE32		107	/* PC-rel 32 bit for GOT entry of
+					   static TLS block offset */
+#define R_ARM_TLS_LE32		108	/* 32 bit offset relative to static
+					   TLS block */
+#define R_ARM_RXPC25		249
+#define R_ARM_RSBREL32		250
+#define R_ARM_THM_RPC22		251
+#define R_ARM_RREL32		252
+#define R_ARM_RABS22		253
+#define R_ARM_RPC24		254
+#define R_ARM_RBASE		255
+/* Keep this the last entry.  */
+#define R_ARM_NUM		256
+
+/* IA-64 specific declarations.  */
+
+/* Processor specific flags for the Ehdr e_flags field.  */
+#define EF_IA_64_MASKOS		0x0000000f	/* os-specific flags */
+#define EF_IA_64_ABI64		0x00000010	/* 64-bit ABI */
+#define EF_IA_64_ARCH		0xff000000	/* arch. version mask */
+
+/* Processor specific values for the Phdr p_type field.  */
+#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* arch extension bits */
+#define PT_IA_64_UNWIND		(PT_LOPROC + 1)	/* ia64 unwind bits */
+#define PT_IA_64_HP_OPT_ANOT	(PT_LOOS + 0x12)
+#define PT_IA_64_HP_HSL_ANOT	(PT_LOOS + 0x13)
+#define PT_IA_64_HP_STACK	(PT_LOOS + 0x14)
+
+/* Processor specific flags for the Phdr p_flags field.  */
+#define PF_IA_64_NORECOV	0x80000000	/* spec insns w/o recovery */
+
+/* Processor specific values for the Shdr sh_type field.  */
+#define SHT_IA_64_EXT		(SHT_LOPROC + 0) /* extension bits */
+#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1) /* unwind bits */
+
+/* Processor specific flags for the Shdr sh_flags field.  */
+#define SHF_IA_64_SHORT		0x10000000	/* section near gp */
+#define SHF_IA_64_NORECOV	0x20000000	/* spec insns w/o recovery */
+
+/* Processor specific values for the Dyn d_tag field.  */
+#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
+#define DT_IA_64_NUM		1
+
+/* IA-64 relocations.  */
+#define R_IA64_NONE		0x00	/* none */
+#define R_IA64_IMM14		0x21	/* symbol + addend, add imm14 */
+#define R_IA64_IMM22		0x22	/* symbol + addend, add imm22 */
+#define R_IA64_IMM64		0x23	/* symbol + addend, mov imm64 */
+#define R_IA64_DIR32MSB		0x24	/* symbol + addend, data4 MSB */
+#define R_IA64_DIR32LSB		0x25	/* symbol + addend, data4 LSB */
+#define R_IA64_DIR64MSB		0x26	/* symbol + addend, data8 MSB */
+#define R_IA64_DIR64LSB		0x27	/* symbol + addend, data8 LSB */
+#define R_IA64_GPREL22		0x2a	/* @gprel(sym + add), add imm22 */
+#define R_IA64_GPREL64I		0x2b	/* @gprel(sym + add), mov imm64 */
+#define R_IA64_GPREL32MSB	0x2c	/* @gprel(sym + add), data4 MSB */
+#define R_IA64_GPREL32LSB	0x2d	/* @gprel(sym + add), data4 LSB */
+#define R_IA64_GPREL64MSB	0x2e	/* @gprel(sym + add), data8 MSB */
+#define R_IA64_GPREL64LSB	0x2f	/* @gprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF22		0x32	/* @ltoff(sym + add), add imm22 */
+#define R_IA64_LTOFF64I		0x33	/* @ltoff(sym + add), mov imm64 */
+#define R_IA64_PLTOFF22		0x3a	/* @pltoff(sym + add), add imm22 */
+#define R_IA64_PLTOFF64I	0x3b	/* @pltoff(sym + add), mov imm64 */
+#define R_IA64_PLTOFF64MSB	0x3e	/* @pltoff(sym + add), data8 MSB */
+#define R_IA64_PLTOFF64LSB	0x3f	/* @pltoff(sym + add), data8 LSB */
+#define R_IA64_FPTR64I		0x43	/* @fptr(sym + add), mov imm64 */
+#define R_IA64_FPTR32MSB	0x44	/* @fptr(sym + add), data4 MSB */
+#define R_IA64_FPTR32LSB	0x45	/* @fptr(sym + add), data4 LSB */
+#define R_IA64_FPTR64MSB	0x46	/* @fptr(sym + add), data8 MSB */
+#define R_IA64_FPTR64LSB	0x47	/* @fptr(sym + add), data8 LSB */
+#define R_IA64_PCREL60B		0x48	/* @pcrel(sym + add), brl */
+#define R_IA64_PCREL21B		0x49	/* @pcrel(sym + add), ptb, call */
+#define R_IA64_PCREL21M		0x4a	/* @pcrel(sym + add), chk.s */
+#define R_IA64_PCREL21F		0x4b	/* @pcrel(sym + add), fchkf */
+#define R_IA64_PCREL32MSB	0x4c	/* @pcrel(sym + add), data4 MSB */
+#define R_IA64_PCREL32LSB	0x4d	/* @pcrel(sym + add), data4 LSB */
+#define R_IA64_PCREL64MSB	0x4e	/* @pcrel(sym + add), data8 MSB */
+#define R_IA64_PCREL64LSB	0x4f	/* @pcrel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_FPTR22	0x52	/* @ltoff(@fptr(s+a)), imm22 */
+#define R_IA64_LTOFF_FPTR64I	0x53	/* @ltoff(@fptr(s+a)), imm64 */
+#define R_IA64_LTOFF_FPTR32MSB	0x54	/* @ltoff(@fptr(s+a)), data4 MSB */
+#define R_IA64_LTOFF_FPTR32LSB	0x55	/* @ltoff(@fptr(s+a)), data4 LSB */
+#define R_IA64_LTOFF_FPTR64MSB	0x56	/* @ltoff(@fptr(s+a)), data8 MSB */
+#define R_IA64_LTOFF_FPTR64LSB	0x57	/* @ltoff(@fptr(s+a)), data8 LSB */
+#define R_IA64_SEGREL32MSB	0x5c	/* @segrel(sym + add), data4 MSB */
+#define R_IA64_SEGREL32LSB	0x5d	/* @segrel(sym + add), data4 LSB */
+#define R_IA64_SEGREL64MSB	0x5e	/* @segrel(sym + add), data8 MSB */
+#define R_IA64_SEGREL64LSB	0x5f	/* @segrel(sym + add), data8 LSB */
+#define R_IA64_SECREL32MSB	0x64	/* @secrel(sym + add), data4 MSB */
+#define R_IA64_SECREL32LSB	0x65	/* @secrel(sym + add), data4 LSB */
+#define R_IA64_SECREL64MSB	0x66	/* @secrel(sym + add), data8 MSB */
+#define R_IA64_SECREL64LSB	0x67	/* @secrel(sym + add), data8 LSB */
+#define R_IA64_REL32MSB		0x6c	/* data 4 + REL */
+#define R_IA64_REL32LSB		0x6d	/* data 4 + REL */
+#define R_IA64_REL64MSB		0x6e	/* data 8 + REL */
+#define R_IA64_REL64LSB		0x6f	/* data 8 + REL */
+#define R_IA64_LTV32MSB		0x74	/* symbol + addend, data4 MSB */
+#define R_IA64_LTV32LSB		0x75	/* symbol + addend, data4 LSB */
+#define R_IA64_LTV64MSB		0x76	/* symbol + addend, data8 MSB */
+#define R_IA64_LTV64LSB		0x77	/* symbol + addend, data8 LSB */
+#define R_IA64_PCREL21BI	0x79	/* @pcrel(sym + add), 21bit inst */
+#define R_IA64_PCREL22		0x7a	/* @pcrel(sym + add), 22bit inst */
+#define R_IA64_PCREL64I		0x7b	/* @pcrel(sym + add), 64bit inst */
+#define R_IA64_IPLTMSB		0x80	/* dynamic reloc, imported PLT, MSB */
+#define R_IA64_IPLTLSB		0x81	/* dynamic reloc, imported PLT, LSB */
+#define R_IA64_COPY		0x84	/* copy relocation */
+#define R_IA64_SUB		0x85	/* Addend and symbol difference */
+#define R_IA64_LTOFF22X		0x86	/* LTOFF22, relaxable.  */
+#define R_IA64_LDXMOV		0x87	/* Use of LTOFF22X.  */
+#define R_IA64_TPREL14		0x91	/* @tprel(sym + add), imm14 */
+#define R_IA64_TPREL22		0x92	/* @tprel(sym + add), imm22 */
+#define R_IA64_TPREL64I		0x93	/* @tprel(sym + add), imm64 */
+#define R_IA64_TPREL64MSB	0x96	/* @tprel(sym + add), data8 MSB */
+#define R_IA64_TPREL64LSB	0x97	/* @tprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_TPREL22	0x9a	/* @ltoff(@tprel(s+a)), imm2 */
+#define R_IA64_DTPMOD64MSB	0xa6	/* @dtpmod(sym + add), data8 MSB */
+#define R_IA64_DTPMOD64LSB	0xa7	/* @dtpmod(sym + add), data8 LSB */
+#define R_IA64_LTOFF_DTPMOD22	0xaa	/* @ltoff(@dtpmod(sym + add)), imm22 */
+#define R_IA64_DTPREL14		0xb1	/* @dtprel(sym + add), imm14 */
+#define R_IA64_DTPREL22		0xb2	/* @dtprel(sym + add), imm22 */
+#define R_IA64_DTPREL64I	0xb3	/* @dtprel(sym + add), imm64 */
+#define R_IA64_DTPREL32MSB	0xb4	/* @dtprel(sym + add), data4 MSB */
+#define R_IA64_DTPREL32LSB	0xb5	/* @dtprel(sym + add), data4 LSB */
+#define R_IA64_DTPREL64MSB	0xb6	/* @dtprel(sym + add), data8 MSB */
+#define R_IA64_DTPREL64LSB	0xb7	/* @dtprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_DTPREL22	0xba	/* @ltoff(@dtprel(s+a)), imm22 */
+
+/* SH specific declarations */
+
+/* SH relocs.  */
+#define	R_SH_NONE		0
+#define	R_SH_DIR32		1
+#define	R_SH_REL32		2
+#define	R_SH_DIR8WPN		3
+#define	R_SH_IND12W		4
+#define	R_SH_DIR8WPL		5
+#define	R_SH_DIR8WPZ		6
+#define	R_SH_DIR8BP		7
+#define	R_SH_DIR8W		8
+#define	R_SH_DIR8L		9
+#define	R_SH_SWITCH16		25
+#define	R_SH_SWITCH32		26
+#define	R_SH_USES		27
+#define	R_SH_COUNT		28
+#define	R_SH_ALIGN		29
+#define	R_SH_CODE		30
+#define	R_SH_DATA		31
+#define	R_SH_LABEL		32
+#define	R_SH_SWITCH8		33
+#define	R_SH_GNU_VTINHERIT	34
+#define	R_SH_GNU_VTENTRY	35
+#define	R_SH_TLS_GD_32		144
+#define	R_SH_TLS_LD_32		145
+#define	R_SH_TLS_LDO_32		146
+#define	R_SH_TLS_IE_32		147
+#define	R_SH_TLS_LE_32		148
+#define	R_SH_TLS_DTPMOD32	149
+#define	R_SH_TLS_DTPOFF32	150
+#define	R_SH_TLS_TPOFF32	151
+#define	R_SH_GOT32		160
+#define	R_SH_PLT32		161
+#define	R_SH_COPY		162
+#define	R_SH_GLOB_DAT		163
+#define	R_SH_JMP_SLOT		164
+#define	R_SH_RELATIVE		165
+#define	R_SH_GOTOFF		166
+#define	R_SH_GOTPC		167
+/* Keep this the last entry.  */
+#define	R_SH_NUM		256
+
+/* Additional s390 relocs */
+
+#define R_390_NONE		0	/* No reloc.  */
+#define R_390_8			1	/* Direct 8 bit.  */
+#define R_390_12		2	/* Direct 12 bit.  */
+#define R_390_16		3	/* Direct 16 bit.  */
+#define R_390_32		4	/* Direct 32 bit.  */
+#define R_390_PC32		5	/* PC relative 32 bit.	*/
+#define R_390_GOT12		6	/* 12 bit GOT offset.  */
+#define R_390_GOT32		7	/* 32 bit GOT offset.  */
+#define R_390_PLT32		8	/* 32 bit PC relative PLT address.  */
+#define R_390_COPY		9	/* Copy symbol at runtime.  */
+#define R_390_GLOB_DAT		10	/* Create GOT entry.  */
+#define R_390_JMP_SLOT		11	/* Create PLT entry.  */
+#define R_390_RELATIVE		12	/* Adjust by program base.  */
+#define R_390_GOTOFF32		13	/* 32 bit offset to GOT.	 */
+#define R_390_GOTPC		14	/* 32 bit PC relative offset to GOT.  */
+#define R_390_GOT16		15	/* 16 bit GOT offset.  */
+#define R_390_PC16		16	/* PC relative 16 bit.	*/
+#define R_390_PC16DBL		17	/* PC relative 16 bit shifted by 1.  */
+#define R_390_PLT16DBL		18	/* 16 bit PC rel. PLT shifted by 1.  */
+#define R_390_PC32DBL		19	/* PC relative 32 bit shifted by 1.  */
+#define R_390_PLT32DBL		20	/* 32 bit PC rel. PLT shifted by 1.  */
+#define R_390_GOTPCDBL		21	/* 32 bit PC rel. GOT shifted by 1.  */
+#define R_390_64		22	/* Direct 64 bit.  */
+#define R_390_PC64		23	/* PC relative 64 bit.	*/
+#define R_390_GOT64		24	/* 64 bit GOT offset.  */
+#define R_390_PLT64		25	/* 64 bit PC relative PLT address.  */
+#define R_390_GOTENT		26	/* 32 bit PC rel. to GOT entry >> 1. */
+#define R_390_GOTOFF16		27	/* 16 bit offset to GOT. */
+#define R_390_GOTOFF64		28	/* 64 bit offset to GOT. */
+#define R_390_GOTPLT12		29	/* 12 bit offset to jump slot.	*/
+#define R_390_GOTPLT16		30	/* 16 bit offset to jump slot.	*/
+#define R_390_GOTPLT32		31	/* 32 bit offset to jump slot.	*/
+#define R_390_GOTPLT64		32	/* 64 bit offset to jump slot.	*/
+#define R_390_GOTPLTENT		33	/* 32 bit rel. offset to jump slot.  */
+#define R_390_PLTOFF16		34	/* 16 bit offset from GOT to PLT. */
+#define R_390_PLTOFF32		35	/* 32 bit offset from GOT to PLT. */
+#define R_390_PLTOFF64		36	/* 16 bit offset from GOT to PLT. */
+#define R_390_TLS_LOAD		37	/* Tag for load insn in TLS code.  */
+#define R_390_TLS_GDCALL	38	/* Tag for function call in general
+					   dynamic TLS code. */
+#define R_390_TLS_LDCALL	39	/* Tag for function call in local
+					   dynamic TLS code. */
+#define R_390_TLS_GD32		40	/* Direct 32 bit for general dynamic
+					   thread local data.  */
+#define R_390_TLS_GD64		41	/* Direct 64 bit for general dynamic
+					  thread local data.  */
+#define R_390_TLS_GOTIE12	42	/* 12 bit GOT offset for static TLS
+					   block offset.  */
+#define R_390_TLS_GOTIE32	43	/* 32 bit GOT offset for static TLS
+					   block offset.  */
+#define R_390_TLS_GOTIE64	44	/* 64 bit GOT offset for static TLS
+					   block offset. */
+#define R_390_TLS_LDM32		45	/* Direct 32 bit for local dynamic
+					   thread local data in LE code.  */
+#define R_390_TLS_LDM64		46	/* Direct 64 bit for local dynamic
+					   thread local data in LE code.  */
+#define R_390_TLS_IE32		47	/* 32 bit address of GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_IE64		48	/* 64 bit address of GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_IEENT		49	/* 32 bit rel. offset to GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_LE32		50	/* 32 bit negated offset relative to
+					   static TLS block.  */
+#define R_390_TLS_LE64		51	/* 64 bit negated offset relative to
+					   static TLS block.  */
+#define R_390_TLS_LDO32		52	/* 32 bit offset relative to TLS
+					   block.  */
+#define R_390_TLS_LDO64		53	/* 64 bit offset relative to TLS
+					   block.  */
+#define R_390_TLS_DTPMOD	54	/* ID of module containing symbol.  */
+#define R_390_TLS_DTPOFF	55	/* Offset in TLS block.	 */
+#define R_390_TLS_TPOFF		56	/* Negated offset in static TLS
+					   block.  */
+#define R_390_20		57	/* Direct 20 bit.  */
+#define R_390_GOT20		58	/* 20 bit GOT offset.  */
+#define R_390_GOTPLT20		59	/* 20 bit offset to jump slot.  */
+#define R_390_TLS_GOTIE20	60	/* 20 bit GOT offset for static TLS
+					   block offset.  */
+/* Keep this the last entry.  */
+#define R_390_NUM		61
+
+
+/* CRIS relocations.  */
+#define R_CRIS_NONE		0
+#define R_CRIS_8		1
+#define R_CRIS_16		2
+#define R_CRIS_32		3
+#define R_CRIS_8_PCREL		4
+#define R_CRIS_16_PCREL		5
+#define R_CRIS_32_PCREL		6
+#define R_CRIS_GNU_VTINHERIT	7
+#define R_CRIS_GNU_VTENTRY	8
+#define R_CRIS_COPY		9
+#define R_CRIS_GLOB_DAT		10
+#define R_CRIS_JUMP_SLOT	11
+#define R_CRIS_RELATIVE		12
+#define R_CRIS_16_GOT		13
+#define R_CRIS_32_GOT		14
+#define R_CRIS_16_GOTPLT	15
+#define R_CRIS_32_GOTPLT	16
+#define R_CRIS_32_GOTREL	17
+#define R_CRIS_32_PLT_GOTREL	18
+#define R_CRIS_32_PLT_PCREL	19
+
+#define R_CRIS_NUM		20
+
+
+/* AMD x86-64 relocations.  */
+#define R_X86_64_NONE		0	/* No reloc */
+#define R_X86_64_64		1	/* Direct 64 bit  */
+#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
+#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
+#define R_X86_64_PLT32		4	/* 32 bit PLT address */
+#define R_X86_64_COPY		5	/* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
+#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
+#define R_X86_64_RELATIVE	8	/* Adjust by program base */
+#define R_X86_64_GOTPCREL	9	/* 32 bit signed PC relative
+					   offset to GOT */
+#define R_X86_64_32		10	/* Direct 32 bit zero extended */
+#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
+#define R_X86_64_16		12	/* Direct 16 bit zero extended */
+#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
+#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
+#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
+#define R_X86_64_DTPMOD64	16	/* ID of module containing symbol */
+#define R_X86_64_DTPOFF64	17	/* Offset in module's TLS block */
+#define R_X86_64_TPOFF64	18	/* Offset in initial TLS block */
+#define R_X86_64_TLSGD		19	/* 32 bit signed PC relative offset
+					   to two GOT entries for GD symbol */
+#define R_X86_64_TLSLD		20	/* 32 bit signed PC relative offset
+					   to two GOT entries for LD symbol */
+#define R_X86_64_DTPOFF32	21	/* Offset in TLS block */
+#define R_X86_64_GOTTPOFF	22	/* 32 bit signed PC relative offset
+					   to GOT entry for IE symbol */
+#define R_X86_64_TPOFF32	23	/* Offset in initial TLS block */
+
+#define R_X86_64_NUM		24
+
+
+/* AM33 relocations.  */
+#define R_MN10300_NONE		0	/* No reloc.  */
+#define R_MN10300_32		1	/* Direct 32 bit.  */
+#define R_MN10300_16		2	/* Direct 16 bit.  */
+#define R_MN10300_8		3	/* Direct 8 bit.  */
+#define R_MN10300_PCREL32	4	/* PC-relative 32-bit.  */
+#define R_MN10300_PCREL16	5	/* PC-relative 16-bit signed.  */
+#define R_MN10300_PCREL8	6	/* PC-relative 8-bit signed.  */
+#define R_MN10300_GNU_VTINHERIT	7	/* Ancient C++ vtable garbage... */
+#define R_MN10300_GNU_VTENTRY	8	/* ... collection annotation.  */
+#define R_MN10300_24		9	/* Direct 24 bit.  */
+#define R_MN10300_GOTPC32	10	/* 32-bit PCrel offset to GOT.  */
+#define R_MN10300_GOTPC16	11	/* 16-bit PCrel offset to GOT.  */
+#define R_MN10300_GOTOFF32	12	/* 32-bit offset from GOT.  */
+#define R_MN10300_GOTOFF24	13	/* 24-bit offset from GOT.  */
+#define R_MN10300_GOTOFF16	14	/* 16-bit offset from GOT.  */
+#define R_MN10300_PLT32		15	/* 32-bit PCrel to PLT entry.  */
+#define R_MN10300_PLT16		16	/* 16-bit PCrel to PLT entry.  */
+#define R_MN10300_GOT32		17	/* 32-bit offset to GOT entry.  */
+#define R_MN10300_GOT24		18	/* 24-bit offset to GOT entry.  */
+#define R_MN10300_GOT16		19	/* 16-bit offset to GOT entry.  */
+#define R_MN10300_COPY		20	/* Copy symbol at runtime.  */
+#define R_MN10300_GLOB_DAT	21	/* Create GOT entry.  */
+#define R_MN10300_JMP_SLOT	22	/* Create PLT entry.  */
+#define R_MN10300_RELATIVE	23	/* Adjust by program base.  */
+
+#define R_MN10300_NUM		24
+
+
+/* M32R relocs.  */
+#define R_M32R_NONE		0	/* No reloc. */
+#define R_M32R_16		1	/* Direct 16 bit. */
+#define R_M32R_32		2	/* Direct 32 bit. */
+#define R_M32R_24		3	/* Direct 24 bit. */
+#define R_M32R_10_PCREL		4	/* PC relative 10 bit shifted. */
+#define R_M32R_18_PCREL		5	/* PC relative 18 bit shifted. */
+#define R_M32R_26_PCREL		6	/* PC relative 26 bit shifted. */
+#define R_M32R_HI16_ULO		7	/* High 16 bit with unsigned low. */
+#define R_M32R_HI16_SLO		8	/* High 16 bit with signed low. */
+#define R_M32R_LO16		9	/* Low 16 bit. */
+#define R_M32R_SDA16		10	/* 16 bit offset in SDA. */
+#define R_M32R_GNU_VTINHERIT	11
+#define R_M32R_GNU_VTENTRY	12
+/* M32R relocs use SHT_RELA.  */
+#define R_M32R_16_RELA		33	/* Direct 16 bit. */
+#define R_M32R_32_RELA		34	/* Direct 32 bit. */
+#define R_M32R_24_RELA		35	/* Direct 24 bit. */
+#define R_M32R_10_PCREL_RELA	36	/* PC relative 10 bit shifted. */
+#define R_M32R_18_PCREL_RELA	37	/* PC relative 18 bit shifted. */
+#define R_M32R_26_PCREL_RELA	38	/* PC relative 26 bit shifted. */
+#define R_M32R_HI16_ULO_RELA	39	/* High 16 bit with unsigned low */
+#define R_M32R_HI16_SLO_RELA	40	/* High 16 bit with signed low */
+#define R_M32R_LO16_RELA	41	/* Low 16 bit */
+#define R_M32R_SDA16_RELA	42	/* 16 bit offset in SDA */
+#define R_M32R_RELA_GNU_VTINHERIT	43
+#define R_M32R_RELA_GNU_VTENTRY	44
+#define R_M32R_REL32		45	/* PC relative 32 bit.  */
+
+#define R_M32R_GOT24		48	/* 24 bit GOT entry */
+#define R_M32R_26_PLTREL	49	/* 26 bit PC relative to PLT shifted */
+#define R_M32R_COPY		50	/* Copy symbol at runtime */
+#define R_M32R_GLOB_DAT		51	/* Create GOT entry */
+#define R_M32R_JMP_SLOT		52	/* Create PLT entry */
+#define R_M32R_RELATIVE		53	/* Adjust by program base */
+#define R_M32R_GOTOFF		54	/* 24 bit offset to GOT */
+#define R_M32R_GOTPC24		55	/* 24 bit PC relative offset to GOT */
+#define R_M32R_GOT16_HI_ULO	56	/* High 16 bit GOT entry with unsigned
+					   low */
+#define R_M32R_GOT16_HI_SLO	57	/* High 16 bit GOT entry with signed
+					   low */
+#define R_M32R_GOT16_LO		58	/* Low 16 bit GOT entry */
+#define R_M32R_GOTPC_HI_ULO	59	/* High 16 bit PC relative offset to
+					   GOT with unsigned low */
+#define R_M32R_GOTPC_HI_SLO	60	/* High 16 bit PC relative offset to
+					   GOT with signed low */
+#define R_M32R_GOTPC_LO		61	/* Low 16 bit PC relative offset to
+					   GOT */
+#define R_M32R_GOTOFF_HI_ULO	62	/* High 16 bit offset to GOT
+					   with unsigned low */
+#define R_M32R_GOTOFF_HI_SLO	63	/* High 16 bit offset to GOT
+					   with signed low */
+#define R_M32R_GOTOFF_LO	64	/* Low 16 bit offset to GOT */
+#define R_M32R_NUM		256	/* Keep this the last entry. */
+
+
+#endif	/* elf.h */

Modified: coreboot-v3/util/lar/stream.c
===================================================================
--- coreboot-v3/util/lar/stream.c	2008-03-27 23:56:36 UTC (rev 647)
+++ coreboot-v3/util/lar/stream.c	2008-04-04 03:29:26 UTC (rev 648)
@@ -32,8 +32,8 @@
 #include <sys/mman.h>
 #include <netinet/in.h>
 #include <libgen.h>
-#include <elf.h>
 
+#include "elf.h"
 #include "lar.h"
 #include "lib.h"
 




From svn at coreboot.org  Fri Apr  4 05:31:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 05:31:40 +0200
Subject: [coreboot] r649 - in coreboot-v3: mainboard/artecgroup/dbe62
	northbridge/amd/geodelx southbridge/amd/cs5536
Message-ID: <mailman.1363.1355071295.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-04-04 05:31:39 +0200 (Fri, 04 Apr 2008)
New Revision: 649

Modified:
   coreboot-v3/mainboard/artecgroup/dbe62/initram.c
   coreboot-v3/northbridge/amd/geodelx/raminit.c
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
Log:
With this set of changes dbe62 gets to a FILO prompt.

Set manual settings for dbe62 PLL; the auto settings are giving
slightly wrong values

Add call to dumplxmsr in dbe62 initram main()

Change dumplxmsr to void parameter

Add dumplxmsrs function to geodelx raminit support code

Correct spelling of CAS.

The big one: set spd variables correctly.

The not so big one: there is a bug in com2 enable I don't understand.
For now comment out two offending lines. The cs5536 debug prints
should be reduced later.

Change fuctory to factory. It's funny but confusing.
This patch also takes into account carl-daniel and uwe's comments.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2008-04-04 03:29:26 UTC (rev 648)
+++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2008-04-04 03:31:39 UTC (rev 649)
@@ -33,9 +33,9 @@
 #include <northbridge/amd/geodelx/raminit.h>
 #include <spd.h>
 
-#define MANUALCONF 0		/* Do automatic strapped PLL config */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
-#define PLLMSRLO 0x02000030
+#define MANUALCONF 1		/* Do manual strapped PLL config */
+#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
+#define PLLMSRLO 0x07de0080	/* from factory bios */
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)
 
@@ -53,25 +53,23 @@
 
 /* Save space by using a short list of SPD values used by Geode LX Memory init */
 static const struct spd_entry spd_table[] = {
-	{SPD_ACCEPTABLE_CAS_LATENCIES, 0xe},
-	{SPD_BANK_DENSITY, 0x40},
-	{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
 	{SPD_MEMORY_TYPE, 7},
-	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
-	{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
-	{SPD_NUM_BANKS_PER_SDRAM, 4},
-	{SPD_PRIMARY_SDRAM_WIDTH, 8},
-	{SPD_NUM_DIMM_BANKS, 1},
-	{SPD_NUM_COLUMNS, 0xa},
 	{SPD_NUM_ROWS, 13},
-	{SPD_REFRESH, 0x3a},
-	{SPD_SDRAM_CYCLE_TIME_2ND, 60},
-	{SPD_SDRAM_CYCLE_TIME_3RD, 75},
-	{SPD_tRAS, 40},
+	{SPD_tRFC, 0x4b},
+	{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
+	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40},
+	{SPD_tRAS, 0x2d},
+	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
+	{SPD_MIN_RAS_TO_CAS_DELAY, 0x58},
+	{SPD_tRRD, 0x3c},
+	{SPD_tRP, 0x58},
+	{SPD_NUM_BANKS_PER_SDRAM, 0x4},
+	{SPD_NUM_COLUMNS, 0x8},
+	{SPD_NUM_DIMM_BANKS, 0x1},
+	{SPD_REFRESH, 0x82},
+	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
+	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
 	{SPD_tRCD, 15},
-	{SPD_tRFC, 70},
-	{SPD_tRP, 15},
-	{SPD_tRRD, 10},
 };
 
 /**
@@ -124,6 +122,8 @@
   */
 int main(void)
 {
+	void dumplxmsrs(void);
+
 	u8 smb_devices[] =  {
 		DIMM0, DIMM1
 	};
@@ -151,8 +151,12 @@
 	sdram_enable(DIMM0, DIMM1);
 	printk(BIOS_DEBUG, "done sdram enable\n");
 
+	dumplxmsrs();
 	/* Check low memory */
-	ram_check(0x00000000, 640*1024);
+	/* The RAM is working now. Leave this test commented out but
+	 * here for reference. 
+	 * Note that the range 0x87000 will fail; that's the stack! */
+	/*	ram_check(0x00000000, 640*1024);*/
 
 	printk(BIOS_DEBUG, "stage1 returns\n");
 	return 0;

Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-04-04 03:29:26 UTC (rev 648)
+++ coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-04-04 03:31:39 UTC (rev 649)
@@ -35,6 +35,42 @@
 
 u8 spd_read_byte(u16 device, u8 address);
 
+
+/** 
+ * Dump key MSR values for RAM init. You can call this function and then use it to 
+ * compare to a factory BIOS setting.
+ * @param level printk level
+ */
+
+void dumplxmsrs(void)
+{
+	const static unsigned long msrs[] = {
+        	MC_CF07_DATA, 
+        	MC_CF8F_DATA, 
+        	MC_CF1017_DATA, 
+        	GLCP_DELAY_CONTROLS, 
+        	MC_CFCLK_DBUG, 
+        	MC_CF_PMCTR,
+		GLCP_SYS_RSTPLL
+	};
+	const static char *msrnames[] = {
+        	"MC_CF07_DATA", 
+        	"MC_CF8F_DATA", 
+        	"MC_CF1017_DATA", 
+        	"GLCP_DELAY_CONTROLS", 
+        	"MC_CFCLK_DBUG", 
+        	"MC_CF_PMCTR",
+		"PLL reg"
+	};
+	int i;
+
+	for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){
+		struct msr msr;
+		msr = rdmsr(msrs[i]);
+		printk(BIOS_DEBUG, "(%lx): %x.%x\n",  msrs[i], msr.hi, msr.lo);
+	}
+
+}
 /**
  * Halt and Catch Fire. Print an error, then loop, sending NULLs on
  * serial port, to ensure the message is visible.
@@ -387,7 +423,7 @@
 		hlt();
 	}
 
-	printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
+	printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
 	msr = rdmsr(MC_CF8F_DATA);
 	msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
 	msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;

Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-04-04 03:29:26 UTC (rev 648)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-04-04 03:31:39 UTC (rev 649)
@@ -258,6 +258,7 @@
 
 	/* COM1 */
 	if (sb->com1_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable COM1\n");
 		/* Set the address. */
 		switch (sb->com1_address) {
 		case 0x3F8:
@@ -308,6 +309,7 @@
 		wrmsr(MDD_UART1_CONF, msr);
 	} else {
 		/* Reset and disable COM1. */
+		printk(BIOS_SPEW, "uarts_init: disable COM1\n");
 		msr = rdmsr(MDD_UART1_CONF);
 		msr.lo = 1;			/* Reset */
 		wrmsr(MDD_UART1_CONF, msr);
@@ -322,6 +324,7 @@
 
 	/* COM2 */
 	if (sb->com2_enable) {
+		printk(BIOS_SPEW, "uarts_init: enable COM2\n");
 		switch (sb->com2_address) {
 		case 0x3F8:
 			addr = 7;
@@ -348,14 +351,20 @@
 		/* GPIO3 - UART2_RX */
 		/* Set: Output Enable (0x4) */
 		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+
 		/* Set: OUTAUX1 Select (0x10) */
 		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
 
 		/* GPIO4 - UART2_TX */
 		/* Set: Input Enable (0x20) */
 		outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+
 		/* Set: INAUX1 Select (0x34) */
-		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
+		/* this totally disables com2 for serial, leave it out until we can
+		 * figure it out
+		 */
+//		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT);
+//		printk(BIOS_SPEW, "uarts_init: set INAUX2 for COM2\n");
 
 		/* Set: GPIO 3 + 3 Pull Up (0x18) */
 		outl(GPIOL_3_SET | GPIOL_4_SET,
@@ -369,7 +378,9 @@
 		msr.lo = (1 << 4) | (1 << 1);
 		msr.hi = 0;
 		wrmsr(MDD_UART2_CONF, msr);
+		printk(BIOS_SPEW, "uarts_init: COM2 enabled\n");
 	} else {
+		printk(BIOS_SPEW, "uarts_init: disable COM2\n");
 		/* Reset and disable COM2. */
 		msr = rdmsr(MDD_UART2_CONF);
 		msr.lo = 1;			/* Reset */
@@ -621,10 +632,13 @@
 	uarts_init(sb);
 
 	if (sb->enable_gpio_int_route) {
+		printk(BIOS_SPEW, "cs5536: call vr_write\n");
 		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
 			 (sb->enable_gpio_int_route & 0xFFFF));
+		printk(BIOS_SPEW, "cs5536: done first call vr_write\n");
 		vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
 			 (sb->enable_gpio_int_route >> 16));
+		printk(BIOS_SPEW, "cs5536: done second call vr_write\n");
 	}
 
 	printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n",




From svn at coreboot.org  Fri Apr  4 05:33:08 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 05:33:08 +0200
Subject: [coreboot] r650 - in coreboot-v3: arch/x86 device include/device
	util/lar
Message-ID: <mailman.1364.1355071295.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-04-04 05:33:08 +0200 (Fri, 04 Apr 2008)
New Revision: 650

Removed:
   coreboot-v3/util/lar/elf.h
Modified:
   coreboot-v3/arch/x86/stage0_i586.S
   coreboot-v3/device/device.c
   coreboot-v3/include/device/device.h
   coreboot-v3/util/lar/stream.c
Log:
Undo the other patches that sneaked in in my last commit.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: coreboot-v3/arch/x86/stage0_i586.S
===================================================================
--- coreboot-v3/arch/x86/stage0_i586.S	2008-04-04 03:31:39 UTC (rev 649)
+++ coreboot-v3/arch/x86/stage0_i586.S	2008-04-04 03:33:08 UTC (rev 650)
@@ -297,20 +297,20 @@
  *   register we want to use for CAR.
  * reg is the register where the IO type should be stored.
  */
-.macro extractmask size_segs, reg
-.if \size_segs <= 0
+.macro extractmask segs, reg
+.if \segs <= 0
 	/* The xorl here is superfluous because at the point of first execution
 	 * of this macro, %eax and %edx are cleared. Later invocations of this
-	 * macro will have a monotonically increasing size_segs parameter.
+	 * macro will have a monotonically increasing segs parameter.
 	 */
 	xorl \reg, \reg
-.elseif \size_segs == 0x1000
+.elseif \segs == 1
 	movl $0x06000000, \reg
-.elseif \size_segs == 0x2000
+.elseif \segs == 2
 	movl $0x06060000, \reg
-.elseif \size_segs == 0x3000
+.elseif \segs == 3
 	movl $0x06060600, \reg
-.elseif \size_segs >= 0x4000
+.elseif \segs >= 4
 	movl $0x06060606, \reg
 .endif
 .endm
@@ -319,8 +319,8 @@
  * windowoffset is the 32k-aligned window into CAR size
  */
 .macro simplemask carsize, windowoffset
-	extractmask ((( \carsize - \windowoffset ) ) - 0x4000 ), %eax
-	extractmask ((( \carsize - \windowoffset ) ) ), %edx
+	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
+	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
 .endm
 
 #if CacheSize > 0x10000

Modified: coreboot-v3/device/device.c
===================================================================
--- coreboot-v3/device/device.c	2008-04-04 03:31:39 UTC (rev 649)
+++ coreboot-v3/device/device.c	2008-04-04 03:33:08 UTC (rev 650)
@@ -130,7 +130,6 @@
 			printk(BIOS_SPEW, "%s: match\n", __func__);
 			return c;
 		}
-		printk(BIOS_SPEW, "no more constructors\n");
 	}
 
 	return NULL;

Modified: coreboot-v3/include/device/device.h
===================================================================
--- coreboot-v3/include/device/device.h	2008-04-04 03:31:39 UTC (rev 649)
+++ coreboot-v3/include/device/device.h	2008-04-04 03:33:08 UTC (rev 650)
@@ -231,7 +231,7 @@
 	/* number of buses attached to the device */
 	unsigned int links;
 
-	const struct device_operations *ops;
+	struct device_operations *ops;
 	void *device_configuration;
 };
 

Deleted: coreboot-v3/util/lar/elf.h
===================================================================
--- coreboot-v3/util/lar/elf.h	2008-04-04 03:31:39 UTC (rev 649)
+++ coreboot-v3/util/lar/elf.h	2008-04-04 03:33:08 UTC (rev 650)
@@ -1,2637 +0,0 @@
-/* This file defines standard ELF types, structures, and macros.
-   Copyright (C) 1995-2003,2004,2005,2006,2007 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
-
-   The GNU C Library is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Lesser General Public
-   License as published by the Free Software Foundation; either
-   version 2.1 of the License, or (at your option) any later version.
-
-   The GNU C Library is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   Lesser General Public License for more details.
-
-   You should have received a copy of the GNU Lesser General Public
-   License along with the GNU C Library; if not, write to the Free
-   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-   02111-1307 USA.  */
-
-#ifndef _ELF_H
-#define	_ELF_H 1
-
-#include <stdint.h>
-
-/* Type for a 16-bit quantity.  */
-typedef uint16_t Elf32_Half;
-typedef uint16_t Elf64_Half;
-
-/* Types for signed and unsigned 32-bit quantities.  */
-typedef uint32_t Elf32_Word;
-typedef	int32_t  Elf32_Sword;
-typedef uint32_t Elf64_Word;
-typedef	int32_t  Elf64_Sword;
-
-/* Types for signed and unsigned 64-bit quantities.  */
-typedef uint64_t Elf32_Xword;
-typedef	int64_t  Elf32_Sxword;
-typedef uint64_t Elf64_Xword;
-typedef	int64_t  Elf64_Sxword;
-
-/* Type of addresses.  */
-typedef uint32_t Elf32_Addr;
-typedef uint64_t Elf64_Addr;
-
-/* Type of file offsets.  */
-typedef uint32_t Elf32_Off;
-typedef uint64_t Elf64_Off;
-
-/* Type for section indices, which are 16-bit quantities.  */
-typedef uint16_t Elf32_Section;
-typedef uint16_t Elf64_Section;
-
-/* Type for version symbol information.  */
-typedef Elf32_Half Elf32_Versym;
-typedef Elf64_Half Elf64_Versym;
-
-
-/* The ELF file header.  This appears at the start of every ELF file.  */
-
-#define EI_NIDENT (16)
-
-typedef struct
-{
-  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
-  Elf32_Half	e_type;			/* Object file type */
-  Elf32_Half	e_machine;		/* Architecture */
-  Elf32_Word	e_version;		/* Object file version */
-  Elf32_Addr	e_entry;		/* Entry point virtual address */
-  Elf32_Off	e_phoff;		/* Program header table file offset */
-  Elf32_Off	e_shoff;		/* Section header table file offset */
-  Elf32_Word	e_flags;		/* Processor-specific flags */
-  Elf32_Half	e_ehsize;		/* ELF header size in bytes */
-  Elf32_Half	e_phentsize;		/* Program header table entry size */
-  Elf32_Half	e_phnum;		/* Program header table entry count */
-  Elf32_Half	e_shentsize;		/* Section header table entry size */
-  Elf32_Half	e_shnum;		/* Section header table entry count */
-  Elf32_Half	e_shstrndx;		/* Section header string table index */
-} Elf32_Ehdr;
-
-typedef struct
-{
-  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
-  Elf64_Half	e_type;			/* Object file type */
-  Elf64_Half	e_machine;		/* Architecture */
-  Elf64_Word	e_version;		/* Object file version */
-  Elf64_Addr	e_entry;		/* Entry point virtual address */
-  Elf64_Off	e_phoff;		/* Program header table file offset */
-  Elf64_Off	e_shoff;		/* Section header table file offset */
-  Elf64_Word	e_flags;		/* Processor-specific flags */
-  Elf64_Half	e_ehsize;		/* ELF header size in bytes */
-  Elf64_Half	e_phentsize;		/* Program header table entry size */
-  Elf64_Half	e_phnum;		/* Program header table entry count */
-  Elf64_Half	e_shentsize;		/* Section header table entry size */
-  Elf64_Half	e_shnum;		/* Section header table entry count */
-  Elf64_Half	e_shstrndx;		/* Section header string table index */
-} Elf64_Ehdr;
-
-/* Fields in the e_ident array.  The EI_* macros are indices into the
-   array.  The macros under each EI_* macro are the values the byte
-   may have.  */
-
-#define EI_MAG0		0		/* File identification byte 0 index */
-#define ELFMAG0		0x7f		/* Magic number byte 0 */
-
-#define EI_MAG1		1		/* File identification byte 1 index */
-#define ELFMAG1		'E'		/* Magic number byte 1 */
-
-#define EI_MAG2		2		/* File identification byte 2 index */
-#define ELFMAG2		'L'		/* Magic number byte 2 */
-
-#define EI_MAG3		3		/* File identification byte 3 index */
-#define ELFMAG3		'F'		/* Magic number byte 3 */
-
-/* Conglomeration of the identification bytes, for easy testing as a word.  */
-#define	ELFMAG		"\177ELF"
-#define	SELFMAG		4
-
-#define EI_CLASS	4		/* File class byte index */
-#define ELFCLASSNONE	0		/* Invalid class */
-#define ELFCLASS32	1		/* 32-bit objects */
-#define ELFCLASS64	2		/* 64-bit objects */
-#define ELFCLASSNUM	3
-
-#define EI_DATA		5		/* Data encoding byte index */
-#define ELFDATANONE	0		/* Invalid data encoding */
-#define ELFDATA2LSB	1		/* 2's complement, little endian */
-#define ELFDATA2MSB	2		/* 2's complement, big endian */
-#define ELFDATANUM	3
-
-#define EI_VERSION	6		/* File version byte index */
-					/* Value must be EV_CURRENT */
-
-#define EI_OSABI	7		/* OS ABI identification */
-#define ELFOSABI_NONE		0	/* UNIX System V ABI */
-#define ELFOSABI_SYSV		0	/* Alias.  */
-#define ELFOSABI_HPUX		1	/* HP-UX */
-#define ELFOSABI_NETBSD		2	/* NetBSD.  */
-#define ELFOSABI_LINUX		3	/* Linux.  */
-#define ELFOSABI_SOLARIS	6	/* Sun Solaris.  */
-#define ELFOSABI_AIX		7	/* IBM AIX.  */
-#define ELFOSABI_IRIX		8	/* SGI Irix.  */
-#define ELFOSABI_FREEBSD	9	/* FreeBSD.  */
-#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX.  */
-#define ELFOSABI_MODESTO	11	/* Novell Modesto.  */
-#define ELFOSABI_OPENBSD	12	/* OpenBSD.  */
-#define ELFOSABI_ARM		97	/* ARM */
-#define ELFOSABI_STANDALONE	255	/* Standalone (embedded) application */
-
-#define EI_ABIVERSION	8		/* ABI version */
-
-#define EI_PAD		9		/* Byte index of padding bytes */
-
-/* Legal values for e_type (object file type).  */
-
-#define ET_NONE		0		/* No file type */
-#define ET_REL		1		/* Relocatable file */
-#define ET_EXEC		2		/* Executable file */
-#define ET_DYN		3		/* Shared object file */
-#define ET_CORE		4		/* Core file */
-#define	ET_NUM		5		/* Number of defined types */
-#define ET_LOOS		0xfe00		/* OS-specific range start */
-#define ET_HIOS		0xfeff		/* OS-specific range end */
-#define ET_LOPROC	0xff00		/* Processor-specific range start */
-#define ET_HIPROC	0xffff		/* Processor-specific range end */
-
-/* Legal values for e_machine (architecture).  */
-
-#define EM_NONE		 0		/* No machine */
-#define EM_M32		 1		/* AT&T WE 32100 */
-#define EM_SPARC	 2		/* SUN SPARC */
-#define EM_386		 3		/* Intel 80386 */
-#define EM_68K		 4		/* Motorola m68k family */
-#define EM_88K		 5		/* Motorola m88k family */
-#define EM_860		 7		/* Intel 80860 */
-#define EM_MIPS		 8		/* MIPS R3000 big-endian */
-#define EM_S370		 9		/* IBM System/370 */
-#define EM_MIPS_RS3_LE	10		/* MIPS R3000 little-endian */
-
-#define EM_PARISC	15		/* HPPA */
-#define EM_VPP500	17		/* Fujitsu VPP500 */
-#define EM_SPARC32PLUS	18		/* Sun's "v8plus" */
-#define EM_960		19		/* Intel 80960 */
-#define EM_PPC		20		/* PowerPC */
-#define EM_PPC64	21		/* PowerPC 64-bit */
-#define EM_S390		22		/* IBM S390 */
-
-#define EM_V800		36		/* NEC V800 series */
-#define EM_FR20		37		/* Fujitsu FR20 */
-#define EM_RH32		38		/* TRW RH-32 */
-#define EM_RCE		39		/* Motorola RCE */
-#define EM_ARM		40		/* ARM */
-#define EM_FAKE_ALPHA	41		/* Digital Alpha */
-#define EM_SH		42		/* Hitachi SH */
-#define EM_SPARCV9	43		/* SPARC v9 64-bit */
-#define EM_TRICORE	44		/* Siemens Tricore */
-#define EM_ARC		45		/* Argonaut RISC Core */
-#define EM_H8_300	46		/* Hitachi H8/300 */
-#define EM_H8_300H	47		/* Hitachi H8/300H */
-#define EM_H8S		48		/* Hitachi H8S */
-#define EM_H8_500	49		/* Hitachi H8/500 */
-#define EM_IA_64	50		/* Intel Merced */
-#define EM_MIPS_X	51		/* Stanford MIPS-X */
-#define EM_COLDFIRE	52		/* Motorola Coldfire */
-#define EM_68HC12	53		/* Motorola M68HC12 */
-#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
-#define EM_PCP		55		/* Siemens PCP */
-#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
-#define EM_NDR1		57		/* Denso NDR1 microprocessor */
-#define EM_STARCORE	58		/* Motorola Start*Core processor */
-#define EM_ME16		59		/* Toyota ME16 processor */
-#define EM_ST100	60		/* STMicroelectronic ST100 processor */
-#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
-#define EM_X86_64	62		/* AMD x86-64 architecture */
-#define EM_PDSP		63		/* Sony DSP Processor */
-
-#define EM_FX66		66		/* Siemens FX66 microcontroller */
-#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
-#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
-#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
-#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
-#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
-#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
-#define EM_SVX		73		/* Silicon Graphics SVx */
-#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
-#define EM_VAX		75		/* Digital VAX */
-#define EM_CRIS		76		/* Axis Communications 32-bit embedded processor */
-#define EM_JAVELIN	77		/* Infineon Technologies 32-bit embedded processor */
-#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
-#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
-#define EM_MMIX		80		/* Donald Knuth's educational 64-bit processor */
-#define EM_HUANY	81		/* Harvard University machine-independent object files */
-#define EM_PRISM	82		/* SiTera Prism */
-#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
-#define EM_FR30		84		/* Fujitsu FR30 */
-#define EM_D10V		85		/* Mitsubishi D10V */
-#define EM_D30V		86		/* Mitsubishi D30V */
-#define EM_V850		87		/* NEC v850 */
-#define EM_M32R		88		/* Mitsubishi M32R */
-#define EM_MN10300	89		/* Matsushita MN10300 */
-#define EM_MN10200	90		/* Matsushita MN10200 */
-#define EM_PJ		91		/* picoJava */
-#define EM_OPENRISC	92		/* OpenRISC 32-bit embedded processor */
-#define EM_ARC_A5	93		/* ARC Cores Tangent-A5 */
-#define EM_XTENSA	94		/* Tensilica Xtensa Architecture */
-#define EM_NUM		95
-
-/* If it is necessary to assign new unofficial EM_* values, please
-   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
-   chances of collision with official or non-GNU unofficial values.  */
-
-#define EM_ALPHA	0x9026
-
-/* Legal values for e_version (version).  */
-
-#define EV_NONE		0		/* Invalid ELF version */
-#define EV_CURRENT	1		/* Current version */
-#define EV_NUM		2
-
-/* Section header.  */
-
-typedef struct
-{
-  Elf32_Word	sh_name;		/* Section name (string tbl index) */
-  Elf32_Word	sh_type;		/* Section type */
-  Elf32_Word	sh_flags;		/* Section flags */
-  Elf32_Addr	sh_addr;		/* Section virtual addr at execution */
-  Elf32_Off	sh_offset;		/* Section file offset */
-  Elf32_Word	sh_size;		/* Section size in bytes */
-  Elf32_Word	sh_link;		/* Link to another section */
-  Elf32_Word	sh_info;		/* Additional section information */
-  Elf32_Word	sh_addralign;		/* Section alignment */
-  Elf32_Word	sh_entsize;		/* Entry size if section holds table */
-} Elf32_Shdr;
-
-typedef struct
-{
-  Elf64_Word	sh_name;		/* Section name (string tbl index) */
-  Elf64_Word	sh_type;		/* Section type */
-  Elf64_Xword	sh_flags;		/* Section flags */
-  Elf64_Addr	sh_addr;		/* Section virtual addr at execution */
-  Elf64_Off	sh_offset;		/* Section file offset */
-  Elf64_Xword	sh_size;		/* Section size in bytes */
-  Elf64_Word	sh_link;		/* Link to another section */
-  Elf64_Word	sh_info;		/* Additional section information */
-  Elf64_Xword	sh_addralign;		/* Section alignment */
-  Elf64_Xword	sh_entsize;		/* Entry size if section holds table */
-} Elf64_Shdr;
-
-/* Special section indices.  */
-
-#define SHN_UNDEF	0		/* Undefined section */
-#define SHN_LORESERVE	0xff00		/* Start of reserved indices */
-#define SHN_LOPROC	0xff00		/* Start of processor-specific */
-#define SHN_BEFORE	0xff00		/* Order section before all others
-					   (Solaris).  */
-#define SHN_AFTER	0xff01		/* Order section after all others
-					   (Solaris).  */
-#define SHN_HIPROC	0xff1f		/* End of processor-specific */
-#define SHN_LOOS	0xff20		/* Start of OS-specific */
-#define SHN_HIOS	0xff3f		/* End of OS-specific */
-#define SHN_ABS		0xfff1		/* Associated symbol is absolute */
-#define SHN_COMMON	0xfff2		/* Associated symbol is common */
-#define SHN_XINDEX	0xffff		/* Index is in extra table.  */
-#define SHN_HIRESERVE	0xffff		/* End of reserved indices */
-
-/* Legal values for sh_type (section type).  */
-
-#define SHT_NULL	  0		/* Section header table entry unused */
-#define SHT_PROGBITS	  1		/* Program data */
-#define SHT_SYMTAB	  2		/* Symbol table */
-#define SHT_STRTAB	  3		/* String table */
-#define SHT_RELA	  4		/* Relocation entries with addends */
-#define SHT_HASH	  5		/* Symbol hash table */
-#define SHT_DYNAMIC	  6		/* Dynamic linking information */
-#define SHT_NOTE	  7		/* Notes */
-#define SHT_NOBITS	  8		/* Program space with no data (bss) */
-#define SHT_REL		  9		/* Relocation entries, no addends */
-#define SHT_SHLIB	  10		/* Reserved */
-#define SHT_DYNSYM	  11		/* Dynamic linker symbol table */
-#define SHT_INIT_ARRAY	  14		/* Array of constructors */
-#define SHT_FINI_ARRAY	  15		/* Array of destructors */
-#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
-#define SHT_GROUP	  17		/* Section group */
-#define SHT_SYMTAB_SHNDX  18		/* Extended section indeces */
-#define	SHT_NUM		  19		/* Number of defined types.  */
-#define SHT_LOOS	  0x60000000	/* Start OS-specific.  */
-#define SHT_GNU_HASH	  0x6ffffff6	/* GNU-style hash table.  */
-#define SHT_GNU_LIBLIST	  0x6ffffff7	/* Prelink library list */
-#define SHT_CHECKSUM	  0x6ffffff8	/* Checksum for DSO content.  */
-#define SHT_LOSUNW	  0x6ffffffa	/* Sun-specific low bound.  */
-#define SHT_SUNW_move	  0x6ffffffa
-#define SHT_SUNW_COMDAT   0x6ffffffb
-#define SHT_SUNW_syminfo  0x6ffffffc
-#define SHT_GNU_verdef	  0x6ffffffd	/* Version definition section.  */
-#define SHT_GNU_verneed	  0x6ffffffe	/* Version needs section.  */
-#define SHT_GNU_versym	  0x6fffffff	/* Version symbol table.  */
-#define SHT_HISUNW	  0x6fffffff	/* Sun-specific high bound.  */
-#define SHT_HIOS	  0x6fffffff	/* End OS-specific type */
-#define SHT_LOPROC	  0x70000000	/* Start of processor-specific */
-#define SHT_HIPROC	  0x7fffffff	/* End of processor-specific */
-#define SHT_LOUSER	  0x80000000	/* Start of application-specific */
-#define SHT_HIUSER	  0x8fffffff	/* End of application-specific */
-
-/* Legal values for sh_flags (section flags).  */
-
-#define SHF_WRITE	     (1 << 0)	/* Writable */
-#define SHF_ALLOC	     (1 << 1)	/* Occupies memory during execution */
-#define SHF_EXECINSTR	     (1 << 2)	/* Executable */
-#define SHF_MERGE	     (1 << 4)	/* Might be merged */
-#define SHF_STRINGS	     (1 << 5)	/* Contains nul-terminated strings */
-#define SHF_INFO_LINK	     (1 << 6)	/* `sh_info' contains SHT index */
-#define SHF_LINK_ORDER	     (1 << 7)	/* Preserve order after combining */
-#define SHF_OS_NONCONFORMING (1 << 8)	/* Non-standard OS specific handling
-					   required */
-#define SHF_GROUP	     (1 << 9)	/* Section is member of a group.  */
-#define SHF_TLS		     (1 << 10)	/* Section hold thread-local data.  */
-#define SHF_MASKOS	     0x0ff00000	/* OS-specific.  */
-#define SHF_MASKPROC	     0xf0000000	/* Processor-specific */
-#define SHF_ORDERED	     (1 << 30)	/* Special ordering requirement
-					   (Solaris).  */
-#define SHF_EXCLUDE	     (1 << 31)	/* Section is excluded unless
-					   referenced or allocated (Solaris).*/
-
-/* Section group handling.  */
-#define GRP_COMDAT	0x1		/* Mark group as COMDAT.  */
-
-/* Symbol table entry.  */
-
-typedef struct
-{
-  Elf32_Word	st_name;		/* Symbol name (string tbl index) */
-  Elf32_Addr	st_value;		/* Symbol value */
-  Elf32_Word	st_size;		/* Symbol size */
-  unsigned char	st_info;		/* Symbol type and binding */
-  unsigned char	st_other;		/* Symbol visibility */
-  Elf32_Section	st_shndx;		/* Section index */
-} Elf32_Sym;
-
-typedef struct
-{
-  Elf64_Word	st_name;		/* Symbol name (string tbl index) */
-  unsigned char	st_info;		/* Symbol type and binding */
-  unsigned char st_other;		/* Symbol visibility */
-  Elf64_Section	st_shndx;		/* Section index */
-  Elf64_Addr	st_value;		/* Symbol value */
-  Elf64_Xword	st_size;		/* Symbol size */
-} Elf64_Sym;
-
-/* The syminfo section if available contains additional information about
-   every dynamic symbol.  */
-
-typedef struct
-{
-  Elf32_Half si_boundto;		/* Direct bindings, symbol bound to */
-  Elf32_Half si_flags;			/* Per symbol flags */
-} Elf32_Syminfo;
-
-typedef struct
-{
-  Elf64_Half si_boundto;		/* Direct bindings, symbol bound to */
-  Elf64_Half si_flags;			/* Per symbol flags */
-} Elf64_Syminfo;
-
-/* Possible values for si_boundto.  */
-#define SYMINFO_BT_SELF		0xffff	/* Symbol bound to self */
-#define SYMINFO_BT_PARENT	0xfffe	/* Symbol bound to parent */
-#define SYMINFO_BT_LOWRESERVE	0xff00	/* Beginning of reserved entries */
-
-/* Possible bitmasks for si_flags.  */
-#define SYMINFO_FLG_DIRECT	0x0001	/* Direct bound symbol */
-#define SYMINFO_FLG_PASSTHRU	0x0002	/* Pass-thru symbol for translator */
-#define SYMINFO_FLG_COPY	0x0004	/* Symbol is a copy-reloc */
-#define SYMINFO_FLG_LAZYLOAD	0x0008	/* Symbol bound to object to be lazy
-					   loaded */
-/* Syminfo version values.  */
-#define SYMINFO_NONE		0
-#define SYMINFO_CURRENT		1
-#define SYMINFO_NUM		2
-
-
-/* How to extract and insert information held in the st_info field.  */
-
-#define ELF32_ST_BIND(val)		(((unsigned char) (val)) >> 4)
-#define ELF32_ST_TYPE(val)		((val) & 0xf)
-#define ELF32_ST_INFO(bind, type)	(((bind) << 4) + ((type) & 0xf))
-
-/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */
-#define ELF64_ST_BIND(val)		ELF32_ST_BIND (val)
-#define ELF64_ST_TYPE(val)		ELF32_ST_TYPE (val)
-#define ELF64_ST_INFO(bind, type)	ELF32_ST_INFO ((bind), (type))
-
-/* Legal values for ST_BIND subfield of st_info (symbol binding).  */
-
-#define STB_LOCAL	0		/* Local symbol */
-#define STB_GLOBAL	1		/* Global symbol */
-#define STB_WEAK	2		/* Weak symbol */
-#define	STB_NUM		3		/* Number of defined types.  */
-#define STB_LOOS	10		/* Start of OS-specific */
-#define STB_HIOS	12		/* End of OS-specific */
-#define STB_LOPROC	13		/* Start of processor-specific */
-#define STB_HIPROC	15		/* End of processor-specific */
-
-/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
-
-#define STT_NOTYPE	0		/* Symbol type is unspecified */
-#define STT_OBJECT	1		/* Symbol is a data object */
-#define STT_FUNC	2		/* Symbol is a code object */
-#define STT_SECTION	3		/* Symbol associated with a section */
-#define STT_FILE	4		/* Symbol's name is file name */
-#define STT_COMMON	5		/* Symbol is a common data object */
-#define STT_TLS		6		/* Symbol is thread-local data object*/
-#define	STT_NUM		7		/* Number of defined types.  */
-#define STT_LOOS	10		/* Start of OS-specific */
-#define STT_HIOS	12		/* End of OS-specific */
-#define STT_LOPROC	13		/* Start of processor-specific */
-#define STT_HIPROC	15		/* End of processor-specific */
-
-
-/* Symbol table indices are found in the hash buckets and chain table
-   of a symbol hash table section.  This special index value indicates
-   the end of a chain, meaning no further symbols are found in that bucket.  */
-
-#define STN_UNDEF	0		/* End of a chain.  */
-
-
-/* How to extract and insert information held in the st_other field.  */
-
-#define ELF32_ST_VISIBILITY(o)	((o) & 0x03)
-
-/* For ELF64 the definitions are the same.  */
-#define ELF64_ST_VISIBILITY(o)	ELF32_ST_VISIBILITY (o)
-
-/* Symbol visibility specification encoded in the st_other field.  */
-#define STV_DEFAULT	0		/* Default symbol visibility rules */
-#define STV_INTERNAL	1		/* Processor specific hidden class */
-#define STV_HIDDEN	2		/* Sym unavailable in other modules */
-#define STV_PROTECTED	3		/* Not preemptible, not exported */
-
-
-/* Relocation table entry without addend (in section of type SHT_REL).  */
-
-typedef struct
-{
-  Elf32_Addr	r_offset;		/* Address */
-  Elf32_Word	r_info;			/* Relocation type and symbol index */
-} Elf32_Rel;
-
-/* I have seen two different definitions of the Elf64_Rel and
-   Elf64_Rela structures, so we'll leave them out until Novell (or
-   whoever) gets their act together.  */
-/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */
-
-typedef struct
-{
-  Elf64_Addr	r_offset;		/* Address */
-  Elf64_Xword	r_info;			/* Relocation type and symbol index */
-} Elf64_Rel;
-
-/* Relocation table entry with addend (in section of type SHT_RELA).  */
-
-typedef struct
-{
-  Elf32_Addr	r_offset;		/* Address */
-  Elf32_Word	r_info;			/* Relocation type and symbol index */
-  Elf32_Sword	r_addend;		/* Addend */
-} Elf32_Rela;
-
-typedef struct
-{
-  Elf64_Addr	r_offset;		/* Address */
-  Elf64_Xword	r_info;			/* Relocation type and symbol index */
-  Elf64_Sxword	r_addend;		/* Addend */
-} Elf64_Rela;
-
-/* How to extract and insert information held in the r_info field.  */
-
-#define ELF32_R_SYM(val)		((val) >> 8)
-#define ELF32_R_TYPE(val)		((val) & 0xff)
-#define ELF32_R_INFO(sym, type)		(((sym) << 8) + ((type) & 0xff))
-
-#define ELF64_R_SYM(i)			((i) >> 32)
-#define ELF64_R_TYPE(i)			((i) & 0xffffffff)
-#define ELF64_R_INFO(sym,type)		((((Elf64_Xword) (sym)) << 32) + (type))
-
-/* Program segment header.  */
-
-typedef struct
-{
-  Elf32_Word	p_type;			/* Segment type */
-  Elf32_Off	p_offset;		/* Segment file offset */
-  Elf32_Addr	p_vaddr;		/* Segment virtual address */
-  Elf32_Addr	p_paddr;		/* Segment physical address */
-  Elf32_Word	p_filesz;		/* Segment size in file */
-  Elf32_Word	p_memsz;		/* Segment size in memory */
-  Elf32_Word	p_flags;		/* Segment flags */
-  Elf32_Word	p_align;		/* Segment alignment */
-} Elf32_Phdr;
-
-typedef struct
-{
-  Elf64_Word	p_type;			/* Segment type */
-  Elf64_Word	p_flags;		/* Segment flags */
-  Elf64_Off	p_offset;		/* Segment file offset */
-  Elf64_Addr	p_vaddr;		/* Segment virtual address */
-  Elf64_Addr	p_paddr;		/* Segment physical address */
-  Elf64_Xword	p_filesz;		/* Segment size in file */
-  Elf64_Xword	p_memsz;		/* Segment size in memory */
-  Elf64_Xword	p_align;		/* Segment alignment */
-} Elf64_Phdr;
-
-/* Legal values for p_type (segment type).  */
-
-#define	PT_NULL		0		/* Program header table entry unused */
-#define PT_LOAD		1		/* Loadable program segment */
-#define PT_DYNAMIC	2		/* Dynamic linking information */
-#define PT_INTERP	3		/* Program interpreter */
-#define PT_NOTE		4		/* Auxiliary information */
-#define PT_SHLIB	5		/* Reserved */
-#define PT_PHDR		6		/* Entry for header table itself */
-#define PT_TLS		7		/* Thread-local storage segment */
-#define	PT_NUM		8		/* Number of defined types */
-#define PT_LOOS		0x60000000	/* Start of OS-specific */
-#define PT_GNU_EH_FRAME	0x6474e550	/* GCC .eh_frame_hdr segment */
-#define PT_GNU_STACK	0x6474e551	/* Indicates stack executability */
-#define PT_GNU_RELRO	0x6474e552	/* Read-only after relocation */
-#define PT_LOSUNW	0x6ffffffa
-#define PT_SUNWBSS	0x6ffffffa	/* Sun Specific segment */
-#define PT_SUNWSTACK	0x6ffffffb	/* Stack segment */
-#define PT_HISUNW	0x6fffffff
-#define PT_HIOS		0x6fffffff	/* End of OS-specific */
-#define PT_LOPROC	0x70000000	/* Start of processor-specific */
-#define PT_HIPROC	0x7fffffff	/* End of processor-specific */
-
-/* Legal values for p_flags (segment flags).  */
-
-#define PF_X		(1 << 0)	/* Segment is executable */
-#define PF_W		(1 << 1)	/* Segment is writable */
-#define PF_R		(1 << 2)	/* Segment is readable */
-#define PF_MASKOS	0x0ff00000	/* OS-specific */
-#define PF_MASKPROC	0xf0000000	/* Processor-specific */
-
-/* Legal values for note segment descriptor types for core files. */
-
-#define NT_PRSTATUS	1		/* Contains copy of prstatus struct */
-#define NT_FPREGSET	2		/* Contains copy of fpregset struct */
-#define NT_PRPSINFO	3		/* Contains copy of prpsinfo struct */
-#define NT_PRXREG	4		/* Contains copy of prxregset struct */
-#define NT_TASKSTRUCT	4		/* Contains copy of task structure */
-#define NT_PLATFORM	5		/* String from sysinfo(SI_PLATFORM) */
-#define NT_AUXV		6		/* Contains copy of auxv array */
-#define NT_GWINDOWS	7		/* Contains copy of gwindows struct */
-#define NT_ASRS		8		/* Contains copy of asrset struct */
-#define NT_PSTATUS	10		/* Contains copy of pstatus struct */
-#define NT_PSINFO	13		/* Contains copy of psinfo struct */
-#define NT_PRCRED	14		/* Contains copy of prcred struct */
-#define NT_UTSNAME	15		/* Contains copy of utsname struct */
-#define NT_LWPSTATUS	16		/* Contains copy of lwpstatus struct */
-#define NT_LWPSINFO	17		/* Contains copy of lwpinfo struct */
-#define NT_PRFPXREG	20		/* Contains copy of fprxregset struct */
-#define NT_PRXFPREG	0x46e62b7f	/* Contains copy of user_fxsr_struct */
-
-/* Legal values for the note segment descriptor types for object files.  */
-
-#define NT_VERSION	1		/* Contains a version string.  */
-
-
-/* Dynamic section entry.  */
-
-typedef struct
-{
-  Elf32_Sword	d_tag;			/* Dynamic entry type */
-  union
-    {
-      Elf32_Word d_val;			/* Integer value */
-      Elf32_Addr d_ptr;			/* Address value */
-    } d_un;
-} Elf32_Dyn;
-
-typedef struct
-{
-  Elf64_Sxword	d_tag;			/* Dynamic entry type */
-  union
-    {
-      Elf64_Xword d_val;		/* Integer value */
-      Elf64_Addr d_ptr;			/* Address value */
-    } d_un;
-} Elf64_Dyn;
-
-/* Legal values for d_tag (dynamic entry type).  */
-
-#define DT_NULL		0		/* Marks end of dynamic section */
-#define DT_NEEDED	1		/* Name of needed library */
-#define DT_PLTRELSZ	2		/* Size in bytes of PLT relocs */
-#define DT_PLTGOT	3		/* Processor defined value */
-#define DT_HASH		4		/* Address of symbol hash table */
-#define DT_STRTAB	5		/* Address of string table */
-#define DT_SYMTAB	6		/* Address of symbol table */
-#define DT_RELA		7		/* Address of Rela relocs */
-#define DT_RELASZ	8		/* Total size of Rela relocs */
-#define DT_RELAENT	9		/* Size of one Rela reloc */
-#define DT_STRSZ	10		/* Size of string table */
-#define DT_SYMENT	11		/* Size of one symbol table entry */
-#define DT_INIT		12		/* Address of init function */
-#define DT_FINI		13		/* Address of termination function */
-#define DT_SONAME	14		/* Name of shared object */
-#define DT_RPATH	15		/* Library search path (deprecated) */
-#define DT_SYMBOLIC	16		/* Start symbol search here */
-#define DT_REL		17		/* Address of Rel relocs */
-#define DT_RELSZ	18		/* Total size of Rel relocs */
-#define DT_RELENT	19		/* Size of one Rel reloc */
-#define DT_PLTREL	20		/* Type of reloc in PLT */
-#define DT_DEBUG	21		/* For debugging; unspecified */
-#define DT_TEXTREL	22		/* Reloc might modify .text */
-#define DT_JMPREL	23		/* Address of PLT relocs */
-#define	DT_BIND_NOW	24		/* Process relocations of object */
-#define	DT_INIT_ARRAY	25		/* Array with addresses of init fct */
-#define	DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
-#define	DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
-#define	DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
-#define DT_RUNPATH	29		/* Library search path */
-#define DT_FLAGS	30		/* Flags for the object being loaded */
-#define DT_ENCODING	32		/* Start of encoded range */
-#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
-#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
-#define	DT_NUM		34		/* Number used */
-#define DT_LOOS		0x6000000d	/* Start of OS-specific */
-#define DT_HIOS		0x6ffff000	/* End of OS-specific */
-#define DT_LOPROC	0x70000000	/* Start of processor-specific */
-#define DT_HIPROC	0x7fffffff	/* End of processor-specific */
-#define	DT_PROCNUM	DT_MIPS_NUM	/* Most used by any processor */
-
-/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
-   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's
-   approach.  */
-#define DT_VALRNGLO	0x6ffffd00
-#define DT_GNU_PRELINKED 0x6ffffdf5	/* Prelinking timestamp */
-#define DT_GNU_CONFLICTSZ 0x6ffffdf6	/* Size of conflict section */
-#define DT_GNU_LIBLISTSZ 0x6ffffdf7	/* Size of library list */
-#define DT_CHECKSUM	0x6ffffdf8
-#define DT_PLTPADSZ	0x6ffffdf9
-#define DT_MOVEENT	0x6ffffdfa
-#define DT_MOVESZ	0x6ffffdfb
-#define DT_FEATURE_1	0x6ffffdfc	/* Feature selection (DTF_*).  */
-#define DT_POSFLAG_1	0x6ffffdfd	/* Flags for DT_* entries, effecting
-					   the following DT_* entry.  */
-#define DT_SYMINSZ	0x6ffffdfe	/* Size of syminfo table (in bytes) */
-#define DT_SYMINENT	0x6ffffdff	/* Entry size of syminfo */
-#define DT_VALRNGHI	0x6ffffdff
-#define DT_VALTAGIDX(tag)	(DT_VALRNGHI - (tag))	/* Reverse order! */
-#define DT_VALNUM 12
-
-/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
-   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
-
-   If any adjustment is made to the ELF object after it has been
-   built these entries will need to be adjusted.  */
-#define DT_ADDRRNGLO	0x6ffffe00
-#define DT_GNU_HASH	0x6ffffef5	/* GNU-style hash table.  */
-#define DT_TLSDESC_PLT	0x6ffffef6
-#define DT_TLSDESC_GOT	0x6ffffef7
-#define DT_GNU_CONFLICT	0x6ffffef8	/* Start of conflict section */
-#define DT_GNU_LIBLIST	0x6ffffef9	/* Library list */
-#define DT_CONFIG	0x6ffffefa	/* Configuration information.  */
-#define DT_DEPAUDIT	0x6ffffefb	/* Dependency auditing.  */
-#define DT_AUDIT	0x6ffffefc	/* Object auditing.  */
-#define	DT_PLTPAD	0x6ffffefd	/* PLT padding.  */
-#define	DT_MOVETAB	0x6ffffefe	/* Move table.  */
-#define DT_SYMINFO	0x6ffffeff	/* Syminfo table.  */
-#define DT_ADDRRNGHI	0x6ffffeff
-#define DT_ADDRTAGIDX(tag)	(DT_ADDRRNGHI - (tag))	/* Reverse order! */
-#define DT_ADDRNUM 11
-
-/* The versioning entry types.  The next are defined as part of the
-   GNU extension.  */
-#define DT_VERSYM	0x6ffffff0
-
-#define DT_RELACOUNT	0x6ffffff9
-#define DT_RELCOUNT	0x6ffffffa
-
-/* These were chosen by Sun.  */
-#define DT_FLAGS_1	0x6ffffffb	/* State flags, see DF_1_* below.  */
-#define	DT_VERDEF	0x6ffffffc	/* Address of version definition
-					   table */
-#define	DT_VERDEFNUM	0x6ffffffd	/* Number of version definitions */
-#define	DT_VERNEED	0x6ffffffe	/* Address of table with needed
-					   versions */
-#define	DT_VERNEEDNUM	0x6fffffff	/* Number of needed versions */
-#define DT_VERSIONTAGIDX(tag)	(DT_VERNEEDNUM - (tag))	/* Reverse order! */
-#define DT_VERSIONTAGNUM 16
-
-/* Sun added these machine-independent extensions in the "processor-specific"
-   range.  Be compatible.  */
-#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */
-#define DT_FILTER       0x7fffffff      /* Shared object to get values from */
-#define DT_EXTRATAGIDX(tag)	((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)
-#define DT_EXTRANUM	3
-
-/* Values of `d_un.d_val' in the DT_FLAGS entry.  */
-#define DF_ORIGIN	0x00000001	/* Object may use DF_ORIGIN */
-#define DF_SYMBOLIC	0x00000002	/* Symbol resolutions starts here */
-#define DF_TEXTREL	0x00000004	/* Object contains text relocations */
-#define DF_BIND_NOW	0x00000008	/* No lazy binding for this object */
-#define DF_STATIC_TLS	0x00000010	/* Module uses the static TLS model */
-
-/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1
-   entry in the dynamic section.  */
-#define DF_1_NOW	0x00000001	/* Set RTLD_NOW for this object.  */
-#define DF_1_GLOBAL	0x00000002	/* Set RTLD_GLOBAL for this object.  */
-#define DF_1_GROUP	0x00000004	/* Set RTLD_GROUP for this object.  */
-#define DF_1_NODELETE	0x00000008	/* Set RTLD_NODELETE for this object.*/
-#define DF_1_LOADFLTR	0x00000010	/* Trigger filtee loading at runtime.*/
-#define DF_1_INITFIRST	0x00000020	/* Set RTLD_INITFIRST for this object*/
-#define DF_1_NOOPEN	0x00000040	/* Set RTLD_NOOPEN for this object.  */
-#define DF_1_ORIGIN	0x00000080	/* $ORIGIN must be handled.  */
-#define DF_1_DIRECT	0x00000100	/* Direct binding enabled.  */
-#define DF_1_TRANS	0x00000200
-#define DF_1_INTERPOSE	0x00000400	/* Object is used to interpose.  */
-#define DF_1_NODEFLIB	0x00000800	/* Ignore default lib search path.  */
-#define DF_1_NODUMP	0x00001000	/* Object can't be dldump'ed.  */
-#define DF_1_CONFALT	0x00002000	/* Configuration alternative created.*/
-#define DF_1_ENDFILTEE	0x00004000	/* Filtee terminates filters search. */
-#define	DF_1_DISPRELDNE	0x00008000	/* Disp reloc applied at build time. */
-#define	DF_1_DISPRELPND	0x00010000	/* Disp reloc applied at run-time.  */
-
-/* Flags for the feature selection in DT_FEATURE_1.  */
-#define DTF_1_PARINIT	0x00000001
-#define DTF_1_CONFEXP	0x00000002
-
-/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */
-#define DF_P1_LAZYLOAD	0x00000001	/* Lazyload following object.  */
-#define DF_P1_GROUPPERM	0x00000002	/* Symbols from next object are not
-					   generally available.  */
-
-/* Version definition sections.  */
-
-typedef struct
-{
-  Elf32_Half	vd_version;		/* Version revision */
-  Elf32_Half	vd_flags;		/* Version information */
-  Elf32_Half	vd_ndx;			/* Version Index */
-  Elf32_Half	vd_cnt;			/* Number of associated aux entries */
-  Elf32_Word	vd_hash;		/* Version name hash value */
-  Elf32_Word	vd_aux;			/* Offset in bytes to verdaux array */
-  Elf32_Word	vd_next;		/* Offset in bytes to next verdef
-					   entry */
-} Elf32_Verdef;
-
-typedef struct
-{
-  Elf64_Half	vd_version;		/* Version revision */
-  Elf64_Half	vd_flags;		/* Version information */
-  Elf64_Half	vd_ndx;			/* Version Index */
-  Elf64_Half	vd_cnt;			/* Number of associated aux entries */
-  Elf64_Word	vd_hash;		/* Version name hash value */
-  Elf64_Word	vd_aux;			/* Offset in bytes to verdaux array */
-  Elf64_Word	vd_next;		/* Offset in bytes to next verdef
-					   entry */
-} Elf64_Verdef;
-
-
-/* Legal values for vd_version (version revision).  */
-#define VER_DEF_NONE	0		/* No version */
-#define VER_DEF_CURRENT	1		/* Current version */
-#define VER_DEF_NUM	2		/* Given version number */
-
-/* Legal values for vd_flags (version information flags).  */
-#define VER_FLG_BASE	0x1		/* Version definition of file itself */
-#define VER_FLG_WEAK	0x2		/* Weak version identifier */
-
-/* Versym symbol index values.  */
-#define	VER_NDX_LOCAL		0	/* Symbol is local.  */
-#define	VER_NDX_GLOBAL		1	/* Symbol is global.  */
-#define	VER_NDX_LORESERVE	0xff00	/* Beginning of reserved entries.  */
-#define	VER_NDX_ELIMINATE	0xff01	/* Symbol is to be eliminated.  */
-
-/* Auxialiary version information.  */
-
-typedef struct
-{
-  Elf32_Word	vda_name;		/* Version or dependency names */
-  Elf32_Word	vda_next;		/* Offset in bytes to next verdaux
-					   entry */
-} Elf32_Verdaux;
-
-typedef struct
-{
-  Elf64_Word	vda_name;		/* Version or dependency names */
-  Elf64_Word	vda_next;		/* Offset in bytes to next verdaux
-					   entry */
-} Elf64_Verdaux;
-
-
-/* Version dependency section.  */
-
-typedef struct
-{
-  Elf32_Half	vn_version;		/* Version of structure */
-  Elf32_Half	vn_cnt;			/* Number of associated aux entries */
-  Elf32_Word	vn_file;		/* Offset of filename for this
-					   dependency */
-  Elf32_Word	vn_aux;			/* Offset in bytes to vernaux array */
-  Elf32_Word	vn_next;		/* Offset in bytes to next verneed
-					   entry */
-} Elf32_Verneed;
-
-typedef struct
-{
-  Elf64_Half	vn_version;		/* Version of structure */
-  Elf64_Half	vn_cnt;			/* Number of associated aux entries */
-  Elf64_Word	vn_file;		/* Offset of filename for this
-					   dependency */
-  Elf64_Word	vn_aux;			/* Offset in bytes to vernaux array */
-  Elf64_Word	vn_next;		/* Offset in bytes to next verneed
-					   entry */
-} Elf64_Verneed;
-
-
-/* Legal values for vn_version (version revision).  */
-#define VER_NEED_NONE	 0		/* No version */
-#define VER_NEED_CURRENT 1		/* Current version */
-#define VER_NEED_NUM	 2		/* Given version number */
-
-/* Auxiliary needed version information.  */
-
-typedef struct
-{
-  Elf32_Word	vna_hash;		/* Hash value of dependency name */
-  Elf32_Half	vna_flags;		/* Dependency specific information */
-  Elf32_Half	vna_other;		/* Unused */
-  Elf32_Word	vna_name;		/* Dependency name string offset */
-  Elf32_Word	vna_next;		/* Offset in bytes to next vernaux
-					   entry */
-} Elf32_Vernaux;
-
-typedef struct
-{
-  Elf64_Word	vna_hash;		/* Hash value of dependency name */
-  Elf64_Half	vna_flags;		/* Dependency specific information */
-  Elf64_Half	vna_other;		/* Unused */
-  Elf64_Word	vna_name;		/* Dependency name string offset */
-  Elf64_Word	vna_next;		/* Offset in bytes to next vernaux
-					   entry */
-} Elf64_Vernaux;
-
-
-/* Legal values for vna_flags.  */
-#define VER_FLG_WEAK	0x2		/* Weak version identifier */
-
-
-/* Auxiliary vector.  */
-
-/* This vector is normally only used by the program interpreter.  The
-   usual definition in an ABI supplement uses the name auxv_t.  The
-   vector is not usually defined in a standard <elf.h> file, but it
-   can't hurt.  We rename it to avoid conflicts.  The sizes of these
-   types are an arrangement between the exec server and the program
-   interpreter, so we don't fully specify them here.  */
-
-typedef struct
-{
-  uint32_t a_type;		/* Entry type */
-  union
-    {
-      uint32_t a_val;		/* Integer value */
-      /* We use to have pointer elements added here.  We cannot do that,
-	 though, since it does not work when using 32-bit definitions
-	 on 64-bit platforms and vice versa.  */
-    } a_un;
-} Elf32_auxv_t;
-
-typedef struct
-{
-  uint64_t a_type;		/* Entry type */
-  union
-    {
-      uint64_t a_val;		/* Integer value */
-      /* We use to have pointer elements added here.  We cannot do that,
-	 though, since it does not work when using 32-bit definitions
-	 on 64-bit platforms and vice versa.  */
-    } a_un;
-} Elf64_auxv_t;
-
-/* Legal values for a_type (entry type).  */
-
-#define AT_NULL		0		/* End of vector */
-#define AT_IGNORE	1		/* Entry should be ignored */
-#define AT_EXECFD	2		/* File descriptor of program */
-#define AT_PHDR		3		/* Program headers for program */
-#define AT_PHENT	4		/* Size of program header entry */
-#define AT_PHNUM	5		/* Number of program headers */
-#define AT_PAGESZ	6		/* System page size */
-#define AT_BASE		7		/* Base address of interpreter */
-#define AT_FLAGS	8		/* Flags */
-#define AT_ENTRY	9		/* Entry point of program */
-#define AT_NOTELF	10		/* Program is not ELF */
-#define AT_UID		11		/* Real uid */
-#define AT_EUID		12		/* Effective uid */
-#define AT_GID		13		/* Real gid */
-#define AT_EGID		14		/* Effective gid */
-#define AT_CLKTCK	17		/* Frequency of times() */
-
-/* Some more special a_type values describing the hardware.  */
-#define AT_PLATFORM	15		/* String identifying platform.  */
-#define AT_HWCAP	16		/* Machine dependent hints about
-					   processor capabilities.  */
-
-/* This entry gives some information about the FPU initialization
-   performed by the kernel.  */
-#define AT_FPUCW	18		/* Used FPU control word.  */
-
-/* Cache block sizes.  */
-#define AT_DCACHEBSIZE	19		/* Data cache block size.  */
-#define AT_ICACHEBSIZE	20		/* Instruction cache block size.  */
-#define AT_UCACHEBSIZE	21		/* Unified cache block size.  */
-
-/* A special ignored value for PPC, used by the kernel to control the
-   interpretation of the AUXV. Must be > 16.  */
-#define AT_IGNOREPPC	22		/* Entry should be ignored.  */
-
-#define	AT_SECURE	23		/* Boolean, was exec setuid-like?  */
-
-/* Pointer to the global system page used for system calls and other
-   nice things.  */
-#define AT_SYSINFO	32
-#define AT_SYSINFO_EHDR	33
-
-/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains
-   log2 of line size; mask those to get cache size.  */
-#define AT_L1I_CACHESHAPE	34
-#define AT_L1D_CACHESHAPE	35
-#define AT_L2_CACHESHAPE	36
-#define AT_L3_CACHESHAPE	37
-
-/* Note section contents.  Each entry in the note section begins with
-   a header of a fixed form.  */
-
-typedef struct
-{
-  Elf32_Word n_namesz;			/* Length of the note's name.  */
-  Elf32_Word n_descsz;			/* Length of the note's descriptor.  */
-  Elf32_Word n_type;			/* Type of the note.  */
-} Elf32_Nhdr;
-
-typedef struct
-{
-  Elf64_Word n_namesz;			/* Length of the note's name.  */
-  Elf64_Word n_descsz;			/* Length of the note's descriptor.  */
-  Elf64_Word n_type;			/* Type of the note.  */
-} Elf64_Nhdr;
-
-/* Known names of notes.  */
-
-/* Solaris entries in the note section have this name.  */
-#define ELF_NOTE_SOLARIS	"SUNW Solaris"
-
-/* Note entries for GNU systems have this name.  */
-#define ELF_NOTE_GNU		"GNU"
-
-
-/* Defined types of notes for Solaris.  */
-
-/* Value of descriptor (one word) is desired pagesize for the binary.  */
-#define ELF_NOTE_PAGESIZE_HINT	1
-
-
-/* Defined note types for GNU systems.  */
-
-/* ABI information.  The descriptor consists of words:
-   word 0: OS descriptor
-   word 1: major version of the ABI
-   word 2: minor version of the ABI
-   word 3: subminor version of the ABI
-*/
-#define NT_GNU_ABI_TAG	1
-#define ELF_NOTE_ABI	NT_GNU_ABI_TAG /* Old name.  */
-
-/* Known OSes.  These values can appear in word 0 of an
-   NT_GNU_ABI_TAG note section entry.  */
-#define ELF_NOTE_OS_LINUX	0
-#define ELF_NOTE_OS_GNU		1
-#define ELF_NOTE_OS_SOLARIS2	2
-#define ELF_NOTE_OS_FREEBSD	3
-
-/* Synthetic hwcap information.  The descriptor begins with two words:
-   word 0: number of entries
-   word 1: bitmask of enabled entries
-   Then follow variable-length entries, one byte followed by a
-   '\0'-terminated hwcap name string.  The byte gives the bit
-   number to test if enabled, (1U << bit) & bitmask.  */
-#define NT_GNU_HWCAP	2
-
-/* Build ID bits as generated by ld --build-id.
-   The descriptor consists of any nonzero number of bytes.  */
-#define NT_GNU_BUILD_ID	3
-
-
-/* Move records.  */
-typedef struct
-{
-  Elf32_Xword m_value;		/* Symbol value.  */
-  Elf32_Word m_info;		/* Size and index.  */
-  Elf32_Word m_poffset;		/* Symbol offset.  */
-  Elf32_Half m_repeat;		/* Repeat count.  */
-  Elf32_Half m_stride;		/* Stride info.  */
-} Elf32_Move;
-
-typedef struct
-{
-  Elf64_Xword m_value;		/* Symbol value.  */
-  Elf64_Xword m_info;		/* Size and index.  */
-  Elf64_Xword m_poffset;	/* Symbol offset.  */
-  Elf64_Half m_repeat;		/* Repeat count.  */
-  Elf64_Half m_stride;		/* Stride info.  */
-} Elf64_Move;
-
-/* Macro to construct move records.  */
-#define ELF32_M_SYM(info)	((info) >> 8)
-#define ELF32_M_SIZE(info)	((unsigned char) (info))
-#define ELF32_M_INFO(sym, size)	(((sym) << 8) + (unsigned char) (size))
-
-#define ELF64_M_SYM(info)	ELF32_M_SYM (info)
-#define ELF64_M_SIZE(info)	ELF32_M_SIZE (info)
-#define ELF64_M_INFO(sym, size)	ELF32_M_INFO (sym, size)
-
-
-/* Motorola 68k specific definitions.  */
-
-/* Values for Elf32_Ehdr.e_flags.  */
-#define EF_CPU32	0x00810000
-
-/* m68k relocs.  */
-
-#define R_68K_NONE	0		/* No reloc */
-#define R_68K_32	1		/* Direct 32 bit  */
-#define R_68K_16	2		/* Direct 16 bit  */
-#define R_68K_8		3		/* Direct 8 bit  */
-#define R_68K_PC32	4		/* PC relative 32 bit */
-#define R_68K_PC16	5		/* PC relative 16 bit */
-#define R_68K_PC8	6		/* PC relative 8 bit */
-#define R_68K_GOT32	7		/* 32 bit PC relative GOT entry */
-#define R_68K_GOT16	8		/* 16 bit PC relative GOT entry */
-#define R_68K_GOT8	9		/* 8 bit PC relative GOT entry */
-#define R_68K_GOT32O	10		/* 32 bit GOT offset */
-#define R_68K_GOT16O	11		/* 16 bit GOT offset */
-#define R_68K_GOT8O	12		/* 8 bit GOT offset */
-#define R_68K_PLT32	13		/* 32 bit PC relative PLT address */
-#define R_68K_PLT16	14		/* 16 bit PC relative PLT address */
-#define R_68K_PLT8	15		/* 8 bit PC relative PLT address */
-#define R_68K_PLT32O	16		/* 32 bit PLT offset */
-#define R_68K_PLT16O	17		/* 16 bit PLT offset */
-#define R_68K_PLT8O	18		/* 8 bit PLT offset */
-#define R_68K_COPY	19		/* Copy symbol at runtime */
-#define R_68K_GLOB_DAT	20		/* Create GOT entry */
-#define R_68K_JMP_SLOT	21		/* Create PLT entry */
-#define R_68K_RELATIVE	22		/* Adjust by program base */
-/* Keep this the last entry.  */
-#define R_68K_NUM	23
-
-/* Intel 80386 specific definitions.  */
-
-/* i386 relocs.  */
-
-#define R_386_NONE	   0		/* No reloc */
-#define R_386_32	   1		/* Direct 32 bit  */
-#define R_386_PC32	   2		/* PC relative 32 bit */
-#define R_386_GOT32	   3		/* 32 bit GOT entry */
-#define R_386_PLT32	   4		/* 32 bit PLT address */
-#define R_386_COPY	   5		/* Copy symbol at runtime */
-#define R_386_GLOB_DAT	   6		/* Create GOT entry */
-#define R_386_JMP_SLOT	   7		/* Create PLT entry */
-#define R_386_RELATIVE	   8		/* Adjust by program base */
-#define R_386_GOTOFF	   9		/* 32 bit offset to GOT */
-#define R_386_GOTPC	   10		/* 32 bit PC relative offset to GOT */
-#define R_386_32PLT	   11
-#define R_386_TLS_TPOFF	   14		/* Offset in static TLS block */
-#define R_386_TLS_IE	   15		/* Address of GOT entry for static TLS
-					   block offset */
-#define R_386_TLS_GOTIE	   16		/* GOT entry for static TLS block
-					   offset */
-#define R_386_TLS_LE	   17		/* Offset relative to static TLS
-					   block */
-#define R_386_TLS_GD	   18		/* Direct 32 bit for GNU version of
-					   general dynamic thread local data */
-#define R_386_TLS_LDM	   19		/* Direct 32 bit for GNU version of
-					   local dynamic thread local data
-					   in LE code */
-#define R_386_16	   20
-#define R_386_PC16	   21
-#define R_386_8		   22
-#define R_386_PC8	   23
-#define R_386_TLS_GD_32	   24		/* Direct 32 bit for general dynamic
-					   thread local data */
-#define R_386_TLS_GD_PUSH  25		/* Tag for pushl in GD TLS code */
-#define R_386_TLS_GD_CALL  26		/* Relocation for call to
-					   __tls_get_addr() */
-#define R_386_TLS_GD_POP   27		/* Tag for popl in GD TLS code */
-#define R_386_TLS_LDM_32   28		/* Direct 32 bit for local dynamic
-					   thread local data in LE code */
-#define R_386_TLS_LDM_PUSH 29		/* Tag for pushl in LDM TLS code */
-#define R_386_TLS_LDM_CALL 30		/* Relocation for call to
-					   __tls_get_addr() in LDM code */
-#define R_386_TLS_LDM_POP  31		/* Tag for popl in LDM TLS code */
-#define R_386_TLS_LDO_32   32		/* Offset relative to TLS block */
-#define R_386_TLS_IE_32	   33		/* GOT entry for negated static TLS
-					   block offset */
-#define R_386_TLS_LE_32	   34		/* Negated offset relative to static
-					   TLS block */
-#define R_386_TLS_DTPMOD32 35		/* ID of module containing symbol */
-#define R_386_TLS_DTPOFF32 36		/* Offset in TLS block */
-#define R_386_TLS_TPOFF32  37		/* Negated offset in static TLS block */
-/* Keep this the last entry.  */
-#define R_386_NUM	   38
-
-/* SUN SPARC specific definitions.  */
-
-/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
-
-#define STT_SPARC_REGISTER	13	/* Global register reserved to app. */
-
-/* Values for Elf64_Ehdr.e_flags.  */
-
-#define EF_SPARCV9_MM		3
-#define EF_SPARCV9_TSO		0
-#define EF_SPARCV9_PSO		1
-#define EF_SPARCV9_RMO		2
-#define EF_SPARC_LEDATA		0x800000 /* little endian data */
-#define EF_SPARC_EXT_MASK	0xFFFF00
-#define EF_SPARC_32PLUS		0x000100 /* generic V8+ features */
-#define EF_SPARC_SUN_US1	0x000200 /* Sun UltraSPARC1 extensions */
-#define EF_SPARC_HAL_R1		0x000400 /* HAL R1 extensions */
-#define EF_SPARC_SUN_US3	0x000800 /* Sun UltraSPARCIII extensions */
-
-/* SPARC relocs.  */
-
-#define R_SPARC_NONE		0	/* No reloc */
-#define R_SPARC_8		1	/* Direct 8 bit */
-#define R_SPARC_16		2	/* Direct 16 bit */
-#define R_SPARC_32		3	/* Direct 32 bit */
-#define R_SPARC_DISP8		4	/* PC relative 8 bit */
-#define R_SPARC_DISP16		5	/* PC relative 16 bit */
-#define R_SPARC_DISP32		6	/* PC relative 32 bit */
-#define R_SPARC_WDISP30		7	/* PC relative 30 bit shifted */
-#define R_SPARC_WDISP22		8	/* PC relative 22 bit shifted */
-#define R_SPARC_HI22		9	/* High 22 bit */
-#define R_SPARC_22		10	/* Direct 22 bit */
-#define R_SPARC_13		11	/* Direct 13 bit */
-#define R_SPARC_LO10		12	/* Truncated 10 bit */
-#define R_SPARC_GOT10		13	/* Truncated 10 bit GOT entry */
-#define R_SPARC_GOT13		14	/* 13 bit GOT entry */
-#define R_SPARC_GOT22		15	/* 22 bit GOT entry shifted */
-#define R_SPARC_PC10		16	/* PC relative 10 bit truncated */
-#define R_SPARC_PC22		17	/* PC relative 22 bit shifted */
-#define R_SPARC_WPLT30		18	/* 30 bit PC relative PLT address */
-#define R_SPARC_COPY		19	/* Copy symbol at runtime */
-#define R_SPARC_GLOB_DAT	20	/* Create GOT entry */
-#define R_SPARC_JMP_SLOT	21	/* Create PLT entry */
-#define R_SPARC_RELATIVE	22	/* Adjust by program base */
-#define R_SPARC_UA32		23	/* Direct 32 bit unaligned */
-
-/* Additional Sparc64 relocs.  */
-
-#define R_SPARC_PLT32		24	/* Direct 32 bit ref to PLT entry */
-#define R_SPARC_HIPLT22		25	/* High 22 bit PLT entry */
-#define R_SPARC_LOPLT10		26	/* Truncated 10 bit PLT entry */
-#define R_SPARC_PCPLT32		27	/* PC rel 32 bit ref to PLT entry */
-#define R_SPARC_PCPLT22		28	/* PC rel high 22 bit PLT entry */
-#define R_SPARC_PCPLT10		29	/* PC rel trunc 10 bit PLT entry */
-#define R_SPARC_10		30	/* Direct 10 bit */
-#define R_SPARC_11		31	/* Direct 11 bit */
-#define R_SPARC_64		32	/* Direct 64 bit */
-#define R_SPARC_OLO10		33	/* 10bit with secondary 13bit addend */
-#define R_SPARC_HH22		34	/* Top 22 bits of direct 64 bit */
-#define R_SPARC_HM10		35	/* High middle 10 bits of ... */
-#define R_SPARC_LM22		36	/* Low middle 22 bits of ... */
-#define R_SPARC_PC_HH22		37	/* Top 22 bits of pc rel 64 bit */
-#define R_SPARC_PC_HM10		38	/* High middle 10 bit of ... */
-#define R_SPARC_PC_LM22		39	/* Low miggle 22 bits of ... */
-#define R_SPARC_WDISP16		40	/* PC relative 16 bit shifted */
-#define R_SPARC_WDISP19		41	/* PC relative 19 bit shifted */
-#define R_SPARC_7		43	/* Direct 7 bit */
-#define R_SPARC_5		44	/* Direct 5 bit */
-#define R_SPARC_6		45	/* Direct 6 bit */
-#define R_SPARC_DISP64		46	/* PC relative 64 bit */
-#define R_SPARC_PLT64		47	/* Direct 64 bit ref to PLT entry */
-#define R_SPARC_HIX22		48	/* High 22 bit complemented */
-#define R_SPARC_LOX10		49	/* Truncated 11 bit complemented */
-#define R_SPARC_H44		50	/* Direct high 12 of 44 bit */
-#define R_SPARC_M44		51	/* Direct mid 22 of 44 bit */
-#define R_SPARC_L44		52	/* Direct low 10 of 44 bit */
-#define R_SPARC_REGISTER	53	/* Global register usage */
-#define R_SPARC_UA64		54	/* Direct 64 bit unaligned */
-#define R_SPARC_UA16		55	/* Direct 16 bit unaligned */
-#define R_SPARC_TLS_GD_HI22	56
-#define R_SPARC_TLS_GD_LO10	57
-#define R_SPARC_TLS_GD_ADD	58
-#define R_SPARC_TLS_GD_CALL	59
-#define R_SPARC_TLS_LDM_HI22	60
-#define R_SPARC_TLS_LDM_LO10	61
-#define R_SPARC_TLS_LDM_ADD	62
-#define R_SPARC_TLS_LDM_CALL	63
-#define R_SPARC_TLS_LDO_HIX22	64
-#define R_SPARC_TLS_LDO_LOX10	65
-#define R_SPARC_TLS_LDO_ADD	66
-#define R_SPARC_TLS_IE_HI22	67
-#define R_SPARC_TLS_IE_LO10	68
-#define R_SPARC_TLS_IE_LD	69
-#define R_SPARC_TLS_IE_LDX	70
-#define R_SPARC_TLS_IE_ADD	71
-#define R_SPARC_TLS_LE_HIX22	72
-#define R_SPARC_TLS_LE_LOX10	73
-#define R_SPARC_TLS_DTPMOD32	74
-#define R_SPARC_TLS_DTPMOD64	75
-#define R_SPARC_TLS_DTPOFF32	76
-#define R_SPARC_TLS_DTPOFF64	77
-#define R_SPARC_TLS_TPOFF32	78
-#define R_SPARC_TLS_TPOFF64	79
-/* Keep this the last entry.  */
-#define R_SPARC_NUM		80
-
-/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */
-
-#define DT_SPARC_REGISTER 0x70000001
-#define DT_SPARC_NUM	2
-
-/* Bits present in AT_HWCAP on SPARC.  */
-
-#define HWCAP_SPARC_FLUSH	1	/* The CPU supports flush insn.  */
-#define HWCAP_SPARC_STBAR	2
-#define HWCAP_SPARC_SWAP	4
-#define HWCAP_SPARC_MULDIV	8
-#define HWCAP_SPARC_V9		16	/* The CPU is v9, so v8plus is ok.  */
-#define HWCAP_SPARC_ULTRA3	32
-#define HWCAP_SPARC_BLKINIT	64	/* Sun4v with block-init/load-twin.  */
-
-/* MIPS R3000 specific definitions.  */
-
-/* Legal values for e_flags field of Elf32_Ehdr.  */
-
-#define EF_MIPS_NOREORDER   1		/* A .noreorder directive was used */
-#define EF_MIPS_PIC	    2		/* Contains PIC code */
-#define EF_MIPS_CPIC	    4		/* Uses PIC calling sequence */
-#define EF_MIPS_XGOT	    8
-#define EF_MIPS_64BIT_WHIRL 16
-#define EF_MIPS_ABI2	    32
-#define EF_MIPS_ABI_ON32    64
-#define EF_MIPS_ARCH	    0xf0000000	/* MIPS architecture level */
-
-/* Legal values for MIPS architecture level.  */
-
-#define EF_MIPS_ARCH_1	    0x00000000	/* -mips1 code.  */
-#define EF_MIPS_ARCH_2	    0x10000000	/* -mips2 code.  */
-#define EF_MIPS_ARCH_3	    0x20000000	/* -mips3 code.  */
-#define EF_MIPS_ARCH_4	    0x30000000	/* -mips4 code.  */
-#define EF_MIPS_ARCH_5	    0x40000000	/* -mips5 code.  */
-#define EF_MIPS_ARCH_32	    0x60000000	/* MIPS32 code.  */
-#define EF_MIPS_ARCH_64	    0x70000000	/* MIPS64 code.  */
-
-/* The following are non-official names and should not be used.  */
-
-#define E_MIPS_ARCH_1	  0x00000000	/* -mips1 code.  */
-#define E_MIPS_ARCH_2	  0x10000000	/* -mips2 code.  */
-#define E_MIPS_ARCH_3	  0x20000000	/* -mips3 code.  */
-#define E_MIPS_ARCH_4	  0x30000000	/* -mips4 code.  */
-#define E_MIPS_ARCH_5	  0x40000000	/* -mips5 code.  */
-#define E_MIPS_ARCH_32	  0x60000000	/* MIPS32 code.  */
-#define E_MIPS_ARCH_64	  0x70000000	/* MIPS64 code.  */
-
-/* Special section indices.  */
-
-#define SHN_MIPS_ACOMMON    0xff00	/* Allocated common symbols */
-#define SHN_MIPS_TEXT	    0xff01	/* Allocated test symbols.  */
-#define SHN_MIPS_DATA	    0xff02	/* Allocated data symbols.  */
-#define SHN_MIPS_SCOMMON    0xff03	/* Small common symbols */
-#define SHN_MIPS_SUNDEFINED 0xff04	/* Small undefined symbols */
-
-/* Legal values for sh_type field of Elf32_Shdr.  */
-
-#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */
-#define SHT_MIPS_MSYM	       0x70000001
-#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */
-#define SHT_MIPS_GPTAB	       0x70000003 /* Global data area sizes */
-#define SHT_MIPS_UCODE	       0x70000004 /* Reserved for SGI/MIPS compilers */
-#define SHT_MIPS_DEBUG	       0x70000005 /* MIPS ECOFF debugging information*/
-#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */
-#define SHT_MIPS_PACKAGE       0x70000007
-#define SHT_MIPS_PACKSYM       0x70000008
-#define SHT_MIPS_RELD	       0x70000009
-#define SHT_MIPS_IFACE         0x7000000b
-#define SHT_MIPS_CONTENT       0x7000000c
-#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */
-#define SHT_MIPS_SHDR	       0x70000010
-#define SHT_MIPS_FDESC	       0x70000011
-#define SHT_MIPS_EXTSYM	       0x70000012
-#define SHT_MIPS_DENSE	       0x70000013
-#define SHT_MIPS_PDESC	       0x70000014
-#define SHT_MIPS_LOCSYM	       0x70000015
-#define SHT_MIPS_AUXSYM	       0x70000016
-#define SHT_MIPS_OPTSYM	       0x70000017
-#define SHT_MIPS_LOCSTR	       0x70000018
-#define SHT_MIPS_LINE	       0x70000019
-#define SHT_MIPS_RFDESC	       0x7000001a
-#define SHT_MIPS_DELTASYM      0x7000001b
-#define SHT_MIPS_DELTAINST     0x7000001c
-#define SHT_MIPS_DELTACLASS    0x7000001d
-#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */
-#define SHT_MIPS_DELTADECL     0x7000001f
-#define SHT_MIPS_SYMBOL_LIB    0x70000020
-#define SHT_MIPS_EVENTS	       0x70000021 /* Event section.  */
-#define SHT_MIPS_TRANSLATE     0x70000022
-#define SHT_MIPS_PIXIE	       0x70000023
-#define SHT_MIPS_XLATE	       0x70000024
-#define SHT_MIPS_XLATE_DEBUG   0x70000025
-#define SHT_MIPS_WHIRL	       0x70000026
-#define SHT_MIPS_EH_REGION     0x70000027
-#define SHT_MIPS_XLATE_OLD     0x70000028
-#define SHT_MIPS_PDR_EXCEPTION 0x70000029
-
-/* Legal values for sh_flags field of Elf32_Shdr.  */
-
-#define SHF_MIPS_GPREL	 0x10000000	/* Must be part of global data area */
-#define SHF_MIPS_MERGE	 0x20000000
-#define SHF_MIPS_ADDR	 0x40000000
-#define SHF_MIPS_STRINGS 0x80000000
-#define SHF_MIPS_NOSTRIP 0x08000000
-#define SHF_MIPS_LOCAL	 0x04000000
-#define SHF_MIPS_NAMES	 0x02000000
-#define SHF_MIPS_NODUPE	 0x01000000
-
-
-/* Symbol tables.  */
-
-/* MIPS specific values for `st_other'.  */
-#define STO_MIPS_DEFAULT		0x0
-#define STO_MIPS_INTERNAL		0x1
-#define STO_MIPS_HIDDEN			0x2
-#define STO_MIPS_PROTECTED		0x3
-#define STO_MIPS_SC_ALIGN_UNUSED	0xff
-
-/* MIPS specific values for `st_info'.  */
-#define STB_MIPS_SPLIT_COMMON		13
-
-/* Entries found in sections of type SHT_MIPS_GPTAB.  */
-
-typedef union
-{
-  struct
-    {
-      Elf32_Word gt_current_g_value;	/* -G value used for compilation */
-      Elf32_Word gt_unused;		/* Not used */
-    } gt_header;			/* First entry in section */
-  struct
-    {
-      Elf32_Word gt_g_value;		/* If this value were used for -G */
-      Elf32_Word gt_bytes;		/* This many bytes would be used */
-    } gt_entry;				/* Subsequent entries in section */
-} Elf32_gptab;
-
-/* Entry found in sections of type SHT_MIPS_REGINFO.  */
-
-typedef struct
-{
-  Elf32_Word	ri_gprmask;		/* General registers used */
-  Elf32_Word	ri_cprmask[4];		/* Coprocessor registers used */
-  Elf32_Sword	ri_gp_value;		/* $gp register value */
-} Elf32_RegInfo;
-
-/* Entries found in sections of type SHT_MIPS_OPTIONS.  */
-
-typedef struct
-{
-  unsigned char kind;		/* Determines interpretation of the
-				   variable part of descriptor.  */
-  unsigned char size;		/* Size of descriptor, including header.  */
-  Elf32_Section section;	/* Section header index of section affected,
-				   0 for global options.  */
-  Elf32_Word info;		/* Kind-specific information.  */
-} Elf_Options;
-
-/* Values for `kind' field in Elf_Options.  */
-
-#define ODK_NULL	0	/* Undefined.  */
-#define ODK_REGINFO	1	/* Register usage information.  */
-#define ODK_EXCEPTIONS	2	/* Exception processing options.  */
-#define ODK_PAD		3	/* Section padding options.  */
-#define ODK_HWPATCH	4	/* Hardware workarounds performed */
-#define ODK_FILL	5	/* record the fill value used by the linker. */
-#define ODK_TAGS	6	/* reserve space for desktop tools to write. */
-#define ODK_HWAND	7	/* HW workarounds.  'AND' bits when merging. */
-#define ODK_HWOR	8	/* HW workarounds.  'OR' bits when merging.  */
-
-/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */
-
-#define OEX_FPU_MIN	0x1f	/* FPE's which MUST be enabled.  */
-#define OEX_FPU_MAX	0x1f00	/* FPE's which MAY be enabled.  */
-#define OEX_PAGE0	0x10000	/* page zero must be mapped.  */
-#define OEX_SMM		0x20000	/* Force sequential memory mode?  */
-#define OEX_FPDBUG	0x40000	/* Force floating point debug mode?  */
-#define OEX_PRECISEFP	OEX_FPDBUG
-#define OEX_DISMISS	0x80000	/* Dismiss invalid address faults?  */
-
-#define OEX_FPU_INVAL	0x10
-#define OEX_FPU_DIV0	0x08
-#define OEX_FPU_OFLO	0x04
-#define OEX_FPU_UFLO	0x02
-#define OEX_FPU_INEX	0x01
-
-/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */
-
-#define OHW_R4KEOP	0x1	/* R4000 end-of-page patch.  */
-#define OHW_R8KPFETCH	0x2	/* may need R8000 prefetch patch.  */
-#define OHW_R5KEOP	0x4	/* R5000 end-of-page patch.  */
-#define OHW_R5KCVTL	0x8	/* R5000 cvt.[ds].l bug.  clean=1.  */
-
-#define OPAD_PREFIX	0x1
-#define OPAD_POSTFIX	0x2
-#define OPAD_SYMBOL	0x4
-
-/* Entry found in `.options' section.  */
-
-typedef struct
-{
-  Elf32_Word hwp_flags1;	/* Extra flags.  */
-  Elf32_Word hwp_flags2;	/* Extra flags.  */
-} Elf_Options_Hw;
-
-/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */
-
-#define OHWA0_R4KEOP_CHECKED	0x00000001
-#define OHWA1_R4KEOP_CLEAN	0x00000002
-
-/* MIPS relocs.  */
-
-#define R_MIPS_NONE		0	/* No reloc */
-#define R_MIPS_16		1	/* Direct 16 bit */
-#define R_MIPS_32		2	/* Direct 32 bit */
-#define R_MIPS_REL32		3	/* PC relative 32 bit */
-#define R_MIPS_26		4	/* Direct 26 bit shifted */
-#define R_MIPS_HI16		5	/* High 16 bit */
-#define R_MIPS_LO16		6	/* Low 16 bit */
-#define R_MIPS_GPREL16		7	/* GP relative 16 bit */
-#define R_MIPS_LITERAL		8	/* 16 bit literal entry */
-#define R_MIPS_GOT16		9	/* 16 bit GOT entry */
-#define R_MIPS_PC16		10	/* PC relative 16 bit */
-#define R_MIPS_CALL16		11	/* 16 bit GOT entry for function */
-#define R_MIPS_GPREL32		12	/* GP relative 32 bit */
-
-#define R_MIPS_SHIFT5		16
-#define R_MIPS_SHIFT6		17
-#define R_MIPS_64		18
-#define R_MIPS_GOT_DISP		19
-#define R_MIPS_GOT_PAGE		20
-#define R_MIPS_GOT_OFST		21
-#define R_MIPS_GOT_HI16		22
-#define R_MIPS_GOT_LO16		23
-#define R_MIPS_SUB		24
-#define R_MIPS_INSERT_A		25
-#define R_MIPS_INSERT_B		26
-#define R_MIPS_DELETE		27
-#define R_MIPS_HIGHER		28
-#define R_MIPS_HIGHEST		29
-#define R_MIPS_CALL_HI16	30
-#define R_MIPS_CALL_LO16	31
-#define R_MIPS_SCN_DISP		32
-#define R_MIPS_REL16		33
-#define R_MIPS_ADD_IMMEDIATE	34
-#define R_MIPS_PJUMP		35
-#define R_MIPS_RELGOT		36
-#define R_MIPS_JALR		37
-#define R_MIPS_TLS_DTPMOD32	38	/* Module number 32 bit */
-#define R_MIPS_TLS_DTPREL32	39	/* Module-relative offset 32 bit */
-#define R_MIPS_TLS_DTPMOD64	40	/* Module number 64 bit */
-#define R_MIPS_TLS_DTPREL64	41	/* Module-relative offset 64 bit */
-#define R_MIPS_TLS_GD		42	/* 16 bit GOT offset for GD */
-#define R_MIPS_TLS_LDM		43	/* 16 bit GOT offset for LDM */
-#define R_MIPS_TLS_DTPREL_HI16	44	/* Module-relative offset, high 16 bits */
-#define R_MIPS_TLS_DTPREL_LO16	45	/* Module-relative offset, low 16 bits */
-#define R_MIPS_TLS_GOTTPREL	46	/* 16 bit GOT offset for IE */
-#define R_MIPS_TLS_TPREL32	47	/* TP-relative offset, 32 bit */
-#define R_MIPS_TLS_TPREL64	48	/* TP-relative offset, 64 bit */
-#define R_MIPS_TLS_TPREL_HI16	49	/* TP-relative offset, high 16 bits */
-#define R_MIPS_TLS_TPREL_LO16	50	/* TP-relative offset, low 16 bits */
-#define R_MIPS_GLOB_DAT		51
-/* Keep this the last entry.  */
-#define R_MIPS_NUM		52
-
-/* Legal values for p_type field of Elf32_Phdr.  */
-
-#define PT_MIPS_REGINFO	0x70000000	/* Register usage information */
-#define PT_MIPS_RTPROC  0x70000001	/* Runtime procedure table. */
-#define PT_MIPS_OPTIONS 0x70000002
-
-/* Special program header types.  */
-
-#define PF_MIPS_LOCAL	0x10000000
-
-/* Legal values for d_tag field of Elf32_Dyn.  */
-
-#define DT_MIPS_RLD_VERSION  0x70000001	/* Runtime linker interface version */
-#define DT_MIPS_TIME_STAMP   0x70000002	/* Timestamp */
-#define DT_MIPS_ICHECKSUM    0x70000003	/* Checksum */
-#define DT_MIPS_IVERSION     0x70000004	/* Version string (string tbl index) */
-#define DT_MIPS_FLAGS	     0x70000005	/* Flags */
-#define DT_MIPS_BASE_ADDRESS 0x70000006	/* Base address */
-#define DT_MIPS_MSYM	     0x70000007
-#define DT_MIPS_CONFLICT     0x70000008	/* Address of CONFLICT section */
-#define DT_MIPS_LIBLIST	     0x70000009	/* Address of LIBLIST section */
-#define DT_MIPS_LOCAL_GOTNO  0x7000000a	/* Number of local GOT entries */
-#define DT_MIPS_CONFLICTNO   0x7000000b	/* Number of CONFLICT entries */
-#define DT_MIPS_LIBLISTNO    0x70000010	/* Number of LIBLIST entries */
-#define DT_MIPS_SYMTABNO     0x70000011	/* Number of DYNSYM entries */
-#define DT_MIPS_UNREFEXTNO   0x70000012	/* First external DYNSYM */
-#define DT_MIPS_GOTSYM	     0x70000013	/* First GOT entry in DYNSYM */
-#define DT_MIPS_HIPAGENO     0x70000014	/* Number of GOT page table entries */
-#define DT_MIPS_RLD_MAP	     0x70000016	/* Address of run time loader map.  */
-#define DT_MIPS_DELTA_CLASS  0x70000017	/* Delta C++ class definition.  */
-#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in
-						DT_MIPS_DELTA_CLASS.  */
-#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */
-#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in
-						DT_MIPS_DELTA_INSTANCE.  */
-#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */
-#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in
-					     DT_MIPS_DELTA_RELOC.  */
-#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta
-					   relocations refer to.  */
-#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in
-					   DT_MIPS_DELTA_SYM.  */
-#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the
-					     class declaration.  */
-#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in
-						DT_MIPS_DELTA_CLASSSYM.  */
-#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */
-#define DT_MIPS_PIXIE_INIT   0x70000023
-#define DT_MIPS_SYMBOL_LIB   0x70000024
-#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025
-#define DT_MIPS_LOCAL_GOTIDX 0x70000026
-#define DT_MIPS_HIDDEN_GOTIDX 0x70000027
-#define DT_MIPS_PROTECTED_GOTIDX 0x70000028
-#define DT_MIPS_OPTIONS	     0x70000029 /* Address of .options.  */
-#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */
-#define DT_MIPS_DYNSTR_ALIGN 0x7000002b
-#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */
-#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve
-						    function stored in GOT.  */
-#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added
-					   by rld on dlopen() calls.  */
-#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */
-#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */
-#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */
-#define DT_MIPS_NUM	     0x32
-
-/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */
-
-#define RHF_NONE		   0		/* No flags */
-#define RHF_QUICKSTART		   (1 << 0)	/* Use quickstart */
-#define RHF_NOTPOT		   (1 << 1)	/* Hash size not power of 2 */
-#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)	/* Ignore LD_LIBRARY_PATH */
-#define RHF_NO_MOVE		   (1 << 3)
-#define RHF_SGI_ONLY		   (1 << 4)
-#define RHF_GUARANTEE_INIT	   (1 << 5)
-#define RHF_DELTA_C_PLUS_PLUS	   (1 << 6)
-#define RHF_GUARANTEE_START_INIT   (1 << 7)
-#define RHF_PIXIE		   (1 << 8)
-#define RHF_DEFAULT_DELAY_LOAD	   (1 << 9)
-#define RHF_REQUICKSTART	   (1 << 10)
-#define RHF_REQUICKSTARTED	   (1 << 11)
-#define RHF_CORD		   (1 << 12)
-#define RHF_NO_UNRES_UNDEF	   (1 << 13)
-#define RHF_RLD_ORDER_SAFE	   (1 << 14)
-
-/* Entries found in sections of type SHT_MIPS_LIBLIST.  */
-
-typedef struct
-{
-  Elf32_Word l_name;		/* Name (string table index) */
-  Elf32_Word l_time_stamp;	/* Timestamp */
-  Elf32_Word l_checksum;	/* Checksum */
-  Elf32_Word l_version;		/* Interface version */
-  Elf32_Word l_flags;		/* Flags */
-} Elf32_Lib;
-
-typedef struct
-{
-  Elf64_Word l_name;		/* Name (string table index) */
-  Elf64_Word l_time_stamp;	/* Timestamp */
-  Elf64_Word l_checksum;	/* Checksum */
-  Elf64_Word l_version;		/* Interface version */
-  Elf64_Word l_flags;		/* Flags */
-} Elf64_Lib;
-
-
-/* Legal values for l_flags.  */
-
-#define LL_NONE		  0
-#define LL_EXACT_MATCH	  (1 << 0)	/* Require exact match */
-#define LL_IGNORE_INT_VER (1 << 1)	/* Ignore interface version */
-#define LL_REQUIRE_MINOR  (1 << 2)
-#define LL_EXPORTS	  (1 << 3)
-#define LL_DELAY_LOAD	  (1 << 4)
-#define LL_DELTA	  (1 << 5)
-
-/* Entries found in sections of type SHT_MIPS_CONFLICT.  */
-
-typedef Elf32_Addr Elf32_Conflict;
-
-
-/* HPPA specific definitions.  */
-
-/* Legal values for e_flags field of Elf32_Ehdr.  */
-
-#define EF_PARISC_TRAPNIL	0x00010000 /* Trap nil pointer dereference.  */
-#define EF_PARISC_EXT		0x00020000 /* Program uses arch. extensions. */
-#define EF_PARISC_LSB		0x00040000 /* Program expects little endian. */
-#define EF_PARISC_WIDE		0x00080000 /* Program expects wide mode.  */
-#define EF_PARISC_NO_KABP	0x00100000 /* No kernel assisted branch
-					      prediction.  */
-#define EF_PARISC_LAZYSWAP	0x00400000 /* Allow lazy swapping.  */
-#define EF_PARISC_ARCH		0x0000ffff /* Architecture version.  */
-
-/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */
-
-#define EFA_PARISC_1_0		    0x020b /* PA-RISC 1.0 big-endian.  */
-#define EFA_PARISC_1_1		    0x0210 /* PA-RISC 1.1 big-endian.  */
-#define EFA_PARISC_2_0		    0x0214 /* PA-RISC 2.0 big-endian.  */
-
-/* Additional section indeces.  */
-
-#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tenatively declared
-					      symbols in ANSI C.  */
-#define SHN_PARISC_HUGE_COMMON	0xff01	   /* Common blocks in huge model.  */
-
-/* Legal values for sh_type field of Elf32_Shdr.  */
-
-#define SHT_PARISC_EXT		0x70000000 /* Contains product specific ext. */
-#define SHT_PARISC_UNWIND	0x70000001 /* Unwind information.  */
-#define SHT_PARISC_DOC		0x70000002 /* Debug info for optimized code. */
-
-/* Legal values for sh_flags field of Elf32_Shdr.  */
-
-#define SHF_PARISC_SHORT	0x20000000 /* Section with short addressing. */
-#define SHF_PARISC_HUGE		0x40000000 /* Section far from gp.  */
-#define SHF_PARISC_SBP		0x80000000 /* Static branch prediction code. */
-
-/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
-
-#define STT_PARISC_MILLICODE	13	/* Millicode function entry point.  */
-
-#define STT_HP_OPAQUE		(STT_LOOS + 0x1)
-#define STT_HP_STUB		(STT_LOOS + 0x2)
-
-/* HPPA relocs.  */
-
-#define R_PARISC_NONE		0	/* No reloc.  */
-#define R_PARISC_DIR32		1	/* Direct 32-bit reference.  */
-#define R_PARISC_DIR21L		2	/* Left 21 bits of eff. address.  */
-#define R_PARISC_DIR17R		3	/* Right 17 bits of eff. address.  */
-#define R_PARISC_DIR17F		4	/* 17 bits of eff. address.  */
-#define R_PARISC_DIR14R		6	/* Right 14 bits of eff. address.  */
-#define R_PARISC_PCREL32	9	/* 32-bit rel. address.  */
-#define R_PARISC_PCREL21L	10	/* Left 21 bits of rel. address.  */
-#define R_PARISC_PCREL17R	11	/* Right 17 bits of rel. address.  */
-#define R_PARISC_PCREL17F	12	/* 17 bits of rel. address.  */
-#define R_PARISC_PCREL14R	14	/* Right 14 bits of rel. address.  */
-#define R_PARISC_DPREL21L	18	/* Left 21 bits of rel. address.  */
-#define R_PARISC_DPREL14R	22	/* Right 14 bits of rel. address.  */
-#define R_PARISC_GPREL21L	26	/* GP-relative, left 21 bits.  */
-#define R_PARISC_GPREL14R	30	/* GP-relative, right 14 bits.  */
-#define R_PARISC_LTOFF21L	34	/* LT-relative, left 21 bits.  */
-#define R_PARISC_LTOFF14R	38	/* LT-relative, right 14 bits.  */
-#define R_PARISC_SECREL32	41	/* 32 bits section rel. address.  */
-#define R_PARISC_SEGBASE	48	/* No relocation, set segment base.  */
-#define R_PARISC_SEGREL32	49	/* 32 bits segment rel. address.  */
-#define R_PARISC_PLTOFF21L	50	/* PLT rel. address, left 21 bits.  */
-#define R_PARISC_PLTOFF14R	54	/* PLT rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF_FPTR32	57	/* 32 bits LT-rel. function pointer. */
-#define R_PARISC_LTOFF_FPTR21L	58	/* LT-rel. fct ptr, left 21 bits. */
-#define R_PARISC_LTOFF_FPTR14R	62	/* LT-rel. fct ptr, right 14 bits. */
-#define R_PARISC_FPTR64		64	/* 64 bits function address.  */
-#define R_PARISC_PLABEL32	65	/* 32 bits function address.  */
-#define R_PARISC_PLABEL21L	66	/* Left 21 bits of fdesc address.  */
-#define R_PARISC_PLABEL14R	70	/* Right 14 bits of fdesc address.  */
-#define R_PARISC_PCREL64	72	/* 64 bits PC-rel. address.  */
-#define R_PARISC_PCREL22F	74	/* 22 bits PC-rel. address.  */
-#define R_PARISC_PCREL14WR	75	/* PC-rel. address, right 14 bits.  */
-#define R_PARISC_PCREL14DR	76	/* PC rel. address, right 14 bits.  */
-#define R_PARISC_PCREL16F	77	/* 16 bits PC-rel. address.  */
-#define R_PARISC_PCREL16WF	78	/* 16 bits PC-rel. address.  */
-#define R_PARISC_PCREL16DF	79	/* 16 bits PC-rel. address.  */
-#define R_PARISC_DIR64		80	/* 64 bits of eff. address.  */
-#define R_PARISC_DIR14WR	83	/* 14 bits of eff. address.  */
-#define R_PARISC_DIR14DR	84	/* 14 bits of eff. address.  */
-#define R_PARISC_DIR16F		85	/* 16 bits of eff. address.  */
-#define R_PARISC_DIR16WF	86	/* 16 bits of eff. address.  */
-#define R_PARISC_DIR16DF	87	/* 16 bits of eff. address.  */
-#define R_PARISC_GPREL64	88	/* 64 bits of GP-rel. address.  */
-#define R_PARISC_GPREL14WR	91	/* GP-rel. address, right 14 bits.  */
-#define R_PARISC_GPREL14DR	92	/* GP-rel. address, right 14 bits.  */
-#define R_PARISC_GPREL16F	93	/* 16 bits GP-rel. address.  */
-#define R_PARISC_GPREL16WF	94	/* 16 bits GP-rel. address.  */
-#define R_PARISC_GPREL16DF	95	/* 16 bits GP-rel. address.  */
-#define R_PARISC_LTOFF64	96	/* 64 bits LT-rel. address.  */
-#define R_PARISC_LTOFF14WR	99	/* LT-rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF14DR	100	/* LT-rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF16F	101	/* 16 bits LT-rel. address.  */
-#define R_PARISC_LTOFF16WF	102	/* 16 bits LT-rel. address.  */
-#define R_PARISC_LTOFF16DF	103	/* 16 bits LT-rel. address.  */
-#define R_PARISC_SECREL64	104	/* 64 bits section rel. address.  */
-#define R_PARISC_SEGREL64	112	/* 64 bits segment rel. address.  */
-#define R_PARISC_PLTOFF14WR	115	/* PLT-rel. address, right 14 bits.  */
-#define R_PARISC_PLTOFF14DR	116	/* PLT-rel. address, right 14 bits.  */
-#define R_PARISC_PLTOFF16F	117	/* 16 bits LT-rel. address.  */
-#define R_PARISC_PLTOFF16WF	118	/* 16 bits PLT-rel. address.  */
-#define R_PARISC_PLTOFF16DF	119	/* 16 bits PLT-rel. address.  */
-#define R_PARISC_LTOFF_FPTR64	120	/* 64 bits LT-rel. function ptr.  */
-#define R_PARISC_LTOFF_FPTR14WR	123	/* LT-rel. fct. ptr., right 14 bits. */
-#define R_PARISC_LTOFF_FPTR14DR	124	/* LT-rel. fct. ptr., right 14 bits. */
-#define R_PARISC_LTOFF_FPTR16F	125	/* 16 bits LT-rel. function ptr.  */
-#define R_PARISC_LTOFF_FPTR16WF	126	/* 16 bits LT-rel. function ptr.  */
-#define R_PARISC_LTOFF_FPTR16DF	127	/* 16 bits LT-rel. function ptr.  */
-#define R_PARISC_LORESERVE	128
-#define R_PARISC_COPY		128	/* Copy relocation.  */
-#define R_PARISC_IPLT		129	/* Dynamic reloc, imported PLT */
-#define R_PARISC_EPLT		130	/* Dynamic reloc, exported PLT */
-#define R_PARISC_TPREL32	153	/* 32 bits TP-rel. address.  */
-#define R_PARISC_TPREL21L	154	/* TP-rel. address, left 21 bits.  */
-#define R_PARISC_TPREL14R	158	/* TP-rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF_TP21L	162	/* LT-TP-rel. address, left 21 bits. */
-#define R_PARISC_LTOFF_TP14R	166	/* LT-TP-rel. address, right 14 bits.*/
-#define R_PARISC_LTOFF_TP14F	167	/* 14 bits LT-TP-rel. address.  */
-#define R_PARISC_TPREL64	216	/* 64 bits TP-rel. address.  */
-#define R_PARISC_TPREL14WR	219	/* TP-rel. address, right 14 bits.  */
-#define R_PARISC_TPREL14DR	220	/* TP-rel. address, right 14 bits.  */
-#define R_PARISC_TPREL16F	221	/* 16 bits TP-rel. address.  */
-#define R_PARISC_TPREL16WF	222	/* 16 bits TP-rel. address.  */
-#define R_PARISC_TPREL16DF	223	/* 16 bits TP-rel. address.  */
-#define R_PARISC_LTOFF_TP64	224	/* 64 bits LT-TP-rel. address.  */
-#define R_PARISC_LTOFF_TP14WR	227	/* LT-TP-rel. address, right 14 bits.*/
-#define R_PARISC_LTOFF_TP14DR	228	/* LT-TP-rel. address, right 14 bits.*/
-#define R_PARISC_LTOFF_TP16F	229	/* 16 bits LT-TP-rel. address.  */
-#define R_PARISC_LTOFF_TP16WF	230	/* 16 bits LT-TP-rel. address.  */
-#define R_PARISC_LTOFF_TP16DF	231	/* 16 bits LT-TP-rel. address.  */
-#define R_PARISC_GNU_VTENTRY	232
-#define R_PARISC_GNU_VTINHERIT	233
-#define R_PARISC_TLS_GD21L	234	/* GD 21-bit left.  */
-#define R_PARISC_TLS_GD14R	235	/* GD 14-bit right.  */
-#define R_PARISC_TLS_GDCALL	236	/* GD call to __t_g_a.  */
-#define R_PARISC_TLS_LDM21L	237	/* LD module 21-bit left.  */
-#define R_PARISC_TLS_LDM14R	238	/* LD module 14-bit right.  */
-#define R_PARISC_TLS_LDMCALL	239	/* LD module call to __t_g_a.  */
-#define R_PARISC_TLS_LDO21L	240	/* LD offset 21-bit left.  */
-#define R_PARISC_TLS_LDO14R	241	/* LD offset 14-bit right.  */
-#define R_PARISC_TLS_DTPMOD32	242	/* DTP module 32-bit.  */
-#define R_PARISC_TLS_DTPMOD64	243	/* DTP module 64-bit.  */
-#define R_PARISC_TLS_DTPOFF32	244	/* DTP offset 32-bit.  */
-#define R_PARISC_TLS_DTPOFF64	245	/* DTP offset 32-bit.  */
-#define R_PARISC_TLS_LE21L	R_PARISC_TPREL21L
-#define R_PARISC_TLS_LE14R	R_PARISC_TPREL14R
-#define R_PARISC_TLS_IE21L	R_PARISC_LTOFF_TP21L
-#define R_PARISC_TLS_IE14R	R_PARISC_LTOFF_TP14R
-#define R_PARISC_TLS_TPREL32	R_PARISC_TPREL32
-#define R_PARISC_TLS_TPREL64	R_PARISC_TPREL64
-#define R_PARISC_HIRESERVE	255
-
-/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */
-
-#define PT_HP_TLS		(PT_LOOS + 0x0)
-#define PT_HP_CORE_NONE		(PT_LOOS + 0x1)
-#define PT_HP_CORE_VERSION	(PT_LOOS + 0x2)
-#define PT_HP_CORE_KERNEL	(PT_LOOS + 0x3)
-#define PT_HP_CORE_COMM		(PT_LOOS + 0x4)
-#define PT_HP_CORE_PROC		(PT_LOOS + 0x5)
-#define PT_HP_CORE_LOADABLE	(PT_LOOS + 0x6)
-#define PT_HP_CORE_STACK	(PT_LOOS + 0x7)
-#define PT_HP_CORE_SHM		(PT_LOOS + 0x8)
-#define PT_HP_CORE_MMF		(PT_LOOS + 0x9)
-#define PT_HP_PARALLEL		(PT_LOOS + 0x10)
-#define PT_HP_FASTBIND		(PT_LOOS + 0x11)
-#define PT_HP_OPT_ANNOT		(PT_LOOS + 0x12)
-#define PT_HP_HSL_ANNOT		(PT_LOOS + 0x13)
-#define PT_HP_STACK		(PT_LOOS + 0x14)
-
-#define PT_PARISC_ARCHEXT	0x70000000
-#define PT_PARISC_UNWIND	0x70000001
-
-/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */
-
-#define PF_PARISC_SBP		0x08000000
-
-#define PF_HP_PAGE_SIZE		0x00100000
-#define PF_HP_FAR_SHARED	0x00200000
-#define PF_HP_NEAR_SHARED	0x00400000
-#define PF_HP_CODE		0x01000000
-#define PF_HP_MODIFY		0x02000000
-#define PF_HP_LAZYSWAP		0x04000000
-#define PF_HP_SBP		0x08000000
-
-
-/* Alpha specific definitions.  */
-
-/* Legal values for e_flags field of Elf64_Ehdr.  */
-
-#define EF_ALPHA_32BIT		1	/* All addresses must be < 2GB.  */
-#define EF_ALPHA_CANRELAX	2	/* Relocations for relaxing exist.  */
-
-/* Legal values for sh_type field of Elf64_Shdr.  */
-
-/* These two are primerily concerned with ECOFF debugging info.  */
-#define SHT_ALPHA_DEBUG		0x70000001
-#define SHT_ALPHA_REGINFO	0x70000002
-
-/* Legal values for sh_flags field of Elf64_Shdr.  */
-
-#define SHF_ALPHA_GPREL		0x10000000
-
-/* Legal values for st_other field of Elf64_Sym.  */
-#define STO_ALPHA_NOPV		0x80	/* No PV required.  */
-#define STO_ALPHA_STD_GPLOAD	0x88	/* PV only used for initial ldgp.  */
-
-/* Alpha relocs.  */
-
-#define R_ALPHA_NONE		0	/* No reloc */
-#define R_ALPHA_REFLONG		1	/* Direct 32 bit */
-#define R_ALPHA_REFQUAD		2	/* Direct 64 bit */
-#define R_ALPHA_GPREL32		3	/* GP relative 32 bit */
-#define R_ALPHA_LITERAL		4	/* GP relative 16 bit w/optimization */
-#define R_ALPHA_LITUSE		5	/* Optimization hint for LITERAL */
-#define R_ALPHA_GPDISP		6	/* Add displacement to GP */
-#define R_ALPHA_BRADDR		7	/* PC+4 relative 23 bit shifted */
-#define R_ALPHA_HINT		8	/* PC+4 relative 16 bit shifted */
-#define R_ALPHA_SREL16		9	/* PC relative 16 bit */
-#define R_ALPHA_SREL32		10	/* PC relative 32 bit */
-#define R_ALPHA_SREL64		11	/* PC relative 64 bit */
-#define R_ALPHA_GPRELHIGH	17	/* GP relative 32 bit, high 16 bits */
-#define R_ALPHA_GPRELLOW	18	/* GP relative 32 bit, low 16 bits */
-#define R_ALPHA_GPREL16		19	/* GP relative 16 bit */
-#define R_ALPHA_COPY		24	/* Copy symbol at runtime */
-#define R_ALPHA_GLOB_DAT	25	/* Create GOT entry */
-#define R_ALPHA_JMP_SLOT	26	/* Create PLT entry */
-#define R_ALPHA_RELATIVE	27	/* Adjust by program base */
-#define R_ALPHA_TLS_GD_HI	28
-#define R_ALPHA_TLSGD		29
-#define R_ALPHA_TLS_LDM		30
-#define R_ALPHA_DTPMOD64	31
-#define R_ALPHA_GOTDTPREL	32
-#define R_ALPHA_DTPREL64	33
-#define R_ALPHA_DTPRELHI	34
-#define R_ALPHA_DTPRELLO	35
-#define R_ALPHA_DTPREL16	36
-#define R_ALPHA_GOTTPREL	37
-#define R_ALPHA_TPREL64		38
-#define R_ALPHA_TPRELHI		39
-#define R_ALPHA_TPRELLO		40
-#define R_ALPHA_TPREL16		41
-/* Keep this the last entry.  */
-#define R_ALPHA_NUM		46
-
-/* Magic values of the LITUSE relocation addend.  */
-#define LITUSE_ALPHA_ADDR	0
-#define LITUSE_ALPHA_BASE	1
-#define LITUSE_ALPHA_BYTOFF	2
-#define LITUSE_ALPHA_JSR	3
-#define LITUSE_ALPHA_TLS_GD	4
-#define LITUSE_ALPHA_TLS_LDM	5
-
-/* Legal values for d_tag of Elf64_Dyn.  */
-#define DT_ALPHA_PLTRO		(DT_LOPROC + 0)
-#define DT_ALPHA_NUM		1
-
-/* PowerPC specific declarations */
-
-/* Values for Elf32/64_Ehdr.e_flags.  */
-#define EF_PPC_EMB		0x80000000	/* PowerPC embedded flag */
-
-/* Cygnus local bits below */
-#define EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag*/
-#define EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib
-						   flag */
-
-/* PowerPC relocations defined by the ABIs */
-#define R_PPC_NONE		0
-#define R_PPC_ADDR32		1	/* 32bit absolute address */
-#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored.  */
-#define R_PPC_ADDR16		3	/* 16bit absolute address */
-#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
-#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
-#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
-#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
-#define R_PPC_ADDR14_BRTAKEN	8
-#define R_PPC_ADDR14_BRNTAKEN	9
-#define R_PPC_REL24		10	/* PC relative 26 bit */
-#define R_PPC_REL14		11	/* PC relative 16 bit */
-#define R_PPC_REL14_BRTAKEN	12
-#define R_PPC_REL14_BRNTAKEN	13
-#define R_PPC_GOT16		14
-#define R_PPC_GOT16_LO		15
-#define R_PPC_GOT16_HI		16
-#define R_PPC_GOT16_HA		17
-#define R_PPC_PLTREL24		18
-#define R_PPC_COPY		19
-#define R_PPC_GLOB_DAT		20
-#define R_PPC_JMP_SLOT		21
-#define R_PPC_RELATIVE		22
-#define R_PPC_LOCAL24PC		23
-#define R_PPC_UADDR32		24
-#define R_PPC_UADDR16		25
-#define R_PPC_REL32		26
-#define R_PPC_PLT32		27
-#define R_PPC_PLTREL32		28
-#define R_PPC_PLT16_LO		29
-#define R_PPC_PLT16_HI		30
-#define R_PPC_PLT16_HA		31
-#define R_PPC_SDAREL16		32
-#define R_PPC_SECTOFF		33
-#define R_PPC_SECTOFF_LO	34
-#define R_PPC_SECTOFF_HI	35
-#define R_PPC_SECTOFF_HA	36
-
-/* PowerPC relocations defined for the TLS access ABI.  */
-#define R_PPC_TLS		67 /* none	(sym+add)@tls */
-#define R_PPC_DTPMOD32		68 /* word32	(sym+add)@dtpmod */
-#define R_PPC_TPREL16		69 /* half16*	(sym+add)@tprel */
-#define R_PPC_TPREL16_LO	70 /* half16	(sym+add)@tprel at l */
-#define R_PPC_TPREL16_HI	71 /* half16	(sym+add)@tprel at h */
-#define R_PPC_TPREL16_HA	72 /* half16	(sym+add)@tprel at ha */
-#define R_PPC_TPREL32		73 /* word32	(sym+add)@tprel */
-#define R_PPC_DTPREL16		74 /* half16*	(sym+add)@dtprel */
-#define R_PPC_DTPREL16_LO	75 /* half16	(sym+add)@dtprel at l */
-#define R_PPC_DTPREL16_HI	76 /* half16	(sym+add)@dtprel at h */
-#define R_PPC_DTPREL16_HA	77 /* half16	(sym+add)@dtprel at ha */
-#define R_PPC_DTPREL32		78 /* word32	(sym+add)@dtprel */
-#define R_PPC_GOT_TLSGD16	79 /* half16*	(sym+add)@got at tlsgd */
-#define R_PPC_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got at tlsgd@l */
-#define R_PPC_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got at tlsgd@h */
-#define R_PPC_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got at tlsgd@ha */
-#define R_PPC_GOT_TLSLD16	83 /* half16*	(sym+add)@got at tlsld */
-#define R_PPC_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got at tlsld@l */
-#define R_PPC_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got at tlsld@h */
-#define R_PPC_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got at tlsld@ha */
-#define R_PPC_GOT_TPREL16	87 /* half16*	(sym+add)@got at tprel */
-#define R_PPC_GOT_TPREL16_LO	88 /* half16	(sym+add)@got at tprel@l */
-#define R_PPC_GOT_TPREL16_HI	89 /* half16	(sym+add)@got at tprel@h */
-#define R_PPC_GOT_TPREL16_HA	90 /* half16	(sym+add)@got at tprel@ha */
-#define R_PPC_GOT_DTPREL16	91 /* half16*	(sym+add)@got at dtprel */
-#define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got at dtprel@l */
-#define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got at dtprel@h */
-#define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got at dtprel@ha */
-
-/* Keep this the last entry.  */
-#define R_PPC_NUM		95
-
-/* The remaining relocs are from the Embedded ELF ABI, and are not
-   in the SVR4 ELF ABI.  */
-#define R_PPC_EMB_NADDR32	101
-#define R_PPC_EMB_NADDR16	102
-#define R_PPC_EMB_NADDR16_LO	103
-#define R_PPC_EMB_NADDR16_HI	104
-#define R_PPC_EMB_NADDR16_HA	105
-#define R_PPC_EMB_SDAI16	106
-#define R_PPC_EMB_SDA2I16	107
-#define R_PPC_EMB_SDA2REL	108
-#define R_PPC_EMB_SDA21		109	/* 16 bit offset in SDA */
-#define R_PPC_EMB_MRKREF	110
-#define R_PPC_EMB_RELSEC16	111
-#define R_PPC_EMB_RELST_LO	112
-#define R_PPC_EMB_RELST_HI	113
-#define R_PPC_EMB_RELST_HA	114
-#define R_PPC_EMB_BIT_FLD	115
-#define R_PPC_EMB_RELSDA	116	/* 16 bit relative offset in SDA */
-
-/* Diab tool relocations.  */
-#define R_PPC_DIAB_SDA21_LO	180	/* like EMB_SDA21, but lower 16 bit */
-#define R_PPC_DIAB_SDA21_HI	181	/* like EMB_SDA21, but high 16 bit */
-#define R_PPC_DIAB_SDA21_HA	182	/* like EMB_SDA21, adjusted high 16 */
-#define R_PPC_DIAB_RELSDA_LO	183	/* like EMB_RELSDA, but lower 16 bit */
-#define R_PPC_DIAB_RELSDA_HI	184	/* like EMB_RELSDA, but high 16 bit */
-#define R_PPC_DIAB_RELSDA_HA	185	/* like EMB_RELSDA, adjusted high 16 */
-
-/* GNU relocs used in PIC code sequences.  */
-#define R_PPC_REL16		249	/* word32   (sym-.) */
-#define R_PPC_REL16_LO		250	/* half16   (sym-.)@l */
-#define R_PPC_REL16_HI		251	/* half16   (sym-.)@h */
-#define R_PPC_REL16_HA		252	/* half16   (sym-.)@ha */
-
-/* This is a phony reloc to handle any old fashioned TOC16 references
-   that may still be in object files.  */
-#define R_PPC_TOC16		255
-
-/* PowerPC specific values for the Dyn d_tag field.  */
-#define DT_PPC_GOT		(DT_LOPROC + 0)
-#define DT_PPC_NUM		1
-
-/* PowerPC64 relocations defined by the ABIs */
-#define R_PPC64_NONE		R_PPC_NONE
-#define R_PPC64_ADDR32		R_PPC_ADDR32 /* 32bit absolute address */
-#define R_PPC64_ADDR24		R_PPC_ADDR24 /* 26bit address, word aligned */
-#define R_PPC64_ADDR16		R_PPC_ADDR16 /* 16bit absolute address */
-#define R_PPC64_ADDR16_LO	R_PPC_ADDR16_LO	/* lower 16bits of address */
-#define R_PPC64_ADDR16_HI	R_PPC_ADDR16_HI	/* high 16bits of address. */
-#define R_PPC64_ADDR16_HA	R_PPC_ADDR16_HA /* adjusted high 16bits.  */
-#define R_PPC64_ADDR14		R_PPC_ADDR14 /* 16bit address, word aligned */
-#define R_PPC64_ADDR14_BRTAKEN	R_PPC_ADDR14_BRTAKEN
-#define R_PPC64_ADDR14_BRNTAKEN	R_PPC_ADDR14_BRNTAKEN
-#define R_PPC64_REL24		R_PPC_REL24 /* PC-rel. 26 bit, word aligned */
-#define R_PPC64_REL14		R_PPC_REL14 /* PC relative 16 bit */
-#define R_PPC64_REL14_BRTAKEN	R_PPC_REL14_BRTAKEN
-#define R_PPC64_REL14_BRNTAKEN	R_PPC_REL14_BRNTAKEN
-#define R_PPC64_GOT16		R_PPC_GOT16
-#define R_PPC64_GOT16_LO	R_PPC_GOT16_LO
-#define R_PPC64_GOT16_HI	R_PPC_GOT16_HI
-#define R_PPC64_GOT16_HA	R_PPC_GOT16_HA
-
-#define R_PPC64_COPY		R_PPC_COPY
-#define R_PPC64_GLOB_DAT	R_PPC_GLOB_DAT
-#define R_PPC64_JMP_SLOT	R_PPC_JMP_SLOT
-#define R_PPC64_RELATIVE	R_PPC_RELATIVE
-
-#define R_PPC64_UADDR32		R_PPC_UADDR32
-#define R_PPC64_UADDR16		R_PPC_UADDR16
-#define R_PPC64_REL32		R_PPC_REL32
-#define R_PPC64_PLT32		R_PPC_PLT32
-#define R_PPC64_PLTREL32	R_PPC_PLTREL32
-#define R_PPC64_PLT16_LO	R_PPC_PLT16_LO
-#define R_PPC64_PLT16_HI	R_PPC_PLT16_HI
-#define R_PPC64_PLT16_HA	R_PPC_PLT16_HA
-
-#define R_PPC64_SECTOFF		R_PPC_SECTOFF
-#define R_PPC64_SECTOFF_LO	R_PPC_SECTOFF_LO
-#define R_PPC64_SECTOFF_HI	R_PPC_SECTOFF_HI
-#define R_PPC64_SECTOFF_HA	R_PPC_SECTOFF_HA
-#define R_PPC64_ADDR30		37 /* word30 (S + A - P) >> 2 */
-#define R_PPC64_ADDR64		38 /* doubleword64 S + A */
-#define R_PPC64_ADDR16_HIGHER	39 /* half16 #higher(S + A) */
-#define R_PPC64_ADDR16_HIGHERA	40 /* half16 #highera(S + A) */
-#define R_PPC64_ADDR16_HIGHEST	41 /* half16 #highest(S + A) */
-#define R_PPC64_ADDR16_HIGHESTA	42 /* half16 #highesta(S + A) */
-#define R_PPC64_UADDR64		43 /* doubleword64 S + A */
-#define R_PPC64_REL64		44 /* doubleword64 S + A - P */
-#define R_PPC64_PLT64		45 /* doubleword64 L + A */
-#define R_PPC64_PLTREL64	46 /* doubleword64 L + A - P */
-#define R_PPC64_TOC16		47 /* half16* S + A - .TOC */
-#define R_PPC64_TOC16_LO	48 /* half16 #lo(S + A - .TOC.) */
-#define R_PPC64_TOC16_HI	49 /* half16 #hi(S + A - .TOC.) */
-#define R_PPC64_TOC16_HA	50 /* half16 #ha(S + A - .TOC.) */
-#define R_PPC64_TOC		51 /* doubleword64 .TOC */
-#define R_PPC64_PLTGOT16	52 /* half16* M + A */
-#define R_PPC64_PLTGOT16_LO	53 /* half16 #lo(M + A) */
-#define R_PPC64_PLTGOT16_HI	54 /* half16 #hi(M + A) */
-#define R_PPC64_PLTGOT16_HA	55 /* half16 #ha(M + A) */
-
-#define R_PPC64_ADDR16_DS	56 /* half16ds* (S + A) >> 2 */
-#define R_PPC64_ADDR16_LO_DS	57 /* half16ds  #lo(S + A) >> 2 */
-#define R_PPC64_GOT16_DS	58 /* half16ds* (G + A) >> 2 */
-#define R_PPC64_GOT16_LO_DS	59 /* half16ds  #lo(G + A) >> 2 */
-#define R_PPC64_PLT16_LO_DS	60 /* half16ds  #lo(L + A) >> 2 */
-#define R_PPC64_SECTOFF_DS	61 /* half16ds* (R + A) >> 2 */
-#define R_PPC64_SECTOFF_LO_DS	62 /* half16ds  #lo(R + A) >> 2 */
-#define R_PPC64_TOC16_DS	63 /* half16ds* (S + A - .TOC.) >> 2 */
-#define R_PPC64_TOC16_LO_DS	64 /* half16ds  #lo(S + A - .TOC.) >> 2 */
-#define R_PPC64_PLTGOT16_DS	65 /* half16ds* (M + A) >> 2 */
-#define R_PPC64_PLTGOT16_LO_DS	66 /* half16ds  #lo(M + A) >> 2 */
-
-/* PowerPC64 relocations defined for the TLS access ABI.  */
-#define R_PPC64_TLS		67 /* none	(sym+add)@tls */
-#define R_PPC64_DTPMOD64	68 /* doubleword64 (sym+add)@dtpmod */
-#define R_PPC64_TPREL16		69 /* half16*	(sym+add)@tprel */
-#define R_PPC64_TPREL16_LO	70 /* half16	(sym+add)@tprel at l */
-#define R_PPC64_TPREL16_HI	71 /* half16	(sym+add)@tprel at h */
-#define R_PPC64_TPREL16_HA	72 /* half16	(sym+add)@tprel at ha */
-#define R_PPC64_TPREL64		73 /* doubleword64 (sym+add)@tprel */
-#define R_PPC64_DTPREL16	74 /* half16*	(sym+add)@dtprel */
-#define R_PPC64_DTPREL16_LO	75 /* half16	(sym+add)@dtprel at l */
-#define R_PPC64_DTPREL16_HI	76 /* half16	(sym+add)@dtprel at h */
-#define R_PPC64_DTPREL16_HA	77 /* half16	(sym+add)@dtprel at ha */
-#define R_PPC64_DTPREL64	78 /* doubleword64 (sym+add)@dtprel */
-#define R_PPC64_GOT_TLSGD16	79 /* half16*	(sym+add)@got at tlsgd */
-#define R_PPC64_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got at tlsgd@l */
-#define R_PPC64_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got at tlsgd@h */
-#define R_PPC64_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got at tlsgd@ha */
-#define R_PPC64_GOT_TLSLD16	83 /* half16*	(sym+add)@got at tlsld */
-#define R_PPC64_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got at tlsld@l */
-#define R_PPC64_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got at tlsld@h */
-#define R_PPC64_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got at tlsld@ha */
-#define R_PPC64_GOT_TPREL16_DS	87 /* half16ds*	(sym+add)@got at tprel */
-#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got at tprel@l */
-#define R_PPC64_GOT_TPREL16_HI	89 /* half16	(sym+add)@got at tprel@h */
-#define R_PPC64_GOT_TPREL16_HA	90 /* half16	(sym+add)@got at tprel@ha */
-#define R_PPC64_GOT_DTPREL16_DS	91 /* half16ds*	(sym+add)@got at dtprel */
-#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got at dtprel@l */
-#define R_PPC64_GOT_DTPREL16_HI	93 /* half16	(sym+add)@got at dtprel@h */
-#define R_PPC64_GOT_DTPREL16_HA	94 /* half16	(sym+add)@got at dtprel@ha */
-#define R_PPC64_TPREL16_DS	95 /* half16ds*	(sym+add)@tprel */
-#define R_PPC64_TPREL16_LO_DS	96 /* half16ds	(sym+add)@tprel at l */
-#define R_PPC64_TPREL16_HIGHER	97 /* half16	(sym+add)@tprel at higher */
-#define R_PPC64_TPREL16_HIGHERA	98 /* half16	(sym+add)@tprel at highera */
-#define R_PPC64_TPREL16_HIGHEST	99 /* half16	(sym+add)@tprel at highest */
-#define R_PPC64_TPREL16_HIGHESTA 100 /* half16	(sym+add)@tprel at highesta */
-#define R_PPC64_DTPREL16_DS	101 /* half16ds* (sym+add)@dtprel */
-#define R_PPC64_DTPREL16_LO_DS	102 /* half16ds	(sym+add)@dtprel at l */
-#define R_PPC64_DTPREL16_HIGHER	103 /* half16	(sym+add)@dtprel at higher */
-#define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel at highera */
-#define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel at highest */
-#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel at highesta */
-
-/* Keep this the last entry.  */
-#define R_PPC64_NUM		107
-
-/* PowerPC64 specific values for the Dyn d_tag field.  */
-#define DT_PPC64_GLINK  (DT_LOPROC + 0)
-#define DT_PPC64_OPD	(DT_LOPROC + 1)
-#define DT_PPC64_OPDSZ	(DT_LOPROC + 2)
-#define DT_PPC64_NUM    3
-
-
-/* ARM specific declarations */
-
-/* Processor specific flags for the ELF header e_flags field.  */
-#define EF_ARM_RELEXEC     0x01
-#define EF_ARM_HASENTRY    0x02
-#define EF_ARM_INTERWORK   0x04
-#define EF_ARM_APCS_26     0x08
-#define EF_ARM_APCS_FLOAT  0x10
-#define EF_ARM_PIC         0x20
-#define EF_ARM_ALIGN8      0x40		/* 8-bit structure alignment is in use */
-#define EF_ARM_NEW_ABI     0x80
-#define EF_ARM_OLD_ABI     0x100
-
-/* Other constants defined in the ARM ELF spec. version B-01.  */
-/* NB. These conflict with values defined above.  */
-#define EF_ARM_SYMSARESORTED	0x04
-#define EF_ARM_DYNSYMSUSESEGIDX 0x08
-#define EF_ARM_MAPSYMSFIRST	0x10
-#define EF_ARM_EABIMASK		0XFF000000
-
-#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
-#define EF_ARM_EABI_UNKNOWN  0x00000000
-#define EF_ARM_EABI_VER1     0x01000000
-#define EF_ARM_EABI_VER2     0x02000000
-
-/* Additional symbol types for Thumb */
-#define STT_ARM_TFUNC      0xd
-
-/* ARM-specific values for sh_flags */
-#define SHF_ARM_ENTRYSECT  0x10000000   /* Section contains an entry point */
-#define SHF_ARM_COMDEF     0x80000000   /* Section may be multiply defined
-					   in the input to a link step */
-
-/* ARM-specific program header flags */
-#define PF_ARM_SB          0x10000000   /* Segment contains the location
-					   addressed by the static base */
-
-/* Processor specific values for the Phdr p_type field.  */
-#define PT_ARM_EXIDX	0x70000001	/* .ARM.exidx segment */
-
-/* ARM relocs.  */
-
-#define R_ARM_NONE		0	/* No reloc */
-#define R_ARM_PC24		1	/* PC relative 26 bit branch */
-#define R_ARM_ABS32		2	/* Direct 32 bit  */
-#define R_ARM_REL32		3	/* PC relative 32 bit */
-#define R_ARM_PC13		4
-#define R_ARM_ABS16		5	/* Direct 16 bit */
-#define R_ARM_ABS12		6	/* Direct 12 bit */
-#define R_ARM_THM_ABS5		7
-#define R_ARM_ABS8		8	/* Direct 8 bit */
-#define R_ARM_SBREL32		9
-#define R_ARM_THM_PC22		10
-#define R_ARM_THM_PC8		11
-#define R_ARM_AMP_VCALL9	12
-#define R_ARM_SWI24		13
-#define R_ARM_THM_SWI8		14
-#define R_ARM_XPC25		15
-#define R_ARM_THM_XPC22		16
-#define R_ARM_TLS_DTPMOD32	17	/* ID of module containing symbol */
-#define R_ARM_TLS_DTPOFF32	18	/* Offset in TLS block */
-#define R_ARM_TLS_TPOFF32	19	/* Offset in static TLS block */
-#define R_ARM_COPY		20	/* Copy symbol at runtime */
-#define R_ARM_GLOB_DAT		21	/* Create GOT entry */
-#define R_ARM_JUMP_SLOT		22	/* Create PLT entry */
-#define R_ARM_RELATIVE		23	/* Adjust by program base */
-#define R_ARM_GOTOFF		24	/* 32 bit offset to GOT */
-#define R_ARM_GOTPC		25	/* 32 bit PC relative offset to GOT */
-#define R_ARM_GOT32		26	/* 32 bit GOT entry */
-#define R_ARM_PLT32		27	/* 32 bit PLT address */
-#define R_ARM_ALU_PCREL_7_0	32
-#define R_ARM_ALU_PCREL_15_8	33
-#define R_ARM_ALU_PCREL_23_15	34
-#define R_ARM_LDR_SBREL_11_0	35
-#define R_ARM_ALU_SBREL_19_12	36
-#define R_ARM_ALU_SBREL_27_20	37
-#define R_ARM_GNU_VTENTRY	100
-#define R_ARM_GNU_VTINHERIT	101
-#define R_ARM_THM_PC11		102	/* thumb unconditional branch */
-#define R_ARM_THM_PC9		103	/* thumb conditional branch */
-#define R_ARM_TLS_GD32		104	/* PC-rel 32 bit for global dynamic
-					   thread local data */
-#define R_ARM_TLS_LDM32		105	/* PC-rel 32 bit for local dynamic
-					   thread local data */
-#define R_ARM_TLS_LDO32		106	/* 32 bit offset relative to TLS
-					   block */
-#define R_ARM_TLS_IE32		107	/* PC-rel 32 bit for GOT entry of
-					   static TLS block offset */
-#define R_ARM_TLS_LE32		108	/* 32 bit offset relative to static
-					   TLS block */
-#define R_ARM_RXPC25		249
-#define R_ARM_RSBREL32		250
-#define R_ARM_THM_RPC22		251
-#define R_ARM_RREL32		252
-#define R_ARM_RABS22		253
-#define R_ARM_RPC24		254
-#define R_ARM_RBASE		255
-/* Keep this the last entry.  */
-#define R_ARM_NUM		256
-
-/* IA-64 specific declarations.  */
-
-/* Processor specific flags for the Ehdr e_flags field.  */
-#define EF_IA_64_MASKOS		0x0000000f	/* os-specific flags */
-#define EF_IA_64_ABI64		0x00000010	/* 64-bit ABI */
-#define EF_IA_64_ARCH		0xff000000	/* arch. version mask */
-
-/* Processor specific values for the Phdr p_type field.  */
-#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* arch extension bits */
-#define PT_IA_64_UNWIND		(PT_LOPROC + 1)	/* ia64 unwind bits */
-#define PT_IA_64_HP_OPT_ANOT	(PT_LOOS + 0x12)
-#define PT_IA_64_HP_HSL_ANOT	(PT_LOOS + 0x13)
-#define PT_IA_64_HP_STACK	(PT_LOOS + 0x14)
-
-/* Processor specific flags for the Phdr p_flags field.  */
-#define PF_IA_64_NORECOV	0x80000000	/* spec insns w/o recovery */
-
-/* Processor specific values for the Shdr sh_type field.  */
-#define SHT_IA_64_EXT		(SHT_LOPROC + 0) /* extension bits */
-#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1) /* unwind bits */
-
-/* Processor specific flags for the Shdr sh_flags field.  */
-#define SHF_IA_64_SHORT		0x10000000	/* section near gp */
-#define SHF_IA_64_NORECOV	0x20000000	/* spec insns w/o recovery */
-
-/* Processor specific values for the Dyn d_tag field.  */
-#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
-#define DT_IA_64_NUM		1
-
-/* IA-64 relocations.  */
-#define R_IA64_NONE		0x00	/* none */
-#define R_IA64_IMM14		0x21	/* symbol + addend, add imm14 */
-#define R_IA64_IMM22		0x22	/* symbol + addend, add imm22 */
-#define R_IA64_IMM64		0x23	/* symbol + addend, mov imm64 */
-#define R_IA64_DIR32MSB		0x24	/* symbol + addend, data4 MSB */
-#define R_IA64_DIR32LSB		0x25	/* symbol + addend, data4 LSB */
-#define R_IA64_DIR64MSB		0x26	/* symbol + addend, data8 MSB */
-#define R_IA64_DIR64LSB		0x27	/* symbol + addend, data8 LSB */
-#define R_IA64_GPREL22		0x2a	/* @gprel(sym + add), add imm22 */
-#define R_IA64_GPREL64I		0x2b	/* @gprel(sym + add), mov imm64 */
-#define R_IA64_GPREL32MSB	0x2c	/* @gprel(sym + add), data4 MSB */
-#define R_IA64_GPREL32LSB	0x2d	/* @gprel(sym + add), data4 LSB */
-#define R_IA64_GPREL64MSB	0x2e	/* @gprel(sym + add), data8 MSB */
-#define R_IA64_GPREL64LSB	0x2f	/* @gprel(sym + add), data8 LSB */
-#define R_IA64_LTOFF22		0x32	/* @ltoff(sym + add), add imm22 */
-#define R_IA64_LTOFF64I		0x33	/* @ltoff(sym + add), mov imm64 */
-#define R_IA64_PLTOFF22		0x3a	/* @pltoff(sym + add), add imm22 */
-#define R_IA64_PLTOFF64I	0x3b	/* @pltoff(sym + add), mov imm64 */
-#define R_IA64_PLTOFF64MSB	0x3e	/* @pltoff(sym + add), data8 MSB */
-#define R_IA64_PLTOFF64LSB	0x3f	/* @pltoff(sym + add), data8 LSB */
-#define R_IA64_FPTR64I		0x43	/* @fptr(sym + add), mov imm64 */
-#define R_IA64_FPTR32MSB	0x44	/* @fptr(sym + add), data4 MSB */
-#define R_IA64_FPTR32LSB	0x45	/* @fptr(sym + add), data4 LSB */
-#define R_IA64_FPTR64MSB	0x46	/* @fptr(sym + add), data8 MSB */
-#define R_IA64_FPTR64LSB	0x47	/* @fptr(sym + add), data8 LSB */
-#define R_IA64_PCREL60B		0x48	/* @pcrel(sym + add), brl */
-#define R_IA64_PCREL21B		0x49	/* @pcrel(sym + add), ptb, call */
-#define R_IA64_PCREL21M		0x4a	/* @pcrel(sym + add), chk.s */
-#define R_IA64_PCREL21F		0x4b	/* @pcrel(sym + add), fchkf */
-#define R_IA64_PCREL32MSB	0x4c	/* @pcrel(sym + add), data4 MSB */
-#define R_IA64_PCREL32LSB	0x4d	/* @pcrel(sym + add), data4 LSB */
-#define R_IA64_PCREL64MSB	0x4e	/* @pcrel(sym + add), data8 MSB */
-#define R_IA64_PCREL64LSB	0x4f	/* @pcrel(sym + add), data8 LSB */
-#define R_IA64_LTOFF_FPTR22	0x52	/* @ltoff(@fptr(s+a)), imm22 */
-#define R_IA64_LTOFF_FPTR64I	0x53	/* @ltoff(@fptr(s+a)), imm64 */
-#define R_IA64_LTOFF_FPTR32MSB	0x54	/* @ltoff(@fptr(s+a)), data4 MSB */
-#define R_IA64_LTOFF_FPTR32LSB	0x55	/* @ltoff(@fptr(s+a)), data4 LSB */
-#define R_IA64_LTOFF_FPTR64MSB	0x56	/* @ltoff(@fptr(s+a)), data8 MSB */
-#define R_IA64_LTOFF_FPTR64LSB	0x57	/* @ltoff(@fptr(s+a)), data8 LSB */
-#define R_IA64_SEGREL32MSB	0x5c	/* @segrel(sym + add), data4 MSB */
-#define R_IA64_SEGREL32LSB	0x5d	/* @segrel(sym + add), data4 LSB */
-#define R_IA64_SEGREL64MSB	0x5e	/* @segrel(sym + add), data8 MSB */
-#define R_IA64_SEGREL64LSB	0x5f	/* @segrel(sym + add), data8 LSB */
-#define R_IA64_SECREL32MSB	0x64	/* @secrel(sym + add), data4 MSB */
-#define R_IA64_SECREL32LSB	0x65	/* @secrel(sym + add), data4 LSB */
-#define R_IA64_SECREL64MSB	0x66	/* @secrel(sym + add), data8 MSB */
-#define R_IA64_SECREL64LSB	0x67	/* @secrel(sym + add), data8 LSB */
-#define R_IA64_REL32MSB		0x6c	/* data 4 + REL */
-#define R_IA64_REL32LSB		0x6d	/* data 4 + REL */
-#define R_IA64_REL64MSB		0x6e	/* data 8 + REL */
-#define R_IA64_REL64LSB		0x6f	/* data 8 + REL */
-#define R_IA64_LTV32MSB		0x74	/* symbol + addend, data4 MSB */
-#define R_IA64_LTV32LSB		0x75	/* symbol + addend, data4 LSB */
-#define R_IA64_LTV64MSB		0x76	/* symbol + addend, data8 MSB */
-#define R_IA64_LTV64LSB		0x77	/* symbol + addend, data8 LSB */
-#define R_IA64_PCREL21BI	0x79	/* @pcrel(sym + add), 21bit inst */
-#define R_IA64_PCREL22		0x7a	/* @pcrel(sym + add), 22bit inst */
-#define R_IA64_PCREL64I		0x7b	/* @pcrel(sym + add), 64bit inst */
-#define R_IA64_IPLTMSB		0x80	/* dynamic reloc, imported PLT, MSB */
-#define R_IA64_IPLTLSB		0x81	/* dynamic reloc, imported PLT, LSB */
-#define R_IA64_COPY		0x84	/* copy relocation */
-#define R_IA64_SUB		0x85	/* Addend and symbol difference */
-#define R_IA64_LTOFF22X		0x86	/* LTOFF22, relaxable.  */
-#define R_IA64_LDXMOV		0x87	/* Use of LTOFF22X.  */
-#define R_IA64_TPREL14		0x91	/* @tprel(sym + add), imm14 */
-#define R_IA64_TPREL22		0x92	/* @tprel(sym + add), imm22 */
-#define R_IA64_TPREL64I		0x93	/* @tprel(sym + add), imm64 */
-#define R_IA64_TPREL64MSB	0x96	/* @tprel(sym + add), data8 MSB */
-#define R_IA64_TPREL64LSB	0x97	/* @tprel(sym + add), data8 LSB */
-#define R_IA64_LTOFF_TPREL22	0x9a	/* @ltoff(@tprel(s+a)), imm2 */
-#define R_IA64_DTPMOD64MSB	0xa6	/* @dtpmod(sym + add), data8 MSB */
-#define R_IA64_DTPMOD64LSB	0xa7	/* @dtpmod(sym + add), data8 LSB */
-#define R_IA64_LTOFF_DTPMOD22	0xaa	/* @ltoff(@dtpmod(sym + add)), imm22 */
-#define R_IA64_DTPREL14		0xb1	/* @dtprel(sym + add), imm14 */
-#define R_IA64_DTPREL22		0xb2	/* @dtprel(sym + add), imm22 */
-#define R_IA64_DTPREL64I	0xb3	/* @dtprel(sym + add), imm64 */
-#define R_IA64_DTPREL32MSB	0xb4	/* @dtprel(sym + add), data4 MSB */
-#define R_IA64_DTPREL32LSB	0xb5	/* @dtprel(sym + add), data4 LSB */
-#define R_IA64_DTPREL64MSB	0xb6	/* @dtprel(sym + add), data8 MSB */
-#define R_IA64_DTPREL64LSB	0xb7	/* @dtprel(sym + add), data8 LSB */
-#define R_IA64_LTOFF_DTPREL22	0xba	/* @ltoff(@dtprel(s+a)), imm22 */
-
-/* SH specific declarations */
-
-/* SH relocs.  */
-#define	R_SH_NONE		0
-#define	R_SH_DIR32		1
-#define	R_SH_REL32		2
-#define	R_SH_DIR8WPN		3
-#define	R_SH_IND12W		4
-#define	R_SH_DIR8WPL		5
-#define	R_SH_DIR8WPZ		6
-#define	R_SH_DIR8BP		7
-#define	R_SH_DIR8W		8
-#define	R_SH_DIR8L		9
-#define	R_SH_SWITCH16		25
-#define	R_SH_SWITCH32		26
-#define	R_SH_USES		27
-#define	R_SH_COUNT		28
-#define	R_SH_ALIGN		29
-#define	R_SH_CODE		30
-#define	R_SH_DATA		31
-#define	R_SH_LABEL		32
-#define	R_SH_SWITCH8		33
-#define	R_SH_GNU_VTINHERIT	34
-#define	R_SH_GNU_VTENTRY	35
-#define	R_SH_TLS_GD_32		144
-#define	R_SH_TLS_LD_32		145
-#define	R_SH_TLS_LDO_32		146
-#define	R_SH_TLS_IE_32		147
-#define	R_SH_TLS_LE_32		148
-#define	R_SH_TLS_DTPMOD32	149
-#define	R_SH_TLS_DTPOFF32	150
-#define	R_SH_TLS_TPOFF32	151
-#define	R_SH_GOT32		160
-#define	R_SH_PLT32		161
-#define	R_SH_COPY		162
-#define	R_SH_GLOB_DAT		163
-#define	R_SH_JMP_SLOT		164
-#define	R_SH_RELATIVE		165
-#define	R_SH_GOTOFF		166
-#define	R_SH_GOTPC		167
-/* Keep this the last entry.  */
-#define	R_SH_NUM		256
-
-/* Additional s390 relocs */
-
-#define R_390_NONE		0	/* No reloc.  */
-#define R_390_8			1	/* Direct 8 bit.  */
-#define R_390_12		2	/* Direct 12 bit.  */
-#define R_390_16		3	/* Direct 16 bit.  */
-#define R_390_32		4	/* Direct 32 bit.  */
-#define R_390_PC32		5	/* PC relative 32 bit.	*/
-#define R_390_GOT12		6	/* 12 bit GOT offset.  */
-#define R_390_GOT32		7	/* 32 bit GOT offset.  */
-#define R_390_PLT32		8	/* 32 bit PC relative PLT address.  */
-#define R_390_COPY		9	/* Copy symbol at runtime.  */
-#define R_390_GLOB_DAT		10	/* Create GOT entry.  */
-#define R_390_JMP_SLOT		11	/* Create PLT entry.  */
-#define R_390_RELATIVE		12	/* Adjust by program base.  */
-#define R_390_GOTOFF32		13	/* 32 bit offset to GOT.	 */
-#define R_390_GOTPC		14	/* 32 bit PC relative offset to GOT.  */
-#define R_390_GOT16		15	/* 16 bit GOT offset.  */
-#define R_390_PC16		16	/* PC relative 16 bit.	*/
-#define R_390_PC16DBL		17	/* PC relative 16 bit shifted by 1.  */
-#define R_390_PLT16DBL		18	/* 16 bit PC rel. PLT shifted by 1.  */
-#define R_390_PC32DBL		19	/* PC relative 32 bit shifted by 1.  */
-#define R_390_PLT32DBL		20	/* 32 bit PC rel. PLT shifted by 1.  */
-#define R_390_GOTPCDBL		21	/* 32 bit PC rel. GOT shifted by 1.  */
-#define R_390_64		22	/* Direct 64 bit.  */
-#define R_390_PC64		23	/* PC relative 64 bit.	*/
-#define R_390_GOT64		24	/* 64 bit GOT offset.  */
-#define R_390_PLT64		25	/* 64 bit PC relative PLT address.  */
-#define R_390_GOTENT		26	/* 32 bit PC rel. to GOT entry >> 1. */
-#define R_390_GOTOFF16		27	/* 16 bit offset to GOT. */
-#define R_390_GOTOFF64		28	/* 64 bit offset to GOT. */
-#define R_390_GOTPLT12		29	/* 12 bit offset to jump slot.	*/
-#define R_390_GOTPLT16		30	/* 16 bit offset to jump slot.	*/
-#define R_390_GOTPLT32		31	/* 32 bit offset to jump slot.	*/
-#define R_390_GOTPLT64		32	/* 64 bit offset to jump slot.	*/
-#define R_390_GOTPLTENT		33	/* 32 bit rel. offset to jump slot.  */
-#define R_390_PLTOFF16		34	/* 16 bit offset from GOT to PLT. */
-#define R_390_PLTOFF32		35	/* 32 bit offset from GOT to PLT. */
-#define R_390_PLTOFF64		36	/* 16 bit offset from GOT to PLT. */
-#define R_390_TLS_LOAD		37	/* Tag for load insn in TLS code.  */
-#define R_390_TLS_GDCALL	38	/* Tag for function call in general
-					   dynamic TLS code. */
-#define R_390_TLS_LDCALL	39	/* Tag for function call in local
-					   dynamic TLS code. */
-#define R_390_TLS_GD32		40	/* Direct 32 bit for general dynamic
-					   thread local data.  */
-#define R_390_TLS_GD64		41	/* Direct 64 bit for general dynamic
-					  thread local data.  */
-#define R_390_TLS_GOTIE12	42	/* 12 bit GOT offset for static TLS
-					   block offset.  */
-#define R_390_TLS_GOTIE32	43	/* 32 bit GOT offset for static TLS
-					   block offset.  */
-#define R_390_TLS_GOTIE64	44	/* 64 bit GOT offset for static TLS
-					   block offset. */
-#define R_390_TLS_LDM32		45	/* Direct 32 bit for local dynamic
-					   thread local data in LE code.  */
-#define R_390_TLS_LDM64		46	/* Direct 64 bit for local dynamic
-					   thread local data in LE code.  */
-#define R_390_TLS_IE32		47	/* 32 bit address of GOT entry for
-					   negated static TLS block offset.  */
-#define R_390_TLS_IE64		48	/* 64 bit address of GOT entry for
-					   negated static TLS block offset.  */
-#define R_390_TLS_IEENT		49	/* 32 bit rel. offset to GOT entry for
-					   negated static TLS block offset.  */
-#define R_390_TLS_LE32		50	/* 32 bit negated offset relative to
-					   static TLS block.  */
-#define R_390_TLS_LE64		51	/* 64 bit negated offset relative to
-					   static TLS block.  */
-#define R_390_TLS_LDO32		52	/* 32 bit offset relative to TLS
-					   block.  */
-#define R_390_TLS_LDO64		53	/* 64 bit offset relative to TLS
-					   block.  */
-#define R_390_TLS_DTPMOD	54	/* ID of module containing symbol.  */
-#define R_390_TLS_DTPOFF	55	/* Offset in TLS block.	 */
-#define R_390_TLS_TPOFF		56	/* Negated offset in static TLS
-					   block.  */
-#define R_390_20		57	/* Direct 20 bit.  */
-#define R_390_GOT20		58	/* 20 bit GOT offset.  */
-#define R_390_GOTPLT20		59	/* 20 bit offset to jump slot.  */
-#define R_390_TLS_GOTIE20	60	/* 20 bit GOT offset for static TLS
-					   block offset.  */
-/* Keep this the last entry.  */
-#define R_390_NUM		61
-
-
-/* CRIS relocations.  */
-#define R_CRIS_NONE		0
-#define R_CRIS_8		1
-#define R_CRIS_16		2
-#define R_CRIS_32		3
-#define R_CRIS_8_PCREL		4
-#define R_CRIS_16_PCREL		5
-#define R_CRIS_32_PCREL		6
-#define R_CRIS_GNU_VTINHERIT	7
-#define R_CRIS_GNU_VTENTRY	8
-#define R_CRIS_COPY		9
-#define R_CRIS_GLOB_DAT		10
-#define R_CRIS_JUMP_SLOT	11
-#define R_CRIS_RELATIVE		12
-#define R_CRIS_16_GOT		13
-#define R_CRIS_32_GOT		14
-#define R_CRIS_16_GOTPLT	15
-#define R_CRIS_32_GOTPLT	16
-#define R_CRIS_32_GOTREL	17
-#define R_CRIS_32_PLT_GOTREL	18
-#define R_CRIS_32_PLT_PCREL	19
-
-#define R_CRIS_NUM		20
-
-
-/* AMD x86-64 relocations.  */
-#define R_X86_64_NONE		0	/* No reloc */
-#define R_X86_64_64		1	/* Direct 64 bit  */
-#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
-#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
-#define R_X86_64_PLT32		4	/* 32 bit PLT address */
-#define R_X86_64_COPY		5	/* Copy symbol at runtime */
-#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
-#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
-#define R_X86_64_RELATIVE	8	/* Adjust by program base */
-#define R_X86_64_GOTPCREL	9	/* 32 bit signed PC relative
-					   offset to GOT */
-#define R_X86_64_32		10	/* Direct 32 bit zero extended */
-#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
-#define R_X86_64_16		12	/* Direct 16 bit zero extended */
-#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
-#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
-#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
-#define R_X86_64_DTPMOD64	16	/* ID of module containing symbol */
-#define R_X86_64_DTPOFF64	17	/* Offset in module's TLS block */
-#define R_X86_64_TPOFF64	18	/* Offset in initial TLS block */
-#define R_X86_64_TLSGD		19	/* 32 bit signed PC relative offset
-					   to two GOT entries for GD symbol */
-#define R_X86_64_TLSLD		20	/* 32 bit signed PC relative offset
-					   to two GOT entries for LD symbol */
-#define R_X86_64_DTPOFF32	21	/* Offset in TLS block */
-#define R_X86_64_GOTTPOFF	22	/* 32 bit signed PC relative offset
-					   to GOT entry for IE symbol */
-#define R_X86_64_TPOFF32	23	/* Offset in initial TLS block */
-
-#define R_X86_64_NUM		24
-
-
-/* AM33 relocations.  */
-#define R_MN10300_NONE		0	/* No reloc.  */
-#define R_MN10300_32		1	/* Direct 32 bit.  */
-#define R_MN10300_16		2	/* Direct 16 bit.  */
-#define R_MN10300_8		3	/* Direct 8 bit.  */
-#define R_MN10300_PCREL32	4	/* PC-relative 32-bit.  */
-#define R_MN10300_PCREL16	5	/* PC-relative 16-bit signed.  */
-#define R_MN10300_PCREL8	6	/* PC-relative 8-bit signed.  */
-#define R_MN10300_GNU_VTINHERIT	7	/* Ancient C++ vtable garbage... */
-#define R_MN10300_GNU_VTENTRY	8	/* ... collection annotation.  */
-#define R_MN10300_24		9	/* Direct 24 bit.  */
-#define R_MN10300_GOTPC32	10	/* 32-bit PCrel offset to GOT.  */
-#define R_MN10300_GOTPC16	11	/* 16-bit PCrel offset to GOT.  */
-#define R_MN10300_GOTOFF32	12	/* 32-bit offset from GOT.  */
-#define R_MN10300_GOTOFF24	13	/* 24-bit offset from GOT.  */
-#define R_MN10300_GOTOFF16	14	/* 16-bit offset from GOT.  */
-#define R_MN10300_PLT32		15	/* 32-bit PCrel to PLT entry.  */
-#define R_MN10300_PLT16		16	/* 16-bit PCrel to PLT entry.  */
-#define R_MN10300_GOT32		17	/* 32-bit offset to GOT entry.  */
-#define R_MN10300_GOT24		18	/* 24-bit offset to GOT entry.  */
-#define R_MN10300_GOT16		19	/* 16-bit offset to GOT entry.  */
-#define R_MN10300_COPY		20	/* Copy symbol at runtime.  */
-#define R_MN10300_GLOB_DAT	21	/* Create GOT entry.  */
-#define R_MN10300_JMP_SLOT	22	/* Create PLT entry.  */
-#define R_MN10300_RELATIVE	23	/* Adjust by program base.  */
-
-#define R_MN10300_NUM		24
-
-
-/* M32R relocs.  */
-#define R_M32R_NONE		0	/* No reloc. */
-#define R_M32R_16		1	/* Direct 16 bit. */
-#define R_M32R_32		2	/* Direct 32 bit. */
-#define R_M32R_24		3	/* Direct 24 bit. */
-#define R_M32R_10_PCREL		4	/* PC relative 10 bit shifted. */
-#define R_M32R_18_PCREL		5	/* PC relative 18 bit shifted. */
-#define R_M32R_26_PCREL		6	/* PC relative 26 bit shifted. */
-#define R_M32R_HI16_ULO		7	/* High 16 bit with unsigned low. */
-#define R_M32R_HI16_SLO		8	/* High 16 bit with signed low. */
-#define R_M32R_LO16		9	/* Low 16 bit. */
-#define R_M32R_SDA16		10	/* 16 bit offset in SDA. */
-#define R_M32R_GNU_VTINHERIT	11
-#define R_M32R_GNU_VTENTRY	12
-/* M32R relocs use SHT_RELA.  */
-#define R_M32R_16_RELA		33	/* Direct 16 bit. */
-#define R_M32R_32_RELA		34	/* Direct 32 bit. */
-#define R_M32R_24_RELA		35	/* Direct 24 bit. */
-#define R_M32R_10_PCREL_RELA	36	/* PC relative 10 bit shifted. */
-#define R_M32R_18_PCREL_RELA	37	/* PC relative 18 bit shifted. */
-#define R_M32R_26_PCREL_RELA	38	/* PC relative 26 bit shifted. */
-#define R_M32R_HI16_ULO_RELA	39	/* High 16 bit with unsigned low */
-#define R_M32R_HI16_SLO_RELA	40	/* High 16 bit with signed low */
-#define R_M32R_LO16_RELA	41	/* Low 16 bit */
-#define R_M32R_SDA16_RELA	42	/* 16 bit offset in SDA */
-#define R_M32R_RELA_GNU_VTINHERIT	43
-#define R_M32R_RELA_GNU_VTENTRY	44
-#define R_M32R_REL32		45	/* PC relative 32 bit.  */
-
-#define R_M32R_GOT24		48	/* 24 bit GOT entry */
-#define R_M32R_26_PLTREL	49	/* 26 bit PC relative to PLT shifted */
-#define R_M32R_COPY		50	/* Copy symbol at runtime */
-#define R_M32R_GLOB_DAT		51	/* Create GOT entry */
-#define R_M32R_JMP_SLOT		52	/* Create PLT entry */
-#define R_M32R_RELATIVE		53	/* Adjust by program base */
-#define R_M32R_GOTOFF		54	/* 24 bit offset to GOT */
-#define R_M32R_GOTPC24		55	/* 24 bit PC relative offset to GOT */
-#define R_M32R_GOT16_HI_ULO	56	/* High 16 bit GOT entry with unsigned
-					   low */
-#define R_M32R_GOT16_HI_SLO	57	/* High 16 bit GOT entry with signed
-					   low */
-#define R_M32R_GOT16_LO		58	/* Low 16 bit GOT entry */
-#define R_M32R_GOTPC_HI_ULO	59	/* High 16 bit PC relative offset to
-					   GOT with unsigned low */
-#define R_M32R_GOTPC_HI_SLO	60	/* High 16 bit PC relative offset to
-					   GOT with signed low */
-#define R_M32R_GOTPC_LO		61	/* Low 16 bit PC relative offset to
-					   GOT */
-#define R_M32R_GOTOFF_HI_ULO	62	/* High 16 bit offset to GOT
-					   with unsigned low */
-#define R_M32R_GOTOFF_HI_SLO	63	/* High 16 bit offset to GOT
-					   with signed low */
-#define R_M32R_GOTOFF_LO	64	/* Low 16 bit offset to GOT */
-#define R_M32R_NUM		256	/* Keep this the last entry. */
-
-
-#endif	/* elf.h */

Modified: coreboot-v3/util/lar/stream.c
===================================================================
--- coreboot-v3/util/lar/stream.c	2008-04-04 03:31:39 UTC (rev 649)
+++ coreboot-v3/util/lar/stream.c	2008-04-04 03:33:08 UTC (rev 650)
@@ -32,8 +32,8 @@
 #include <sys/mman.h>
 #include <netinet/in.h>
 #include <libgen.h>
+#include <elf.h>
 
-#include "elf.h"
 #include "lar.h"
 #include "lib.h"
 




From svn at coreboot.org  Fri Apr  4 05:46:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 05:46:40 +0200
Subject: [coreboot] r651 - in coreboot-v3: device include/device
Message-ID: <mailman.1365.1355071295.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-04-04 05:46:39 +0200 (Fri, 04 Apr 2008)
New Revision: 651

Modified:
   coreboot-v3/device/root_device.c
   coreboot-v3/include/device/device.h
Log:
remove const from default root ops. device ops can not be const because they're
changed during run time. (trivial patch)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: coreboot-v3/device/root_device.c
===================================================================
--- coreboot-v3/device/root_device.c	2008-04-04 03:33:08 UTC (rev 650)
+++ coreboot-v3/device/root_device.c	2008-04-04 03:46:39 UTC (rev 651)
@@ -216,7 +216,7 @@
  * own ops in (e.g.) the mainboard, and initialize it in the dts in the
  * mainboard directory. 
  */
-const struct device_operations default_dev_ops_root = {
+struct device_operations default_dev_ops_root = {
 	.phase4_read_resources   = root_dev_read_resources,
 	.phase4_set_resources    = root_dev_set_resources,
 	.phase5_enable_resources = root_dev_enable_resources,

Modified: coreboot-v3/include/device/device.h
===================================================================
--- coreboot-v3/include/device/device.h	2008-04-04 03:33:08 UTC (rev 650)
+++ coreboot-v3/include/device/device.h	2008-04-04 03:46:39 UTC (rev 651)
@@ -283,7 +283,7 @@
 resource_t align_up(resource_t val, unsigned long gran);
 resource_t align_down(resource_t val, unsigned long gran);
 
-extern const struct device_operations default_dev_ops_root;
+extern struct device_operations default_dev_ops_root;
 
 extern int id_eq(struct device_id *id1, struct device_id *id2);
 void root_dev_read_resources(struct device * dev);




From malateshkamat at gmail.com  Fri Apr  4 07:31:19 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Fri, 4 Apr 2008 11:01:19 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <47F4DBB7.4050100@onelabs.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
Message-ID: <fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>

Hi...
       I am working on ASRock motherboard .....in FWH mode...

with regards.
Malatesh

On 03/04/2008, bari <bari at onelabs.com> wrote:
>
> malatesh kamatad wrote:
>
> >
> > Hi all..
> >       I have worked with PM49fl00x.diff patch ,its worked fine and i got
> > the output as below
> >
> >
> The PM49fl00x can work in LPC and FWH modes. Do you know which mode is
> being used?
> What mainboard did you test this in?
>
> >                    Now i am working on SST49LF004B
> >             33-4C-NHE
> >                                   0710022-CA   with the  motherboard
> >  K8Upgrade-VM800
> >                  The flashrom detect flash device on this board, But the
> > erasing and writting operation is not happening properly
> >   hier flashrom output :
> >
> Is this the board by ASRock?
>
> -Bari
>
>
>
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From bari at onelabs.com  Fri Apr  4 08:03:36 2008
From: bari at onelabs.com (bari)
Date: Fri, 04 Apr 2008 01:03:36 -0500
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
Message-ID: <47F5C4B8.5000700@onelabs.com>

Try Peters suggestion of reading the flash after an erase and see what 
is there.

If it is erased, read back after you have tried to write and compare.

See what is or is not happening.

-Bari

malatesh kamatad wrote:
> Hi...
>        I am working on ASRock motherboard .....in FWH mode...
>
> with regards.
> Malatesh
>
> On 03/04/2008, *bari* <bari at onelabs.com <mailto:bari at onelabs.com>> wrote:
>
>     malatesh kamatad wrote:
>
>
>         Hi all..
>               I have worked with PM49fl00x.diff patch ,its worked fine
>         and i got the output as below
>            
>
>     The PM49fl00x can work in LPC and FWH modes. Do you know which
>     mode is being used?
>     What mainboard did you test this in?
>
>                            Now i am working on SST49LF004B            
>                               33-4C-NHE
>                                           0710022-CA   with the
>          motherboard  K8Upgrade-VM800
>                          The flashrom detect flash device on this
>         board, But the erasing and writting operation is not happening
>         properly
>           hier flashrom output :            
>
>     Is this the board by ASRock?
>
>     -Bari
>
>
>




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 08:04:36 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 08:04:36 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F5952F.1060803@coresystems.de>
References: <47F5952F.1060803@coresystems.de>
Message-ID: <47F5C4F4.6030205@gmx.net>

On 04.04.2008 04:40, Stefan Reinauer wrote:
> The idea to this patch is from Patrick Georgi but I reimplemented it
> from scratch since I can't reach the other box for a few days. It
> fixes stage0_i586.S assembling on the latest official GNU binutils
> version. Without this patch the compilation fails with:
>
>  AS      build/arch/x86/stage0_i586.o
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler
> messages:
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> expecting operand after ','; got nothing
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> expecting operand after ','; got nothing

Sorry, that patch only papers over the bug. If we ever decide to use CAR
at another location, this will break again and we'll have to duplicate
some of the code you touched in the patch. I'd prefer to know why a
division fails, but a subtractoin succeeds.


Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 08:07:47 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 08:07:47 +0200
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <13426df10804032011g6c337c4ak8ba1f6388ab3896@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>	
	<47F4B0C3.40901@gmx.net> <20080403120935.GA21945@greenwood>	
	<13426df10804032003i525026c5r8f8efe282daa2630@mail.gmail.com>
	<13426df10804032011g6c337c4ak8ba1f6388ab3896@mail.gmail.com>
Message-ID: <47F5C5B3.3050909@gmx.net>

On 04.04.2008 05:11, ron minnich wrote:
> firefox crashed. Message went out, patch did not :-)
>
> ron
>
> On Thu, Apr 3, 2008 at 8:03 PM, ron minnich <rminnich at gmail.com> wrote:
>   
>> latest version, takes into account all comments to date, works.
>>
>>  ron
>>
>>     
> With this set of changes dbe62 gets to a FILO prompt.
>
> Set manual settings for dbe62 PLL; the auto settings are giving
> slightly wrong values
>
> Add call to dumplxmsr in dbe62 initram main()
>
> Change dumplxmsr to void parameter
>
> Add dumplxmsrs function to geodelx raminit support code
>
> Correct spelling of CAS.
>
> The big one: set spd variables correctly.
>
> The not so big one: there is a bug in com2 enable I don't understand.
> For now comment out two offending lines. The cs5536 debug prints
> should be reduced later.
>
> Change fuctory to factory. It's funny but confusing. 
>
> This patch also takes into account carl-daniel and uwe's comments.
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

For the record, this is also
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
and/or
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 08:10:36 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 08:10:36 +0200
Subject: [coreboot] [PATCH] fix lar compilation for non-Linux platforms
In-Reply-To: <47F597E6.5030107@coresystems.de>
References: <47F597E6.5030107@coresystems.de>
Message-ID: <47F5C65C.5020204@gmx.net>

On 04.04.2008 04:52, Stefan Reinauer wrote:
> This patch allows compilation on non-glibc platforms again.
>
>
> This adds the glibc elf.h to allow compilation on non-glibc platforms.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>   

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel



From patrick at georgi-clan.de  Fri Apr  4 08:33:40 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 04 Apr 2008 08:33:40 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F5C4F4.6030205@gmx.net>
References: <47F5952F.1060803@coresystems.de>  <47F5C4F4.6030205@gmx.net>
Message-ID: <1207290820.5987.11.camel@tetris>

Am Freitag, den 04.04.2008, 08:04 +0200 schrieb Carl-Daniel Hailfinger:
> On 04.04.2008 04:40, Stefan Reinauer wrote:
> > The idea to this patch is from Patrick Georgi but I reimplemented it
> > from scratch since I can't reach the other box for a few days. It
> > fixes stage0_i586.S assembling on the latest official GNU binutils
> > version. Without this patch the compilation fails with:

> > /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
> > expecting operand after ','; got nothing

> Sorry, that patch only papers over the bug. If we ever decide to use
> CAR
> at another location, this will break again and we'll have to duplicate
> some of the code you touched in the patch. I'd prefer to know why a
> division fails, but a subtractoin succeeds.
parentheses fail in the gnuas macros. for some reason, when copying the
arguments, gnu as (in that defective version) stops after the first
closing ')', making the whole statement invalid.

My change (which this is based on) actually removed them all except the
outermost level, but gnuas seems to be clever enough to remove unneeded
parens before passing things on. That's possible if there are only 
subtractions, but not when mixed with divisions like in the original
version.

The original code says this:
 ?extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax

extractmask is a macro with 2 arguments, segs [== ?(((\carsize -
\windowoffset) / 0x1000) - 4)] and reg [== %eax].
At some point, extractmask does:
?.if \segs <= 0

which should expand to
.if ?(((\carsize - \windowoffset) / 0x1000) - 4) ?<= 0

but which - due to the bug - really expands to
.if (((\carsize -  \windowoffset) <= 0

et voila: "missing ')'"


Regards,
Patrick Georgi




From malateshkamat at gmail.com  Fri Apr  4 10:41:02 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Fri, 4 Apr 2008 14:11:02 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <47F5C4B8.5000700@onelabs.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
Message-ID: <fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>

Hi..

         We are having two BIOS i.e, PM49FL004( motherboard's BIOS) and
empty flashrom

        SST49LF004B ..

       We are trying to flash the content of PM49FL004 to SST49LF004B
flashrom

        according to your suggestion we have done ..we are getting output
as bellow..



[root at localhost ~]# flashrom -E

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

Erasing flash chip

Erasing page: 0007 at address: 0x00070000

[root at localhost ~]# flashrom -r malateh.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

Reading Flash...done

[root at localhost ~]# flashrom -w malateh.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

Flash image seems to be a legacy BIOS. Disabling checks.

Programming page: 0007 at address: 0x00070000

[root at localhost ~]# flashrom -v malateh.bin

Calibrating delay loop... OK.

No coreboot table found.

Found chipset "VIA VT8237", enabling flash write... OK.

SST49LF004A/B found at physical address 0xfff80000.

Flash part is SST49LF004A/B (512 KB).

Flash image seems to be a legacy BIOS. Disabling checks.

Verifying flash... VERIFIED.


 After that we tried to boot the system by SST49lf004B but system is not
rebooting....

So we want to flash the content of the Pm49fl004 to SST49lf004 so that our
system can boot

using SST49lf004....

thanks,
Malatesh..


On 04/04/2008, bari <bari at onelabs.com> wrote:
>
> Try Peters suggestion of reading the flash after an erase and see what is
> there.
>
> If it is erased, read back after you have tried to write and compare.
>
> See what is or is not happening.
>
> -Bari
>
> malatesh kamatad wrote:
>
> > Hi...
> >       I am working on ASRock motherboard .....in FWH mode...
> >
> > with regards.
> > Malatesh
> >
> > On 03/04/2008, *bari* <bari at onelabs.com <mailto:bari at onelabs.com>>
> > wrote:
> >
> >    malatesh kamatad wrote:
> >
> >
> >        Hi all..
> >              I have worked with PM49fl00x.diff patch ,its worked fine
> >        and i got the output as below
> >
> >    The PM49fl00x can work in LPC and FWH modes. Do you know which
> >    mode is being used?
> >    What mainboard did you test this in?
> >
> >                           Now i am working on SST49LF004B
> >                            33-4C-NHE
> >                                          0710022-CA   with the
> >         motherboard  K8Upgrade-VM800
> >                         The flashrom detect flash device on this
> >        board, But the erasing and writting operation is not happening
> >        properly
> >          hier flashrom output :
> >    Is this the board by ASRock?
> >
> >    -Bari
> >
> >
> >
> >
>
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From peter at stuge.se  Fri Apr  4 10:56:37 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 10:56:37 +0200
Subject: [coreboot] [PATCH] Add subversion number
In-Reply-To: <20080404032446.GA16511@localdomain>
References: <47F59BC7.2090908@coresystems.de>
	<20080404032446.GA16511@localdomain>
Message-ID: <20080404085637.22591.qmail@stuge.se>

On Thu, Apr 03, 2008 at 09:24:46PM -0600, Ward Vandewege wrote:
> On Thu, Apr 03, 2008 at 09:08:55PM -0600, Stefan Reinauer wrote:
> >    This patch uses the svn version as the sublevel part of the coreboot
> >    version string.
> 
> Great!

I really like this idea but the patch depends on svn being installed
to build properly.

Is this also the case for the rev used in superiotool and flashrom?

Could we save the rev somewhere on checkout instead of looking up on
build?


//Peter



From peter at stuge.se  Fri Apr  4 11:29:21 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 11:29:21 +0200
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
Message-ID: <20080404092921.2207.qmail@stuge.se>

On Fri, Apr 04, 2008 at 02:11:02PM +0530, malatesh kamatad wrote:
> We are having two BIOS i.e, PM49FL004( motherboard's BIOS) and
> empty flashrom SST49LF004B ..
>
> We are trying to flash the content of PM49FL004 to SST49LF004B flashrom
> according to your suggestion we have done ..we are getting output
> as bellow..

Yes, you said so earlier. There is clearly a language issue. :\

Please start investigating what happens with the SST flash chip after
each flashrom operation.

Step by step:

* Insert Pm49LF004 chip
* Run flashrom -r original.bin
* Insert SST49LF004B chip
* Run flashrom -E
* Run flashrom -r sst_after_erase.bin
* Run flashrom -w original.bin
* Run flashrom -r sst_after_write.bin
* Analyze sst_after_*.bin and try to find a pattern that can explain
  what is failing at each step.


//Peter



From duwe at lst.de  Fri Apr  4 11:58:03 2008
From: duwe at lst.de (Torsten Duwe)
Date: Fri, 4 Apr 2008 11:58:03 +0200
Subject: [coreboot] libpayload: CMOS / BCD functions
In-Reply-To: <20080331152504.GE27868@cosmic.amd.com>
References: <20080327202407.GA9398@greenwood>
	<20080329012635.8137.qmail@stuge.se>
	<20080331152504.GE27868@cosmic.amd.com>
Message-ID: <200804041158.03444.duwe@lst.de>

On Monday 31 March 2008, Jordan Crouse wrote:
> On 29/03/08 02:26 +0100, Peter Stuge wrote:
> > On Fri, Mar 28, 2008 at 08:42:41AM -0600, Jordan Crouse wrote:
> > > On the other hand, CMOS is the agreed upon term for x86 platforms -
> > > it sounds stupid to our ears, but we're not typical users.  I would
> > > stick with CMOS.
> >
> > I prefer to educate users rather than bending around a bad habit.

CMOS RAM is a krufty legacy from the 1980ies, well known by that name.
It simply _is_not_ NVRAM, like it appeared shortly after on SparcStations.
I'd really *love* to store OFW boot device, path and args in it, but those 
lousy 112 Bytes are only good for tight bit packing.

> This won't come as a surprise to anybody, but we are lagging years behind
> the other architectures. [...] I hate the idea of spending
> valuable cycles thinking about other architectures when we're still so
> far away from making our primary one work.  Just my opinion.

Full Ack. I do not want to go on a crusade to preach an abstraction which is 
not practical. The x86 PC does not have NVRAM as we know it; CMOS RAM is 
different, because it is so much smaller, so let's call it differently.

	Torsten



From malateshkamat at gmail.com  Fri Apr  4 13:03:49 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Fri, 4 Apr 2008 16:33:49 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
Message-ID: <fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>

   I worked with the step by step this is the output......

[root at localhost ~]# flashrom -r original.bin
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "VIA VT8237", enabling flash write... OK.
Pm49FL004 found at physical address 0xfff80000.
Flash part is Pm49FL004 (512 KB).
Reading Flash...done

[root at localhost ~]# flashrom -E
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "VIA VT8237", enabling flash write... OK.
SST49LF004A/B found at physical address 0xfff80000.
Flash part is SST49LF004A/B (512 KB).
Erasing flash chip

[root at localhost ~]# flashrom -r sst_after_erase.bin
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "VIA VT8237", enabling flash write... OK.
SST49LF004A/B found at physical address 0xfff80000.
Flash part is SST49LF004A/B (512 KB).
Reading Flash...done

[root at localhost ~]# flashrom -w original.bin
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "VIA VT8237", enabling flash write... OK.
SST49LF004A/B found at physical address 0xfff80000.
Flash part is SST49LF004A/B (512 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Programming page: 0007 at address: 0x00070000

[root at localhost ~]# flashrom -r sst_after_write.bin
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "VIA VT8237", enabling flash write... OK.
SST49LF004A/B found at physical address 0xfff80000.
Flash part is SST49LF004A/B (512 KB).
Reading Flash...done

Thanks,
Malatesh.
On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
>
> Hi..
>
>          We are having two BIOS i.e, PM49FL004( motherboard's BIOS) and
> empty flashrom
>
>         SST49LF004B ..
>
>        We are trying to flash the content of PM49FL004 to SST49LF004B
> flashrom
>
>         according to your suggestion we have done ..we are getting output
> as bellow..
>
>
>
> [root at localhost ~]# flashrom -E
>
> Calibrating delay loop... OK.
>
> No coreboot table found.
>
> Found chipset "VIA VT8237", enabling flash write... OK.
>
> SST49LF004A/B found at physical address 0xfff80000.
>
> Flash part is SST49LF004A/B (512 KB).
>
> Erasing flash chip
>
> Erasing page: 0007 at address: 0x00070000
>
> [root at localhost ~]# flashrom -r malateh.bin
>
> Calibrating delay loop... OK.
>
> No coreboot table found.
>
> Found chipset "VIA VT8237", enabling flash write... OK.
>
> SST49LF004A/B found at physical address 0xfff80000.
>
> Flash part is SST49LF004A/B (512 KB).
>
> Reading Flash...done
>
> [root at localhost ~]# flashrom -w malateh.bin
>
> Calibrating delay loop... OK.
>
> No coreboot table found.
>
> Found chipset "VIA VT8237", enabling flash write... OK.
>
> SST49LF004A/B found at physical address 0xfff80000.
>
> Flash part is SST49LF004A/B (512 KB).
>
> Flash image seems to be a legacy BIOS. Disabling checks.
>
> Programming page: 0007 at address: 0x00070000
>
> [root at localhost ~]# flashrom -v malateh.bin
>
> Calibrating delay loop... OK.
>
> No coreboot table found.
>
> Found chipset "VIA VT8237", enabling flash write... OK.
>
> SST49LF004A/B found at physical address 0xfff80000.
>
> Flash part is SST49LF004A/B (512 KB).
>
> Flash image seems to be a legacy BIOS. Disabling checks.
>
> Verifying flash... VERIFIED.
>
>
>  After that we tried to boot the system by SST49lf004B but system is not
> rebooting....
>
> So we want to flash the content of the Pm49fl004 to SST49lf004 so that our
> system can boot
>
> using SST49lf004....
>
> thanks,
> Malatesh..
>
>
> On 04/04/2008, bari <bari at onelabs.com> wrote:
> >
> > Try Peters suggestion of reading the flash after an erase and see what
> > is there.
> >
> > If it is erased, read back after you have tried to write and compare.
> >
> > See what is or is not happening.
> >
> > -Bari
> >
> > malatesh kamatad wrote:
> >
> > > Hi...
> > >       I am working on ASRock motherboard .....in FWH mode...
> > >
> > > with regards.
> > > Malatesh
> > >
> > > On 03/04/2008, *bari* <bari at onelabs.com <mailto:bari at onelabs.com>>
> > > wrote:
> > >
> > >    malatesh kamatad wrote:
> > >
> > >
> > >        Hi all..
> > >              I have worked with PM49fl00x.diff patch ,its worked fine
> > >        and i got the output as below
> > >
> > >    The PM49fl00x can work in LPC and FWH modes. Do you know which
> > >    mode is being used?
> > >    What mainboard did you test this in?
> > >
> > >                           Now i am working on SST49LF004B
> > >                              33-4C-NHE
> > >                                          0710022-CA   with the
> > >         motherboard  K8Upgrade-VM800
> > >                         The flashrom detect flash device on this
> > >        board, But the erasing and writting operation is not happening
> > >        properly
> > >          hier flashrom output :
> > >    Is this the board by ASRock?
> > >
> > >    -Bari
> > >
> > >
> > >
> > >
> >
>
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From corey.osgood at gmail.com  Fri Apr  4 13:21:41 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 4 Apr 2008 07:21:41 -0400
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
Message-ID: <dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>

what's the output of diff -us original.bin sst_after_write.bin? Can you
download the bios from the manufacturer and see if flashing that works?

-Corey

On Fri, Apr 4, 2008 at 7:03 AM, malatesh kamatad <malateshkamat at gmail.com>
wrote:

>    I worked with the step by step this is the output......
>
> [root at localhost ~]# flashrom -r original.bin
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> Pm49FL004 found at physical address 0xfff80000.
> Flash part is Pm49FL004 (512 KB).
> Reading Flash...done
>
> [root at localhost ~]# flashrom -E
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> SST49LF004A/B found at physical address 0xfff80000.
> Flash part is SST49LF004A/B (512 KB).
> Erasing flash chip
>
> [root at localhost ~]# flashrom -r sst_after_erase.bin
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> SST49LF004A/B found at physical address 0xfff80000.
> Flash part is SST49LF004A/B (512 KB).
> Reading Flash...done
>
> [root at localhost ~]# flashrom -w original.bin
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> SST49LF004A/B found at physical address 0xfff80000.
> Flash part is SST49LF004A/B (512 KB).
> Flash image seems to be a legacy BIOS. Disabling checks.
> Programming page: 0007 at address: 0x00070000
>
> [root at localhost ~]# flashrom -r sst_after_write.bin
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> SST49LF004A/B found at physical address 0xfff80000.
> Flash part is SST49LF004A/B (512 KB).
> Reading Flash...done
>
> Thanks,
> Malatesh.
>
> On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
> >
> > Hi..
> >
> >          We are having two BIOS i.e, PM49FL004( motherboard's BIOS) and
> > empty flashrom
> >
> >         SST49LF004B ..
> >
> >        We are trying to flash the content of PM49FL004 to SST49LF004B
> > flashrom
> >
> >         according to your suggestion we have done ..we are getting
> > output  as bellow..
> >
> >
> >
> > [root at localhost ~]# flashrom -E
> >
> > Calibrating delay loop... OK.
> >
> > No coreboot table found.
> >
> > Found chipset "VIA VT8237", enabling flash write... OK.
> >
> > SST49LF004A/B found at physical address 0xfff80000.
> >
> > Flash part is SST49LF004A/B (512 KB).
> >
> > Erasing flash chip
> >
> > Erasing page: 0007 at address: 0x00070000
> >
> > [root at localhost ~]# flashrom -r malateh.bin
> >
> > Calibrating delay loop... OK.
> >
> > No coreboot table found.
> >
> > Found chipset "VIA VT8237", enabling flash write... OK.
> >
> > SST49LF004A/B found at physical address 0xfff80000.
> >
> > Flash part is SST49LF004A/B (512 KB).
> >
> > Reading Flash...done
> >
> > [root at localhost ~]# flashrom -w malateh.bin
> >
> > Calibrating delay loop... OK.
> >
> > No coreboot table found.
> >
> > Found chipset "VIA VT8237", enabling flash write... OK.
> >
> > SST49LF004A/B found at physical address 0xfff80000.
> >
> > Flash part is SST49LF004A/B (512 KB).
> >
> > Flash image seems to be a legacy BIOS. Disabling checks.
> >
> > Programming page: 0007 at address: 0x00070000
> >
> > [root at localhost ~]# flashrom -v malateh.bin
> >
> > Calibrating delay loop... OK.
> >
> > No coreboot table found.
> >
> > Found chipset "VIA VT8237", enabling flash write... OK.
> >
> > SST49LF004A/B found at physical address 0xfff80000.
> >
> > Flash part is SST49LF004A/B (512 KB).
> >
> > Flash image seems to be a legacy BIOS. Disabling checks.
> >
> > Verifying flash... VERIFIED.
> >
> >
> >  After that we tried to boot the system by SST49lf004B but system is not
> > rebooting....
> >
> > So we want to flash the content of the Pm49fl004 to SST49lf004 so that
> > our system can boot
> >
> > using SST49lf004....
> >
> > thanks,
> > Malatesh..
> >
> >
> > On 04/04/2008, bari <bari at onelabs.com> wrote:
> > >
> > > Try Peters suggestion of reading the flash after an erase and see what
> > > is there.
> > >
> > > If it is erased, read back after you have tried to write and compare.
> > >
> > > See what is or is not happening.
> > >
> > > -Bari
> > >
> > > malatesh kamatad wrote:
> > >
> > > > Hi...
> > > >       I am working on ASRock motherboard .....in FWH mode...
> > > >
> > > > with regards.
> > > > Malatesh
> > > >
> > > > On 03/04/2008, *bari* <bari at onelabs.com <mailto:bari at onelabs.com>>
> > > > wrote:
> > > >
> > > >    malatesh kamatad wrote:
> > > >
> > > >
> > > >        Hi all..
> > > >              I have worked with PM49fl00x.diff patch ,its worked
> > > > fine
> > > >        and i got the output as below
> > > >
> > > >    The PM49fl00x can work in LPC and FWH modes. Do you know which
> > > >    mode is being used?
> > > >    What mainboard did you test this in?
> > > >
> > > >                           Now i am working on SST49LF004B
> > > >                                33-4C-NHE
> > > >                                          0710022-CA   with the
> > > >         motherboard  K8Upgrade-VM800
> > > >                         The flashrom detect flash device on this
> > > >        board, But the erasing and writting operation is not
> > > > happening
> > > >        properly
> > > >          hier flashrom output :
> > > >    Is this the board by ASRock?
> > > >
> > > >    -Bari
> > > >
> > > >
> > > >
> > > >
> > >
> >
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From uwe at hermann-uwe.de  Fri Apr  4 14:25:31 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Apr 2008 14:25:31 +0200
Subject: [coreboot] [PATCH] Add subversion number
In-Reply-To: <20080404085637.22591.qmail@stuge.se>
References: <47F59BC7.2090908@coresystems.de>
	<20080404032446.GA16511@localdomain>
	<20080404085637.22591.qmail@stuge.se>
Message-ID: <20080404122531.GA14205@greenwood>

On Fri, Apr 04, 2008 at 10:56:37AM +0200, Peter Stuge wrote:
> > >    This patch uses the svn version as the sublevel part of the coreboot
> > >    version string.
> 
> I really like this idea but the patch depends on svn being installed
> to build properly.

Yes, but I think it would be ok if we use "unknown" or "0" or something
like that if svn is not available (haven't tried what happens currently).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From malateshkamat at gmail.com  Fri Apr  4 14:41:53 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Fri, 4 Apr 2008 18:11:53 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
	<dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
Message-ID: <fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>

 Ya i got result like this after comparing

  [root at localhost ~]# diff -us original.bin sst_after_write.bin
Binary files original.bin and sst_after_write.bin differ

   but its showing that there is a difference in between to files ....

  i think write is not happening proper ....

Thanks .
malatesh

On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
>
> what's the output of diff -us original.bin sst_after_write.bin? Can you
> download the bios from the manufacturer and see if flashing that works?
>
> -Corey
>
> On Fri, Apr 4, 2008 at 7:03 AM, malatesh kamatad <malateshkamat at gmail.com>
> wrote:
>
> >    I worked with the step by step this is the output......
> >
> > [root at localhost ~]# flashrom -r original.bin
> > Calibrating delay loop... OK.
> > No coreboot table found.
> > Found chipset "VIA VT8237", enabling flash write... OK.
> > Pm49FL004 found at physical address 0xfff80000.
> > Flash part is Pm49FL004 (512 KB).
> > Reading Flash...done
> >
> > [root at localhost ~]# flashrom -E
> > Calibrating delay loop... OK.
> > No coreboot table found.
> > Found chipset "VIA VT8237", enabling flash write... OK.
> > SST49LF004A/B found at physical address 0xfff80000.
> > Flash part is SST49LF004A/B (512 KB).
> > Erasing flash chip
> >
> > [root at localhost ~]# flashrom -r sst_after_erase.bin
> > Calibrating delay loop... OK.
> > No coreboot table found.
> > Found chipset "VIA VT8237", enabling flash write... OK.
> > SST49LF004A/B found at physical address 0xfff80000.
> > Flash part is SST49LF004A/B (512 KB).
> > Reading Flash...done
> >
> > [root at localhost ~]# flashrom -w original.bin
> > Calibrating delay loop... OK.
> > No coreboot table found.
> > Found chipset "VIA VT8237", enabling flash write... OK.
> > SST49LF004A/B found at physical address 0xfff80000.
> > Flash part is SST49LF004A/B (512 KB).
> > Flash image seems to be a legacy BIOS. Disabling checks.
> > Programming page: 0007 at address: 0x00070000
> >
> > [root at localhost ~]# flashrom -r sst_after_write.bin
> > Calibrating delay loop... OK.
> > No coreboot table found.
> > Found chipset "VIA VT8237", enabling flash write... OK.
> > SST49LF004A/B found at physical address 0xfff80000.
> > Flash part is SST49LF004A/B (512 KB).
> > Reading Flash...done
> >
> > Thanks,
> > Malatesh.
> >
> > On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
> > >
> > > Hi..
> > >
> > >          We are having two BIOS i.e, PM49FL004( motherboard's BIOS)
> > > and empty flashrom
> > >
> > >         SST49LF004B ..
> > >
> > >        We are trying to flash the content of PM49FL004 to SST49LF004B
> > > flashrom
> > >
> > >         according to your suggestion we have done ..we are getting
> > > output  as bellow..
> > >
> > >
> > >
> > > [root at localhost ~]# flashrom -E
> > >
> > > Calibrating delay loop... OK.
> > >
> > > No coreboot table found.
> > >
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > >
> > > SST49LF004A/B found at physical address 0xfff80000.
> > >
> > > Flash part is SST49LF004A/B (512 KB).
> > >
> > > Erasing flash chip
> > >
> > > Erasing page: 0007 at address: 0x00070000
> > >
> > > [root at localhost ~]# flashrom -r malateh.bin
> > >
> > > Calibrating delay loop... OK.
> > >
> > > No coreboot table found.
> > >
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > >
> > > SST49LF004A/B found at physical address 0xfff80000.
> > >
> > > Flash part is SST49LF004A/B (512 KB).
> > >
> > > Reading Flash...done
> > >
> > > [root at localhost ~]# flashrom -w malateh.bin
> > >
> > > Calibrating delay loop... OK.
> > >
> > > No coreboot table found.
> > >
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > >
> > > SST49LF004A/B found at physical address 0xfff80000.
> > >
> > > Flash part is SST49LF004A/B (512 KB).
> > >
> > > Flash image seems to be a legacy BIOS. Disabling checks.
> > >
> > > Programming page: 0007 at address: 0x00070000
> > >
> > > [root at localhost ~]# flashrom -v malateh.bin
> > >
> > > Calibrating delay loop... OK.
> > >
> > > No coreboot table found.
> > >
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > >
> > > SST49LF004A/B found at physical address 0xfff80000.
> > >
> > > Flash part is SST49LF004A/B (512 KB).
> > >
> > > Flash image seems to be a legacy BIOS. Disabling checks.
> > >
> > > Verifying flash... VERIFIED.
> > >
> > >
> > >  After that we tried to boot the system by SST49lf004B but system is
> > > not rebooting....
> > >
> > > So we want to flash the content of the Pm49fl004 to SST49lf004 so that
> > > our system can boot
> > >
> > > using SST49lf004....
> > >
> > > thanks,
> > > Malatesh..
> > >
> > >
> > > On 04/04/2008, bari <bari at onelabs.com> wrote:
> > > >
> > > > Try Peters suggestion of reading the flash after an erase and see
> > > > what is there.
> > > >
> > > > If it is erased, read back after you have tried to write and
> > > > compare.
> > > >
> > > > See what is or is not happening.
> > > >
> > > > -Bari
> > > >
> > > > malatesh kamatad wrote:
> > > >
> > > > > Hi...
> > > > >       I am working on ASRock motherboard .....in FWH mode...
> > > > >
> > > > > with regards.
> > > > > Malatesh
> > > > >
> > > > > On 03/04/2008, *bari* <bari at onelabs.com <mailto:bari at onelabs.com>>
> > > > > wrote:
> > > > >
> > > > >    malatesh kamatad wrote:
> > > > >
> > > > >
> > > > >        Hi all..
> > > > >              I have worked with PM49fl00x.diff patch ,its worked
> > > > > fine
> > > > >        and i got the output as below
> > > > >
> > > > >    The PM49fl00x can work in LPC and FWH modes. Do you know which
> > > > >    mode is being used?
> > > > >    What mainboard did you test this in?
> > > > >
> > > > >                           Now i am working on SST49LF004B
> > > > >                                  33-4C-NHE
> > > > >                                          0710022-CA   with the
> > > > >         motherboard  K8Upgrade-VM800
> > > > >                         The flashrom detect flash device on this
> > > > >        board, But the erasing and writting operation is not
> > > > > happening
> > > > >        properly
> > > > >          hier flashrom output :
> > > > >    Is this the board by ASRock?
> > > > >
> > > > >    -Bari
> > > > >
> > > > >
> > > > >
> > > > >
> > > >
> > >
> >
> > --
> > coreboot mailing list
> > coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> >
>
>
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From corey.osgood at gmail.com  Fri Apr  4 14:59:44 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 4 Apr 2008 08:59:44 -0400
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
	<dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
	<fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>
Message-ID: <dd3c80060804040559h4b7510b1q7747f44e897fa4da@mail.gmail.com>

Ok, so if you open up the sst_after_erase.bin with a hex editor, is there
anything in it? Does that match the data from the diff, or is it a binary
ORing of the data from the diff? Do you have any other flash chips you can
try on the board?

On Fri, Apr 4, 2008 at 8:41 AM, malatesh kamatad <malateshkamat at gmail.com>
wrote:

>  Ya i got result like this after comparing
>
>   [root at localhost ~]# diff -us original.bin sst_after_write.bin
> Binary files original.bin and sst_after_write.bin differ
>
>    but its showing that there is a difference in between to files ....
>
>   i think write is not happening proper ....
>
> Thanks .
> malatesh
>
>
> On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
> >
> > what's the output of diff -us original.bin sst_after_write.bin? Can you
> > download the bios from the manufacturer and see if flashing that works?
> >
> > -Corey
> >
> > On Fri, Apr 4, 2008 at 7:03 AM, malatesh kamatad <
> > malateshkamat at gmail.com> wrote:
> >
> > >    I worked with the step by step this is the output......
> > >
> > > [root at localhost ~]# flashrom -r original.bin
> > > Calibrating delay loop... OK.
> > > No coreboot table found.
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > Pm49FL004 found at physical address 0xfff80000.
> > > Flash part is Pm49FL004 (512 KB).
> > > Reading Flash...done
> > >
> > > [root at localhost ~]# flashrom -E
> > > Calibrating delay loop... OK.
> > > No coreboot table found.
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > SST49LF004A/B found at physical address 0xfff80000.
> > > Flash part is SST49LF004A/B (512 KB).
> > > Erasing flash chip
> > >
> > > [root at localhost ~]# flashrom -r sst_after_erase.bin
> > > Calibrating delay loop... OK.
> > > No coreboot table found.
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > SST49LF004A/B found at physical address 0xfff80000.
> > > Flash part is SST49LF004A/B (512 KB).
> > > Reading Flash...done
> > >
> > > [root at localhost ~]# flashrom -w original.bin
> > > Calibrating delay loop... OK.
> > > No coreboot table found.
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > SST49LF004A/B found at physical address 0xfff80000.
> > > Flash part is SST49LF004A/B (512 KB).
> > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > Programming page: 0007 at address: 0x00070000
> > >
> > > [root at localhost ~]# flashrom -r sst_after_write.bin
> > > Calibrating delay loop... OK.
> > > No coreboot table found.
> > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > SST49LF004A/B found at physical address 0xfff80000.
> > > Flash part is SST49LF004A/B (512 KB).
> > > Reading Flash...done
> > >
> > > Thanks,
> > > Malatesh.
> > >
> > > On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
> > > >
> > > > Hi..
> > > >
> > > >          We are having two BIOS i.e, PM49FL004( motherboard's BIOS)
> > > > and empty flashrom
> > > >
> > > >         SST49LF004B ..
> > > >
> > > >        We are trying to flash the content of PM49FL004 to
> > > > SST49LF004B flashrom
> > > >
> > > >         according to your suggestion we have done ..we are getting
> > > > output  as bellow..
> > > >
> > > >
> > > >
> > > > [root at localhost ~]# flashrom -E
> > > >
> > > > Calibrating delay loop... OK.
> > > >
> > > > No coreboot table found.
> > > >
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > >
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > >
> > > > Flash part is SST49LF004A/B (512 KB).
> > > >
> > > > Erasing flash chip
> > > >
> > > > Erasing page: 0007 at address: 0x00070000
> > > >
> > > > [root at localhost ~]# flashrom -r malateh.bin
> > > >
> > > > Calibrating delay loop... OK.
> > > >
> > > > No coreboot table found.
> > > >
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > >
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > >
> > > > Flash part is SST49LF004A/B (512 KB).
> > > >
> > > > Reading Flash...done
> > > >
> > > > [root at localhost ~]# flashrom -w malateh.bin
> > > >
> > > > Calibrating delay loop... OK.
> > > >
> > > > No coreboot table found.
> > > >
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > >
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > >
> > > > Flash part is SST49LF004A/B (512 KB).
> > > >
> > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > >
> > > > Programming page: 0007 at address: 0x00070000
> > > >
> > > > [root at localhost ~]# flashrom -v malateh.bin
> > > >
> > > > Calibrating delay loop... OK.
> > > >
> > > > No coreboot table found.
> > > >
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > >
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > >
> > > > Flash part is SST49LF004A/B (512 KB).
> > > >
> > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > >
> > > > Verifying flash... VERIFIED.
> > > >
> > > >
> > > >  After that we tried to boot the system by SST49lf004B but system is
> > > > not rebooting....
> > > >
> > > > So we want to flash the content of the Pm49fl004 to SST49lf004 so
> > > > that our system can boot
> > > >
> > > > using SST49lf004....
> > > >
> > > > thanks,
> > > > Malatesh..
> > > >
> > > >
> > > > On 04/04/2008, bari <bari at onelabs.com> wrote:
> > > > >
> > > > > Try Peters suggestion of reading the flash after an erase and see
> > > > > what is there.
> > > > >
> > > > > If it is erased, read back after you have tried to write and
> > > > > compare.
> > > > >
> > > > > See what is or is not happening.
> > > > >
> > > > > -Bari
> > > > >
> > > > > malatesh kamatad wrote:
> > > > >
> > > > > > Hi...
> > > > > >       I am working on ASRock motherboard .....in FWH mode...
> > > > > >
> > > > > > with regards.
> > > > > > Malatesh
> > > > > >
> > > > > > On 03/04/2008, *bari* <bari at onelabs.com <mailto:bari at onelabs.com>>
> > > > > > wrote:
> > > > > >
> > > > > >    malatesh kamatad wrote:
> > > > > >
> > > > > >
> > > > > >        Hi all..
> > > > > >              I have worked with PM49fl00x.diff patch ,its worked
> > > > > > fine
> > > > > >        and i got the output as below
> > > > > >
> > > > > >    The PM49fl00x can work in LPC and FWH modes. Do you know
> > > > > > which
> > > > > >    mode is being used?
> > > > > >    What mainboard did you test this in?
> > > > > >
> > > > > >                           Now i am working on SST49LF004B
> > > > > >                                    33-4C-NHE
> > > > > >                                          0710022-CA   with the
> > > > > >         motherboard  K8Upgrade-VM800
> > > > > >                         The flashrom detect flash device on this
> > > > > >        board, But the erasing and writting operation is not
> > > > > > happening
> > > > > >        properly
> > > > > >          hier flashrom output :
> > > > > >    Is this the board by ASRock?
> > > > > >
> > > > > >    -Bari
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > >
> > > >
> > >
> > > --
> > > coreboot mailing list
> > > coreboot at coreboot.org
> > > http://www.coreboot.org/mailman/listinfo/coreboot
> > >
> >
> >
>
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From stepan at coresystems.de  Fri Apr  4 15:08:47 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 07:08:47 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F5C4F4.6030205@gmx.net>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
Message-ID: <47F6285F.2040807@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 04.04.2008 04:40, Stefan Reinauer wrote:
>   
>> The idea to this patch is from Patrick Georgi but I reimplemented it
>> from scratch since I can't reach the other box for a few days. It
>> fixes stage0_i586.S assembling on the latest official GNU binutils
>> version. Without this patch the compilation fails with:
>>
>>  AS      build/arch/x86/stage0_i586.o
>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler
>> messages:
>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
>> missing ')'
[..]
> Sorry, that patch only papers over the bug. If we ever decide to use CAR
> at another location, this will break again and we'll have to duplicate
> some of the code you touched in the patch. I'd prefer to know why a
> division fails, but a subtractoin succeeds.
>   
Why is that code more position dependent than the previous, 
non-compiling code?

While I think, requiring the latest version of binutils (or, any other 
toolchain part, for that matter) is fair, we should not require features 
that do not work in the latest "stable" version but require a snapshot 
release to be installed.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Fri Apr  4 15:10:06 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 15:10:06 +0200
Subject: [coreboot] r652 - coreboot-v3/util/lar
Message-ID: <mailman.1366.1355071295.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-04-04 15:10:05 +0200 (Fri, 04 Apr 2008)
New Revision: 652

Added:
   coreboot-v3/util/lar/elf.h
Modified:
   coreboot-v3/util/lar/stream.c
Log:
This adds the glibc elf.h to allow compilation on non-glibc platforms.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Added: coreboot-v3/util/lar/elf.h
===================================================================
--- coreboot-v3/util/lar/elf.h	                        (rev 0)
+++ coreboot-v3/util/lar/elf.h	2008-04-04 13:10:05 UTC (rev 652)
@@ -0,0 +1,2637 @@
+/* This file defines standard ELF types, structures, and macros.
+   Copyright (C) 1995-2003,2004,2005,2006,2007 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, write to the Free
+   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307 USA.  */
+
+#ifndef _ELF_H
+#define	_ELF_H 1
+
+#include <stdint.h>
+
+/* Type for a 16-bit quantity.  */
+typedef uint16_t Elf32_Half;
+typedef uint16_t Elf64_Half;
+
+/* Types for signed and unsigned 32-bit quantities.  */
+typedef uint32_t Elf32_Word;
+typedef	int32_t  Elf32_Sword;
+typedef uint32_t Elf64_Word;
+typedef	int32_t  Elf64_Sword;
+
+/* Types for signed and unsigned 64-bit quantities.  */
+typedef uint64_t Elf32_Xword;
+typedef	int64_t  Elf32_Sxword;
+typedef uint64_t Elf64_Xword;
+typedef	int64_t  Elf64_Sxword;
+
+/* Type of addresses.  */
+typedef uint32_t Elf32_Addr;
+typedef uint64_t Elf64_Addr;
+
+/* Type of file offsets.  */
+typedef uint32_t Elf32_Off;
+typedef uint64_t Elf64_Off;
+
+/* Type for section indices, which are 16-bit quantities.  */
+typedef uint16_t Elf32_Section;
+typedef uint16_t Elf64_Section;
+
+/* Type for version symbol information.  */
+typedef Elf32_Half Elf32_Versym;
+typedef Elf64_Half Elf64_Versym;
+
+
+/* The ELF file header.  This appears at the start of every ELF file.  */
+
+#define EI_NIDENT (16)
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf32_Half	e_type;			/* Object file type */
+  Elf32_Half	e_machine;		/* Architecture */
+  Elf32_Word	e_version;		/* Object file version */
+  Elf32_Addr	e_entry;		/* Entry point virtual address */
+  Elf32_Off	e_phoff;		/* Program header table file offset */
+  Elf32_Off	e_shoff;		/* Section header table file offset */
+  Elf32_Word	e_flags;		/* Processor-specific flags */
+  Elf32_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf32_Half	e_phentsize;		/* Program header table entry size */
+  Elf32_Half	e_phnum;		/* Program header table entry count */
+  Elf32_Half	e_shentsize;		/* Section header table entry size */
+  Elf32_Half	e_shnum;		/* Section header table entry count */
+  Elf32_Half	e_shstrndx;		/* Section header string table index */
+} Elf32_Ehdr;
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf64_Half	e_type;			/* Object file type */
+  Elf64_Half	e_machine;		/* Architecture */
+  Elf64_Word	e_version;		/* Object file version */
+  Elf64_Addr	e_entry;		/* Entry point virtual address */
+  Elf64_Off	e_phoff;		/* Program header table file offset */
+  Elf64_Off	e_shoff;		/* Section header table file offset */
+  Elf64_Word	e_flags;		/* Processor-specific flags */
+  Elf64_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf64_Half	e_phentsize;		/* Program header table entry size */
+  Elf64_Half	e_phnum;		/* Program header table entry count */
+  Elf64_Half	e_shentsize;		/* Section header table entry size */
+  Elf64_Half	e_shnum;		/* Section header table entry count */
+  Elf64_Half	e_shstrndx;		/* Section header string table index */
+} Elf64_Ehdr;
+
+/* Fields in the e_ident array.  The EI_* macros are indices into the
+   array.  The macros under each EI_* macro are the values the byte
+   may have.  */
+
+#define EI_MAG0		0		/* File identification byte 0 index */
+#define ELFMAG0		0x7f		/* Magic number byte 0 */
+
+#define EI_MAG1		1		/* File identification byte 1 index */
+#define ELFMAG1		'E'		/* Magic number byte 1 */
+
+#define EI_MAG2		2		/* File identification byte 2 index */
+#define ELFMAG2		'L'		/* Magic number byte 2 */
+
+#define EI_MAG3		3		/* File identification byte 3 index */
+#define ELFMAG3		'F'		/* Magic number byte 3 */
+
+/* Conglomeration of the identification bytes, for easy testing as a word.  */
+#define	ELFMAG		"\177ELF"
+#define	SELFMAG		4
+
+#define EI_CLASS	4		/* File class byte index */
+#define ELFCLASSNONE	0		/* Invalid class */
+#define ELFCLASS32	1		/* 32-bit objects */
+#define ELFCLASS64	2		/* 64-bit objects */
+#define ELFCLASSNUM	3
+
+#define EI_DATA		5		/* Data encoding byte index */
+#define ELFDATANONE	0		/* Invalid data encoding */
+#define ELFDATA2LSB	1		/* 2's complement, little endian */
+#define ELFDATA2MSB	2		/* 2's complement, big endian */
+#define ELFDATANUM	3
+
+#define EI_VERSION	6		/* File version byte index */
+					/* Value must be EV_CURRENT */
+
+#define EI_OSABI	7		/* OS ABI identification */
+#define ELFOSABI_NONE		0	/* UNIX System V ABI */
+#define ELFOSABI_SYSV		0	/* Alias.  */
+#define ELFOSABI_HPUX		1	/* HP-UX */
+#define ELFOSABI_NETBSD		2	/* NetBSD.  */
+#define ELFOSABI_LINUX		3	/* Linux.  */
+#define ELFOSABI_SOLARIS	6	/* Sun Solaris.  */
+#define ELFOSABI_AIX		7	/* IBM AIX.  */
+#define ELFOSABI_IRIX		8	/* SGI Irix.  */
+#define ELFOSABI_FREEBSD	9	/* FreeBSD.  */
+#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX.  */
+#define ELFOSABI_MODESTO	11	/* Novell Modesto.  */
+#define ELFOSABI_OPENBSD	12	/* OpenBSD.  */
+#define ELFOSABI_ARM		97	/* ARM */
+#define ELFOSABI_STANDALONE	255	/* Standalone (embedded) application */
+
+#define EI_ABIVERSION	8		/* ABI version */
+
+#define EI_PAD		9		/* Byte index of padding bytes */
+
+/* Legal values for e_type (object file type).  */
+
+#define ET_NONE		0		/* No file type */
+#define ET_REL		1		/* Relocatable file */
+#define ET_EXEC		2		/* Executable file */
+#define ET_DYN		3		/* Shared object file */
+#define ET_CORE		4		/* Core file */
+#define	ET_NUM		5		/* Number of defined types */
+#define ET_LOOS		0xfe00		/* OS-specific range start */
+#define ET_HIOS		0xfeff		/* OS-specific range end */
+#define ET_LOPROC	0xff00		/* Processor-specific range start */
+#define ET_HIPROC	0xffff		/* Processor-specific range end */
+
+/* Legal values for e_machine (architecture).  */
+
+#define EM_NONE		 0		/* No machine */
+#define EM_M32		 1		/* AT&T WE 32100 */
+#define EM_SPARC	 2		/* SUN SPARC */
+#define EM_386		 3		/* Intel 80386 */
+#define EM_68K		 4		/* Motorola m68k family */
+#define EM_88K		 5		/* Motorola m88k family */
+#define EM_860		 7		/* Intel 80860 */
+#define EM_MIPS		 8		/* MIPS R3000 big-endian */
+#define EM_S370		 9		/* IBM System/370 */
+#define EM_MIPS_RS3_LE	10		/* MIPS R3000 little-endian */
+
+#define EM_PARISC	15		/* HPPA */
+#define EM_VPP500	17		/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18		/* Sun's "v8plus" */
+#define EM_960		19		/* Intel 80960 */
+#define EM_PPC		20		/* PowerPC */
+#define EM_PPC64	21		/* PowerPC 64-bit */
+#define EM_S390		22		/* IBM S390 */
+
+#define EM_V800		36		/* NEC V800 series */
+#define EM_FR20		37		/* Fujitsu FR20 */
+#define EM_RH32		38		/* TRW RH-32 */
+#define EM_RCE		39		/* Motorola RCE */
+#define EM_ARM		40		/* ARM */
+#define EM_FAKE_ALPHA	41		/* Digital Alpha */
+#define EM_SH		42		/* Hitachi SH */
+#define EM_SPARCV9	43		/* SPARC v9 64-bit */
+#define EM_TRICORE	44		/* Siemens Tricore */
+#define EM_ARC		45		/* Argonaut RISC Core */
+#define EM_H8_300	46		/* Hitachi H8/300 */
+#define EM_H8_300H	47		/* Hitachi H8/300H */
+#define EM_H8S		48		/* Hitachi H8S */
+#define EM_H8_500	49		/* Hitachi H8/500 */
+#define EM_IA_64	50		/* Intel Merced */
+#define EM_MIPS_X	51		/* Stanford MIPS-X */
+#define EM_COLDFIRE	52		/* Motorola Coldfire */
+#define EM_68HC12	53		/* Motorola M68HC12 */
+#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
+#define EM_PCP		55		/* Siemens PCP */
+#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
+#define EM_NDR1		57		/* Denso NDR1 microprocessor */
+#define EM_STARCORE	58		/* Motorola Start*Core processor */
+#define EM_ME16		59		/* Toyota ME16 processor */
+#define EM_ST100	60		/* STMicroelectronic ST100 processor */
+#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
+#define EM_X86_64	62		/* AMD x86-64 architecture */
+#define EM_PDSP		63		/* Sony DSP Processor */
+
+#define EM_FX66		66		/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
+#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
+#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
+#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
+#define EM_SVX		73		/* Silicon Graphics SVx */
+#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX		75		/* Digital VAX */
+#define EM_CRIS		76		/* Axis Communications 32-bit embedded processor */
+#define EM_JAVELIN	77		/* Infineon Technologies 32-bit embedded processor */
+#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
+#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX		80		/* Donald Knuth's educational 64-bit processor */
+#define EM_HUANY	81		/* Harvard University machine-independent object files */
+#define EM_PRISM	82		/* SiTera Prism */
+#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		84		/* Fujitsu FR30 */
+#define EM_D10V		85		/* Mitsubishi D10V */
+#define EM_D30V		86		/* Mitsubishi D30V */
+#define EM_V850		87		/* NEC v850 */
+#define EM_M32R		88		/* Mitsubishi M32R */
+#define EM_MN10300	89		/* Matsushita MN10300 */
+#define EM_MN10200	90		/* Matsushita MN10200 */
+#define EM_PJ		91		/* picoJava */
+#define EM_OPENRISC	92		/* OpenRISC 32-bit embedded processor */
+#define EM_ARC_A5	93		/* ARC Cores Tangent-A5 */
+#define EM_XTENSA	94		/* Tensilica Xtensa Architecture */
+#define EM_NUM		95
+
+/* If it is necessary to assign new unofficial EM_* values, please
+   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
+   chances of collision with official or non-GNU unofficial values.  */
+
+#define EM_ALPHA	0x9026
+
+/* Legal values for e_version (version).  */
+
+#define EV_NONE		0		/* Invalid ELF version */
+#define EV_CURRENT	1		/* Current version */
+#define EV_NUM		2
+
+/* Section header.  */
+
+typedef struct
+{
+  Elf32_Word	sh_name;		/* Section name (string tbl index) */
+  Elf32_Word	sh_type;		/* Section type */
+  Elf32_Word	sh_flags;		/* Section flags */
+  Elf32_Addr	sh_addr;		/* Section virtual addr at execution */
+  Elf32_Off	sh_offset;		/* Section file offset */
+  Elf32_Word	sh_size;		/* Section size in bytes */
+  Elf32_Word	sh_link;		/* Link to another section */
+  Elf32_Word	sh_info;		/* Additional section information */
+  Elf32_Word	sh_addralign;		/* Section alignment */
+  Elf32_Word	sh_entsize;		/* Entry size if section holds table */
+} Elf32_Shdr;
+
+typedef struct
+{
+  Elf64_Word	sh_name;		/* Section name (string tbl index) */
+  Elf64_Word	sh_type;		/* Section type */
+  Elf64_Xword	sh_flags;		/* Section flags */
+  Elf64_Addr	sh_addr;		/* Section virtual addr at execution */
+  Elf64_Off	sh_offset;		/* Section file offset */
+  Elf64_Xword	sh_size;		/* Section size in bytes */
+  Elf64_Word	sh_link;		/* Link to another section */
+  Elf64_Word	sh_info;		/* Additional section information */
+  Elf64_Xword	sh_addralign;		/* Section alignment */
+  Elf64_Xword	sh_entsize;		/* Entry size if section holds table */
+} Elf64_Shdr;
+
+/* Special section indices.  */
+
+#define SHN_UNDEF	0		/* Undefined section */
+#define SHN_LORESERVE	0xff00		/* Start of reserved indices */
+#define SHN_LOPROC	0xff00		/* Start of processor-specific */
+#define SHN_BEFORE	0xff00		/* Order section before all others
+					   (Solaris).  */
+#define SHN_AFTER	0xff01		/* Order section after all others
+					   (Solaris).  */
+#define SHN_HIPROC	0xff1f		/* End of processor-specific */
+#define SHN_LOOS	0xff20		/* Start of OS-specific */
+#define SHN_HIOS	0xff3f		/* End of OS-specific */
+#define SHN_ABS		0xfff1		/* Associated symbol is absolute */
+#define SHN_COMMON	0xfff2		/* Associated symbol is common */
+#define SHN_XINDEX	0xffff		/* Index is in extra table.  */
+#define SHN_HIRESERVE	0xffff		/* End of reserved indices */
+
+/* Legal values for sh_type (section type).  */
+
+#define SHT_NULL	  0		/* Section header table entry unused */
+#define SHT_PROGBITS	  1		/* Program data */
+#define SHT_SYMTAB	  2		/* Symbol table */
+#define SHT_STRTAB	  3		/* String table */
+#define SHT_RELA	  4		/* Relocation entries with addends */
+#define SHT_HASH	  5		/* Symbol hash table */
+#define SHT_DYNAMIC	  6		/* Dynamic linking information */
+#define SHT_NOTE	  7		/* Notes */
+#define SHT_NOBITS	  8		/* Program space with no data (bss) */
+#define SHT_REL		  9		/* Relocation entries, no addends */
+#define SHT_SHLIB	  10		/* Reserved */
+#define SHT_DYNSYM	  11		/* Dynamic linker symbol table */
+#define SHT_INIT_ARRAY	  14		/* Array of constructors */
+#define SHT_FINI_ARRAY	  15		/* Array of destructors */
+#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
+#define SHT_GROUP	  17		/* Section group */
+#define SHT_SYMTAB_SHNDX  18		/* Extended section indeces */
+#define	SHT_NUM		  19		/* Number of defined types.  */
+#define SHT_LOOS	  0x60000000	/* Start OS-specific.  */
+#define SHT_GNU_HASH	  0x6ffffff6	/* GNU-style hash table.  */
+#define SHT_GNU_LIBLIST	  0x6ffffff7	/* Prelink library list */
+#define SHT_CHECKSUM	  0x6ffffff8	/* Checksum for DSO content.  */
+#define SHT_LOSUNW	  0x6ffffffa	/* Sun-specific low bound.  */
+#define SHT_SUNW_move	  0x6ffffffa
+#define SHT_SUNW_COMDAT   0x6ffffffb
+#define SHT_SUNW_syminfo  0x6ffffffc
+#define SHT_GNU_verdef	  0x6ffffffd	/* Version definition section.  */
+#define SHT_GNU_verneed	  0x6ffffffe	/* Version needs section.  */
+#define SHT_GNU_versym	  0x6fffffff	/* Version symbol table.  */
+#define SHT_HISUNW	  0x6fffffff	/* Sun-specific high bound.  */
+#define SHT_HIOS	  0x6fffffff	/* End OS-specific type */
+#define SHT_LOPROC	  0x70000000	/* Start of processor-specific */
+#define SHT_HIPROC	  0x7fffffff	/* End of processor-specific */
+#define SHT_LOUSER	  0x80000000	/* Start of application-specific */
+#define SHT_HIUSER	  0x8fffffff	/* End of application-specific */
+
+/* Legal values for sh_flags (section flags).  */
+
+#define SHF_WRITE	     (1 << 0)	/* Writable */
+#define SHF_ALLOC	     (1 << 1)	/* Occupies memory during execution */
+#define SHF_EXECINSTR	     (1 << 2)	/* Executable */
+#define SHF_MERGE	     (1 << 4)	/* Might be merged */
+#define SHF_STRINGS	     (1 << 5)	/* Contains nul-terminated strings */
+#define SHF_INFO_LINK	     (1 << 6)	/* `sh_info' contains SHT index */
+#define SHF_LINK_ORDER	     (1 << 7)	/* Preserve order after combining */
+#define SHF_OS_NONCONFORMING (1 << 8)	/* Non-standard OS specific handling
+					   required */
+#define SHF_GROUP	     (1 << 9)	/* Section is member of a group.  */
+#define SHF_TLS		     (1 << 10)	/* Section hold thread-local data.  */
+#define SHF_MASKOS	     0x0ff00000	/* OS-specific.  */
+#define SHF_MASKPROC	     0xf0000000	/* Processor-specific */
+#define SHF_ORDERED	     (1 << 30)	/* Special ordering requirement
+					   (Solaris).  */
+#define SHF_EXCLUDE	     (1 << 31)	/* Section is excluded unless
+					   referenced or allocated (Solaris).*/
+
+/* Section group handling.  */
+#define GRP_COMDAT	0x1		/* Mark group as COMDAT.  */
+
+/* Symbol table entry.  */
+
+typedef struct
+{
+  Elf32_Word	st_name;		/* Symbol name (string tbl index) */
+  Elf32_Addr	st_value;		/* Symbol value */
+  Elf32_Word	st_size;		/* Symbol size */
+  unsigned char	st_info;		/* Symbol type and binding */
+  unsigned char	st_other;		/* Symbol visibility */
+  Elf32_Section	st_shndx;		/* Section index */
+} Elf32_Sym;
+
+typedef struct
+{
+  Elf64_Word	st_name;		/* Symbol name (string tbl index) */
+  unsigned char	st_info;		/* Symbol type and binding */
+  unsigned char st_other;		/* Symbol visibility */
+  Elf64_Section	st_shndx;		/* Section index */
+  Elf64_Addr	st_value;		/* Symbol value */
+  Elf64_Xword	st_size;		/* Symbol size */
+} Elf64_Sym;
+
+/* The syminfo section if available contains additional information about
+   every dynamic symbol.  */
+
+typedef struct
+{
+  Elf32_Half si_boundto;		/* Direct bindings, symbol bound to */
+  Elf32_Half si_flags;			/* Per symbol flags */
+} Elf32_Syminfo;
+
+typedef struct
+{
+  Elf64_Half si_boundto;		/* Direct bindings, symbol bound to */
+  Elf64_Half si_flags;			/* Per symbol flags */
+} Elf64_Syminfo;
+
+/* Possible values for si_boundto.  */
+#define SYMINFO_BT_SELF		0xffff	/* Symbol bound to self */
+#define SYMINFO_BT_PARENT	0xfffe	/* Symbol bound to parent */
+#define SYMINFO_BT_LOWRESERVE	0xff00	/* Beginning of reserved entries */
+
+/* Possible bitmasks for si_flags.  */
+#define SYMINFO_FLG_DIRECT	0x0001	/* Direct bound symbol */
+#define SYMINFO_FLG_PASSTHRU	0x0002	/* Pass-thru symbol for translator */
+#define SYMINFO_FLG_COPY	0x0004	/* Symbol is a copy-reloc */
+#define SYMINFO_FLG_LAZYLOAD	0x0008	/* Symbol bound to object to be lazy
+					   loaded */
+/* Syminfo version values.  */
+#define SYMINFO_NONE		0
+#define SYMINFO_CURRENT		1
+#define SYMINFO_NUM		2
+
+
+/* How to extract and insert information held in the st_info field.  */
+
+#define ELF32_ST_BIND(val)		(((unsigned char) (val)) >> 4)
+#define ELF32_ST_TYPE(val)		((val) & 0xf)
+#define ELF32_ST_INFO(bind, type)	(((bind) << 4) + ((type) & 0xf))
+
+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */
+#define ELF64_ST_BIND(val)		ELF32_ST_BIND (val)
+#define ELF64_ST_TYPE(val)		ELF32_ST_TYPE (val)
+#define ELF64_ST_INFO(bind, type)	ELF32_ST_INFO ((bind), (type))
+
+/* Legal values for ST_BIND subfield of st_info (symbol binding).  */
+
+#define STB_LOCAL	0		/* Local symbol */
+#define STB_GLOBAL	1		/* Global symbol */
+#define STB_WEAK	2		/* Weak symbol */
+#define	STB_NUM		3		/* Number of defined types.  */
+#define STB_LOOS	10		/* Start of OS-specific */
+#define STB_HIOS	12		/* End of OS-specific */
+#define STB_LOPROC	13		/* Start of processor-specific */
+#define STB_HIPROC	15		/* End of processor-specific */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_NOTYPE	0		/* Symbol type is unspecified */
+#define STT_OBJECT	1		/* Symbol is a data object */
+#define STT_FUNC	2		/* Symbol is a code object */
+#define STT_SECTION	3		/* Symbol associated with a section */
+#define STT_FILE	4		/* Symbol's name is file name */
+#define STT_COMMON	5		/* Symbol is a common data object */
+#define STT_TLS		6		/* Symbol is thread-local data object*/
+#define	STT_NUM		7		/* Number of defined types.  */
+#define STT_LOOS	10		/* Start of OS-specific */
+#define STT_HIOS	12		/* End of OS-specific */
+#define STT_LOPROC	13		/* Start of processor-specific */
+#define STT_HIPROC	15		/* End of processor-specific */
+
+
+/* Symbol table indices are found in the hash buckets and chain table
+   of a symbol hash table section.  This special index value indicates
+   the end of a chain, meaning no further symbols are found in that bucket.  */
+
+#define STN_UNDEF	0		/* End of a chain.  */
+
+
+/* How to extract and insert information held in the st_other field.  */
+
+#define ELF32_ST_VISIBILITY(o)	((o) & 0x03)
+
+/* For ELF64 the definitions are the same.  */
+#define ELF64_ST_VISIBILITY(o)	ELF32_ST_VISIBILITY (o)
+
+/* Symbol visibility specification encoded in the st_other field.  */
+#define STV_DEFAULT	0		/* Default symbol visibility rules */
+#define STV_INTERNAL	1		/* Processor specific hidden class */
+#define STV_HIDDEN	2		/* Sym unavailable in other modules */
+#define STV_PROTECTED	3		/* Not preemptible, not exported */
+
+
+/* Relocation table entry without addend (in section of type SHT_REL).  */
+
+typedef struct
+{
+  Elf32_Addr	r_offset;		/* Address */
+  Elf32_Word	r_info;			/* Relocation type and symbol index */
+} Elf32_Rel;
+
+/* I have seen two different definitions of the Elf64_Rel and
+   Elf64_Rela structures, so we'll leave them out until Novell (or
+   whoever) gets their act together.  */
+/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */
+
+typedef struct
+{
+  Elf64_Addr	r_offset;		/* Address */
+  Elf64_Xword	r_info;			/* Relocation type and symbol index */
+} Elf64_Rel;
+
+/* Relocation table entry with addend (in section of type SHT_RELA).  */
+
+typedef struct
+{
+  Elf32_Addr	r_offset;		/* Address */
+  Elf32_Word	r_info;			/* Relocation type and symbol index */
+  Elf32_Sword	r_addend;		/* Addend */
+} Elf32_Rela;
+
+typedef struct
+{
+  Elf64_Addr	r_offset;		/* Address */
+  Elf64_Xword	r_info;			/* Relocation type and symbol index */
+  Elf64_Sxword	r_addend;		/* Addend */
+} Elf64_Rela;
+
+/* How to extract and insert information held in the r_info field.  */
+
+#define ELF32_R_SYM(val)		((val) >> 8)
+#define ELF32_R_TYPE(val)		((val) & 0xff)
+#define ELF32_R_INFO(sym, type)		(((sym) << 8) + ((type) & 0xff))
+
+#define ELF64_R_SYM(i)			((i) >> 32)
+#define ELF64_R_TYPE(i)			((i) & 0xffffffff)
+#define ELF64_R_INFO(sym,type)		((((Elf64_Xword) (sym)) << 32) + (type))
+
+/* Program segment header.  */
+
+typedef struct
+{
+  Elf32_Word	p_type;			/* Segment type */
+  Elf32_Off	p_offset;		/* Segment file offset */
+  Elf32_Addr	p_vaddr;		/* Segment virtual address */
+  Elf32_Addr	p_paddr;		/* Segment physical address */
+  Elf32_Word	p_filesz;		/* Segment size in file */
+  Elf32_Word	p_memsz;		/* Segment size in memory */
+  Elf32_Word	p_flags;		/* Segment flags */
+  Elf32_Word	p_align;		/* Segment alignment */
+} Elf32_Phdr;
+
+typedef struct
+{
+  Elf64_Word	p_type;			/* Segment type */
+  Elf64_Word	p_flags;		/* Segment flags */
+  Elf64_Off	p_offset;		/* Segment file offset */
+  Elf64_Addr	p_vaddr;		/* Segment virtual address */
+  Elf64_Addr	p_paddr;		/* Segment physical address */
+  Elf64_Xword	p_filesz;		/* Segment size in file */
+  Elf64_Xword	p_memsz;		/* Segment size in memory */
+  Elf64_Xword	p_align;		/* Segment alignment */
+} Elf64_Phdr;
+
+/* Legal values for p_type (segment type).  */
+
+#define	PT_NULL		0		/* Program header table entry unused */
+#define PT_LOAD		1		/* Loadable program segment */
+#define PT_DYNAMIC	2		/* Dynamic linking information */
+#define PT_INTERP	3		/* Program interpreter */
+#define PT_NOTE		4		/* Auxiliary information */
+#define PT_SHLIB	5		/* Reserved */
+#define PT_PHDR		6		/* Entry for header table itself */
+#define PT_TLS		7		/* Thread-local storage segment */
+#define	PT_NUM		8		/* Number of defined types */
+#define PT_LOOS		0x60000000	/* Start of OS-specific */
+#define PT_GNU_EH_FRAME	0x6474e550	/* GCC .eh_frame_hdr segment */
+#define PT_GNU_STACK	0x6474e551	/* Indicates stack executability */
+#define PT_GNU_RELRO	0x6474e552	/* Read-only after relocation */
+#define PT_LOSUNW	0x6ffffffa
+#define PT_SUNWBSS	0x6ffffffa	/* Sun Specific segment */
+#define PT_SUNWSTACK	0x6ffffffb	/* Stack segment */
+#define PT_HISUNW	0x6fffffff
+#define PT_HIOS		0x6fffffff	/* End of OS-specific */
+#define PT_LOPROC	0x70000000	/* Start of processor-specific */
+#define PT_HIPROC	0x7fffffff	/* End of processor-specific */
+
+/* Legal values for p_flags (segment flags).  */
+
+#define PF_X		(1 << 0)	/* Segment is executable */
+#define PF_W		(1 << 1)	/* Segment is writable */
+#define PF_R		(1 << 2)	/* Segment is readable */
+#define PF_MASKOS	0x0ff00000	/* OS-specific */
+#define PF_MASKPROC	0xf0000000	/* Processor-specific */
+
+/* Legal values for note segment descriptor types for core files. */
+
+#define NT_PRSTATUS	1		/* Contains copy of prstatus struct */
+#define NT_FPREGSET	2		/* Contains copy of fpregset struct */
+#define NT_PRPSINFO	3		/* Contains copy of prpsinfo struct */
+#define NT_PRXREG	4		/* Contains copy of prxregset struct */
+#define NT_TASKSTRUCT	4		/* Contains copy of task structure */
+#define NT_PLATFORM	5		/* String from sysinfo(SI_PLATFORM) */
+#define NT_AUXV		6		/* Contains copy of auxv array */
+#define NT_GWINDOWS	7		/* Contains copy of gwindows struct */
+#define NT_ASRS		8		/* Contains copy of asrset struct */
+#define NT_PSTATUS	10		/* Contains copy of pstatus struct */
+#define NT_PSINFO	13		/* Contains copy of psinfo struct */
+#define NT_PRCRED	14		/* Contains copy of prcred struct */
+#define NT_UTSNAME	15		/* Contains copy of utsname struct */
+#define NT_LWPSTATUS	16		/* Contains copy of lwpstatus struct */
+#define NT_LWPSINFO	17		/* Contains copy of lwpinfo struct */
+#define NT_PRFPXREG	20		/* Contains copy of fprxregset struct */
+#define NT_PRXFPREG	0x46e62b7f	/* Contains copy of user_fxsr_struct */
+
+/* Legal values for the note segment descriptor types for object files.  */
+
+#define NT_VERSION	1		/* Contains a version string.  */
+
+
+/* Dynamic section entry.  */
+
+typedef struct
+{
+  Elf32_Sword	d_tag;			/* Dynamic entry type */
+  union
+    {
+      Elf32_Word d_val;			/* Integer value */
+      Elf32_Addr d_ptr;			/* Address value */
+    } d_un;
+} Elf32_Dyn;
+
+typedef struct
+{
+  Elf64_Sxword	d_tag;			/* Dynamic entry type */
+  union
+    {
+      Elf64_Xword d_val;		/* Integer value */
+      Elf64_Addr d_ptr;			/* Address value */
+    } d_un;
+} Elf64_Dyn;
+
+/* Legal values for d_tag (dynamic entry type).  */
+
+#define DT_NULL		0		/* Marks end of dynamic section */
+#define DT_NEEDED	1		/* Name of needed library */
+#define DT_PLTRELSZ	2		/* Size in bytes of PLT relocs */
+#define DT_PLTGOT	3		/* Processor defined value */
+#define DT_HASH		4		/* Address of symbol hash table */
+#define DT_STRTAB	5		/* Address of string table */
+#define DT_SYMTAB	6		/* Address of symbol table */
+#define DT_RELA		7		/* Address of Rela relocs */
+#define DT_RELASZ	8		/* Total size of Rela relocs */
+#define DT_RELAENT	9		/* Size of one Rela reloc */
+#define DT_STRSZ	10		/* Size of string table */
+#define DT_SYMENT	11		/* Size of one symbol table entry */
+#define DT_INIT		12		/* Address of init function */
+#define DT_FINI		13		/* Address of termination function */
+#define DT_SONAME	14		/* Name of shared object */
+#define DT_RPATH	15		/* Library search path (deprecated) */
+#define DT_SYMBOLIC	16		/* Start symbol search here */
+#define DT_REL		17		/* Address of Rel relocs */
+#define DT_RELSZ	18		/* Total size of Rel relocs */
+#define DT_RELENT	19		/* Size of one Rel reloc */
+#define DT_PLTREL	20		/* Type of reloc in PLT */
+#define DT_DEBUG	21		/* For debugging; unspecified */
+#define DT_TEXTREL	22		/* Reloc might modify .text */
+#define DT_JMPREL	23		/* Address of PLT relocs */
+#define	DT_BIND_NOW	24		/* Process relocations of object */
+#define	DT_INIT_ARRAY	25		/* Array with addresses of init fct */
+#define	DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
+#define	DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
+#define	DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
+#define DT_RUNPATH	29		/* Library search path */
+#define DT_FLAGS	30		/* Flags for the object being loaded */
+#define DT_ENCODING	32		/* Start of encoded range */
+#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
+#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
+#define	DT_NUM		34		/* Number used */
+#define DT_LOOS		0x6000000d	/* Start of OS-specific */
+#define DT_HIOS		0x6ffff000	/* End of OS-specific */
+#define DT_LOPROC	0x70000000	/* Start of processor-specific */
+#define DT_HIPROC	0x7fffffff	/* End of processor-specific */
+#define	DT_PROCNUM	DT_MIPS_NUM	/* Most used by any processor */
+
+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
+   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's
+   approach.  */
+#define DT_VALRNGLO	0x6ffffd00
+#define DT_GNU_PRELINKED 0x6ffffdf5	/* Prelinking timestamp */
+#define DT_GNU_CONFLICTSZ 0x6ffffdf6	/* Size of conflict section */
+#define DT_GNU_LIBLISTSZ 0x6ffffdf7	/* Size of library list */
+#define DT_CHECKSUM	0x6ffffdf8
+#define DT_PLTPADSZ	0x6ffffdf9
+#define DT_MOVEENT	0x6ffffdfa
+#define DT_MOVESZ	0x6ffffdfb
+#define DT_FEATURE_1	0x6ffffdfc	/* Feature selection (DTF_*).  */
+#define DT_POSFLAG_1	0x6ffffdfd	/* Flags for DT_* entries, effecting
+					   the following DT_* entry.  */
+#define DT_SYMINSZ	0x6ffffdfe	/* Size of syminfo table (in bytes) */
+#define DT_SYMINENT	0x6ffffdff	/* Entry size of syminfo */
+#define DT_VALRNGHI	0x6ffffdff
+#define DT_VALTAGIDX(tag)	(DT_VALRNGHI - (tag))	/* Reverse order! */
+#define DT_VALNUM 12
+
+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
+   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
+
+   If any adjustment is made to the ELF object after it has been
+   built these entries will need to be adjusted.  */
+#define DT_ADDRRNGLO	0x6ffffe00
+#define DT_GNU_HASH	0x6ffffef5	/* GNU-style hash table.  */
+#define DT_TLSDESC_PLT	0x6ffffef6
+#define DT_TLSDESC_GOT	0x6ffffef7
+#define DT_GNU_CONFLICT	0x6ffffef8	/* Start of conflict section */
+#define DT_GNU_LIBLIST	0x6ffffef9	/* Library list */
+#define DT_CONFIG	0x6ffffefa	/* Configuration information.  */
+#define DT_DEPAUDIT	0x6ffffefb	/* Dependency auditing.  */
+#define DT_AUDIT	0x6ffffefc	/* Object auditing.  */
+#define	DT_PLTPAD	0x6ffffefd	/* PLT padding.  */
+#define	DT_MOVETAB	0x6ffffefe	/* Move table.  */
+#define DT_SYMINFO	0x6ffffeff	/* Syminfo table.  */
+#define DT_ADDRRNGHI	0x6ffffeff
+#define DT_ADDRTAGIDX(tag)	(DT_ADDRRNGHI - (tag))	/* Reverse order! */
+#define DT_ADDRNUM 11
+
+/* The versioning entry types.  The next are defined as part of the
+   GNU extension.  */
+#define DT_VERSYM	0x6ffffff0
+
+#define DT_RELACOUNT	0x6ffffff9
+#define DT_RELCOUNT	0x6ffffffa
+
+/* These were chosen by Sun.  */
+#define DT_FLAGS_1	0x6ffffffb	/* State flags, see DF_1_* below.  */
+#define	DT_VERDEF	0x6ffffffc	/* Address of version definition
+					   table */
+#define	DT_VERDEFNUM	0x6ffffffd	/* Number of version definitions */
+#define	DT_VERNEED	0x6ffffffe	/* Address of table with needed
+					   versions */
+#define	DT_VERNEEDNUM	0x6fffffff	/* Number of needed versions */
+#define DT_VERSIONTAGIDX(tag)	(DT_VERNEEDNUM - (tag))	/* Reverse order! */
+#define DT_VERSIONTAGNUM 16
+
+/* Sun added these machine-independent extensions in the "processor-specific"
+   range.  Be compatible.  */
+#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */
+#define DT_FILTER       0x7fffffff      /* Shared object to get values from */
+#define DT_EXTRATAGIDX(tag)	((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)
+#define DT_EXTRANUM	3
+
+/* Values of `d_un.d_val' in the DT_FLAGS entry.  */
+#define DF_ORIGIN	0x00000001	/* Object may use DF_ORIGIN */
+#define DF_SYMBOLIC	0x00000002	/* Symbol resolutions starts here */
+#define DF_TEXTREL	0x00000004	/* Object contains text relocations */
+#define DF_BIND_NOW	0x00000008	/* No lazy binding for this object */
+#define DF_STATIC_TLS	0x00000010	/* Module uses the static TLS model */
+
+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1
+   entry in the dynamic section.  */
+#define DF_1_NOW	0x00000001	/* Set RTLD_NOW for this object.  */
+#define DF_1_GLOBAL	0x00000002	/* Set RTLD_GLOBAL for this object.  */
+#define DF_1_GROUP	0x00000004	/* Set RTLD_GROUP for this object.  */
+#define DF_1_NODELETE	0x00000008	/* Set RTLD_NODELETE for this object.*/
+#define DF_1_LOADFLTR	0x00000010	/* Trigger filtee loading at runtime.*/
+#define DF_1_INITFIRST	0x00000020	/* Set RTLD_INITFIRST for this object*/
+#define DF_1_NOOPEN	0x00000040	/* Set RTLD_NOOPEN for this object.  */
+#define DF_1_ORIGIN	0x00000080	/* $ORIGIN must be handled.  */
+#define DF_1_DIRECT	0x00000100	/* Direct binding enabled.  */
+#define DF_1_TRANS	0x00000200
+#define DF_1_INTERPOSE	0x00000400	/* Object is used to interpose.  */
+#define DF_1_NODEFLIB	0x00000800	/* Ignore default lib search path.  */
+#define DF_1_NODUMP	0x00001000	/* Object can't be dldump'ed.  */
+#define DF_1_CONFALT	0x00002000	/* Configuration alternative created.*/
+#define DF_1_ENDFILTEE	0x00004000	/* Filtee terminates filters search. */
+#define	DF_1_DISPRELDNE	0x00008000	/* Disp reloc applied at build time. */
+#define	DF_1_DISPRELPND	0x00010000	/* Disp reloc applied at run-time.  */
+
+/* Flags for the feature selection in DT_FEATURE_1.  */
+#define DTF_1_PARINIT	0x00000001
+#define DTF_1_CONFEXP	0x00000002
+
+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */
+#define DF_P1_LAZYLOAD	0x00000001	/* Lazyload following object.  */
+#define DF_P1_GROUPPERM	0x00000002	/* Symbols from next object are not
+					   generally available.  */
+
+/* Version definition sections.  */
+
+typedef struct
+{
+  Elf32_Half	vd_version;		/* Version revision */
+  Elf32_Half	vd_flags;		/* Version information */
+  Elf32_Half	vd_ndx;			/* Version Index */
+  Elf32_Half	vd_cnt;			/* Number of associated aux entries */
+  Elf32_Word	vd_hash;		/* Version name hash value */
+  Elf32_Word	vd_aux;			/* Offset in bytes to verdaux array */
+  Elf32_Word	vd_next;		/* Offset in bytes to next verdef
+					   entry */
+} Elf32_Verdef;
+
+typedef struct
+{
+  Elf64_Half	vd_version;		/* Version revision */
+  Elf64_Half	vd_flags;		/* Version information */
+  Elf64_Half	vd_ndx;			/* Version Index */
+  Elf64_Half	vd_cnt;			/* Number of associated aux entries */
+  Elf64_Word	vd_hash;		/* Version name hash value */
+  Elf64_Word	vd_aux;			/* Offset in bytes to verdaux array */
+  Elf64_Word	vd_next;		/* Offset in bytes to next verdef
+					   entry */
+} Elf64_Verdef;
+
+
+/* Legal values for vd_version (version revision).  */
+#define VER_DEF_NONE	0		/* No version */
+#define VER_DEF_CURRENT	1		/* Current version */
+#define VER_DEF_NUM	2		/* Given version number */
+
+/* Legal values for vd_flags (version information flags).  */
+#define VER_FLG_BASE	0x1		/* Version definition of file itself */
+#define VER_FLG_WEAK	0x2		/* Weak version identifier */
+
+/* Versym symbol index values.  */
+#define	VER_NDX_LOCAL		0	/* Symbol is local.  */
+#define	VER_NDX_GLOBAL		1	/* Symbol is global.  */
+#define	VER_NDX_LORESERVE	0xff00	/* Beginning of reserved entries.  */
+#define	VER_NDX_ELIMINATE	0xff01	/* Symbol is to be eliminated.  */
+
+/* Auxialiary version information.  */
+
+typedef struct
+{
+  Elf32_Word	vda_name;		/* Version or dependency names */
+  Elf32_Word	vda_next;		/* Offset in bytes to next verdaux
+					   entry */
+} Elf32_Verdaux;
+
+typedef struct
+{
+  Elf64_Word	vda_name;		/* Version or dependency names */
+  Elf64_Word	vda_next;		/* Offset in bytes to next verdaux
+					   entry */
+} Elf64_Verdaux;
+
+
+/* Version dependency section.  */
+
+typedef struct
+{
+  Elf32_Half	vn_version;		/* Version of structure */
+  Elf32_Half	vn_cnt;			/* Number of associated aux entries */
+  Elf32_Word	vn_file;		/* Offset of filename for this
+					   dependency */
+  Elf32_Word	vn_aux;			/* Offset in bytes to vernaux array */
+  Elf32_Word	vn_next;		/* Offset in bytes to next verneed
+					   entry */
+} Elf32_Verneed;
+
+typedef struct
+{
+  Elf64_Half	vn_version;		/* Version of structure */
+  Elf64_Half	vn_cnt;			/* Number of associated aux entries */
+  Elf64_Word	vn_file;		/* Offset of filename for this
+					   dependency */
+  Elf64_Word	vn_aux;			/* Offset in bytes to vernaux array */
+  Elf64_Word	vn_next;		/* Offset in bytes to next verneed
+					   entry */
+} Elf64_Verneed;
+
+
+/* Legal values for vn_version (version revision).  */
+#define VER_NEED_NONE	 0		/* No version */
+#define VER_NEED_CURRENT 1		/* Current version */
+#define VER_NEED_NUM	 2		/* Given version number */
+
+/* Auxiliary needed version information.  */
+
+typedef struct
+{
+  Elf32_Word	vna_hash;		/* Hash value of dependency name */
+  Elf32_Half	vna_flags;		/* Dependency specific information */
+  Elf32_Half	vna_other;		/* Unused */
+  Elf32_Word	vna_name;		/* Dependency name string offset */
+  Elf32_Word	vna_next;		/* Offset in bytes to next vernaux
+					   entry */
+} Elf32_Vernaux;
+
+typedef struct
+{
+  Elf64_Word	vna_hash;		/* Hash value of dependency name */
+  Elf64_Half	vna_flags;		/* Dependency specific information */
+  Elf64_Half	vna_other;		/* Unused */
+  Elf64_Word	vna_name;		/* Dependency name string offset */
+  Elf64_Word	vna_next;		/* Offset in bytes to next vernaux
+					   entry */
+} Elf64_Vernaux;
+
+
+/* Legal values for vna_flags.  */
+#define VER_FLG_WEAK	0x2		/* Weak version identifier */
+
+
+/* Auxiliary vector.  */
+
+/* This vector is normally only used by the program interpreter.  The
+   usual definition in an ABI supplement uses the name auxv_t.  The
+   vector is not usually defined in a standard <elf.h> file, but it
+   can't hurt.  We rename it to avoid conflicts.  The sizes of these
+   types are an arrangement between the exec server and the program
+   interpreter, so we don't fully specify them here.  */
+
+typedef struct
+{
+  uint32_t a_type;		/* Entry type */
+  union
+    {
+      uint32_t a_val;		/* Integer value */
+      /* We use to have pointer elements added here.  We cannot do that,
+	 though, since it does not work when using 32-bit definitions
+	 on 64-bit platforms and vice versa.  */
+    } a_un;
+} Elf32_auxv_t;
+
+typedef struct
+{
+  uint64_t a_type;		/* Entry type */
+  union
+    {
+      uint64_t a_val;		/* Integer value */
+      /* We use to have pointer elements added here.  We cannot do that,
+	 though, since it does not work when using 32-bit definitions
+	 on 64-bit platforms and vice versa.  */
+    } a_un;
+} Elf64_auxv_t;
+
+/* Legal values for a_type (entry type).  */
+
+#define AT_NULL		0		/* End of vector */
+#define AT_IGNORE	1		/* Entry should be ignored */
+#define AT_EXECFD	2		/* File descriptor of program */
+#define AT_PHDR		3		/* Program headers for program */
+#define AT_PHENT	4		/* Size of program header entry */
+#define AT_PHNUM	5		/* Number of program headers */
+#define AT_PAGESZ	6		/* System page size */
+#define AT_BASE		7		/* Base address of interpreter */
+#define AT_FLAGS	8		/* Flags */
+#define AT_ENTRY	9		/* Entry point of program */
+#define AT_NOTELF	10		/* Program is not ELF */
+#define AT_UID		11		/* Real uid */
+#define AT_EUID		12		/* Effective uid */
+#define AT_GID		13		/* Real gid */
+#define AT_EGID		14		/* Effective gid */
+#define AT_CLKTCK	17		/* Frequency of times() */
+
+/* Some more special a_type values describing the hardware.  */
+#define AT_PLATFORM	15		/* String identifying platform.  */
+#define AT_HWCAP	16		/* Machine dependent hints about
+					   processor capabilities.  */
+
+/* This entry gives some information about the FPU initialization
+   performed by the kernel.  */
+#define AT_FPUCW	18		/* Used FPU control word.  */
+
+/* Cache block sizes.  */
+#define AT_DCACHEBSIZE	19		/* Data cache block size.  */
+#define AT_ICACHEBSIZE	20		/* Instruction cache block size.  */
+#define AT_UCACHEBSIZE	21		/* Unified cache block size.  */
+
+/* A special ignored value for PPC, used by the kernel to control the
+   interpretation of the AUXV. Must be > 16.  */
+#define AT_IGNOREPPC	22		/* Entry should be ignored.  */
+
+#define	AT_SECURE	23		/* Boolean, was exec setuid-like?  */
+
+/* Pointer to the global system page used for system calls and other
+   nice things.  */
+#define AT_SYSINFO	32
+#define AT_SYSINFO_EHDR	33
+
+/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains
+   log2 of line size; mask those to get cache size.  */
+#define AT_L1I_CACHESHAPE	34
+#define AT_L1D_CACHESHAPE	35
+#define AT_L2_CACHESHAPE	36
+#define AT_L3_CACHESHAPE	37
+
+/* Note section contents.  Each entry in the note section begins with
+   a header of a fixed form.  */
+
+typedef struct
+{
+  Elf32_Word n_namesz;			/* Length of the note's name.  */
+  Elf32_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf32_Word n_type;			/* Type of the note.  */
+} Elf32_Nhdr;
+
+typedef struct
+{
+  Elf64_Word n_namesz;			/* Length of the note's name.  */
+  Elf64_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf64_Word n_type;			/* Type of the note.  */
+} Elf64_Nhdr;
+
+/* Known names of notes.  */
+
+/* Solaris entries in the note section have this name.  */
+#define ELF_NOTE_SOLARIS	"SUNW Solaris"
+
+/* Note entries for GNU systems have this name.  */
+#define ELF_NOTE_GNU		"GNU"
+
+
+/* Defined types of notes for Solaris.  */
+
+/* Value of descriptor (one word) is desired pagesize for the binary.  */
+#define ELF_NOTE_PAGESIZE_HINT	1
+
+
+/* Defined note types for GNU systems.  */
+
+/* ABI information.  The descriptor consists of words:
+   word 0: OS descriptor
+   word 1: major version of the ABI
+   word 2: minor version of the ABI
+   word 3: subminor version of the ABI
+*/
+#define NT_GNU_ABI_TAG	1
+#define ELF_NOTE_ABI	NT_GNU_ABI_TAG /* Old name.  */
+
+/* Known OSes.  These values can appear in word 0 of an
+   NT_GNU_ABI_TAG note section entry.  */
+#define ELF_NOTE_OS_LINUX	0
+#define ELF_NOTE_OS_GNU		1
+#define ELF_NOTE_OS_SOLARIS2	2
+#define ELF_NOTE_OS_FREEBSD	3
+
+/* Synthetic hwcap information.  The descriptor begins with two words:
+   word 0: number of entries
+   word 1: bitmask of enabled entries
+   Then follow variable-length entries, one byte followed by a
+   '\0'-terminated hwcap name string.  The byte gives the bit
+   number to test if enabled, (1U << bit) & bitmask.  */
+#define NT_GNU_HWCAP	2
+
+/* Build ID bits as generated by ld --build-id.
+   The descriptor consists of any nonzero number of bytes.  */
+#define NT_GNU_BUILD_ID	3
+
+
+/* Move records.  */
+typedef struct
+{
+  Elf32_Xword m_value;		/* Symbol value.  */
+  Elf32_Word m_info;		/* Size and index.  */
+  Elf32_Word m_poffset;		/* Symbol offset.  */
+  Elf32_Half m_repeat;		/* Repeat count.  */
+  Elf32_Half m_stride;		/* Stride info.  */
+} Elf32_Move;
+
+typedef struct
+{
+  Elf64_Xword m_value;		/* Symbol value.  */
+  Elf64_Xword m_info;		/* Size and index.  */
+  Elf64_Xword m_poffset;	/* Symbol offset.  */
+  Elf64_Half m_repeat;		/* Repeat count.  */
+  Elf64_Half m_stride;		/* Stride info.  */
+} Elf64_Move;
+
+/* Macro to construct move records.  */
+#define ELF32_M_SYM(info)	((info) >> 8)
+#define ELF32_M_SIZE(info)	((unsigned char) (info))
+#define ELF32_M_INFO(sym, size)	(((sym) << 8) + (unsigned char) (size))
+
+#define ELF64_M_SYM(info)	ELF32_M_SYM (info)
+#define ELF64_M_SIZE(info)	ELF32_M_SIZE (info)
+#define ELF64_M_INFO(sym, size)	ELF32_M_INFO (sym, size)
+
+
+/* Motorola 68k specific definitions.  */
+
+/* Values for Elf32_Ehdr.e_flags.  */
+#define EF_CPU32	0x00810000
+
+/* m68k relocs.  */
+
+#define R_68K_NONE	0		/* No reloc */
+#define R_68K_32	1		/* Direct 32 bit  */
+#define R_68K_16	2		/* Direct 16 bit  */
+#define R_68K_8		3		/* Direct 8 bit  */
+#define R_68K_PC32	4		/* PC relative 32 bit */
+#define R_68K_PC16	5		/* PC relative 16 bit */
+#define R_68K_PC8	6		/* PC relative 8 bit */
+#define R_68K_GOT32	7		/* 32 bit PC relative GOT entry */
+#define R_68K_GOT16	8		/* 16 bit PC relative GOT entry */
+#define R_68K_GOT8	9		/* 8 bit PC relative GOT entry */
+#define R_68K_GOT32O	10		/* 32 bit GOT offset */
+#define R_68K_GOT16O	11		/* 16 bit GOT offset */
+#define R_68K_GOT8O	12		/* 8 bit GOT offset */
+#define R_68K_PLT32	13		/* 32 bit PC relative PLT address */
+#define R_68K_PLT16	14		/* 16 bit PC relative PLT address */
+#define R_68K_PLT8	15		/* 8 bit PC relative PLT address */
+#define R_68K_PLT32O	16		/* 32 bit PLT offset */
+#define R_68K_PLT16O	17		/* 16 bit PLT offset */
+#define R_68K_PLT8O	18		/* 8 bit PLT offset */
+#define R_68K_COPY	19		/* Copy symbol at runtime */
+#define R_68K_GLOB_DAT	20		/* Create GOT entry */
+#define R_68K_JMP_SLOT	21		/* Create PLT entry */
+#define R_68K_RELATIVE	22		/* Adjust by program base */
+/* Keep this the last entry.  */
+#define R_68K_NUM	23
+
+/* Intel 80386 specific definitions.  */
+
+/* i386 relocs.  */
+
+#define R_386_NONE	   0		/* No reloc */
+#define R_386_32	   1		/* Direct 32 bit  */
+#define R_386_PC32	   2		/* PC relative 32 bit */
+#define R_386_GOT32	   3		/* 32 bit GOT entry */
+#define R_386_PLT32	   4		/* 32 bit PLT address */
+#define R_386_COPY	   5		/* Copy symbol at runtime */
+#define R_386_GLOB_DAT	   6		/* Create GOT entry */
+#define R_386_JMP_SLOT	   7		/* Create PLT entry */
+#define R_386_RELATIVE	   8		/* Adjust by program base */
+#define R_386_GOTOFF	   9		/* 32 bit offset to GOT */
+#define R_386_GOTPC	   10		/* 32 bit PC relative offset to GOT */
+#define R_386_32PLT	   11
+#define R_386_TLS_TPOFF	   14		/* Offset in static TLS block */
+#define R_386_TLS_IE	   15		/* Address of GOT entry for static TLS
+					   block offset */
+#define R_386_TLS_GOTIE	   16		/* GOT entry for static TLS block
+					   offset */
+#define R_386_TLS_LE	   17		/* Offset relative to static TLS
+					   block */
+#define R_386_TLS_GD	   18		/* Direct 32 bit for GNU version of
+					   general dynamic thread local data */
+#define R_386_TLS_LDM	   19		/* Direct 32 bit for GNU version of
+					   local dynamic thread local data
+					   in LE code */
+#define R_386_16	   20
+#define R_386_PC16	   21
+#define R_386_8		   22
+#define R_386_PC8	   23
+#define R_386_TLS_GD_32	   24		/* Direct 32 bit for general dynamic
+					   thread local data */
+#define R_386_TLS_GD_PUSH  25		/* Tag for pushl in GD TLS code */
+#define R_386_TLS_GD_CALL  26		/* Relocation for call to
+					   __tls_get_addr() */
+#define R_386_TLS_GD_POP   27		/* Tag for popl in GD TLS code */
+#define R_386_TLS_LDM_32   28		/* Direct 32 bit for local dynamic
+					   thread local data in LE code */
+#define R_386_TLS_LDM_PUSH 29		/* Tag for pushl in LDM TLS code */
+#define R_386_TLS_LDM_CALL 30		/* Relocation for call to
+					   __tls_get_addr() in LDM code */
+#define R_386_TLS_LDM_POP  31		/* Tag for popl in LDM TLS code */
+#define R_386_TLS_LDO_32   32		/* Offset relative to TLS block */
+#define R_386_TLS_IE_32	   33		/* GOT entry for negated static TLS
+					   block offset */
+#define R_386_TLS_LE_32	   34		/* Negated offset relative to static
+					   TLS block */
+#define R_386_TLS_DTPMOD32 35		/* ID of module containing symbol */
+#define R_386_TLS_DTPOFF32 36		/* Offset in TLS block */
+#define R_386_TLS_TPOFF32  37		/* Negated offset in static TLS block */
+/* Keep this the last entry.  */
+#define R_386_NUM	   38
+
+/* SUN SPARC specific definitions.  */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_SPARC_REGISTER	13	/* Global register reserved to app. */
+
+/* Values for Elf64_Ehdr.e_flags.  */
+
+#define EF_SPARCV9_MM		3
+#define EF_SPARCV9_TSO		0
+#define EF_SPARCV9_PSO		1
+#define EF_SPARCV9_RMO		2
+#define EF_SPARC_LEDATA		0x800000 /* little endian data */
+#define EF_SPARC_EXT_MASK	0xFFFF00
+#define EF_SPARC_32PLUS		0x000100 /* generic V8+ features */
+#define EF_SPARC_SUN_US1	0x000200 /* Sun UltraSPARC1 extensions */
+#define EF_SPARC_HAL_R1		0x000400 /* HAL R1 extensions */
+#define EF_SPARC_SUN_US3	0x000800 /* Sun UltraSPARCIII extensions */
+
+/* SPARC relocs.  */
+
+#define R_SPARC_NONE		0	/* No reloc */
+#define R_SPARC_8		1	/* Direct 8 bit */
+#define R_SPARC_16		2	/* Direct 16 bit */
+#define R_SPARC_32		3	/* Direct 32 bit */
+#define R_SPARC_DISP8		4	/* PC relative 8 bit */
+#define R_SPARC_DISP16		5	/* PC relative 16 bit */
+#define R_SPARC_DISP32		6	/* PC relative 32 bit */
+#define R_SPARC_WDISP30		7	/* PC relative 30 bit shifted */
+#define R_SPARC_WDISP22		8	/* PC relative 22 bit shifted */
+#define R_SPARC_HI22		9	/* High 22 bit */
+#define R_SPARC_22		10	/* Direct 22 bit */
+#define R_SPARC_13		11	/* Direct 13 bit */
+#define R_SPARC_LO10		12	/* Truncated 10 bit */
+#define R_SPARC_GOT10		13	/* Truncated 10 bit GOT entry */
+#define R_SPARC_GOT13		14	/* 13 bit GOT entry */
+#define R_SPARC_GOT22		15	/* 22 bit GOT entry shifted */
+#define R_SPARC_PC10		16	/* PC relative 10 bit truncated */
+#define R_SPARC_PC22		17	/* PC relative 22 bit shifted */
+#define R_SPARC_WPLT30		18	/* 30 bit PC relative PLT address */
+#define R_SPARC_COPY		19	/* Copy symbol at runtime */
+#define R_SPARC_GLOB_DAT	20	/* Create GOT entry */
+#define R_SPARC_JMP_SLOT	21	/* Create PLT entry */
+#define R_SPARC_RELATIVE	22	/* Adjust by program base */
+#define R_SPARC_UA32		23	/* Direct 32 bit unaligned */
+
+/* Additional Sparc64 relocs.  */
+
+#define R_SPARC_PLT32		24	/* Direct 32 bit ref to PLT entry */
+#define R_SPARC_HIPLT22		25	/* High 22 bit PLT entry */
+#define R_SPARC_LOPLT10		26	/* Truncated 10 bit PLT entry */
+#define R_SPARC_PCPLT32		27	/* PC rel 32 bit ref to PLT entry */
+#define R_SPARC_PCPLT22		28	/* PC rel high 22 bit PLT entry */
+#define R_SPARC_PCPLT10		29	/* PC rel trunc 10 bit PLT entry */
+#define R_SPARC_10		30	/* Direct 10 bit */
+#define R_SPARC_11		31	/* Direct 11 bit */
+#define R_SPARC_64		32	/* Direct 64 bit */
+#define R_SPARC_OLO10		33	/* 10bit with secondary 13bit addend */
+#define R_SPARC_HH22		34	/* Top 22 bits of direct 64 bit */
+#define R_SPARC_HM10		35	/* High middle 10 bits of ... */
+#define R_SPARC_LM22		36	/* Low middle 22 bits of ... */
+#define R_SPARC_PC_HH22		37	/* Top 22 bits of pc rel 64 bit */
+#define R_SPARC_PC_HM10		38	/* High middle 10 bit of ... */
+#define R_SPARC_PC_LM22		39	/* Low miggle 22 bits of ... */
+#define R_SPARC_WDISP16		40	/* PC relative 16 bit shifted */
+#define R_SPARC_WDISP19		41	/* PC relative 19 bit shifted */
+#define R_SPARC_7		43	/* Direct 7 bit */
+#define R_SPARC_5		44	/* Direct 5 bit */
+#define R_SPARC_6		45	/* Direct 6 bit */
+#define R_SPARC_DISP64		46	/* PC relative 64 bit */
+#define R_SPARC_PLT64		47	/* Direct 64 bit ref to PLT entry */
+#define R_SPARC_HIX22		48	/* High 22 bit complemented */
+#define R_SPARC_LOX10		49	/* Truncated 11 bit complemented */
+#define R_SPARC_H44		50	/* Direct high 12 of 44 bit */
+#define R_SPARC_M44		51	/* Direct mid 22 of 44 bit */
+#define R_SPARC_L44		52	/* Direct low 10 of 44 bit */
+#define R_SPARC_REGISTER	53	/* Global register usage */
+#define R_SPARC_UA64		54	/* Direct 64 bit unaligned */
+#define R_SPARC_UA16		55	/* Direct 16 bit unaligned */
+#define R_SPARC_TLS_GD_HI22	56
+#define R_SPARC_TLS_GD_LO10	57
+#define R_SPARC_TLS_GD_ADD	58
+#define R_SPARC_TLS_GD_CALL	59
+#define R_SPARC_TLS_LDM_HI22	60
+#define R_SPARC_TLS_LDM_LO10	61
+#define R_SPARC_TLS_LDM_ADD	62
+#define R_SPARC_TLS_LDM_CALL	63
+#define R_SPARC_TLS_LDO_HIX22	64
+#define R_SPARC_TLS_LDO_LOX10	65
+#define R_SPARC_TLS_LDO_ADD	66
+#define R_SPARC_TLS_IE_HI22	67
+#define R_SPARC_TLS_IE_LO10	68
+#define R_SPARC_TLS_IE_LD	69
+#define R_SPARC_TLS_IE_LDX	70
+#define R_SPARC_TLS_IE_ADD	71
+#define R_SPARC_TLS_LE_HIX22	72
+#define R_SPARC_TLS_LE_LOX10	73
+#define R_SPARC_TLS_DTPMOD32	74
+#define R_SPARC_TLS_DTPMOD64	75
+#define R_SPARC_TLS_DTPOFF32	76
+#define R_SPARC_TLS_DTPOFF64	77
+#define R_SPARC_TLS_TPOFF32	78
+#define R_SPARC_TLS_TPOFF64	79
+/* Keep this the last entry.  */
+#define R_SPARC_NUM		80
+
+/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */
+
+#define DT_SPARC_REGISTER 0x70000001
+#define DT_SPARC_NUM	2
+
+/* Bits present in AT_HWCAP on SPARC.  */
+
+#define HWCAP_SPARC_FLUSH	1	/* The CPU supports flush insn.  */
+#define HWCAP_SPARC_STBAR	2
+#define HWCAP_SPARC_SWAP	4
+#define HWCAP_SPARC_MULDIV	8
+#define HWCAP_SPARC_V9		16	/* The CPU is v9, so v8plus is ok.  */
+#define HWCAP_SPARC_ULTRA3	32
+#define HWCAP_SPARC_BLKINIT	64	/* Sun4v with block-init/load-twin.  */
+
+/* MIPS R3000 specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_MIPS_NOREORDER   1		/* A .noreorder directive was used */
+#define EF_MIPS_PIC	    2		/* Contains PIC code */
+#define EF_MIPS_CPIC	    4		/* Uses PIC calling sequence */
+#define EF_MIPS_XGOT	    8
+#define EF_MIPS_64BIT_WHIRL 16
+#define EF_MIPS_ABI2	    32
+#define EF_MIPS_ABI_ON32    64
+#define EF_MIPS_ARCH	    0xf0000000	/* MIPS architecture level */
+
+/* Legal values for MIPS architecture level.  */
+
+#define EF_MIPS_ARCH_1	    0x00000000	/* -mips1 code.  */
+#define EF_MIPS_ARCH_2	    0x10000000	/* -mips2 code.  */
+#define EF_MIPS_ARCH_3	    0x20000000	/* -mips3 code.  */
+#define EF_MIPS_ARCH_4	    0x30000000	/* -mips4 code.  */
+#define EF_MIPS_ARCH_5	    0x40000000	/* -mips5 code.  */
+#define EF_MIPS_ARCH_32	    0x60000000	/* MIPS32 code.  */
+#define EF_MIPS_ARCH_64	    0x70000000	/* MIPS64 code.  */
+
+/* The following are non-official names and should not be used.  */
+
+#define E_MIPS_ARCH_1	  0x00000000	/* -mips1 code.  */
+#define E_MIPS_ARCH_2	  0x10000000	/* -mips2 code.  */
+#define E_MIPS_ARCH_3	  0x20000000	/* -mips3 code.  */
+#define E_MIPS_ARCH_4	  0x30000000	/* -mips4 code.  */
+#define E_MIPS_ARCH_5	  0x40000000	/* -mips5 code.  */
+#define E_MIPS_ARCH_32	  0x60000000	/* MIPS32 code.  */
+#define E_MIPS_ARCH_64	  0x70000000	/* MIPS64 code.  */
+
+/* Special section indices.  */
+
+#define SHN_MIPS_ACOMMON    0xff00	/* Allocated common symbols */
+#define SHN_MIPS_TEXT	    0xff01	/* Allocated test symbols.  */
+#define SHN_MIPS_DATA	    0xff02	/* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON    0xff03	/* Small common symbols */
+#define SHN_MIPS_SUNDEFINED 0xff04	/* Small undefined symbols */
+
+/* Legal values for sh_type field of Elf32_Shdr.  */
+
+#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */
+#define SHT_MIPS_MSYM	       0x70000001
+#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */
+#define SHT_MIPS_GPTAB	       0x70000003 /* Global data area sizes */
+#define SHT_MIPS_UCODE	       0x70000004 /* Reserved for SGI/MIPS compilers */
+#define SHT_MIPS_DEBUG	       0x70000005 /* MIPS ECOFF debugging information*/
+#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */
+#define SHT_MIPS_PACKAGE       0x70000007
+#define SHT_MIPS_PACKSYM       0x70000008
+#define SHT_MIPS_RELD	       0x70000009
+#define SHT_MIPS_IFACE         0x7000000b
+#define SHT_MIPS_CONTENT       0x7000000c
+#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */
+#define SHT_MIPS_SHDR	       0x70000010
+#define SHT_MIPS_FDESC	       0x70000011
+#define SHT_MIPS_EXTSYM	       0x70000012
+#define SHT_MIPS_DENSE	       0x70000013
+#define SHT_MIPS_PDESC	       0x70000014
+#define SHT_MIPS_LOCSYM	       0x70000015
+#define SHT_MIPS_AUXSYM	       0x70000016
+#define SHT_MIPS_OPTSYM	       0x70000017
+#define SHT_MIPS_LOCSTR	       0x70000018
+#define SHT_MIPS_LINE	       0x70000019
+#define SHT_MIPS_RFDESC	       0x7000001a
+#define SHT_MIPS_DELTASYM      0x7000001b
+#define SHT_MIPS_DELTAINST     0x7000001c
+#define SHT_MIPS_DELTACLASS    0x7000001d
+#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */
+#define SHT_MIPS_DELTADECL     0x7000001f
+#define SHT_MIPS_SYMBOL_LIB    0x70000020
+#define SHT_MIPS_EVENTS	       0x70000021 /* Event section.  */
+#define SHT_MIPS_TRANSLATE     0x70000022
+#define SHT_MIPS_PIXIE	       0x70000023
+#define SHT_MIPS_XLATE	       0x70000024
+#define SHT_MIPS_XLATE_DEBUG   0x70000025
+#define SHT_MIPS_WHIRL	       0x70000026
+#define SHT_MIPS_EH_REGION     0x70000027
+#define SHT_MIPS_XLATE_OLD     0x70000028
+#define SHT_MIPS_PDR_EXCEPTION 0x70000029
+
+/* Legal values for sh_flags field of Elf32_Shdr.  */
+
+#define SHF_MIPS_GPREL	 0x10000000	/* Must be part of global data area */
+#define SHF_MIPS_MERGE	 0x20000000
+#define SHF_MIPS_ADDR	 0x40000000
+#define SHF_MIPS_STRINGS 0x80000000
+#define SHF_MIPS_NOSTRIP 0x08000000
+#define SHF_MIPS_LOCAL	 0x04000000
+#define SHF_MIPS_NAMES	 0x02000000
+#define SHF_MIPS_NODUPE	 0x01000000
+
+
+/* Symbol tables.  */
+
+/* MIPS specific values for `st_other'.  */
+#define STO_MIPS_DEFAULT		0x0
+#define STO_MIPS_INTERNAL		0x1
+#define STO_MIPS_HIDDEN			0x2
+#define STO_MIPS_PROTECTED		0x3
+#define STO_MIPS_SC_ALIGN_UNUSED	0xff
+
+/* MIPS specific values for `st_info'.  */
+#define STB_MIPS_SPLIT_COMMON		13
+
+/* Entries found in sections of type SHT_MIPS_GPTAB.  */
+
+typedef union
+{
+  struct
+    {
+      Elf32_Word gt_current_g_value;	/* -G value used for compilation */
+      Elf32_Word gt_unused;		/* Not used */
+    } gt_header;			/* First entry in section */
+  struct
+    {
+      Elf32_Word gt_g_value;		/* If this value were used for -G */
+      Elf32_Word gt_bytes;		/* This many bytes would be used */
+    } gt_entry;				/* Subsequent entries in section */
+} Elf32_gptab;
+
+/* Entry found in sections of type SHT_MIPS_REGINFO.  */
+
+typedef struct
+{
+  Elf32_Word	ri_gprmask;		/* General registers used */
+  Elf32_Word	ri_cprmask[4];		/* Coprocessor registers used */
+  Elf32_Sword	ri_gp_value;		/* $gp register value */
+} Elf32_RegInfo;
+
+/* Entries found in sections of type SHT_MIPS_OPTIONS.  */
+
+typedef struct
+{
+  unsigned char kind;		/* Determines interpretation of the
+				   variable part of descriptor.  */
+  unsigned char size;		/* Size of descriptor, including header.  */
+  Elf32_Section section;	/* Section header index of section affected,
+				   0 for global options.  */
+  Elf32_Word info;		/* Kind-specific information.  */
+} Elf_Options;
+
+/* Values for `kind' field in Elf_Options.  */
+
+#define ODK_NULL	0	/* Undefined.  */
+#define ODK_REGINFO	1	/* Register usage information.  */
+#define ODK_EXCEPTIONS	2	/* Exception processing options.  */
+#define ODK_PAD		3	/* Section padding options.  */
+#define ODK_HWPATCH	4	/* Hardware workarounds performed */
+#define ODK_FILL	5	/* record the fill value used by the linker. */
+#define ODK_TAGS	6	/* reserve space for desktop tools to write. */
+#define ODK_HWAND	7	/* HW workarounds.  'AND' bits when merging. */
+#define ODK_HWOR	8	/* HW workarounds.  'OR' bits when merging.  */
+
+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */
+
+#define OEX_FPU_MIN	0x1f	/* FPE's which MUST be enabled.  */
+#define OEX_FPU_MAX	0x1f00	/* FPE's which MAY be enabled.  */
+#define OEX_PAGE0	0x10000	/* page zero must be mapped.  */
+#define OEX_SMM		0x20000	/* Force sequential memory mode?  */
+#define OEX_FPDBUG	0x40000	/* Force floating point debug mode?  */
+#define OEX_PRECISEFP	OEX_FPDBUG
+#define OEX_DISMISS	0x80000	/* Dismiss invalid address faults?  */
+
+#define OEX_FPU_INVAL	0x10
+#define OEX_FPU_DIV0	0x08
+#define OEX_FPU_OFLO	0x04
+#define OEX_FPU_UFLO	0x02
+#define OEX_FPU_INEX	0x01
+
+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */
+
+#define OHW_R4KEOP	0x1	/* R4000 end-of-page patch.  */
+#define OHW_R8KPFETCH	0x2	/* may need R8000 prefetch patch.  */
+#define OHW_R5KEOP	0x4	/* R5000 end-of-page patch.  */
+#define OHW_R5KCVTL	0x8	/* R5000 cvt.[ds].l bug.  clean=1.  */
+
+#define OPAD_PREFIX	0x1
+#define OPAD_POSTFIX	0x2
+#define OPAD_SYMBOL	0x4
+
+/* Entry found in `.options' section.  */
+
+typedef struct
+{
+  Elf32_Word hwp_flags1;	/* Extra flags.  */
+  Elf32_Word hwp_flags2;	/* Extra flags.  */
+} Elf_Options_Hw;
+
+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */
+
+#define OHWA0_R4KEOP_CHECKED	0x00000001
+#define OHWA1_R4KEOP_CLEAN	0x00000002
+
+/* MIPS relocs.  */
+
+#define R_MIPS_NONE		0	/* No reloc */
+#define R_MIPS_16		1	/* Direct 16 bit */
+#define R_MIPS_32		2	/* Direct 32 bit */
+#define R_MIPS_REL32		3	/* PC relative 32 bit */
+#define R_MIPS_26		4	/* Direct 26 bit shifted */
+#define R_MIPS_HI16		5	/* High 16 bit */
+#define R_MIPS_LO16		6	/* Low 16 bit */
+#define R_MIPS_GPREL16		7	/* GP relative 16 bit */
+#define R_MIPS_LITERAL		8	/* 16 bit literal entry */
+#define R_MIPS_GOT16		9	/* 16 bit GOT entry */
+#define R_MIPS_PC16		10	/* PC relative 16 bit */
+#define R_MIPS_CALL16		11	/* 16 bit GOT entry for function */
+#define R_MIPS_GPREL32		12	/* GP relative 32 bit */
+
+#define R_MIPS_SHIFT5		16
+#define R_MIPS_SHIFT6		17
+#define R_MIPS_64		18
+#define R_MIPS_GOT_DISP		19
+#define R_MIPS_GOT_PAGE		20
+#define R_MIPS_GOT_OFST		21
+#define R_MIPS_GOT_HI16		22
+#define R_MIPS_GOT_LO16		23
+#define R_MIPS_SUB		24
+#define R_MIPS_INSERT_A		25
+#define R_MIPS_INSERT_B		26
+#define R_MIPS_DELETE		27
+#define R_MIPS_HIGHER		28
+#define R_MIPS_HIGHEST		29
+#define R_MIPS_CALL_HI16	30
+#define R_MIPS_CALL_LO16	31
+#define R_MIPS_SCN_DISP		32
+#define R_MIPS_REL16		33
+#define R_MIPS_ADD_IMMEDIATE	34
+#define R_MIPS_PJUMP		35
+#define R_MIPS_RELGOT		36
+#define R_MIPS_JALR		37
+#define R_MIPS_TLS_DTPMOD32	38	/* Module number 32 bit */
+#define R_MIPS_TLS_DTPREL32	39	/* Module-relative offset 32 bit */
+#define R_MIPS_TLS_DTPMOD64	40	/* Module number 64 bit */
+#define R_MIPS_TLS_DTPREL64	41	/* Module-relative offset 64 bit */
+#define R_MIPS_TLS_GD		42	/* 16 bit GOT offset for GD */
+#define R_MIPS_TLS_LDM		43	/* 16 bit GOT offset for LDM */
+#define R_MIPS_TLS_DTPREL_HI16	44	/* Module-relative offset, high 16 bits */
+#define R_MIPS_TLS_DTPREL_LO16	45	/* Module-relative offset, low 16 bits */
+#define R_MIPS_TLS_GOTTPREL	46	/* 16 bit GOT offset for IE */
+#define R_MIPS_TLS_TPREL32	47	/* TP-relative offset, 32 bit */
+#define R_MIPS_TLS_TPREL64	48	/* TP-relative offset, 64 bit */
+#define R_MIPS_TLS_TPREL_HI16	49	/* TP-relative offset, high 16 bits */
+#define R_MIPS_TLS_TPREL_LO16	50	/* TP-relative offset, low 16 bits */
+#define R_MIPS_GLOB_DAT		51
+/* Keep this the last entry.  */
+#define R_MIPS_NUM		52
+
+/* Legal values for p_type field of Elf32_Phdr.  */
+
+#define PT_MIPS_REGINFO	0x70000000	/* Register usage information */
+#define PT_MIPS_RTPROC  0x70000001	/* Runtime procedure table. */
+#define PT_MIPS_OPTIONS 0x70000002
+
+/* Special program header types.  */
+
+#define PF_MIPS_LOCAL	0x10000000
+
+/* Legal values for d_tag field of Elf32_Dyn.  */
+
+#define DT_MIPS_RLD_VERSION  0x70000001	/* Runtime linker interface version */
+#define DT_MIPS_TIME_STAMP   0x70000002	/* Timestamp */
+#define DT_MIPS_ICHECKSUM    0x70000003	/* Checksum */
+#define DT_MIPS_IVERSION     0x70000004	/* Version string (string tbl index) */
+#define DT_MIPS_FLAGS	     0x70000005	/* Flags */
+#define DT_MIPS_BASE_ADDRESS 0x70000006	/* Base address */
+#define DT_MIPS_MSYM	     0x70000007
+#define DT_MIPS_CONFLICT     0x70000008	/* Address of CONFLICT section */
+#define DT_MIPS_LIBLIST	     0x70000009	/* Address of LIBLIST section */
+#define DT_MIPS_LOCAL_GOTNO  0x7000000a	/* Number of local GOT entries */
+#define DT_MIPS_CONFLICTNO   0x7000000b	/* Number of CONFLICT entries */
+#define DT_MIPS_LIBLISTNO    0x70000010	/* Number of LIBLIST entries */
+#define DT_MIPS_SYMTABNO     0x70000011	/* Number of DYNSYM entries */
+#define DT_MIPS_UNREFEXTNO   0x70000012	/* First external DYNSYM */
+#define DT_MIPS_GOTSYM	     0x70000013	/* First GOT entry in DYNSYM */
+#define DT_MIPS_HIPAGENO     0x70000014	/* Number of GOT page table entries */
+#define DT_MIPS_RLD_MAP	     0x70000016	/* Address of run time loader map.  */
+#define DT_MIPS_DELTA_CLASS  0x70000017	/* Delta C++ class definition.  */
+#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in
+						DT_MIPS_DELTA_CLASS.  */
+#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */
+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in
+						DT_MIPS_DELTA_INSTANCE.  */
+#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */
+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in
+					     DT_MIPS_DELTA_RELOC.  */
+#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta
+					   relocations refer to.  */
+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in
+					   DT_MIPS_DELTA_SYM.  */
+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the
+					     class declaration.  */
+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in
+						DT_MIPS_DELTA_CLASSSYM.  */
+#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */
+#define DT_MIPS_PIXIE_INIT   0x70000023
+#define DT_MIPS_SYMBOL_LIB   0x70000024
+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025
+#define DT_MIPS_LOCAL_GOTIDX 0x70000026
+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027
+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028
+#define DT_MIPS_OPTIONS	     0x70000029 /* Address of .options.  */
+#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */
+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b
+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */
+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve
+						    function stored in GOT.  */
+#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added
+					   by rld on dlopen() calls.  */
+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */
+#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */
+#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */
+#define DT_MIPS_NUM	     0x32
+
+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */
+
+#define RHF_NONE		   0		/* No flags */
+#define RHF_QUICKSTART		   (1 << 0)	/* Use quickstart */
+#define RHF_NOTPOT		   (1 << 1)	/* Hash size not power of 2 */
+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)	/* Ignore LD_LIBRARY_PATH */
+#define RHF_NO_MOVE		   (1 << 3)
+#define RHF_SGI_ONLY		   (1 << 4)
+#define RHF_GUARANTEE_INIT	   (1 << 5)
+#define RHF_DELTA_C_PLUS_PLUS	   (1 << 6)
+#define RHF_GUARANTEE_START_INIT   (1 << 7)
+#define RHF_PIXIE		   (1 << 8)
+#define RHF_DEFAULT_DELAY_LOAD	   (1 << 9)
+#define RHF_REQUICKSTART	   (1 << 10)
+#define RHF_REQUICKSTARTED	   (1 << 11)
+#define RHF_CORD		   (1 << 12)
+#define RHF_NO_UNRES_UNDEF	   (1 << 13)
+#define RHF_RLD_ORDER_SAFE	   (1 << 14)
+
+/* Entries found in sections of type SHT_MIPS_LIBLIST.  */
+
+typedef struct
+{
+  Elf32_Word l_name;		/* Name (string table index) */
+  Elf32_Word l_time_stamp;	/* Timestamp */
+  Elf32_Word l_checksum;	/* Checksum */
+  Elf32_Word l_version;		/* Interface version */
+  Elf32_Word l_flags;		/* Flags */
+} Elf32_Lib;
+
+typedef struct
+{
+  Elf64_Word l_name;		/* Name (string table index) */
+  Elf64_Word l_time_stamp;	/* Timestamp */
+  Elf64_Word l_checksum;	/* Checksum */
+  Elf64_Word l_version;		/* Interface version */
+  Elf64_Word l_flags;		/* Flags */
+} Elf64_Lib;
+
+
+/* Legal values for l_flags.  */
+
+#define LL_NONE		  0
+#define LL_EXACT_MATCH	  (1 << 0)	/* Require exact match */
+#define LL_IGNORE_INT_VER (1 << 1)	/* Ignore interface version */
+#define LL_REQUIRE_MINOR  (1 << 2)
+#define LL_EXPORTS	  (1 << 3)
+#define LL_DELAY_LOAD	  (1 << 4)
+#define LL_DELTA	  (1 << 5)
+
+/* Entries found in sections of type SHT_MIPS_CONFLICT.  */
+
+typedef Elf32_Addr Elf32_Conflict;
+
+
+/* HPPA specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_PARISC_TRAPNIL	0x00010000 /* Trap nil pointer dereference.  */
+#define EF_PARISC_EXT		0x00020000 /* Program uses arch. extensions. */
+#define EF_PARISC_LSB		0x00040000 /* Program expects little endian. */
+#define EF_PARISC_WIDE		0x00080000 /* Program expects wide mode.  */
+#define EF_PARISC_NO_KABP	0x00100000 /* No kernel assisted branch
+					      prediction.  */
+#define EF_PARISC_LAZYSWAP	0x00400000 /* Allow lazy swapping.  */
+#define EF_PARISC_ARCH		0x0000ffff /* Architecture version.  */
+
+/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */
+
+#define EFA_PARISC_1_0		    0x020b /* PA-RISC 1.0 big-endian.  */
+#define EFA_PARISC_1_1		    0x0210 /* PA-RISC 1.1 big-endian.  */
+#define EFA_PARISC_2_0		    0x0214 /* PA-RISC 2.0 big-endian.  */
+
+/* Additional section indeces.  */
+
+#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tenatively declared
+					      symbols in ANSI C.  */
+#define SHN_PARISC_HUGE_COMMON	0xff01	   /* Common blocks in huge model.  */
+
+/* Legal values for sh_type field of Elf32_Shdr.  */
+
+#define SHT_PARISC_EXT		0x70000000 /* Contains product specific ext. */
+#define SHT_PARISC_UNWIND	0x70000001 /* Unwind information.  */
+#define SHT_PARISC_DOC		0x70000002 /* Debug info for optimized code. */
+
+/* Legal values for sh_flags field of Elf32_Shdr.  */
+
+#define SHF_PARISC_SHORT	0x20000000 /* Section with short addressing. */
+#define SHF_PARISC_HUGE		0x40000000 /* Section far from gp.  */
+#define SHF_PARISC_SBP		0x80000000 /* Static branch prediction code. */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_PARISC_MILLICODE	13	/* Millicode function entry point.  */
+
+#define STT_HP_OPAQUE		(STT_LOOS + 0x1)
+#define STT_HP_STUB		(STT_LOOS + 0x2)
+
+/* HPPA relocs.  */
+
+#define R_PARISC_NONE		0	/* No reloc.  */
+#define R_PARISC_DIR32		1	/* Direct 32-bit reference.  */
+#define R_PARISC_DIR21L		2	/* Left 21 bits of eff. address.  */
+#define R_PARISC_DIR17R		3	/* Right 17 bits of eff. address.  */
+#define R_PARISC_DIR17F		4	/* 17 bits of eff. address.  */
+#define R_PARISC_DIR14R		6	/* Right 14 bits of eff. address.  */
+#define R_PARISC_PCREL32	9	/* 32-bit rel. address.  */
+#define R_PARISC_PCREL21L	10	/* Left 21 bits of rel. address.  */
+#define R_PARISC_PCREL17R	11	/* Right 17 bits of rel. address.  */
+#define R_PARISC_PCREL17F	12	/* 17 bits of rel. address.  */
+#define R_PARISC_PCREL14R	14	/* Right 14 bits of rel. address.  */
+#define R_PARISC_DPREL21L	18	/* Left 21 bits of rel. address.  */
+#define R_PARISC_DPREL14R	22	/* Right 14 bits of rel. address.  */
+#define R_PARISC_GPREL21L	26	/* GP-relative, left 21 bits.  */
+#define R_PARISC_GPREL14R	30	/* GP-relative, right 14 bits.  */
+#define R_PARISC_LTOFF21L	34	/* LT-relative, left 21 bits.  */
+#define R_PARISC_LTOFF14R	38	/* LT-relative, right 14 bits.  */
+#define R_PARISC_SECREL32	41	/* 32 bits section rel. address.  */
+#define R_PARISC_SEGBASE	48	/* No relocation, set segment base.  */
+#define R_PARISC_SEGREL32	49	/* 32 bits segment rel. address.  */
+#define R_PARISC_PLTOFF21L	50	/* PLT rel. address, left 21 bits.  */
+#define R_PARISC_PLTOFF14R	54	/* PLT rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF_FPTR32	57	/* 32 bits LT-rel. function pointer. */
+#define R_PARISC_LTOFF_FPTR21L	58	/* LT-rel. fct ptr, left 21 bits. */
+#define R_PARISC_LTOFF_FPTR14R	62	/* LT-rel. fct ptr, right 14 bits. */
+#define R_PARISC_FPTR64		64	/* 64 bits function address.  */
+#define R_PARISC_PLABEL32	65	/* 32 bits function address.  */
+#define R_PARISC_PLABEL21L	66	/* Left 21 bits of fdesc address.  */
+#define R_PARISC_PLABEL14R	70	/* Right 14 bits of fdesc address.  */
+#define R_PARISC_PCREL64	72	/* 64 bits PC-rel. address.  */
+#define R_PARISC_PCREL22F	74	/* 22 bits PC-rel. address.  */
+#define R_PARISC_PCREL14WR	75	/* PC-rel. address, right 14 bits.  */
+#define R_PARISC_PCREL14DR	76	/* PC rel. address, right 14 bits.  */
+#define R_PARISC_PCREL16F	77	/* 16 bits PC-rel. address.  */
+#define R_PARISC_PCREL16WF	78	/* 16 bits PC-rel. address.  */
+#define R_PARISC_PCREL16DF	79	/* 16 bits PC-rel. address.  */
+#define R_PARISC_DIR64		80	/* 64 bits of eff. address.  */
+#define R_PARISC_DIR14WR	83	/* 14 bits of eff. address.  */
+#define R_PARISC_DIR14DR	84	/* 14 bits of eff. address.  */
+#define R_PARISC_DIR16F		85	/* 16 bits of eff. address.  */
+#define R_PARISC_DIR16WF	86	/* 16 bits of eff. address.  */
+#define R_PARISC_DIR16DF	87	/* 16 bits of eff. address.  */
+#define R_PARISC_GPREL64	88	/* 64 bits of GP-rel. address.  */
+#define R_PARISC_GPREL14WR	91	/* GP-rel. address, right 14 bits.  */
+#define R_PARISC_GPREL14DR	92	/* GP-rel. address, right 14 bits.  */
+#define R_PARISC_GPREL16F	93	/* 16 bits GP-rel. address.  */
+#define R_PARISC_GPREL16WF	94	/* 16 bits GP-rel. address.  */
+#define R_PARISC_GPREL16DF	95	/* 16 bits GP-rel. address.  */
+#define R_PARISC_LTOFF64	96	/* 64 bits LT-rel. address.  */
+#define R_PARISC_LTOFF14WR	99	/* LT-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF14DR	100	/* LT-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF16F	101	/* 16 bits LT-rel. address.  */
+#define R_PARISC_LTOFF16WF	102	/* 16 bits LT-rel. address.  */
+#define R_PARISC_LTOFF16DF	103	/* 16 bits LT-rel. address.  */
+#define R_PARISC_SECREL64	104	/* 64 bits section rel. address.  */
+#define R_PARISC_SEGREL64	112	/* 64 bits segment rel. address.  */
+#define R_PARISC_PLTOFF14WR	115	/* PLT-rel. address, right 14 bits.  */
+#define R_PARISC_PLTOFF14DR	116	/* PLT-rel. address, right 14 bits.  */
+#define R_PARISC_PLTOFF16F	117	/* 16 bits LT-rel. address.  */
+#define R_PARISC_PLTOFF16WF	118	/* 16 bits PLT-rel. address.  */
+#define R_PARISC_PLTOFF16DF	119	/* 16 bits PLT-rel. address.  */
+#define R_PARISC_LTOFF_FPTR64	120	/* 64 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR14WR	123	/* LT-rel. fct. ptr., right 14 bits. */
+#define R_PARISC_LTOFF_FPTR14DR	124	/* LT-rel. fct. ptr., right 14 bits. */
+#define R_PARISC_LTOFF_FPTR16F	125	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR16WF	126	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR16DF	127	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LORESERVE	128
+#define R_PARISC_COPY		128	/* Copy relocation.  */
+#define R_PARISC_IPLT		129	/* Dynamic reloc, imported PLT */
+#define R_PARISC_EPLT		130	/* Dynamic reloc, exported PLT */
+#define R_PARISC_TPREL32	153	/* 32 bits TP-rel. address.  */
+#define R_PARISC_TPREL21L	154	/* TP-rel. address, left 21 bits.  */
+#define R_PARISC_TPREL14R	158	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF_TP21L	162	/* LT-TP-rel. address, left 21 bits. */
+#define R_PARISC_LTOFF_TP14R	166	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP14F	167	/* 14 bits LT-TP-rel. address.  */
+#define R_PARISC_TPREL64	216	/* 64 bits TP-rel. address.  */
+#define R_PARISC_TPREL14WR	219	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_TPREL14DR	220	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_TPREL16F	221	/* 16 bits TP-rel. address.  */
+#define R_PARISC_TPREL16WF	222	/* 16 bits TP-rel. address.  */
+#define R_PARISC_TPREL16DF	223	/* 16 bits TP-rel. address.  */
+#define R_PARISC_LTOFF_TP64	224	/* 64 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP14WR	227	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP14DR	228	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP16F	229	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP16WF	230	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP16DF	231	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_GNU_VTENTRY	232
+#define R_PARISC_GNU_VTINHERIT	233
+#define R_PARISC_TLS_GD21L	234	/* GD 21-bit left.  */
+#define R_PARISC_TLS_GD14R	235	/* GD 14-bit right.  */
+#define R_PARISC_TLS_GDCALL	236	/* GD call to __t_g_a.  */
+#define R_PARISC_TLS_LDM21L	237	/* LD module 21-bit left.  */
+#define R_PARISC_TLS_LDM14R	238	/* LD module 14-bit right.  */
+#define R_PARISC_TLS_LDMCALL	239	/* LD module call to __t_g_a.  */
+#define R_PARISC_TLS_LDO21L	240	/* LD offset 21-bit left.  */
+#define R_PARISC_TLS_LDO14R	241	/* LD offset 14-bit right.  */
+#define R_PARISC_TLS_DTPMOD32	242	/* DTP module 32-bit.  */
+#define R_PARISC_TLS_DTPMOD64	243	/* DTP module 64-bit.  */
+#define R_PARISC_TLS_DTPOFF32	244	/* DTP offset 32-bit.  */
+#define R_PARISC_TLS_DTPOFF64	245	/* DTP offset 32-bit.  */
+#define R_PARISC_TLS_LE21L	R_PARISC_TPREL21L
+#define R_PARISC_TLS_LE14R	R_PARISC_TPREL14R
+#define R_PARISC_TLS_IE21L	R_PARISC_LTOFF_TP21L
+#define R_PARISC_TLS_IE14R	R_PARISC_LTOFF_TP14R
+#define R_PARISC_TLS_TPREL32	R_PARISC_TPREL32
+#define R_PARISC_TLS_TPREL64	R_PARISC_TPREL64
+#define R_PARISC_HIRESERVE	255
+
+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */
+
+#define PT_HP_TLS		(PT_LOOS + 0x0)
+#define PT_HP_CORE_NONE		(PT_LOOS + 0x1)
+#define PT_HP_CORE_VERSION	(PT_LOOS + 0x2)
+#define PT_HP_CORE_KERNEL	(PT_LOOS + 0x3)
+#define PT_HP_CORE_COMM		(PT_LOOS + 0x4)
+#define PT_HP_CORE_PROC		(PT_LOOS + 0x5)
+#define PT_HP_CORE_LOADABLE	(PT_LOOS + 0x6)
+#define PT_HP_CORE_STACK	(PT_LOOS + 0x7)
+#define PT_HP_CORE_SHM		(PT_LOOS + 0x8)
+#define PT_HP_CORE_MMF		(PT_LOOS + 0x9)
+#define PT_HP_PARALLEL		(PT_LOOS + 0x10)
+#define PT_HP_FASTBIND		(PT_LOOS + 0x11)
+#define PT_HP_OPT_ANNOT		(PT_LOOS + 0x12)
+#define PT_HP_HSL_ANNOT		(PT_LOOS + 0x13)
+#define PT_HP_STACK		(PT_LOOS + 0x14)
+
+#define PT_PARISC_ARCHEXT	0x70000000
+#define PT_PARISC_UNWIND	0x70000001
+
+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */
+
+#define PF_PARISC_SBP		0x08000000
+
+#define PF_HP_PAGE_SIZE		0x00100000
+#define PF_HP_FAR_SHARED	0x00200000
+#define PF_HP_NEAR_SHARED	0x00400000
+#define PF_HP_CODE		0x01000000
+#define PF_HP_MODIFY		0x02000000
+#define PF_HP_LAZYSWAP		0x04000000
+#define PF_HP_SBP		0x08000000
+
+
+/* Alpha specific definitions.  */
+
+/* Legal values for e_flags field of Elf64_Ehdr.  */
+
+#define EF_ALPHA_32BIT		1	/* All addresses must be < 2GB.  */
+#define EF_ALPHA_CANRELAX	2	/* Relocations for relaxing exist.  */
+
+/* Legal values for sh_type field of Elf64_Shdr.  */
+
+/* These two are primerily concerned with ECOFF debugging info.  */
+#define SHT_ALPHA_DEBUG		0x70000001
+#define SHT_ALPHA_REGINFO	0x70000002
+
+/* Legal values for sh_flags field of Elf64_Shdr.  */
+
+#define SHF_ALPHA_GPREL		0x10000000
+
+/* Legal values for st_other field of Elf64_Sym.  */
+#define STO_ALPHA_NOPV		0x80	/* No PV required.  */
+#define STO_ALPHA_STD_GPLOAD	0x88	/* PV only used for initial ldgp.  */
+
+/* Alpha relocs.  */
+
+#define R_ALPHA_NONE		0	/* No reloc */
+#define R_ALPHA_REFLONG		1	/* Direct 32 bit */
+#define R_ALPHA_REFQUAD		2	/* Direct 64 bit */
+#define R_ALPHA_GPREL32		3	/* GP relative 32 bit */
+#define R_ALPHA_LITERAL		4	/* GP relative 16 bit w/optimization */
+#define R_ALPHA_LITUSE		5	/* Optimization hint for LITERAL */
+#define R_ALPHA_GPDISP		6	/* Add displacement to GP */
+#define R_ALPHA_BRADDR		7	/* PC+4 relative 23 bit shifted */
+#define R_ALPHA_HINT		8	/* PC+4 relative 16 bit shifted */
+#define R_ALPHA_SREL16		9	/* PC relative 16 bit */
+#define R_ALPHA_SREL32		10	/* PC relative 32 bit */
+#define R_ALPHA_SREL64		11	/* PC relative 64 bit */
+#define R_ALPHA_GPRELHIGH	17	/* GP relative 32 bit, high 16 bits */
+#define R_ALPHA_GPRELLOW	18	/* GP relative 32 bit, low 16 bits */
+#define R_ALPHA_GPREL16		19	/* GP relative 16 bit */
+#define R_ALPHA_COPY		24	/* Copy symbol at runtime */
+#define R_ALPHA_GLOB_DAT	25	/* Create GOT entry */
+#define R_ALPHA_JMP_SLOT	26	/* Create PLT entry */
+#define R_ALPHA_RELATIVE	27	/* Adjust by program base */
+#define R_ALPHA_TLS_GD_HI	28
+#define R_ALPHA_TLSGD		29
+#define R_ALPHA_TLS_LDM		30
+#define R_ALPHA_DTPMOD64	31
+#define R_ALPHA_GOTDTPREL	32
+#define R_ALPHA_DTPREL64	33
+#define R_ALPHA_DTPRELHI	34
+#define R_ALPHA_DTPRELLO	35
+#define R_ALPHA_DTPREL16	36
+#define R_ALPHA_GOTTPREL	37
+#define R_ALPHA_TPREL64		38
+#define R_ALPHA_TPRELHI		39
+#define R_ALPHA_TPRELLO		40
+#define R_ALPHA_TPREL16		41
+/* Keep this the last entry.  */
+#define R_ALPHA_NUM		46
+
+/* Magic values of the LITUSE relocation addend.  */
+#define LITUSE_ALPHA_ADDR	0
+#define LITUSE_ALPHA_BASE	1
+#define LITUSE_ALPHA_BYTOFF	2
+#define LITUSE_ALPHA_JSR	3
+#define LITUSE_ALPHA_TLS_GD	4
+#define LITUSE_ALPHA_TLS_LDM	5
+
+/* Legal values for d_tag of Elf64_Dyn.  */
+#define DT_ALPHA_PLTRO		(DT_LOPROC + 0)
+#define DT_ALPHA_NUM		1
+
+/* PowerPC specific declarations */
+
+/* Values for Elf32/64_Ehdr.e_flags.  */
+#define EF_PPC_EMB		0x80000000	/* PowerPC embedded flag */
+
+/* Cygnus local bits below */
+#define EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag*/
+#define EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib
+						   flag */
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE		0
+#define R_PPC_ADDR32		1	/* 32bit absolute address */
+#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16		3	/* 16bit absolute address */
+#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
+#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN	8
+#define R_PPC_ADDR14_BRNTAKEN	9
+#define R_PPC_REL24		10	/* PC relative 26 bit */
+#define R_PPC_REL14		11	/* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN	12
+#define R_PPC_REL14_BRNTAKEN	13
+#define R_PPC_GOT16		14
+#define R_PPC_GOT16_LO		15
+#define R_PPC_GOT16_HI		16
+#define R_PPC_GOT16_HA		17
+#define R_PPC_PLTREL24		18
+#define R_PPC_COPY		19
+#define R_PPC_GLOB_DAT		20
+#define R_PPC_JMP_SLOT		21
+#define R_PPC_RELATIVE		22
+#define R_PPC_LOCAL24PC		23
+#define R_PPC_UADDR32		24
+#define R_PPC_UADDR16		25
+#define R_PPC_REL32		26
+#define R_PPC_PLT32		27
+#define R_PPC_PLTREL32		28
+#define R_PPC_PLT16_LO		29
+#define R_PPC_PLT16_HI		30
+#define R_PPC_PLT16_HA		31
+#define R_PPC_SDAREL16		32
+#define R_PPC_SECTOFF		33
+#define R_PPC_SECTOFF_LO	34
+#define R_PPC_SECTOFF_HI	35
+#define R_PPC_SECTOFF_HA	36
+
+/* PowerPC relocations defined for the TLS access ABI.  */
+#define R_PPC_TLS		67 /* none	(sym+add)@tls */
+#define R_PPC_DTPMOD32		68 /* word32	(sym+add)@dtpmod */
+#define R_PPC_TPREL16		69 /* half16*	(sym+add)@tprel */
+#define R_PPC_TPREL16_LO	70 /* half16	(sym+add)@tprel at l */
+#define R_PPC_TPREL16_HI	71 /* half16	(sym+add)@tprel at h */
+#define R_PPC_TPREL16_HA	72 /* half16	(sym+add)@tprel at ha */
+#define R_PPC_TPREL32		73 /* word32	(sym+add)@tprel */
+#define R_PPC_DTPREL16		74 /* half16*	(sym+add)@dtprel */
+#define R_PPC_DTPREL16_LO	75 /* half16	(sym+add)@dtprel at l */
+#define R_PPC_DTPREL16_HI	76 /* half16	(sym+add)@dtprel at h */
+#define R_PPC_DTPREL16_HA	77 /* half16	(sym+add)@dtprel at ha */
+#define R_PPC_DTPREL32		78 /* word32	(sym+add)@dtprel */
+#define R_PPC_GOT_TLSGD16	79 /* half16*	(sym+add)@got at tlsgd */
+#define R_PPC_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got at tlsgd@l */
+#define R_PPC_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got at tlsgd@h */
+#define R_PPC_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got at tlsgd@ha */
+#define R_PPC_GOT_TLSLD16	83 /* half16*	(sym+add)@got at tlsld */
+#define R_PPC_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got at tlsld@l */
+#define R_PPC_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got at tlsld@h */
+#define R_PPC_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got at tlsld@ha */
+#define R_PPC_GOT_TPREL16	87 /* half16*	(sym+add)@got at tprel */
+#define R_PPC_GOT_TPREL16_LO	88 /* half16	(sym+add)@got at tprel@l */
+#define R_PPC_GOT_TPREL16_HI	89 /* half16	(sym+add)@got at tprel@h */
+#define R_PPC_GOT_TPREL16_HA	90 /* half16	(sym+add)@got at tprel@ha */
+#define R_PPC_GOT_DTPREL16	91 /* half16*	(sym+add)@got at dtprel */
+#define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got at dtprel@l */
+#define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got at dtprel@h */
+#define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got at dtprel@ha */
+
+/* Keep this the last entry.  */
+#define R_PPC_NUM		95
+
+/* The remaining relocs are from the Embedded ELF ABI, and are not
+   in the SVR4 ELF ABI.  */
+#define R_PPC_EMB_NADDR32	101
+#define R_PPC_EMB_NADDR16	102
+#define R_PPC_EMB_NADDR16_LO	103
+#define R_PPC_EMB_NADDR16_HI	104
+#define R_PPC_EMB_NADDR16_HA	105
+#define R_PPC_EMB_SDAI16	106
+#define R_PPC_EMB_SDA2I16	107
+#define R_PPC_EMB_SDA2REL	108
+#define R_PPC_EMB_SDA21		109	/* 16 bit offset in SDA */
+#define R_PPC_EMB_MRKREF	110
+#define R_PPC_EMB_RELSEC16	111
+#define R_PPC_EMB_RELST_LO	112
+#define R_PPC_EMB_RELST_HI	113
+#define R_PPC_EMB_RELST_HA	114
+#define R_PPC_EMB_BIT_FLD	115
+#define R_PPC_EMB_RELSDA	116	/* 16 bit relative offset in SDA */
+
+/* Diab tool relocations.  */
+#define R_PPC_DIAB_SDA21_LO	180	/* like EMB_SDA21, but lower 16 bit */
+#define R_PPC_DIAB_SDA21_HI	181	/* like EMB_SDA21, but high 16 bit */
+#define R_PPC_DIAB_SDA21_HA	182	/* like EMB_SDA21, adjusted high 16 */
+#define R_PPC_DIAB_RELSDA_LO	183	/* like EMB_RELSDA, but lower 16 bit */
+#define R_PPC_DIAB_RELSDA_HI	184	/* like EMB_RELSDA, but high 16 bit */
+#define R_PPC_DIAB_RELSDA_HA	185	/* like EMB_RELSDA, adjusted high 16 */
+
+/* GNU relocs used in PIC code sequences.  */
+#define R_PPC_REL16		249	/* word32   (sym-.) */
+#define R_PPC_REL16_LO		250	/* half16   (sym-.)@l */
+#define R_PPC_REL16_HI		251	/* half16   (sym-.)@h */
+#define R_PPC_REL16_HA		252	/* half16   (sym-.)@ha */
+
+/* This is a phony reloc to handle any old fashioned TOC16 references
+   that may still be in object files.  */
+#define R_PPC_TOC16		255
+
+/* PowerPC specific values for the Dyn d_tag field.  */
+#define DT_PPC_GOT		(DT_LOPROC + 0)
+#define DT_PPC_NUM		1
+
+/* PowerPC64 relocations defined by the ABIs */
+#define R_PPC64_NONE		R_PPC_NONE
+#define R_PPC64_ADDR32		R_PPC_ADDR32 /* 32bit absolute address */
+#define R_PPC64_ADDR24		R_PPC_ADDR24 /* 26bit address, word aligned */
+#define R_PPC64_ADDR16		R_PPC_ADDR16 /* 16bit absolute address */
+#define R_PPC64_ADDR16_LO	R_PPC_ADDR16_LO	/* lower 16bits of address */
+#define R_PPC64_ADDR16_HI	R_PPC_ADDR16_HI	/* high 16bits of address. */
+#define R_PPC64_ADDR16_HA	R_PPC_ADDR16_HA /* adjusted high 16bits.  */
+#define R_PPC64_ADDR14		R_PPC_ADDR14 /* 16bit address, word aligned */
+#define R_PPC64_ADDR14_BRTAKEN	R_PPC_ADDR14_BRTAKEN
+#define R_PPC64_ADDR14_BRNTAKEN	R_PPC_ADDR14_BRNTAKEN
+#define R_PPC64_REL24		R_PPC_REL24 /* PC-rel. 26 bit, word aligned */
+#define R_PPC64_REL14		R_PPC_REL14 /* PC relative 16 bit */
+#define R_PPC64_REL14_BRTAKEN	R_PPC_REL14_BRTAKEN
+#define R_PPC64_REL14_BRNTAKEN	R_PPC_REL14_BRNTAKEN
+#define R_PPC64_GOT16		R_PPC_GOT16
+#define R_PPC64_GOT16_LO	R_PPC_GOT16_LO
+#define R_PPC64_GOT16_HI	R_PPC_GOT16_HI
+#define R_PPC64_GOT16_HA	R_PPC_GOT16_HA
+
+#define R_PPC64_COPY		R_PPC_COPY
+#define R_PPC64_GLOB_DAT	R_PPC_GLOB_DAT
+#define R_PPC64_JMP_SLOT	R_PPC_JMP_SLOT
+#define R_PPC64_RELATIVE	R_PPC_RELATIVE
+
+#define R_PPC64_UADDR32		R_PPC_UADDR32
+#define R_PPC64_UADDR16		R_PPC_UADDR16
+#define R_PPC64_REL32		R_PPC_REL32
+#define R_PPC64_PLT32		R_PPC_PLT32
+#define R_PPC64_PLTREL32	R_PPC_PLTREL32
+#define R_PPC64_PLT16_LO	R_PPC_PLT16_LO
+#define R_PPC64_PLT16_HI	R_PPC_PLT16_HI
+#define R_PPC64_PLT16_HA	R_PPC_PLT16_HA
+
+#define R_PPC64_SECTOFF		R_PPC_SECTOFF
+#define R_PPC64_SECTOFF_LO	R_PPC_SECTOFF_LO
+#define R_PPC64_SECTOFF_HI	R_PPC_SECTOFF_HI
+#define R_PPC64_SECTOFF_HA	R_PPC_SECTOFF_HA
+#define R_PPC64_ADDR30		37 /* word30 (S + A - P) >> 2 */
+#define R_PPC64_ADDR64		38 /* doubleword64 S + A */
+#define R_PPC64_ADDR16_HIGHER	39 /* half16 #higher(S + A) */
+#define R_PPC64_ADDR16_HIGHERA	40 /* half16 #highera(S + A) */
+#define R_PPC64_ADDR16_HIGHEST	41 /* half16 #highest(S + A) */
+#define R_PPC64_ADDR16_HIGHESTA	42 /* half16 #highesta(S + A) */
+#define R_PPC64_UADDR64		43 /* doubleword64 S + A */
+#define R_PPC64_REL64		44 /* doubleword64 S + A - P */
+#define R_PPC64_PLT64		45 /* doubleword64 L + A */
+#define R_PPC64_PLTREL64	46 /* doubleword64 L + A - P */
+#define R_PPC64_TOC16		47 /* half16* S + A - .TOC */
+#define R_PPC64_TOC16_LO	48 /* half16 #lo(S + A - .TOC.) */
+#define R_PPC64_TOC16_HI	49 /* half16 #hi(S + A - .TOC.) */
+#define R_PPC64_TOC16_HA	50 /* half16 #ha(S + A - .TOC.) */
+#define R_PPC64_TOC		51 /* doubleword64 .TOC */
+#define R_PPC64_PLTGOT16	52 /* half16* M + A */
+#define R_PPC64_PLTGOT16_LO	53 /* half16 #lo(M + A) */
+#define R_PPC64_PLTGOT16_HI	54 /* half16 #hi(M + A) */
+#define R_PPC64_PLTGOT16_HA	55 /* half16 #ha(M + A) */
+
+#define R_PPC64_ADDR16_DS	56 /* half16ds* (S + A) >> 2 */
+#define R_PPC64_ADDR16_LO_DS	57 /* half16ds  #lo(S + A) >> 2 */
+#define R_PPC64_GOT16_DS	58 /* half16ds* (G + A) >> 2 */
+#define R_PPC64_GOT16_LO_DS	59 /* half16ds  #lo(G + A) >> 2 */
+#define R_PPC64_PLT16_LO_DS	60 /* half16ds  #lo(L + A) >> 2 */
+#define R_PPC64_SECTOFF_DS	61 /* half16ds* (R + A) >> 2 */
+#define R_PPC64_SECTOFF_LO_DS	62 /* half16ds  #lo(R + A) >> 2 */
+#define R_PPC64_TOC16_DS	63 /* half16ds* (S + A - .TOC.) >> 2 */
+#define R_PPC64_TOC16_LO_DS	64 /* half16ds  #lo(S + A - .TOC.) >> 2 */
+#define R_PPC64_PLTGOT16_DS	65 /* half16ds* (M + A) >> 2 */
+#define R_PPC64_PLTGOT16_LO_DS	66 /* half16ds  #lo(M + A) >> 2 */
+
+/* PowerPC64 relocations defined for the TLS access ABI.  */
+#define R_PPC64_TLS		67 /* none	(sym+add)@tls */
+#define R_PPC64_DTPMOD64	68 /* doubleword64 (sym+add)@dtpmod */
+#define R_PPC64_TPREL16		69 /* half16*	(sym+add)@tprel */
+#define R_PPC64_TPREL16_LO	70 /* half16	(sym+add)@tprel at l */
+#define R_PPC64_TPREL16_HI	71 /* half16	(sym+add)@tprel at h */
+#define R_PPC64_TPREL16_HA	72 /* half16	(sym+add)@tprel at ha */
+#define R_PPC64_TPREL64		73 /* doubleword64 (sym+add)@tprel */
+#define R_PPC64_DTPREL16	74 /* half16*	(sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO	75 /* half16	(sym+add)@dtprel at l */
+#define R_PPC64_DTPREL16_HI	76 /* half16	(sym+add)@dtprel at h */
+#define R_PPC64_DTPREL16_HA	77 /* half16	(sym+add)@dtprel at ha */
+#define R_PPC64_DTPREL64	78 /* doubleword64 (sym+add)@dtprel */
+#define R_PPC64_GOT_TLSGD16	79 /* half16*	(sym+add)@got at tlsgd */
+#define R_PPC64_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got at tlsgd@l */
+#define R_PPC64_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got at tlsgd@h */
+#define R_PPC64_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got at tlsgd@ha */
+#define R_PPC64_GOT_TLSLD16	83 /* half16*	(sym+add)@got at tlsld */
+#define R_PPC64_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got at tlsld@l */
+#define R_PPC64_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got at tlsld@h */
+#define R_PPC64_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got at tlsld@ha */
+#define R_PPC64_GOT_TPREL16_DS	87 /* half16ds*	(sym+add)@got at tprel */
+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got at tprel@l */
+#define R_PPC64_GOT_TPREL16_HI	89 /* half16	(sym+add)@got at tprel@h */
+#define R_PPC64_GOT_TPREL16_HA	90 /* half16	(sym+add)@got at tprel@ha */
+#define R_PPC64_GOT_DTPREL16_DS	91 /* half16ds*	(sym+add)@got at dtprel */
+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got at dtprel@l */
+#define R_PPC64_GOT_DTPREL16_HI	93 /* half16	(sym+add)@got at dtprel@h */
+#define R_PPC64_GOT_DTPREL16_HA	94 /* half16	(sym+add)@got at dtprel@ha */
+#define R_PPC64_TPREL16_DS	95 /* half16ds*	(sym+add)@tprel */
+#define R_PPC64_TPREL16_LO_DS	96 /* half16ds	(sym+add)@tprel at l */
+#define R_PPC64_TPREL16_HIGHER	97 /* half16	(sym+add)@tprel at higher */
+#define R_PPC64_TPREL16_HIGHERA	98 /* half16	(sym+add)@tprel at highera */
+#define R_PPC64_TPREL16_HIGHEST	99 /* half16	(sym+add)@tprel at highest */
+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16	(sym+add)@tprel at highesta */
+#define R_PPC64_DTPREL16_DS	101 /* half16ds* (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO_DS	102 /* half16ds	(sym+add)@dtprel at l */
+#define R_PPC64_DTPREL16_HIGHER	103 /* half16	(sym+add)@dtprel at higher */
+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel at highera */
+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel at highest */
+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel at highesta */
+
+/* Keep this the last entry.  */
+#define R_PPC64_NUM		107
+
+/* PowerPC64 specific values for the Dyn d_tag field.  */
+#define DT_PPC64_GLINK  (DT_LOPROC + 0)
+#define DT_PPC64_OPD	(DT_LOPROC + 1)
+#define DT_PPC64_OPDSZ	(DT_LOPROC + 2)
+#define DT_PPC64_NUM    3
+
+
+/* ARM specific declarations */
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARM_RELEXEC     0x01
+#define EF_ARM_HASENTRY    0x02
+#define EF_ARM_INTERWORK   0x04
+#define EF_ARM_APCS_26     0x08
+#define EF_ARM_APCS_FLOAT  0x10
+#define EF_ARM_PIC         0x20
+#define EF_ARM_ALIGN8      0x40		/* 8-bit structure alignment is in use */
+#define EF_ARM_NEW_ABI     0x80
+#define EF_ARM_OLD_ABI     0x100
+
+/* Other constants defined in the ARM ELF spec. version B-01.  */
+/* NB. These conflict with values defined above.  */
+#define EF_ARM_SYMSARESORTED	0x04
+#define EF_ARM_DYNSYMSUSESEGIDX 0x08
+#define EF_ARM_MAPSYMSFIRST	0x10
+#define EF_ARM_EABIMASK		0XFF000000
+
+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
+#define EF_ARM_EABI_UNKNOWN  0x00000000
+#define EF_ARM_EABI_VER1     0x01000000
+#define EF_ARM_EABI_VER2     0x02000000
+
+/* Additional symbol types for Thumb */
+#define STT_ARM_TFUNC      0xd
+
+/* ARM-specific values for sh_flags */
+#define SHF_ARM_ENTRYSECT  0x10000000   /* Section contains an entry point */
+#define SHF_ARM_COMDEF     0x80000000   /* Section may be multiply defined
+					   in the input to a link step */
+
+/* ARM-specific program header flags */
+#define PF_ARM_SB          0x10000000   /* Segment contains the location
+					   addressed by the static base */
+
+/* Processor specific values for the Phdr p_type field.  */
+#define PT_ARM_EXIDX	0x70000001	/* .ARM.exidx segment */
+
+/* ARM relocs.  */
+
+#define R_ARM_NONE		0	/* No reloc */
+#define R_ARM_PC24		1	/* PC relative 26 bit branch */
+#define R_ARM_ABS32		2	/* Direct 32 bit  */
+#define R_ARM_REL32		3	/* PC relative 32 bit */
+#define R_ARM_PC13		4
+#define R_ARM_ABS16		5	/* Direct 16 bit */
+#define R_ARM_ABS12		6	/* Direct 12 bit */
+#define R_ARM_THM_ABS5		7
+#define R_ARM_ABS8		8	/* Direct 8 bit */
+#define R_ARM_SBREL32		9
+#define R_ARM_THM_PC22		10
+#define R_ARM_THM_PC8		11
+#define R_ARM_AMP_VCALL9	12
+#define R_ARM_SWI24		13
+#define R_ARM_THM_SWI8		14
+#define R_ARM_XPC25		15
+#define R_ARM_THM_XPC22		16
+#define R_ARM_TLS_DTPMOD32	17	/* ID of module containing symbol */
+#define R_ARM_TLS_DTPOFF32	18	/* Offset in TLS block */
+#define R_ARM_TLS_TPOFF32	19	/* Offset in static TLS block */
+#define R_ARM_COPY		20	/* Copy symbol at runtime */
+#define R_ARM_GLOB_DAT		21	/* Create GOT entry */
+#define R_ARM_JUMP_SLOT		22	/* Create PLT entry */
+#define R_ARM_RELATIVE		23	/* Adjust by program base */
+#define R_ARM_GOTOFF		24	/* 32 bit offset to GOT */
+#define R_ARM_GOTPC		25	/* 32 bit PC relative offset to GOT */
+#define R_ARM_GOT32		26	/* 32 bit GOT entry */
+#define R_ARM_PLT32		27	/* 32 bit PLT address */
+#define R_ARM_ALU_PCREL_7_0	32
+#define R_ARM_ALU_PCREL_15_8	33
+#define R_ARM_ALU_PCREL_23_15	34
+#define R_ARM_LDR_SBREL_11_0	35
+#define R_ARM_ALU_SBREL_19_12	36
+#define R_ARM_ALU_SBREL_27_20	37
+#define R_ARM_GNU_VTENTRY	100
+#define R_ARM_GNU_VTINHERIT	101
+#define R_ARM_THM_PC11		102	/* thumb unconditional branch */
+#define R_ARM_THM_PC9		103	/* thumb conditional branch */
+#define R_ARM_TLS_GD32		104	/* PC-rel 32 bit for global dynamic
+					   thread local data */
+#define R_ARM_TLS_LDM32		105	/* PC-rel 32 bit for local dynamic
+					   thread local data */
+#define R_ARM_TLS_LDO32		106	/* 32 bit offset relative to TLS
+					   block */
+#define R_ARM_TLS_IE32		107	/* PC-rel 32 bit for GOT entry of
+					   static TLS block offset */
+#define R_ARM_TLS_LE32		108	/* 32 bit offset relative to static
+					   TLS block */
+#define R_ARM_RXPC25		249
+#define R_ARM_RSBREL32		250
+#define R_ARM_THM_RPC22		251
+#define R_ARM_RREL32		252
+#define R_ARM_RABS22		253
+#define R_ARM_RPC24		254
+#define R_ARM_RBASE		255
+/* Keep this the last entry.  */
+#define R_ARM_NUM		256
+
+/* IA-64 specific declarations.  */
+
+/* Processor specific flags for the Ehdr e_flags field.  */
+#define EF_IA_64_MASKOS		0x0000000f	/* os-specific flags */
+#define EF_IA_64_ABI64		0x00000010	/* 64-bit ABI */
+#define EF_IA_64_ARCH		0xff000000	/* arch. version mask */
+
+/* Processor specific values for the Phdr p_type field.  */
+#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* arch extension bits */
+#define PT_IA_64_UNWIND		(PT_LOPROC + 1)	/* ia64 unwind bits */
+#define PT_IA_64_HP_OPT_ANOT	(PT_LOOS + 0x12)
+#define PT_IA_64_HP_HSL_ANOT	(PT_LOOS + 0x13)
+#define PT_IA_64_HP_STACK	(PT_LOOS + 0x14)
+
+/* Processor specific flags for the Phdr p_flags field.  */
+#define PF_IA_64_NORECOV	0x80000000	/* spec insns w/o recovery */
+
+/* Processor specific values for the Shdr sh_type field.  */
+#define SHT_IA_64_EXT		(SHT_LOPROC + 0) /* extension bits */
+#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1) /* unwind bits */
+
+/* Processor specific flags for the Shdr sh_flags field.  */
+#define SHF_IA_64_SHORT		0x10000000	/* section near gp */
+#define SHF_IA_64_NORECOV	0x20000000	/* spec insns w/o recovery */
+
+/* Processor specific values for the Dyn d_tag field.  */
+#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
+#define DT_IA_64_NUM		1
+
+/* IA-64 relocations.  */
+#define R_IA64_NONE		0x00	/* none */
+#define R_IA64_IMM14		0x21	/* symbol + addend, add imm14 */
+#define R_IA64_IMM22		0x22	/* symbol + addend, add imm22 */
+#define R_IA64_IMM64		0x23	/* symbol + addend, mov imm64 */
+#define R_IA64_DIR32MSB		0x24	/* symbol + addend, data4 MSB */
+#define R_IA64_DIR32LSB		0x25	/* symbol + addend, data4 LSB */
+#define R_IA64_DIR64MSB		0x26	/* symbol + addend, data8 MSB */
+#define R_IA64_DIR64LSB		0x27	/* symbol + addend, data8 LSB */
+#define R_IA64_GPREL22		0x2a	/* @gprel(sym + add), add imm22 */
+#define R_IA64_GPREL64I		0x2b	/* @gprel(sym + add), mov imm64 */
+#define R_IA64_GPREL32MSB	0x2c	/* @gprel(sym + add), data4 MSB */
+#define R_IA64_GPREL32LSB	0x2d	/* @gprel(sym + add), data4 LSB */
+#define R_IA64_GPREL64MSB	0x2e	/* @gprel(sym + add), data8 MSB */
+#define R_IA64_GPREL64LSB	0x2f	/* @gprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF22		0x32	/* @ltoff(sym + add), add imm22 */
+#define R_IA64_LTOFF64I		0x33	/* @ltoff(sym + add), mov imm64 */
+#define R_IA64_PLTOFF22		0x3a	/* @pltoff(sym + add), add imm22 */
+#define R_IA64_PLTOFF64I	0x3b	/* @pltoff(sym + add), mov imm64 */
+#define R_IA64_PLTOFF64MSB	0x3e	/* @pltoff(sym + add), data8 MSB */
+#define R_IA64_PLTOFF64LSB	0x3f	/* @pltoff(sym + add), data8 LSB */
+#define R_IA64_FPTR64I		0x43	/* @fptr(sym + add), mov imm64 */
+#define R_IA64_FPTR32MSB	0x44	/* @fptr(sym + add), data4 MSB */
+#define R_IA64_FPTR32LSB	0x45	/* @fptr(sym + add), data4 LSB */
+#define R_IA64_FPTR64MSB	0x46	/* @fptr(sym + add), data8 MSB */
+#define R_IA64_FPTR64LSB	0x47	/* @fptr(sym + add), data8 LSB */
+#define R_IA64_PCREL60B		0x48	/* @pcrel(sym + add), brl */
+#define R_IA64_PCREL21B		0x49	/* @pcrel(sym + add), ptb, call */
+#define R_IA64_PCREL21M		0x4a	/* @pcrel(sym + add), chk.s */
+#define R_IA64_PCREL21F		0x4b	/* @pcrel(sym + add), fchkf */
+#define R_IA64_PCREL32MSB	0x4c	/* @pcrel(sym + add), data4 MSB */
+#define R_IA64_PCREL32LSB	0x4d	/* @pcrel(sym + add), data4 LSB */
+#define R_IA64_PCREL64MSB	0x4e	/* @pcrel(sym + add), data8 MSB */
+#define R_IA64_PCREL64LSB	0x4f	/* @pcrel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_FPTR22	0x52	/* @ltoff(@fptr(s+a)), imm22 */
+#define R_IA64_LTOFF_FPTR64I	0x53	/* @ltoff(@fptr(s+a)), imm64 */
+#define R_IA64_LTOFF_FPTR32MSB	0x54	/* @ltoff(@fptr(s+a)), data4 MSB */
+#define R_IA64_LTOFF_FPTR32LSB	0x55	/* @ltoff(@fptr(s+a)), data4 LSB */
+#define R_IA64_LTOFF_FPTR64MSB	0x56	/* @ltoff(@fptr(s+a)), data8 MSB */
+#define R_IA64_LTOFF_FPTR64LSB	0x57	/* @ltoff(@fptr(s+a)), data8 LSB */
+#define R_IA64_SEGREL32MSB	0x5c	/* @segrel(sym + add), data4 MSB */
+#define R_IA64_SEGREL32LSB	0x5d	/* @segrel(sym + add), data4 LSB */
+#define R_IA64_SEGREL64MSB	0x5e	/* @segrel(sym + add), data8 MSB */
+#define R_IA64_SEGREL64LSB	0x5f	/* @segrel(sym + add), data8 LSB */
+#define R_IA64_SECREL32MSB	0x64	/* @secrel(sym + add), data4 MSB */
+#define R_IA64_SECREL32LSB	0x65	/* @secrel(sym + add), data4 LSB */
+#define R_IA64_SECREL64MSB	0x66	/* @secrel(sym + add), data8 MSB */
+#define R_IA64_SECREL64LSB	0x67	/* @secrel(sym + add), data8 LSB */
+#define R_IA64_REL32MSB		0x6c	/* data 4 + REL */
+#define R_IA64_REL32LSB		0x6d	/* data 4 + REL */
+#define R_IA64_REL64MSB		0x6e	/* data 8 + REL */
+#define R_IA64_REL64LSB		0x6f	/* data 8 + REL */
+#define R_IA64_LTV32MSB		0x74	/* symbol + addend, data4 MSB */
+#define R_IA64_LTV32LSB		0x75	/* symbol + addend, data4 LSB */
+#define R_IA64_LTV64MSB		0x76	/* symbol + addend, data8 MSB */
+#define R_IA64_LTV64LSB		0x77	/* symbol + addend, data8 LSB */
+#define R_IA64_PCREL21BI	0x79	/* @pcrel(sym + add), 21bit inst */
+#define R_IA64_PCREL22		0x7a	/* @pcrel(sym + add), 22bit inst */
+#define R_IA64_PCREL64I		0x7b	/* @pcrel(sym + add), 64bit inst */
+#define R_IA64_IPLTMSB		0x80	/* dynamic reloc, imported PLT, MSB */
+#define R_IA64_IPLTLSB		0x81	/* dynamic reloc, imported PLT, LSB */
+#define R_IA64_COPY		0x84	/* copy relocation */
+#define R_IA64_SUB		0x85	/* Addend and symbol difference */
+#define R_IA64_LTOFF22X		0x86	/* LTOFF22, relaxable.  */
+#define R_IA64_LDXMOV		0x87	/* Use of LTOFF22X.  */
+#define R_IA64_TPREL14		0x91	/* @tprel(sym + add), imm14 */
+#define R_IA64_TPREL22		0x92	/* @tprel(sym + add), imm22 */
+#define R_IA64_TPREL64I		0x93	/* @tprel(sym + add), imm64 */
+#define R_IA64_TPREL64MSB	0x96	/* @tprel(sym + add), data8 MSB */
+#define R_IA64_TPREL64LSB	0x97	/* @tprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_TPREL22	0x9a	/* @ltoff(@tprel(s+a)), imm2 */
+#define R_IA64_DTPMOD64MSB	0xa6	/* @dtpmod(sym + add), data8 MSB */
+#define R_IA64_DTPMOD64LSB	0xa7	/* @dtpmod(sym + add), data8 LSB */
+#define R_IA64_LTOFF_DTPMOD22	0xaa	/* @ltoff(@dtpmod(sym + add)), imm22 */
+#define R_IA64_DTPREL14		0xb1	/* @dtprel(sym + add), imm14 */
+#define R_IA64_DTPREL22		0xb2	/* @dtprel(sym + add), imm22 */
+#define R_IA64_DTPREL64I	0xb3	/* @dtprel(sym + add), imm64 */
+#define R_IA64_DTPREL32MSB	0xb4	/* @dtprel(sym + add), data4 MSB */
+#define R_IA64_DTPREL32LSB	0xb5	/* @dtprel(sym + add), data4 LSB */
+#define R_IA64_DTPREL64MSB	0xb6	/* @dtprel(sym + add), data8 MSB */
+#define R_IA64_DTPREL64LSB	0xb7	/* @dtprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_DTPREL22	0xba	/* @ltoff(@dtprel(s+a)), imm22 */
+
+/* SH specific declarations */
+
+/* SH relocs.  */
+#define	R_SH_NONE		0
+#define	R_SH_DIR32		1
+#define	R_SH_REL32		2
+#define	R_SH_DIR8WPN		3
+#define	R_SH_IND12W		4
+#define	R_SH_DIR8WPL		5
+#define	R_SH_DIR8WPZ		6
+#define	R_SH_DIR8BP		7
+#define	R_SH_DIR8W		8
+#define	R_SH_DIR8L		9
+#define	R_SH_SWITCH16		25
+#define	R_SH_SWITCH32		26
+#define	R_SH_USES		27
+#define	R_SH_COUNT		28
+#define	R_SH_ALIGN		29
+#define	R_SH_CODE		30
+#define	R_SH_DATA		31
+#define	R_SH_LABEL		32
+#define	R_SH_SWITCH8		33
+#define	R_SH_GNU_VTINHERIT	34
+#define	R_SH_GNU_VTENTRY	35
+#define	R_SH_TLS_GD_32		144
+#define	R_SH_TLS_LD_32		145
+#define	R_SH_TLS_LDO_32		146
+#define	R_SH_TLS_IE_32		147
+#define	R_SH_TLS_LE_32		148
+#define	R_SH_TLS_DTPMOD32	149
+#define	R_SH_TLS_DTPOFF32	150
+#define	R_SH_TLS_TPOFF32	151
+#define	R_SH_GOT32		160
+#define	R_SH_PLT32		161
+#define	R_SH_COPY		162
+#define	R_SH_GLOB_DAT		163
+#define	R_SH_JMP_SLOT		164
+#define	R_SH_RELATIVE		165
+#define	R_SH_GOTOFF		166
+#define	R_SH_GOTPC		167
+/* Keep this the last entry.  */
+#define	R_SH_NUM		256
+
+/* Additional s390 relocs */
+
+#define R_390_NONE		0	/* No reloc.  */
+#define R_390_8			1	/* Direct 8 bit.  */
+#define R_390_12		2	/* Direct 12 bit.  */
+#define R_390_16		3	/* Direct 16 bit.  */
+#define R_390_32		4	/* Direct 32 bit.  */
+#define R_390_PC32		5	/* PC relative 32 bit.	*/
+#define R_390_GOT12		6	/* 12 bit GOT offset.  */
+#define R_390_GOT32		7	/* 32 bit GOT offset.  */
+#define R_390_PLT32		8	/* 32 bit PC relative PLT address.  */
+#define R_390_COPY		9	/* Copy symbol at runtime.  */
+#define R_390_GLOB_DAT		10	/* Create GOT entry.  */
+#define R_390_JMP_SLOT		11	/* Create PLT entry.  */
+#define R_390_RELATIVE		12	/* Adjust by program base.  */
+#define R_390_GOTOFF32		13	/* 32 bit offset to GOT.	 */
+#define R_390_GOTPC		14	/* 32 bit PC relative offset to GOT.  */
+#define R_390_GOT16		15	/* 16 bit GOT offset.  */
+#define R_390_PC16		16	/* PC relative 16 bit.	*/
+#define R_390_PC16DBL		17	/* PC relative 16 bit shifted by 1.  */
+#define R_390_PLT16DBL		18	/* 16 bit PC rel. PLT shifted by 1.  */
+#define R_390_PC32DBL		19	/* PC relative 32 bit shifted by 1.  */
+#define R_390_PLT32DBL		20	/* 32 bit PC rel. PLT shifted by 1.  */
+#define R_390_GOTPCDBL		21	/* 32 bit PC rel. GOT shifted by 1.  */
+#define R_390_64		22	/* Direct 64 bit.  */
+#define R_390_PC64		23	/* PC relative 64 bit.	*/
+#define R_390_GOT64		24	/* 64 bit GOT offset.  */
+#define R_390_PLT64		25	/* 64 bit PC relative PLT address.  */
+#define R_390_GOTENT		26	/* 32 bit PC rel. to GOT entry >> 1. */
+#define R_390_GOTOFF16		27	/* 16 bit offset to GOT. */
+#define R_390_GOTOFF64		28	/* 64 bit offset to GOT. */
+#define R_390_GOTPLT12		29	/* 12 bit offset to jump slot.	*/
+#define R_390_GOTPLT16		30	/* 16 bit offset to jump slot.	*/
+#define R_390_GOTPLT32		31	/* 32 bit offset to jump slot.	*/
+#define R_390_GOTPLT64		32	/* 64 bit offset to jump slot.	*/
+#define R_390_GOTPLTENT		33	/* 32 bit rel. offset to jump slot.  */
+#define R_390_PLTOFF16		34	/* 16 bit offset from GOT to PLT. */
+#define R_390_PLTOFF32		35	/* 32 bit offset from GOT to PLT. */
+#define R_390_PLTOFF64		36	/* 16 bit offset from GOT to PLT. */
+#define R_390_TLS_LOAD		37	/* Tag for load insn in TLS code.  */
+#define R_390_TLS_GDCALL	38	/* Tag for function call in general
+					   dynamic TLS code. */
+#define R_390_TLS_LDCALL	39	/* Tag for function call in local
+					   dynamic TLS code. */
+#define R_390_TLS_GD32		40	/* Direct 32 bit for general dynamic
+					   thread local data.  */
+#define R_390_TLS_GD64		41	/* Direct 64 bit for general dynamic
+					  thread local data.  */
+#define R_390_TLS_GOTIE12	42	/* 12 bit GOT offset for static TLS
+					   block offset.  */
+#define R_390_TLS_GOTIE32	43	/* 32 bit GOT offset for static TLS
+					   block offset.  */
+#define R_390_TLS_GOTIE64	44	/* 64 bit GOT offset for static TLS
+					   block offset. */
+#define R_390_TLS_LDM32		45	/* Direct 32 bit for local dynamic
+					   thread local data in LE code.  */
+#define R_390_TLS_LDM64		46	/* Direct 64 bit for local dynamic
+					   thread local data in LE code.  */
+#define R_390_TLS_IE32		47	/* 32 bit address of GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_IE64		48	/* 64 bit address of GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_IEENT		49	/* 32 bit rel. offset to GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_LE32		50	/* 32 bit negated offset relative to
+					   static TLS block.  */
+#define R_390_TLS_LE64		51	/* 64 bit negated offset relative to
+					   static TLS block.  */
+#define R_390_TLS_LDO32		52	/* 32 bit offset relative to TLS
+					   block.  */
+#define R_390_TLS_LDO64		53	/* 64 bit offset relative to TLS
+					   block.  */
+#define R_390_TLS_DTPMOD	54	/* ID of module containing symbol.  */
+#define R_390_TLS_DTPOFF	55	/* Offset in TLS block.	 */
+#define R_390_TLS_TPOFF		56	/* Negated offset in static TLS
+					   block.  */
+#define R_390_20		57	/* Direct 20 bit.  */
+#define R_390_GOT20		58	/* 20 bit GOT offset.  */
+#define R_390_GOTPLT20		59	/* 20 bit offset to jump slot.  */
+#define R_390_TLS_GOTIE20	60	/* 20 bit GOT offset for static TLS
+					   block offset.  */
+/* Keep this the last entry.  */
+#define R_390_NUM		61
+
+
+/* CRIS relocations.  */
+#define R_CRIS_NONE		0
+#define R_CRIS_8		1
+#define R_CRIS_16		2
+#define R_CRIS_32		3
+#define R_CRIS_8_PCREL		4
+#define R_CRIS_16_PCREL		5
+#define R_CRIS_32_PCREL		6
+#define R_CRIS_GNU_VTINHERIT	7
+#define R_CRIS_GNU_VTENTRY	8
+#define R_CRIS_COPY		9
+#define R_CRIS_GLOB_DAT		10
+#define R_CRIS_JUMP_SLOT	11
+#define R_CRIS_RELATIVE		12
+#define R_CRIS_16_GOT		13
+#define R_CRIS_32_GOT		14
+#define R_CRIS_16_GOTPLT	15
+#define R_CRIS_32_GOTPLT	16
+#define R_CRIS_32_GOTREL	17
+#define R_CRIS_32_PLT_GOTREL	18
+#define R_CRIS_32_PLT_PCREL	19
+
+#define R_CRIS_NUM		20
+
+
+/* AMD x86-64 relocations.  */
+#define R_X86_64_NONE		0	/* No reloc */
+#define R_X86_64_64		1	/* Direct 64 bit  */
+#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
+#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
+#define R_X86_64_PLT32		4	/* 32 bit PLT address */
+#define R_X86_64_COPY		5	/* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
+#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
+#define R_X86_64_RELATIVE	8	/* Adjust by program base */
+#define R_X86_64_GOTPCREL	9	/* 32 bit signed PC relative
+					   offset to GOT */
+#define R_X86_64_32		10	/* Direct 32 bit zero extended */
+#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
+#define R_X86_64_16		12	/* Direct 16 bit zero extended */
+#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
+#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
+#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
+#define R_X86_64_DTPMOD64	16	/* ID of module containing symbol */
+#define R_X86_64_DTPOFF64	17	/* Offset in module's TLS block */
+#define R_X86_64_TPOFF64	18	/* Offset in initial TLS block */
+#define R_X86_64_TLSGD		19	/* 32 bit signed PC relative offset
+					   to two GOT entries for GD symbol */
+#define R_X86_64_TLSLD		20	/* 32 bit signed PC relative offset
+					   to two GOT entries for LD symbol */
+#define R_X86_64_DTPOFF32	21	/* Offset in TLS block */
+#define R_X86_64_GOTTPOFF	22	/* 32 bit signed PC relative offset
+					   to GOT entry for IE symbol */
+#define R_X86_64_TPOFF32	23	/* Offset in initial TLS block */
+
+#define R_X86_64_NUM		24
+
+
+/* AM33 relocations.  */
+#define R_MN10300_NONE		0	/* No reloc.  */
+#define R_MN10300_32		1	/* Direct 32 bit.  */
+#define R_MN10300_16		2	/* Direct 16 bit.  */
+#define R_MN10300_8		3	/* Direct 8 bit.  */
+#define R_MN10300_PCREL32	4	/* PC-relative 32-bit.  */
+#define R_MN10300_PCREL16	5	/* PC-relative 16-bit signed.  */
+#define R_MN10300_PCREL8	6	/* PC-relative 8-bit signed.  */
+#define R_MN10300_GNU_VTINHERIT	7	/* Ancient C++ vtable garbage... */
+#define R_MN10300_GNU_VTENTRY	8	/* ... collection annotation.  */
+#define R_MN10300_24		9	/* Direct 24 bit.  */
+#define R_MN10300_GOTPC32	10	/* 32-bit PCrel offset to GOT.  */
+#define R_MN10300_GOTPC16	11	/* 16-bit PCrel offset to GOT.  */
+#define R_MN10300_GOTOFF32	12	/* 32-bit offset from GOT.  */
+#define R_MN10300_GOTOFF24	13	/* 24-bit offset from GOT.  */
+#define R_MN10300_GOTOFF16	14	/* 16-bit offset from GOT.  */
+#define R_MN10300_PLT32		15	/* 32-bit PCrel to PLT entry.  */
+#define R_MN10300_PLT16		16	/* 16-bit PCrel to PLT entry.  */
+#define R_MN10300_GOT32		17	/* 32-bit offset to GOT entry.  */
+#define R_MN10300_GOT24		18	/* 24-bit offset to GOT entry.  */
+#define R_MN10300_GOT16		19	/* 16-bit offset to GOT entry.  */
+#define R_MN10300_COPY		20	/* Copy symbol at runtime.  */
+#define R_MN10300_GLOB_DAT	21	/* Create GOT entry.  */
+#define R_MN10300_JMP_SLOT	22	/* Create PLT entry.  */
+#define R_MN10300_RELATIVE	23	/* Adjust by program base.  */
+
+#define R_MN10300_NUM		24
+
+
+/* M32R relocs.  */
+#define R_M32R_NONE		0	/* No reloc. */
+#define R_M32R_16		1	/* Direct 16 bit. */
+#define R_M32R_32		2	/* Direct 32 bit. */
+#define R_M32R_24		3	/* Direct 24 bit. */
+#define R_M32R_10_PCREL		4	/* PC relative 10 bit shifted. */
+#define R_M32R_18_PCREL		5	/* PC relative 18 bit shifted. */
+#define R_M32R_26_PCREL		6	/* PC relative 26 bit shifted. */
+#define R_M32R_HI16_ULO		7	/* High 16 bit with unsigned low. */
+#define R_M32R_HI16_SLO		8	/* High 16 bit with signed low. */
+#define R_M32R_LO16		9	/* Low 16 bit. */
+#define R_M32R_SDA16		10	/* 16 bit offset in SDA. */
+#define R_M32R_GNU_VTINHERIT	11
+#define R_M32R_GNU_VTENTRY	12
+/* M32R relocs use SHT_RELA.  */
+#define R_M32R_16_RELA		33	/* Direct 16 bit. */
+#define R_M32R_32_RELA		34	/* Direct 32 bit. */
+#define R_M32R_24_RELA		35	/* Direct 24 bit. */
+#define R_M32R_10_PCREL_RELA	36	/* PC relative 10 bit shifted. */
+#define R_M32R_18_PCREL_RELA	37	/* PC relative 18 bit shifted. */
+#define R_M32R_26_PCREL_RELA	38	/* PC relative 26 bit shifted. */
+#define R_M32R_HI16_ULO_RELA	39	/* High 16 bit with unsigned low */
+#define R_M32R_HI16_SLO_RELA	40	/* High 16 bit with signed low */
+#define R_M32R_LO16_RELA	41	/* Low 16 bit */
+#define R_M32R_SDA16_RELA	42	/* 16 bit offset in SDA */
+#define R_M32R_RELA_GNU_VTINHERIT	43
+#define R_M32R_RELA_GNU_VTENTRY	44
+#define R_M32R_REL32		45	/* PC relative 32 bit.  */
+
+#define R_M32R_GOT24		48	/* 24 bit GOT entry */
+#define R_M32R_26_PLTREL	49	/* 26 bit PC relative to PLT shifted */
+#define R_M32R_COPY		50	/* Copy symbol at runtime */
+#define R_M32R_GLOB_DAT		51	/* Create GOT entry */
+#define R_M32R_JMP_SLOT		52	/* Create PLT entry */
+#define R_M32R_RELATIVE		53	/* Adjust by program base */
+#define R_M32R_GOTOFF		54	/* 24 bit offset to GOT */
+#define R_M32R_GOTPC24		55	/* 24 bit PC relative offset to GOT */
+#define R_M32R_GOT16_HI_ULO	56	/* High 16 bit GOT entry with unsigned
+					   low */
+#define R_M32R_GOT16_HI_SLO	57	/* High 16 bit GOT entry with signed
+					   low */
+#define R_M32R_GOT16_LO		58	/* Low 16 bit GOT entry */
+#define R_M32R_GOTPC_HI_ULO	59	/* High 16 bit PC relative offset to
+					   GOT with unsigned low */
+#define R_M32R_GOTPC_HI_SLO	60	/* High 16 bit PC relative offset to
+					   GOT with signed low */
+#define R_M32R_GOTPC_LO		61	/* Low 16 bit PC relative offset to
+					   GOT */
+#define R_M32R_GOTOFF_HI_ULO	62	/* High 16 bit offset to GOT
+					   with unsigned low */
+#define R_M32R_GOTOFF_HI_SLO	63	/* High 16 bit offset to GOT
+					   with signed low */
+#define R_M32R_GOTOFF_LO	64	/* Low 16 bit offset to GOT */
+#define R_M32R_NUM		256	/* Keep this the last entry. */
+
+
+#endif	/* elf.h */

Modified: coreboot-v3/util/lar/stream.c
===================================================================
--- coreboot-v3/util/lar/stream.c	2008-04-04 03:46:39 UTC (rev 651)
+++ coreboot-v3/util/lar/stream.c	2008-04-04 13:10:05 UTC (rev 652)
@@ -32,8 +32,8 @@
 #include <sys/mman.h>
 #include <netinet/in.h>
 #include <libgen.h>
-#include <elf.h>
 
+#include "elf.h"
 #include "lar.h"
 #include "lib.h"
 




From stepan at coresystems.de  Fri Apr  4 15:10:24 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 07:10:24 -0600
Subject: [coreboot] [PATCH] fix lar compilation for non-Linux platforms
In-Reply-To: <47F5C65C.5020204@gmx.net>
References: <47F597E6.5030107@coresystems.de> <47F5C65C.5020204@gmx.net>
Message-ID: <47F628C0.2050907@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 04.04.2008 04:52, Stefan Reinauer wrote:
>   
>> This patch allows compilation on non-glibc platforms again.
>>
>>
>> This adds the glibc elf.h to allow compilation on non-glibc platforms.
>>
>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>   
>>     
>
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

thanks, r652

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Fri Apr  4 15:16:33 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 15:16:33 +0200
Subject: [coreboot] r3213 - trunk/payloads/libpayload/include
Message-ID: <mailman.1367.1355071295.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-04 15:16:33 +0200 (Fri, 04 Apr 2008)
New Revision: 3213

Modified:
   trunk/payloads/libpayload/include/libpayload.h
Log:
Add BIN2HEX and HEX2BIN macros (trivial).

They're generally useful for lots of stuff, but especially for converting
to/from the compact 160 bit (20 byte) representation of SHA-1 hashes to
the "hex" representation (same as 'sha1sum' output), which is 40 bytes long.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/payloads/libpayload/include/libpayload.h
===================================================================
--- trunk/payloads/libpayload/include/libpayload.h	2008-04-03 23:01:23 UTC (rev 3212)
+++ trunk/payloads/libpayload/include/libpayload.h	2008-04-04 13:16:33 UTC (rev 3213)
@@ -41,6 +41,10 @@
 #define MAX(a,b) ((a) > (b) ? (a) : (b))
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
+#define BIN2HEX(b) ("0123456789abcdef"[b & 15])
+#define HEX2BIN(h) (('0' <= h && h <= '9') ? (h - '0') : \
+                    ('a' <= h && h <= 'f') ? (h - 'a' + 10) : 0)
+
 #define LITTLE_ENDIAN	1234
 #define BIG_ENDIAN	4321
 #ifdef CONFIG_TARGET_I386




From malateshkamat at gmail.com  Fri Apr  4 15:25:11 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Fri, 4 Apr 2008 18:55:11 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <dd3c80060804040559h4b7510b1q7747f44e897fa4da@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
	<dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
	<fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>
	<dd3c80060804040559h4b7510b1q7747f44e897fa4da@mail.gmail.com>
Message-ID: <fa70bcc0804040625wb01013vd941cd25fb274bba@mail.gmail.com>

Ya .. after checking that file i got result like this ...it shows that there
is a content in that file

[root at localhost ~]# hexdump sst_after_erase.bin
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0080000

  I think erasing is not happened properly..

Thanks..
malatesh

On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
>
> Ok, so if you open up the sst_after_erase.bin with a hex editor, is there
> anything in it? Does that match the data from the diff, or is it a binary
> ORing of the data from the diff? Do you have any other flash chips you can
> try on the board?
>
> On Fri, Apr 4, 2008 at 8:41 AM, malatesh kamatad <malateshkamat at gmail.com>
> wrote:
>
> >  Ya i got result like this after comparing
> >
> >   [root at localhost ~]# diff -us original.bin sst_after_write.bin
> > Binary files original.bin and sst_after_write.bin differ
> >
> >    but its showing that there is a difference in between to files ....
> >
> >   i think write is not happening proper ....
> >
> > Thanks .
> > malatesh
> >
> >
> > On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
> > >
> > > what's the output of diff -us original.bin sst_after_write.bin? Can
> > > you download the bios from the manufacturer and see if flashing that works?
> > >
> > > -Corey
> > >
> > > On Fri, Apr 4, 2008 at 7:03 AM, malatesh kamatad <
> > > malateshkamat at gmail.com> wrote:
> > >
> > > >    I worked with the step by step this is the output......
> > > >
> > > > [root at localhost ~]# flashrom -r original.bin
> > > > Calibrating delay loop... OK.
> > > > No coreboot table found.
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > Pm49FL004 found at physical address 0xfff80000.
> > > > Flash part is Pm49FL004 (512 KB).
> > > > Reading Flash...done
> > > >
> > > > [root at localhost ~]# flashrom -E
> > > > Calibrating delay loop... OK.
> > > > No coreboot table found.
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > Flash part is SST49LF004A/B (512 KB).
> > > > Erasing flash chip
> > > >
> > > > [root at localhost ~]# flashrom -r sst_after_erase.bin
> > > > Calibrating delay loop... OK.
> > > > No coreboot table found.
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > Flash part is SST49LF004A/B (512 KB).
> > > > Reading Flash...done
> > > >
> > > > [root at localhost ~]# flashrom -w original.bin
> > > > Calibrating delay loop... OK.
> > > > No coreboot table found.
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > Flash part is SST49LF004A/B (512 KB).
> > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > Programming page: 0007 at address: 0x00070000
> > > >
> > > > [root at localhost ~]# flashrom -r sst_after_write.bin
> > > > Calibrating delay loop... OK.
> > > > No coreboot table found.
> > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > Flash part is SST49LF004A/B (512 KB).
> > > > Reading Flash...done
> > > >
> > > > Thanks,
> > > > Malatesh.
> > > >
> > > > On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
> > > > >
> > > > > Hi..
> > > > >
> > > > >          We are having two BIOS i.e, PM49FL004( motherboard's
> > > > > BIOS) and empty flashrom
> > > > >
> > > > >         SST49LF004B ..
> > > > >
> > > > >        We are trying to flash the content of PM49FL004 to
> > > > > SST49LF004B flashrom
> > > > >
> > > > >         according to your suggestion we have done ..we are getting
> > > > > output  as bellow..
> > > > >
> > > > >
> > > > >
> > > > > [root at localhost ~]# flashrom -E
> > > > >
> > > > > Calibrating delay loop... OK.
> > > > >
> > > > > No coreboot table found.
> > > > >
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > >
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > >
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > >
> > > > > Erasing flash chip
> > > > >
> > > > > Erasing page: 0007 at address: 0x00070000
> > > > >
> > > > > [root at localhost ~]# flashrom -r malateh.bin
> > > > >
> > > > > Calibrating delay loop... OK.
> > > > >
> > > > > No coreboot table found.
> > > > >
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > >
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > >
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > >
> > > > > Reading Flash...done
> > > > >
> > > > > [root at localhost ~]# flashrom -w malateh.bin
> > > > >
> > > > > Calibrating delay loop... OK.
> > > > >
> > > > > No coreboot table found.
> > > > >
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > >
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > >
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > >
> > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > >
> > > > > Programming page: 0007 at address: 0x00070000
> > > > >
> > > > > [root at localhost ~]# flashrom -v malateh.bin
> > > > >
> > > > > Calibrating delay loop... OK.
> > > > >
> > > > > No coreboot table found.
> > > > >
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > >
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > >
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > >
> > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > >
> > > > > Verifying flash... VERIFIED.
> > > > >
> > > > >
> > > > >  After that we tried to boot the system by SST49lf004B but system
> > > > > is not rebooting....
> > > > >
> > > > > So we want to flash the content of the Pm49fl004 to SST49lf004 so
> > > > > that our system can boot
> > > > >
> > > > > using SST49lf004....
> > > > >
> > > > > thanks,
> > > > > Malatesh..
> > > > >
> > > > >
> > > > > On 04/04/2008, bari <bari at onelabs.com> wrote:
> > > > > >
> > > > > > Try Peters suggestion of reading the flash after an erase and
> > > > > > see what is there.
> > > > > >
> > > > > > If it is erased, read back after you have tried to write and
> > > > > > compare.
> > > > > >
> > > > > > See what is or is not happening.
> > > > > >
> > > > > > -Bari
> > > > > >
> > > > > > malatesh kamatad wrote:
> > > > > >
> > > > > > > Hi...
> > > > > > >       I am working on ASRock motherboard .....in FWH mode...
> > > > > > >
> > > > > > > with regards.
> > > > > > > Malatesh
> > > > > > >
> > > > > > > On 03/04/2008, *bari* <bari at onelabs.com <mailto:
> > > > > > > bari at onelabs.com>> wrote:
> > > > > > >
> > > > > > >    malatesh kamatad wrote:
> > > > > > >
> > > > > > >
> > > > > > >        Hi all..
> > > > > > >              I have worked with PM49fl00x.diff patch ,its
> > > > > > > worked fine
> > > > > > >        and i got the output as below
> > > > > > >
> > > > > > >    The PM49fl00x can work in LPC and FWH modes. Do you know
> > > > > > > which
> > > > > > >    mode is being used?
> > > > > > >    What mainboard did you test this in?
> > > > > > >
> > > > > > >                           Now i am working on SST49LF004B
> > > > > > >                                      33-4C-NHE
> > > > > > >                                          0710022-CA   with the
> > > > > > >         motherboard  K8Upgrade-VM800
> > > > > > >                         The flashrom detect flash device on
> > > > > > > this
> > > > > > >        board, But the erasing and writting operation is not
> > > > > > > happening
> > > > > > >        properly
> > > > > > >          hier flashrom output :
> > > > > > >    Is this the board by ASRock?
> > > > > > >
> > > > > > >    -Bari
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > >
> > > > >
> > > >
> > > > --
> > > > coreboot mailing list
> > > > coreboot at coreboot.org
> > > > http://www.coreboot.org/mailman/listinfo/coreboot
> > > >
> > >
> > >
> >
>
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From svn at coreboot.org  Fri Apr  4 15:28:10 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 15:28:10 +0200
Subject: [coreboot] r3214 - trunk/payloads/coreinfo
Message-ID: <mailman.1368.1355071295.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-04 15:28:10 +0200 (Fri, 04 Apr 2008)
New Revision: 3214

Modified:
   trunk/payloads/coreinfo/Kconfig
Log:
Document a rough estimate of how much space in the ELF file each of the
coreinfo features / modules will consume (trivial).

The measurements were done with libpayload r3213 (but compiled with -Os),
and coreinfo r3211 (also compiled with -Os).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/payloads/coreinfo/Kconfig
===================================================================
--- trunk/payloads/coreinfo/Kconfig	2008-04-04 13:16:33 UTC (rev 3213)
+++ trunk/payloads/coreinfo/Kconfig	2008-04-04 13:28:10 UTC (rev 3214)
@@ -34,6 +34,8 @@
 	  Show the current date and time in the lower-right corner of
 	  the coreinfo menu.
 
+	  This option will increase the ELF file size by ca. 256 bytes.
+
 endmenu
 
 menu "Modules"
@@ -41,18 +43,26 @@
 config MODULE_COREBOOT
 	bool "Enable the coreboot module"
 	default y
+	help
+	  This option will increase the ELF file size by ca. 2250 bytes.
 
 config MODULE_CPUINFO
 	bool "Enable the cpuinfo module"
 	default y
+	help
+	  This option will increase the ELF file size by ca. 2650 bytes.
 
 config MODULE_PCI
 	bool "Enable the PCI info module"
 	default y
+	help
+	  This option will increase the ELF file size by ca. 1750 bytes.
 
 config MODULE_NVRAM
 	bool "Enable the NVRAM dump module"
 	default y
+	help
+	  This option will increase the ELF file size by ca. 150 bytes.
 
 endmenu
 




From uwe at hermann-uwe.de  Fri Apr  4 15:53:06 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Apr 2008 15:53:06 +0200
Subject: [coreboot] [PATCH] coreinfo: Fix build for zero selected modules
Message-ID: <20080404135306.GA22836@greenwood>

See patch.

(yes, there are valid reasons to build a coreinfo with no modules
selected at all -- not all coreinfo functionality is implemented
as a module; even if it would, no valid kconfig combination should
result in a failing build)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at coreboot.org  Fri Apr  4 16:02:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 16:02:40 +0200
Subject: [coreboot] r653 - coreboot-v3
Message-ID: <mailman.1369.1355071295.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-04 16:02:39 +0200 (Fri, 04 Apr 2008)
New Revision: 653

Modified:
   coreboot-v3/HACKING
Log:
Document origins of util/lar/elf.h (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: coreboot-v3/HACKING
===================================================================
--- coreboot-v3/HACKING	2008-04-04 13:10:05 UTC (rev 652)
+++ coreboot-v3/HACKING	2008-04-04 14:02:39 UTC (rev 653)
@@ -59,6 +59,11 @@
 * util/lar/*: GPLv2
   Independant project, but written specifically for coreboot.
 
+* util/lar/elf.h: LGPL-2.1 or later
+  Source: glibc, http://ftp.gnu.org/gnu/glibc/
+  Original files: elf/elf.h
+  Current version we use: 2.7
+
 * include/lar.h, util/lar/lar.h, util/lar/example.c:
   Dual-licensed (GPLv2 + revised BSD license)
 




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 16:27:37 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 16:27:37 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F6285F.2040807@coresystems.de>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<47F6285F.2040807@coresystems.de>
Message-ID: <47F63AD9.7060909@gmx.net>

On 04.04.2008 15:08, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>> On 04.04.2008 04:40, Stefan Reinauer wrote:
>>  
>>> The idea to this patch is from Patrick Georgi but I reimplemented it
>>> from scratch since I can't reach the other box for a few days. It
>>> fixes stage0_i586.S assembling on the latest official GNU binutils
>>> version. Without this patch the compilation fails with:
>>>
>>>  AS      build/arch/x86/stage0_i586.o
>>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler
>>> messages:
>>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:345: Error:
>>> missing ')'
> [..]
>> Sorry, that patch only papers over the bug. If we ever decide to use CAR
>> at another location, this will break again and we'll have to duplicate
>> some of the code you touched in the patch. I'd prefer to know why a
>> division fails, but a subtractoin succeeds.
>>   
> Why is that code more position dependent than the previous,
> non-compiling code?

You hardcode the segment size to 4k. If we place the CAR area somewhere
else, we have to deal with 16k and even 64k segments. The current code
uses abstract segments as a unit and that abstraction is removed by the
patch.


> While I think, requiring the latest version of binutils (or, any other
> toolchain part, for that matter) is fair, we should not require
> features that do not work in the latest "stable" version but require a
> snapshot release to be installed.

It works in older versions. The version you used is buggy. There is no
reason not to blacklist that broken version unless someone can prove
that the new behaviour is correct according to any spec.

Regards,
Carl-Daniel



From stepan at coresystems.de  Fri Apr  4 16:27:57 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 08:27:57 -0600
Subject: [coreboot] [PATCH] coreinfo: Fix build for zero selected modules
In-Reply-To: <20080404135306.GA22836@greenwood>
References: <20080404135306.GA22836@greenwood>
Message-ID: <47F63AED.1090700@coresystems.de>

Uwe Hermann wrote:
> See patch.
>
> (yes, there are valid reasons to build a coreinfo with no modules
> selected at all -- not all coreinfo functionality is implemented
> as a module; even if it would, no valid kconfig combination should
> result in a failing build)
>
>
> Uwe.
>   
Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From stepan at coresystems.de  Fri Apr  4 16:32:17 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 08:32:17 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F63AD9.7060909@gmx.net>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
Message-ID: <47F63BF1.4010100@coresystems.de>

Carl-Daniel Hailfinger wrote:
>> While I think, requiring the latest version of binutils (or, any other
>> toolchain part, for that matter) is fair, we should not require
>> features that do not work in the latest "stable" version but require a
>> snapshot release to be installed.
>>     
>
> It works in older versions. The version you used is buggy. There is no
> reason not to blacklist that broken version unless someone can prove
> that the new behaviour is correct according to any spec.
>   
That's plain wrong, sorry. I also used 2.17 and the error is the same. 
So the two latest stable versions of binutils don't work with that code. 
You won't get that code to translate unless you use an experimental 
version of binutils (snapshot).

So either we get this problem solved differently or I'll have to go 
ahead and check the patch in. Relying on experimental toolchains is not 
an option. Even if your toolchain provider uses experimental binutils 
versions, that's nothing we should enforce.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Fri Apr  4 16:49:50 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 16:49:50 +0200
Subject: [coreboot] r654 - coreboot-v3/arch/x86
Message-ID: <mailman.1370.1355071295.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-04-04 16:49:50 +0200 (Fri, 04 Apr 2008)
New Revision: 654

Modified:
   coreboot-v3/arch/x86/stage0_i586.S
Log:
Add a workaround for a bug in some binutils version which strictly
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669

This was committed as r3044 in coreboot v2.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Jordan Crouse <jordan.crouse at amd.com> 


Modified: coreboot-v3/arch/x86/stage0_i586.S
===================================================================
--- coreboot-v3/arch/x86/stage0_i586.S	2008-04-04 14:02:39 UTC (rev 653)
+++ coreboot-v3/arch/x86/stage0_i586.S	2008-04-04 14:49:50 UTC (rev 654)
@@ -319,8 +319,15 @@
  * windowoffset is the 32k-aligned window into CAR size
  */
 .macro simplemask carsize, windowoffset
+	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+	extractmask gas_bug_workaround, %eax
+	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+	extractmask gas_bug_workaround, %edx
+/* Without the gas bug workaround, the entire macro would consist only of the
+ * two lines below.
 	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
 	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+ */
 .endm
 
 #if CacheSize > 0x10000




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 16:54:08 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 16:54:08 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F63BF1.4010100@coresystems.de>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de>
Message-ID: <47F64110.7010602@gmx.net>

On 04.04.2008 16:32, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>>> While I think, requiring the latest version of binutils (or, any other
>>> toolchain part, for that matter) is fair, we should not require
>>> features that do not work in the latest "stable" version but require a
>>> snapshot release to be installed.
>>>     
>>
>> It works in older versions. The version you used is buggy. There is no
>> reason not to blacklist that broken version unless someone can prove
>> that the new behaviour is correct according to any spec.
>>   
> That's plain wrong, sorry. I also used 2.17 and the error is the same.
> So the two latest stable versions of binutils don't work with that
> code. You won't get that code to translate unless you use an
> experimental version of binutils (snapshot).

I stand corrected. We fixed one binutils problem with that piece of code
in r3044 of v2, but the patch was not applied to v3. I have corrected
that in r654 of v3.

> So either we get this problem solved differently or I'll have to go
> ahead and check the patch in. Relying on experimental toolchains is
> not an option. Even if your toolchain provider uses experimental
> binutils versions, that's nothing we should enforce.

Can you retest with current HEAD? Thanks!

Regards,
Carl-Daniel



From svn at coreboot.org  Fri Apr  4 17:02:45 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 17:02:45 +0200
Subject: [coreboot] r3215 - trunk/coreboot-v2/src/cpu/x86/car
Message-ID: <mailman.1371.1355071295.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-04-04 17:02:45 +0200 (Fri, 04 Apr 2008)
New Revision: 3215

Modified:
   trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc
Log:
Add a workaround for a bug in some binutils version which strictly
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669

The same change was committed in r3044 to the AMD CAR code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>


Modified: trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc	2008-04-04 13:28:10 UTC (rev 3214)
+++ trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc	2008-04-04 15:02:45 UTC (rev 3215)
@@ -158,8 +158,15 @@
  * windowoffset is the 32k-aligned window into CAR size
  */
 .macro simplemask carsize, windowoffset
+	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+	extractmask gas_bug_workaround, %eax
+	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+	extractmask gas_bug_workaround, %edx
+/* Without the gas bug workaround, the entire macro would consist only of the
+ * two lines below.
 	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
 	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+ */
 .endm
 
 #if CacheSize > 0x10000




From peter at stuge.se  Fri Apr  4 17:52:18 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 17:52:18 +0200
Subject: [coreboot] [PATCH] Add subversion number
In-Reply-To: <20080404122531.GA14205@greenwood>
References: <47F59BC7.2090908@coresystems.de>
	<20080404032446.GA16511@localdomain>
	<20080404085637.22591.qmail@stuge.se>
	<20080404122531.GA14205@greenwood>
Message-ID: <20080404155218.24792.qmail@stuge.se>

On Fri, Apr 04, 2008 at 02:25:31PM +0200, Uwe Hermann wrote:
> > I really like this idea but the patch depends on svn being installed
> > to build properly.
> 
> Yes, but I think it would be ok if we use "unknown" or "0" or something
> like that if svn is not available

For tarballs that we make available I don't like that so much.
It is very useful information to have in debug logs.


> (haven't tried what happens currently).

I expect it to just be blank.


//Peter



From stepan at coresystems.de  Fri Apr  4 17:57:21 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 09:57:21 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F64110.7010602@gmx.net>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de> <47F64110.7010602@gmx.net>
Message-ID: <47F64FE1.6050306@coresystems.de>

Carl-Daniel Hailfinger wrote:

>> So either we get this problem solved differently or I'll have to go
>> ahead and check the patch in. Relying on experimental toolchains is
>> not an option. Even if your toolchain provider uses experimental
>> binutils versions, that's nothing we should enforce.
>>     
>
> Can you retest with current HEAD? Thanks!
>   
Great! It reduced the number of errors:

  AS      build/arch/x86/stage0_i586.o
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler messages:
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error: 
missing ')'
/Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error: 
missing ')'
make: *** [/Users/stepan/Devel/coreboot-v3/build/arch/x86/stage0_i586.o] 
Error 1

I think this is getting there.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From peter at stuge.se  Fri Apr  4 18:19:18 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 18:19:18 +0200
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804040625wb01013vd941cd25fb274bba@mail.gmail.com>
References: <fa70bcc0804022259v42aafdfar9cefc900b0a3c516@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
	<dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
	<fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>
	<dd3c80060804040559h4b7510b1q7747f44e897fa4da@mail.gmail.com>
	<fa70bcc0804040625wb01013vd941cd25fb274bba@mail.gmail.com>
Message-ID: <20080404161918.2073.qmail@stuge.se>

Hello,

On Fri, Apr 04, 2008 at 06:55:11PM +0530, malatesh kamatad wrote:
> Ya .. after checking that file i got result like this ...it shows
> that there is a content in that file
> 
> [root at localhost ~]# hexdump sst_after_erase.bin
> 0000000 ffff ffff ffff ffff ffff ffff ffff ffff
> *
> 0080000

This shows that erasing the chip works correctly. That is good news.

hexdump uses * to indicate that the previous 16 bytes of data is
repeated until the next printed address. In this case the file
contains all 0xff.


>   I think erasing is not happened properly..

Flash memory erases to all bits set to 1. When bytes are "flashed",
the neccesary bits in each byte are cleared to 0.


Please also do hexdump of sst_after_write.bin. Hopefully the contents
of that file can provide some hints about why writing fails.

This could be a timing problem in flashrom, but that is just a guess.


//Peter



From svn at coreboot.org  Fri Apr  4 18:49:11 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  4 Apr 2008 18:49:11 +0200
Subject: [coreboot] r3216 - trunk/payloads/coreinfo
Message-ID: <mailman.1372.1355071295.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-04 18:49:09 +0200 (Fri, 04 Apr 2008)
New Revision: 3216

Modified:
   trunk/payloads/coreinfo/coreinfo.c
Log:
Fix the case where the user selects no modules in Kconfig at all.
Until now, the build would break, and even if it didn't the ELF would
triple-fault in QEMU.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/payloads/coreinfo/coreinfo.c
===================================================================
--- trunk/payloads/coreinfo/coreinfo.c	2008-04-04 15:02:45 UTC (rev 3215)
+++ trunk/payloads/coreinfo/coreinfo.c	2008-04-04 16:49:09 UTC (rev 3216)
@@ -72,7 +72,8 @@
 	for (i = 0; i < ARRAY_SIZE(modules); i++)
 		ptr += sprintf(ptr, "F%d: %s ", i + 1, modules[i]->name);
 
-	mvprintw(23, 0, menu);
+	if (ARRAY_SIZE(modules) != 0)
+		mvprintw(23, 0, menu);
 
 #ifdef CONFIG_SHOW_DATE_TIME
 	mvprintw(23, 59, "%02d/%02d/20%02d - %02d:%02d:%02d",
@@ -121,6 +122,9 @@
 
 static void redraw_module(void)
 {
+	if (ARRAY_SIZE(modules) == 0)
+		return;
+
 	wclear(modwin);
 	modules[curwin]->redraw(modwin);
 	refresh();
@@ -133,7 +137,8 @@
 	center(0, "coreinfo v0.1");
 
 	print_menu();
-	modules[curwin]->redraw(modwin);
+	if (ARRAY_SIZE(modules) != 0)
+		modules[curwin]->redraw(modwin);
 	refresh();
 
 	while (1) {
@@ -145,14 +150,16 @@
 		if (key >= KEY_F(1) && key <= KEY_F(9)) {
 			unsigned char ch = key - KEY_F(1);
 
-			if (ch < ARRAY_SIZE(modules)) {
+			if (ch <= ARRAY_SIZE(modules)) {
+				if (ch == ARRAY_SIZE(modules))
+					continue;
 				curwin = ch;
 				redraw_module();
 				continue;
 			}
 		}
 
-		if (modules[curwin]->handle)
+		if (ARRAY_SIZE(modules) != 0 && modules[curwin]->handle)
 			if (modules[curwin]->handle(key))
 				redraw_module();
 	}




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 18:51:17 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 18:51:17 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F64FE1.6050306@coresystems.de>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de> <47F64110.7010602@gmx.net>
	<47F64FE1.6050306@coresystems.de>
Message-ID: <47F65C85.7060204@gmx.net>

On 04.04.2008 17:57, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>
>>> So either we get this problem solved differently or I'll have to go
>>> ahead and check the patch in. Relying on experimental toolchains is
>>> not an option. Even if your toolchain provider uses experimental
>>> binutils versions, that's nothing we should enforce.
>>>     
>>
>> Can you retest with current HEAD? Thanks!
>>   
> Great! It reduced the number of errors:
>
>  AS      build/arch/x86/stage0_i586.o
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler
> messages:
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
> missing ')'
> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
> missing ')'
> make: ***
> [/Users/stepan/Devel/coreboot-v3/build/arch/x86/stage0_i586.o] Error 1
>
> I think this is getting there.

Strange. The code now should be identical to what we use for v2 AMD CAR.
I'll see what I can do. Probably some #define needs to be replaced with
.set to fix the rest of the bug. I'll report back ASAP.

By the way, why are you working with the _generic_ x86 CAR code in v3
instead of porting the _AMD_ CAR code from v2 to v3?


Regards,
Carl-Daniel



From uwe at hermann-uwe.de  Fri Apr  4 18:54:25 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 4 Apr 2008 18:54:25 +0200
Subject: [coreboot] [PATCH] coreinfo: Fix build for zero selected	modules
In-Reply-To: <47F63AED.1090700@coresystems.de>
References: <20080404135306.GA22836@greenwood>
	<47F63AED.1090700@coresystems.de>
Message-ID: <20080404165425.GA27933@greenwood>

On Fri, Apr 04, 2008 at 08:27:57AM -0600, Stefan Reinauer wrote:
> Acked-by: Stefan Reinauer <stepan at coresystems.de>

Thanks, r3216.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 19:06:56 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 19:06:56 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F65C85.7060204@gmx.net>
References: <47F5952F.1060803@coresystems.de>
	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>
	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>
	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>
	<47F65C85.7060204@gmx.net>
Message-ID: <47F66030.5070800@gmx.net>

On 04.04.2008 18:51, Carl-Daniel Hailfinger wrote:
> On 04.04.2008 17:57, Stefan Reinauer wrote:
>   
>> Carl-Daniel Hailfinger wrote:
>>
>>     
>>>> So either we get this problem solved differently or I'll have to go
>>>> ahead and check the patch in. Relying on experimental toolchains is
>>>> not an option. Even if your toolchain provider uses experimental
>>>> binutils versions, that's nothing we should enforce.
>>>>     
>>>>         
>>> Can you retest with current HEAD? Thanks!
>>>   
>>>       
>> Great! It reduced the number of errors:
>>
>>  AS      build/arch/x86/stage0_i586.o
>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler
>> messages:
>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>> missing ')'
>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>> missing ')'
>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>> missing ')'
>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>> missing ')'
>> make: ***
>> [/Users/stepan/Devel/coreboot-v3/build/arch/x86/stage0_i586.o] Error 1
>>
>> I think this is getting there.
>>     
>
> Strange. The code now should be identical to what we use for v2 AMD CAR.
>   

Actually, I think that any v2 AMD CAR target should fail as well on a
machine having problems with this code in v3. Maybe there is a
difference after preprocessing somewhere...

> I'll see what I can do. Probably some #define needs to be replaced with
> .set to fix the rest of the bug. I'll report back ASAP.
>
> By the way, why are you working with the _generic_ x86 CAR code in v3
> instead of porting the _AMD_ CAR code from v2 to v3?
>   

Do you have any patch which would help me reproduce the issue? The v3
tree currently lacks a target using the code in question.


Regards,
Carl-Daniel



From mart.raudsepp at artecdesign.ee  Fri Apr  4 19:35:39 2008
From: mart.raudsepp at artecdesign.ee (Mart Raudsepp)
Date: Fri, 04 Apr 2008 20:35:39 +0300
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
Message-ID: <1207330539.4785.20.camel@martr-gentoo.artec>

?hel kenal p?eval, K, 2008-04-02 kell 23:04, kirjutas ron minnich:
> now how do we get a disk to boot? All we have is USB :-)

Actually we have 3.75MB of space to use for kernel and initramfs on the
dongle ;)


boot: mem at 0xffc00000,0x140000 initrd=mem at 0xffd40000,0x140000 console=tty0 console=ttyS0,115200 ro
Found Linux version 2.6.24.3 (leio at martr-gentoo) #1 PREEMPT Thu Apr 3 17:41:23 EEST 2008 bzImage.
.....
BusyBox v1.9.1 (2008-04-03 17:34:30 EEST) built-in shell (ash)


In other words, I get a busybox shell from the SVN HEAD code of
coreboot-v3 on DBE62 now! Nice work Ron and co


To get that I had to enable 4MB mode on the dongle with a
outb(0xf4,0x88);
in some init code. Picked randomly northbridge/amd/geodelx/geodelxinit.c
northbridge_init_early() as a hack

Then I had to manually add the VSA, as its requirement seems hardcoded
and its addition isn't part of the build in a manner payload.elf is.

And then I merged together a 4MB image from a kernel image, initramfs
image and the firmware, like so:

        cp vmlinuz "dongle_image"
        dd if=initrd.gz of="dongle_image" bs=4096 seek=320
        dd if=firmware.rom of="dongle_image" bs=4096 seek=960 # assumes 256KB firmware image

and wrote that to the dongle.

My payload.elf was a FILO that has
AUTOBOOT_FILE = "mem at 0xffc00000,0x140000 initrd=mem at 0xffd40000,0x140000 console=tty0 console=ttyS0,115200 ro"

This then allows for a 1.25MB kernel and 1.25MB zero padded initramfs
from inside the dongle, adjust numbers as necessary. In particular the
size of initrd could be 0x280000 or offsets shuffled around for a bigger
kernel - I just used those numbers as everything fits nicely that I need
and I don't need to write in too much zeroes for replacing just the
initramfs (kernel chokes if the given size is larger than the actual
initramfs, but is fine if the remaining space is zero padded). The
offsets are chosen from the starting points of the 32 erase blocks
(equally divided amongst the 4MB) so that when overwriting one part, it
doesn't erase the end of the previous content.


The initrd.gz was created from a rootfs directory with
cd "rootfs" && find . | cpio --quiet -o -H newc | gzip -9 >"../initrd.gz"


NAND and network doesn't seem to work at first glance, but nice progress!

CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.


Regards,
Mart Raudsepp
Artec Design LLC




From stepan at coresystems.de  Fri Apr  4 19:47:38 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 11:47:38 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F65C85.7060204@gmx.net>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de> <47F64110.7010602@gmx.net>
	<47F64FE1.6050306@coresystems.de> <47F65C85.7060204@gmx.net>
Message-ID: <47F669BA.10102@coresystems.de>

Carl-Daniel Hailfinger wrote:
> Strange. The code now should be identical to what we use for v2 AMD CAR.
> I'll see what I can do. Probably some #define needs to be replaced with
> .set to fix the rest of the bug. I'll report back ASAP.
>
> By the way, why are you working with the _generic_ x86 CAR code in v3
> instead of porting the _AMD_ CAR code from v2 to v3?
>   

Excuse me, I don't understand your question. I just try to compile 
coreboot v3 for Qemu.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From stepan at coresystems.de  Fri Apr  4 19:49:46 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 11:49:46 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F66030.5070800@gmx.net>
References: <47F5952F.1060803@coresystems.de>	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>	<47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net>
Message-ID: <47F66A3A.3030801@coresystems.de>

Carl-Daniel Hailfinger wrote:
> Do you have any patch which would help me reproduce the issue? The v3
> tree currently lacks a target using the code in question.
>
>   
Not at all. Just build the Qemu target with a freshly checked out tree 
and an official version of binutils from gnu.org


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 19:50:14 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 19:50:14 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F66030.5070800@gmx.net>
References: <47F5952F.1060803@coresystems.de>	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>	<47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net>
Message-ID: <47F66A56.2090301@gmx.net>

On 04.04.2008 19:06, Carl-Daniel Hailfinger wrote:
> On 04.04.2008 18:51, Carl-Daniel Hailfinger wrote:
>   
>> On 04.04.2008 17:57, Stefan Reinauer wrote:
>>   
>>     
>>> Carl-Daniel Hailfinger wrote:
>>>
>>>     
>>>       
>>>>> So either we get this problem solved differently or I'll have to go
>>>>> ahead and check the patch in. Relying on experimental toolchains is
>>>>> not an option. Even if your toolchain provider uses experimental
>>>>> binutils versions, that's nothing we should enforce.
>>>>>     
>>>>>         
>>>>>           
>>>> Can you retest with current HEAD? Thanks!
>>>>   
>>>>       
>>>>         
>>> Great! It reduced the number of errors:
>>>
>>>  AS      build/arch/x86/stage0_i586.o
>>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S: Assembler
>>> messages:
>>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>>> missing ')'
>>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>>> missing ')'
>>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>>> missing ')'
>>> /Users/stepan/Devel/coreboot-v3/arch/x86/stage0_i586.S:352: Error:
>>> missing ')'
>>> make: ***
>>> [/Users/stepan/Devel/coreboot-v3/build/arch/x86/stage0_i586.o] Error 1
>>>
>>> I think this is getting there.
>>>     
>>>       
>> Strange. The code now should be identical to what we use for v2 AMD CAR.
>>   
>>     
>
> Actually, I think that any v2 AMD CAR target should fail as well on a
> machine having problems with this code in v3. Maybe there is a
> difference after preprocessing somewhere...
>   

Please include build/arch/x86/stage0_asm.s in your reply. We should be
able to reduce that file to a simple testcase. Maybe you want to CC:
Segher in your reply.


>> I'll see what I can do. Probably some #define needs to be replaced with
>> .set to fix the rest of the bug. I'll report back ASAP.
>>
>> By the way, why are you working with the _generic_ x86 CAR code in v3
>> instead of porting the _AMD_ CAR code from v2 to v3?
>>   
>>     
>
> Do you have any patch which would help me reproduce the issue? The v3
> tree currently lacks a target using the code in question.
>   

I take that back. The qemu target in v3 compiles fine for me and it uses
that file. I have an i686 openSUSE 10.3 system with
GNU ld (GNU Binutils) 2.17.50.20070726-14 (SUSE Linux)

Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 19:52:58 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 19:52:58 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F669BA.10102@coresystems.de>
References: <47F5952F.1060803@coresystems.de>
	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>
	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>
	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>
	<47F65C85.7060204@gmx.net> <47F669BA.10102@coresystems.de>
Message-ID: <47F66AFA.4090709@gmx.net>

On 04.04.2008 19:47, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>> Strange. The code now should be identical to what we use for v2 AMD CAR.
>> I'll see what I can do. Probably some #define needs to be replaced with
>> .set to fix the rest of the bug. I'll report back ASAP.
>>
>> By the way, why are you working with the _generic_ x86 CAR code in v3
>> instead of porting the _AMD_ CAR code from v2 to v3?
>>   
>
> Excuse me, I don't understand your question. I just try to compile
> coreboot v3 for Qemu.

Ah sorry, I thought you were trying to port K8 to v3.

Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 19:54:11 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 19:54:11 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F66A3A.3030801@coresystems.de>
References: <47F5952F.1060803@coresystems.de>	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>	<47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
Message-ID: <47F66B43.5010009@gmx.net>

On 04.04.2008 19:49, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>> Do you have any patch which would help me reproduce the issue? The v3
>> tree currently lacks a target using the code in question.
>>
>>   
> Not at all. Just build the Qemu target with a freshly checked out tree
> and an official version of binutils from gnu.org

By the way, IIRC Segher once wrote that binutils from gnu.org are a
completely different beast compared to "linux binutils" shipped by
almost all distributors.

Regards,
Carl-Daniel



From stepan at coresystems.de  Fri Apr  4 20:01:34 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 12:01:34 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F66B43.5010009@gmx.net>
References: <47F5952F.1060803@coresystems.de>	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>	<47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net>
Message-ID: <47F66CFE.20208@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 04.04.2008 19:49, Stefan Reinauer wrote:
>   
>> Carl-Daniel Hailfinger wrote:
>>     
>>> Do you have any patch which would help me reproduce the issue? The v3
>>> tree currently lacks a target using the code in question.
>>>
>>>   
>>>       
>> Not at all. Just build the Qemu target with a freshly checked out tree
>> and an official version of binutils from gnu.org
>>     
>
> By the way, IIRC Segher once wrote that binutils from gnu.org are a
> completely different beast compared to "linux binutils" shipped by
> almost all distributors.
>   

No doubt. But I am compiling coreboot, not Linux.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From eswierk at arastra.com  Fri Apr  4 20:07:55 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Fri, 4 Apr 2008 11:07:55 -0700
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F66B43.5010009@gmx.net>
References: <47F5952F.1060803@coresystems.de> <47F6285F.2040807@coresystems.de>
	<47F63AD9.7060909@gmx.net> <47F63BF1.4010100@coresystems.de>
	<47F64110.7010602@gmx.net> <47F64FE1.6050306@coresystems.de>
	<47F65C85.7060204@gmx.net> <47F66030.5070800@gmx.net>
	<47F66A3A.3030801@coresystems.de> <47F66B43.5010009@gmx.net>
Message-ID: <e6c711510804041107k7d7241a6p6819d98df2284ce9@mail.gmail.com>

On Fri, Apr 4, 2008 at 10:54 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
>  By the way, IIRC Segher once wrote that binutils from gnu.org are a
>  completely different beast compared to "linux binutils" shipped by
>  almost all distributors.

In an ideal world coreboot would be buildable on a wide variety of
binutils versions, but it seems to me that coreboot uses a number of
linker features that just aren't well exercised and only a few people
on the planet understand at all, judging from bug discussions on the
binutils lists. Since I'm not one of them, I choose to be lazy and
stop fighting binutils bugs.

So with the latest Fedora upgrade, I gave up on using the Fedora
binutils and now build a gnu.org one from scratch (along with a
complete cross-compiling toolchain for building a Linux payload with
busybox, uClibc, etc.--I'm happy to share the build scripts if anyone
is interested).

FWIW.

--Ed



From peter at stuge.se  Fri Apr  4 20:28:55 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 20:28:55 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <e6c711510804041107k7d7241a6p6819d98df2284ce9@mail.gmail.com>
References: <47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de> <47F64110.7010602@gmx.net>
	<47F64FE1.6050306@coresystems.de> <47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net>
	<e6c711510804041107k7d7241a6p6819d98df2284ce9@mail.gmail.com>
Message-ID: <20080404182855.23044.qmail@stuge.se>

On Fri, Apr 04, 2008 at 11:07:55AM -0700, Ed Swierk wrote:
> So with the latest Fedora upgrade, I gave up on using the Fedora
> binutils and now build a gnu.org one from scratch (along with a
> complete cross-compiling toolchain for building a Linux payload with
> busybox, uClibc, etc.--I'm happy to share the build scripts if anyone
> is interested).

Also there is crossdev and just plain Gentoo, either just vanilla
binutils ebuilds or even catalyst for a complete custom system build.


//Peter



From peter at stuge.se  Fri Apr  4 20:31:13 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 20:31:13 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F66CFE.20208@coresystems.de>
References: <47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de> <47F64110.7010602@gmx.net>
	<47F64FE1.6050306@coresystems.de> <47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net> <47F66CFE.20208@coresystems.de>
Message-ID: <20080404183113.24239.qmail@stuge.se>

On Fri, Apr 04, 2008 at 12:01:34PM -0600, Stefan Reinauer wrote:
> >binutils from gnu.org are a completely different beast compared to
> >"linux binutils" shipped by almost all distributors.
> 
> No doubt. But I am compiling coreboot, not Linux.

I think the meaning was "found in Linux" rather than
"meant for building Linux."

Yes, distributions are patch happy. Maybe simply because their
timeframe is too different from upstream.


//Peter



From eswierk at arastra.com  Fri Apr  4 20:43:45 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Fri, 4 Apr 2008 11:43:45 -0700
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <20080404182855.23044.qmail@stuge.se>
References: <47F6285F.2040807@coresystems.de> <47F63BF1.4010100@coresystems.de>
	<47F64110.7010602@gmx.net> <47F64FE1.6050306@coresystems.de>
	<47F65C85.7060204@gmx.net> <47F66030.5070800@gmx.net>
	<47F66A3A.3030801@coresystems.de> <47F66B43.5010009@gmx.net>
	<e6c711510804041107k7d7241a6p6819d98df2284ce9@mail.gmail.com>
	<20080404182855.23044.qmail@stuge.se>
Message-ID: <e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>

On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
>  Also there is crossdev and just plain Gentoo, either just vanilla
>  binutils ebuilds or even catalyst for a complete custom system build.

And buildroot and LFS and lots of others too. I'm not knocking any of
those, but they are more complex than what I was looking for. My
50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.

--Ed
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 20:54:02 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 20:54:02 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <20080404183113.24239.qmail@stuge.se>
References: <47F6285F.2040807@coresystems.de>
	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>
	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>
	<47F65C85.7060204@gmx.net>	<47F66030.5070800@gmx.net>
	<47F66A3A.3030801@coresystems.de>	<47F66B43.5010009@gmx.net>
	<47F66CFE.20208@coresystems.de>
	<20080404183113.24239.qmail@stuge.se>
Message-ID: <47F6794A.1040201@gmx.net>

On 04.04.2008 20:31, Peter Stuge wrote:
> On Fri, Apr 04, 2008 at 12:01:34PM -0600, Stefan Reinauer wrote:
>   
>>> binutils from gnu.org are a completely different beast compared to
>>> "linux binutils" shipped by almost all distributors.
>>>       
>> No doubt. But I am compiling coreboot, not Linux.
>>     
>
> I think the meaning was "found in Linux" rather than
> "meant for building Linux."
>   

Indeed.

> Yes, distributions are patch happy. Maybe simply because their
> timeframe is too different from upstream.
>   

That, and sometimes it is difficult to get some "essential" patches
merged upstream.

Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 20:59:50 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 20:59:50 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <20080404182855.23044.qmail@stuge.se>
References: <47F6285F.2040807@coresystems.de>
	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>
	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>
	<47F65C85.7060204@gmx.net>	<47F66030.5070800@gmx.net>
	<47F66A3A.3030801@coresystems.de>	<47F66B43.5010009@gmx.net>	<e6c711510804041107k7d7241a6p6819d98df2284ce9@mail.gmail.com>
	<20080404182855.23044.qmail@stuge.se>
Message-ID: <47F67AA6.80805@gmx.net>

On 04.04.2008 20:28, Peter Stuge wrote:
> On Fri, Apr 04, 2008 at 11:07:55AM -0700, Ed Swierk wrote:
>   
>> So with the latest Fedora upgrade, I gave up on using the Fedora
>> binutils and now build a gnu.org one from scratch (along with a
>> complete cross-compiling toolchain for building a Linux payload with
>> busybox, uClibc, etc.--I'm happy to share the build scripts if anyone
>> is interested).
>>     
>
> Also there is crossdev and just plain Gentoo, either just vanilla
> binutils ebuilds or even catalyst for a complete custom system build.
>   

Can all of you please try to build the qemu target in v3 (preferably svn
HEAD)?
It is really easy (make distclean; make menuconfig; make), leave all
settings at the default in menuconfig, then simply exit with saving the
configuration.

I would be very interested in build/arch/x86/stage0_asm.s if the build
fails for you.


Regards,
Carl-Daniel



From segher at kernel.crashing.org  Fri Apr  4 21:07:21 2008
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 4 Apr 2008 21:07:21 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <1207290820.5987.11.camel@tetris>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<1207290820.5987.11.camel@tetris>
Message-ID: <60e541fc694fdf3c339203313511cf6a@kernel.crashing.org>

> parentheses fail in the gnuas macros.

For reference, it is called "GNU assembler" or "GAS".

>  for some reason, when copying the
> arguments, gnu as (in that defective version) stops after the first
> closing ')', making the whole statement invalid.

What GAS versions fail?  Steps to reproduce / standalone testcase?


Segher




From segher at kernel.crashing.org  Fri Apr  4 21:09:34 2008
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 4 Apr 2008 21:09:34 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F63BF1.4010100@coresystems.de>
References: <47F5952F.1060803@coresystems.de> <47F5C4F4.6030205@gmx.net>
	<47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de>
Message-ID: <912d6c330961ed9e917f6be1e2d1850b@kernel.crashing.org>

>> It works in older versions. The version you used is buggy. There is no
>> reason not to blacklist that broken version unless someone can prove
>> that the new behaviour is correct according to any spec.
>>
> That's plain wrong, sorry. I also used 2.17 and the error is the same. 
> So the two latest stable versions of binutils don't work with that 
> code. You won't get that code to translate unless you use an 
> experimental version of binutils (snapshot).

There is nothing "experimental" about binutils mainline.

> So either we get this problem solved differently or I'll have to go 
> ahead and check the patch in. Relying on experimental toolchains is 
> not an option. Even if your toolchain provider uses experimental 
> binutils versions, that's nothing we should enforce.

Not if there's a sane workaround, no.


Segher




From segher at kernel.crashing.org  Fri Apr  4 21:11:18 2008
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 4 Apr 2008 21:11:18 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F66B43.5010009@gmx.net>
References: <47F5952F.1060803@coresystems.de>	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>	<47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net>
Message-ID: <17ca70155e87083344f089081d506062@kernel.crashing.org>

>>> Do you have any patch which would help me reproduce the issue? The v3
>>> tree currently lacks a target using the code in question.
>>>
>>>
>> Not at all. Just build the Qemu target with a freshly checked out tree
>> and an official version of binutils from gnu.org
>
> By the way, IIRC Segher once wrote that binutils from gnu.org are a
> completely different beast compared to "linux binutils" shipped by
> almost all distributors.

Not a "completely different beast", but please do us a favour and try
with FSF binutils before reporting problems :-)


Segher




From segher at kernel.crashing.org  Fri Apr  4 21:20:30 2008
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 4 Apr 2008 21:20:30 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <20080404183113.24239.qmail@stuge.se>
References: <47F6285F.2040807@coresystems.de> <47F63AD9.7060909@gmx.net>
	<47F63BF1.4010100@coresystems.de> <47F64110.7010602@gmx.net>
	<47F64FE1.6050306@coresystems.de> <47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net> <47F66CFE.20208@coresystems.de>
	<20080404183113.24239.qmail@stuge.se>
Message-ID: <8bb64ad9e547aab44dd7662093730f66@kernel.crashing.org>

>>> binutils from gnu.org are a completely different beast compared to
>>> "linux binutils" shipped by almost all distributors.
>>
>> No doubt. But I am compiling coreboot, not Linux.
>
> I think the meaning was "found in Linux" rather than
> "meant for building Linux."

I mean the thing that calls itself "linux binutils":

http://www.kernel.org/pub/linux/devel/binutils/

Long ago, in a galaxy far far away, this was relevant.  Nowadays,
no one should have a reason not to use binutils mainline.


Segher




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 21:27:40 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 21:27:40 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <17ca70155e87083344f089081d506062@kernel.crashing.org>
References: <47F5952F.1060803@coresystems.de>	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>	<47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net>
	<17ca70155e87083344f089081d506062@kernel.crashing.org>
Message-ID: <47F6812C.4060005@gmx.net>

On 04.04.2008 21:11, Segher Boessenkool wrote:
>>>> Do you have any patch which would help me reproduce the issue? The v3
>>>> tree currently lacks a target using the code in question.
>>>>
>>>>
>>> Not at all. Just build the Qemu target with a freshly checked out tree
>>> and an official version of binutils from gnu.org
>>
>> By the way, IIRC Segher once wrote that binutils from gnu.org are a
>> completely different beast compared to "linux binutils" shipped by
>> almost all distributors.
>
> Not a "completely different beast", but please do us a favour and try
> with FSF binutils before reporting problems :-)

It seems that the FSF binutils are broken and the versions shipped by
distributors are OK. It was rumored that the failing build happened on
MacOS, if that helps any.

My best guess at what is failing for Stefan is attached. The failing
line is the one calling the simplemask macro.


Regards,
Carl-Daniel
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From juergen127 at kreuzholzen.de  Fri Apr  4 21:28:36 2008
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Fri, 4 Apr 2008 21:28:36 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>
References: <47F6285F.2040807@coresystems.de>
	<20080404182855.23044.qmail@stuge.se>
	<e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>
Message-ID: <200804042128.37199.juergen127@kreuzholzen.de>

On Friday 04 April 2008 20:43, Ed Swierk wrote:
> On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
> >  Also there is crossdev and just plain Gentoo, either just vanilla
> >  binutils ebuilds or even catalyst for a complete custom system build.
>
> And buildroot and LFS and lots of others too. I'm not knocking any of
> those, but they are more complex than what I was looking for. My
> 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
> binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.

What about a reference toolchain everybody can build on his host and use to 
compile coreboot? I believe we will out of luck to support every toolchain on 
this planet.

Juergen



From juergen127 at kreuzholzen.de  Fri Apr  4 21:28:36 2008
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Fri, 4 Apr 2008 21:28:36 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>
References: <47F6285F.2040807@coresystems.de>
	<20080404182855.23044.qmail@stuge.se>
	<e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>
Message-ID: <200804042128.37199.juergen127@kreuzholzen.de>

On Friday 04 April 2008 20:43, Ed Swierk wrote:
> On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
> >  Also there is crossdev and just plain Gentoo, either just vanilla
> >  binutils ebuilds or even catalyst for a complete custom system build.
>
> And buildroot and LFS and lots of others too. I'm not knocking any of
> those, but they are more complex than what I was looking for. My
> 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
> binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.

What about a reference toolchain everybody can build on his host and use to 
compile coreboot? I believe we will out of luck to support every toolchain on 
this planet.

Juergen



From jordan at chalmers.se  Fri Apr  4 21:31:38 2008
From: jordan at chalmers.se (Ulf Jordan)
Date: Fri, 4 Apr 2008 21:31:38 +0200 (CEST)
Subject: [coreboot] [PATCH] Add subversion number
In-Reply-To: <20080404155218.24792.qmail@stuge.se>
References: <47F59BC7.2090908@coresystems.de>
	<20080404032446.GA16511@localdomain>
	<20080404085637.22591.qmail@stuge.se>
	<20080404122531.GA14205@greenwood>
	<20080404155218.24792.qmail@stuge.se>
Message-ID: <Pine.LNX.4.63.0804042030080.743@elfpc10.elmagn.chalmers.se>

On Fri, 4 Apr 2008, Peter Stuge wrote:

> On Fri, Apr 04, 2008 at 02:25:31PM +0200, Uwe Hermann wrote:
>> On Fri, Apr 04, 2008 at 10:56:37AM +0200, Peter Stuge wrote:
>>> I really like this idea but the patch depends on svn being installed
>>> to build properly.

Yes, that was (partially) discussed [1] in the thread leading up to the 
original implementation for superiotool.

>> Yes, but I think it would be ok if we use "unknown" or "0" or something
>> like that if svn is not available
>
> For tarballs that we make available I don't like that so much.
> It is very useful information to have in debug logs.

True, that would be nice. However it is non-trivial to automatically get a 
more *accurate* (fallback) revision number in a non-subversion 
environment.

The needed information is lost when the tarball is generated, e.g. by 
viewvc. Extracting and preserving that information on the fly looks 
cumbersome (would neccessitate changes to viewvc and whatever generates 
the snapshots at qa.coreboot.org)

OTOH, using a not-so-accurate fallback like "unknown" or "0" (possibly 
even the revision number of the Makefile) looks perfectly tractable: 
substitute the fallback when the output from the svnversion pipeline is 
empty.

>> (haven't tried what happens currently).
>
> I expect it to just be blank.

Yes (I have seen some superiotool dumps like that on the list).


Also note that the patch at the start of this thread is based on the 
superiotool/flashrom code, which does not recurse into subdirectories [2]. 
A subdirectory aware pipeline is available in [3].


[1] http://www.coreboot.org/pipermail/coreboot/2007-October/025606.html
[2] http://www.coreboot.org/pipermail/coreboot/2007-October/025630.html
[3] http://www.coreboot.org/pipermail/coreboot/2007-October/026139.html


/ulf



From mylesgw at gmail.com  Fri Apr  4 21:34:08 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 4 Apr 2008 13:34:08 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <200804042128.37199.juergen127@kreuzholzen.de>
References: <47F6285F.2040807@coresystems.de><20080404182855.23044.qmail@stuge.se><e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>
	<200804042128.37199.juergen127@kreuzholzen.de>
Message-ID: <04d501c8968a$da789d10$1a02a8c0@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Juergen Beisert
> Sent: Friday, April 04, 2008 1:29 PM
> To: linuxbios at linuxbios.org
> Cc: Ed Swierk; coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH] fix stage0_i586.S in v3
> 
> On Friday 04 April 2008 20:43, Ed Swierk wrote:
> > On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
> > >  Also there is crossdev and just plain Gentoo, either just vanilla
> > >  binutils ebuilds or even catalyst for a complete custom system build.
> >
> > And buildroot and LFS and lots of others too. I'm not knocking any of
> > those, but they are more complex than what I was looking for. My
> > 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
> > binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.
> 
> What about a reference toolchain everybody can build on his host and use
> to
> compile coreboot? I believe we will out of luck to support every toolchain
> on
> this planet.

I think it is nicer to have a black list.  Hopefully the build succeeds in
more instances than it fails.  Otherwise we might pick a reference toolchain
that turns out to have bugs later.

Myles




From stepan at coresystems.de  Fri Apr  4 22:02:06 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 14:02:06 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <17ca70155e87083344f089081d506062@kernel.crashing.org>
References: <47F5952F.1060803@coresystems.de>	<47F5C4F4.6030205@gmx.net>	<47F6285F.2040807@coresystems.de>	<47F63AD9.7060909@gmx.net>	<47F63BF1.4010100@coresystems.de>	<47F64110.7010602@gmx.net>	<47F64FE1.6050306@coresystems.de>	<47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net>
	<17ca70155e87083344f089081d506062@kernel.crashing.org>
Message-ID: <47F6893E.2060405@coresystems.de>

Segher Boessenkool wrote:
>>>> Do you have any patch which would help me reproduce the issue? The v3
>>>> tree currently lacks a target using the code in question.
>>>>
>>>>
>>> Not at all. Just build the Qemu target with a freshly checked out tree
>>> and an official version of binutils from gnu.org
>>
>> By the way, IIRC Segher once wrote that binutils from gnu.org are a
>> completely different beast compared to "linux binutils" shipped by
>> almost all distributors.
>
> Not a "completely different beast", but please do us a favour and try
> with FSF binutils before reporting problems :-)

Hello, Segher,

I am reporting with FSF binutils, because using non-FSF linux specific 
binutils is currently not an option here.
I want coreboot to compile with the FSF version of binutils, hence the 
patch to v3 I sent yesterday.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From segher at kernel.crashing.org  Fri Apr  4 22:08:38 2008
From: segher at kernel.crashing.org (Segher Boessenkool)
Date: Fri, 4 Apr 2008 22:08:38 +0200
Subject: [coreboot] r3213 - trunk/payloads/libpayload/include
In-Reply-To: <200804041317.m34DH62V010825@gate.crashing.org>
References: <200804041317.m34DH62V010825@gate.crashing.org>
Message-ID: <19113cbb7f8f940855a449c9110bdb7e@kernel.crashing.org>

> +#define BIN2HEX(b) ("0123456789abcdef"[b & 15])
> +#define HEX2BIN(h) (('0' <= h && h <= '9') ? (h - '0') : \
> +                    ('a' <= h && h <= 'f') ? (h - 'a' + 10) : 0)

These macros are unsafe: lack of parentheses around the uses of
the parameters, and multiple evaluation in the second macro.

Please consider using an inline function instead (or a "real"
function, to make code size smaller).

Btw, could the SVN checkin list be set up with a followup-to: header?


Segher




From stepan at coresystems.de  Fri Apr  4 22:14:12 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 14:14:12 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <200804042128.37199.juergen127@kreuzholzen.de>
References: <47F6285F.2040807@coresystems.de>	<20080404182855.23044.qmail@stuge.se>	<e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>
	<200804042128.37199.juergen127@kreuzholzen.de>
Message-ID: <47F68C14.4070102@coresystems.de>

Juergen Beisert wrote:
> On Friday 04 April 2008 20:43, Ed Swierk wrote:
>   
>> On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
>>     
>>>  Also there is crossdev and just plain Gentoo, either just vanilla
>>>  binutils ebuilds or even catalyst for a complete custom system build.
>>>       
>> And buildroot and LFS and lots of others too. I'm not knocking any of
>> those, but they are more complex than what I was looking for. My
>> 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
>> binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.
>>     
>
> What about a reference toolchain everybody can build on his host and use to 
> compile coreboot? I believe we will out of luck to support every toolchain on 
> this planet.
>
> Juergen
>
>   
Yes. It will end up in something like this.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From stepan at coresystems.de  Fri Apr  4 22:14:12 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 14:14:12 -0600
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <200804042128.37199.juergen127@kreuzholzen.de>
References: <47F6285F.2040807@coresystems.de>	<20080404182855.23044.qmail@stuge.se>	<e6c711510804041143g5153e491id167c0cf40a056d8@mail.gmail.com>
	<200804042128.37199.juergen127@kreuzholzen.de>
Message-ID: <47F68C14.4070102@coresystems.de>

Juergen Beisert wrote:
> On Friday 04 April 2008 20:43, Ed Swierk wrote:
>   
>> On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
>>     
>>>  Also there is crossdev and just plain Gentoo, either just vanilla
>>>  binutils ebuilds or even catalyst for a complete custom system build.
>>>       
>> And buildroot and LFS and lots of others too. I'm not knocking any of
>> those, but they are more complex than what I was looking for. My
>> 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
>> binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.
>>     
>
> What about a reference toolchain everybody can build on his host and use to 
> compile coreboot? I believe we will out of luck to support every toolchain on 
> this planet.
>
> Juergen
>
>   
Yes. It will end up in something like this.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From stepan at coresystems.de  Fri Apr  4 22:15:53 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 14:15:53 -0600
Subject: [coreboot] stage0_i586.S Try 2
Message-ID: <47F68C79.5040603@coresystems.de>

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From peter at stuge.se  Fri Apr  4 22:18:04 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 22:18:04 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <47F67AA6.80805@gmx.net>
References: <47F63BF1.4010100@coresystems.de> <47F64110.7010602@gmx.net>
	<47F64FE1.6050306@coresystems.de> <47F65C85.7060204@gmx.net>
	<47F66030.5070800@gmx.net> <47F66A3A.3030801@coresystems.de>
	<47F66B43.5010009@gmx.net>
	<e6c711510804041107k7d7241a6p6819d98df2284ce9@mail.gmail.com>
	<20080404182855.23044.qmail@stuge.se> <47F67AA6.80805@gmx.net>
Message-ID: <20080404201804.6900.qmail@stuge.se>

On Fri, Apr 04, 2008 at 08:59:50PM +0200, Carl-Daniel Hailfinger wrote:
> Can all of you please try to build the qemu target in v3 (preferably
> svn HEAD)?

654 builds here. Gentoo with binutils-2.18-r1 which means

mirror://kernel/linux/devel/binutils/binutils-2.18.tar.bz2
mirror://kernel/linux/devel/binutils/test/binutils-2.18.tar.bz2
mirror://gnu/binutils/binutils-2.18.tar.bz2

plus

http://dev.gentoo.org/~vapier/dist/binutils-2.18-patches-1.5.tar.bz2


If I understood Segher correctly those three binutils-2.18.tar.bz2
are not exactly the same? Strange!


//Peter



From nathanael at gnat.ca  Fri Apr  4 22:17:45 2008
From: nathanael at gnat.ca (Nathanael D. Noblet)
Date: Fri, 04 Apr 2008 14:17:45 -0600
Subject: [coreboot] Offtopic - Request for opinions...
Message-ID: <47F68CE9.9070708@gnat.ca>

Hello,
   Long time lurker, and old time attempter... (waay back in v1 with an 
sis 535 or something like that)...  Anyway, I have a project that our 
company may be undertaking and some of it relies on instant on / small 
form factor computers. Think kiosk type system. We'll be running linux, 
custom built or one of the super small distros, built to run off a CF 
card or boot off the network. Here's where I've got some questions that 
I imagine people on this list may have some expertise.

   We'd hope to have something that has hardware accelerated graphics 
capabilities (likely using DirectFB for graphics) so something that has 
linux drivers would be a major plus. We'd potentially like to use more 
than one monitor per device. We don't need many of the common parts on a 
regular PC or mini-ITX type boards, but are wondering what kind of 
company you would approach to get something like that built. We'd like 
to have coreboot as the bios to help with boot times etc. If you were 
looking for something like that, where would you go? Most of the miniITX 
  boards don't quite fit the need. I'm wondering what volumes you'd need 
for a custom board to reach that same price, considering we'd really 
have very little on the device, cpu, ram, cf, video and a network. Which 
   I guess describes almost all computers... Anyway, pointers on where 
to purchase, or get a board developed that could do stuff like this. 
We've initially contemplated the Via boards, but have seen that there 
are more and more offerings out there. The Geode based systems could be 
fine if there was hardware assistance for the graphics we imagine... 
Anyway, any pointers on a stuff like this would be appreciated.

-- 
Nathanael D. Noblet



From juergen127 at kreuzholzen.de  Fri Apr  4 22:22:30 2008
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Fri, 4 Apr 2008 22:22:30 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <04d501c8968a$da789d10$1a02a8c0@chimp>
References: <47F6285F.2040807@coresystems.de>
	<200804042128.37199.juergen127@kreuzholzen.de>
	<04d501c8968a$da789d10$1a02a8c0@chimp>
Message-ID: <200804042222.31273.juergen127@kreuzholzen.de>

On Friday 04 April 2008 21:34, Myles Watson wrote:
> > -----Original Message-----
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Juergen Beisert
> > Sent: Friday, April 04, 2008 1:29 PM
> > To: linuxbios at linuxbios.org
> > Cc: Ed Swierk; coreboot at coreboot.org
> > Subject: Re: [coreboot] [PATCH] fix stage0_i586.S in v3
> >
> > On Friday 04 April 2008 20:43, Ed Swierk wrote:
> > > On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
> > > >  Also there is crossdev and just plain Gentoo, either just vanilla
> > > >  binutils ebuilds or even catalyst for a complete custom system
> > > > build.
> > >
> > > And buildroot and LFS and lots of others too. I'm not knocking any of
> > > those, but they are more complex than what I was looking for. My
> > > 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
> > > binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.
> >
> > What about a reference toolchain everybody can build on his host and use
> > to
> > compile coreboot? I believe we will out of luck to support every
> > toolchain on
> > this planet.
>
> I think it is nicer to have a black list.  Hopefully the build succeeds in
> more instances than it fails.  Otherwise we might pick a reference
> toolchain that turns out to have bugs later.

But it's easier to fix. You fix one reference toolchain and make everyone 
happy.

Black lists only gets bigger and bigger...

Juergen



From juergen127 at kreuzholzen.de  Fri Apr  4 22:22:30 2008
From: juergen127 at kreuzholzen.de (Juergen Beisert)
Date: Fri, 4 Apr 2008 22:22:30 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <04d501c8968a$da789d10$1a02a8c0@chimp>
References: <47F6285F.2040807@coresystems.de>
	<200804042128.37199.juergen127@kreuzholzen.de>
	<04d501c8968a$da789d10$1a02a8c0@chimp>
Message-ID: <200804042222.31273.juergen127@kreuzholzen.de>

On Friday 04 April 2008 21:34, Myles Watson wrote:
> > -----Original Message-----
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Juergen Beisert
> > Sent: Friday, April 04, 2008 1:29 PM
> > To: linuxbios at linuxbios.org
> > Cc: Ed Swierk; coreboot at coreboot.org
> > Subject: Re: [coreboot] [PATCH] fix stage0_i586.S in v3
> >
> > On Friday 04 April 2008 20:43, Ed Swierk wrote:
> > > On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
> > > >  Also there is crossdev and just plain Gentoo, either just vanilla
> > > >  binutils ebuilds or even catalyst for a complete custom system
> > > > build.
> > >
> > > And buildroot and LFS and lots of others too. I'm not knocking any of
> > > those, but they are more complex than what I was looking for. My
> > > 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
> > > binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.
> >
> > What about a reference toolchain everybody can build on his host and use
> > to
> > compile coreboot? I believe we will out of luck to support every
> > toolchain on
> > this planet.
>
> I think it is nicer to have a black list.  Hopefully the build succeeds in
> more instances than it fails.  Otherwise we might pick a reference
> toolchain that turns out to have bugs later.

But it's easier to fix. You fix one reference toolchain and make everyone 
happy.

Black lists only gets bigger and bigger...

Juergen



From peter at stuge.se  Fri Apr  4 22:23:25 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 22:23:25 +0200
Subject: [coreboot] stage0_i586.S Try 2
In-Reply-To: <47F68C79.5040603@coresystems.de>
References: <47F68C79.5040603@coresystems.de>
Message-ID: <20080404202325.9273.qmail@stuge.se>

On Fri, Apr 04, 2008 at 02:15:53PM -0600, Stefan Reinauer wrote:
> -	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
> -	extractmask gas_bug_workaround, %eax
> -	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
> -	extractmask gas_bug_workaround, %edx
> -/* Without the gas bug workaround, the entire macro would consist only of the
> - * two lines below.
> -	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
> -	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
> - */
> +	extractmask (((\carsize - \windowoffset) >> 12 ) - 4), %eax
> +	extractmask (((\carsize - \windowoffset) >> 12 )), %edx

Builds here, but others who have had problems should test too.

I would like a short comment above this that outlines the problem and
explains why >> is the solution.


//Peter



From peter at stuge.se  Fri Apr  4 22:41:27 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 4 Apr 2008 22:41:27 +0200
Subject: [coreboot] Offtopic - Request for opinions...
In-Reply-To: <47F68CE9.9070708@gnat.ca>
References: <47F68CE9.9070708@gnat.ca>
Message-ID: <20080404204127.16392.qmail@stuge.se>

On Fri, Apr 04, 2008 at 02:17:45PM -0600, Nathanael D. Noblet wrote:
> We'd hope to have something that has hardware accelerated graphics 
> capabilities (likely using DirectFB for graphics) so something that has 
> linux drivers would be a major plus.

So far the spec is standard stuff.


> We'd potentially like to use more than one monitor per device.

This is not so common however.


> We don't need many of the common parts on a regular PC or mini-ITX
> type boards, but are wondering what kind of company you would
> approach to get something like that built.

I have a few suggestions here in Sweden, but that may not help you.


> We'd like to have coreboot as the bios to help with boot times etc.
> If you were looking for something like that, where would you go?
> Most of the miniITX boards don't quite fit the need. I'm wondering
> what volumes you'd need for a custom board to reach that same
> price

10k would be my optimistic guesstimate.


> We've initially contemplated the Via boards, but have seen that
> there are more and more offerings out there. The Geode based
> systems could be fine if there was hardware assistance for the
> graphics we imagine...

I think your graphics requirements will be the dealmaker/breaker.

I don't know any integrated graphics with multiple independent
outputs. There is TV out but I guess that's not what you're after.

What kind of acceleration do you need? 2d primitives like blitting
and scaling or 3d stuff? Pixel shaders? Etc? DirectFB doesn't
do much 3d AFAIK, and they don't seem to have support for very many
of the most recent graphics chipsets.

Perhaps you could use NVIDIA+nouveau on X.


For smaller series I would try to create a solution using standard
components, some mobo and a discrete graphics card. Maybe even USB.

If you have the volume then talk to a graphics chip vendor about
modesetting without video BIOS and documentation for writing open
source drivers. Worst case they may not be able to help even if
they want to. :(


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  4 22:46:34 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 04 Apr 2008 22:46:34 +0200
Subject: [coreboot] stage0_i586.S Try 2
In-Reply-To: <47F68C79.5040603@coresystems.de>
References: <47F68C79.5040603@coresystems.de>
Message-ID: <47F693AA.6020509@gmx.net>

On 04.04.2008 22:15, Stefan Reinauer wrote:
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Could you try this whitespace-only change instead?

Preliminary version...

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: arch/x86/stage0_i586.S
===================================================================
--- arch/x86/stage0_i586.S	(Revision 654)
+++ arch/x86/stage0_i586.S	(Arbeitskopie)
@@ -319,14 +319,13 @@
  * windowoffset is the 32k-aligned window into CAR size
  */
 .macro simplemask carsize, windowoffset
-	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+	.set gas_bug_workaround,(((\carsize-\windowoffset)/0x1000)-4)
 	extractmask gas_bug_workaround, %eax
-	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+	.set gas_bug_workaround,(((\carsize-\windowoffset)/0x1000))
 	extractmask gas_bug_workaround, %edx
-/* Without the gas bug workaround, the entire macro would consist only of the
- * two lines below.
-	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
-	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+/* DO NOT CHANGE THE FORMATTING of the two lines below! It will break GNU as.
+	extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax
+	extractmask (((\carsize-\windowoffset)/0x1000)), %edx
  */
 .endm
 





From ward at gnu.org  Fri Apr  4 22:57:59 2008
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 4 Apr 2008 14:57:59 -0600
Subject: [coreboot] [PATCH] [buildrom] fix alix.1c build for v3
Message-ID: <20080404205759.GA19442@localdomain>

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator
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From jordan.crouse at amd.com  Fri Apr  4 23:12:38 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 4 Apr 2008 15:12:38 -0600
Subject: [coreboot] fix alix.1c build for v3
In-Reply-To: <20080404205759.GA19442@localdomain>
References: <20080404205759.GA19442@localdomain>
Message-ID: <20080404211238.GB21771@cosmic.amd.com>

On 04/04/08 14:57 -0600, Ward Vandewege wrote:
> -- 
> Ward Vandewege <ward at fsf.org>
> Free Software Foundation - Senior System Administrator

> 
> This fixes v3 build for alix.1c. Tested on real hardware.
> 
> Signed-off-by: Ward Vandewege <ward at gnu.org>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

> Index: config/platforms/alix1c.conf
> ===================================================================
> --- config/platforms/alix1c.conf	(revision 140)
> +++ config/platforms/alix1c.conf	(working copy)
> @@ -32,6 +32,8 @@
>  CBV2_TDIR=alix1c
>  CBV2_TAG=3079
>  
> +CBV3_TAG=638
> +
>  # FILO configuration
>  
>  FILO_CONFIG=alix1c-Config
> Index: Makefile
> ===================================================================
> --- Makefile	(revision 140)
> +++ Makefile	(working copy)
> @@ -79,10 +79,17 @@
>  
>  rom: $(HOSTTOOLS-y) payload $(COREBOOT-y)
>  	@ cp $(CBV3_OUTPUT) $(TARGET_ROM_FILE)
> -	@ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(PAYLOAD_TARGET):normal/payload
> +	@ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(CBV3_PAYLOAD_TARGET):normal/payload
> +ifeq ($(CONFIG_VSA_LEGACY),y)
> +	@ $(STAGING_DIR)/bin/lar -a $(TARGET_ROM_FILE) $(SOURCE_DIR)/amd_vsa_lx_1.01.bin:blob/vsa
> +endif
> +ifeq ($(CONFIG_VSA_OPENVSA),y)
> +	@ echo "Adding OpenVSA: TODO FIXME - let's actually implement this?"
> +endif
>  	@ for file in `ls $(ROM_DIR)`; do \
>  		$(STAGING_DIR)/bin/lar -a $(TARGET_ROM_FILE) $(ROM_DIR)/$$file:$$file; \
>  	done
> +	@ $(STAGING_DIR)/bin/lar -z $(TARGET_ROM_FILE)
>  endif
>  
>  payload: $(PAYLOAD_TARGET)
> Index: packages/filo/conf/alix1c-Config
> ===================================================================
> --- packages/filo/conf/alix1c-Config	(revision 0)
> +++ packages/filo/conf/alix1c-Config	(revision 0)
> @@ -0,0 +1,50 @@
> +# Use grub instead of autoboot?
> +USE_GRUB = 1
> +# Grub menu.lst path
> +MENULST_FILE = "hda1:/boot/grub/menu.lst"
> +# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus
> +IDE_DISK = 1
> +# Add a short delay when polling status registers
> +# (required on some broken SATA controllers)
> +IDE_DISK_POLL_DELAY = 1
> +# Driver for USB Storage
> +USB_DISK = 1
> +# VGA text console
> +VGA_CONSOLE = 1
> +PC_KEYBOARD = 1
> +# Enable the serial console
> +SERIAL_CONSOLE = 1
> +# Serial console; real external serial port
> +SERIAL_IOBASE = 0x3f8
> +SERIAL_SPEED = 115200
> +# Filesystems
> +FSYS_EXT2FS = 1
> +FSYS_ISO9660 = 1
> +# Support for boot disk image in bootable CD-ROM (El Torito)
> +ELTORITO = 1
> +# PCI support
> +SUPPORT_PCI = 1
> +# Enable this to scan PCI busses above bus 0
> +# AMD64 based boards do need this.
> +PCI_BRUTE_SCAN = 1
> +# Loader for standard Linux kernel image, a.k.a. /vmlinuz
> +LINUX_LOADER = 1
> +
> +# Debugging
> +#DEBUG_ALL = 1
> +#DEBUG_ELFBOOT = 1
> +#DEBUG_ELFNOTE = 1
> +#DEBUG_LINUXBIOS = 1
> +#DEBUG_MALLOC = 1
> +#DEBUG_MULTIBOOT = 1
> +#DEBUG_SEGMENT = 1
> +#DEBUG_SYS_INFO = 1
> +#DEBUG_TIMER = 1
> +#DEBUG_BLOCKDEV = 1
> +#DEBUG_PCI = 1
> +#DEBUG_VIA_SOUND = 1
> +#DEBUG_LINUXLOAD = 1
> +#DEBUG_IDE = 1
> +#DEBUG_USB = 1
> +#DEBUG_ELTORITO = 1
> +
> Index: packages/coreboot-v3/coreboot-v3.mk
> ===================================================================
> --- packages/coreboot-v3/coreboot-v3.mk	(revision 140)
> +++ packages/coreboot-v3/coreboot-v3.mk	(working copy)
> @@ -32,6 +32,12 @@
>  
>  CBV3_PATCHES ?=
>  
> +CBV3_PAYLOAD_TARGET=$(CBV3_DIR)/payload.elf
> +
> +$(CBV3_PAYLOAD_TARGET): $(PAYLOAD_TARGET)
> +	@ echo $(PAYLOAD_TARGET)
> +	@ cp $< $@
> +
>  $(SOURCE_DIR)/$(CBV3_TARBALL):
>  	@ mkdir -p $(SOURCE_DIR)/coreboot-v3
>  	@ $(BIN_DIR)/fetchsvn.sh $(CBV3_URL) \
> @@ -62,7 +68,7 @@
>  endif
>  	@ touch $@
>  
> -$(CBV3_OUTPUT): $(CBV3_STAMP_DIR)/.configured
> +$(CBV3_OUTPUT): $(CBV3_STAMP_DIR)/.configured $(CBV3_PAYLOAD_TARGET)
>  	@ echo "Building coreboot v3..."
>  	@ $(MAKE) -C $(CBV3_SRC_DIR) $(CBV3_ROM_SIZE) > $(CBV3_BUILD_LOG) 2>&1
>  

> -- 
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From joe at smittys.pointclark.net  Fri Apr  4 23:51:51 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Fri, 04 Apr 2008 17:51:51 -0400
Subject: [coreboot] GRUB 2 GSOC 2008 UHCI Support
Message-ID: <20080404175151.pucuk266g40cok4s@www.smittys.pointclark.net>

Some exciting news:-)
Looks like GRUB is looking at UHCI support for a GSOC 2008 project.  
Could this be used for coreboot's payload??

http://www.gnu.org/software/grub/grub-soc.html

Thanks - Joe



From jordan.crouse at amd.com  Sat Apr  5 00:03:40 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 4 Apr 2008 16:03:40 -0600
Subject: [coreboot] libpayload: Geode video console support
Message-ID: <20080404220340.GD21771@cosmic.amd.com>

As just demonstrated in Denver, support for mulitple video console
backends in libpayload, as well as Geode support for said video console
infrastructure.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.
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From jordan.crouse at amd.com  Sat Apr  5 00:11:00 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 4 Apr 2008 16:11:00 -0600
Subject: [coreboot] libpayload: gcc wrappers
Message-ID: <20080404221100.GE21771@cosmic.amd.com>

Continuing the parade of Denver patches, here is an implementation for
gcc wrappers for libpayload.

Jordan Crouse

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.
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From jordan.crouse at amd.com  Sat Apr  5 00:18:32 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 4 Apr 2008 16:18:32 -0600
Subject: [coreboot] libpayload: remove uneeded stack structures
Message-ID: <20080404221832.GF21771@cosmic.amd.com>

Following the cleanup of libpayload init, we had some uneeded
structures laying about.   This removes them.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.
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From jordan.crouse at amd.com  Sat Apr  5 00:45:18 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 4 Apr 2008 16:45:18 -0600
Subject: [coreboot] GRUB 2 GSOC 2008 UHCI Support
In-Reply-To: <20080404175151.pucuk266g40cok4s@www.smittys.pointclark.net>
References: <20080404175151.pucuk266g40cok4s@www.smittys.pointclark.net>
Message-ID: <20080404224518.GG21771@cosmic.amd.com>

On 04/04/08 17:51 -0400, joe at smittys.pointclark.net wrote:
> Some exciting news:-)
> Looks like GRUB is looking at UHCI support for a GSOC 2008 project.  
> Could this be used for coreboot's payload??
> 
> http://www.gnu.org/software/grub/grub-soc.html

Yes, assuming we can license it as something other then GPL.

> Thanks - Joe
> 
> -- 
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From svn at coreboot.org  Sat Apr  5 01:38:51 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  5 Apr 2008 01:38:51 +0200
Subject: [coreboot] r655 - coreboot-v3/util/xcompile
Message-ID: <mailman.1373.1355071296.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-04-05 01:38:51 +0200 (Sat, 05 Apr 2008)
New Revision: 655

Modified:
   coreboot-v3/util/xcompile/xcompile
Log:
fix i386-elf binutils weirdness. Thanks to Segher Boessenkool for finding this
out. (trivial)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: coreboot-v3/util/xcompile/xcompile
===================================================================
--- coreboot-v3/util/xcompile/xcompile	2008-04-04 14:49:50 UTC (rev 654)
+++ coreboot-v3/util/xcompile/xcompile	2008-04-04 23:38:51 UTC (rev 655)
@@ -82,7 +82,7 @@
 		fi
 		echo "CC_x86 := $CC"
 		echo "AR_x86 := i386-elf-ar"
-		echo "AS_x86 := i386-elf-as"
+		echo "AS_x86 := i386-elf-as --divide"
 		echo "LD_x86 := i386-elf-ld"
 		echo "NM_x86 := i386-elf-nm"
 		echo "OBJCOPY_x86 := i386-elf-objcopy"




From ward at gnu.org  Sat Apr  5 01:39:19 2008
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 4 Apr 2008 17:39:19 -0600
Subject: [coreboot] [PATCH] v3: add defconfig file for alix.1c
Message-ID: <20080404233919.GA5254@localdomain>

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator
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From c-d.hailfinger.devel.2006 at gmx.net  Sat Apr  5 01:51:38 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 05 Apr 2008 01:51:38 +0200
Subject: [coreboot] stage0_i586.S Try 2
In-Reply-To: <47F693AA.6020509@gmx.net>
References: <47F68C79.5040603@coresystems.de> <47F693AA.6020509@gmx.net>
Message-ID: <47F6BF0A.7070304@gmx.net>

On 04.04.2008 22:46, Carl-Daniel Hailfinger wrote:
> On 04.04.2008 22:15, Stefan Reinauer wrote:
>   
>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>     
>
> Could you try this whitespace-only change instead?
>   

Turns out this was not about whitespace, but the "/" character used in
the division was interpreted as a comment character if GNU as had been
compiled for an i*86-elf target (commonly seen on MacOSX).
Stefan committed a fix in r655.


Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Sat Apr  5 01:52:03 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 05 Apr 2008 01:52:03 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <200804042222.31273.juergen127@kreuzholzen.de>
References: <47F6285F.2040807@coresystems.de>	<200804042128.37199.juergen127@kreuzholzen.de>	<04d501c8968a$da789d10$1a02a8c0@chimp>
	<200804042222.31273.juergen127@kreuzholzen.de>
Message-ID: <47F6BF23.8090205@gmx.net>

On 04.04.2008 22:22, Juergen Beisert wrote:
> On Friday 04 April 2008 21:34, Myles Watson wrote:
>   
>>> -----Original Message-----
>>> From: coreboot-bounces at coreboot.org
>>> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Juergen Beisert
>>> Sent: Friday, April 04, 2008 1:29 PM
>>> To: linuxbios at linuxbios.org
>>> Cc: Ed Swierk; coreboot at coreboot.org
>>> Subject: Re: [coreboot] [PATCH] fix stage0_i586.S in v3
>>>
>>> On Friday 04 April 2008 20:43, Ed Swierk wrote:
>>>       
>>>> On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
>>>>         
>>>>>  Also there is crossdev and just plain Gentoo, either just vanilla
>>>>>  binutils ebuilds or even catalyst for a complete custom system
>>>>> build.
>>>>>           
>>>> And buildroot and LFS and lots of others too. I'm not knocking any of
>>>> those, but they are more complex than what I was looking for. My
>>>> 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
>>>> binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.
>>>>         
>>> What about a reference toolchain everybody can build on his host and use
>>> to
>>> compile coreboot? I believe we will out of luck to support every
>>> toolchain on
>>> this planet.
>>>       
>> I think it is nicer to have a black list.  Hopefully the build succeeds in
>> more instances than it fails.  Otherwise we might pick a reference
>> toolchain that turns out to have bugs later.
>>     
>
> But it's easier to fix. You fix one reference toolchain and make everyone 
> happy.
>
> Black lists only gets bigger and bigger...
>   

Turns out this was not about whitespace, but the "/" character used in
the division was interpreted as a comment character if GNU as had been
compiled for an i*86-elf target (commonly seen on MacOSX).
Stefan committed a fix in r655.


Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Sat Apr  5 01:52:03 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 05 Apr 2008 01:52:03 +0200
Subject: [coreboot] [PATCH] fix stage0_i586.S in v3
In-Reply-To: <200804042222.31273.juergen127@kreuzholzen.de>
References: <47F6285F.2040807@coresystems.de>	<200804042128.37199.juergen127@kreuzholzen.de>	<04d501c8968a$da789d10$1a02a8c0@chimp>
	<200804042222.31273.juergen127@kreuzholzen.de>
Message-ID: <47F6BF23.8090205@gmx.net>

On 04.04.2008 22:22, Juergen Beisert wrote:
> On Friday 04 April 2008 21:34, Myles Watson wrote:
>   
>>> -----Original Message-----
>>> From: coreboot-bounces at coreboot.org
>>> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Juergen Beisert
>>> Sent: Friday, April 04, 2008 1:29 PM
>>> To: linuxbios at linuxbios.org
>>> Cc: Ed Swierk; coreboot at coreboot.org
>>> Subject: Re: [coreboot] [PATCH] fix stage0_i586.S in v3
>>>
>>> On Friday 04 April 2008 20:43, Ed Swierk wrote:
>>>       
>>>> On Fri, Apr 4, 2008 at 11:28 AM, Peter Stuge <peter at stuge.se> wrote:
>>>>         
>>>>>  Also there is crossdev and just plain Gentoo, either just vanilla
>>>>>  binutils ebuilds or even catalyst for a complete custom system
>>>>> build.
>>>>>           
>>>> And buildroot and LFS and lots of others too. I'm not knocking any of
>>>> those, but they are more complex than what I was looking for. My
>>>> 50-line shell script (attached) builds a cross-compiling gcc (4.2.2) +
>>>> binutils (2.17) + uClibc (0.9.29) toolchain, nothing more.
>>>>         
>>> What about a reference toolchain everybody can build on his host and use
>>> to
>>> compile coreboot? I believe we will out of luck to support every
>>> toolchain on
>>> this planet.
>>>       
>> I think it is nicer to have a black list.  Hopefully the build succeeds in
>> more instances than it fails.  Otherwise we might pick a reference
>> toolchain that turns out to have bugs later.
>>     
>
> But it's easier to fix. You fix one reference toolchain and make everyone 
> happy.
>
> Black lists only gets bigger and bigger...
>   

Turns out this was not about whitespace, but the "/" character used in
the division was interpreted as a comment character if GNU as had been
compiled for an i*86-elf target (commonly seen on MacOSX).
Stefan committed a fix in r655.


Regards,
Carl-Daniel



From jordan.crouse at amd.com  Sat Apr  5 01:57:28 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 4 Apr 2008 17:57:28 -0600
Subject: [coreboot] v3: add defconfig file for alix.1c
In-Reply-To: <20080404233919.GA5254@localdomain>
References: <20080404233919.GA5254@localdomain>
Message-ID: <20080404235728.GH21771@cosmic.amd.com>

On 04/04/08 17:39 -0600, Ward Vandewege wrote:
> -- 
> Ward Vandewege <ward at fsf.org>
> Free Software Foundation - Senior System Administrator

> 
> We need a defconfig file for the alix.1c under v3.
> 
> Signed-off-by: Ward Vandewege <ward at gnu.org>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>
> Index: mainboard/pcengines/alix1c/defconfig
> ===================================================================
> --- mainboard/pcengines/alix1c/defconfig	(revision 0)
> +++ mainboard/pcengines/alix1c/defconfig	(revision 0)
> @@ -0,0 +1,102 @@
> +#
> +# Automatically generated make config: don't edit
> +# coreboot version: 3.0.0
> +# Sun Feb 24 11:45:09 2008
> +#
> +
> +#
> +# General setup
> +#
> +CONFIG_EXPERIMENTAL=y
> +CONFIG_EXPERT=y
> +CONFIG_LOCALVERSION=""
> +# CONFIG_BEEPS is not set
> +
> +#
> +# Mainboard
> +#
> +# CONFIG_VENDOR_ADL is not set
> +# CONFIG_VENDOR_AMD is not set
> +# CONFIG_VENDOR_ARTECGROUP is not set
> +# CONFIG_VENDOR_EMULATION is not set
> +CONFIG_VENDOR_PCENGINES=y
> +CONFIG_MAINBOARD_NAME="pcengines/alix1c"
> +CONFIG_BOARD_PCENGINES_ALIX1C=y
> +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
> +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
> +CONFIG_COREBOOT_ROMSIZE_KB_512=y
> +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
> +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
> +CONFIG_COREBOOT_ROMSIZE_KB=480
> +CONFIG_ARCH_X86=y
> +CONFIG_ARCH="x86"
> +CONFIG_CPU_AMD_GEODELX=y
> +CONFIG_OPTION_TABLE=y
> +CONFIG_PIRQ_TABLE=y
> +CONFIG_CARBASE=0x80000
> +CONFIG_CARSIZE=0x8000
> +
> +#
> +# Compression
> +#
> +CONFIG_COMPRESSION_LZMA=y
> +# CONFIG_COMPRESSION_NRV2B is not set
> +# CONFIG_DEFAULT_COMPRESSION_LZMA is not set
> +# CONFIG_DEFAULT_COMPRESSION_NRV2B is not set
> +CONFIG_DEFAULT_COMPRESSION_NONE=y
> +
> +#
> +# Console
> +#
> +CONFIG_CONSOLE=y
> +CONFIG_CONSOLE_LOGLEVEL_8=y
> +# CONFIG_CONSOLE_LOGLEVEL_7 is not set
> +# CONFIG_CONSOLE_LOGLEVEL_6 is not set
> +# CONFIG_CONSOLE_LOGLEVEL_5 is not set
> +# CONFIG_CONSOLE_LOGLEVEL_4 is not set
> +# CONFIG_CONSOLE_LOGLEVEL_3 is not set
> +# CONFIG_CONSOLE_LOGLEVEL_2 is not set
> +# CONFIG_CONSOLE_LOGLEVEL_1 is not set
> +# CONFIG_CONSOLE_LOGLEVEL_0 is not set
> +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
> +CONFIG_CONSOLE_SERIAL=y
> +CONFIG_CONSOLE_SERIAL_COM1=y
> +# CONFIG_CONSOLE_SERIAL_COM2 is not set
> +CONFIG_CONSOLE_SERIAL_115200=y
> +# CONFIG_CONSOLE_SERIAL_57600 is not set
> +# CONFIG_CONSOLE_SERIAL_38400 is not set
> +# CONFIG_CONSOLE_SERIAL_19200 is not set
> +# CONFIG_CONSOLE_SERIAL_9600 is not set
> +# CONFIG_CONSOLE_USB is not set
> +
> +#
> +# Cosmetic console options
> +#
> +# CONFIG_CONSOLE_PREFIX is not set
> +# CONFIG_CONSOLE_BUFFER is not set
> +
> +#
> +# Devices
> +#
> +CONFIG_PCI_OPTION_ROM_RUN=y
> +# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set
> +CONFIG_PCI_OPTION_ROM_RUN_VM86=y
> +# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set
> +# CONFIG_MULTIPLE_VGA_INIT is not set
> +# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set
> +
> +#
> +# Power management
> +#
> +CONFIG_NORTHBRIDGE_AMD_GEODELX=y
> +CONFIG_SOUTHBRIDGE_AMD_CS5536=y
> +CONFIG_SUPERIO_WINBOND_W83627HF=y
> +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32
> +
> +#
> +# Payload
> +#
> +CONFIG_PAYLOAD_PREPARSE_ELF=y
> +# CONFIG_PAYLOAD_ELF is not set
> +# CONFIG_PAYLOAD_NONE is not set
> +CONFIG_PAYLOAD_FILE="../payload.elf"

> -- 
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From stepan at coresystems.de  Sat Apr  5 02:08:43 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 18:08:43 -0600
Subject: [coreboot] stage0_i586.S Try 2
In-Reply-To: <47F6BF0A.7070304@gmx.net>
References: <47F68C79.5040603@coresystems.de> <47F693AA.6020509@gmx.net>
	<47F6BF0A.7070304@gmx.net>
Message-ID: <47F6C30B.1090807@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 04.04.2008 22:46, Carl-Daniel Hailfinger wrote:
>   
>> On 04.04.2008 22:15, Stefan Reinauer wrote:
>>   
>>     
>>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>>     
>>>       
>> Could you try this whitespace-only change instead?
>>   
>>     
>
> Turns out this was not about whitespace, but the "/" character used in
> the division was interpreted as a comment character if GNU as had been
> compiled for an i*86-elf target (commonly seen on MacOSX).
>   
Just as a side node: This has nothing to do with Mac OS X but was 
compiled from the GNU binutils sources. Mac OS X does not use ELF in any 
way.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Sat Apr  5 02:09:29 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  5 Apr 2008 02:09:29 +0200
Subject: [coreboot] r656 - coreboot-v3/mainboard/pcengines/alix1c
Message-ID: <mailman.1374.1355071296.16123.coreboot@coreboot.org>

Author: ward
Date: 2008-04-05 02:09:29 +0200 (Sat, 05 Apr 2008)
New Revision: 656

Added:
   coreboot-v3/mainboard/pcengines/alix1c/defconfig
Log:

We need a defconfig file for the alix.1c under v3.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Added: coreboot-v3/mainboard/pcengines/alix1c/defconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/defconfig	                        (rev 0)
+++ coreboot-v3/mainboard/pcengines/alix1c/defconfig	2008-04-05 00:09:29 UTC (rev 656)
@@ -0,0 +1,102 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version: 3.0.0
+# Sun Feb 24 11:45:09 2008
+#
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+# CONFIG_BEEPS is not set
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_ADL is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_EMULATION is not set
+CONFIG_VENDOR_PCENGINES=y
+CONFIG_MAINBOARD_NAME="pcengines/alix1c"
+CONFIG_BOARD_PCENGINES_ALIX1C=y
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_512=y
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=480
+CONFIG_ARCH_X86=y
+CONFIG_ARCH="x86"
+CONFIG_CPU_AMD_GEODELX=y
+CONFIG_OPTION_TABLE=y
+CONFIG_PIRQ_TABLE=y
+CONFIG_CARBASE=0x80000
+CONFIG_CARSIZE=0x8000
+
+#
+# Compression
+#
+CONFIG_COMPRESSION_LZMA=y
+# CONFIG_COMPRESSION_NRV2B is not set
+# CONFIG_DEFAULT_COMPRESSION_LZMA is not set
+# CONFIG_DEFAULT_COMPRESSION_NRV2B is not set
+CONFIG_DEFAULT_COMPRESSION_NONE=y
+
+#
+# Console
+#
+CONFIG_CONSOLE=y
+CONFIG_CONSOLE_LOGLEVEL_8=y
+# CONFIG_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_CONSOLE_SERIAL_COM1=y
+# CONFIG_CONSOLE_SERIAL_COM2 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+# CONFIG_CONSOLE_USB is not set
+
+#
+# Cosmetic console options
+#
+# CONFIG_CONSOLE_PREFIX is not set
+# CONFIG_CONSOLE_BUFFER is not set
+
+#
+# Devices
+#
+CONFIG_PCI_OPTION_ROM_RUN=y
+# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set
+CONFIG_PCI_OPTION_ROM_RUN_VM86=y
+# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set
+# CONFIG_MULTIPLE_VGA_INIT is not set
+# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set
+
+#
+# Power management
+#
+CONFIG_NORTHBRIDGE_AMD_GEODELX=y
+CONFIG_SOUTHBRIDGE_AMD_CS5536=y
+CONFIG_SUPERIO_WINBOND_W83627HF=y
+CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_PREPARSE_ELF=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_NONE is not set
+CONFIG_PAYLOAD_FILE="../payload.elf"




From ward at gnu.org  Sat Apr  5 02:11:01 2008
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 4 Apr 2008 18:11:01 -0600
Subject: [coreboot] v3: add defconfig file for alix.1c
In-Reply-To: <20080404235728.GH21771@cosmic.amd.com>
References: <20080404233919.GA5254@localdomain>
	<20080404235728.GH21771@cosmic.amd.com>
Message-ID: <20080405001101.GA5700@localdomain>

On Fri, Apr 04, 2008 at 05:57:28PM -0600, Jordan Crouse wrote:
> On 04/04/08 17:39 -0600, Ward Vandewege wrote:
> > -- 
> > Ward Vandewege <ward at fsf.org>
> > Free Software Foundation - Senior System Administrator
> 
> > 
> > We need a defconfig file for the alix.1c under v3.
> > 
> > Signed-off-by: Ward Vandewege <ward at gnu.org>
> 
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Thanks, r656.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From joe at smittys.pointclark.net  Sat Apr  5 02:15:25 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Fri, 04 Apr 2008 20:15:25 -0400
Subject: [coreboot] GRUB 2 GSOC 2008 UHCI Support
In-Reply-To: <20080404224518.GG21771@cosmic.amd.com>
References: <20080404175151.pucuk266g40cok4s@www.smittys.pointclark.net>
	<20080404224518.GG21771@cosmic.amd.com>
Message-ID: <20080404201525.qoq2hrsf4kok0840@www.smittys.pointclark.net>

Quoting Jordan Crouse <jordan.crouse at amd.com>:

> On 04/04/08 17:51 -0400, joe at smittys.pointclark.net wrote:
>> Some exciting news:-)
>> Looks like GRUB is looking at UHCI support for a GSOC 2008 project.
>> Could this be used for coreboot's payload??
>>
>> http://www.gnu.org/software/grub/grub-soc.html
>
> Yes, assuming we can license it as something other then GPL.
>
Not sure what you mean? Is all the GRUB2 code that Patrick Georgi  
worked on licensed with something other then GPL?


Thanks - Joe



From jordan.crouse at amd.com  Sat Apr  5 02:29:30 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 4 Apr 2008 18:29:30 -0600
Subject: [coreboot] GRUB 2 GSOC 2008 UHCI Support
In-Reply-To: <20080404201525.qoq2hrsf4kok0840@www.smittys.pointclark.net>
References: <20080404175151.pucuk266g40cok4s@www.smittys.pointclark.net>
	<20080404224518.GG21771@cosmic.amd.com>
	<20080404201525.qoq2hrsf4kok0840@www.smittys.pointclark.net>
Message-ID: <20080405002930.GI21771@cosmic.amd.com>

On 04/04/08 20:15 -0400, joe at smittys.pointclark.net wrote:
> Quoting Jordan Crouse <jordan.crouse at amd.com>:
>
>> On 04/04/08 17:51 -0400, joe at smittys.pointclark.net wrote:
>>> Some exciting news:-)
>>> Looks like GRUB is looking at UHCI support for a GSOC 2008 project.
>>> Could this be used for coreboot's payload??
>>>
>>> http://www.gnu.org/software/grub/grub-soc.html
>>
>> Yes, assuming we can license it as something other then GPL.
>>
> Not sure what you mean? Is all the GRUB2 code that Patrick Georgi worked on 
> licensed with something other then GPL?

If we want to use it with libpayload (which I assumed is what you were 
talking about), then it would need to be something other then GPL.

Jordan

>
> Thanks - Joe
>

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From stepan at coresystems.de  Sat Apr  5 02:34:20 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 04 Apr 2008 18:34:20 -0600
Subject: [coreboot] GRUB 2 GSOC 2008 UHCI Support
In-Reply-To: <20080404201525.qoq2hrsf4kok0840@www.smittys.pointclark.net>
References: <20080404175151.pucuk266g40cok4s@www.smittys.pointclark.net>	<20080404224518.GG21771@cosmic.amd.com>
	<20080404201525.qoq2hrsf4kok0840@www.smittys.pointclark.net>
Message-ID: <47F6C90C.1000707@coresystems.de>

joe at smittys.pointclark.net wrote:
> Quoting Jordan Crouse <jordan.crouse at amd.com>:
>
>   
>> On 04/04/08 17:51 -0400, joe at smittys.pointclark.net wrote:
>>     
>>> Some exciting news:-)
>>> Looks like GRUB is looking at UHCI support for a GSOC 2008 project.
>>> Could this be used for coreboot's payload??
>>>
>>> http://www.gnu.org/software/grub/grub-soc.html
>>>       
>> Yes, assuming we can license it as something other then GPL.
>>
>>     
> Not sure what you mean? Is all the GRUB2 code that Patrick Georgi  
> worked on licensed with something other then GPL?
>
>   
libpayload is BSD licensed.

Patrick is currently working on a BSD/GPL dual licensed USB stack for 
grub2/libpayload/...

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From joe at smittys.pointclark.net  Sat Apr  5 02:51:08 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Fri, 04 Apr 2008 20:51:08 -0400
Subject: [coreboot] GRUB 2 GSOC 2008 UHCI Support
In-Reply-To: <47F6C90C.1000707@coresystems.de>
References: <20080404175151.pucuk266g40cok4s@www.smittys.pointclark.net>
	<20080404224518.GG21771@cosmic.amd.com>
	<20080404201525.qoq2hrsf4kok0840@www.smittys.pointclark.net>
	<47F6C90C.1000707@coresystems.de>
Message-ID: <20080404205108.ivlc9js58xwcss84@www.smittys.pointclark.net>

Quoting Stefan Reinauer <stepan at coresystems.de>:

> joe at smittys.pointclark.net wrote:
>> Quoting Jordan Crouse <jordan.crouse at amd.com>:
>>
>>
>>> On 04/04/08 17:51 -0400, joe at smittys.pointclark.net wrote:
>>>
>>>> Some exciting news:-)
>>>> Looks like GRUB is looking at UHCI support for a GSOC 2008 project.
>>>> Could this be used for coreboot's payload??
>>>>
>>>> http://www.gnu.org/software/grub/grub-soc.html
>>>>
>>> Yes, assuming we can license it as something other then GPL.
>>>
>>>
>> Not sure what you mean? Is all the GRUB2 code that Patrick Georgi    
>> worked on licensed with something other then GPL?
>>
>>
> libpayload is BSD licensed.
>
> Patrick is currently working on a BSD/GPL dual licensed USB stack for
> grub2/libpayload/...
>
Cool, hopefully UHCI or even EHCI???

Thanks - Joe



From svn at coreboot.org  Sat Apr  5 03:07:28 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  5 Apr 2008 03:07:28 +0200
Subject: [coreboot] r3217 - in trunk/payloads/libpayload: . i386
Message-ID: <mailman.1375.1355071296.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-04-05 03:07:27 +0200 (Sat, 05 Apr 2008)
New Revision: 3217

Modified:
   trunk/payloads/libpayload/i386/head.S
   trunk/payloads/libpayload/i386/main.c
   trunk/payloads/libpayload/libpayload.ldscript
Log:
libpayload: remove unneeded stack stuff

Following on the previous code to streamline the libpayload init code,
this removes the now unneeded stack structures.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/payloads/libpayload/i386/head.S
===================================================================
--- trunk/payloads/libpayload/i386/head.S	2008-04-04 16:49:09 UTC (rev 3216)
+++ trunk/payloads/libpayload/i386/head.S	2008-04-05 01:07:27 UTC (rev 3217)
@@ -54,9 +54,9 @@
 	movl %esp, %esi
 
 	/* Setup new stack. */
-	movl _istack, %ebx
+	movl $_stack, %ebx
 
-	movl (%ebx), %esp
+	movl %ebx, %esp
 
 	/* Save old stack pointer. */
 	pushl %esi

Modified: trunk/payloads/libpayload/i386/main.c
===================================================================
--- trunk/payloads/libpayload/i386/main.c	2008-04-04 16:49:09 UTC (rev 3216)
+++ trunk/payloads/libpayload/i386/main.c	2008-04-05 01:07:27 UTC (rev 3217)
@@ -29,23 +29,6 @@
 
 #include <libpayload.h>
 
-/*
- * This structure seeds the stack. We provide the return address of our main
- * function, and further down, the address of the function that we call when
- * we leave and try to restore the original stack. At the very bottom of the
- * stack we store the original stack pointer from the calling application.
- */
-
-extern void _leave(void);
-
-static struct {
-	uint32_t esp;
-} initial_stack  __attribute__ ((section(".istack"))) = {
-	(uint32_t) &initial_stack,
-};
-
-void *_istack = &initial_stack;
-
 /**
  * This is our C entry function - set up the system
  * and jump into the payload entry point.

Modified: trunk/payloads/libpayload/libpayload.ldscript
===================================================================
--- trunk/payloads/libpayload/libpayload.ldscript	2008-04-04 16:49:09 UTC (rev 3216)
+++ trunk/payloads/libpayload/libpayload.ldscript	2008-04-05 01:07:27 UTC (rev 3217)
@@ -73,17 +73,12 @@
 		. = ALIGN(16);
 		_eheap = .;
 
-		_stack = .;
+		_estack = .;
 		. += STACK_SIZE;
 		. = ALIGN(16);
 		_stack = .;
 	}
 
-	/* Put the static bits of our inital stack at the bottom */
-	.istack : {
-		*(.istack)
-	}
-
 	_end = .;
 
 	/DISCARD/ : { *(.comment) *(.note) *(.note.*) }




From uwe at hermann-uwe.de  Sat Apr  5 03:08:29 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 5 Apr 2008 03:08:29 +0200
Subject: [coreboot] libpayload: remove uneeded stack structures
In-Reply-To: <20080404221832.GF21771@cosmic.amd.com>
References: <20080404221832.GF21771@cosmic.amd.com>
Message-ID: <20080405010829.GA28640@greenwood>

On Fri, Apr 04, 2008 at 04:18:32PM -0600, Jordan Crouse wrote:
> libpayload: remove unneeded stack stuff
> 
> Following on the previous code to sreamline the libpayload init code,
> this removes the now uneeded stack structures
> 
> Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>

Thanks, r3217. Tested in QEMU.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From svn at coreboot.org  Sat Apr  5 06:28:24 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  5 Apr 2008 06:28:24 +0200
Subject: [coreboot] r141 - in buildrom-devel: . config/platforms
	packages/coreboot-v3 packages/filo/conf packages/roms
Message-ID: <mailman.1376.1355071296.16123.coreboot@coreboot.org>

Author: ward
Date: 2008-04-05 06:28:24 +0200 (Sat, 05 Apr 2008)
New Revision: 141

Added:
   buildrom-devel/packages/filo/conf/alix1c-Config
Modified:
   buildrom-devel/Makefile
   buildrom-devel/config/platforms/alix1c.conf
   buildrom-devel/packages/coreboot-v3/coreboot-v3.mk
   buildrom-devel/packages/roms/roms.mk
Log:


This fixes v3 build for alix.1c. Tested on real hardware.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Modified: buildrom-devel/Makefile
===================================================================
--- buildrom-devel/Makefile	2008-03-29 18:22:02 UTC (rev 140)
+++ buildrom-devel/Makefile	2008-04-05 04:28:24 UTC (rev 141)
@@ -76,13 +76,25 @@
 else
 LAR_PAYLOAD_FLAGS=-a
 endif
+	
+ifeq ($(or $(CONFIG_VSA_LEGACY), $(CONFIG_VSA_OPENVSA)),)
+else
+OPTIONROM_TARGETS+=geodevsa
+endif
 
 rom: $(HOSTTOOLS-y) payload $(COREBOOT-y)
 	@ cp $(CBV3_OUTPUT) $(TARGET_ROM_FILE)
-	@ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(PAYLOAD_TARGET):normal/payload
+	@ $(STAGING_DIR)/bin/lar $(LAR_PAYLOAD_FLAGS) $(TARGET_ROM_FILE) $(CBV3_PAYLOAD_TARGET):normal/payload
+ifeq ($(CONFIG_VSA_LEGACY),y)
+	@ $(STAGING_DIR)/bin/lar -a $(TARGET_ROM_FILE) $(SOURCE_DIR)/amd_vsa_lx_1.01.bin:blob/vsa
+endif
+ifeq ($(CONFIG_VSA_OPENVSA),y)
+	@ echo "Adding OpenVSA: TODO FIXME - let's actually implement this?"
+endif
 	@ for file in `ls $(ROM_DIR)`; do \
 		$(STAGING_DIR)/bin/lar -a $(TARGET_ROM_FILE) $(ROM_DIR)/$$file:$$file; \
 	done
+	@ $(STAGING_DIR)/bin/lar -z $(TARGET_ROM_FILE)
 endif
 
 payload: $(PAYLOAD_TARGET)

Modified: buildrom-devel/config/platforms/alix1c.conf
===================================================================
--- buildrom-devel/config/platforms/alix1c.conf	2008-03-29 18:22:02 UTC (rev 140)
+++ buildrom-devel/config/platforms/alix1c.conf	2008-04-05 04:28:24 UTC (rev 141)
@@ -32,6 +32,8 @@
 CBV2_TDIR=alix1c
 CBV2_TAG=3079
 
+CBV3_TAG=656
+
 # FILO configuration
 
 FILO_CONFIG=alix1c-Config

Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk
===================================================================
--- buildrom-devel/packages/coreboot-v3/coreboot-v3.mk	2008-03-29 18:22:02 UTC (rev 140)
+++ buildrom-devel/packages/coreboot-v3/coreboot-v3.mk	2008-04-05 04:28:24 UTC (rev 141)
@@ -32,6 +32,12 @@
 
 CBV3_PATCHES ?=
 
+CBV3_PAYLOAD_TARGET=$(CBV3_DIR)/payload.elf
+
+$(CBV3_PAYLOAD_TARGET): $(PAYLOAD_TARGET)
+	@ echo $(PAYLOAD_TARGET)
+	@ cp $< $@
+
 $(SOURCE_DIR)/$(CBV3_TARBALL):
 	@ mkdir -p $(SOURCE_DIR)/coreboot-v3
 	@ $(BIN_DIR)/fetchsvn.sh $(CBV3_URL) \
@@ -62,7 +68,7 @@
 endif
 	@ touch $@
 
-$(CBV3_OUTPUT): $(CBV3_STAMP_DIR)/.configured
+$(CBV3_OUTPUT): $(CBV3_STAMP_DIR)/.configured $(CBV3_PAYLOAD_TARGET)
 	@ echo "Building coreboot v3..."
 	@ $(MAKE) -C $(CBV3_SRC_DIR) $(CBV3_ROM_SIZE) > $(CBV3_BUILD_LOG) 2>&1
 

Added: buildrom-devel/packages/filo/conf/alix1c-Config
===================================================================
--- buildrom-devel/packages/filo/conf/alix1c-Config	                        (rev 0)
+++ buildrom-devel/packages/filo/conf/alix1c-Config	2008-04-05 04:28:24 UTC (rev 141)
@@ -0,0 +1,50 @@
+# Use grub instead of autoboot?
+USE_GRUB = 1
+# Grub menu.lst path
+MENULST_FILE = "hda1:/boot/grub/menu.lst"
+# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus
+IDE_DISK = 1
+# Add a short delay when polling status registers
+# (required on some broken SATA controllers)
+IDE_DISK_POLL_DELAY = 1
+# Driver for USB Storage
+USB_DISK = 1
+# VGA text console
+VGA_CONSOLE = 1
+PC_KEYBOARD = 1
+# Enable the serial console
+SERIAL_CONSOLE = 1
+# Serial console; real external serial port
+SERIAL_IOBASE = 0x3f8
+SERIAL_SPEED = 115200
+# Filesystems
+FSYS_EXT2FS = 1
+FSYS_ISO9660 = 1
+# Support for boot disk image in bootable CD-ROM (El Torito)
+ELTORITO = 1
+# PCI support
+SUPPORT_PCI = 1
+# Enable this to scan PCI busses above bus 0
+# AMD64 based boards do need this.
+PCI_BRUTE_SCAN = 1
+# Loader for standard Linux kernel image, a.k.a. /vmlinuz
+LINUX_LOADER = 1
+
+# Debugging
+#DEBUG_ALL = 1
+#DEBUG_ELFBOOT = 1
+#DEBUG_ELFNOTE = 1
+#DEBUG_LINUXBIOS = 1
+#DEBUG_MALLOC = 1
+#DEBUG_MULTIBOOT = 1
+#DEBUG_SEGMENT = 1
+#DEBUG_SYS_INFO = 1
+#DEBUG_TIMER = 1
+#DEBUG_BLOCKDEV = 1
+#DEBUG_PCI = 1
+#DEBUG_VIA_SOUND = 1
+#DEBUG_LINUXLOAD = 1
+#DEBUG_IDE = 1
+#DEBUG_USB = 1
+#DEBUG_ELTORITO = 1
+

Modified: buildrom-devel/packages/roms/roms.mk
===================================================================
--- buildrom-devel/packages/roms/roms.mk	2008-03-29 18:22:02 UTC (rev 140)
+++ buildrom-devel/packages/roms/roms.mk	2008-04-05 04:28:24 UTC (rev 141)
@@ -2,7 +2,7 @@
 # here
 
 
-OPTIONROM_TARGETS=
+OPTIONROM_TARGETS?=
 
 OPTIONROM-y =
 OPTIONROM-$(CONFIG_PLATFORM_NORWICH) += rom-geode.inc




From ward at gnu.org  Sat Apr  5 08:29:38 2008
From: ward at gnu.org (Ward Vandewege)
Date: Sat, 5 Apr 2008 00:29:38 -0600
Subject: [coreboot] fix alix.1c build for v3
In-Reply-To: <20080404211238.GB21771@cosmic.amd.com>
References: <20080404205759.GA19442@localdomain>
	<20080404211238.GB21771@cosmic.amd.com>
Message-ID: <20080405062938.GA21348@localdomain>

On Fri, Apr 04, 2008 at 03:12:38PM -0600, Jordan Crouse wrote:
> On 04/04/08 14:57 -0600, Ward Vandewege wrote:
> > -- 
> > Ward Vandewege <ward at fsf.org>
> > Free Software Foundation - Senior System Administrator
> 
> > 
> > This fixes v3 build for alix.1c. Tested on real hardware.
> > 
> > Signed-off-by: Ward Vandewege <ward at gnu.org>
> 
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Commited with two small additional changes: bumpted up v3 revision to have
the mainboard/pcengines/alix.1c/defconfig available, and added a check to
download the vsa if it's not available.

r141

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator



From malateshkamat at gmail.com  Sat Apr  5 08:55:33 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Sat, 5 Apr 2008 12:25:33 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804040625wb01013vd941cd25fb274bba@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
	<dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
	<fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>
	<dd3c80060804040559h4b7510b1q7747f44e897fa4da@mail.gmail.com>
	<fa70bcc0804040625wb01013vd941cd25fb274bba@mail.gmail.com>
Message-ID: <fa70bcc0804042355w2f1b42c7q42f755b58eb48d9c@mail.gmail.com>

Hello,
  But the content after writing by using  below command shows result like
this....

[root at localhost ~]# /usr/local/sbin/flashrom -r | hexdump

0000000 6143 696c 7262 7461 6e69 2067 6564 616c
0000010 2079 6f6c 706f 2e2e 202e 4b4f 0a2e 6f4e
0000020 6320 726f 6265 6f6f 2074 6174 6c62 2065
0000030 6f66 6e75 2e64 460a 756f 646e 6320 6968
0000040 7370 7465 2220 4956 2041 5456 3238 3733
0000050 2c22 6520 616e 6c62 6e69 2067 6c66 7361
0000060 2068 7277 7469 2e65 2e2e 4f20 2e4b 530a
0000070 5453 3934 464c 3030 4134 422f 6620 756f
0000080 646e 6120 2074 6870 7379 6369 6c61 6120
0000090 6464 6572 7373 3020 6678 6666 3038 3030
00000a0 2e30 460a 616c 6873 7020 7261 2074 7369
00000b0 5320 5453 3934 464c 3030 4134 422f 2820
00000c0 3135 2032 424b 2e29 450a 7272 726f 203a
00000d0 6f4e 6620 6c69 6e65 6d61 2065 7073 6365
00000e0 6669 6569 2e64 000a
00000e7

************************************
  But using only hexdump i got result like this ...

[root at localhost ~]# hexdump sst_after_write05.bin
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0080000

Thanks.
Malatesh

On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
>
> Ya .. after checking that file i got result like this ...it shows that
> there is a content in that file
>
> [root at localhost ~]# hexdump sst_after_erase.bin
> 0000000 ffff ffff ffff ffff ffff ffff ffff ffff
> *
> 0080000
>
>   I think erasing is not happened properly..
>
> Thanks..
> malatesh
>
> On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
> >
> > Ok, so if you open up the sst_after_erase.bin with a hex editor, is
> > there anything in it? Does that match the data from the diff, or is it a
> > binary ORing of the data from the diff? Do you have any other flash chips
> > you can try on the board?
> >
> > On Fri, Apr 4, 2008 at 8:41 AM, malatesh kamatad <
> > malateshkamat at gmail.com> wrote:
> >
> > >  Ya i got result like this after comparing
> > >
> > >   [root at localhost ~]# diff -us original.bin sst_after_write.bin
> > > Binary files original.bin and sst_after_write.bin differ
> > >
> > >    but its showing that there is a difference in between to files ....
> > >
> > >   i think write is not happening proper ....
> > >
> > > Thanks .
> > > malatesh
> > >
> > >
> > > On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
> > > >
> > > > what's the output of diff -us original.bin sst_after_write.bin? Can
> > > > you download the bios from the manufacturer and see if flashing that works?
> > > >
> > > > -Corey
> > > >
> > > > On Fri, Apr 4, 2008 at 7:03 AM, malatesh kamatad <
> > > > malateshkamat at gmail.com> wrote:
> > > >
> > > > >    I worked with the step by step this is the output......
> > > > >
> > > > > [root at localhost ~]# flashrom -r original.bin
> > > > > Calibrating delay loop... OK.
> > > > > No coreboot table found.
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > Pm49FL004 found at physical address 0xfff80000.
> > > > > Flash part is Pm49FL004 (512 KB).
> > > > > Reading Flash...done
> > > > >
> > > > > [root at localhost ~]# flashrom -E
> > > > > Calibrating delay loop... OK.
> > > > > No coreboot table found.
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > Erasing flash chip
> > > > >
> > > > > [root at localhost ~]# flashrom -r sst_after_erase.bin
> > > > > Calibrating delay loop... OK.
> > > > > No coreboot table found.
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > Reading Flash...done
> > > > >
> > > > > [root at localhost ~]# flashrom -w original.bin
> > > > > Calibrating delay loop... OK.
> > > > > No coreboot table found.
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > > Programming page: 0007 at address: 0x00070000
> > > > >
> > > > > [root at localhost ~]# flashrom -r sst_after_write.bin
> > > > > Calibrating delay loop... OK.
> > > > > No coreboot table found.
> > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > Reading Flash...done
> > > > >
> > > > > Thanks,
> > > > > Malatesh.
> > > > >
> > > > > On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
> > > > > >
> > > > > > Hi..
> > > > > >
> > > > > >          We are having two BIOS i.e, PM49FL004( motherboard's
> > > > > > BIOS) and empty flashrom
> > > > > >
> > > > > >         SST49LF004B ..
> > > > > >
> > > > > >        We are trying to flash the content of PM49FL004 to
> > > > > > SST49LF004B flashrom
> > > > > >
> > > > > >         according to your suggestion we have done ..we are
> > > > > > getting output  as bellow..
> > > > > >
> > > > > >
> > > > > >
> > > > > > [root at localhost ~]# flashrom -E
> > > > > >
> > > > > > Calibrating delay loop... OK.
> > > > > >
> > > > > > No coreboot table found.
> > > > > >
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > >
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > >
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > >
> > > > > > Erasing flash chip
> > > > > >
> > > > > > Erasing page: 0007 at address: 0x00070000
> > > > > >
> > > > > > [root at localhost ~]# flashrom -r malateh.bin
> > > > > >
> > > > > > Calibrating delay loop... OK.
> > > > > >
> > > > > > No coreboot table found.
> > > > > >
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > >
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > >
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > >
> > > > > > Reading Flash...done
> > > > > >
> > > > > > [root at localhost ~]# flashrom -w malateh.bin
> > > > > >
> > > > > > Calibrating delay loop... OK.
> > > > > >
> > > > > > No coreboot table found.
> > > > > >
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > >
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > >
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > >
> > > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > > >
> > > > > > Programming page: 0007 at address: 0x00070000
> > > > > >
> > > > > > [root at localhost ~]# flashrom -v malateh.bin
> > > > > >
> > > > > > Calibrating delay loop... OK.
> > > > > >
> > > > > > No coreboot table found.
> > > > > >
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > >
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > >
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > >
> > > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > > >
> > > > > > Verifying flash... VERIFIED.
> > > > > >
> > > > > >
> > > > > >  After that we tried to boot the system by SST49lf004B but
> > > > > > system is not rebooting....
> > > > > >
> > > > > > So we want to flash the content of the Pm49fl004 to SST49lf004
> > > > > > so that our system can boot
> > > > > >
> > > > > > using SST49lf004....
> > > > > >
> > > > > > thanks,
> > > > > > Malatesh..
> > > > > >
> > > > > >
> > > > > > On 04/04/2008, bari <bari at onelabs.com> wrote:
> > > > > > >
> > > > > > > Try Peters suggestion of reading the flash after an erase and
> > > > > > > see what is there.
> > > > > > >
> > > > > > > If it is erased, read back after you have tried to write and
> > > > > > > compare.
> > > > > > >
> > > > > > > See what is or is not happening.
> > > > > > >
> > > > > > > -Bari
> > > > > > >
> > > > > > > malatesh kamatad wrote:
> > > > > > >
> > > > > > > > Hi...
> > > > > > > >       I am working on ASRock motherboard .....in FWH mode...
> > > > > > > >
> > > > > > > > with regards.
> > > > > > > > Malatesh
> > > > > > > >
> > > > > > > > On 03/04/2008, *bari* <bari at onelabs.com <mailto:
> > > > > > > > bari at onelabs.com>> wrote:
> > > > > > > >
> > > > > > > >    malatesh kamatad wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >        Hi all..
> > > > > > > >              I have worked with PM49fl00x.diff patch ,its
> > > > > > > > worked fine
> > > > > > > >        and i got the output as below
> > > > > > > >
> > > > > > > >    The PM49fl00x can work in LPC and FWH modes. Do you know
> > > > > > > > which
> > > > > > > >    mode is being used?
> > > > > > > >    What mainboard did you test this in?
> > > > > > > >
> > > > > > > >                           Now i am working on SST49LF004B
> > > > > > > >                                        33-4C-NHE
> > > > > > > >                                          0710022-CA   with
> > > > > > > > the
> > > > > > > >         motherboard  K8Upgrade-VM800
> > > > > > > >                         The flashrom detect flash device on
> > > > > > > > this
> > > > > > > >        board, But the erasing and writting operation is not
> > > > > > > > happening
> > > > > > > >        properly
> > > > > > > >          hier flashrom output :
> > > > > > > >    Is this the board by ASRock?
> > > > > > > >
> > > > > > > >    -Bari
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > >
> > > > > >
> > > > >
> > > > > --
> > > > > coreboot mailing list
> > > > > coreboot at coreboot.org
> > > > > http://www.coreboot.org/mailman/listinfo/coreboot
> > > > >
> > > >
> > > >
> > >
> >
>
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From stepan at coresystems.de  Sat Apr  5 19:32:04 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 05 Apr 2008 11:32:04 -0600
Subject: [coreboot] [PATCH] v3: read option roms from lar instead of hard
	coded address
Message-ID: <47F7B794.8080206@coresystems.de>

Signed-off-by: Stefan Reinauer <stepan at coreboot.org>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From rminnich at gmail.com  Sat Apr  5 19:40:31 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 5 Apr 2008 10:40:31 -0700
Subject: [coreboot] [PATCH] v3: read option roms from lar instead of
	hard coded address
In-Reply-To: <47F7B794.8080206@coresystems.de>
References: <47F7B794.8080206@coresystems.de>
Message-ID: <13426df10804051040j4eb7bf76ydee5b0fa0df7a459@mail.gmail.com>

On Sat, Apr 5, 2008 at 10:32 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
> Signed-off-by: Stefan Reinauer <stepan at coreboot.org>
>

Now this is really neat!

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From peter at stuge.se  Sat Apr  5 19:54:08 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 5 Apr 2008 19:54:08 +0200
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804042355w2f1b42c7q42f755b58eb48d9c@mail.gmail.com>
References: <47F4DBB7.4050100@onelabs.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
	<dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
	<fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>
	<dd3c80060804040559h4b7510b1q7747f44e897fa4da@mail.gmail.com>
	<fa70bcc0804040625wb01013vd941cd25fb274bba@mail.gmail.com>
	<fa70bcc0804042355w2f1b42c7q42f755b58eb48d9c@mail.gmail.com>
Message-ID: <20080405175408.30351.qmail@stuge.se>

Hi,

On Sat, Apr 05, 2008 at 12:25:33PM +0530, malatesh kamatad wrote:
> But the content after writing by using  below command shows result
> like this....

I suggest you have a look at the flashrom documentation. There is no
point in running flashrom like that.


> [root at localhost ~]# /usr/local/sbin/flashrom -r | hexdump
> 
> 0000000 6143 696c 7262 7461 6e69 2067 6564 616c
> 0000010 2079 6f6c 706f 2e2e 202e 4b4f 0a2e 6f4e
> 0000020 6320 726f 6265 6f6f 2074 6174 6c62 2065
> 0000030 6f66 6e75 2e64 460a 756f 646e 6320 6968
> 0000040 7370 7465 2220 4956 2041 5456 3238 3733
> 0000050 2c22 6520 616e 6c62 6e69 2067 6c66 7361
> 0000060 2068 7277 7469 2e65 2e2e 4f20 2e4b 530a
> 0000070 5453 3934 464c 3030 4134 422f 6620 756f
> 0000080 646e 6120 2074 6870 7379 6369 6c61 6120
> 0000090 6464 6572 7373 3020 6678 6666 3038 3030
> 00000a0 2e30 460a 616c 6873 7020 7261 2074 7369
> 00000b0 5320 5453 3934 464c 3030 4134 422f 2820
> 00000c0 3135 2032 424b 2e29 450a 7272 726f 203a
> 00000d0 6f4e 6620 6c69 6e65 6d61 2065 7073 6365
> 00000e0 6669 6569 2e64 000a

The following is the cleartext of the above hexdump:

6143 696c 7262 7461 6e69 2067 6564 616c Calibrating dela
2079 6f6c 706f 2e2e 202e 4b4f 0a2e 6f4e y loop... OK. No
6320 726f 6265 6f6f 2074 6174 6c62 2065 coreboot table
6f66 6e75 2e64 460a 756f 646e 6320 6968 found. Found chi
7370 7465 2220 4956 2041 5456 3238 3733 pset "VIA VT8237
2c22 6520 616e 6c62 6e69 2067 6c66 7361 ", enabling flas
2068 7277 7469 2e65 2e2e 4f20 2e4b 530a h write... OK. S
5453 3934 464c 3030 4134 422f 6620 756f ST49LF004A/B fou
646e 6120 2074 6870 7379 6369 6c61 6120 nd at physical a
6464 6572 7373 3020 6678 6666 3038 3030 ddress 0xfff8000
2e30 460a 616c 6873 7020 7261 2074 7369 0. Flash part is
5320 5453 3934 464c 3030 4134 422f 2820 SST49LF004A/B (
3135 2032 424b 2e29 450a 7272 726f 203a 512 KB). Error:
6f4e 6620 6c69 6e65 6d61 2065 7073 6365 No filename spec
6669 6569 2e64 000a ified.

flashrom has not performed any action.

I do not think it is possible for flashrom to write data it has read
from the flash chip to stdout. I also don't think it would be useful.


> ************************************
>   But using only hexdump i got result like this ...
> 
> [root at localhost ~]# hexdump sst_after_write05.bin
> 0000000 ffff ffff ffff ffff ffff ffff ffff ffff
> *
> 0080000

This shows that writing fails completely.

So the problem is within the write algorithm that flashrom uses with
this flash chip. Feel free to compare the code in flashrom with the
programming algorithm specified in the flash chip datasheet. Best
case you only have to pick another write function, but my guess is
that some code needs to change.

Oh, by the way, erasing may also not work properly for this chip, if
you have never successfully programmed anything into the SST chip
then we don't know for sure if erase works or not. They come erased
(all 0xff) from factory so failure to erase using flashrom would not
be obvious. Verifying this is a good start, and easier than writing.
But it also requires another, working, method of writing to the SST
chip. (Flash programmer, another mainboard, etc.)


//Peter



From marc.jones at amd.com  Sat Apr  5 20:38:18 2008
From: marc.jones at amd.com (Marc Jones)
Date: Sat, 05 Apr 2008 12:38:18 -0600
Subject: [coreboot] [patch][v2] fix PCI routing on Geode 5536
Message-ID: <47F7C71A.4090800@amd.com>

This patch fixes the PIR routing setup using the current PIR table for 
Geode 5536 systems. I think that this is also the v3 db800 and other 
5536 Linux booting problems.


-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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From stepan at coresystems.de  Sat Apr  5 20:43:25 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 05 Apr 2008 12:43:25 -0600
Subject: [coreboot] [patch][v2] fix PCI routing on Geode 5536
In-Reply-To: <47F7C71A.4090800@amd.com>
References: <47F7C71A.4090800@amd.com>
Message-ID: <47F7C84D.7080509@coresystems.de>

Marc Jones wrote:
> This patch fixes the PIR routing setup using the current PIR table for 
> Geode 5536 systems. I think that this is also the v3 db800 and other 
> 5536 Linux booting problems.
>
>
> Don't check exclusive IRQ field. This field is rarely used (and not used in
> the LX tables). There is not a good reason to mask off non-exclusive IRQs.
>
> Signed-off-by: Marc Jones(marc.jones at amd.com)

Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Sat Apr  5 22:18:48 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  5 Apr 2008 22:18:48 +0200
Subject: [coreboot] r657 - coreboot-v3/device
Message-ID: <mailman.1377.1355071296.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-04-05 22:18:47 +0200 (Sat, 05 Apr 2008)
New Revision: 657

Modified:
   coreboot-v3/device/pci_rom.c
Log:
retrieve option roms from lar.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/device/pci_rom.c
===================================================================
--- coreboot-v3/device/pci_rom.c	2008-04-05 00:09:29 UTC (rev 656)
+++ coreboot-v3/device/pci_rom.c	2008-04-05 20:18:47 UTC (rev 657)
@@ -27,6 +27,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <string.h>
+#include <lar.h>
 
 struct rom_header *pci_rom_probe(struct device *dev)
 {
@@ -35,12 +36,30 @@
 	struct pci_data *rom_data;
 	unsigned int i;
 	unsigned char sum = 0, *rom_bytes;
+	struct mem_file archive, result;
 
 	if (dev->on_mainboard) {
+		int ret;
+		char pcifile[] = "pci0000,0000.rom";
 		/* In case some device PCI_ROM_ADDRESS can not be set
 		 * or readonly.
 		 */
-		rom_address = dev->rom_address;
+		init_archive(&archive);
+		sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor,
+				dev->id.u.pci.device);
+
+		ret = find_file(&archive, pcifile, &result);
+		if (ret) {
+			printk(BIOS_INFO, "No option rom for onboard device.\n");
+			return NULL;
+		}
+
+		/* FIXME hardcode to 0xc0000 for now because we can only init
+		 * VGA anyways.
+		 */
+		process_file(&result, (void *)0xc0000);
+		rom_address = 0xc0000;
+
 	} else {
 		rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
 	}
@@ -140,10 +159,11 @@
 		if (dev != vga_pri)
 			return NULL;	// Only one VGA supported.
 #endif
-		printk(BIOS_DEBUG,
-		       "Copying VGA ROM image from %p to 0x%x, 0x%x bytes\n",
-		       rom_header, PCI_VGA_RAM_IMAGE_START, rom_size);
-		memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size);
+		if (rom_header != (void *)PCI_VGA_RAM_IMAGE_START) {
+			printk(BIOS_DEBUG, "Copying VGA ROM image from %p to 0x%x, 0x%x bytes\n", 
+					rom_header, PCI_VGA_RAM_IMAGE_START, rom_size);
+			memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size);
+		}
 		vga_inited = 1;
 		return (struct rom_header *)(PCI_VGA_RAM_IMAGE_START);
 #endif




From bios at ryven.de  Sat Apr  5 23:26:01 2008
From: bios at ryven.de (Markus)
Date: Sat, 5 Apr 2008 23:26:01 +0200
Subject: [coreboot] flashrom + Scenic Mobile 510 Agp
Message-ID: <20080405232601.480b878d@Tansmeta>

hi, I tried flashrom on the Notebook Scenic Mobile 510 Agp.
Unforunal after calibarte loop the nb goes off. I think the read-access
goes into apm.
The notebook seems nice, because the flash is sockled.
superio workes.
SMSC sch5317 (id=0x85, rev=0x00,) at 0x370

Regard
Markus



From joe at smittys.pointclark.net  Sun Apr  6 02:24:41 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Sat, 05 Apr 2008 20:24:41 -0400
Subject: [coreboot] v2[PATCH]ICH series halt tco timer
Message-ID: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>

This patch halts the tco timer early in the boot process on all ICH  
series southbridges. It also keeps the boot processes from rebooting  
through out the coreboot process.

Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>

Thanks - Joe
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From corey.osgood at gmail.com  Sun Apr  6 03:01:22 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 5 Apr 2008 21:01:22 -0400
Subject: [coreboot] v2[PATCH]ICH series halt tco timer
In-Reply-To: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>
References: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>
Message-ID: <dd3c80060804051801h3f77bd4an87c041715bae5814@mail.gmail.com>

On Sat, Apr 5, 2008 at 8:24 PM, <joe at smittys.pointclark.net> wrote:

> This patch halts the tco timer early in the boot process on all ICH series
> southbridges. It also keeps the boot processes from rebooting through out
> the coreboot process.
>
> Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
>
> Thanks - Joe


Index: src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
> ===================================================================
> --- src/southbridge/intel/i82801xx/i82801xx_early_lpc.c    (revision 0)
> +++ src/southbridge/intel/i82801xx/i82801xx_early_lpc.c    (revision 0)
> @@ -0,0 +1,44 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301
> USA
> + *
> + */
> +
> +#define PMBASE_ADDR    0x0400 /* ACPI Base Address Register */
> +#define TCOBASE        0x60 /* TCO Base Address Register */
> +#define TCO1_CNT    0x08 /* TCO1 Control Register */


These should go into i82801xx.h, along with the defines in i82801xx_lpc.h.
Do that, and this patch is
Acked-by: Corey Osgood <corey.osgood at gmail.com>


> +
> +static void i82801xx_halt_tco_timer(void)
> +{
> +    device_t dev;
> +    uint16_t halt_tco_timer;
> +
> +    /* Set the LPC device statically. */
> +    dev = PCI_DEV(0x0, 0x1f, 0x0);
> +
> +    /* Temporarily set ACPI base address (I/O space). */
> +    pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
>
+
> +    /* Temporarily enable ACPI I/O. */
> +    pci_write_config8(dev, ACPI_CNTL, 0x10);
> +
> +    /* Halt the TCO timer, preventing SMI and automatic reboot */
> +    outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR +
> TCOBASE + TCO1_CNT);
> +
> +    /* Disable ACPI I/O. */
> +    pci_write_config8(dev, ACPI_CNTL, 0x00);
> +}
> Index: src/mainboard/rca/rm4100/auto.c
> ===================================================================
> --- src/mainboard/rca/rm4100/auto.c    (revision 3217)
> +++ src/mainboard/rca/rm4100/auto.c    (working copy)
> @@ -42,6 +42,7 @@
>  #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
>
>  #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
> +#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
>
>  /**
>   * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
> @@ -69,24 +70,6 @@
>  #include "sdram/generic_sdram.c"
>
>  /**
> - * We have to disable the TCO Timer system reboot feature
> - * or we get several reboots through out the boot processes.
> - */
> -static void disable_tco_timer(void)
> -{
> -    device_t dev;
> -    u8 reg8;
> -
> -    /* Set the LPC device statically. */
> -    dev = PCI_DEV(0x0, 0x1f, 0x0);
> -
> -    /* Disable the TCO Timer system reboot feature. */
> -    reg8 = pci_read_config8(dev, 0xd4);
> -    reg8 |= (1 << 1);
> -    pci_write_config8(dev, 0xd4, reg8);
> -}
> -
> -/**
>   * The AC'97 Audio Controller I/O space registers are read only by
> default
>   * so we need to enable them by setting register 0x41 to 0x01.
>   */
> @@ -131,6 +114,6 @@
>      /* ram_check(0, 640 * 1024); */
>      /* ram_check(130048 * 1024, 131072 * 1024); */
>
> -    disable_tco_timer();
> +    i82801xx_halt_tco_timer();
>      ac97_io_enable();
>  }
>
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From joe at smittys.pointclark.net  Sun Apr  6 05:06:55 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Sat, 05 Apr 2008 23:06:55 -0400
Subject: [coreboot] v2[PATCH]ICH series halt tco timer
In-Reply-To: <dd3c80060804051801h3f77bd4an87c041715bae5814@mail.gmail.com>
References: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>
	<dd3c80060804051801h3f77bd4an87c041715bae5814@mail.gmail.com>
Message-ID: <20080405230655.hm9dkh3s008k440w@www.smittys.pointclark.net>

Quoting Corey Osgood <corey.osgood at gmail.com>:

> On Sat, Apr 5, 2008 at 8:24 PM, <joe at smittys.pointclark.net> wrote:
>
>> This patch halts the tco timer early in the boot process on all ICH series
>> southbridges. It also keeps the boot processes from rebooting through out
>> the coreboot process.
>>
>> Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
>>
>> Thanks - Joe
>
>
> Index: src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
>> ===================================================================
>> --- src/southbridge/intel/i82801xx/i82801xx_early_lpc.c    (revision 0)
>> +++ src/southbridge/intel/i82801xx/i82801xx_early_lpc.c    (revision 0)
>> @@ -0,0 +1,44 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301
>> USA
>> + *
>> + */
>> +
>> +#define PMBASE_ADDR    0x0400 /* ACPI Base Address Register */
>> +#define TCOBASE        0x60 /* TCO Base Address Register */
>> +#define TCO1_CNT    0x08 /* TCO1 Control Register */
>
>
> These should go into i82801xx.h, along with the defines in i82801xx_lpc.h.
> Do that, and this patch is
> Acked-by: Corey Osgood <corey.osgood at gmail.com>
>
I can move the TCOBASE TCO1_CNT to i82801xx.h because these are static but,
PMBASE_ADDR is a variable and should not be placed in a header file correct?

>
>
>> +
>> +static void i82801xx_halt_tco_timer(void)
>> +{
>> +    device_t dev;
>> +    uint16_t halt_tco_timer;
>> +
>> +    /* Set the LPC device statically. */
>> +    dev = PCI_DEV(0x0, 0x1f, 0x0);
>> +
>> +    /* Temporarily set ACPI base address (I/O space). */
>> +    pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
>>
> +
>> +    /* Temporarily enable ACPI I/O. */
>> +    pci_write_config8(dev, ACPI_CNTL, 0x10);
>> +
>> +    /* Halt the TCO timer, preventing SMI and automatic reboot */
>> +    outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR +
>> TCOBASE + TCO1_CNT);
>> +
>> +    /* Disable ACPI I/O. */
>> +    pci_write_config8(dev, ACPI_CNTL, 0x00);
>> +}
>> Index: src/mainboard/rca/rm4100/auto.c
>> ===================================================================
>> --- src/mainboard/rca/rm4100/auto.c    (revision 3217)
>> +++ src/mainboard/rca/rm4100/auto.c    (working copy)
>> @@ -42,6 +42,7 @@
>>  #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
>>
>>  #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
>> +#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
>>
>>  /**
>>   * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
>> @@ -69,24 +70,6 @@
>>  #include "sdram/generic_sdram.c"
>>
>>  /**
>> - * We have to disable the TCO Timer system reboot feature
>> - * or we get several reboots through out the boot processes.
>> - */
>> -static void disable_tco_timer(void)
>> -{
>> -    device_t dev;
>> -    u8 reg8;
>> -
>> -    /* Set the LPC device statically. */
>> -    dev = PCI_DEV(0x0, 0x1f, 0x0);
>> -
>> -    /* Disable the TCO Timer system reboot feature. */
>> -    reg8 = pci_read_config8(dev, 0xd4);
>> -    reg8 |= (1 << 1);
>> -    pci_write_config8(dev, 0xd4, reg8);
>> -}
>> -
>> -/**
>>   * The AC'97 Audio Controller I/O space registers are read only by
>> default
>>   * so we need to enable them by setting register 0x41 to 0x01.
>>   */
>> @@ -131,6 +114,6 @@
>>      /* ram_check(0, 640 * 1024); */
>>      /* ram_check(130048 * 1024, 131072 * 1024); */
>>
>> -    disable_tco_timer();
>> +    i82801xx_halt_tco_timer();
>>      ac97_io_enable();
>>  }
>>
>



Thanks - Joe



From corey.osgood at gmail.com  Sun Apr  6 05:17:37 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 5 Apr 2008 23:17:37 -0400
Subject: [coreboot] v2[PATCH]ICH series halt tco timer
In-Reply-To: <20080405230655.hm9dkh3s008k440w@www.smittys.pointclark.net>
References: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>
	<dd3c80060804051801h3f77bd4an87c041715bae5814@mail.gmail.com>
	<20080405230655.hm9dkh3s008k440w@www.smittys.pointclark.net>
Message-ID: <dd3c80060804052017v71825302v762662fd002ff53f@mail.gmail.com>

On Sat, Apr 5, 2008 at 11:06 PM, <joe at smittys.pointclark.net> wrote:

> Quoting Corey Osgood <corey.osgood at gmail.com>:
>
>  On Sat, Apr 5, 2008 at 8:24 PM, <joe at smittys.pointclark.net> wrote:
> >
> >  This patch halts the tco timer early in the boot process on all ICH
> > > series
> > > southbridges. It also keeps the boot processes from rebooting through
> > > out
> > > the coreboot process.
> > >
> > > Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
> > >
> > > Thanks - Joe
> > >
> >
> >
> > Index: src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
> >
> > > ===================================================================
> > > --- src/southbridge/intel/i82801xx/i82801xx_early_lpc.c    (revision
> > > 0)
> > > +++ src/southbridge/intel/i82801xx/i82801xx_early_lpc.c    (revision
> > > 0)
> > > @@ -0,0 +1,44 @@
> > > +/*
> > > + * This file is part of the coreboot project.
> > > + *
> > > + * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > modify
> > > + * it under the terms of the GNU General Public License version 2 as
> > > + * published by the Free Software Foundation.
> > > + *
> > > + * This program is distributed in the hope that it will be useful,
> > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > > + * GNU General Public License for more details.
> > > + *
> > > + * You should have received a copy of the GNU General Public License
> > > + * along with this program; if not, write to the Free Software
> > > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
> > >  02110-1301
> > > USA
> > > + *
> > > + */
> > > +
> > > +#define PMBASE_ADDR    0x0400 /* ACPI Base Address Register */
> > > +#define TCOBASE        0x60 /* TCO Base Address Register */
> > > +#define TCO1_CNT    0x08 /* TCO1 Control Register */
> > >
> >
> >
> > These should go into i82801xx.h, along with the defines in
> > i82801xx_lpc.h.
> > Do that, and this patch is
> > Acked-by: Corey Osgood <corey.osgood at gmail.com>
> >
> >  I can move the TCOBASE TCO1_CNT to i82801xx.h because these are static
> but,
> PMBASE_ADDR is a variable and should not be placed in a header file
> correct?


PMBASE_ADDR can be anywhere we want it to be, so long as it doesn't collide
with any IO addresses that have been reserved for other things. Currently,
it's defined in i82801xx_lpc.c at the same address, that's why I was saying
to move those defines as well (so PMBASE_ADDR isn't defined in 2 different
places). If PMBASE_ADDR ever needs to be somewhere else for some reason in
the future, we can make it configurable at build time (or something).

-Corey


>
>
>
> >
> >  +
> > > +static void i82801xx_halt_tco_timer(void)
> > > +{
> > > +    device_t dev;
> > > +    uint16_t halt_tco_timer;
> > > +
> > > +    /* Set the LPC device statically. */
> > > +    dev = PCI_DEV(0x0, 0x1f, 0x0);
> > > +
> > > +    /* Temporarily set ACPI base address (I/O space). */
> > > +    pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
> > >
> > >  +
> >
> > > +    /* Temporarily enable ACPI I/O. */
> > > +    pci_write_config8(dev, ACPI_CNTL, 0x10);
> > > +
> > > +    /* Halt the TCO timer, preventing SMI and automatic reboot */
> > > +    outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11),
> > > PMBASE_ADDR +
> > > TCOBASE + TCO1_CNT);
> > > +
> > > +    /* Disable ACPI I/O. */
> > > +    pci_write_config8(dev, ACPI_CNTL, 0x00);
> > > +}
> > > Index: src/mainboard/rca/rm4100/auto.c
> > > ===================================================================
> > > --- src/mainboard/rca/rm4100/auto.c    (revision 3217)
> > > +++ src/mainboard/rca/rm4100/auto.c    (working copy)
> > > @@ -42,6 +42,7 @@
> > >  #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
> > >
> > >  #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
> > > +#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
> > >
> > >  /**
> > >  * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
> > > @@ -69,24 +70,6 @@
> > >  #include "sdram/generic_sdram.c"
> > >
> > >  /**
> > > - * We have to disable the TCO Timer system reboot feature
> > > - * or we get several reboots through out the boot processes.
> > > - */
> > > -static void disable_tco_timer(void)
> > > -{
> > > -    device_t dev;
> > > -    u8 reg8;
> > > -
> > > -    /* Set the LPC device statically. */
> > > -    dev = PCI_DEV(0x0, 0x1f, 0x0);
> > > -
> > > -    /* Disable the TCO Timer system reboot feature. */
> > > -    reg8 = pci_read_config8(dev, 0xd4);
> > > -    reg8 |= (1 << 1);
> > > -    pci_write_config8(dev, 0xd4, reg8);
> > > -}
> > > -
> > > -/**
> > >  * The AC'97 Audio Controller I/O space registers are read only by
> > > default
> > >  * so we need to enable them by setting register 0x41 to 0x01.
> > >  */
> > > @@ -131,6 +114,6 @@
> > >     /* ram_check(0, 640 * 1024); */
> > >     /* ram_check(130048 * 1024, 131072 * 1024); */
> > >
> > > -    disable_tco_timer();
> > > +    i82801xx_halt_tco_timer();
> > >     ac97_io_enable();
> > >  }
> > >
> > >
> >
>
>
> Thanks - Joe
>
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From joe at smittys.pointclark.net  Sun Apr  6 05:38:07 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Sat, 05 Apr 2008 23:38:07 -0400
Subject: [coreboot] v2[PATCH]ICH series halt tco timer
In-Reply-To: <dd3c80060804052017v71825302v762662fd002ff53f@mail.gmail.com>
References: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>
	<dd3c80060804051801h3f77bd4an87c041715bae5814@mail.gmail.com>
	<20080405230655.hm9dkh3s008k440w@www.smittys.pointclark.net>
	<dd3c80060804052017v71825302v762662fd002ff53f@mail.gmail.com>
Message-ID: <20080405233807.l0f88zvb484c0gwg@www.smittys.pointclark.net>


> PMBASE_ADDR can be anywhere we want it to be, so long as it doesn't collide
> with any IO addresses that have been reserved for other things. Currently,
> it's defined in i82801xx_lpc.c at the same address, that's why I was saying
> to move those defines as well (so PMBASE_ADDR isn't defined in 2 different
> places). If PMBASE_ADDR ever needs to be somewhere else for some reason in
> the future, we can make it configurable at build time (or something).
>
> -Corey
>
Ok, here is the revised patch.

Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>


Thanks - Joe
-------------- next part --------------
Index: src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
===================================================================
--- src/southbridge/intel/i82801xx/i82801xx_early_lpc.c	(revision 0)
+++ src/southbridge/intel/i82801xx/i82801xx_early_lpc.c	(revision 0)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+static void i82801xx_halt_tco_timer(void)
+{
+	device_t dev;
+	uint16_t halt_tco_timer;
+
+	/* Set the LPC device statically. */
+	dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Temporarily set ACPI base address (I/O space). */
+	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+	/* Temporarily enable ACPI I/O. */
+	pci_write_config8(dev, ACPI_CNTL, 0x10);
+
+	/* Halt the TCO timer, preventing SMI and automatic reboot */
+	outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
+
+	/* Disable ACPI I/O. */
+	pci_write_config8(dev, ACPI_CNTL, 0x00);
+}
Index: src/southbridge/intel/i82801xx/i82801xx_lpc.c
===================================================================
--- src/southbridge/intel/i82801xx/i82801xx_lpc.c	(revision 3217)
+++ src/southbridge/intel/i82801xx/i82801xx_lpc.c	(working copy)
@@ -32,7 +32,6 @@
 #include <arch/io.h>
 #include "i82801xx.h"
 
-#define PMBASE_ADDR	0x00000400 /* ACPI Base Address Register */
 #define GPIO_BASE_ADDR	0x00000500 /* GPIO Base Address Register */
 
 #define NMI_OFF 0
Index: src/southbridge/intel/i82801xx/i82801xx.h
===================================================================
--- src/southbridge/intel/i82801xx/i82801xx.h	(revision 3217)
+++ src/southbridge/intel/i82801xx/i82801xx.h	(working copy)
@@ -34,6 +34,7 @@
 #define GEN_PMCON_3		0xa4
 
 #define PMBASE			0x40
+#define PMBASE_ADDR		0x0400 /* ACPI Base Address Register */
 #define ACPI_CNTL		0x44
 #define BIOS_CNTL		0x4E
 #define GPIO_BASE_ICH0_5	0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
@@ -68,6 +69,9 @@
 #define MTT			0x70
 #define PCI_MAST_STS		0x82
 
+#define TCOBASE			0x60 /* TCO Base Address Register */
+#define TCO1_CNT		0x08 /* TCO1 Control Register */
+
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)
 #define RTC_POWER_FAILED	(1 << 1)
Index: src/mainboard/rca/rm4100/auto.c
===================================================================
--- src/mainboard/rca/rm4100/auto.c	(revision 3217)
+++ src/mainboard/rca/rm4100/auto.c	(working copy)
@@ -42,6 +42,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
 
 /**
  * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
@@ -69,24 +70,6 @@
 #include "sdram/generic_sdram.c"
 
 /**
- * We have to disable the TCO Timer system reboot feature
- * or we get several reboots through out the boot processes.
- */
-static void disable_tco_timer(void)
-{
-	device_t dev;
-	u8 reg8;
-
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Disable the TCO Timer system reboot feature. */
-	reg8 = pci_read_config8(dev, 0xd4);
-	reg8 |= (1 << 1);
-	pci_write_config8(dev, 0xd4, reg8);
-}
-
-/**
  * The AC'97 Audio Controller I/O space registers are read only by default
  * so we need to enable them by setting register 0x41 to 0x01.
  */
@@ -131,6 +114,6 @@
 	/* ram_check(0, 640 * 1024); */
 	/* ram_check(130048 * 1024, 131072 * 1024); */
 
-	disable_tco_timer();
+	i82801xx_halt_tco_timer();
 	ac97_io_enable();
 }

From corey.osgood at gmail.com  Sun Apr  6 05:58:49 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 5 Apr 2008 23:58:49 -0400
Subject: [coreboot] v2[PATCH]ICH series halt tco timer
In-Reply-To: <20080405233807.l0f88zvb484c0gwg@www.smittys.pointclark.net>
References: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>
	<dd3c80060804051801h3f77bd4an87c041715bae5814@mail.gmail.com>
	<20080405230655.hm9dkh3s008k440w@www.smittys.pointclark.net>
	<dd3c80060804052017v71825302v762662fd002ff53f@mail.gmail.com>
	<20080405233807.l0f88zvb484c0gwg@www.smittys.pointclark.net>
Message-ID: <dd3c80060804052058t35a974a4ybb3d0870c528d265@mail.gmail.com>

On Sat, Apr 5, 2008 at 11:38 PM, <joe at smittys.pointclark.net> wrote:

>
>  PMBASE_ADDR can be anywhere we want it to be, so long as it doesn't
> > collide
> > with any IO addresses that have been reserved for other things.
> > Currently,
> > it's defined in i82801xx_lpc.c at the same address, that's why I was
> > saying
> > to move those defines as well (so PMBASE_ADDR isn't defined in 2
> > different
> > places). If PMBASE_ADDR ever needs to be somewhere else for some reason
> > in
> > the future, we can make it configurable at build time (or something).
> >
> > -Corey
> >
> >  Ok, here is the revised patch.
>
>
> Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
>
>
> Thanks - Joe
>

Acked-by: Corey Osgood <corey.osgood at gmail.com>
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From svn at coreboot.org  Sun Apr  6 06:26:21 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  6 Apr 2008 06:26:21 +0200
Subject: [coreboot] r3218 - in trunk/coreboot-v2/src: mainboard/rca/rm4100
	southbridge/intel/i82801xx
Message-ID: <mailman.1378.1355071296.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2008-04-06 06:26:19 +0200 (Sun, 06 Apr 2008)
New Revision: 3218

Added:
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
Log:
This patch halts the tco timer early in the boot process on all ICH series southbridges.
It also keeps the boot processes from rebooting through out the coreboot process.

Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood at gmail.com>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c	2008-04-05 01:07:27 UTC (rev 3217)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c	2008-04-06 04:26:19 UTC (rev 3218)
@@ -42,6 +42,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
 
 /**
  * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
@@ -69,24 +70,6 @@
 #include "sdram/generic_sdram.c"
 
 /**
- * We have to disable the TCO Timer system reboot feature
- * or we get several reboots through out the boot processes.
- */
-static void disable_tco_timer(void)
-{
-	device_t dev;
-	u8 reg8;
-
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Disable the TCO Timer system reboot feature. */
-	reg8 = pci_read_config8(dev, 0xd4);
-	reg8 |= (1 << 1);
-	pci_write_config8(dev, 0xd4, reg8);
-}
-
-/**
  * The AC'97 Audio Controller I/O space registers are read only by default
  * so we need to enable them by setting register 0x41 to 0x01.
  */
@@ -131,6 +114,6 @@
 	/* ram_check(0, 640 * 1024); */
 	/* ram_check(130048 * 1024, 131072 * 1024); */
 
-	disable_tco_timer();
+	i82801xx_halt_tco_timer();
 	ac97_io_enable();
 }

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h	2008-04-05 01:07:27 UTC (rev 3217)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx.h	2008-04-06 04:26:19 UTC (rev 3218)
@@ -34,6 +34,7 @@
 #define GEN_PMCON_3		0xa4
 
 #define PMBASE			0x40
+#define PMBASE_ADDR		0x0400 /* ACPI Base Address Register */
 #define ACPI_CNTL		0x44
 #define BIOS_CNTL		0x4E
 #define GPIO_BASE_ICH0_5	0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
@@ -68,6 +69,9 @@
 #define MTT			0x70
 #define PCI_MAST_STS		0x82
 
+#define TCOBASE			0x60 /* TCO Base Address Register */
+#define TCO1_CNT		0x08 /* TCO1 Control Register */
+
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)
 #define RTC_POWER_FAILED	(1 << 1)

Added: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c	2008-04-06 04:26:19 UTC (rev 3218)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+static void i82801xx_halt_tco_timer(void)
+{
+	device_t dev;
+	uint16_t halt_tco_timer;
+
+	/* Set the LPC device statically. */
+	dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Temporarily set ACPI base address (I/O space). */
+	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+	/* Temporarily enable ACPI I/O. */
+	pci_write_config8(dev, ACPI_CNTL, 0x10);
+
+	/* Halt the TCO timer, preventing SMI and automatic reboot */
+	outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
+
+	/* Disable ACPI I/O. */
+	pci_write_config8(dev, ACPI_CNTL, 0x00);
+}

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2008-04-05 01:07:27 UTC (rev 3217)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2008-04-06 04:26:19 UTC (rev 3218)
@@ -32,7 +32,6 @@
 #include <arch/io.h>
 #include "i82801xx.h"
 
-#define PMBASE_ADDR	0x00000400 /* ACPI Base Address Register */
 #define GPIO_BASE_ADDR	0x00000500 /* GPIO Base Address Register */
 
 #define NMI_OFF 0




From joe at smittys.pointclark.net  Sun Apr  6 06:29:07 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Sun, 06 Apr 2008 00:29:07 -0400
Subject: [coreboot] v2[PATCH]ICH series halt tco timer
In-Reply-To: <dd3c80060804052058t35a974a4ybb3d0870c528d265@mail.gmail.com>
References: <20080405202441.bdkf7n4ef4k4880w@www.smittys.pointclark.net>
	<dd3c80060804051801h3f77bd4an87c041715bae5814@mail.gmail.com>
	<20080405230655.hm9dkh3s008k440w@www.smittys.pointclark.net>
	<dd3c80060804052017v71825302v762662fd002ff53f@mail.gmail.com>
	<20080405233807.l0f88zvb484c0gwg@www.smittys.pointclark.net>
	<dd3c80060804052058t35a974a4ybb3d0870c528d265@mail.gmail.com>
Message-ID: <20080406002907.f99s453jz4kw4c0c@www.smittys.pointclark.net>

Quoting Corey Osgood <corey.osgood at gmail.com>:

> On Sat, Apr 5, 2008 at 11:38 PM, <joe at smittys.pointclark.net> wrote:
>
>>
>>  PMBASE_ADDR can be anywhere we want it to be, so long as it doesn't
>> > collide
>> > with any IO addresses that have been reserved for other things.
>> > Currently,
>> > it's defined in i82801xx_lpc.c at the same address, that's why I was
>> > saying
>> > to move those defines as well (so PMBASE_ADDR isn't defined in 2
>> > different
>> > places). If PMBASE_ADDR ever needs to be somewhere else for some reason
>> > in
>> > the future, we can make it configurable at build time (or something).
>> >
>> > -Corey
>> >
>> >  Ok, here is the revised patch.
>>
>>
>> Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
>>
>>
>> Thanks - Joe
>>
>
> Acked-by: Corey Osgood <corey.osgood at gmail.com>
>

r3218

Thanks - Joe



From Countzero786 at gmx.de  Sun Apr  6 18:35:26 2008
From: Countzero786 at gmx.de (Countzero786 at gmx.de)
Date: Sun, 06 Apr 2008 18:35:26 +0200
Subject: [coreboot] lifebook b-2175 working with coreboot?
Message-ID: <20080406163526.327100@gmx.net>

Greetings,
I'd like to know if there's a chance I can get coreboot to run on an old Fujitsu-Siemens Lifebook B-2175 I own.
As it uses the Intel 440mx chipset, here are links to the (complete I think?) official documentation:
http://www.intel.com/design/chipsets/designex/273504.htm
http://www.intel.com/design/chipsets/specupdt/245051.htm
http://www.intel.com/design/chipsets/datashts/440MX-66DSPub.htm
http://www.intel.com/design/chipsets/embedded/docs/440mx.htm

And the data I got from probing with the tools I found on your site, lspci and dmesg.

Thanks for your time in advance. Said.

./flashrom
--------------------
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel 440MX", enabling flash write... OK.
MBM29F400TC found at physical address 0xfff80000.
Flash part is MBM29F400TC (512 KB).
No operations were specified.

./superiotool -d
--------------------
superiotool r3194
Found SMSC FDC37N769 (id=0x28, rev=0x01) at 0x3f0
Register dump:
idx 00 01 02 03 04 05 06 07  08 09 0a 0b 0c 0d 0e 0f  10 11 12 13 14 15 16 17  18 19 1a 1b 1c 1d 1e 1f  20 21 22 23 24 25 26 27  28 29 2a 2b 2c 2d 2e 2f
val 20 90 00 f4 00 00 ff 00  00 00 40 00 0e 28 01 00  00 00 00 00 02 00 00 03  00 00 00 00 00 00 80 00  00 00 00 00 00 00 00 00  00 00 00 00 00 03 00 00
def 28 9c 88 70 00 00 ff 00  00 00 00 00 02 28 NA 00  00 80 RR RR NA NA NA 03  RR RR RR RR RR RR 80 00  3c RR RR 00 00 00 00 00  00 00 RR 00 00 03 00 00

lspci -v -v -v
--------------------
00:00.0 Host bridge: Intel Corporation 82440MX Host Bridge (rev 01)
        Subsystem: Fujitsu Limited. Unknown device 107f
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
        Latency: 64

00:00.1 Multimedia audio controller: Intel Corporation 82440MX AC'97 Audio Controller
        Subsystem: Fujitsu Limited. QSound_SigmaTel Stac97 PCI Audio
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0
        Interrupt: pin B routed to IRQ 9
        Region 0: I/O ports at 1000 [size=256]
        Region 1: I/O ports at 1400 [size=64]

00:00.2 Modem: Intel Corporation 82440MX AC'97 Modem Controller (prog-if 00 [Generic])
        Subsystem: Fujitsu Limited. Unknown device 10d1
        Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Interrupt: pin B routed to IRQ 9
        Region 0: I/O ports at 2000 [size=256]
        Region 1: I/O ports at 1800 [size=128]

00:07.0 Bridge: Intel Corporation 82440MX ISA Bridge (rev 01)
        Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0

00:07.1 IDE interface: Intel Corporation 82440MX EIDE Controller (prog-if 80 [Master])
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 64
        Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8]
        Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1]
        Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8]
        Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1]
        Region 4: I/O ports at 1480 [size=16]

00:07.2 USB Controller: Intel Corporation 82440MX USB Universal Host Controller (prog-if 00 [UHCI])
        Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 64
        Interrupt: pin D routed to IRQ 15
        Region 4: I/O ports at 14a0 [size=32]

00:07.3 Bridge: Intel Corporation 82440MX Power Management Controller
        Control: I/O+ Mem+ BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

00:12.0 Ethernet controller: Intel Corporation 82557/8/9 Ethernet Pro 100 (rev 09)
        Subsystem: Fujitsu Limited. Unknown device 1070
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 66 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 9
        Region 0: Memory at fc020000 (32-bit, non-prefetchable) [size=4K]
        Region 1: I/O ports at 1440 [size=64]
        Region 2: Memory at fc000000 (32-bit, non-prefetchable) [size=128K]
        Capabilities: <access denied>

00:13.0 CardBus bridge: O2 Micro, Inc. OZ6933/711E1 CardBus/SmartCardBus Controller (rev 02)
        Subsystem: Fujitsu Limited. Unknown device 10e6
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 168
        Interrupt: pin A routed to IRQ 9
        Region 0: Memory at 20020000 (32-bit, non-prefetchable) [size=4K]
        Bus: primary=00, secondary=01, subordinate=04, sec-latency=176
        Memory window 0: 10000000-13fff000 (prefetchable)
        Memory window 1: 14000000-17fff000
        I/O window 0: 00001c00-00001cff
        I/O window 1: 00002800-000028ff
        BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt+ PostWrite+
        16-bit legacy interface ports at 0001

00:13.1 CardBus bridge: O2 Micro, Inc. OZ6933/711E1 CardBus/SmartCardBus Controller (rev 02)
        Subsystem: Fujitsu Limited. Unknown device 10e6
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 168
        Interrupt: pin B routed to IRQ 9
        Region 0: Memory at 20021000 (32-bit, non-prefetchable) [size=4K]
        Bus: primary=00, secondary=05, subordinate=08, sec-latency=176
        Memory window 0: 18000000-1bfff000 (prefetchable)
        Memory window 1: 1c000000-1ffff000
        I/O window 0: 00002c00-00002cff
        I/O window 1: 00003000-000030ff
        BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt+ PostWrite+
        16-bit legacy interface ports at 0001

00:14.0 VGA compatible controller: ATI Technologies Inc Rage Mobility P/M (rev 64) (prog-if 00 [VGA controller])
        Subsystem: Fujitsu Limited. Unknown device 1103
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 66 (2000ns min), Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 9
        Region 0: Memory at fd000000 (32-bit, non-prefetchable) [size=16M]
        Region 1: I/O ports at 2400 [size=256]
        Region 2: Memory at fc021000 (32-bit, non-prefetchable) [size=4K]
        [virtual] Expansion ROM at 20000000 [disabled] [size=128K]
        Capabilities: <access denied>


dmesg
--------------------
Linux version 2.6.24-WDC (root at wdc.inc) (gcc version 4.3.0 (GCC) ) #1 Fri Apr 4 09:50:06 CEST 2008
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
 BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
 BIOS-e820: 00000000000e7800 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 0000000007fe0000 (usable)
 BIOS-e820: 0000000007fe0000 - 0000000007fefc00 (ACPI data)
 BIOS-e820: 0000000007fefc00 - 0000000007ff0000 (ACPI NVS)
 BIOS-e820: 0000000007ff0000 - 0000000007ff2000 (reserved)
 BIOS-e820: 0000000007ff2000 - 0000000008000000 (usable)
 BIOS-e820: 00000000fff00000 - 0000000100000000 (reserved)
128MB LOWMEM available.
Entering add_active_range(0, 0, 32768) 0 entries of 256 used
Zone PFN ranges:
  DMA             0 ->     4096
  Normal       4096 ->    32768
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
    0:        0 ->    32768
On node 0 totalpages: 32768
  DMA zone: 32 pages used for memmap
  DMA zone: 0 pages reserved
  DMA zone: 4064 pages, LIFO batch:0
  Normal zone: 224 pages used for memmap
  Normal zone: 28448 pages, LIFO batch:7
  Movable zone: 0 pages used for memmap
DMI 2.3 present.
ACPI: RSDP 000F64D0, 0014 (r0 FUJ   )
ACPI: RSDT 07FEC74F, 0028 (r1 FUJ    QUILT     1060000 FUJ      1000)
ACPI: FACP 07FEFB8C, 0074 (r1 FUJ    QUILT     1060000 FUJ      1000)
ACPI: DSDT 07FEC777, 3415 (r1 FUJ    QUILT     1060000 MSFT  1000007)
ACPI: FACS 07FEFFC0, 0040
ACPI: DMI detected: Fujitsu Siemens
ACPI: PM-Timer IO Port: 0xff08
Allocating PCI resources starting at 10000000 (gap: 08000000:f7f00000)
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 00000000000e8000
swsusp: Registered nosave memory region: 00000000000e8000 - 0000000000100000
swsusp: Registered nosave memory region: 0000000007fe0000 - 0000000007fef000
swsusp: Registered nosave memory region: 0000000007fef000 - 0000000007ff0000
swsusp: Registered nosave memory region: 0000000007ff0000 - 0000000007ff2000
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
Kernel command line: root=/dev/hda3 ro vga=6
Local APIC disabled by BIOS -- you can enable it with "lapic"
mapped APIC to ffffb000 (01102000)
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
PID hash table entries: 512 (order: 9, 2048 bytes)
Detected 497.575 MHz processor.
Console: colour VGA+ 80x60
console [tty0] enabled
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 125144k/131072k available (2200k kernel code, 5316k reserved, 720k data, 284k init, 0k highmem)
virtual kernel memory layout:
    fixmap  : 0xfffb5000 - 0xfffff000   ( 296 kB)
    vmalloc : 0xc8800000 - 0xfffb3000   ( 887 MB)
    lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
      .init : 0xc03de000 - 0xc0425000   ( 284 kB)
      .data : 0xc03260b7 - 0xc03da39c   ( 720 kB)
      .text : 0xc0100000 - 0xc03260b7   (2200 kB)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 995.54 BogoMIPS (lpj=497774)
Mount-cache hash table entries: 512
CPU: After generic identify, caps: 0383f9ff 00000000 00000000 00000000 00000000 00000000 00000000 00000000
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 128K
CPU: After all inits, caps: 0383f9ff 00000000 00000000 00000040 00000000 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Compat vDSO mapped to ffffe000.
CPU: Intel Celeron (Coppermine) stepping 06
Checking 'hlt' instruction... OK.
Freeing SMP alternatives: 0k freed
Early unpacking initramfs... done
ACPI: Core revision 20070126
ACPI: Looking for DSDT in initramfs... error, file /DSDT.aml not found.
ACPI: setting ELCR to 0200 (from 8200)
net_namespace: 64 bytes
NET: Registered protocol family 16
EISA bus registered
ACPI: bus type pci registered
PCI: PCI BIOS revision 2.10 entry at 0xfd9ce, last bus=2
PCI: Using configuration type 1
Setting up standard PCI resources
ACPI: EC: Look up EC in DSDT
ACPI: Interpreter enabled
ACPI: (supports S0 S3 S4 S5)
ACPI: Using PIC for interrupt routing
ACPI: EC: GPE = 0x2c, I/O: command/status = 0x66, data = 0x62
ACPI: EC: driver started in poll mode
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI quirk: region ff00-ff3f claimed by PIIX4 ACPI
PCI quirk: region ff80-ff8f claimed by PIIX4 SMB
PIIX4 devres C PIO at fd60-fd67
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 7 *9 10 11)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 7 *9 10 11)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 7 *9 10 11)
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 7 10 11 *15)
ACPI: Power Resource [USBP] (on)
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
ACPI: bus type pnp registered
pnp: PnP ACPI: found 8 devices
ACPI: ACPI bus type pnp unregistered
SCSI subsystem initialized
PCI: Using ACPI for IRQ routing
PCI: If a device doesn't work, try "pci=routeirq".  If it helps, post a report
Time: tsc clocksource has been installed.
system 00:01: ioport range 0x4d0-0x4d1 has been reserved
system 00:01: ioport range 0xff00-0xff3f has been reserved
system 00:01: ioport range 0xf800-0xf87f has been reserved
system 00:01: ioport range 0xfd60-0xfd67 has been reserved
system 00:01: ioport range 0xfe00-0xfe00 has been reserved
system 00:01: ioport range 0xff80-0xff8f has been reserved
PCI: Bus 1, cardbus bridge: 0000:00:13.0
  IO window: 00001c00-00001cff
  IO window: 00002800-000028ff
  PREFETCH window: 10000000-13ffffff
  MEM window: 14000000-17ffffff
PCI: Bus 5, cardbus bridge: 0000:00:13.1
  IO window: 00002c00-00002cff
  IO window: 00003000-000030ff
  PREFETCH window: 18000000-1bffffff
  MEM window: 1c000000-1fffffff
ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 9
PCI: setting IRQ 9 as level-triggered
ACPI: PCI Interrupt 0000:00:13.0[A] -> Link [LNKA] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:13.0 to 64
ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 9
ACPI: PCI Interrupt 0000:00:13.1[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:13.1 to 64
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
Unpacking initramfs... done
Freeing initrd memory: 749k freed
IA-32 Microcode Update Driver: v1.14a <tigran at aivazian.fsnet.co.uk>
apm: BIOS version 1.2 Flags 0x03 (Driver version 1.16ac)
apm: overridden by ACPI.
Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
io scheduler noop registered
io scheduler anticipatory registered (default)
PCI: Firmware left 0000:00:12.0 e100 interrupts enabled, disabling
Boot video device is 0000:00:14.0
isapnp: Scanning for PnP cards...
Switched to high resolution mode on CPU 0
isapnp: No Plug & Play device found
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
PCI: Enabling device 0000:00:00.2 (0000 -> 0001)
ACPI: PCI Interrupt 0000:00:00.2[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9
ACPI: PCI interrupt for device 0000:00:00.2 disabled
loop: module loaded
PNP: PS/2 Controller [PNP0303:KBC,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mice: PS/2 mouse device common for all mice
EISA: Probing bus 0 at eisa.0
cpuidle: using governor ladder
cpuidle: using governor menu
TCP cubic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
Using IPI Shortcut mode
Freeing unused kernel memory: 284k freed
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
PIIX4: IDE controller (0x8086:0x7199 rev 0x00) at  PCI slot 0000:00:07.1
PIIX4: not 100% native mode: will probe irqs later
    ide0: BM-DMA at 0x1480-0x1487, BIOS settings: hda:DMA, hdb:pio
PIIX4: IDE port disabled
Probing IDE interface ide0...
input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0
hda: TOSHIBA MK1016GAP, ATA DISK drive
hda: host max PIO4 wanted PIO255(auto-tune) selected PIO4
hda: UDMA/33 mode selected
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
hda: max request size: 128KiB
hda: 19640880 sectors (10056 MB), CHS=19485/16/63
hda: cache flushes not supported
 hda: hda1 hda2 < hda5 > hda3 hda4
SGI XFS with ACLs, security attributes, realtime, no debug enabled
SGI XFS Quota Management subsystem
Filesystem "hda3": Disabling barriers, not supported by the underlying device
XFS mounting filesystem hda3
Ending clean XFS mount for filesystem: hda3
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0
rtc0: alarms up to one month, y3k
floppy0: no floppy controllers found
ide-floppy driver 0.99.newide
ACPI: AC Adapter [AC] (on-line)
ACPI: Battery Slot [CMB1] (battery absent)
input: Power Button (FF) as /devices/virtual/input/input1
ACPI: Power Button (FF) [PWRF]
input: Power Button (CM) as /devices/virtual/input/input2
ACPI: Power Button (CM) [PWRB]
input: Lid Switch as /devices/virtual/input/input3
ACPI: Lid Switch [LID]
ACPI: CPU0 (power states: C1[C1] C2[C2])
ACPI: Processor [CPU0] (supports 8 throttling states)
Marking TSC unstable due to: TSC halts in idle.
Time: acpi_pm clocksource has been installed.
USB Universal Host Controller Interface driver v3.0
PCI: Enabling device 0000:00:07.2 (0000 -> 0001)
ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 15
PCI: setting IRQ 15 as level-triggered
ACPI: PCI Interrupt 0000:00:07.2[D] -> Link [LNKD] -> GSI 15 (level, low) -> IRQ 15
uhci_hcd 0000:00:07.2: UHCI Host Controller
uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:07.2: irq 15, io base 0x000014a0
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
eepro100.c:v1.09j-t 9/29/99 Donald Becker
eepro100.c: $Revision: 1.36 $ 2000/11/17 Modified by Andrey V. Savochkin <saw at saw.sw.com.sg> and others
ACPI: PCI Interrupt Link [LNKC] enabled at IRQ 9
ACPI: PCI Interrupt 0000:00:12.0[A] -> Link [LNKC] -> GSI 9 (level, low) -> IRQ 9
eth0: OEM i82557/i82558 10/100 Ethernet, 00:00:0e:21:09:35, IRQ 9.
  Board assembly 000000-000, Physical connectors present: RJ45
  Primary interface chip i82555 PHY #1.
  General self-test: passed.
  Serial sub-system self-test: passed.
  Internal registers self-test: passed.
  ROM checksum self-test: passed (0xdbd8681d).
input: PC Speaker as /devices/platform/pcspkr/input/input4
input: PS/2 Touchpad as /devices/platform/i8042/serio1/input/input5
piix4_smbus 0000:00:07.3: Found 0000:00:07.3 device
usb 1-1: new low speed USB device using uhci_hcd and address 2
e100: Intel(R) PRO/100 Network Driver, 3.5.23-k4-NAPI
e100: Copyright(c) 1999-2006 Intel Corporation
Yenta: CardBus bridge found at 0000:00:13.0 [10cf:10e6]
Yenta O2: res at 0x94/0xD4: ea/00
Yenta O2: enabling read prefetch/write burst
usb 1-1: configuration #1 chosen from 1 choice
input: LBPS/2 Fujitsu Lifebook TouchScreen as /devices/platform/i8042/serio1/input/input6
Yenta: ISA IRQ mask 0x0cb8, PCI irq 9
Socket status: 30000006
Yenta: CardBus bridge found at 0000:00:13.1 [10cf:10e6]
Yenta: ISA IRQ mask 0x0cb8, PCI irq 9
Socket status: 30000006
ACPI: PCI Interrupt 0000:00:00.1[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:00.1 to 64
intel8x0_measure_ac97_clock: measured 50106 usecs
intel8x0: clocking to 48000
usbcore: registered new interface driver hiddev
input: Logitech USB-PS/2 Optical Mouse as /devices/pci0000:00/0000:00:07.2/usb1/1-1/1-1:1.0/input/input7
input,hidraw0: USB HID v1.10 Mouse [Logitech USB-PS/2 Optical Mouse] on usb-0000:00:07.2-1
usbcore: registered new interface driver usbhid
drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
cs: IO port probe 0x100-0x3af: clean.
cs: IO port probe 0x3e0-0x4ff: clean.
cs: IO port probe 0x820-0x8ff: clean.
cs: IO port probe 0xc00-0xcf7: clean.
cs: IO port probe 0xa00-0xaff: clean.
cs: IO port probe 0x100-0x3af: clean.
cs: IO port probe 0x3e0-0x4ff: clean.
cs: IO port probe 0x820-0x8ff: clean.
cs: IO port probe 0xc00-0xcf7: clean.
cs: IO port probe 0xa00-0xaff: clean.
Filesystem "hda3": Disabling barriers, not supported by the underlying device
Filesystem "hda3": Disabling barriers, not supported by the underlying device
JFS: nTxBlock = 986, nTxLock = 7895
Filesystem "hda4": Disabling barriers, not supported by the underlying device
XFS mounting filesystem hda4
Ending clean XFS mount for filesystem: hda4
Adding 248968k swap on /dev/hda5.  Priority:-1 extents:1 across:248968k
hda: cache flushes not supported
ip_tables: (C) 2000-2006 Netfilter Core Team
nf_conntrack version 0.5.0 (2048 buckets, 8192 max)
spurious 8259A interrupt: IRQ7.

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From Countzero786 at gmx.de  Sun Apr  6 19:06:05 2008
From: Countzero786 at gmx.de (Countzero786 at gmx.de)
Date: Sun, 06 Apr 2008 19:06:05 +0200
Subject: [coreboot] lifebook b-2175 working with coreboot?
Message-ID: <20080406170605.142940@gmx.net>

Here's dmidecode and lspci -n for the sake of completeness =)

lspci -n
00:00.0 0600: 8086:7194 (rev 01)
00:00.1 0401: 8086:7195
00:00.2 0703: 8086:7196
00:07.0 0680: 8086:7198 (rev 01)
00:07.1 0101: 8086:7199
00:07.2 0c03: 8086:719a
00:07.3 0680: 8086:719b
00:12.0 0200: 8086:1229 (rev 09)
00:13.0 0607: 1217:6933 (rev 02)
00:13.1 0607: 1217:6933 (rev 02)
00:14.0 0300: 1002:4c52 (rev 64)

# dmidecode 2.9
SMBIOS 2.3 present.
41 structures occupying 1106 bytes.
Table at 0x07FF0000.

Handle 0x0000, DMI type 0, 20 bytes
BIOS Information
        Vendor: Phoenix/FUJITSU
        Version: Version  1.06
        Release Date: 11/13/2000
        Address: 0xE4000
        Runtime Size: 112 kB
        ROM Size: 512 kB
        Characteristics:
                PCI is supported
                PC Card (PCMCIA) is supported
                PNP is supported
                APM is supported
                BIOS is upgradeable
                BIOS shadowing is allowed
                Selectable boot is supported
                EDD is supported
                3.5"/720 KB floppy services are supported (int 13h)
                Print screen service is supported (int 5h)
                8042 keyboard services are supported (int 9h)
                Serial services are supported (int 14h)
                Printer services are supported (int 17h)
                CGA/mono video services are supported (int 10h)
                ACPI is supported
                BIOS boot specification is supported
                Function key-initiated network boot is supported

Handle 0x0001, DMI type 1, 25 bytes
System Information
        Manufacturer: FUJITSU SIEMENS
        Product Name: LIFEBOOK B Series
        Version:
        Serial Number: YBTT002429
        UUID: A3D31AFD-CC5F-11D4-8B14-00000E210935
        Wake-up Type: Power Switch

Handle 0x0002, DMI type 2, 8 bytes
Base Board Information
        Manufacturer: FUJITSU
        Product Name: QUILT
        Version:
        Serial Number:

Handle 0x0003, DMI type 3, 13 bytes
Chassis Information
        Manufacturer: FUJITSU SIEMENS
        Type: Notebook
        Lock: Not Present
        Version:
        Serial Number: YBTT002429
        Asset Tag: <BAD INDEX>
        Boot-up State: Unknown
        Power Supply State: Unknown
        Thermal State: Unknown
        Security Status: Unknown

Handle 0x0004, DMI type 4, 32 bytes
Processor Information
        Socket Designation: Onboard
        Type: Central Processor
        Family: Celeron
        Manufacturer: Intel Corporation
        ID: 86 06 00 00 FF F9 83 03
        Signature: Type 0, Family 6, Model 8, Stepping 6
        Flags:
                FPU (Floating-point unit on-chip)
                VME (Virtual mode extension)
                DE (Debugging extension)
                PSE (Page size extension)
                TSC (Time stamp counter)
                MSR (Model specific registers)
                PAE (Physical address extension)
                MCE (Machine check exception)
                CX8 (CMPXCHG8 instruction supported)
                SEP (Fast system call)
                MTRR (Memory type range registers)
                PGE (Page global enable)
                MCA (Machine check architecture)
                CMOV (Conditional move instruction supported)
                PAT (Page attribute table)
                PSE-36 (36-bit page size extension)
                MMX (MMX technology supported)
                FXSR (Fast floating-point save and restore)
                SSE (Streaming SIMD extensions)
        Version: Intel(R) Celeron(TM) processor
        Voltage: 1.3 V
        External Clock: 100 MHz
        Max Speed: 500 MHz
        Current Speed: 500 MHz
        Status: Unpopulated
        Upgrade: None
        L1 Cache Handle: 0x0007
        L2 Cache Handle: 0x0008
        L3 Cache Handle: Not Provided

Handle 0x0005, DMI type 5, 18 bytes
Memory Controller Information
        Error Detecting Method: None
        Error Correcting Capabilities:
                None
        Supported Interleave: One-way Interleave
        Current Interleave: One-way Interleave
        Maximum Memory Module Size: 256 MB
        Maximum Total Memory Size: 256 MB
        Supported Speeds:
                Other
        Supported Memory Types:
                DIMM
                SDRAM
        Memory Module Voltage: 3.3 V
        Associated Memory Slots: 1
                0x0006
        Enabled Error Correcting Capabilities:
                None

Handle 0x0006, DMI type 6, 12 bytes
Memory Module Information
        Socket Designation: DIMM1
        Bank Connections: 0 1
        Current Speed: Unknown
        Type: DIMM SDRAM
        Installed Size: 128 MB (Double-bank Connection)
        Enabled Size: 128 MB (Double-bank Connection)
        Error Status: OK

Handle 0x0007, DMI type 7, 19 bytes
Cache Information
        Socket Designation: L1 Cache
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Write Back
        Location: Internal
        Installed Size: 32 KB
        Maximum Size: 32 KB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: None
        System Type: Other
        Associativity: 4-way Set-associative

Handle 0x0008, DMI type 7, 19 bytes
Cache Information
        Socket Designation: L2 Cache
        Configuration: Enabled, Not Socketed, Level 2
        Operational Mode: Write Back
        Location: Internal
        Installed Size: 128 KB
        Maximum Size: 128 KB
        Supported SRAM Types:
                Pipeline Burst
                Synchronous
        Installed SRAM Type: Pipeline Burst Synchronous
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Unified
        Associativity: Unknown

Handle 0x0009, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Parallel
        External Connector Type: DB-25 female
        Port Type: Parallel Port PS/2

Handle 0x000A, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Serial
        External Connector Type: DB-9 male
        Port Type: Serial Port 16550A Compatible

Handle 0x000B, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Infrared
        External Connector Type: Infrared
        Port Type: Serial Port 16550A Compatible

Handle 0x000C, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Mouse
        External Connector Type: PS/2
        Port Type: Mouse Port

Handle 0x000D, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: USB-1
        External Connector Type: Access Bus (USB)
        Port Type: USB

Handle 0x000E, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: USB-2
        External Connector Type: Access Bus (USB)
        Port Type: USB

Handle 0x000F, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Modem
        External Connector Type: RJ-11
        Port Type: Modem Port

Handle 0x0010, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: LAN
        External Connector Type: RJ-45
        Port Type: Network Port

Handle 0x0011, DMI type 126, 9 bytes
Inactive

Handle 0x0012, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: CardBus-1
        External Connector Type: 68 Pin Dual Inline
        Port Type: Cardbus

Handle 0x0013, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: CardBus-2
        External Connector Type: 68 Pin Dual Inline
        Port Type: Cardbus

Handle 0x0014, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Mic In
        External Connector Type: Mini Jack (headphones)
        Port Type: Audio Port

Handle 0x0015, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Headphone
        External Connector Type: Mini Jack (headphones)
        Port Type: Audio Port

Handle 0x0016, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Monitor
        External Connector Type: DB-15 female
        Port Type: Video Port

Handle 0x0017, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Floppy Disk
        External Connector Type: Other
        Port Type: Other

Handle 0x0018, DMI type 8, 9 bytes
Port Connector Information
        Internal Reference Designator: Not Specified
        Internal Connector Type: None
        External Reference Designator: Connector Box
        External Connector Type: Other
        Port Type: Other

Handle 0x0019, DMI type 9, 13 bytes
System Slot Information
        Designation: CardBus-1
        Type: 32-bit PC Card (PCMCIA)
        Current Usage: Unknown
        Length: Other
        ID: Adapter 0, Socket 0
        Characteristics:
                5.0 V is provided
                3.3 V is provided
                PC Card-16 is supported
                Cardbus is supported
                Modem ring resume is supported
                PME signal is supported

Handle 0x001A, DMI type 9, 13 bytes
System Slot Information
        Designation: CardBus-2
        Type: 32-bit PC Card (PCMCIA)
        Current Usage: Unknown
        Length: Other
        ID: Adapter 1, Socket 0
        Characteristics:
                5.0 V is provided
                3.3 V is provided
                PC Card-16 is supported
                Cardbus is supported
                Modem ring resume is supported
                PME signal is supported

Handle 0x001B, DMI type 13, 22 bytes
BIOS Language Information
        Installable Languages: 2
                enUS
                jaJP
        Currently Installed Language: enUS

Handle 0x001C, DMI type 15, 35 bytes
System Event Log
        Area Length: 48 bytes
        Header Start Offset: 0x0000
        Header Length: 16 bytes
        Data Start Offset: 0x0010
        Access Method: Memory-mapped physical 32-bit address
        Access Address: 0xFFF80000
        Status: Valid, Not Full
        Change Token: 0x00000059
        Header Format: Type 1
        Supported Log Type Descriptors: 6
        Descriptor 1: POST memory resize
        Data Format 1: None
        Descriptor 2: POST error
        Data Format 2: POST results bitmap
        Descriptor 3: System reconfigured
        Data Format 3: None
        Descriptor 4: Log area reset/cleared
        Data Format 4: None
        Descriptor 5: System boot
        Data Format 5: None
        Descriptor 6: OEM-specific
        Data Format 6: None

Handle 0x001D, DMI type 16, 15 bytes
Physical Memory Array
        Location: System Board Or Motherboard
        Use: System Memory
        Error Correction Type: None
        Maximum Capacity: 256 MB
        Error Information Handle: Not Provided
        Number Of Devices: 1

Handle 0x001E, DMI type 17, 23 bytes
Memory Device
        Array Handle: 0x001D
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 128 MB
        Form Factor: DIMM
        Set: None
        Locator: DIMM1
        Bank Locator: Bank 0/1
        Type: SDRAM
        Type Detail: Synchronous
        Speed: 100 MHz (10.0 ns)

Handle 0x001F, DMI type 19, 15 bytes
Memory Array Mapped Address
        Starting Address: 0x00000000000
        Ending Address: 0x00007FFFFFF
        Range Size: 128 MB
        Physical Array Handle: 0x001D
        Partition Width: 0

Handle 0x0020, DMI type 20, 19 bytes
Memory Device Mapped Address
        Starting Address: 0x00000000000
        Ending Address: 0x00007FFFFFF
        Range Size: 128 MB
        Physical Device Handle: 0x001E
        Memory Array Mapped Address Handle: 0x001F
        Partition Row Position: 1

Handle 0x0021, DMI type 21, 7 bytes
Built-in Pointing Device
        Type: Other
        Interface: PS/2
        Buttons: 2

Handle 0x0022, DMI type 126, 26 bytes
Inactive

Handle 0x0023, DMI type 126, 26 bytes
Inactive

Handle 0x0024, DMI type 24, 5 bytes
Hardware Security
        Power-On Password Status: Disabled
        Keyboard Password Status: Disabled
        Administrator Password Status: Enabled
        Front Panel Reset Status: Not Implemented

Handle 0x0025, DMI type 32, 11 bytes
System Boot Information
        Status: No errors detected

Handle 0x0026, DMI type 143, 16 bytes
OEM-specific Type
        Header and Data:
                8F 10 26 00 00 5F 46 4A 5F 4F 45 4D 5F 10 00 00
        Strings:
                ..'
                ..

Handle 0x0027, DMI type 143, 8 bytes
OEM-specific Type
        Header and Data:
                8F 08 27 00 01 03 00 00
        Strings:
                ..(

Handle 0x0028, DMI type 127, 4 bytes
End Of Table
-- 
Der GMX SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen! 
Ideal f?r Modem und ISDN: http://www.gmx.net/de/go/smartsurfer



From darmawan.salihun at gmail.com  Mon Apr  7 09:23:54 2008
From: darmawan.salihun at gmail.com (Darmawan Salihun)
Date: Mon, 7 Apr 2008 14:23:54 +0700
Subject: [coreboot] Offtopic - Request for opinions...
In-Reply-To: <47F68CE9.9070708@gnat.ca>
References: <47F68CE9.9070708@gnat.ca>
Message-ID: <46893e740804070023w4a635fc1mc91e8183a6ae4625@mail.gmail.com>

On Sat, Apr 5, 2008 at 3:17 AM, Nathanael D. Noblet <nathanael at gnat.ca> wrote:
> Hello,
>    Long time lurker, and old time attempter... (waay back in v1 with an
>  sis 535 or something like that)...  Anyway, I have a project that our
>  company may be undertaking and some of it relies on instant on / small
>  form factor computers. Think kiosk type system. We'll be running linux,
>  custom built or one of the super small distros, built to run off a CF
>  card or boot off the network. Here's where I've got some questions that
>  I imagine people on this list may have some expertise.
>
>    We'd hope to have something that has hardware accelerated graphics
>  capabilities (likely using DirectFB for graphics) so something that has
>  linux drivers would be a major plus. We'd potentially like to use more
>  than one monitor per device. We don't need many of the common parts on a
>  regular PC or mini-ITX type boards, but are wondering what kind of
>  company you would approach to get something like that built. We'd like
>  to have coreboot as the bios to help with boot times etc. If you were
>  looking for something like that, where would you go? Most of the miniITX
>   boards don't quite fit the need. I'm wondering what volumes you'd need
>  for a custom board to reach that same price, considering we'd really
>  have very little on the device, cpu, ram, cf, video and a network. Which
>    I guess describes almost all computers... Anyway, pointers on where
>  to purchase, or get a board developed that could do stuff like this.
>  We've initially contemplated the Via boards, but have seen that there
>  are more and more offerings out there. The Geode based systems could be
>  fine if there was hardware assistance for the graphics we imagine...
>  Anyway, any pointers on a stuff like this would be appreciated.

Does an AMD 690G system fit your requirement? it has two video outputs,
most vendors implement one as regular VGA and the other one as HDMI.
It has solid ATI Linux driver ( I have test it both in x86 32-bit and
x86_64 Linux).
The driver takes quite a large space though, but I think your CF will be enough
to host it. As for the Linux BIOS support, I think AMD already working
on it but
not released publicly yet, for high volumes "client" like your need, AMD might
be giving special assistance or something, ask the AMD guys here ;-).

-- 
Regards,

Darmawan Salihun
--------------------------------------------------------------------
-= Human knowledge belongs to the world =-



From savchenko at altell.ru  Mon Apr  7 10:42:15 2008
From: savchenko at altell.ru (Mikhail Savchenko)
Date: Mon, 7 Apr 2008 12:42:15 +0400
Subject: [coreboot] grub2 with corebootv2
Message-ID: <002b01c8988b$48673aa0$d935afe0$@ru>

Does anybody have success experience running corebootv2 with grub2 as
payload?

I'm build and trying to run grun2 from repo on coreboot site which, as I
see, already have phdr patch for running with corebootv2,  but I  doesn't
have any success.

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From klaus123 at ibnoetzold.de  Mon Apr  7 12:25:28 2008
From: klaus123 at ibnoetzold.de (Klaus Stammermann)
Date: Mon, 7 Apr 2008 12:25:28 +0200 (CEST)
Subject: [coreboot] Device mapping problem
In-Reply-To: <20080401154556.GD19364@greenwood>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
	<20080401154556.GD19364@greenwood>
Message-ID: <52711.87.122.23.245.1207563928.squirrel@www.ibnoetzold.de>

> On Tue, Apr 01, 2008 at 01:55:34PM +0200, Klaus Stammermann wrote:
>> At first I can't boot my system with coreboot yet. I changed kernel
>> params
>> so initrd now will be loaded. Used kernel params are now same as in lilo
>> of original system.
>
> What does 'cat /proc/cmdline' on the same disk (but booted with the
> original BIOS) say?
>

auto BOOT IMAGE=Zenwalk ro root=801 splash=silent

I will try these kernel parameters and show results here.

Greetings
Klaus



From klaus123 at ibnoetzold.de  Mon Apr  7 12:42:28 2008
From: klaus123 at ibnoetzold.de (Klaus Stammermann)
Date: Mon, 7 Apr 2008 12:42:28 +0200 (CEST)
Subject: [coreboot] Device mapping problem
In-Reply-To: <47F3601F.3060706@coresystems.de>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
	<20080401154556.GD19364@greenwood> <47F3601F.3060706@coresystems.de>
Message-ID: <57454.87.122.23.245.1207564948.squirrel@www.ibnoetzold.de>

> Uwe Hermann wrote:
>>> And of course on original bios system DMI 2.2 is started. On coreboot
>>> DMI
>>> is not present or is invalid.
>>>
>>
>> Not a problem, either. coreboot doesn't provide DMI (not needed).
>>
>>
> That's not entirely true anymore. Nowadays Linux disables ACPI if DMI is
> not present. That results mostl likely in interrupts not working anymore.
>
> Klaus, can you try acpi=force on the kernel command line and see if that
> helps?
>

I tried acpi=force but it didn't solve my problem. I will try other params
for kernel to set root dir. Here is starting log with that parameter:

0

coreboot-2.0.0.0-Fallback Mo 7. Apr 12:26:47 CEST 2008 starting...
 Enabling mainboard devices
 Enabling shadow ram
vt8623 init starting
Detecting Memory
Number of Banks 04
Number of Rows 0d
Priamry DRAM width08
No Columns 0a
MA type e0
Bank 0 (*16 Mb) 10
No Physical Banks 01
Total Memory (*16 Mb) 10
CAS Supported 2.5 3
Cycle time at CL X     (nS)50
Cycle time at CL X-0.5 (nS)60
Cycle time at CL X-1   (nS)00
Starting at CAS 3
We can do CAS 2.5
tRP 3c
tRCD 3c
tRAS 28
Low Bond 00  High Bondcc  Setting DQS delay88vt8623 done
00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00
10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00
20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00
50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00
60:02 ff 00 30 62 32 01 20 42 2d 43 58 00 44 00 00
70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 10
80:0f 60 00 00 80 00 00 00 02 00 00 00 00 00 00 00
90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00
b0:00 00 00 00 80 00 00 00 88 00 00 04 00 00 00 00
c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00
f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00
AGP
 Doing MTRR init.
Copying coreboot to RAM.
Jumping to coreboot.
coreboot-2.0.0.0-Fallback Mo 7. Apr 12:26:47 CEST 2008 booting...
clocks_per_usec: 1378
Enumerating buses...
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0001 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1106/3123] enabled
PCI: 00:01.0 [1106/b091] enabled
PCI: 00:0d.0 [1106/3044] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.0 [1106/3038] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.1 [1106/3038] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.2 [1106/3038] enabled
In vt8235_enable ffff ffff.
Disabling static device: PCI: 00:10.3
In vt8235_enable 1106 3177.
Initialising Devices
Keyboard init...
PCI: 00:11.0 [1106/3177] enabled
In vt8235_enable 1106 0571.
PCI: 00:11.1 [1106/0571] enabled
In vt8235_enable 1106 3059.
PCI: 00:11.5 [1106/3059] enabled
In vt8235_enable 1106 3068.
PCI: 00:11.6 [1106/3068] disabled
In vt8235_enable 1106 3065.
PCI: 00:12.0 [1106/3065] enabled
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1106/3122] enabled
PCI: pci_scan_bus returning with max=001
vt1211 enabling PNP devices.
PNP: 002e.0 enabled
vt1211 enabling PNP devices.
PNP: 002e.1 enabled
vt1211 enabling PNP devices.
PNP: 002e.2 enabled
vt1211 enabling PNP devices.
PNP: 002e.3 enabled
vt1211 enabling PNP devices.
PNP: 002e.b enabled
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1106/3123] enabled
PCI: 00:01.0 [1106/b091] enabled
PCI: 00:0d.0 [1106/3044] enabled
PCI: 00:10.0 [1106/3038] enabled
PCI: 00:10.1 [1106/3038] enabled
PCI: 00:10.2 [1106/3038] enabled
PCI: 00:10.3 [1106/3104] enabled
PCI: 00:11.0 [1106/3177] enabled
PCI: 00:11.1 [1106/0571] enabled
PCI: 00:11.5 [1106/3059] enabled
PCI: 00:11.6 [1106/3068] enabled
PCI: 00:12.0 [1106/3065] enabled
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [1106/3122] enabled
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus returning with max=002
done
Allocating resources...
Reading resources...
Done reading resources.
Allocating VGA resource PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0001
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
I would set ram size to 0x40000 Kbytes
PCI: 00:0d.0 10 <- [0x00febfc000 - 0x00febfc7ff] size 0x00000800 gran 0x0b
mem
PCI: 00:0d.0 14 <- [0x0000002400 - 0x000000247f] size 0x00000080 gran 0x07 io
PCI: 00:10.0 20 <- [0x0000002800 - 0x000000281f] size 0x00000020 gran 0x05 io
PCI: 00:10.1 20 <- [0x0000002820 - 0x000000283f] size 0x00000020 gran 0x05 io
PCI: 00:10.2 20 <- [0x0000002840 - 0x000000285f] size 0x00000020 gran 0x05 io
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io
PCI: 00:11.1 20 <- [0x00000028c0 - 0x00000028cf] size 0x00000010 gran 0x04 io
PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 14 <- [0x00febfe000 - 0x00febfe0ff] size 0x00000100 gran 0x08
mem
I would set ram size to 0x40000 Kbytes
PCI: 00:0d.0 10 <- [0x00febfd000 - 0x00febfd7ff] size 0x00000800 gran 0x0b
mem
PCI: 00:0d.0 14 <- [0x0000002480 - 0x00000024ff] size 0x00000080 gran 0x07 io
PCI: 00:10.0 20 <- [0x0000002860 - 0x000000287f] size 0x00000020 gran 0x05 io
PCI: 00:10.1 20 <- [0x0000002880 - 0x000000289f] size 0x00000020 gran 0x05 io
PCI: 00:10.2 20 <- [0x00000028a0 - 0x00000028bf] size 0x00000020 gran 0x05 io
PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] size 0x00000100 gran 0x08
mem
PCI: 00:11.1 20 <- [0x00000028d0 - 0x00000028df] size 0x00000010 gran 0x04 io
PCI: 00:11.5 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
PCI: 00:11.6 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] size 0x00000100 gran 0x08
mem
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000f
PCI: 00:01.0 cmd <- 07
PCI: 01:00.0 cmd <- ffff
PCI: 00:0d.0 cmd <- 83
PCI: 00:10.0 subsystem <- 00/00
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 subsystem <- 00/00
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 subsystem <- 00/00
PCI: 00:10.2 cmd <- 01
PCI: 00:11.0 cmd <- 07
PNP: 002e.0 - enabling
PNP: 002e.1 - enabling
PNP: 002e.2 - enabling
PNP: 002e.3 - enabling
PNP: 002e.b - enabling
PCI: 00:11.1 cmd <- 81
PCI: 00:11.5 subsystem <- 00/00
PCI: 00:11.5 cmd <- 01
PCI: 00:12.0 cmd <- 83
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000f
PCI: 00:01.0 cmd <- 07
PCI: 02:00.0 cmd <- 03
PCI: 00:0d.0 cmd <- 83
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 cmd <- 01
PCI: 00:10.3 cmd <- 02
PCI: 00:11.0 cmd <- 07
PCI: 00:11.1 cmd <- 81
PCI: 00:11.5 cmd <- 01
PCI: 00:11.6 cmd <- 01
PCI: 00:12.0 cmd <- 83
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Centaur device 698
CPU: family 06, model 09, stepping 08
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  128MB, type WB
Setting variable MTRR 1, base:  128MB, range:   64MB, type WB
Setting variable MTRR 2, base:  192MB, range:   32MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Disabling local apic...done.
CPU #0 Initialized
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:11.0 init
vt8235 init
RTC Init
RTC: Checksum invalid zeroing cmos
Invalid CMOS LB checksum
pci_routing_fixup: dev is 000114c0
setting firewire
Assigning IRQ 9 to 0:d.0
  Readback = 9
setting usb
Assigning IRQ 5 to 0:10.0
  Readback = 5
Assigning IRQ 9 to 0:10.1
  Readback = 9
Assigning IRQ 9 to 0:10.2
  Readback = 9
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting vt8235
Assigning IRQ 5 to 0:11.1
  Readback = 5
Assigning IRQ 9 to 0:11.5
  Readback = 9
Assigning IRQ 9 to 0:11.6
  Readback = 9
setting ethernet
Assigning IRQ 5 to 0:12.0
  Readback = 5
setting vga
setting pci slot
setting cardbus slot
setting riser slot
PNP: 002e.0 init
PNP: 002e.1 init
PNP: 002e.2 init
PNP: 002e.3 init
PNP: 002e.b init
PCI: 00:11.1 init
Enabling VIA IDE.
ide_init: enabling compatibility IDE addresses
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
enables in reg 0x40 0x18
enables in reg 0x40 read back as 0x1b
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x81
command in reg 0x4 reads back as 0x7
PCI: 00:11.5 init
PCI: 00:12.0 init
Configuring VIA Rhine LAN
PCI: 00:00.0 init
VT8623 random fixup ...
Frame buffer at d0000000
PCI: 00:00.0 init
VT8623 random fixup ...
Frame buffer at d0000000
PCI: 00:01.0 init
VT8623 AGP random fixup ...
PCI: 00:0d.0 init
PCI: 01:00.0 init
VGA random fixup ...
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3122
rom base, size: fffc0000
write_protect_vgabios
bus/devfn = 0x100
biosint: INT# 0x15
biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1a7d4
biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1a7d4
biosint:  ip 0x641c   cs 0xc000  flags 0x46
biosint: INT# 0x1a
biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b
biosint:  ip 0x40f0   cs 0xc000  flags 0x46
0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5
biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1a7d4
biosint:  ip 0x651b   cs 0xc000  flags 0x87
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1a7d4
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112
biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1a7d4
biosint:  ip 0x6533   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112
biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6479   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6485   cs 0xc000  flags 0x202
PCI: 00:01.0 init
VT8623 AGP random fixup ...
PCI: 00:0d.0 init
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:10.3 init
PCI: 00:11.0 init
vt8235 init
RTC Init
Invalid CMOS LB checksum
pci_routing_fixup: dev is 0001ba18
setting firewire
Assigning IRQ 9 to 0:d.0
  Readback = 9
setting usb
Assigning IRQ 5 to 0:10.0
  Readback = 5
Assigning IRQ 9 to 0:10.1
  Readback = 9
Assigning IRQ 9 to 0:10.2
  Readback = 9
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting vt8235
Assigning IRQ 5 to 0:11.1
  Readback = 5
Assigning IRQ 9 to 0:11.5
  Readback = 9
Assigning IRQ 9 to 0:11.6
  Readback = 9
setting ethernet
Assigning IRQ 5 to 0:12.0
  Readback = 5
setting vga
setting pci slot
setting cardbus slot
setting riser slot
PCI: 00:11.1 init
Enabling VIA IDE.
ide_init: enabling compatibility IDE addresses
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
enables in reg 0x40 0x1b
enables in reg 0x40 read back as 0x1b
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8f
command in reg 0x4 0x7
command in reg 0x4 reads back as 0x7
PCI: 00:11.5 init
PCI: 00:11.6 init
PCI: 00:12.0 init
Configuring VIA Rhine LAN
PCI: 02:00.0 init
VGA random fixup ...
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3122
rom base, size: fffc0000
write_protect_vgabios
bus/devfn = 0x100
biosint: INT# 0x15
biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1c724
biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1c724
biosint:  ip 0x641c   cs 0xc000  flags 0x46
biosint: INT# 0x1a
biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b
biosint:  ip 0x40f0   cs 0xc000  flags 0x46
0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5
biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1c724
biosint:  ip 0x651b   cs 0xc000  flags 0x87
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c724
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112
biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1c724
biosint:  ip 0x6533   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112
biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6479   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6485   cs 0xc000  flags 0x202
Devices initialized
Copying IRQ routing tables to 0xf0000...done.
Verifing copy of IRQ routing tables at 0xf0000...done
Checking IRQ routing table consistency...
check_pirq_routing_table() - irq_routing_table located at: 0x000f0000
done.
ACPI: Writing ACPI tables at f0400...
ACPI:     * FACS
ACPI:     * DSDT @ 000f04aa Length 3f0
ACPI:     * FADT
ACPI: added table 1/8 Length now 40
ACPI: done.
Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0c00 to 0x00100000
Wrote coreboot table at: 00000530 - 00000c0c  checksum 14e3

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

rom_stream: 0xfffd0000 - 0xfffd9f0f
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0x100000 size 0x23f00 offset 0xc0 filesize 0x9c48
(cleaned up) New segment addr 0x100000 size 0x23f00 offset 0xc0 filesize
0x9c48
New segment addr 0x123f00 size 0x48 offset 0x9d20 filesize 0x48
(cleaned up) New segment addr 0x123f00 size 0x48 offset 0x9d20 filesize 0x48
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000023f00
filesz: 0x0000000000009c48
Clearing Segment: addr: 0x0000000000109c48 memsz: 0x000000000001a2b8
Loading Segment: addr: 0x0000000000123f00 memsz: 0x0000000000000048
filesz: 0x0000000000000048
Jumping to boot code at 0x107f1c
FILO version 0.5 (klausst at thor) Mon Apr  7 12:22:21 CEST 2008
No sound device found
boot: hda1:/boot/vmlinuz root=/dev/sda1 initrd=/boot/initrd.splash
acpi=force earlyprintk=serial,ttyS0,115200 console=tty0
console=ttyS0,115200
hda: LBA 2049MB: SanDisk SDCFX-2048
Mounted ext2fs
Found Linux version 2.6.18.2-34-default (geeko at buildhost) #1 SMP Mon Nov
27 11:46:27 UTC 2006 bzImage.
Loading kernel... ok
Loading initrd... ok
Jumping to entry point...
Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
 BIOS-e820: 0000000000100000 - 000000000e000000 (usable)
early console enabled
0MB HIGHMEM available.
224MB LOWMEM available.
DMI not present or invalid.
Using APIC driver default
IO/L-APIC disabled because your old system seems to be old
overwrite with "apic"
ACPI: acpi=force override
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 10000000 (gap: 0e000000:f2000000)
Detected 599.732 MHz processor.
Built 1 zonelists.  Total pages: 57344
Kernel command line: root=/dev/sda1 acpi=force
earlyprintk=serial,ttyS0,115200 console=tty0 console=ttyS0,115200
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
PID hash table entries: 1024 (order: 10, 4096 bytes)
disabling early console
Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
 BIOS-e820: 0000000000100000 - 000000000e000000 (usable)
early console enabled
0MB HIGHMEM available.
224MB LOWMEM available.
DMI not present or invalid.
Using APIC driver default
IO/L-APIC disabled because your old system seems to be old
overwrite with "apic"
ACPI: acpi=force override
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 10000000 (gap: 0e000000:f2000000)
Detected 599.732 MHz processor.
Built 1 zonelists.  Total pages: 57344
Kernel command line: root=/dev/sda1 acpi=force
earlyprintk=serial,ttyS0,115200 console=tty0 console=ttyS0,115200
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
PID hash table entries: 1024 (order: 10, 4096 bytes)
disabling early console
Console: colour VGA+ 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 222892k/229376k available (1697k kernel code, 6008k reserved, 968k
data, 196k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 1201.26 BogoMIPS
(lpj=2402521)
Security Framework v1.0.0 initialized
Mount-cache hash table entries: 512
CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line)
CPU: L2 Cache: 64K (32 bytes/line)
Compat vDSO mapped to ffffe000.
Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
Freeing SMP alternatives: 16k freed
checking if image is initramfs...it isn't (bad gzip magic numbers); looks
like an initrd
Freeing initrd memory: 622k freed
ACPI: Core revision 20060707
ACPI: setting ELCR to 0020 (from 0220)
CPU0: Centaur VIA Nehemiah stepping 08
SMP motherboard not detected.
Local APIC not detected. Using dummy APIC emulation.
Brought up 1 CPUs
migration_cost=0
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: Using configuration type 1
Setting up standard PCI resources
irq 5: nobody cared (try booting with the "irqpoll" option)
 [<c0146772>] __report_bad_irq+0x36/0x7d
 [<c0146968>] note_interrupt+0x1af/0x1eb
 [<c01ea916>] acpi_ev_sci_xrupt_handler+0x12/0x19
 [<c01e5562>] acpi_irq+0xb/0x14
 [<c0145ed6>] handle_IRQ_event+0x23/0x49
 [<c0145fb5>] __do_IRQ+0xb9/0xee
 [<c01067aa>] do_IRQ+0x71/0x83
 [<c0104e1a>] common_interrupt+0x1a/0x20
 [<c0124db8>] __do_softirq+0x51/0xbb
 [<c0124e58>] do_softirq+0x36/0x3a
 [<c01067af>] do_IRQ+0x76/0x83
 [<c0104e1a>] common_interrupt+0x1a/0x20
 [<c01465a2>] setup_irq+0x132/0x190
 [<c01e5557>] acpi_irq+0x0/0x14
 [<c014667c>] request_irq+0x7c/0x98
 [<c01ea904>] acpi_ev_sci_xrupt_handler+0x0/0x19
 [<c01e5b96>] acpi_os_install_interrupt_handler+0x60/0x8d
 [<c01e5557>] acpi_irq+0x0/0x14
 [<c01e9ff0>] acpi_ev_install_xrupt_handlers+0x9/0x61
 [<c01ea429>] acpi_ev_install_region_handlers+0x62/0x69
 [<c01fb792>] acpi_enable_subsystem+0x86/0xa6
 [<c03b7afd>] acpi_init+0x54/0x1f2
 [<c0226b45>] class_create+0x40/0x56
 [<c03b61ce>] fbmem_init+0x5b/0x86
 [<c0100414>] init+0x118/0x2bc
 [<c0103ca6>] ret_from_fork+0x6/0x20
 [<c01002fc>] init+0x0/0x2bc
 [<c01002fc>] init+0x0/0x2bc
 [<c0102005>] kernel_thread_helper+0x5/0xb
handlers:
[<c01e5557>] (acpi_irq+0x0/0x14)
Disabling IRQ #5
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Interrupt Link [LNKA] (IRQs *5 9 10)
ACPI: PCI Interrupt Link [LNKB] (IRQs 5 *9 10)
ACPI: PCI Interrupt Link [LNKC] (IRQs 5 *9 10)
ACPI: PCI Interrupt Link [LNKD] (IRQs *5 9 10)
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI quirk: region 0400-047f claimed by vt8235 PM
PCI quirk: region 0f00-0f0f claimed by vt8235 SMB
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 0 devices
PnPBIOS: Disabled by ACPI PNP
PCI: Using ACPI for IRQ routing
PCI: If a device doesn't work, try "pci=routeirq".  If it helps, post a
report
PCI: Bridge: 0000:00:01.0
  IO window: disabled.
  MEM window: dc000000-ddffffff
  PREFETCH window: d8000000-dbffffff
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 4096)
TCP reno registered
apm: BIOS not found.
audit: initializing netlink socket (disabled)
audit(1207572089.092:1): initialized
Total HugeTLB memory allocated, 0
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
isapnp: Scanning for PnP cards...
isapnp: No Plug & Play device found
Real Time Clock Driver v1.12ac
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
PNP: No PS/2 controller found. Probing ports directly.
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
mice: PS/2 mouse device common for all mice
input: PC Speaker as /class/input/input0
input: AT Translated Set 2 keyboard as /class/input/input1
input: ImExPS/2 Generic Explorer Mouse as /class/input/input2
md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
md: bitmap version 4.39
NET: Registered protocol family 1
Using IPI No-Shortcut mode
ACPI: (supports<6>Time: tsc clocksource has been installed.
 S0 S5)
md: Autodetecting RAID arrays.
md: autorun ...
md: ... autorun DONE.
RAMDISK: Couldn't find valid RAM disk image starting at 0.
VFS: Cannot open root device "sda1" or unknown-block(0,0)
Please append a correct "root=" boot option
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(0,0)



From klaus123 at ibnoetzold.de  Mon Apr  7 13:09:15 2008
From: klaus123 at ibnoetzold.de (Klaus Stammermann)
Date: Mon, 7 Apr 2008 13:09:15 +0200 (CEST)
Subject: [coreboot] Device mapping problem
In-Reply-To: <20080401154556.GD19364@greenwood>
References: <39859.87.122.21.88.1207050934.squirrel@www.ibnoetzold.de>
	<20080401154556.GD19364@greenwood>
Message-ID: <45143.87.122.23.245.1207566555.squirrel@www.ibnoetzold.de>

>> boot: hda1:/boot/vmlinuz root=/dev/sda1 initrd=/boot/initrd.splash
>> console=tty0 console=ttyS0,115200
>
> This is the interesting part. Are you sure FILO views your disk
> (CF card?) as hda1? Is your /boot an extra partition (mount point) or is
> it part of the "/" filesystem on hda1?
>
> Are you sure Linux views your disk (CF card?) as /dev/sda1? Did you try
> /dev/sdb1?
>
On Linux my disk is mounted as /dev/sda1 on system with original BIOS. So
I didn't try others like /dev/sdb1.

> The dmesg from below says:
>   Kernel command line: BOOT_IMAGE=Zenwalk ro root=801 splash=silent
> which is quite different. Where does this stuff come from?
>
> I'd also use "splash=silent" in FILO for now, btw.
>
> Have you tried "root=801" instead of "root=/dev/sda1" in FILO (no idea
> what 801 is)?
>
"root=801" is written by automated installation of Zenwalk and is used by
Lilo. I just tried this parameter with coreboot, but there is no great
different by using this.

Log with acpi=force and root=801:

0

coreboot-2.0.0.0-Fallback Mo 7. Apr 12:53:17 CEST 2008 starting...
 Enabling mainboard devices
 Enabling shadow ram
vt8623 init starting
Detecting Memory
Number of Banks 04
Number of Rows 0d
Priamry DRAM width08
No Columns 0a
MA type e0
Bank 0 (*16 Mb) 10
No Physical Banks 01
Total Memory (*16 Mb) 10
CAS Supported 2.5 3
Cycle time at CL X     (nS)50
Cycle time at CL X-0.5 (nS)60
Cycle time at CL X-1   (nS)00
Starting at CAS 3
We can do CAS 2.5
tRP 3c
tRCD 3c
tRAS 28
Low Bond 00  High Bondcd  Setting DQS delay88vt8623 done
00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00
10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00
20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00
50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00
60:02 ff 00 30 62 32 01 20 42 2d 43 58 00 44 00 00
70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 10
80:0f 60 00 00 80 00 00 00 02 00 00 00 00 00 00 00
90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00
b0:00 00 00 00 80 00 00 00 88 00 00 04 00 00 00 00
c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00
f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00
AGP
 Doing MTRR init.
Copying coreboot to RAM.
Jumping to coreboot.
coreboot-2.0.0.0-Fallback Mo 7. Apr 12:54:44 CEST 2008 booting...
clocks_per_usec: 1378
Enumerating buses...
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0001 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1106/3123] enabled
PCI: 00:01.0 [1106/b091] enabled
PCI: 00:0d.0 [1106/3044] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.0 [1106/3038] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.1 [1106/3038] enabled
In vt8235_enable 1106 3038.
PCI: 00:10.2 [1106/3038] enabled
In vt8235_enable ffff ffff.
Disabling static device: PCI: 00:10.3
In vt8235_enable 1106 3177.
Initialising Devices
Keyboard init...
PCI: 00:11.0 [1106/3177] enabled
In vt8235_enable 1106 0571.
PCI: 00:11.1 [1106/0571] enabled
In vt8235_enable 1106 3059.
PCI: 00:11.5 [1106/3059] enabled
In vt8235_enable 1106 3068.
PCI: 00:11.6 [1106/3068] disabled
In vt8235_enable 1106 3065.
PCI: 00:12.0 [1106/3065] enabled
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1106/3122] enabled
PCI: pci_scan_bus returning with max=001
vt1211 enabling PNP devices.
PNP: 002e.0 enabled
vt1211 enabling PNP devices.
PNP: 002e.1 enabled
vt1211 enabling PNP devices.
PNP: 002e.2 enabled
vt1211 enabling PNP devices.
PNP: 002e.3 enabled
vt1211 enabling PNP devices.
PNP: 002e.b enabled
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1106/3123] enabled
PCI: 00:01.0 [1106/b091] enabled
PCI: 00:0d.0 [1106/3044] enabled
PCI: 00:10.0 [1106/3038] enabled
PCI: 00:10.1 [1106/3038] enabled
PCI: 00:10.2 [1106/3038] enabled
PCI: 00:10.3 [1106/3104] enabled
PCI: 00:11.0 [1106/3177] enabled
PCI: 00:11.1 [1106/0571] enabled
PCI: 00:11.5 [1106/3059] enabled
PCI: 00:11.6 [1106/3068] enabled
PCI: 00:12.0 [1106/3065] enabled
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [1106/3122] enabled
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus returning with max=002
done
Allocating resources...
Reading resources...
Done reading resources.
Allocating VGA resource PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0001
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
I would set ram size to 0x40000 Kbytes
PCI: 00:0d.0 10 <- [0x00febfc000 - 0x00febfc7ff] size 0x00000800 gran 0x0b
mem
PCI: 00:0d.0 14 <- [0x0000002400 - 0x000000247f] size 0x00000080 gran 0x07 io
PCI: 00:10.0 20 <- [0x0000002800 - 0x000000281f] size 0x00000020 gran 0x05 io
PCI: 00:10.1 20 <- [0x0000002820 - 0x000000283f] size 0x00000020 gran 0x05 io
PCI: 00:10.2 20 <- [0x0000002840 - 0x000000285f] size 0x00000020 gran 0x05 io
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io
PCI: 00:11.1 20 <- [0x00000028c0 - 0x00000028cf] size 0x00000010 gran 0x04 io
PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 14 <- [0x00febfe000 - 0x00febfe0ff] size 0x00000100 gran 0x08
mem
I would set ram size to 0x40000 Kbytes
PCI: 00:0d.0 10 <- [0x00febfd000 - 0x00febfd7ff] size 0x00000800 gran 0x0b
mem
PCI: 00:0d.0 14 <- [0x0000002480 - 0x00000024ff] size 0x00000080 gran 0x07 io
PCI: 00:10.0 20 <- [0x0000002860 - 0x000000287f] size 0x00000020 gran 0x05 io
PCI: 00:10.1 20 <- [0x0000002880 - 0x000000289f] size 0x00000020 gran 0x05 io
PCI: 00:10.2 20 <- [0x00000028a0 - 0x00000028bf] size 0x00000020 gran 0x05 io
PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] size 0x00000100 gran 0x08
mem
PCI: 00:11.1 20 <- [0x00000028d0 - 0x00000028df] size 0x00000010 gran 0x04 io
PCI: 00:11.5 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
PCI: 00:11.6 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] size 0x00000100 gran 0x08
mem
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000f
PCI: 00:01.0 cmd <- 07
PCI: 01:00.0 cmd <- ffff
PCI: 00:0d.0 cmd <- 83
PCI: 00:10.0 subsystem <- 00/00
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 subsystem <- 00/00
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 subsystem <- 00/00
PCI: 00:10.2 cmd <- 01
PCI: 00:11.0 cmd <- 07
PNP: 002e.0 - enabling
PNP: 002e.1 - enabling
PNP: 002e.2 - enabling
PNP: 002e.3 - enabling
PNP: 002e.b - enabling
PCI: 00:11.1 cmd <- 81
PCI: 00:11.5 subsystem <- 00/00
PCI: 00:11.5 cmd <- 01
PCI: 00:12.0 cmd <- 83
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000f
PCI: 00:01.0 cmd <- 07
PCI: 02:00.0 cmd <- 03
PCI: 00:0d.0 cmd <- 83
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 cmd <- 01
PCI: 00:10.3 cmd <- 02
PCI: 00:11.0 cmd <- 07
PCI: 00:11.1 cmd <- 81
PCI: 00:11.5 cmd <- 01
PCI: 00:11.6 cmd <- 01
PCI: 00:12.0 cmd <- 83
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Centaur device 698
CPU: family 06, model 09, stepping 08
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  128MB, type WB
Setting variable MTRR 1, base:  128MB, range:   64MB, type WB
Setting variable MTRR 2, base:  192MB, range:   32MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Disabling local apic...done.
CPU #0 Initialized
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:11.0 init
vt8235 init
RTC Init
RTC: Checksum invalid zeroing cmos
Invalid CMOS LB checksum
pci_routing_fixup: dev is 000114c0
setting firewire
Assigning IRQ 9 to 0:d.0
  Readback = 9
setting usb
Assigning IRQ 5 to 0:10.0
  Readback = 5
Assigning IRQ 9 to 0:10.1
  Readback = 9
Assigning IRQ 9 to 0:10.2
  Readback = 9
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting vt8235
Assigning IRQ 5 to 0:11.1
  Readback = 5
Assigning IRQ 9 to 0:11.5
  Readback = 9
Assigning IRQ 9 to 0:11.6
  Readback = 9
setting ethernet
Assigning IRQ 5 to 0:12.0
  Readback = 5
setting vga
setting pci slot
setting cardbus slot
setting riser slot
PNP: 002e.0 init
PNP: 002e.1 init
PNP: 002e.2 init
PNP: 002e.3 init
PNP: 002e.b init
PCI: 00:11.1 init
Enabling VIA IDE.
ide_init: enabling compatibility IDE addresses
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
enables in reg 0x40 0x18
enables in reg 0x40 read back as 0x1b
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8a
command in reg 0x4 0x81
command in reg 0x4 reads back as 0x7
PCI: 00:11.5 init
PCI: 00:12.0 init
Configuring VIA Rhine LAN
PCI: 00:00.0 init
VT8623 random fixup ...
Frame buffer at d0000000
PCI: 00:00.0 init
VT8623 random fixup ...
Frame buffer at d0000000
PCI: 00:01.0 init
VT8623 AGP random fixup ...
PCI: 00:0d.0 init
PCI: 01:00.0 init
VGA random fixup ...
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3122
rom base, size: fffc0000
write_protect_vgabios
bus/devfn = 0x100
biosint: INT# 0x15
biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1a7d4
biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1a7d4
biosint:  ip 0x641c   cs 0xc000  flags 0x46
biosint: INT# 0x1a
biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b
biosint:  ip 0x40f0   cs 0xc000  flags 0x46
0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5
biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1a7d4
biosint:  ip 0x651b   cs 0xc000  flags 0x87
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1a7d4
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112
biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1a7d4
biosint:  ip 0x6533   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112
biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6479   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6485   cs 0xc000  flags 0x202
PCI: 00:01.0 init
VT8623 AGP random fixup ...
PCI: 00:0d.0 init
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:10.3 init
PCI: 00:11.0 init
vt8235 init
RTC Init
Invalid CMOS LB checksum
pci_routing_fixup: dev is 0001ba18
setting firewire
Assigning IRQ 9 to 0:d.0
  Readback = 9
setting usb
Assigning IRQ 5 to 0:10.0
  Readback = 5
Assigning IRQ 9 to 0:10.1
  Readback = 9
Assigning IRQ 9 to 0:10.2
  Readback = 9
Assigning IRQ 5 to 0:10.3
  Readback = 5
setting vt8235
Assigning IRQ 5 to 0:11.1
  Readback = 5
Assigning IRQ 9 to 0:11.5
  Readback = 9
Assigning IRQ 9 to 0:11.6
  Readback = 9
setting ethernet
Assigning IRQ 5 to 0:12.0
  Readback = 5
setting vga
setting pci slot
setting cardbus slot
setting riser slot
PCI: 00:11.1 init
Enabling VIA IDE.
ide_init: enabling compatibility IDE addresses
enables in reg 0x42 0x9
enables in reg 0x42 read back as 0x9
enables in reg 0x40 0x1b
enables in reg 0x40 read back as 0x1b
enables in reg 0x9 0x8a
enables in reg 0x9 read back as 0x8f
command in reg 0x4 0x7
command in reg 0x4 reads back as 0x7
PCI: 00:11.5 init
PCI: 00:11.6 init
PCI: 00:12.0 init
Configuring VIA Rhine LAN
PCI: 02:00.0 init
VGA random fixup ...
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3122
rom base, size: fffc0000
write_protect_vgabios
bus/devfn = 0x100
biosint: INT# 0x15
biosint: eax 0x5f00 ebx 0x1a7d4 ecx 0x19f8c edx 0x1c724
biosint: ebp 0x19f54 esp 0xff2 edi 0xf9b0 esi 0x1c724
biosint:  ip 0x641c   cs 0xc000  flags 0x46
biosint: INT# 0x1a
biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b
biosint:  ip 0x40f0   cs 0xc000  flags 0x46
0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x12
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112
biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f0f ebx 0x1a7d4 ecx 0x9f8c edx 0x103d5
biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1c724
biosint:  ip 0x651b   cs 0xc000  flags 0x87
biosint: INT# 0x15
biosint: eax 0x5f02 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c724
biosint:  ip 0x6468   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112
biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112
biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f18 ebx 0x1a7d4 ecx 0x9f01 edx 0x103d5
biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1c724
biosint:  ip 0x6533   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x46
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112
biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112
biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f06 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6479   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010101 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010000 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f01 ebx 0x10c01 ecx 0x80010001 edx 0x112
biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd
biosint:  ip 0x6448   cs 0xc000  flags 0x246
biosint: INT# 0x15
biosint: eax 0x5f08 ebx 0x18001 ecx 0x80010001 edx 0x0
biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7
biosint:  ip 0x6485   cs 0xc000  flags 0x202
Devices initialized
Copying IRQ routing tables to 0xf0000...done.
Verifing copy of IRQ routing tables at 0xf0000...done
Checking IRQ routing table consistency...
check_pirq_routing_table() - irq_routing_table located at: 0x000f0000
done.
ACPI: Writing ACPI tables at f0400...
ACPI:     * FACS
ACPI:     * DSDT @ 000f04aa Length 3f0
ACPI:     * FADT
ACPI: added table 1/8 Length now 40
ACPI: done.
Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0c00 to 0x00100000
Wrote coreboot table at: 00000530 - 00000c0c  checksum 15df

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

rom_stream: 0xfffd0000 - 0xfffd9f0f
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0x100000 size 0x23f00 offset 0xc0 filesize 0x9c48
(cleaned up) New segment addr 0x100000 size 0x23f00 offset 0xc0 filesize
0x9c48
New segment addr 0x123f00 size 0x48 offset 0x9d20 filesize 0x48
(cleaned up) New segment addr 0x123f00 size 0x48 offset 0x9d20 filesize 0x48
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000023f00
filesz: 0x0000000000009c48
Clearing Segment: addr: 0x0000000000109c48 memsz: 0x000000000001a2b8
Loading Segment: addr: 0x0000000000123f00 memsz: 0x0000000000000048
filesz: 0x0000000000000048
Jumping to boot code at 0x107f1c
FILO version 0.5 (klausst at thor) Mon Apr  7 12:51:24 CEST 2008
No sound device found
boot: hda1:/boot/vmlinuz root=801 initrd=/boot/initrd.splash acpi=force
earlyprintk=serial,ttyS0,115200 console=tty0 console=ttyS0,115200
hda: LBA 2049MB: SanDisk SDCFX-2048
Mounted ext2fs
Found Linux version 2.6.18.2-34-default (geeko at buildhost) #1 SMP Mon Nov
27 11:46:27 UTC 2006 bzImage.
Loading kernel... ok
Loading initrd... ok
Jumping to entry point...
Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
 BIOS-e820: 0000000000100000 - 000000000e000000 (usable)
early console enabled
0MB HIGHMEM available.
224MB LOWMEM available.
DMI not present or invalid.
Using APIC driver default
IO/L-APIC disabled because your old system seems to be old
overwrite with "apic"
ACPI: acpi=force override
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 10000000 (gap: 0e000000:f2000000)
Detected 599.731 MHz processor.
Built 1 zonelists.  Total pages: 57344
Kernel command line: root=801 acpi=force earlyprintk=serial,ttyS0,115200
console=tty0 console=ttyS0,115200
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
PID hash table entries: 1024 (order: 10, 4096 bytes)
disabling early console
Linux version 2.6.18.2-34-default (geeko at buildhost) (gcc version 4.1.2
20061115 (prerelease) (SUSE Linux)) #1 SMP Mon Nov 27 11:46:27 UTC 2006
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
 BIOS-e820: 0000000000100000 - 000000000e000000 (usable)
early console enabled
0MB HIGHMEM available.
224MB LOWMEM available.
DMI not present or invalid.
Using APIC driver default
IO/L-APIC disabled because your old system seems to be old
overwrite with "apic"
ACPI: acpi=force override
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 10000000 (gap: 0e000000:f2000000)
Detected 599.731 MHz processor.
Built 1 zonelists.  Total pages: 57344
Kernel command line: root=801 acpi=force earlyprintk=serial,ttyS0,115200
console=tty0 console=ttyS0,115200
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
PID hash table entries: 1024 (order: 10, 4096 bytes)
disabling early console
Console: colour VGA+ 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 222892k/229376k available (1697k kernel code, 6008k reserved, 968k
data, 196k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 1201.25 BogoMIPS
(lpj=2402519)
Security Framework v1.0.0 initialized
Mount-cache hash table entries: 512
CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line)
CPU: L2 Cache: 64K (32 bytes/line)
Compat vDSO mapped to ffffe000.
Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
Freeing SMP alternatives: 16k freed
checking if image is initramfs...it isn't (bad gzip magic numbers); looks
like an initrd
Freeing initrd memory: 622k freed
ACPI: Core revision 20060707
ACPI: setting ELCR to 0020 (from 0220)
CPU0: Centaur VIA Nehemiah stepping 08
SMP motherboard not detected.
Local APIC not detected. Using dummy APIC emulation.
Brought up 1 CPUs
migration_cost=0
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: Using configuration type 1
Setting up standard PCI resources
irq 5: nobody cared (try booting with the "irqpoll" option)
 [<c0146772>] __report_bad_irq+0x36/0x7d
 [<c0146968>] note_interrupt+0x1af/0x1eb
 [<c01ea916>] acpi_ev_sci_xrupt_handler+0x12/0x19
 [<c01e5562>] acpi_irq+0xb/0x14
 [<c0145ed6>] handle_IRQ_event+0x23/0x49
 [<c0145fb5>] __do_IRQ+0xb9/0xee
 [<c01067aa>] do_IRQ+0x71/0x83
 [<c0104e1a>] common_interrupt+0x1a/0x20
 [<c0124db8>] __do_softirq+0x51/0xbb
 [<c0124e58>] do_softirq+0x36/0x3a
 [<c01067af>] do_IRQ+0x76/0x83
 [<c0104e1a>] common_interrupt+0x1a/0x20
 [<c01465a2>] setup_irq+0x132/0x190
 [<c01e5557>] acpi_irq+0x0/0x14
 [<c014667c>] request_irq+0x7c/0x98
 [<c01ea904>] acpi_ev_sci_xrupt_handler+0x0/0x19
 [<c01e5b96>] acpi_os_install_interrupt_handler+0x60/0x8d
 [<c01e5557>] acpi_irq+0x0/0x14
 [<c01e9ff0>] acpi_ev_install_xrupt_handlers+0x9/0x61
 [<c01ea429>] acpi_ev_install_region_handlers+0x62/0x69
 [<c01fb792>] acpi_enable_subsystem+0x86/0xa6
 [<c03b7afd>] acpi_init+0x54/0x1f2
 [<c0226b45>] class_create+0x40/0x56
 [<c03b61ce>] fbmem_init+0x5b/0x86
 [<c0100414>] init+0x118/0x2bc
 [<c0103ca6>] ret_from_fork+0x6/0x20
 [<c01002fc>] init+0x0/0x2bc
 [<c01002fc>] init+0x0/0x2bc
 [<c0102005>] kernel_thread_helper+0x5/0xb
handlers:
[<c01e5557>] (acpi_irq+0x0/0x14)
Disabling IRQ #5
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Interrupt Link [LNKA] (IRQs *5 9 10)
ACPI: PCI Interrupt Link [LNKB] (IRQs 5 *9 10)
ACPI: PCI Interrupt Link [LNKC] (IRQs 5 *9 10)
ACPI: PCI Interrupt Link [LNKD] (IRQs *5 9 10)
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI quirk: region 0400-047f claimed by vt8235 PM
PCI quirk: region 0f00-0f0f claimed by vt8235 SMB
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 0 devices
PnPBIOS: Disabled by ACPI PNP
PCI: Using ACPI for IRQ routing
PCI: If a device doesn't work, try "pci=routeirq".  If it helps, post a
report
PCI: Bridge: 0000:00:01.0
  IO window: disabled.
  MEM window: dc000000-ddffffff
  PREFETCH window: d8000000-dbffffff
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 4096)
TCP reno registered
apm: BIOS not found.
audit: initializing netlink socket (disabled)
audit(1207573720.092:1): initialized
Total HugeTLB memory allocated, 0
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
isapnp: Scanning for PnP cards...
isapnp: No Plug & Play device found
Real Time Clock Driver v1.12ac
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
PNP: No PS/2 controller found. Probing ports directly.
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
mice: PS/2 mouse device common for all mice
input: PC Speaker as /class/input/input0
input: AT Translated Set 2 keyboard as /class/input/input1
input: ImExPS/2 Generic Explorer Mouse as /class/input/input2
md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
md: bitmap version 4.39
NET: Registered protocol family 1
Using IPI No-Shortcut mode
ACPI: (supports S0 S5)
md: Autodetecting RAID arrays.
Time: tsc clocksource has been installed.
md: autorun ...
md: ... autorun DONE.
RAMDISK: Couldn't find valid RAM disk image starting at 0.
VFS: Cannot open root device "801" or unknown-block(8,1)
Please append a correct "root=" boot option
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(8,1)




From joe at smittys.pointclark.net  Mon Apr  7 14:18:20 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Mon, 07 Apr 2008 08:18:20 -0400
Subject: [coreboot] i2c-i810 code
In-Reply-To: <1AC89277-BDA4-46DF-8BFD-ED95FB9DAC9F@edgedesign.us>
References: <20080406234222.sm5jx8crsw4gk004@www.smittys.pointclark.net>
	<1AC89277-BDA4-46DF-8BFD-ED95FB9DAC9F@edgedesign.us>
Message-ID: <20080407081820.boi58mwyswk044ok@www.smittys.pointclark.net>

What do you guys think about this? Is there any licensing issues I  
should be worried about??

>
> My $.02 is that it's fine as long as you are complying with the
> lm-sensors licensing.
>
>
> Phil
>
> On Apr 6, 2008, at 8:42 PM, joe at smittys.pointclark.net wrote:
>
>> Hello,
>> I am a coreboot developer working on some code for and intel   
>> northbridge chipset (Intel 830M). This board has an embedded tv-out  
>>  chip and I was wondering if it would be ok to use parts of the   
>> i2c-i810.c code from lm-sensors for this project. It would be of   
>> course be released under the terms of the GNU GPL. What do you think?
>>
>> Thanks - Joe




From uwe at hermann-uwe.de  Mon Apr  7 14:59:01 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 7 Apr 2008 14:59:01 +0200
Subject: [coreboot] i2c-i810 code
In-Reply-To: <20080407081820.boi58mwyswk044ok@www.smittys.pointclark.net>
References: <20080406234222.sm5jx8crsw4gk004@www.smittys.pointclark.net>
	<1AC89277-BDA4-46DF-8BFD-ED95FB9DAC9F@edgedesign.us>
	<20080407081820.boi58mwyswk044ok@www.smittys.pointclark.net>
Message-ID: <20080407125901.GA18481@greenwood>

On Mon, Apr 07, 2008 at 08:18:20AM -0400, joe at smittys.pointclark.net wrote:
> What do you guys think about this? Is there any licensing issues I  
> should be worried about??

Are we talking about this file?
http://lm-sensors.org/browser/lm-sensors/trunk/kernel/busses/i2c-i810.c

If yes, there is no problem. It's GPLv2-or-later and can be copied into
our repo (and adapted as needed), no problem. Just keep the complete
license header intact, of course.

The question is how much of that code you need, lots of it looks very
Linux-specific and would need quite some modifications. It might be
easier to write your own code from scratch for coreboot.

What exactly do you intend to do? Where's this code needed?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Mon Apr  7 15:09:40 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 7 Apr 2008 15:09:40 +0200
Subject: [coreboot] lifebook b-2175 working with coreboot?
In-Reply-To: <20080406163526.327100@gmx.net>
References: <20080406163526.327100@gmx.net>
Message-ID: <20080407130940.GB18481@greenwood>

Hi,

On Sun, Apr 06, 2008 at 06:35:26PM +0200, Countzero786 at gmx.de wrote:
> I'd like to know if there's a chance I can get coreboot to run on an old Fujitsu-Siemens Lifebook B-2175 I own.
> As it uses the Intel 440mx chipset, here are links to the (complete I think?) official documentation:
> http://www.intel.com/design/chipsets/designex/273504.htm
> http://www.intel.com/design/chipsets/specupdt/245051.htm
> http://www.intel.com/design/chipsets/datashts/440MX-66DSPub.htm
> http://www.intel.com/design/chipsets/embedded/docs/440mx.htm

Yep, documentation is available and it _could_ be done (chipset is very
similar to 440BX and 82371EB), but...

The main problem will be that in order to do this, you'll have to have a
socketed BIOS chip (i.e. one which is not soldered onto the mainboard,
but rather in a socket, so it can be removed/replaced without soldering).

Have you opened and checked if that's the case on this laptop? I had a
very similar device and there the flash ROM was soldered, and _very_ hard
to access physically.

(don't attempt to open your laptop unless you know what you're doing)


> ./flashrom
> --------------------
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel 440MX", enabling flash write... OK.
> MBM29F400TC found at physical address 0xfff80000.
> Flash part is MBM29F400TC (512 KB).
> No operations were specified.

Looks, ok, same chip as on my laptop. Detecting and reading the chip
worked for me, but I didn't attempt writing (as I have no means of
recovery in case it fails).

You shouldn't try it either, you won't be able to reflash another BIOS
easily (boot floppy disks won't help at all, btw).


> ./superiotool -d
> --------------------
> superiotool r3194
> Found SMSC FDC37N769 (id=0x28, rev=0x01) at 0x3f0
> Register dump:
> idx 00 01 02 03 04 05 06 07  08 09 0a 0b 0c 0d 0e 0f  10 11 12 13 14 15 16 17  18 19 1a 1b 1c 1d 1e 1f  20 21 22 23 24 25 26 27  28 29 2a 2b 2c 2d 2e 2f
> val 20 90 00 f4 00 00 ff 00  00 00 40 00 0e 28 01 00  00 00 00 00 02 00 00 03  00 00 00 00 00 00 80 00  00 00 00 00 00 00 00 00  00 00 00 00 00 03 00 00
> def 28 9c 88 70 00 00 ff 00  00 00 00 00 02 28 NA 00  00 80 RR RR NA NA NA 03  RR RR RR RR RR RR 80 00  3c RR RR 00 00 00 00 00  00 00 RR 00 00 03 00 00

Not a problem, the Super I/O support is doable.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From malateshkamat at gmail.com  Mon Apr  7 15:47:54 2008
From: malateshkamat at gmail.com (malatesh kamatad)
Date: Mon, 7 Apr 2008 19:17:54 +0530
Subject: [coreboot] Flashing problem with SST49LF004B
In-Reply-To: <fa70bcc0804042355w2f1b42c7q42f755b58eb48d9c@mail.gmail.com>
References: <fa70bcc0804020447q1e2d365dva0b059de3558722@mail.gmail.com>
	<fa70bcc0804032231g7f6b2ff2t1beac2e92dbb6095@mail.gmail.com>
	<47F5C4B8.5000700@onelabs.com>
	<fa70bcc0804040141n36698101w58521b24f6f7c949@mail.gmail.com>
	<fa70bcc0804040403k258a0d9eic9a105c48b05cf95@mail.gmail.com>
	<dd3c80060804040421m53b1db96uffedcb725d06b1a2@mail.gmail.com>
	<fa70bcc0804040541q33a7a50y5bd6dd65d15b6cc@mail.gmail.com>
	<dd3c80060804040559h4b7510b1q7747f44e897fa4da@mail.gmail.com>
	<fa70bcc0804040625wb01013vd941cd25fb274bba@mail.gmail.com>
	<fa70bcc0804042355w2f1b42c7q42f755b58eb48d9c@mail.gmail.com>
Message-ID: <fa70bcc0804070647u4e894948k7d2f5684965c8907@mail.gmail.com>

Hi...
      But in the data sheet they have mentioned like the SST49LF00xB detects
whether it is being

accessed   via a FWH or LPC protocol by detecting the START field contents;
a 1101b or 1110b

indi-cates a Firmware Memory cycle and a 0000b indicates an LPC memory
cycle.

but when i checked the content in the empty SST chip it shows like this

[root at localhost <http://www.coreboot.org/mailman/listinfo/coreboot>
~]# hexdump sst_after_erase.bin
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0080000

from this i came to know that SST chip is working in LPC mode  as

compared  to  data sheet ...is  it  right?  i  am  totally  confusing....

please inform me how to find  whether chip is in FWH or LPC mode.

thanks in advance
Malatesh





On 05/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
>
> Hello,
>   But the content after writing by using  below command shows result like
> this....
>
> [root at localhost ~]# /usr/local/sbin/flashrom -r | hexdump
>
> 0000000 6143 696c 7262 7461 6e69 2067 6564 616c
> 0000010 2079 6f6c 706f 2e2e 202e 4b4f 0a2e 6f4e
> 0000020 6320 726f 6265 6f6f 2074 6174 6c62 2065
> 0000030 6f66 6e75 2e64 460a 756f 646e 6320 6968
> 0000040 7370 7465 2220 4956 2041 5456 3238 3733
> 0000050 2c22 6520 616e 6c62 6e69 2067 6c66 7361
> 0000060 2068 7277 7469 2e65 2e2e 4f20 2e4b 530a
> 0000070 5453 3934 464c 3030 4134 422f 6620 756f
> 0000080 646e 6120 2074 6870 7379 6369 6c61 6120
> 0000090 6464 6572 7373 3020 6678 6666 3038 3030
> 00000a0 2e30 460a 616c 6873 7020 7261 2074 7369
> 00000b0 5320 5453 3934 464c 3030 4134 422f 2820
> 00000c0 3135 2032 424b 2e29 450a 7272 726f 203a
> 00000d0 6f4e 6620 6c69 6e65 6d61 2065 7073 6365
> 00000e0 6669 6569 2e64 000a
> 00000e7
>
> ************************************
>   But using only hexdump i got result like this ...
>
> [root at localhost ~]# hexdump sst_after_write05.bin
> 0000000 ffff ffff ffff ffff ffff ffff ffff ffff
> *
> 0080000
>
> Thanks.
> Malatesh
>
> On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
> >
> > Ya .. after checking that file i got result like this ...it shows that
> > there is a content in that file
> >
> > [root at localhost ~]# hexdump sst_after_erase.bin
> > 0000000 ffff ffff ffff ffff ffff ffff ffff ffff
> > *
> > 0080000
> >
> >   I think erasing is not happened properly..
> >
> > Thanks..
> > malatesh
> >
> > On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
> > >
> > > Ok, so if you open up the sst_after_erase.bin with a hex editor, is
> > > there anything in it? Does that match the data from the diff, or is it a
> > > binary ORing of the data from the diff? Do you have any other flash chips
> > > you can try on the board?
> > >
> > > On Fri, Apr 4, 2008 at 8:41 AM, malatesh kamatad <
> > > malateshkamat at gmail.com> wrote:
> > >
> > > >  Ya i got result like this after comparing
> > > >
> > > >   [root at localhost ~]# diff -us original.bin sst_after_write.bin
> > > > Binary files original.bin and sst_after_write.bin differ
> > > >
> > > >    but its showing that there is a difference in between to files
> > > > ....
> > > >
> > > >   i think write is not happening proper ....
> > > >
> > > > Thanks .
> > > > malatesh
> > > >
> > > >
> > > > On 04/04/2008, Corey Osgood <corey.osgood at gmail.com> wrote:
> > > > >
> > > > > what's the output of diff -us original.bin sst_after_write.bin?
> > > > > Can you download the bios from the manufacturer and see if flashing that
> > > > > works?
> > > > >
> > > > > -Corey
> > > > >
> > > > > On Fri, Apr 4, 2008 at 7:03 AM, malatesh kamatad <
> > > > > malateshkamat at gmail.com> wrote:
> > > > >
> > > > > >    I worked with the step by step this is the output......
> > > > > >
> > > > > > [root at localhost ~]# flashrom -r original.bin
> > > > > > Calibrating delay loop... OK.
> > > > > > No coreboot table found.
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > Pm49FL004 found at physical address 0xfff80000.
> > > > > > Flash part is Pm49FL004 (512 KB).
> > > > > > Reading Flash...done
> > > > > >
> > > > > > [root at localhost ~]# flashrom -E
> > > > > > Calibrating delay loop... OK.
> > > > > > No coreboot table found.
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > Erasing flash chip
> > > > > >
> > > > > > [root at localhost ~]# flashrom -r sst_after_erase.bin
> > > > > > Calibrating delay loop... OK.
> > > > > > No coreboot table found.
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > Reading Flash...done
> > > > > >
> > > > > > [root at localhost ~]# flashrom -w original.bin
> > > > > > Calibrating delay loop... OK.
> > > > > > No coreboot table found.
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > > > Programming page: 0007 at address: 0x00070000
> > > > > >
> > > > > > [root at localhost ~]# flashrom -r sst_after_write.bin
> > > > > > Calibrating delay loop... OK.
> > > > > > No coreboot table found.
> > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > Reading Flash...done
> > > > > >
> > > > > > Thanks,
> > > > > > Malatesh.
> > > > > >
> > > > > > On 04/04/2008, malatesh kamatad <malateshkamat at gmail.com> wrote:
> > > > > > >
> > > > > > > Hi..
> > > > > > >
> > > > > > >          We are having two BIOS i.e, PM49FL004( motherboard's
> > > > > > > BIOS) and empty flashrom
> > > > > > >
> > > > > > >         SST49LF004B ..
> > > > > > >
> > > > > > >        We are trying to flash the content of PM49FL004 to
> > > > > > > SST49LF004B flashrom
> > > > > > >
> > > > > > >         according to your suggestion we have done ..we are
> > > > > > > getting output  as bellow..
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > [root at localhost ~]# flashrom -E
> > > > > > >
> > > > > > > Calibrating delay loop... OK.
> > > > > > >
> > > > > > > No coreboot table found.
> > > > > > >
> > > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > >
> > > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > >
> > > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > >
> > > > > > > Erasing flash chip
> > > > > > >
> > > > > > > Erasing page: 0007 at address: 0x00070000
> > > > > > >
> > > > > > > [root at localhost ~]# flashrom -r malateh.bin
> > > > > > >
> > > > > > > Calibrating delay loop... OK.
> > > > > > >
> > > > > > > No coreboot table found.
> > > > > > >
> > > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > >
> > > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > >
> > > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > >
> > > > > > > Reading Flash...done
> > > > > > >
> > > > > > > [root at localhost ~]# flashrom -w malateh.bin
> > > > > > >
> > > > > > > Calibrating delay loop... OK.
> > > > > > >
> > > > > > > No coreboot table found.
> > > > > > >
> > > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > >
> > > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > >
> > > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > >
> > > > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > > > >
> > > > > > > Programming page: 0007 at address: 0x00070000
> > > > > > >
> > > > > > > [root at localhost ~]# flashrom -v malateh.bin
> > > > > > >
> > > > > > > Calibrating delay loop... OK.
> > > > > > >
> > > > > > > No coreboot table found.
> > > > > > >
> > > > > > > Found chipset "VIA VT8237", enabling flash write... OK.
> > > > > > >
> > > > > > > SST49LF004A/B found at physical address 0xfff80000.
> > > > > > >
> > > > > > > Flash part is SST49LF004A/B (512 KB).
> > > > > > >
> > > > > > > Flash image seems to be a legacy BIOS. Disabling checks.
> > > > > > >
> > > > > > > Verifying flash... VERIFIED.
> > > > > > >
> > > > > > >
> > > > > > >  After that we tried to boot the system by SST49lf004B but
> > > > > > > system is not rebooting....
> > > > > > >
> > > > > > > So we want to flash the content of the Pm49fl004 to SST49lf004
> > > > > > > so that our system can boot
> > > > > > >
> > > > > > > using SST49lf004....
> > > > > > >
> > > > > > > thanks,
> > > > > > > Malatesh..
> > > > > > >
> > > > > > >
> > > > > > > On 04/04/2008, bari <bari at onelabs.com> wrote:
> > > > > > > >
> > > > > > > > Try Peters suggestion of reading the flash after an erase
> > > > > > > > and see what is there.
> > > > > > > >
> > > > > > > > If it is erased, read back after you have tried to write and
> > > > > > > > compare.
> > > > > > > >
> > > > > > > > See what is or is not happening.
> > > > > > > >
> > > > > > > > -Bari
> > > > > > > >
> > > > > > > > malatesh kamatad wrote:
> > > > > > > >
> > > > > > > > > Hi...
> > > > > > > > >       I am working on ASRock motherboard .....in FWH
> > > > > > > > > mode...
> > > > > > > > >
> > > > > > > > > with regards.
> > > > > > > > > Malatesh
> > > > > > > > >
> > > > > > > > > On 03/04/2008, *bari* <bari at onelabs.com <mailto:
> > > > > > > > > bari at onelabs.com>> wrote:
> > > > > > > > >
> > > > > > > > >    malatesh kamatad wrote:
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >        Hi all..
> > > > > > > > >              I have worked with PM49fl00x.diff patch ,its
> > > > > > > > > worked fine
> > > > > > > > >        and i got the output as below
> > > > > > > > >
> > > > > > > > >    The PM49fl00x can work in LPC and FWH modes. Do you
> > > > > > > > > know which
> > > > > > > > >    mode is being used?
> > > > > > > > >    What mainboard did you test this in?
> > > > > > > > >
> > > > > > > > >                           Now i am working on SST49LF004B
> > > > > > > > >                                          33-4C-NHE
> > > > > > > > >                                          0710022-CA   with
> > > > > > > > > the
> > > > > > > > >         motherboard  K8Upgrade-VM800
> > > > > > > > >                         The flashrom detect flash device
> > > > > > > > > on this
> > > > > > > > >        board, But the erasing and writting operation is
> > > > > > > > > not happening
> > > > > > > > >        properly
> > > > > > > > >          hier flashrom output :
> > > > > > > > >    Is this the board by ASRock?
> > > > > > > > >
> > > > > > > > >    -Bari
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > >
> > > > > > >
> > > > > >
> > > > > > --
> > > > > > coreboot mailing list
> > > > > > coreboot at coreboot.org
> > > > > > http://www.coreboot.org/mailman/listinfo/coreboot
> > > > > >
> > > > >
> > > > >
> > > >
> > >
> >
>
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From savchenko at altell.ru  Mon Apr  7 15:51:01 2008
From: savchenko at altell.ru (Mikhail Savchenko)
Date: Mon, 7 Apr 2008 17:51:01 +0400
Subject: [coreboot] lzma compression
Message-ID: <002801c898b6$6abcd850$403688f0$@ru>

AS I Know 7zip algorithm using for this compression is paid for commercial
use. Are there any special license issues about it's using during coreboot?

 

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From joe at smittys.pointclark.net  Mon Apr  7 16:11:47 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Mon, 07 Apr 2008 10:11:47 -0400
Subject: [coreboot] i2c-i810 code
In-Reply-To: <20080407125901.GA18481@greenwood>
References: <20080406234222.sm5jx8crsw4gk004@www.smittys.pointclark.net>
	<1AC89277-BDA4-46DF-8BFD-ED95FB9DAC9F@edgedesign.us>
	<20080407081820.boi58mwyswk044ok@www.smittys.pointclark.net>
	<20080407125901.GA18481@greenwood>
Message-ID: <20080407101147.ccj92eyspw4gcww8@www.smittys.pointclark.net>

Quoting Uwe Hermann <uwe at hermann-uwe.de>:

> On Mon, Apr 07, 2008 at 08:18:20AM -0400, joe at smittys.pointclark.net wrote:
>> What do you guys think about this? Is there any licensing issues I
>> should be worried about??
>
> Are we talking about this file?
> http://lm-sensors.org/browser/lm-sensors/trunk/kernel/busses/i2c-i810.c
>
Yes
>
> If yes, there is no problem. It's GPLv2-or-later and can be copied into
> our repo (and adapted as needed), no problem. Just keep the complete
> license header intact, of course.
>
> The question is how much of that code you need, lots of it looks very
> Linux-specific and would need quite some modifications.
Yes
> It might be
> easier to write your own code from scratch for coreboot.
>
Probibly, but I could use certian functions from this code.
>
> What exactly do you intend to do? Where's this code needed?
>
This code will enable communications with the Conexant CX25873 tv-out  
chip via i2c through the northbridge GPIO lines. Then I can program  
the tv-out registers and initialize it. I'm still not exactly sure  
where this code will run. If can run before VGA is initialized that  
would be great. But it may have to run after, to get the correct clock  
and timing signals from the northbridge graphics, which means a  
modification to the coreboot core code.

Thanks - Joe



From jordan.crouse at amd.com  Mon Apr  7 17:09:23 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 7 Apr 2008 09:09:23 -0600
Subject: [coreboot] i2c-i810 code
In-Reply-To: <20080407081820.boi58mwyswk044ok@www.smittys.pointclark.net>
References: <20080406234222.sm5jx8crsw4gk004@www.smittys.pointclark.net>
	<1AC89277-BDA4-46DF-8BFD-ED95FB9DAC9F@edgedesign.us>
	<20080407081820.boi58mwyswk044ok@www.smittys.pointclark.net>
Message-ID: <20080407150923.GD27196@cosmic.amd.com>

On 07/04/08 08:18 -0400, joe at smittys.pointclark.net wrote:
> What do you guys think about this? Is there any licensing issues I  
> should be worried about??

I don't think so - as long as the original code can be licensed under
the GPLv2, then you can use it in coreboot as long as you retain the
original copyright information.

Jordan

> >> Hello,
> >> I am a coreboot developer working on some code for and intel   
> >> northbridge chipset (Intel 830M). This board has an embedded tv-out  
> >>  chip and I was wondering if it would be ok to use parts of the   
> >> i2c-i810.c code from lm-sensors for this project. It would be of   
> >> course be released under the terms of the GNU GPL. What do you think?
> >>
> >> Thanks - Joe
> 
> 
> -- 
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From eswierk at arastra.com  Mon Apr  7 17:35:29 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Mon, 7 Apr 2008 08:35:29 -0700
Subject: [coreboot] [PATCH] Make flashrom work with ST M50FW016/040 chips
Message-ID: <e6c711510804070835p227f3c60kdb5c24d28a4df4dd@mail.gmail.com>

Currently flashrom defines the ST M50FW016 and M50FW040 to use jedec
commands, but these chips don't support them, as far as I can tell.
They do support the 82802ab command set, however.

I tested this patch with an M50FW016. I don't have an M50FW040 but the
datasheet indicates the same command set as the M50FW016.

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed
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From joe at smittys.pointclark.net  Mon Apr  7 17:53:36 2008
From: joe at smittys.pointclark.net (joe at smittys.pointclark.net)
Date: Mon, 07 Apr 2008 11:53:36 -0400
Subject: [coreboot] [PATCH] Make flashrom work with ST M50FW016/040	chips
In-Reply-To: <e6c711510804070835p227f3c60kdb5c24d28a4df4dd@mail.gmail.com>
References: <e6c711510804070835p227f3c60kdb5c24d28a4df4dd@mail.gmail.com>
Message-ID: <20080407115336.ve5s7ehnwkgkwg44@www.smittys.pointclark.net>

Quoting Ed Swierk <eswierk at arastra.com>:

> Currently flashrom defines the ST M50FW016 and M50FW040 to use jedec
> commands, but these chips don't support them, as far as I can tell.
> They do support the 82802ab command set, however.
>
> I tested this patch with an M50FW016. I don't have an M50FW040 but the
> datasheet indicates the same command set as the M50FW016.
>
> Signed-off-by: Ed Swierk <eswierk at arastra.com>
>
> --Ed
>
Yup I had to make this change to the M50FW080 to get it to work.

Acked-by: Joseph Smith <joe at smittys.pointclark.net>


Thanks - Joe



From Marc.Jones at amd.com  Mon Apr  7 18:57:20 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Mon, 07 Apr 2008 10:57:20 -0600
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <1207330539.4785.20.camel@martr-gentoo.artec>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
	<1207330539.4785.20.camel@martr-gentoo.artec>
Message-ID: <47FA5270.7060906@amd.com>


Mart Raudsepp wrote:

...
>
> To get that I had to enable 4MB mode on the dongle with a
> outb(0xf4,0x88);
> in some init code. Picked randomly northbridge/amd/geodelx/geodelxinit.c
> northbridge_init_early() as a hack
>
>   
Please add these kind of customizations to the mainboard code. stage1.c 
would probably work.
> Then I had to manually add the VSA, as its requirement seems hardcoded
> and its addition isn't part of the build in a manner payload.elf is.
>
>   

We need to get this is platform into buildrom to automate the VSA addition.

>
> NAND and network doesn't seem to work at first glance, but nice progress!
>
> CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.
>   
You can either have the IDE or FLASH header since they share pins.
enable_ide_nand_flash needs to be set in the mainboard dts.

Marc

-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From mart.raudsepp at artecdesign.ee  Mon Apr  7 19:05:26 2008
From: mart.raudsepp at artecdesign.ee (Mart Raudsepp)
Date: Mon, 07 Apr 2008 20:05:26 +0300
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <47FA5270.7060906@amd.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
	<1207330539.4785.20.camel@martr-gentoo.artec>
	<47FA5270.7060906@amd.com>
Message-ID: <1207587926.4799.2.camel@martr-gentoo.artec>

?hel kenal p?eval, E, 2008-04-07 kell 10:57, kirjutas Marc Jones:
> > Then I had to manually add the VSA, as its requirement seems hardcoded
> > and its addition isn't part of the build in a manner payload.elf is.
> >
> >   
> 
> We need to get this is platform into buildrom to automate the VSA addition.

I see that as something suitable to be exposed in Kconfig as well, in
addition(?).
"Include VSA blob", "Include OpenVSA", "No VSA (relying on lxfb)"

> >
> > NAND and network doesn't seem to work at first glance, but nice progress!
> >
> > CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.
> >   
> You can either have the IDE or FLASH header since they share pins.
> enable_ide_nand_flash needs to be set in the mainboard dts.

Indeed.


Regards,
Mart Raudsepp
Artec Design LLC




From Marc.Jones at amd.com  Mon Apr  7 19:18:02 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Mon, 07 Apr 2008 11:18:02 -0600
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <1207587926.4799.2.camel@martr-gentoo.artec>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>	
	<1207330539.4785.20.camel@martr-gentoo.artec>
	<47FA5270.7060906@amd.com>
	<1207587926.4799.2.camel@martr-gentoo.artec>
Message-ID: <47FA574A.3030906@amd.com>

Mart Raudsepp wrote:
> ?hel kenal p?eval, E, 2008-04-07 kell 10:57, kirjutas Marc Jones:
>   
>>> Then I had to manually add the VSA, as its requirement seems hardcoded
>>> and its addition isn't part of the build in a manner payload.elf is.
>>>
>>>   
>>>       
>> We need to get this is platform into buildrom to automate the VSA addition.
>>     
>
> I see that as something suitable to be exposed in Kconfig as well, in
> addition(?).
> "Include VSA blob", "Include OpenVSA", "No VSA (relying on lxfb)"
>   
Ah, looks like the make/build gurus have some idea how this should work. 
I will let them comment.
Marc


--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From Countzero786 at gmx.de  Mon Apr  7 19:22:32 2008
From: Countzero786 at gmx.de (Countzero786 at gmx.de)
Date: Mon, 07 Apr 2008 19:22:32 +0200
Subject: [coreboot] lifebook b-2175 working with coreboot?
In-Reply-To: <20080407130940.GB18481@greenwood>
References: <20080406163526.327100@gmx.net> <20080407130940.GB18481@greenwood>
Message-ID: <20080407172232.249890@gmx.net>

On Mon, 7 Apr 2008 15:09:40 +0200, uwe at hermann-uwe.de wrote:
>Have you opened and checked if that's the case on this laptop? I had a
>very similar device and there the flash ROM was soldered, and _very_ hard
>to access physically.

Hey,

Yeah I had a look at front and back of the mainboard and although I wasn't able to identify the bios, I did find all chips to be soldered.

Well, I guess that means there's no way for me to try coreboot with that notebook then. :S

Anyway.

Regards, Said.

PS: I don't know if it's of any use, but I found this list while searching for information on the topic (http://www.elhof.de/Files/Devicelisten/Minato/DL_M1890.pdf)
-- 
GMX startet ShortView.de. Hier findest Du Leute mit Deinen Interessen!
Jetzt dabei sein: http://www.shortview.de/?mc=sv_ext_mf at gmx



From jordan.crouse at amd.com  Mon Apr  7 19:34:59 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 7 Apr 2008 11:34:59 -0600
Subject: [coreboot] patch: dbe62 boots to FILO!
In-Reply-To: <47FA574A.3030906@amd.com>
References: <13426df10804022304y94b5649jf57c0aede5a81505@mail.gmail.com>
	<1207330539.4785.20.camel@martr-gentoo.artec>
	<47FA5270.7060906@amd.com>
	<1207587926.4799.2.camel@martr-gentoo.artec>
	<47FA574A.3030906@amd.com>
Message-ID: <20080407173459.GE27196@cosmic.amd.com>

On 07/04/08 11:18 -0600, Marc Jones wrote:
> Mart Raudsepp wrote:
> > ?hel kenal p?eval, E, 2008-04-07 kell 10:57, kirjutas Marc Jones:
> >   
> >>> Then I had to manually add the VSA, as its requirement seems hardcoded
> >>> and its addition isn't part of the build in a manner payload.elf is.
> >>>
> >>>   
> >>>       
> >> We need to get this is platform into buildrom to automate the VSA addition.
> >>     
> >
> > I see that as something suitable to be exposed in Kconfig as well, in
> > addition(?).
> > "Include VSA blob", "Include OpenVSA", "No VSA (relying on lxfb)"
> >   
> Ah, looks like the make/build gurus have some idea how this should work. 
> I will let them comment.
> Marc

We have this - working fine for v2, and  Ward was working on it for v3 this
weekend.  I want to say that he checked it in for alix, but I'm not positive.

We are not supporting the "No VSA" path  for Geode - its either open vsa or
legacy.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From svn at coreboot.org  Mon Apr  7 19:49:58 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  7 Apr 2008 19:49:58 +0200
Subject: [coreboot] r3219 - in trunk/coreboot-v2/src: arch/i386/boot
	cpu/amd/model_10xxx
Message-ID: <mailman.1379.1355071297.16123.coreboot@coreboot.org>

Author: mjones
Date: 2008-04-07 19:49:57 +0200 (Mon, 07 Apr 2008)
New Revision: 3219

Removed:
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c
Modified:
   trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c
Log:
Don't check exclusive IRQ fieldin the PIR table.
This field is rarely used (and not used in the LX tables).
There is not a good reason to mask off non-exclusive IRQs. 

Signed-off-by: Marc Jones(marc.jones at amd.com)
Acked-by: Stefan Reinauer <stepan at coresystems.de> 



Modified: trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c	2008-04-06 04:26:19 UTC (rev 3218)
+++ trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c	2008-04-07 17:49:57 UTC (rev 3219)
@@ -121,7 +121,7 @@
 		for (j = 0; j < 4; j++) {
 
 			int link = pirq_tbl->slots[i].irq[j].link;
-			int bitmap = pirq_tbl->slots[i].irq[j].bitmap & pirq_tbl->exclusive_irqs;
+			int bitmap = pirq_tbl->slots[i].irq[j].bitmap;
 			int irq = 0;
 
 			printk_debug("INT: %c link: %x bitmap: %x  ",

Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c	2008-04-06 04:26:19 UTC (rev 3218)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid_common.c	2008-04-07 17:49:57 UTC (rev 3219)
@@ -1,312 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-#include <cpu/x86/tsc.h>
-
-
-static u32 get_vstime(u32 nodeid, u32 slam)
-{
-	u32 val;
-	u32 v;
-	device_t dev;
-
-#if defined(__ROMCC__)
-	dev = NODE_PCI(nodeid, 3);
-#else
-	dev = get_node_pci(nodeid, 3);
-#endif
-
-	val = pci_read_config32(dev, 0xd8);
-
-	val >>= slam?0:4;
-	val &= 7;
-
-	switch (val) {
-	case 4: v = 60; break;
-	case 5: v = 100; break;
-	case 6: v = 200; break;
-	case 7: v = 500; break;
-	default:
-		v = (val+1)*10; // in us
-	}
-
-	return v;
-}
-
-static void udelay_tsc(u32 us)
-{
-	/* Use TSC to delay because it is fixed, ie. it will not changed with p-states.
-	 * Also, We use the APIC TIMER register is to hold flags for AP init.
-	 */
-	u32 dword;
-	tsc_t tsc, tsc1, tscd;
-	u32 d =  0x00000200; //800Mhz or 200Mhz or 1.6G or get the NBFID at first
-	u32 dn = 0x1000000/2; // howmany us need to use hi
-
-	tscd.hi = us/dn;
-	tscd.lo = (us - tscd.hi * dn) * d;
-
-	tsc1 = rdtsc();
-	dword = tsc1.lo + tscd.lo;
-	if((dword<tsc1.lo) || (dword<tscd.lo)) {
-		tsc1.hi++;
-	}
-	tsc1.lo = dword;
-	tsc1.hi+= tscd.hi;
-
-	do {
-		tsc = rdtsc();
-	} while ((tsc.hi>tsc1.hi) || ((tsc.hi==tsc1.hi) && (tsc.lo>tsc1.lo)));
-
-}
-
-#ifdef __ROMCC__
-void udelay(u32 usecs)
-{
-	udelay_tsc(usecs);
-}
-#endif
-
-static u32 set_vid(u32 newvid, u32 bit_offset, u32 nodeid, u32 coreid)
-{
-	u32 val;
-	msr_t msr;
-	u32 curvid;
-	u32 slam;
-	u32 delay;
-	u32 count = 3;
-	device_t dev;
-
-	msr = rdmsr(0xc0010071);//status
-	curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits
-
-	if(newvid == curvid) return curvid;
-
-#if defined(__ROMCC__)
-	dev = NODE_PCI(nodeid, 3);
-#else
-	dev = get_node_pci(nodeid, 3);
-#endif
-
-	val = pci_read_config32(dev, 0xa0);
-
-	slam = (val >> 29) & 1;
-	delay = get_vstime(nodeid, slam);
-
-	if(!slam) {
-		if(curvid>newvid) {
-			count = (curvid - newvid) * 2;
-		} else {
-			count = (newvid - curvid) * 2;
-		}
-	}
-
-	while(count-->0) {
-		if(slam) {
-			curvid = newvid;
-		}
-		else { //ramp
-			if(curvid>newvid) {
-				curvid--;
-			} else {
-				curvid++;
-			}
-		}
-
-		msr = rdmsr(0xc0010070); //control
-		msr.lo &= ~(0x7f<<bit_offset);
-		msr.lo |= (curvid<<bit_offset);
-		wrmsr(0xc0010070, msr); // how about all copys, APIC or PCI conf space?
-
-		udelay_tsc(delay);
-
-		msr = rdmsr(0xc0010071);//status
-		curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits
-
-		if(curvid == newvid) break;
-
-	}
-
-	return curvid;
-}
-
-
-static u32 set_nb_vid(u32 newvid, u32 nodeid, u32 coreid)
-{
-	return set_vid(newvid, 25, nodeid, coreid);
-}
-
-
-static u32 set_core_vid(u32 newvid, u32 nodeid, u32 coreid)
-{
-	return set_vid(newvid, 9, nodeid, coreid);
-}
-
-
-static unsigned set_cof(u32 val, u32 mask, u32 nodeid, u32 coreid)
-{
-	msr_t msr;
-	int count = 3;
-
-	val &= mask;
-
-	// FIXME: What is count for? Why 3 times? What about node and core id?
-	while(count-- > 0) {
-
-		msr = rdmsr(0xc0010071);
-		msr.lo &= mask;
-		if(msr.lo == val) break;
-
-		msr = rdmsr(0xc0010070);
-		msr.lo &= ~(mask);
-		msr.lo |= val;
-		wrmsr(0xc0010070, msr);
-	}
-
-	return msr.lo;
-}
-
-static u32 set_core_cof(u32 fid, u32 did, u32 nodeid, u32 coreid)
-{
-	u32 val;
-	u32 mask;
-
-	mask = (7<<6) | 0x3f;
-	val = ((did & 7)<<6) | (fid & 0x3f);
-
-	return set_cof(val, mask, nodeid, coreid);
-
-}
-
-
-static u32 set_nb_cof(u32 did, u32 nodeid, u32 coreid) // fid need warmreset
-{
-	u32 val;
-	u32 mask;
-
-	mask = 1<<22;
-	val = (did & 1)<<22;
-
-	return set_cof(val, mask, nodeid, coreid);
-
-}
-
-
-/* set vid and cof for core and nb after warm reset is not started by BIOS */
-static void set_core_nb_max_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // P0
-{
-	msr_t msr;
-	u32 val;
-	u32 vid;
-	u32 mask;
-	u32 did;
-	device_t dev;
-
-	msr = rdmsr(0xc0010064);
-
-#if defined(__ROMCC__)
-	dev = NODE_PCI(nodeid, 3);
-#else
-	dev = get_node_pci(nodeid, 3);
-#endif
-
-	val = pci_read_config32(dev, 0xa0);
-	if((val>>8) & 1) { // PVI
-		vid = (msr.lo >> 25) & 0x7f;
-	} else { //SVI
-		vid = (msr.lo >> 9) & 0x7f;
-	}
-	set_core_vid(vid, nodeid, coreid);
-
-	mask = (0x7<<6) | 0x3f;
-	val = msr.lo & mask;
-	set_cof(val, mask, nodeid, coreid);
-
-	//set nb cof and vid
-	did = (msr.lo >> 22) & 1;
-	vid = (msr.lo >> 25) & 0x7f;
-	if(did) {
-		 set_nb_cof(did, nodeid, coreid);
-		set_nb_vid(vid, nodeid, coreid);
-	} else {
-		set_nb_vid(vid, nodeid, coreid);
-		 set_nb_cof(did, nodeid, coreid);
-	}
-
-	//set the p state
-	msr.hi = 0;
-	msr.lo = 0;
-	wrmsr(0xc0010062, msr);
-
-}
-
-
-/* set vid and cof for core and nb after warm reset is not started by BIOS */
-static void  set_core_nb_min_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // Px
-{
-	msr_t msr;
-	u32 val;
-	u32 vid;
-	u32 mask;
-	u32 did;
-	u32 pstate;
-	device_t dev;
-
-#if defined(__ROMCC__)
-	dev = NODE_PCI(nodeid, 3);
-#else
-	dev = get_node_pci(nodeid, 3);
-#endif
-
-
-	val = pci_read_config32(dev, 0xdc); //PstateMaxVal
-
-	pstate = (val >> 8) & 0x7;
-
-	msr = rdmsr(0xc0010064 + pstate);
-
-	mask = (7<<6) | 0x3f;
-	val = msr.lo & mask;
-	set_cof(val, mask, nodeid, coreid);
-
-	val = pci_read_config32(dev, 0xa0);
-	if((val>>8) & 1) { // PVI
-		 vid = (msr.lo>>25) & 0x7f;
-	} else { //SVI
-		 vid = (msr.lo>>9) & 0x7f;
-	}
-	set_core_vid(vid, nodeid, coreid);
-
-	//set nb cof and vid
-	did = (msr.lo >> 22) & 1;
-	vid = (msr.lo >> 25) & 0x7f;
-	if(did) {
-		set_nb_cof(did, nodeid, coreid);
-		set_nb_vid(vid, nodeid, coreid);
-	} else {
-		set_nb_vid(vid, nodeid, coreid);
-		set_nb_cof(did, nodeid, coreid);
-	}
-
-	//set the p state
-	msr.hi = 0;
-	msr.lo = pstate;
-	wrmsr(0xc0010062, msr);
-}

Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h	2008-04-06 04:26:19 UTC (rev 3218)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000018.h	2008-04-07 17:49:57 UTC (rev 3219)
@@ -1,163 +0,0 @@
-/*
- ============================================================
- (c) Advanced Micro Devices, Inc., 2004-2005
-
- The  enclosed microcode  is intended  to be  used  with AMD
- Microprocessors.  You  may   copy,  view  and  install  the
- enclosed microcode  only for development  and deployment of
- firmware,  BIOS,  or  operating  system code  for  computer
- systems   that  contain  AMD   processors.   You   are  not
- authorized  to use  the  enclosed microcode  for any  other
- purpose.
-
- THE  MICROCODE IS PROVIDED  "AS IS"  WITHOUT ANY  EXPRESS OR
- IMPLIED WARRANTY  OF ANY KIND, INCLUDING BUT  NOT LIMITED TO
- WARRANTIES    OF    MERCHANTABILITY,   NON-    INFRINGEMENT,
- TITLE,FITNESS  FOR  ANY  PARTICULAR PURPOSE,  OR  WARRANTIES
- ARISING FROM CONDUCT, COURSE  OF DEALING, OR USAGE OF TRADE.
- AMD does not assume  any responsibility for any errors which
- may  appear   in  this   microcode  or  any   other  related
- information provided  to you by  AMD, or result from  use of
- this microcode.   AMD is not obligated  to furnish, support,
- or  make   any  further  information,   software,  technical
- information, know-how, or show-how available related to this
- microcode.
-
- The  microcode is provided  with "RESTRICTED  RIGHTS."  Use,
- duplication, or disclosure by the U.S. Government is subject
- to  the  restrictions as  set  forth  in  FAR 52.227-14  and
- DFAR252.227-7013,  et seq.,  or its  successor.  Use  of the
- microcode    by    the    U.S.     Government    constitutes
- acknowledgement  of   AMD's  proprietary  rights   in  them.
- ============================================================
-*/
-
-0x07, 0x20, 0x08, 0x02, 0x18, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
-0x66, 0x70, 0x30, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-0xff, 0xff, 0xff, 0xff, 0xa4, 0x06, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-0x72, 0x09, 0x00, 0x00, 0x70, 0x09, 0x00, 0x00, 0x9b, 0x0b, 0x00, 0x00,
-0xff, 0xff, 0xff, 0xff, 0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x37,
-0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
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-0xff, 0xfb, 0xfd, 0xff, 0x57, 0x7d, 0xf0, 0xcd, 0xff, 0x1f, 0xb7, 0xfe,
-0xc0, 0xcf, 0xc3, 0x3f, 0xff, 0x01, 0xff, 0xf7, 0x00, 0x02, 0x07, 0xff,
-0x35, 0x00, 0x90, 0x8b, 0xf0, 0x0f, 0xe0, 0x3f, 0x07, 0xf0, 0x6f, 0xf8,
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-0x7f, 0x00, 0xff, 0x86, 0xff, 0x1e, 0x00, 0xf8, 0x1f, 0xf8, 0x07, 0xf0,
-0xfc, 0x03, 0x78, 0x33, 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
-0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x7f, 0x0f, 0x00,
-0xf8, 0x0f, 0xfc, 0x03, 0x19, 0xfe, 0x01, 0xbc, 0xe0, 0x3f, 0xf0, 0x0f,
-0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f, 0xbf, 0xe1, 0x1f, 0xc0,
-0x00, 0xb4, 0xb2, 0x06, 0xbf, 0xdf, 0xff, 0xff, 0xd5, 0x07, 0xdf, 0x7c,
-0x67, 0xb2, 0xe7, 0xf9, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xf0, 0x7f, 0xff,
-0x20, 0x70, 0xf0, 0x0f, 0x03, 0x00, 0xed, 0x58, 0xff, 0x00, 0xfe, 0x03,
-0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe,
-0xf0, 0x0f, 0xe0, 0x3f, 0x07, 0xf0, 0x6f, 0xf8, 0xef, 0x01, 0x80, 0xff,
-0xff, 0xff, 0x29, 0x2a, 0x5f, 0xd0, 0xc1, 0xc3, 0xff, 0xff, 0xb3, 0xdd,
-0xff, 0x7e, 0xfd, 0x0f, 0x1f, 0xf8, 0x57, 0xf6, 0xbc, 0x63, 0x2d, 0x3c,
-0x03, 0xd4, 0x00, 0x40, 0xff, 0xd7, 0xbf, 0xb7, 0xe1, 0xdf, 0xeb, 0xe7,
-0xef, 0xff, 0xff, 0x57, 0x87, 0x7f, 0xbf, 0xea, 0xfa, 0x0f, 0xfc, 0x03,
-0x1f, 0xbe, 0xf5, 0xfc, 0x80, 0x02, 0x4b, 0x00, 0x8a, 0xca, 0xff, 0x7f,
-0xf0, 0xf0, 0x17, 0x74, 0x6c, 0xf7, 0xff, 0xff, 0xff, 0xc3, 0xbf, 0x5f,
-0x95, 0xfd, 0x07, 0xfe, 0x0b, 0x0f, 0xef, 0x58, 0x00, 0xd0, 0x00, 0x35,
-0xab, 0xea, 0xff, 0xfb, 0x05, 0x78, 0xf4, 0x67, 0xff, 0xd5, 0xfb, 0xff,
-0xaf, 0xfa, 0xe1, 0xdf, 0xff, 0x80, 0xfe, 0x03, 0x3d, 0xff, 0x87, 0x6f,
-0x12, 0x00, 0xa0, 0xc0, 0xff, 0x0f, 0xf0, 0xaf, 0x03, 0xf8, 0x3f, 0xfc,
-0xff, 0x2f, 0xc0, 0xff, 0x2d, 0x65, 0xff, 0xf0, 0x0d, 0xfe, 0x04, 0xb6,
-0x2f, 0x03, 0xad, 0xc3, 0x51, 0x0d, 0x00, 0x8c, 0xff, 0xfe, 0x03, 0xf8,
-0xff, 0xb9, 0xc9, 0x19, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
-0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xf2, 0xb9, 0x06, 0x00,
-0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe, 0xf0, 0x1f, 0xf8, 0x07,
-0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
-0x00, 0xff, 0xdf, 0x03, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
-0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
-0xf0, 0x6f, 0xf8, 0x07, 0x01, 0x80, 0xff, 0xef, 0x7f, 0x00, 0xff, 0x81,
-0x80, 0x7f, 0xc3, 0x3f, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
-0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xd7, 0x00, 0x40, 0x34,
-0xc0, 0x3f, 0x80, 0xff, 0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe,
-0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
-0x9a, 0x6b, 0x00, 0x00, 0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
-0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x07, 0xfe, 0x01,
-0x0d, 0xff, 0x00, 0xfe, 0xf0, 0xff, 0x3d, 0x00, 0xf4, 0x3f, 0xf0, 0xaf,
-0x72, 0xf8, 0x55, 0xaa, 0xd2, 0x7b, 0xcf, 0x3f, 0xfc, 0xe1, 0x5b, 0xa9,
-0x80, 0xff, 0x93, 0xff, 0x81, 0x87, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0x1e,
-0x67, 0xf2, 0x1f, 0xf8, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xc0, 0x7f, 0xe0,
-0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
-0x0f, 0x00, 0xdc, 0x7f, 0xfe, 0x73, 0xfb, 0xff, 0xf4, 0x22, 0x1f, 0xde,
-0xc0, 0x9f, 0x40, 0x5d, 0x63, 0xc0, 0x75, 0xf8, 0xe5, 0x3f, 0xb5, 0xff,
-0xdd, 0xef, 0xf8, 0xe1, 0xbf, 0x07, 0x00, 0xfe, 0x7f, 0xff, 0x9d, 0xfc,
-0xff, 0x00, 0x3f, 0x0f, 0xfe, 0xff, 0x7f, 0xf2, 0xfc, 0x03, 0xfc, 0x3c,
-0xff, 0xff, 0x3f, 0xc0, 0xf0, 0xfd, 0x64, 0xf0, 0x08, 0x90, 0x00, 0x00,
-0xfe, 0xbf, 0xff, 0xdc, 0x87, 0x37, 0xae, 0x88, 0xfb, 0x0f, 0xfc, 0x33,
-0x1f, 0xfe, 0x98, 0x96, 0xcd, 0xff, 0xff, 0x5f, 0x7e, 0x78, 0xa7, 0xba,
-0x00, 0x04, 0x48, 0x00, 0x00, 0xff, 0x81, 0x7f, 0xf2, 0xc3, 0x3b, 0x13,
-0xfd, 0xfd, 0x37, 0xff, 0x3f, 0x0f, 0xff, 0x7e, 0xd6, 0xf7, 0xff, 0xfd,
-0xe5, 0x3b, 0xfc, 0x71, 0x00, 0x80, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0,
-0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
-0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe, 0x7b, 0x00, 0xe0, 0xff,
-0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
-0x3f, 0x80, 0x7f, 0xc3, 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
-0xff, 0x3d, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
-0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
-0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x1e, 0x00, 0xf0, 0x1f, 0xf8, 0x07,
-0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
-0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, 0x00, 0xfc, 0x7f, 0x0f,
-0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
-0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, 0xc0, 0xbf, 0xe1, 0x1f,
-0x07, 0x00, 0xfe, 0xbf, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
-0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xe0, 0x1f, 0xc0, 0x7f,
-0x0f, 0xe0, 0xdf, 0xf0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
-0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
-0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
-
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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-

Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h	2008-04-06 04:26:19 UTC (rev 3218)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000033.h	2008-04-07 17:49:57 UTC (rev 3219)
@@ -1,163 +0,0 @@
-/*
- ============================================================
- (c) Advanced Micro Devices, Inc., 2004-2005
-
- The  enclosed microcode  is intended  to be  used  with AMD
- Microprocessors.  You  may   copy,  view  and  install  the
- enclosed microcode  only for development  and deployment of
- firmware,  BIOS,  or  operating  system code  for  computer
- systems   that  contain  AMD   processors.   You   are  not
- authorized  to use  the  enclosed microcode  for any  other
- purpose.
-
- THE  MICROCODE IS PROVIDED  "AS IS"  WITHOUT ANY  EXPRESS OR
- IMPLIED WARRANTY  OF ANY KIND, INCLUDING BUT  NOT LIMITED TO
- WARRANTIES    OF    MERCHANTABILITY,   NON-    INFRINGEMENT,
- TITLE,FITNESS  FOR  ANY  PARTICULAR PURPOSE,  OR  WARRANTIES
- ARISING FROM CONDUCT, COURSE  OF DEALING, OR USAGE OF TRADE.
- AMD does not assume  any responsibility for any errors which
- may  appear   in  this   microcode  or  any   other  related
- information provided  to you by  AMD, or result from  use of
- this microcode.   AMD is not obligated  to furnish, support,
- or  make   any  further  information,   software,  technical
- information, know-how, or show-how available related to this
- microcode.
-
- The  microcode is provided  with "RESTRICTED  RIGHTS."  Use,
- duplication, or disclosure by the U.S. Government is subject
- to  the  restrictions as  set  forth  in  FAR 52.227-14  and
- DFAR252.227-7013,  et seq.,  or its  successor.  Use  of the
- microcode    by    the    U.S.     Government    constitutes
- acknowledgement  of   AMD's  proprietary  rights   in  them.
- ============================================================
-*/
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-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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-
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-

Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h	2008-04-06 04:26:19 UTC (rev 3218)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000035.h	2008-04-07 17:49:57 UTC (rev 3219)
@@ -1,163 +0,0 @@
-/*
- ============================================================
- (c) Advanced Micro Devices, Inc., 2004-2005
-
- The  enclosed microcode  is intended  to be  used  with AMD
- Microprocessors.  You  may   copy,  view  and  install  the
- enclosed microcode  only for development  and deployment of
- firmware,  BIOS,  or  operating  system code  for  computer
- systems   that  contain  AMD   processors.   You   are  not
- authorized  to use  the  enclosed microcode  for any  other
- purpose.
-
- THE  MICROCODE IS PROVIDED  "AS IS"  WITHOUT ANY  EXPRESS OR
- IMPLIED WARRANTY  OF ANY KIND, INCLUDING BUT  NOT LIMITED TO
- WARRANTIES    OF    MERCHANTABILITY,   NON-    INFRINGEMENT,
- TITLE,FITNESS  FOR  ANY  PARTICULAR PURPOSE,  OR  WARRANTIES
- ARISING FROM CONDUCT, COURSE  OF DEALING, OR USAGE OF TRADE.
- AMD does not assume  any responsibility for any errors which
- may  appear   in  this   microcode  or  any   other  related
- information provided  to you by  AMD, or result from  use of
- this microcode.   AMD is not obligated  to furnish, support,
- or  make   any  further  information,   software,  technical
- information, know-how, or show-how available related to this
- microcode.
-
- The  microcode is provided  with "RESTRICTED  RIGHTS."  Use,
- duplication, or disclosure by the U.S. Government is subject
- to  the  restrictions as  set  forth  in  FAR 52.227-14  and
- DFAR252.227-7013,  et seq.,  or its  successor.  Use  of the
- microcode    by    the    U.S.     Government    constitutes
- acknowledgement  of   AMD's  proprietary  rights   in  them.
- ============================================================
-*/
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-
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-

Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c	2008-04-06 04:26:19 UTC (rev 3218)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/pstate.c	2008-04-07 17:49:57 UTC (rev 3219)
@@ -1,456 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/pae.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-
-#include "../../../northbridge/amd/amdfam10/amdfam10.h"
-
-#include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/mem.h>
-
-#include <cpu/amd/quadcore.h>
-
-#include <cpu/amd/model_10xxx_msr.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-extern device_t get_node_pci(u32 nodeid, u32 fn);
-
-#include "fidvid_common.c"
-
-#define PSTATES_DEBUG 0
-
-
-
-static void inline dump_msr_pstates(u32 nodes)
-{
-#if PSTATES_DEBUG==1
-	int i, j;
-	for(j=0; j<5; j++) {
-		printk_debug("P%d:", j);
-		for(i=0;i<nodes;i++)  {
-			printk_debug(" [%08x %08x] ", sysconf.msr_pstate[i*5+j].hi, sysconf.msr_pstate[i*5+j].lo);
-		}
-		printk_debug("\n");
-	}
-#endif
-}
-
-
-static void inline dump_p(const char *p_c, u32 nodes, u32 *p)
-{
-#if PSTATES_DEBUG==1
-	int i, j;
-		printk_debug(p_c);
-		printk_debug("p:");
-		for(i=0;i<nodes;i++)  {
-			printk_debug(" %d ", p[i]);
-		}
-		printk_debug("\n");
-
-#endif
-}
-
-
-//according the pstate and make it work conformed to mixed conf system
-static u32 get_pwrvalue(u32 val)
-{
-	u32 times;
-	switch((val>>8)&3) {
-	case 0: times = 1000; break;
-	case 1: times = 100;  break;
-	case 2: times = 10;   break;
-	default:
-		//error
-		times = 1;
-	}
-
-	return (val & 0xff) * times;
-
-}
-
-
-static u32 get_powerstep(u32 val)
-{
-	u32 time;
-	if(val<4) {time = (4 - val)*100;}
-	else if(val<8) { time = (9+4-val)*10;}
-	else { time = (10+8-val) * 5; }
-
-	return time;
-
-}
-
-
-static u32 get_plllocktime(u32 val)
-{
-	u32 time;
-	switch(val) {
-	case 0:
-	case 1:
-	case 2:
-	case 3:
-		time = val+1; break;
-	case 4: time = 8; break;
-	case 5: time = 16; break;
-	default:
-		//erro2
-		time = 1;
-	}
-	return time;
-}
-
-
-static void disable_pstate(u32 nodes, u32 *p)
-{
-	int i;
-
-	for(i=0;i<nodes; i++) {
-		sysconf.msr_pstate[i*5+p[i]].hi &= ~(1<<(63-32));
-	}
-}
-
-
-static void match_pstate(u32 nodes, u32 *p)
-{
-	int i;
-	u32 corecof_min, pwrvalue_max, pwrval_max;
-	u32 enable;
-	enable = (sysconf.msr_