[coreboot] DBE62 v3 strangeness since v3 rev 649

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Tue Apr 15 23:52:30 CEST 2008

Hi Ron,

this one is for you: Your commit 649 had a few probably unintended side
- set_delay_control thinks zero DIMMs are installed because
SPD_PRIMARY_SDRAM_WIDTH does not exist in the SPD table.
- Due to that, the GLCP_DELAY_CONTROLS msr is set to 0.

Please confirm that you really wanted these settings.


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