[coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset

[Jeremy Jackson]

On Wed, 2008-04-16 at 18:12 +0200, Carl-Daniel Hailfinger wrote:

> > What is the longest amount of time between any two POST code updates?
> > The only think I can think of is ECC ram clearing.
> >   
> 
> One hour, probably longer. A payload is not guaranteed to poke the TCO
> timer, so as long as the payload is running, the TCO timer could fire in
> theory.

This is another feature to add to the list of payload flags.
PAYLOAD_FLAG_HANDLES_TCO

assumes payload is specific to the board's TCO timer, 

or just disable it for the *payload*... still useful for normal/fallback
handling.

-- 
Jeremy Jackson
Coplanar Networks
(519)489-4903
http://www.coplanar.net
jerj at coplanar.net