[coreboot] DBE62 v3 strangeness since v3 rev 649
mart.raudsepp at artecdesign.ee
Fri Apr 18 01:13:29 CEST 2008
> On Thu, Apr 17, 2008 at 4:25 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> On 17.04.2008 18:08, ron minnich wrote:
>> > are you running on a dbe62? good news!
>> No, Mart Raudsepp ran it. I'm one of those strange people who actually
>> read logs and compare them to what would be expected by reading the
>> By the way, diffing coreboot output at maximum verbosity before and
>> after a patch is a great way to make sure the commit didn't do
>> unintended things.
> it's weird as I test before every commit. So why this failed? I don't
I should clarify that the device doesn't fail boot, it works (and hence I
was able to get the MSR dumps with Carl-Daniel's tool), but perhaps not
optimally due to the dubious register values as probably seen from the
dump I sent him. I haven't had any time to parse and understand any of the
values personally yet.
>> Marc Jones wrote that the current state of code is unlikely to work.
>> That's another reason why I would like to know how the
>> SPD_PRIMARY_SDRAM_WIDTH removal happened.
> That puzzles me too. As of my last test it was all working. I will try
> to do a burn tonight before and after svn up and see how it goes.
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