[coreboot] problem about ioapic

Rudolf Marek r.marek at assembler.cz
Mon Apr 21 11:23:50 CEST 2008

aaron lwe wrote:
>>  I think I dont have the IRQ in my tables for for asus a8v-e SE because they
>> use gigabit card. Just add it to ACPI/MADT table.
> It turned out that the ethernet card get its memory mapped address at
> 0xfec00000,
> which should be reserved. I manually add 0xfec00000 and 0xfee00000 in
> filo as two
> reserved regions when doing a e820 map convert and then linux
> automatically changed
> ethernet card's memory base address to 0x40000000, problem solved.
> I haven't time to see this pci memory allocation issuse, just make it
> work this way for now.
> and coreboot doesn't seem to have a way to reserve a memory region, does it?

No it does not. You can only make holes to memory map. Question is why the PCI 
allocator in coreboot did this. Imho there is somehere some minus so it starts 
bellow the fec00000 (at least for K8).

>>  And dont forget to copy the shadow RAM register settings from NB back to
>> southbridge, (D0F7 registers around 0x60, check the NB code of k8t890) or
>>  the dd if=/dev/sda of=/dev/null will not work and DMA will timeout just
>> after you will all memory with the buffers - and lastly the 0xC0000-0xEFFFF,
>> which will fail the DMA.
> Thanks for the information.
> I've another MB with a C7+CN700+VT8237R, and I cannot make apic work on it yet.
> The worked MB is VIA eden + CN700 + VT8237R.
> I put the following code in vt8237r_lpc.c:
> l[0] = 0x1;
> val = l[4];
> printk_debug("ioapic ver is %d\n", val);
> and the result is 0. the result is right when using the worked MB.
> So I guess maybe C7 has more to configure than just the code in lapic.c.

But the IOAPIC is independent of CPU lapic. It seems that some memory routing is 


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