[coreboot] The discussion of PCI memory IO

Peter Stuge peter at stuge.se
Wed Apr 23 23:03:20 CEST 2008

On Wed, Apr 23, 2008 at 05:20:37PM +0800, Feng, Libo wrote:
> So, you mean no access will be routined to the last GB memory even
> it exists physically, due to FLASH ROM, PCI memory IO, APIC and OS
> reservation?

Not with physical 32-bit addresses, but using PAE it is possible to
reach beyond 4GB, where RAM over 3GB would be available.


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