From Marc.Karasek at Sun.COM  Fri Aug  1 00:48:23 2008
From: Marc.Karasek at Sun.COM (Marc Karasek)
Date: Thu, 31 Jul 2008 18:48:23 -0400
Subject: [coreboot] section .id cant be allocated in segment 1 - error
In-Reply-To: <9aae56cb0807302220l4f3ae5bfl3c127c18d36537ff@mail.gmail.com>
References: <9aae56cb0807290227r3a9e78den5c2919d423e78ba6@mail.gmail.com>
	<20080729133343.22509.qmail@stuge.se> <488F6B0A.80309@sun.com>
	<9aae56cb0807302220l4f3ae5bfl3c127c18d36537ff@mail.gmail.com>
Message-ID: <48924137.3080001@sun.com>

Dump Fedora 8 as soon as you can.

There should be a big fat warning on Coreboot website to NOT use Fedora 8.

*********************
Marc Karasek
MTS
Sun Microsystems
mailto:marc.karasek at sun.com
ph:770.360.6415
*********************



Amrish Purohit wrote:
> Marc Karasek,
>
> you are right. that was compiler problem. i got prpblem compiling 
> coreboot in fedora 8 distribution. but it compiled nicely in cent os 5 
> distribution.
> thanks for your support.
> Amrish purohit
>
>
>
> On Wed, Jul 30, 2008 at 12:40 AM, Marc Karasek <Marc.Karasek at sun.com 
> <mailto:Marc.Karasek at sun.com>> wrote:
>
>     This is a compiler problem.  What gcc version etc.. are you using?
>
>     *********************
>     Marc Karasek
>     MTS
>     Sun Microsystems
>     mailto:marc.karasek at sun.com <mailto:marc.karasek at sun.com>
>     ph:770.360.6415
>     *********************
>
>
>
>
>     Peter Stuge wrote:
>
>         Hello Amrish,
>
>         On Tue, Jul 29, 2008 at 02:57:05PM +0530, Amrish Purohit wrote:
>          
>
>             hi all
>             i am implementing coreboot in qemu with linux kernel as a
>             payload.
>             but when i compile coreboot it shows above subject error.
>             i have
>             changed the ROM_SIZE option to 2048x1024 and my linux.elf
>             size is
>             440785 bytes.
>             so what may be wrong.
>                
>
>
>         Sorry, but we are unable to help you without more information.
>
>         Please send the output from the buildtarget and make commands.
>
>
>         //Peter
>
>         --
>         coreboot mailing list
>         coreboot at coreboot.org <mailto:coreboot at coreboot.org>
>         http://www.coreboot.org/mailman/listinfo/coreboot
>          
>
>
>     --
>     coreboot mailing list
>     coreboot at coreboot.org <mailto:coreboot at coreboot.org>
>     http://www.coreboot.org/mailman/listinfo/coreboot
>
>



From svn at coreboot.org  Fri Aug  1 13:20:10 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:20:10 +0200
Subject: [coreboot] r3438 - trunk/coreboot-v2/util/newconfig
Message-ID: <mailman.1725.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:20:09 +0200 (Fri, 01 Aug 2008)
New Revision: 3438

Modified:
   trunk/coreboot-v2/util/newconfig/config.g
Log:
fix typos in config.g, and don't arbitrarily hide some build information
(doesn't make sense in v2). For silent build, use make -s
(trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2008-07-23 23:22:59 UTC (rev 3437)
+++ trunk/coreboot-v2/util/newconfig/config.g	2008-08-01 11:20:09 UTC (rev 3438)
@@ -223,7 +223,7 @@
 		# init object files added by 'initobject' directive
 		self.initobjectrules = {}
 
-		# driver files added by 'drive' directive
+		# driver files added by 'driver' directive
 		self.driverrules = {}
 
 		# loader scripts added by 'ldscript' directive
@@ -2072,11 +2072,9 @@
 		if (type  == 'S'):
 			# for .S, .o depends on .s
 			file.write("%s: %s.s\n" % (init[0], init[3]))
-        		file.write("\t at echo $(CC) ... -o $@ $<\n")
         		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
 			# and .s depends on .S
 			file.write("%s.s: %s\n" % (init[3], source))
-			file.write("\t at echo $(CPP) ... $< > $@\n")
 			# Note: next 2 lines are ONE output line!
         		file.write("\t$(CPP) $(CPPFLAGS) $< ")
 			file.write(">$@.new && mv $@.new $@\n")
@@ -2091,11 +2089,9 @@
 		if (type  == 'S'):
 			# for .S, .o depends on .s
 			file.write("%s: %s.s\n" % (obj[0], obj[3]))
-        		file.write("\t at echo $(CC) ... -o $@ $<\n")
         		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
 			# and .s depends on .S
 			file.write("%s.s: %s\n" % (obj[3], source))
-			file.write("\t at echo $(CPP) ... $< > $@\n")
 			# Note: next 2 lines are ONE output line!
         		file.write("\t$(CPP) $(CPPFLAGS) $< ")
 			file.write(">$@.new && mv $@.new $@\n")




From svn at coreboot.org  Fri Aug  1 13:20:34 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:20:34 +0200
Subject: [coreboot] r3439 - trunk/coreboot-v2/util/buildrom
Message-ID: <mailman.1726.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:20:33 +0200 (Fri, 01 Aug 2008)
New Revision: 3439

Modified:
   trunk/coreboot-v2/util/buildrom/buildrom.c
Log:
fix build warnings for buildrom (trivial)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/util/buildrom/buildrom.c
===================================================================
--- trunk/coreboot-v2/util/buildrom/buildrom.c	2008-08-01 11:20:09 UTC (rev 3438)
+++ trunk/coreboot-v2/util/buildrom/buildrom.c	2008-08-01 11:20:33 UTC (rev 3439)
@@ -66,15 +66,15 @@
 		fatal("stat of infile");
 	if (payloadbuf.st_size > (romsize - size)){
 		fprintf(stderr, "ERROR: payload (%d) + coreboot (%d) - Size is %d bytes larger than ROM size (%d).\n", 
-				payloadbuf.st_size, size, 
-				payloadbuf.st_size+size-romsize,
+				(int)payloadbuf.st_size, size, 
+				(int)(payloadbuf.st_size+size-romsize),
 				romsize);
 		exit(1);
 	}
 
 	printf("Payload: %d coreboot: %d ROM size: %d Left space: %d\n",
-			payloadbuf.st_size, size, romsize,
-			romsize-payloadbuf.st_size-size);
+			(int)payloadbuf.st_size, size, romsize,
+			(int)(romsize-payloadbuf.st_size-size));
 
 	cp = malloc(romsize);
 	if (!cp)




From svn at coreboot.org  Fri Aug  1 13:21:48 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:21:48 +0200
Subject: [coreboot] r3440 - in trunk/coreboot-v2/targets/iwill: dk8s2 dk8x
Message-ID: <mailman.1727.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:21:47 +0200 (Fri, 01 Aug 2008)
New Revision: 3440

Modified:
   trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb
   trunk/coreboot-v2/targets/iwill/dk8x/Config.lb
Log:
CONFIG_LOGICAL_CPUS=2 does not make sense because it is a BOOL. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb	2008-08-01 11:20:33 UTC (rev 3439)
+++ trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb	2008-08-01 11:21:47 UTC (rev 3440)
@@ -30,7 +30,7 @@
 ###
 option CONFIG_SMP=1
 option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=2
+#option CONFIG_LOGICAL_CPUS=1
 option CONFIG_MAX_PHYSICAL_CPUS=2
 #
 ###

Modified: trunk/coreboot-v2/targets/iwill/dk8x/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/iwill/dk8x/Config.lb	2008-08-01 11:20:33 UTC (rev 3439)
+++ trunk/coreboot-v2/targets/iwill/dk8x/Config.lb	2008-08-01 11:21:47 UTC (rev 3440)
@@ -30,7 +30,7 @@
 ###
 option CONFIG_SMP=1
 option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=2
+#option CONFIG_LOGICAL_CPUS=1
 option CONFIG_MAX_PHYSICAL_CPUS=2
 #
 ###




From svn at coreboot.org  Fri Aug  1 13:25:42 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:25:42 +0200
Subject: [coreboot] r3441 - in trunk/coreboot-v2/src/devices: . emulator
	emulator/pcbios emulator/x86emu
Message-ID: <mailman.1728.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:25:41 +0200 (Fri, 01 Aug 2008)
New Revision: 3441

Modified:
   trunk/coreboot-v2/src/devices/emulator/biosemu.c
   trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.c
   trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.h
   trunk/coreboot-v2/src/devices/emulator/x86emu/decode.h
   trunk/coreboot-v2/src/devices/pci_device.c
   trunk/coreboot-v2/src/devices/pci_rom.c
   trunk/coreboot-v2/src/devices/pciexp_device.c
Log:
fix typos and warnings in the device tree code (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/devices/emulator/biosemu.c
===================================================================
--- trunk/coreboot-v2/src/devices/emulator/biosemu.c	2008-08-01 11:21:47 UTC (rev 3440)
+++ trunk/coreboot-v2/src/devices/emulator/biosemu.c	2008-08-01 11:25:41 UTC (rev 3441)
@@ -7,6 +7,8 @@
 
 #include <x86emu/x86emu.h>
 
+#include "pcbios/pcibios.h"
+
 #define MEM_WB(where, what) wrb(where, what)
 #define MEM_WW(where, what) wrw(where, what)
 #define MEM_WL(where, what) wrl(where, what)
@@ -22,6 +24,10 @@
 u32 x_inl(u16 port);
 void x_outl(u16 port, u32 val);
 
+
+// sys.c
+void X86EMU_setMemBase(void *base, size_t size);
+
 /* general software interrupt handler */
 u32 getIntVect(int num)
 {

Modified: trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.c
===================================================================
--- trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.c	2008-08-01 11:21:47 UTC (rev 3440)
+++ trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.c	2008-08-01 11:25:41 UTC (rev 3441)
@@ -7,9 +7,9 @@
 
 #include "pcibios.h"
 
-int pcibios_handler()
+int pcibios_handler(void)
 {
-	int i, ret = 0;
+	int  ret = 0;
 	struct device *dev = 0;
 
 	switch (X86_AX) {

Modified: trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.h
===================================================================
--- trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.h	2008-08-01 11:21:47 UTC (rev 3440)
+++ trunk/coreboot-v2/src/devices/emulator/pcbios/pcibios.h	2008-08-01 11:25:41 UTC (rev 3441)
@@ -25,4 +25,7 @@
 	SET_FAILED		= 0x88,
 	BUFFER_TOO_SMALL	= 0x89
 };
-#endif /* PCI_BIOS_H */
\ No newline at end of file
+
+int pcibios_handler(void);
+
+#endif /* PCI_BIOS_H */

Modified: trunk/coreboot-v2/src/devices/emulator/x86emu/decode.h
===================================================================
--- trunk/coreboot-v2/src/devices/emulator/x86emu/decode.h	2008-08-01 11:21:47 UTC (rev 3440)
+++ trunk/coreboot-v2/src/devices/emulator/x86emu/decode.h	2008-08-01 11:25:41 UTC (rev 3441)
@@ -79,6 +79,7 @@
 unsigned decode_rm00_address(int rm);
 unsigned decode_rm01_address(int rm);
 unsigned decode_rm10_address(int rm);
+unsigned decode_rmXX_address(int mod, int rm);
 
 #ifdef  __cplusplus
 }                       			/* End of "C" linkage for C++   	*/

Modified: trunk/coreboot-v2/src/devices/pci_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_device.c	2008-08-01 11:21:47 UTC (rev 3440)
+++ trunk/coreboot-v2/src/devices/pci_device.c	2008-08-01 11:25:41 UTC (rev 3441)
@@ -647,6 +647,7 @@
 void pci_dev_init(struct device *dev)
 {
 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
+	void run_bios(struct device * dev, unsigned long addr);
 	struct rom_header *rom, *ram;
 
 #if CONFIG_PCI_ROM_RUN != 1
@@ -666,7 +667,7 @@
 	if (ram == NULL)
 		return;
 
-	run_bios(dev, ram);
+	run_bios(dev, (unsigned long)ram);
 
 #if CONFIG_CONSOLE_VGA == 1
 	/* vga_inited is a trigger of the VGA console code. */
@@ -1070,7 +1071,7 @@
 	}
 	post_code(0x25);
 
-	/* Die if any leftover Static devices are are found.  
+	/* Die if any left over static devices are are found.  
 	 * There's probably a problem in the Config.lb.
 	*/
 	if(old_devices) {
@@ -1078,7 +1079,7 @@
 		for(left = old_devices; left; left = left->sibling) {
 			printk_err("%s\n", dev_path(left));
 		}
-		die("PCI: Left over static devices.  Check your Config.lb\n");
+		printk_warning("PCI: Left over static devices.  Check your mainboard Config.lb\n");
 	}
 
 	/* For all children that implement scan_bus (i.e. bridges)

Modified: trunk/coreboot-v2/src/devices/pci_rom.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_rom.c	2008-08-01 11:21:47 UTC (rev 3440)
+++ trunk/coreboot-v2/src/devices/pci_rom.c	2008-08-01 11:25:41 UTC (rev 3441)
@@ -26,6 +26,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <string.h>
 
 struct rom_header * pci_rom_probe(struct device *dev)
 {
@@ -62,7 +63,7 @@
 		return NULL;
 	}
 
-	rom_data = (unsigned char *) rom_header + le32_to_cpu(rom_header->data);
+	rom_data = (struct pci_data *) ((void *)rom_header + le32_to_cpu(rom_header->data));
 	printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
 		    rom_data->vendor, rom_data->device);
 	if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
@@ -95,8 +96,8 @@
 	rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
 
 	do {
-		rom_header = (unsigned char *) rom_header + image_size; // get next image
-	        rom_data = (unsigned char *) rom_header + le32_to_cpu(rom_header->data);
+		rom_header = (struct rom_header *)((void *) rom_header + image_size); // get next image
+	        rom_data = (struct pci_data *)((void *) rom_header + le32_to_cpu(rom_header->data));
         	image_size = le32_to_cpu(rom_data->ilen) * 512;
 	} while ((rom_data->type!=0) && (rom_data->indicator!=0));  // make sure we got x86 version
 
@@ -111,7 +112,7 @@
 #endif
 		printk_debug("copying VGA ROM Image from 0x%x to 0x%x, 0x%x bytes\n",
 			    rom_header, PCI_VGA_RAM_IMAGE_START, rom_size);
-		memcpy(PCI_VGA_RAM_IMAGE_START, rom_header, rom_size);
+		memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size);
 		return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START);
 	} else {
 		printk_debug("copying non-VGA ROM Image from 0x%x to 0x%x, 0x%x bytes\n",

Modified: trunk/coreboot-v2/src/devices/pciexp_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/pciexp_device.c	2008-08-01 11:21:47 UTC (rev 3440)
+++ trunk/coreboot-v2/src/devices/pciexp_device.c	2008-08-01 11:25:41 UTC (rev 3441)
@@ -34,7 +34,7 @@
 		/* error... */
 		return;
 	}
-	printk_debug("PCIEXP: tunning %s\n", dev_path(dev));
+	printk_debug("PCIe: tunning %s\n", dev_path(dev));
 #warning "IMPLEMENT PCI EXPRESS TUNING"
 }
 




From svn at coreboot.org  Fri Aug  1 13:31:09 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:31:09 +0200
Subject: [coreboot] r3442 - in trunk/coreboot-v2/src/arch/i386: include/arch
	include/arch/smp smp
Message-ID: <mailman.1729.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:31:08 +0200 (Fri, 01 Aug 2008)
New Revision: 3442

Modified:
   trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h
   trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h
   trunk/coreboot-v2/src/arch/i386/smp/mpspec.c
Log:
fix warnings, make mptable struct members explicitly packed, as they're
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h	2008-08-01 11:25:41 UTC (rev 3441)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h	2008-08-01 11:31:08 UTC (rev 3442)
@@ -37,8 +37,8 @@
 #define SRAT_TABLE	      "SRAT    "
 #define SLIT_TABLE	      "SLIT    "
 
-#define OEM_ID                "LXBIOS"
-#define ASLC                  "NONE"
+#define OEM_ID                "CORE  "
+#define ASLC                  "CORE"
 
 /* ACPI 2.0 table RSDP */
 
@@ -219,7 +219,7 @@
 	struct acpi_table_header header;
 	u32 firmware_ctrl;
 	u32 dsdt;
-	u8 res1;
+	u8 model;
 	u8 preferred_pm_profile;
 	u16 sci_int;
 	u32 smi_cmd;

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h	2008-08-01 11:25:41 UTC (rev 3441)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h	2008-08-01 11:31:08 UTC (rev 3442)
@@ -35,7 +35,7 @@
 	unsigned char mpf_feature3;	/* Unused (0)			*/
 	unsigned char mpf_feature4;	/* Unused (0)			*/
 	unsigned char mpf_feature5;	/* Unused (0)			*/
-};
+} __attribute__((packed));
 
 struct mp_config_table
 {
@@ -53,7 +53,7 @@
 	unsigned short mpe_length;	/* Extended Table size */
 	unsigned char mpe_checksum;	/* Extended Table checksum */
 	unsigned char reserved;
-};
+} __attribute__((packed));
 
 /* Followed by entries */
 
@@ -77,14 +77,14 @@
 #define MPC_CPU_FAMILY_MASK	0xF00
 	unsigned long mpc_featureflag;	/* CPUID feature value */
 	unsigned long mpc_reserved[2];
-};
+} __attribute__((packed));
 
 struct mpc_config_bus
 {
 	unsigned char mpc_type;
 	unsigned char mpc_busid;
-	unsigned char mpc_bustype[6] __attribute((packed));
-};
+	unsigned char mpc_bustype[6];
+} __attribute__((packed));
 
 #define BUSTYPE_EISA	"EISA"
 #define BUSTYPE_ISA	"ISA"
@@ -102,7 +102,7 @@
 	unsigned char mpc_flags;
 #define MPC_APIC_USABLE		0x01
 	unsigned long mpc_apicaddr;
-};
+} __attribute__((packed));
 
 struct mpc_config_intsrc
 {
@@ -113,7 +113,7 @@
 	unsigned char mpc_srcbusirq;
 	unsigned char mpc_dstapic;
 	unsigned char mpc_dstirq;
-};
+} __attribute__((packed));
 
 enum mp_irq_source_types {
 	mp_INT = 0,
@@ -142,7 +142,7 @@
 	unsigned char mpc_destapic;	
 #define MP_APIC_ALL	0xFF
 	unsigned char mpc_destapiclint;
-};
+} __attribute__((packed));
 
 /*
  *	Default configurations
@@ -174,7 +174,7 @@
 struct mp_exten_config {
 	unsigned char mpe_type;
 	unsigned char mpe_length;
-};
+} __attribute__((packed));
 
 typedef struct mp_exten_config *mpe_t;
 
@@ -190,7 +190,7 @@
 	unsigned int  mpe_address_base_high;
 	unsigned int  mpe_address_length_low;
 	unsigned int  mpe_address_length_high;
-};
+} __attribute__((packed));
 
 struct mp_exten_bus_hierarchy {
 	unsigned char mpe_type;
@@ -200,7 +200,7 @@
 #define BUS_SUBTRACTIVE_DECODE 1
 	unsigned char mpe_parent_busid;
 	unsigned char reserved[3];
-};
+} __attribute__((packed));
 
 struct mp_exten_compatibility_address_space {
 	unsigned char mpe_type;
@@ -226,7 +226,7 @@
 	 * XFB0 - XFBB
 	 * XFC0 - XCDF
 	 */
-};
+} __attribute__((packed));
 
 /* Default local apic addr */
 #define LAPIC_ADDR 0xFEE00000
@@ -240,7 +240,7 @@
 	unsigned int featureflag);
 void smp_write_processors(struct mp_config_table *mc);
 void smp_write_bus(struct mp_config_table *mc,
-	unsigned char id, unsigned char *bustype);
+	unsigned char id, char *bustype);
 void smp_write_ioapic(struct mp_config_table *mc,
 	unsigned char id, unsigned char ver, 
 	unsigned long apicaddr);

Modified: trunk/coreboot-v2/src/arch/i386/smp/mpspec.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/smp/mpspec.c	2008-08-01 11:25:41 UTC (rev 3441)
+++ trunk/coreboot-v2/src/arch/i386/smp/mpspec.c	2008-08-01 11:31:08 UTC (rev 3442)
@@ -155,7 +155,7 @@
 }
 
 void smp_write_bus(struct mp_config_table *mc,
-	unsigned char id, unsigned char *bustype)
+	unsigned char id, char *bustype)
 {
 	struct mpc_config_bus *mpc;
 	mpc = smp_next_mpc_entry(mc);




From svn at coreboot.org  Fri Aug  1 13:32:12 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:32:12 +0200
Subject: [coreboot] r3443 - trunk/coreboot-v2/src/lib
Message-ID: <mailman.1730.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:32:12 +0200 (Fri, 01 Aug 2008)
New Revision: 3443

Modified:
   trunk/coreboot-v2/src/lib/Config.lb
Log:
clean up Config.lb in lib/ (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/lib/Config.lb	2008-08-01 11:31:08 UTC (rev 3442)
+++ trunk/coreboot-v2/src/lib/Config.lb	2008-08-01 11:32:12 UTC (rev 3443)
@@ -1,6 +1,5 @@
 uses HAVE_FALLBACK_BOOT
 uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_USBDEBUG_DIRECT
 
 object clog2.o
@@ -23,9 +22,7 @@
 makedefine .PHONY : version.o
 
 if CONFIG_USE_INIT
-#	if CONFIG_USE_PRINTK_IN_CAR
 	initobject uart8250.c
-#	end
 	initobject memset.o
 	initobject memcpy.o
 	initobject memcmp.o




From svn at coreboot.org  Fri Aug  1 13:35:48 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:35:48 +0200
Subject: [coreboot] r3444 - trunk/coreboot-v2/src/drivers/pci/onboard
Message-ID: <mailman.1731.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:35:46 +0200 (Fri, 01 Aug 2008)
New Revision: 3444

Modified:
   trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c
Log:
clean up comment in onboard.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c
===================================================================
--- trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c	2008-08-01 11:32:12 UTC (rev 3443)
+++ trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c	2008-08-01 11:35:46 UTC (rev 3444)
@@ -11,58 +11,60 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-/*you need to 
-	1.add
-                                                chip drivers/pci/onboard
-                                                        device pci x.0 on end
-                                                        register "rom_address" = "0xfff80000"
-                                                end
-	in your MB mainboard Config.lb
-	2. add 
-		#       48K for SCSI FW or ATI ROM
-		        option ROM_SIZE = 512*1024-48*1024
-	in your MB targets Config.lb, afer romimage "normal"
-	3. create you vgabios.bin under normal bios and put that in dir that targets Config residues.
-		# dd if=/dev/mem of=atix.rom skip=1536 count=96
-	4. after build coreboot.rom
-		# cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
-	or use nsxv to build you image
-		# time ./nsxv s2850
+/*
+ * How to use the onboard device driver for option rom execution:
+ *
+ * 1. You need to add the driver to your mainboard Config.lb:
+ *
+ *      chip drivers/pci/onboard
+ *	    device pci x.0 on end
+ *          register "rom_address" = "0xfff80000"
+ *      end
+ * 2. Reduce the size of your normal (or fallback) image, by adding the
+ *    following lines to your target Config.lb, after romimage "normal"
+ *      # 48K for SCSI FW or ATI ROM
+ *      option ROM_SIZE = 512*1024-48*1024
+ * 3. Create your vgabios.bin, for example using awardeco and put it in the
+ *    directory of your target Config.lb. You can also read an option rom from
+ *    a running system, but this is unreliable, as some option roms are changed
+ *    during execution:
+ *      #  dd if=/dev/mem of=atix.rom skip=1536 count=96
+ * 4. After you built coreboot.rom, attach the option rom to your coreboot
+ *    image:
+ *      # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
+ *
+ * Alternatively you can use the following script "nsxv" to build your image
+ * Usage:
+ * # ./nsxv s2850
+ *     
+ *     #!/bin/bash
+ *     MBVENDOR=tyan
+ *     MBMODEL=$1
+ *     LBROOT=/home/yhlu/xx/xx
+ *     
+ *     echo $1
+ *     date
+ *     
+ *     cd "$LBROOT/freebios2/targets"
+ *     rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL"
+ *     ./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt"
+ *     cd "$MBVENDOR/$MBMODEL/$MBMODEL"
+ *     #make clean
+ *     eval make &> "$LBROOT/x_m.txt"
+ *             if [ $? -eq 0 ]; then
+ *                     echo "ok."
+ *             else
+ *                     echo "FAILED! Log excerpt:"
+ *                     tail -n 15 "$LBROOT/x_m.txt"
+ *                     exit
+ *             fi
+ *     cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
+ *     cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
+ *     
+ *     date
+ *     
+ */
 
-put following in nsxv and put nsxv in your LBROOT
-
-#!/bin/bash
-MBVENDOR=tyan
-MBMODEL=$1
-LBROOT=/home/yhlu/xx/xx
-
-echo $1
-date
-
-cd "$LBROOT/freebios2/targets"
-rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL"
-./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt"
-cd "$MBVENDOR/$MBMODEL/$MBMODEL"
-#make clean
-eval make &> "$LBROOT/x_m.txt"
-        if [ $? -eq 0 ]; then
-                echo "ok."
-        else
-                echo "FAILED! Log excerpt:"
-                tail -n 15 "$LBROOT/x_m.txt"
-                exit
-        fi
-cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
-cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
-
-date
-
-
-*/
-		
-
-
-
 static void onboard_enable(device_t dev) 
 {
 	struct drivers_pci_onboard_config *conf;




From svn at coreboot.org  Fri Aug  1 13:36:41 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:36:41 +0200
Subject: [coreboot] r3445 - trunk/coreboot-v2/src/sdram
Message-ID: <mailman.1732.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:36:40 +0200 (Fri, 01 Aug 2008)
New Revision: 3445

Modified:
   trunk/coreboot-v2/src/sdram/generic_sdram.c
Log:
fix typo in commend of generic_sdram.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/sdram/generic_sdram.c
===================================================================
--- trunk/coreboot-v2/src/sdram/generic_sdram.c	2008-08-01 11:35:46 UTC (rev 3444)
+++ trunk/coreboot-v2/src/sdram/generic_sdram.c	2008-08-01 11:36:40 UTC (rev 3445)
@@ -52,7 +52,7 @@
 	}
 
 	/* Now that everything is setup enable the SDRAM.
-	 * Some chipsets do the work for use while on others 
+	 * Some chipsets do the work for us while on others 
 	 * we need to it by hand.
 	 */
 	print_debug("Ram3\r\n");




From svn at coreboot.org  Fri Aug  1 13:37:34 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:37:34 +0200
Subject: [coreboot] r3446 - trunk/coreboot-v2/src/config
Message-ID: <mailman.1733.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:37:33 +0200 (Fri, 01 Aug 2008)
New Revision: 3446

Modified:
   trunk/coreboot-v2/src/config/coreboot_ram.ld
Log:
fix typo in coreboot_ram.ld comment (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/config/coreboot_ram.ld
===================================================================
--- trunk/coreboot-v2/src/config/coreboot_ram.ld	2008-08-01 11:36:40 UTC (rev 3445)
+++ trunk/coreboot-v2/src/config/coreboot_ram.ld	2008-08-01 11:37:33 UTC (rev 3446)
@@ -98,7 +98,7 @@
 	_estack = .;
         _heap = .;
         .heap . : {
-                /* Reserve 256K for the heap */
+                /* Reserve HEAP_SIZE bytes for the heap */
                 . = HEAP_SIZE ;
                 . = ALIGN(4);
         }




From svn at coreboot.org  Fri Aug  1 13:38:24 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:38:24 +0200
Subject: [coreboot] r3447 - trunk/coreboot-v2/src/console
Message-ID: <mailman.1734.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:38:23 +0200 (Fri, 01 Aug 2008)
New Revision: 3447

Modified:
   trunk/coreboot-v2/src/console/vga_console.c
Log:
fix warning in vga console code (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/console/vga_console.c
===================================================================
--- trunk/coreboot-v2/src/console/vga_console.c	2008-08-01 11:37:33 UTC (rev 3446)
+++ trunk/coreboot-v2/src/console/vga_console.c	2008-08-01 11:38:23 UTC (rev 3447)
@@ -36,7 +36,7 @@
 	// these are globals
 	vga_line = 0;
 	vga_col = 0;
-	vidmem = (unsigned char *) VIDBUFFER;
+	vidmem = (char *) VIDBUFFER;
 	
 	// mainboard or chip specific init routines
 	// also loads font




From svn at coreboot.org  Fri Aug  1 13:39:35 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:39:35 +0200
Subject: [coreboot] r3448 - trunk/coreboot-v2/src/include
Message-ID: <mailman.1735.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:39:35 +0200 (Fri, 01 Aug 2008)
New Revision: 3448

Modified:
   trunk/coreboot-v2/src/include/string.h
Log:
function prototypes don't need extern. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/include/string.h
===================================================================
--- trunk/coreboot-v2/src/include/string.h	2008-08-01 11:38:23 UTC (rev 3447)
+++ trunk/coreboot-v2/src/include/string.h	2008-08-01 11:39:35 UTC (rev 3448)
@@ -4,13 +4,13 @@
 #include <stddef.h>
 #include <stdlib.h>
 
-extern void *memcpy(void *dest, const void *src, size_t n);
-extern void *memmove(void *dest, const void *src, size_t n);
-extern void *memset(void *s, int c, size_t n);
-extern int memcmp(const void *s1, const void *s2, size_t n);
+void *memcpy(void *dest, const void *src, size_t n);
+void *memmove(void *dest, const void *src, size_t n);
+void *memset(void *s, int c, size_t n);
+int memcmp(const void *s1, const void *s2, size_t n);
+void *malloc(size_t size);
+int sprintf(char * buf, const char *fmt, ...);
 
-extern int sprintf(char * buf, const char *fmt, ...);
-
 // yes, linux has fancy ones. We don't care. This stuff gets used 
 // hardly at all. And the pain of including those files is just too high.
 




From svn at coreboot.org  Fri Aug  1 13:40:16 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:40:16 +0200
Subject: [coreboot] r3449 - trunk/coreboot-v2/src/include
Message-ID: <mailman.1736.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:40:16 +0200 (Fri, 01 Aug 2008)
New Revision: 3449

Modified:
   trunk/coreboot-v2/src/include/spd.h
Log:
add some SPD values from specs. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/include/spd.h
===================================================================
--- trunk/coreboot-v2/src/include/spd.h	2008-08-01 11:39:35 UTC (rev 3448)
+++ trunk/coreboot-v2/src/include/spd.h	2008-08-01 11:40:16 UTC (rev 3449)
@@ -73,6 +73,7 @@
 #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME      33 /* Command and address signal input hold time */
 #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME    34 /* Data signal input setup time */
 #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME     35 /* Data signal input hold time */
+#define SPD_WRITE_RECOVERY_TIME             36 /* Write recovery time (tWR) */
 #define SPD_SPD_DATA_REVISION_CODE          62 /* SPD data revision code */
 #define SPD_CHECKSUM_FOR_BYTES_0_TO_62      63 /* Checksum for bytes 0-62 */
 #define SPD_MANUFACTURER_JEDEC_ID_CODE      64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
@@ -129,6 +130,11 @@
 #define SPD_CAS_LATENCY_3_5              0x20
 #define SPD_CAS_LATENCY_4_0              0x40
 
+#define SPD_CAS_LATENCY_DDR2_3		(1 << 3)
+#define SPD_CAS_LATENCY_DDR2_4		(1 << 4)
+#define SPD_CAS_LATENCY_DDR2_5		(1 << 5)
+#define SPD_CAS_LATENCY_DDR2_6		(1 << 6)
+
 /* SPD_SUPPORTED_BURST_LENGTHS values. */
 #define SPD_BURST_LENGTH_1               1
 #define SPD_BURST_LENGTH_2               2




From svn at coreboot.org  Fri Aug  1 13:48:00 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:48:00 +0200
Subject: [coreboot] r3450 - trunk/coreboot-v2/src/stream
Message-ID: <mailman.1737.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:48:00 +0200 (Fri, 01 Aug 2008)
New Revision: 3450

Modified:
   trunk/coreboot-v2/src/stream/rom_stream.c
Log:
fix compile warnings of rom_stream.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/stream/rom_stream.c
===================================================================
--- trunk/coreboot-v2/src/stream/rom_stream.c	2008-08-01 11:40:16 UTC (rev 3449)
+++ trunk/coreboot-v2/src/stream/rom_stream.c	2008-08-01 11:48:00 UTC (rev 3450)
@@ -80,8 +80,8 @@
 #if _RAMBASE<0x00100000
 	olen = *(unsigned int *)dest;
 #if (CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)
-	if((dest < 0xa0000) && ((dest+olen)>0xa0000)) {
-		dest = (CONFIG_LB_MEM_TOPK<<10);
+	if((dest < (unsigned char *)0xa0000) && ((dest+olen)>(unsigned char *)0xa0000)) {
+		dest = (unsigned char *)(CONFIG_LB_MEM_TOPK<<10);
 	}
 #endif
         if((dest < (unsigned char *) 0xf0000) && ((dest+olen)> (unsigned char *)0xf0000)) { // coreboot tables etc




From svn at coreboot.org  Fri Aug  1 13:50:52 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:50:52 +0200
Subject: [coreboot] r3451 - trunk/coreboot-v2/src/southbridge/ricoh/rl5c476
Message-ID: <mailman.1738.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:50:52 +0200 (Fri, 01 Aug 2008)
New Revision: 3451

Modified:
   trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
Log:
coding style fixes (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c	2008-08-01 11:48:00 UTC (rev 3450)
+++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c	2008-08-01 11:50:52 UTC (rev 3451)
@@ -1,7 +1,6 @@
 /*
  * (C) Copyright 2004 Nick Barker <nick.barker9 at btinternet.com>
  *
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ -20,7 +19,6 @@
 /* (C) Copyright 2005 Nick Barker <nick.barker at btinternet.com
    brought into line with the current architecture of coreboot */ 
 
-
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -34,10 +32,10 @@
 static int enable_cf_boot = 0;
 static unsigned int cf_base;
 
-static void udelay(int i){
+static void udelay(int i)
+{
 	for(; i > 0 ; i--)
 		inb(0x80);
-
 }
 
 static void rl5c476_init(device_t dev)
@@ -105,8 +103,6 @@
 		pc16->ioffl1 = 0x0;
 		pc16->ioffh1 = 0;
 
-
-
 		// set up CF config window
 		pc16->smpga0 = cf_base>>24;
 		pc16->smsth0 = (cf_base>>20)&0x0f;
@@ -164,15 +160,12 @@
 		resource->size = 0x1000;
 		resource->align = resource->gran = 12;
 		resource->limit= 0xffff0000;
-		//compute_allocate_resource(&dev->link[0],resource,resource->flags,resource->flags);
 	}
 	cardbus_read_resources(dev);
-
 }
 
 void rl5c476_set_resources(device_t dev)
 {
-
 	struct resource *resource;
 	printk_debug("%s In set resources \n",dev_path(dev));
 	if( enable_cf_boot && (PCI_FUNC(dev->path.u.pci.devfn) == 1)){




From svn at coreboot.org  Fri Aug  1 13:53:39 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:53:39 +0200
Subject: [coreboot] r3452 - in trunk/coreboot-v2/src/cpu/intel:
	hyperthreading thermal_monitoring
Message-ID: <mailman.1739.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:53:39 +0200 (Fri, 01 Aug 2008)
New Revision: 3452

Removed:
   trunk/coreboot-v2/src/cpu/intel/thermal_monitoring/Config.lb
Modified:
   trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c
Log:
drop unused code (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c	2008-08-01 11:50:52 UTC (rev 3451)
+++ trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c	2008-08-01 11:53:39 UTC (rev 3452)
@@ -48,7 +48,6 @@
 	for(i = 1; i < siblings; i++) {
 		struct device_path cpu_path;
 		device_t new;
-		unsigned long count;
 		/* Build the cpu device path */
 		cpu_path.type = DEVICE_PATH_APIC;
 		cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i;

Deleted: trunk/coreboot-v2/src/cpu/intel/thermal_monitoring/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/thermal_monitoring/Config.lb	2008-08-01 11:50:52 UTC (rev 3451)
+++ trunk/coreboot-v2/src/cpu/intel/thermal_monitoring/Config.lb	2008-08-01 11:53:39 UTC (rev 3452)
@@ -1,3 +0,0 @@
-#define THERMAL_MONITORING_OFF 0
-#define THERMAL_MONITORING_SET 0x00000008
-#define MISC_ENABLE 0x01a0




From svn at coreboot.org  Fri Aug  1 13:54:55 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 13:54:55 +0200
Subject: [coreboot] r3453 - trunk/coreboot-v2/src/cpu/x86/mtrr
Message-ID: <mailman.1740.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 13:54:55 +0200 (Fri, 01 Aug 2008)
New Revision: 3453

Modified:
   trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c
Log:
same spelling in all mtrr output.. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c	2008-08-01 11:53:39 UTC (rev 3452)
+++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c	2008-08-01 11:54:55 UTC (rev 3453)
@@ -352,7 +352,7 @@
 
         printk_debug("\n");
         /* Initialized the fixed_mtrrs to uncached */
-        printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
+        printk_debug("Setting fixed MTRRs(%d-%d) Type: UC\n",
 	        0, NUM_FIXED_RANGES);
         set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
 




From svn at coreboot.org  Fri Aug  1 14:06:09 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 14:06:09 +0200
Subject: [coreboot] r3454 - trunk/coreboot-v2/src/pc80
Message-ID: <mailman.1741.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 14:06:08 +0200 (Fri, 01 Aug 2008)
New Revision: 3454

Removed:
   trunk/coreboot-v2/src/pc80/serial.inc
Log:
serial.inc is not used anywhere. drop it (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Deleted: trunk/coreboot-v2/src/pc80/serial.inc
===================================================================
--- trunk/coreboot-v2/src/pc80/serial.inc	2008-08-01 11:54:55 UTC (rev 3453)
+++ trunk/coreboot-v2/src/pc80/serial.inc	2008-08-01 12:06:08 UTC (rev 3454)
@@ -1,107 +0,0 @@
-#include <part/fallback_boot.h>
-
-
-/* Base Address */
-#ifndef TTYS0_BASE
-#define TTYS0_BASE	0x3f8
-#endif
-
-/* Baud Rate */
-#ifndef TTYS0_BAUD
-#define TTYS0_BAUD 115200
-#endif
-
-#if ((115200%TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-
-/* Baud Rate Divisor */
-#define TTYS0_DIV	(115200/TTYS0_BAUD)
-#define TTYS0_DIV_LO	(TTYS0_DIV&0xFF)
-#define TTYS0_DIV_HI	((TTYS0_DIV >> 8)&0xFF)
-
-/* Line Control Settings */
-#ifndef TTYS0_LCS
-/* Set 8bit, 1 stop bit, no parity */
-#define TTYS0_LCS	0x3
-#endif
-
-/* Data */
-#define TTYS0_RBR (TTYS0_BASE+0x00)
-
-/* Control */
-#define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (TTYS0_BASE+0x01)
-#define TTYS0_IIR (TTYS0_BASE+0x02)
-#define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (TTYS0_BASE+0x03)
-#define TTYS0_MCR (TTYS0_BASE+0x04)
-#define TTYS0_DLL TTYS0_RBR
-#define TTYS0_DLM TTYS0_IER
-
-/* Status */
-#define TTYS0_LSR (TTYS0_BASE+0x05)
-#define TTYS0_MSR (TTYS0_BASE+0x06)
-#define TTYS0_SCR (TTYS0_BASE+0x07)
-
-#if USE_OPTION_TABLE == 1
-.section ".rom.data"
-	.type	 div, at object
-	.size	 div,8
-div:
-.byte 1,2,3,6,12,24,48,96
-
-.previous
-#endif
-
-	jmp	serial0
-
-	/* uses:	ax, dx */
-#define TTYS0_TX_AL		\
-	mov	%al, %ah	; \
-9:	mov	$TTYS0_LSR, %dx	; \
-	inb	%dx, %al	; \
-	test	$0x20, %al	; \
-	je	9b		; \
-	mov	$TTYS0_TBR, %dx	; \
-	mov	%ah, %al	; \
-	outb	%al, %dx
-
-serial_init:
-	/* Set 115.2Kbps,8n1 */
-	/* Set 8bit, 1 stop bit, no parity, DLAB */
-	mov	$TTYS0_LCR, %dx
-	mov	$(TTYS0_LCS | 0x80), %al
-	out	%al, %dx
-
-	/* set Baud Rate Divisor to 1 ==> 115200 Buad */
-#if USE_OPTION_TABLE == 1
-
-	movb	$(RTC_BOOT_BYTE+1), %al
-	outb	%al, $0x70
-	xorl	%edx,%edx
-	inb	$0x71, %al
-	andb	$7,%al
-	movb	%al,%dl
-	movb	div(%edx),%al
-	mov	$TTYS0_DLL, %dx
-	out	%al, %dx
-	mov	$TTYS0_DLM, %dx
-	xorb	%al,%al
-	out	%al, %dx
-#else
-	mov	$TTYS0_DLL, %dx
-	mov	$TTYS0_DIV_LO, %al
-	out	%al, %dx
-	mov	$TTYS0_DLM, %dx
-	mov	$TTYS0_DIV_HI, %al
-	out	%al, %dx
-#endif
-	/* Disable DLAB */
-	mov	$TTYS0_LCR, %dx
-	mov	$(TTYS0_LCS & 0x7f), %al
-	out	%al, %dx
-	RETSP
-
-serial0:
-	CALLSP(serial_init)




From svn at coreboot.org  Fri Aug  1 14:11:00 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 14:11:00 +0200
Subject: [coreboot] r3455 - in trunk/coreboot-v2/src/cpu/intel: model_69x
	model_6dx model_6xx
Message-ID: <mailman.1742.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 14:11:00 +0200 (Fri, 01 Aug 2008)
New Revision: 3455

Modified:
   trunk/coreboot-v2/src/cpu/intel/model_69x/model_69x_init.c
   trunk/coreboot-v2/src/cpu/intel/model_6dx/model_6dx_init.c
   trunk/coreboot-v2/src/cpu/intel/model_6xx/model_6xx_init.c
Log:
match against all steppings of a CPU model, because these are _model_ drivers.
(trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/cpu/intel/model_69x/model_69x_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_69x/model_69x_init.c	2008-08-01 12:06:08 UTC (rev 3454)
+++ trunk/coreboot-v2/src/cpu/intel/model_69x/model_69x_init.c	2008-08-01 12:11:00 UTC (rev 3455)
@@ -38,7 +38,8 @@
 	.init     = model_69x_init,
 };
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, 0x0695 }, /* Pentium M */
+	{ X86_VENDOR_INTEL, 0x0690 }, /* Pentium M */
+	{ X86_VENDOR_INTEL, 0x0695 },
 	{ 0, 0 },
 };
 

Modified: trunk/coreboot-v2/src/cpu/intel/model_6dx/model_6dx_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6dx/model_6dx_init.c	2008-08-01 12:06:08 UTC (rev 3454)
+++ trunk/coreboot-v2/src/cpu/intel/model_6dx/model_6dx_init.c	2008-08-01 12:11:00 UTC (rev 3455)
@@ -38,6 +38,7 @@
 	.init     = model_6dx_init,
 };
 static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x06D0 }, /* Pentium M on 90nm with 2MiB of L2 cache */
 	{ X86_VENDOR_INTEL, 0x06D6 }, /* Pentium M on 90nm with 2MiB of L2 cache */
 	{ 0, 0 },
 };

Modified: trunk/coreboot-v2/src/cpu/intel/model_6xx/model_6xx_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6xx/model_6xx_init.c	2008-08-01 12:06:08 UTC (rev 3454)
+++ trunk/coreboot-v2/src/cpu/intel/model_6xx/model_6xx_init.c	2008-08-01 12:11:00 UTC (rev 3455)
@@ -44,17 +44,21 @@
 	.init     = model_6xx_init,
 };
 static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0650 },
 	{ X86_VENDOR_INTEL, 0x0652 },
-	{ X86_VENDOR_INTEL, 0x0665 }, /* Celeron (Mendocino) */
+	{ X86_VENDOR_INTEL, 0x0660 }, /* Celeron (Mendocino) */
+	{ X86_VENDOR_INTEL, 0x0665 },
 	{ X86_VENDOR_INTEL, 0x0672 },
 	{ X86_VENDOR_INTEL, 0x0673 },
+	{ X86_VENDOR_INTEL, 0x0680 },
 	{ X86_VENDOR_INTEL, 0x0681 },
 	{ X86_VENDOR_INTEL, 0x0683 },
 	{ X86_VENDOR_INTEL, 0x0686 },
 	{ X86_VENDOR_INTEL, 0x06A0 },
 	{ X86_VENDOR_INTEL, 0x06A1 },
 	{ X86_VENDOR_INTEL, 0x06A4 },
-	{ X86_VENDOR_INTEL, 0x06B4 }, /* Mobile Celeron FCBGA */
+	{ X86_VENDOR_INTEL, 0x06B0 }, /* Mobile Celeron FCBGA */
+	{ X86_VENDOR_INTEL, 0x06B4 },
 	{ 0, 0 },
 };
 




From svn at coreboot.org  Fri Aug  1 14:12:37 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 14:12:37 +0200
Subject: [coreboot] r3456 - trunk/coreboot-v2/src/ram
Message-ID: <mailman.1743.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 14:12:37 +0200 (Fri, 01 Aug 2008)
New Revision: 3456

Modified:
   trunk/coreboot-v2/src/ram/ramtest.c
Log:
use printk, when possible. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/ram/ramtest.c
===================================================================
--- trunk/coreboot-v2/src/ram/ramtest.c	2008-08-01 12:11:00 UTC (rev 3455)
+++ trunk/coreboot-v2/src/ram/ramtest.c	2008-08-01 12:12:37 UTC (rev 3456)
@@ -29,22 +29,34 @@
 	/* 
 	 * Fill.
 	 */
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("DRAM fill: 0x%08x-0x%08x\r\n", start, stop);
+#else
 	print_debug("DRAM fill: ");
 	print_debug_hex32(start);
 	print_debug("-");
 	print_debug_hex32(stop);
 	print_debug("\r\n");
+#endif
 	for(addr = start; addr < stop ; addr += 4) {
 		/* Display address being filled */
-		if (!(addr & 0xffff)) {
+		if (!(addr & 0xfffff)) {
+#if CONFIG_USE_PRINTK_IN_CAR
+			printk_debug("%08x \r", addr);
+#else
 			print_debug_hex32(addr);
 			print_debug(" \r");
+#endif
 		}
 		write_phys(addr, addr);
 	};
 	/* Display final address */
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("%08x\r\nDRAM filled\r\n", addr);
+#else
 	print_debug_hex32(addr);
 	print_debug("\r\nDRAM filled\r\n");
+#endif
 }
 
 static void ram_verify(unsigned long start, unsigned long stop)
@@ -54,40 +66,70 @@
 	/* 
 	 * Verify.
 	 */
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("DRAM verify: 0x%08x-0x%08x\r\n", start, stop);
+#else
 	print_debug("DRAM verify: ");
 	print_debug_hex32(start);
 	print_debug_char('-');
 	print_debug_hex32(stop);
 	print_debug("\r\n");
+#endif
 	for(addr = start; addr < stop ; addr += 4) {
 		unsigned long value;
 		/* Display address being tested */
-		if (!(addr & 0xffff)) {
+		if (!(addr & 0xfffff)) {
+#if CONFIG_USE_PRINTK_IN_CAR
+			printk_debug("%08x \r", addr);
+#else
 			print_debug_hex32(addr);
 			print_debug(" \r");
+#endif
 		}
 		value = read_phys(addr);
 		if (value != addr) {
 			/* Display address with error */
+#if CONFIG_USE_PRINTK_IN_CAR
+			printk_err("Fail: @0x%08x Read value=0x%08x\r\n", addr, value);
+#else
 			print_err("Fail: @0x");
 			print_err_hex32(addr);
 			print_err(" Read value=0x");
 			print_err_hex32(value);
 			print_err("\r\n");
+#endif
 			i++;
 			if(i>256) {
+#if CONFIG_USE_PRINTK_IN_CAR
+				printk_debug("Aborting.\n\r");
+#else
 				print_debug("Aborting.\n\r");
+#endif
 				break;
 			}
 		}
 	}
 	/* Display final address */
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("%08x", addr);
+#else
 	print_debug_hex32(addr);
+#endif
+
 	if (i) {
+#if CONFIG_USE_PRINTK_IN_CAR
+		printk_debug("\r\nDRAM did _NOT_ verify!\r\n");
+#else
 		print_debug("\r\nDRAM did _NOT_ verify!\r\n");
+#endif
+		die("DRAM ERROR");
 	}
 	else {
+#if CONFIG_USE_PRINTK_IN_CAR
+		printk_debug("\r\nDRAM range verified.\r\n");
+#else
 		print_debug("\r\nDRAM range verified.\r\n");
+#endif
 	}
 }
 
@@ -99,13 +141,21 @@
 	 * test than a "Is my DRAM faulty?" test.  Not all bits
 	 * are tested.   -Tyson
 	 */
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("Testing DRAM : %08x - %08x\r\n", start, stop);
+#else
 	print_debug("Testing DRAM : ");
 	print_debug_hex32(start);
 	print_debug("-");	
 	print_debug_hex32(stop);
 	print_debug("\r\n");
+#endif
 	ram_fill(start, stop);
 	ram_verify(start, stop);
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("Done.\r\n");
+#else
 	print_debug("Done.\r\n");
+#endif
 }
 




From svn at coreboot.org  Fri Aug  1 14:20:26 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 14:20:26 +0200
Subject: [coreboot] r3457 - trunk/coreboot-v2/src/config
Message-ID: <mailman.1744.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 14:20:26 +0200 (Fri, 01 Aug 2008)
New Revision: 3457

Modified:
   trunk/coreboot-v2/src/config/Config.lb
Log:
clean out obsoleted config.lb rules and output, fix indenting (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/config/Config.lb
===================================================================
--- trunk/coreboot-v2/src/config/Config.lb	2008-08-01 12:12:37 UTC (rev 3456)
+++ trunk/coreboot-v2/src/config/Config.lb	2008-08-01 12:20:26 UTC (rev 3457)
@@ -84,7 +84,7 @@
 
 	makerule coreboot_apc.o
 		depends "coreboot_apc.a c_start.o $(LIBGCC_FILE_NAME)"
-        action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
+        	action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
 	end
 
 	makerule coreboot_apc
@@ -126,11 +126,6 @@
 	action	"$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
 end
 
-#makerule crt0.S   
-#	depends	"$(CRT0)" 
-#	action		"cp $< $@"
-#end
-
 # the buildrom tool
 makerule buildrom 
 	depends	"$(TOP)/util/buildrom/buildrom.c" 
@@ -141,13 +136,11 @@
 makedefine .PHONY : crt0.s
 makerule crt0.s   
 	depends	"crt0.S $(CRT0_INCLUDES)" 
-	action	"@echo \"$(CPP) ... $< > $@ \""
 	action	"$(CPP) $(CPPFLAGS) -I. -I$(TOP)/src  $< > $@.new && mv $@.new $@"
 end
 
 makerule crt0.o  
 	depends	"crt0.s" 
-	action	"@echo $(CC) ... -o $@ $<"
 	action	"@$(CC) -c $(CPU_OPT) -o $@ $<"
 end
 
@@ -179,11 +172,6 @@
 	action	"$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" 
 end
 
-#makerule /$(TARGET_DIR)/option_table.c
-#	depends	"build_opt_tbl $(MAINBOARD)/cmos.layout" 
-#	action	"./build_opt_tbl -b  --config $(MAINBOARD)/cmos.layout"
-#end
-
 makerule option_table.c
 	depends	"build_opt_tbl $(MAINBOARD)/cmos.layout" 
 	action	"./build_opt_tbl -b  --config $(MAINBOARD)/cmos.layout --header option_table.h"
@@ -196,12 +184,6 @@
 
 if HAVE_OPTION_TABLE
 object ./option_table.o 
-#special rule
-#makerule option_table.o 
-#	depends	"option_table.c" 
-#	action	"$(CC) -c $(CFLAGS) -o $@ $<"
-#end
-# object option_table.o 
 end
 
 makerule clean  




From svn at coreboot.org  Fri Aug  1 14:28:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 14:28:40 +0200
Subject: [coreboot] r3458 - trunk/coreboot-v2/src/devices
Message-ID: <mailman.1745.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 14:28:38 +0200 (Fri, 01 Aug 2008)
New Revision: 3458

Modified:
   trunk/coreboot-v2/src/devices/device.c
Log:
clarify in the printks what function is actually called. This little smart magic
drove me crazy during debugging. Fix Typos. Add a warning because the
on-chipset devices are hardcoded. For newer machines, a lot more memory space
will have special meanings, and we can't hardcode them all in an ifdef desert.

(trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/devices/device.c
===================================================================
--- trunk/coreboot-v2/src/devices/device.c	2008-08-01 12:20:26 UTC (rev 3457)
+++ trunk/coreboot-v2/src/devices/device.c	2008-08-01 12:28:38 UTC (rev 3458)
@@ -272,7 +272,7 @@
 	min_align = 0;
 	base = bridge->base;
 
-	printk_spew("%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d\n", 
+	printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d\n", 
 		dev_path(bus->dev),
 		(bridge->flags & IORESOURCE_IO)? "io":
 		(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
@@ -312,7 +312,7 @@
 			align = min_align;
 		}
 
-		/* Propogate the resource alignment to the bridge register  */
+		/* Propagate the resource alignment to the bridge register  */
 		if (align > bridge->align) {
 			bridge->align = align;
 		}
@@ -325,10 +325,12 @@
 		if (bridge->limit > resource->limit) {
 			bridge->limit = resource->limit;
 		}
+#warning This heuristics should be replaced by real devices with fixed resources.
 		/* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */
 		if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) {
 			bridge->limit = DEVICE_MEM_HIGH;
 		}
+
 		if (resource->flags & IORESOURCE_IO) {
 			/* Don't allow potential aliases over the
 			 * legacy pci expansion card addresses.
@@ -373,7 +375,7 @@
 	 */
 	bridge->size = round(base, bridge->gran) - bridge->base;
 
-	printk_spew("%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d done\n", 
+	printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d done\n", 
 		dev_path(bus->dev),
 		(bridge->flags & IORESOURCE_IO)? "io":
 		(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
@@ -633,7 +635,7 @@
  * relocated to their final position and stored to the hardware.
  *
  * I/O resources start at DEVICE_IO_START and grow upward. MEM resources start
- * at DEVICE_MEM_START and grow downward.
+ * at DEVICE_MEM_HIGH and grow downward.
  *
  * Since the assignment is hierarchical we set the values into the dev_root
  * struct. 




From peter at stuge.se  Fri Aug  1 14:41:37 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Aug 2008 14:41:37 +0200
Subject: [coreboot] r3458 - trunk/coreboot-v2/src/devices
Message-ID: <20080801124137.15955.qmail@stuge.se>

On Fri, Aug 01, 2008 at 02:28:40PM +0200, svn at coreboot.org wrote:
> Author: stepan
> New Revision: 3458

Sweet cleanups!


//Peter



From svn at coreboot.org  Fri Aug  1 14:53:05 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 14:53:05 +0200
Subject: [coreboot] r3459 - trunk/coreboot-v2/src/devices
Message-ID: <mailman.1746.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 14:53:04 +0200 (Fri, 01 Aug 2008)
New Revision: 3459

Modified:
   trunk/coreboot-v2/src/devices/pciexp_device.c
Log:
Typo, thanks to Idwer for spotting this. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/devices/pciexp_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/pciexp_device.c	2008-08-01 12:28:38 UTC (rev 3458)
+++ trunk/coreboot-v2/src/devices/pciexp_device.c	2008-08-01 12:53:04 UTC (rev 3459)
@@ -34,7 +34,7 @@
 		/* error... */
 		return;
 	}
-	printk_debug("PCIe: tunning %s\n", dev_path(dev));
+	printk_debug("PCIe: tuning %s\n", dev_path(dev));
 #warning "IMPLEMENT PCI EXPRESS TUNING"
 }
 




From svn at coreboot.org  Fri Aug  1 15:08:33 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 15:08:33 +0200
Subject: [coreboot] r3460 - trunk/coreboot-v2/src/devices
Message-ID: <mailman.1747.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 15:08:33 +0200 (Fri, 01 Aug 2008)
New Revision: 3460

Modified:
   trunk/coreboot-v2/src/devices/device.c
Log:
a heuristics is something different 

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/devices/device.c
===================================================================
--- trunk/coreboot-v2/src/devices/device.c	2008-08-01 12:53:04 UTC (rev 3459)
+++ trunk/coreboot-v2/src/devices/device.c	2008-08-01 13:08:33 UTC (rev 3460)
@@ -325,7 +325,7 @@
 		if (bridge->limit > resource->limit) {
 			bridge->limit = resource->limit;
 		}
-#warning This heuristics should be replaced by real devices with fixed resources.
+#warning This heuristic should be replaced by real devices with fixed resources.
 		/* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */
 		if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) {
 			bridge->limit = DEVICE_MEM_HIGH;




From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  1 16:47:00 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 Aug 2008 16:47:00 +0200
Subject: [coreboot] [PATCH] v3 mainboard Kconfig cleanup
In-Reply-To: <48775AED.50909@gmx.net>
References: <487562BA.2060501@gmx.net> <48775AED.50909@gmx.net>
Message-ID: <489321E4.6020004@gmx.net>

Would someone please review this? Thanks.

Regards,
Carl-Daniel

On 11.07.2008 15:06, Carl-Daniel Hailfinger wrote:
> On 10.07.2008 03:15, Carl-Daniel Hailfinger wrote:
>   
>> Hi!
>>
>> Right now, our Kconfig files in the mainboard/ directory in the v3 tree
>> are not exactly in the best shape.
>> - MAINBOARD_NAME is claimed to be the mainboard name, but it is used
>> exclusively as mainboard directory.
>> - MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to
>> $VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes
>> $VENDOR/$BOARD as board path.
>> - MAINBOARD_NAME has a help text which will never be displayed to the user.
>>   
>>     
>
> Final patch. The diffstat is encouraging: A total of 200 lines have been
> removed completely.
>
> Per-board Kconfig files have been deleted, the remnants making sense
> have been merged into per-vendor Kconfig files and the never-shown help
> texts have been removed.
>
> If there are ever some real per-board options and not just tricks to
> make the makefiles behave, we can resurrect the per-board Kconfig files.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/adl/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/adl/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/adl/Kconfig	(working copy)
> @@ -36,5 +36,8 @@
>  
>  endchoice
>  
> -source "mainboard/adl/msm800sev/Kconfig"
> +config MAINBOARD_DIR
> +	string
> +	default adl/msm800sev
> +	depends BOARD_ADL_MSM800SEV
>  
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/adl/msm800sev/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/adl/msm800sev/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/adl/msm800sev/Kconfig	(working copy)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default adl/msm800sev
> -	depends BOARD_ADL_MSM800SEV
> -	help
> -	  This is the name for the Advanced Digital Logic MSM800SEV mainboard.
> -
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/Kconfig	(working copy)
> @@ -48,6 +48,13 @@
>  
>  endchoice
>  
> -source "mainboard/amd/db800/Kconfig"
> -source "mainboard/amd/norwich/Kconfig"
> +config MAINBOARD_DIR
> +	string
> +	default amd/db800
> +	depends BOARD_AMD_DB800
>  
> +config MAINBOARD_DIR
> +	string
> +	default amd/norwich
> +	depends BOARD_AMD_NORWICH
> +
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/norwich/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/norwich/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/norwich/Kconfig	(working copy)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default amd/norwich
> -	depends BOARD_AMD_NORWICH
> -	help
> -	  This is the default mainboard name.
> -
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/db800/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/db800/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/amd/db800/Kconfig	(working copy)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default amd/db800
> -	depends BOARD_AMD_DB800
> -	help
> -	  This is the default mainboard name.
> -
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/Kconfig	(working copy)
> @@ -47,5 +47,12 @@
>  
>  endchoice
>  
> -source "mainboard/artecgroup/dbe61/Kconfig"
> -source "mainboard/artecgroup/dbe62/Kconfig"
> +config MAINBOARD_DIR
> +	string
> +	default artecgroup/dbe61
> +	depends BOARD_ARTECGROUP_DBE61
> +
> +config MAINBOARD_DIR
> +	string
> +	default artecgroup/dbe62
> +	depends BOARD_ARTECGROUP_DBE62
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/dbe61/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/dbe61/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/dbe61/Kconfig	(working copy)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default artecgroup/dbe61
> -	depends BOARD_ARTECGROUP_DBE61
> -	help
> -	  This is the default mainboard name.
> -
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/dbe62/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/dbe62/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/artecgroup/dbe62/Kconfig	(working copy)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default artecgroup/dbe62
> -	depends BOARD_ARTECGROUP_DBE62
> -	help
> -	  This is the default mainboard name.
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/Kconfig	(working copy)
> @@ -48,6 +48,12 @@
>  
>  endchoice
>  
> -source "mainboard/pcengines/alix1c/Kconfig"
> -source "mainboard/pcengines/alix2c3/Kconfig"
> +config MAINBOARD_DIR
> +	string
> +	default pcengines/alix1c
> +	depends BOARD_PCENGINES_ALIX1C
>  
> +config MAINBOARD_DIR
> +	string
> +	default pcengines/alix2c3
> +	depends BOARD_PCENGINES_ALIX2C3
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix1c/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix1c/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix1c/Kconfig	(working copy)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default pcengines/alix1c
> -	depends BOARD_PCENGINES_ALIX1C
> -	help
> -	  This is the default mainboard name.
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix1c/defconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix1c/defconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix1c/defconfig	(working copy)
> @@ -20,7 +20,7 @@
>  # CONFIG_VENDOR_ARTECGROUP is not set
>  # CONFIG_VENDOR_EMULATION is not set
>  CONFIG_VENDOR_PCENGINES=y
> -CONFIG_MAINBOARD_NAME="pcengines/alix1c"
> +CONFIG_MAINBOARD_DIR="pcengines/alix1c"
>  CONFIG_BOARD_PCENGINES_ALIX1C=y
>  # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
>  # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix2c3/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix2c3/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix2c3/Kconfig	(working copy)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default pcengines/alix2c3
> -	depends BOARD_PCENGINES_ALIX2C3
> -	help
> -	  This is the default mainboard name.
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix2c3/defconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix2c3/defconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/pcengines/alix2c3/defconfig	(working copy)
> @@ -19,7 +19,7 @@
>  # CONFIG_VENDOR_ARTECGROUP is not set
>  # CONFIG_VENDOR_EMULATION is not set
>  CONFIG_VENDOR_PCENGINES=y
> -CONFIG_MAINBOARD_NAME="pcengines/alix2c3"
> +CONFIG_MAINBOARD_DIR="pcengines/alix2c3"
>  # CONFIG_BOARD_PCENGINES_ALIX1C is not set
>  CONFIG_BOARD_PCENGINES_ALIX2C3=y
>  # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/Kconfig	(working copy)
> @@ -37,5 +37,8 @@
>  
>  endchoice
>  
> -source "mainboard/emulation/qemu-x86/Kconfig"
> +config MAINBOARD_DIR
> +	string
> +	default emulation/qemu-x86
> +	depends BOARD_EMULATION_QEMU_X86
>  
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/qemu-x86/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/qemu-x86/Kconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/qemu-x86/Kconfig	(working copy)
> @@ -1,29 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -## Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default emulation/qemu-x86
> -	depends BOARD_EMULATION_QEMU_X86
> -	help
> -	  This is the default mainboard name.
> -
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/qemu-x86/defconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/qemu-x86/defconfig	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/emulation/qemu-x86/defconfig	(working copy)
> @@ -19,7 +19,7 @@
>  # CONFIG_VENDOR_ARTECGROUP is not set
>  CONFIG_VENDOR_EMULATION=y
>  # CONFIG_VENDOR_PCENGINES is not set
> -CONFIG_MAINBOARD_NAME="emulation/qemu-x86"
> +CONFIG_MAINBOARD_DIR="emulation/qemu-x86"
>  CONFIG_BOARD_EMULATION_QEMU_X86=y
>  # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
>  CONFIG_COREBOOT_ROMSIZE_KB_256=y
> Index: corebootv3-mainboard_Kconfig_cleanup/Makefile
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/Makefile	(revision 694)
> +++ corebootv3-mainboard_Kconfig_cleanup/Makefile	(working copy)
> @@ -81,7 +81,7 @@
>  	$(Q)printf "  DONE\n"
>  
>  ARCH:=$(shell echo $(CONFIG_ARCH))
> -MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_NAME))
> +MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_DIR))
>  export MAINBOARDDIR
>  
>  COREBOOTINCLUDE    :=   -I$(src) -Iinclude \
>
>
>
>   


-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Fri Aug  1 17:40:40 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 08:40:40 -0700
Subject: [coreboot] [PATCH] v3 mainboard Kconfig cleanup
In-Reply-To: <489321E4.6020004@gmx.net>
References: <487562BA.2060501@gmx.net> <48775AED.50909@gmx.net>
	<489321E4.6020004@gmx.net>
Message-ID: <13426df10808010840x35f64446taf3335d4ab08be36@mail.gmail.com>

looks fine.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From rminnich at gmail.com  Fri Aug  1 18:07:26 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 09:07:26 -0700
Subject: [coreboot] patch: k8 support in v3.
Message-ID: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>

I want to move fast on this. I have a few hours today and I want to
put them to getting code in. Let's make sure we get this in.

IF there are copyright issues, note it for the log and commit a patch
later. If there are formatting issues, ditto.

This almost builds. dts is not built, any idea why?  I could use help.
Anybody want to do the superio? Should be quick.

Let's get going. I will try to do at least one file per day until
we're there. But today, I ought to be able to get pretty far pretty
fast. Your support will help this happen.

ron
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From peter at stuge.se  Fri Aug  1 18:40:01 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Aug 2008 18:40:01 +0200
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
Message-ID: <20080801164001.26470.qmail@stuge.se>

On Fri, Aug 01, 2008 at 09:07:26AM -0700, ron minnich wrote:
> This almost builds. dts is not built, any idea why?  I could use
> help.

Looking at it.


> Anybody want to do the superio? Should be quick.

What's needed here specifically?


> Your support will help this happen.

What about amdk8 vs amdfam10 ? Can we already do something clever?
(Yes, yes, let's get it working first. :p)


//Peter



From peter at stuge.se  Fri Aug  1 18:42:28 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Aug 2008 18:42:28 +0200
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
Message-ID: <20080801164228.27265.qmail@stuge.se>

On Fri, Aug 01, 2008 at 09:07:26AM -0700, ron minnich wrote:
> This almost builds. dts is not built, any idea why?  I could use
> help.

Patch missing mainboard/gigabyte/Kconfig


//Peter



From Marc.Jones at amd.com  Fri Aug  1 18:50:28 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Fri, 1 Aug 2008 10:50:28 -0600
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
Message-ID: <48933ED4.8060001@amd.com>

ron minnich wrote:
...

> OK, this is it, beginnings of K8 support 
> 
> and some geode cleanup. 
> 
> 1. fix some includes on geode. 
> Index: arch/x86/geodelx/stage1.c
> Index: southbridge/amd/cs5536/stage1.c
> 2. add amd_k8.h include. 
> 
Seperate out the geode stuff. I think you can selfack it. They are 
trivial IMO. Here's an ack for the geode stuff anyway.

Acked-by: Marc Jones <marc.jones at amd.com>




> Index: arch/x86/Makefile
> Add K8 clauses
> Index: arch/x86/mtrr.h
> Index: include/arch/x86/amd_k8.h
> mv this to include, it is needed in several places now. 
> 
> K8 files: 
> Index: arch/x86/amdk8/stage1.c
> Index: arch/x86/amd/stage0.S
> Index: arch/x86/Kconfig
> Index: mainboard/gigabyte/m57sli/Makefile
> Index: mainboard/gigabyte/m57sli/dts
> Index: mainboard/gigabyte/m57sli/stage1.c
> Index: mainboard/gigabyte/m57sli/initram.c
> Index: mainboard/gigabyte/m57sli/Kconfig
> Index: mainboard/Kconfig
> 
> 
> The m57sli almost builds. It's pretty empty. The dtc is not run .
> 
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
> 

...

> -#endif				/* ARCH_X86_MTRR_H */
> Index: arch/x86/Makefile
> ===================================================================
> --- arch/x86/Makefile	(revision 699)
> +++ arch/x86/Makefile	(working copy)
> @@ -124,9 +124,12 @@
>  	STAGE0_ARCH_X86_OBJ += geodelx/stage1.o
>  	STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o
>  else
> -	STAGE0_CAR_OBJ = stage0_i586.o
> +ifeq ($(CONFIG_CPU_AMD_K8),y)
> +	STAGE0_CAR_OBJ = amd/stage0.o
> +	STAGE0_ARCH_X86_OBJ += amdk8/stage1.o
>  endif
>  endif
> +endif

Add else and put the stage0_i586 on the end?

I agree with getting the pieces in place as we go.
The files looked fine to me but I didn't try to build it.....

Acked-by: Marc Jones <marc.jones at amd.com>




-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors




From peter at stuge.se  Fri Aug  1 18:55:37 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Aug 2008 18:55:37 +0200
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <48933ED4.8060001@amd.com>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
	<48933ED4.8060001@amd.com>
Message-ID: <20080801165537.31853.qmail@stuge.se>

On Fri, Aug 01, 2008 at 10:50:28AM -0600, Marc Jones wrote:
> >OK, this is it, beginnings of K8 support 
> >
> >and some geode cleanup. 
> >
> >1. fix some includes on geode. 
> >Index: arch/x86/geodelx/stage1.c
> >Index: southbridge/amd/cs5536/stage1.c
> >2. add amd_k8.h include. 
> >
> Seperate out the geode stuff. I think you can selfack it. They are 
> trivial IMO.

I second this. Please commit this separately right away Ron.


> Here's an ack for the geode stuff anyway.
> 
> Acked-by: Marc Jones <marc.jones at amd.com>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Fri Aug  1 18:59:10 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 18:59:10 +0200
Subject: [coreboot] r701 - in coreboot-v3: arch/x86/geodelx
	southbridge/amd/cs5536
Message-ID: <mailman.1748.1355071348.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-01 18:59:09 +0200 (Fri, 01 Aug 2008)
New Revision: 701

Modified:
   coreboot-v3/arch/x86/geodelx/stage1.c
   coreboot-v3/southbridge/amd/cs5536/stage1.c
Log:
minor include stuff. 
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marc.jones at amd.com>

Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/arch/x86/geodelx/stage1.c
===================================================================
--- coreboot-v3/arch/x86/geodelx/stage1.c	2008-07-30 15:08:25 UTC (rev 700)
+++ coreboot-v3/arch/x86/geodelx/stage1.c	2008-08-01 16:59:09 UTC (rev 701)
@@ -20,9 +20,9 @@
 
 #include <types.h>
 #include <lib.h>
-#include <msr.h>
 #include <amd_geodelx.h>
 #include <console.h>
+#include <msr.h>
 
 static const struct msrinit msr_table[] = {
   /* Setup access to cache under 1MB. */

Modified: coreboot-v3/southbridge/amd/cs5536/stage1.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/stage1.c	2008-07-30 15:08:25 UTC (rev 700)
+++ coreboot-v3/southbridge/amd/cs5536/stage1.c	2008-08-01 16:59:09 UTC (rev 701)
@@ -18,6 +18,7 @@
  */
 
 #include <types.h>
+#include <console.h>
 #include <msr.h>
 #include <lib.h>
 #include <amd_geodelx.h>




From rminnich at gmail.com  Fri Aug  1 19:00:06 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 10:00:06 -0700
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <20080801165537.31853.qmail@stuge.se>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
	<48933ED4.8060001@amd.com> <20080801165537.31853.qmail@stuge.se>
Message-ID: <13426df10808011000g23376262i79dc7ec9abbb17bb@mail.gmail.com>

geode bits done rev 701


Committed revision 701.



From svn at coreboot.org  Fri Aug  1 19:03:22 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 19:03:22 +0200
Subject: [coreboot] r702 - in coreboot-v3: arch/x86 arch/x86/amd
	arch/x86/amdk8 include/arch/x86 mainboard mainboard/gigabyte
	mainboard/gigabyte/m57sli
Message-ID: <mailman.1749.1355071348.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-01 19:03:22 +0200 (Fri, 01 Aug 2008)
New Revision: 702

Added:
   coreboot-v3/arch/x86/amd/
   coreboot-v3/arch/x86/amd/stage0.S
   coreboot-v3/arch/x86/amdk8/
   coreboot-v3/arch/x86/amdk8/stage1.c
   coreboot-v3/arch/x86/intel/
   coreboot-v3/include/arch/x86/amd_k8.h
   coreboot-v3/include/arch/x86/mtrr.h
   coreboot-v3/mainboard/gigabyte/
   coreboot-v3/mainboard/gigabyte/Kconfig
   coreboot-v3/mainboard/gigabyte/m57sli/
   coreboot-v3/mainboard/gigabyte/m57sli/Kconfig
   coreboot-v3/mainboard/gigabyte/m57sli/Makefile
   coreboot-v3/mainboard/gigabyte/m57sli/dts
   coreboot-v3/mainboard/gigabyte/m57sli/initram.c
   coreboot-v3/mainboard/gigabyte/m57sli/stage1.c
Removed:
   coreboot-v3/arch/x86/mtrr.h
Modified:
   coreboot-v3/arch/x86/Kconfig
   coreboot-v3/arch/x86/Makefile
   coreboot-v3/mainboard/Kconfig
Log:
The m57sli almost builds. It's pretty empty. The dtc is not run .

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Marc Jones <marc.jones at amd.com>


Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig	2008-08-01 16:59:09 UTC (rev 701)
+++ coreboot-v3/arch/x86/Kconfig	2008-08-01 17:03:22 UTC (rev 702)
@@ -48,6 +48,14 @@
 	  arch/x86/Makefile for more hints on possible values.
 	  It is usually set in mainboard/*/Kconfig.
 
+config CPU_AMD_K8
+	boolean
+	help
+	  CPU type. At the moment this option selects the reset vector and
+	  Cache-as-RAM (CAR) implementation for a mainboard. See
+	  arch/x86/Makefile for more hints on possible values.
+	  It is usually set in mainboard/*/Kconfig.
+
 config OPTION_TABLE
 	boolean
 	help
@@ -74,6 +82,7 @@
 	hex
 	default 0x8f000 if CPU_I586
 	default 0x80000 if CPU_AMD_GEODELX
+	default 0xc8000 if CPU_AMD_K8
 	help
 	  This option sets the base address of the area used for CAR.
 
@@ -81,5 +90,6 @@
 	hex
 	default 0x1000 if CPU_I586
 	default 0x8000 if CPU_AMD_GEODELX
+	default 0x08000 if CPU_AMD_K8
 	help
 	  This option sets the size of the area used for CAR.

Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-08-01 16:59:09 UTC (rev 701)
+++ coreboot-v3/arch/x86/Makefile	2008-08-01 17:03:22 UTC (rev 702)
@@ -124,9 +124,12 @@
 	STAGE0_ARCH_X86_OBJ += geodelx/stage1.o
 	STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o
 else
-	STAGE0_CAR_OBJ = stage0_i586.o
+ifeq ($(CONFIG_CPU_AMD_K8),y)
+	STAGE0_CAR_OBJ = amd/stage0.o
+	STAGE0_ARCH_X86_OBJ += amdk8/stage1.o
 endif
 endif
+endif
 
 ifeq ($(CONFIG_PAYLOAD_NO_PREPARSE_ELF), y)
 	PARSEELF =
@@ -245,6 +248,15 @@
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
 
+$(obj)/arch/x86/amd/stage0.o: $(src)/arch/x86/amd/stage0.S
+	$(Q)mkdir -p $(dir $@)
+	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
+	$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
+		-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
+		-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
+	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
+	$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
+
 $(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@)) (XIP)\n"
 	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o

Added: coreboot-v3/arch/x86/amd/stage0.S
===================================================================
--- coreboot-v3/arch/x86/amd/stage0.S	                        (rev 0)
+++ coreboot-v3/arch/x86/amd/stage0.S	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,467 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#include "../macros.h"
+#define CacheSize DCACHE_RAM_SIZE
+#define CacheBase DCACHE_RAM_BASE
+#define MEM_TOPK 2048
+#define ASSEMBLY
+
+/* leave some space for global variable to pass to RAM stage */
+#define GlobalVarSize 32
+
+#ifdef CONFIG_CPU_AMD_K10
+#define CacheSizeAPStack 0x400 /* 1K */
+#endif
+
+#include <mtrr.h>
+#include <amd_k8.h>
+
+	.code16
+	.globl _stage0
+_stage0:
+	cli
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp;
+
+	/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
+	 * executing any further code. Even though paging is disabled we
+	 * could still get false address translations due to the TLB if we
+	 * didn't invalidate it.
+	 */
+	xorl	%eax, %eax
+	movl	%eax, %cr3	/* Invalidate TLB. */
+
+	/* Switch to protected mode. */
+
+	/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
+	 * using BFD version 2.15.94.0.2.2 20041220 this works fine without
+	 * all the ld hackery and so on. So leave it as is with this comment.
+	 */
+
+	data32	lgdt %cs:gdtptr
+
+	movl	%cr0, %eax
+	andl	$0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
+	orl	$0x60000001, %eax /* CD, NW, PE = 1 */
+	movl	%eax, %cr0
+
+	/* Restore BIST result. */
+	movl	%ebp, %eax
+
+	// port80_post(0x23)
+
+	/* Now we are in protected mode. Jump to a 32 bit code segment. */
+	data32	ljmp $ROM_CODE_SEG, $protected_stage0
+
+	/* I am leaving this weird jump in here in the event that future gas
+	 * bugs force it to be used.
+	 */
+	/* .byte 0x66 */
+	.code32
+	/* ljmp	$ROM_CODE_SEG, $protected_stage0 */
+
+	/* .code16 */
+	.align 4
+	.globl gdt16
+gdt16 = . - _stage0
+gdt16x:
+	.word	gdt16xend - gdt16x -1	/* Compute the table limit. */
+	.long	gdt16x
+	.word	0
+
+	/* selgdt 0x08, flat code segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x9b, 0xcf, 0x00
+
+	/* selgdt 0x10, flat data segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x93, 0xcf, 0x00
+gdt16xend:
+
+	/* From now on we are 32bit. */
+	.code32
+
+	/* We have two gdts where we could have one. That is ok.
+	 *
+	 * Let's not worry about this -- optimizing gdt is pointless since
+	 * we're only in it for a little bit.
+	 *
+	 * Btw. note the trick below: The GDT points to ITSELF, and the first
+	 * good descriptor is at offset 8. So you word-align the table, and
+	 * then because you chose 8, you get a nice 64-bit aligned GDT entry,
+	 * which is good as this is the size of the entry.
+	 *
+	 * Just in case you ever wonder why people do this.
+	 */
+	.align 4
+	.globl gdtptr
+	.globl gdt_limit
+gdt_limit = gdt_end - gdt - 1		/* Compute the table limit. */
+
+gdt:
+gdtptr:
+	.word	gdt_end - gdt -1	/* Compute the table limit. */
+	.long	gdt			/* We know the offset. */
+	.word	0
+
+	/* selgdt 0x08, flat code segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x9b, 0xcf, 0x00
+
+	/* selgdt 0x10, flat data segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x93, 0xcf, 0x00
+
+	/* selgdt 0x18, flat code segment for CAR */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x9b, 0xcf, 0x00
+
+	/* selgdt 0x20, flat data segment for CAR */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x93, 0xcf, 0x00
+gdt_end:
+
+	/* When we come here we are in protected mode. We expand the stack
+	 * and copy the data segment from ROM to the memory.
+	 *
+	 * After that, we call the chipset bootstrap routine that
+	 * does what is left of the chipset initialization.
+	 *
+	 * Note: Aligned to 4 so that we are sure that the prefetch
+	 * cache will be reloaded.
+	 */
+
+	.align  4
+	.globl protected_stage0
+protected_stage0:
+	/* This code was used by v2. TODO. */
+	lgdt	%cs:gdtptr
+	ljmp	$ROM_CODE_SEG, $__protected_stage0
+
+.globl __protected_stage0
+__protected_stage0:
+	/* Save the BIST result */
+	movl	%eax, %ebp
+
+	/*for normal part %ebx already contain cpu_init_detected from fallback call */
+
+cache_as_ram_setup:
+
+	movb	$0xA0, %al
+	outb	%al, $0x80
+
+	/* check if cpu_init_detected */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(1 << 11), %eax
+	movl	%eax, %ebx	/* We store the status */
+
+#ifdef CONFIG_CPU_AMD_K10
+	/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
+
+	/* Only BSP needed, for other nodes set during HT/memory init. */
+	/* So we need to check if it is BSP */
+	movl	$0x1b, %ecx
+	rdmsr
+	bt	$8, %eax /*BSC */
+	jnc	CAR_FAM10_out
+
+	/* Enable RT tables on BSP */
+	movl	$0x8000c06c, %eax
+	movw	$0xcf8, %dx
+	outl	%eax, %dx
+	addw	$4, %dx
+	inl	%dx, %eax
+	btr	$0, %eax
+	outl	%eax, %dx
+
+	/* Setup temporary DRAM map: [0,16M) bit 0-23 */
+	movl	$0x8000c144, %eax
+	movw	$0xcf8, %dx
+	outl	%eax, %dx
+	addw	$4, %dx
+	movl	$0, %eax
+	outl	%eax, %dx
+
+	movl	$0x8000c140, %eax
+	movw	$0xcf8, %dx
+	outl	%eax, %dx
+	addw	$4, %dx
+	movl	$3, %eax
+	outl	%eax, %dx
+
+CAR_FAM10_out:
+
+#endif
+
+#ifdef CONFIG_CPU_AMD_K10
+	/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
+	   Re-enable it in after RAM is initialized and before CAR is disabled */
+	movl	$0xc001102a, %ecx
+	rdmsr
+	bts	$15, %eax
+	wrmsr
+#endif
+
+	/* Set MtrrFixDramModEn for clear fixed mtrr */
+enable_fixed_mtrr_dram_modify:
+	movl	$SYSCFG_MSR, %ecx
+	rdmsr
+	andl	$(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
+	orl	$SYSCFG_MSR_MtrrFixDramModEn, %eax
+	wrmsr
+
+	/* Clear all MTRRs */
+	xorl	%edx, %edx
+	movl	$fixed_mtrr_msr, %esi
+
+clear_fixed_var_mtrr:
+	lodsl	(%esi), %eax
+	testl	%eax, %eax
+	jz		clear_fixed_var_mtrr_out
+
+	movl	%eax, %ecx
+	xorl	%eax, %eax
+	wrmsr
+
+	jmp		clear_fixed_var_mtrr
+clear_fixed_var_mtrr_out:
+
+/* 0x06 is the WB IO type for a given 4k segment.
+ * 0x1e is the MEM IO type for a given 4k segment (K10 and above).
+ * segs is the number of 4k segments in the area of the particular
+ *   register we want to use for CAR.
+ * reg is the register where the IO type should be stored.
+ */
+.macro extractmask segs, reg
+.if \segs <= 0
+	/* The xorl here is superfluous because at the point of first execution
+	 * of this macro, %eax and %edx are cleared. Later invocations of this
+	 * macro will have a monotonically increasing segs parameter.
+	 */
+	xorl \reg, \reg
+#ifdef CONFIG_CPU_AMD_K10
+.elseif \segs == 1
+	movl $0x1e000000, \reg /* WB MEM type */
+.elseif \segs == 2
+	movl $0x1e1e0000, \reg /* WB MEM type */
+.elseif \segs == 3
+	movl $0x1e1e1e00, \reg /* WB MEM type */
+.elseif \segs >= 4
+	movl $0x1e1e1e1e, \reg /* WB MEM type */
+#else
+.elseif \segs == 1
+	movl $0x06000000, \reg /* WB IO type */
+.elseif \segs == 2
+	movl $0x06060000, \reg /* WB IO type */
+.elseif \segs == 3
+	movl $0x06060600, \reg /* WB IO type */
+.elseif \segs >= 4
+	movl $0x06060606, \reg /* WB IO type */
+#endif
+.endif
+.endm
+
+/* size is the cache size in bytes we want to use for CAR.
+ * windowoffset is the 32k-aligned window into CAR size
+ */
+.macro simplemask carsize, windowoffset
+	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+	extractmask gas_bug_workaround, %eax
+	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+	extractmask gas_bug_workaround, %edx
+/* Without the gas bug workaround, the entire macro would consist only of the
+ * two lines below.
+	extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
+	extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+ */
+.endm
+
+#if CacheSize > 0x10000
+#error Invalid CAR size, must be at most 64k.
+#endif
+#if CacheSize < 0x1000
+#error Invalid CAR size, must be at least 4k. This is a processor limitation.
+#endif
+#if (CacheSize & (0x1000 - 1))
+#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
+#endif
+
+#if CacheSize > 0x8000 
+        /* enable caching for 32K-64K using fixed mtrr */
+        movl    $0x268, %ecx  /* fix4k_c0000*/
+	simplemask CacheSize, 0x8000
+        wrmsr
+#endif
+
+        /* enable caching for 0-32K using fixed mtrr */
+        movl    $0x269, %ecx  /* fix4k_c8000*/
+	simplemask CacheSize, 0
+	wrmsr
+
+	/* enable memory access for first MBs using top_mem */
+	movl	$TOP_MEM, %ecx
+	xorl	%edx, %edx
+	movl	$(((MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
+	wrmsr
+
+
+	/* disable cache */
+	movl	%cr0, %eax
+	orl		$(1 << 30),%eax
+	movl	%eax, %cr0
+/* this seems safe to do always. Leave it for now. */
+/*#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))*/
+	/* Set the default memory type and enable fixed and variable MTRRs */
+	movl	$MTRRdefType_MSR, %ecx
+	xorl	%edx, %edx
+	/* Enable Variable and Fixed MTRRs */
+	movl	$0x00000c00, %eax
+	wrmsr
+
+	/* Enable the MTRRs and IORRs in SYSCFG */
+	movl	$SYSCFG_MSR, %ecx
+	rdmsr
+	orl		$(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
+	wrmsr
+
+	movb	$0xA1, %al
+	outb	%al, $0x80
+
+	/* enable cache */
+	movl	%cr0, %eax
+	andl	$0x9fffffff, %eax
+	movl	%eax, %cr0
+
+
+#ifdef CONFIG_CPU_AMD_K10
+	/* So we need to check if it is BSP */
+	movl	$0x1b, %ecx
+	rdmsr
+	bt	$8, %eax /*BSC */
+	jnc	CAR_FAM10_ap
+#endif
+
+	movb	$0xA2, %al
+	outb	%al, $0x80
+
+/*#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))*/
+		/* Read the range with lodsl*/
+	cld
+	movl	$CacheBase, %esi
+	movl	$(CacheSize >> 2), %ecx
+	rep		lodsl
+	/* Clear the range */
+	movl	$CacheBase, %edi
+	movl	$(CacheSize >> 2), %ecx
+	xorl	%eax, %eax
+	rep		stosl
+
+//#endif /*USE_FAILOVER_IMAGE == 1*/
+
+	/* set up the stack pointer */
+	movl	$(CacheBase + CacheSize - GlobalVarSize), %eax
+	movl	%eax, %esp
+
+	movb	$0xA3, %al
+	outb	%al, $0x80
+
+#ifdef CONFIG_CPU_AMD_K10
+
+	jmp	CAR_FAM10_ap_out
+CAR_FAM10_ap:
+	/* need to set stack pointer for AP */
+	/* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
+	/* So need to get the NodeID and CoreID at first */
+	/* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
+
+	/* store our init detected */
+	movl	%ebx, %esi
+
+	/* get the coreid bits at first */
+	movl	$0x80000008, %eax
+	cpuid
+	shrl	$12, %ecx
+	andl	$0x0f, %ecx
+	movl	%ecx, %edi
+
+	/* get the initial apic id */
+	movl	$1, %eax
+	cpuid
+	shrl	$24, %ebx
+
+	/* get the nb cfg bit 54 */
+	movl	$0xc001001f, %ecx /* NB_CFG_MSR */
+	rdmsr
+	movl	%edi, %ecx	/* CoreID bits */
+	bt	$(54-32), %edx
+	jc	roll_cfg
+	rolb	%cl, %bl
+roll_cfg:
+
+	/* calculate stack pointer */
+	movl	$CacheSizeAPStack, %eax
+	mull	%ebx
+	movl	$(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
+	subl	%eax, %esp
+
+	/* retrive init detected */
+	movl	%esi, %ebx
+
+	movb	$0xA4, %al
+	outb	%al, $0x80
+
+CAR_FAM10_ap_out:
+#endif
+
+	movb	$0xA5, %al
+	outb	%al, $0x80
+
+	/* Restore the BIST result */
+	movl	%ebp, %eax
+
+	/* We need to set ebp ? No need */
+	movl	%esp, %ebp
+	pushl	%ebx  /* init detected */
+	pushl	%eax  /* bist */
+	call	stage1_main
+	/* We will not go back */
+
+	movb	$0xAF, %al		/* Should never see this postcode */
+	outb	%al, $0x80
+
+fixed_mtrr_msr:
+	.long	0x250, 0x258, 0x259
+	.long	0x268, 0x269, 0x26A
+	.long	0x26B, 0x26C, 0x26D
+	.long	0x26E, 0x26F
+var_mtrr_msr:
+	.long	0x200, 0x201, 0x202, 0x203
+	.long	0x204, 0x205, 0x206, 0x207
+	.long	0x208, 0x209, 0x20A, 0x20B
+	.long	0x20C, 0x20D, 0x20E, 0x20F
+var_iorr_msr:
+	.long	0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
+mem_top:
+	.long	0xC001001A, 0xC001001D
+	.long	0x000 /* NULL, end of table */
+
+cache_as_ram_setup_out:

Added: coreboot-v3/arch/x86/amdk8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amdk8/stage1.c	                        (rev 0)
+++ coreboot-v3/arch/x86/amdk8/stage1.c	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <msr.h>
+#include <amd_k8.h>
+
+/**
+ * Disable Cache As RAM (CAR) after memory is setup.
+ *
+ * Unknown how to do this just yet. 
+ */
+void disable_car(void)
+{
+	/* OK, here is the theory: we should be able to copy 
+	 * the data back over itself, and the wbinvd should then 
+	 * flush to memory. Let's see. 
+	 */
+	__asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
+	__asm__ __volatile__ ("wbinvd\n");
+	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
+	banner(BIOS_DEBUG, "disable_car: done");
+}

Deleted: coreboot-v3/arch/x86/mtrr.h
===================================================================
--- coreboot-v3/arch/x86/mtrr.h	2008-08-01 16:59:09 UTC (rev 701)
+++ coreboot-v3/arch/x86/mtrr.h	2008-08-01 17:03:22 UTC (rev 702)
@@ -1,41 +0,0 @@
-#ifndef ARCH_X86_MTRR_H
-#define ARCH_X86_MTRR_H
-
-/*  These are the region types  */
-#define MTRR_TYPE_UNCACHEABLE 0
-#define MTRR_TYPE_WRCOMB     1
-/*#define MTRR_TYPE_         2*/
-/*#define MTRR_TYPE_         3*/
-#define MTRR_TYPE_WRTHROUGH  4
-#define MTRR_TYPE_WRPROT     5
-#define MTRR_TYPE_WRBACK     6
-#define MTRR_NUM_TYPES       7
-
-#define MTRRcap_MSR     0x0fe
-#define MTRRdefType_MSR 0x2ff
-
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
-#define NUM_FIXED_RANGES 88
-#define MTRRfix64K_00000_MSR 0x250
-#define MTRRfix16K_80000_MSR 0x258
-#define MTRRfix16K_A0000_MSR 0x259
-#define MTRRfix4K_C0000_MSR 0x268
-#define MTRRfix4K_C8000_MSR 0x269
-#define MTRRfix4K_D0000_MSR 0x26a
-#define MTRRfix4K_D8000_MSR 0x26b
-#define MTRRfix4K_E0000_MSR 0x26c
-#define MTRRfix4K_E8000_MSR 0x26d
-#define MTRRfix4K_F0000_MSR 0x26e
-#define MTRRfix4K_F8000_MSR 0x26f
-
-#if !defined (ASSEMBLY)
-
-void x86_setup_var_mtrrs(unsigned address_bits);
-void x86_setup_mtrrs(unsigned address_bits);
-int x86_mtrr_check(void);
-
-#endif
-
-#endif				/* ARCH_X86_MTRR_H */

Added: coreboot-v3/include/arch/x86/amd_k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd_k8.h	                        (rev 0)
+++ coreboot-v3/include/arch/x86/amd_k8.h	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#define ROM_CODE_SEG		0x08
+#define ROM_DATA_SEG		0x10
+
+#define CACHE_RAM_CODE_SEG	0x18
+#define CACHE_RAM_DATA_SEG	0x20
+
+#define IORR_FIRST 0xC0010016
+#define IORR_LAST  0xC0010019
+
+#define MTRR_READ_MEM			(1 << 4)
+#define MTRR_WRITE_MEM			(1 << 3)
+
+#define SYSCFG_MSR			0xC0010010
+#define SYSCFG_MSR_TOM2En		(1 << 21)
+#define SYSCFG_MSR_MtrrVarDramEn	(1 << 20)
+#define SYSCFG_MSR_MtrrFixDramModEn	(1 << 19)
+#define SYSCFG_MSR_MtrrFixDramEn	(1 << 18)
+#define SYSCFG_MSR_UcLockEn		(1 << 17)
+#define SYSCFG_MSR_ChxToDirtyDis	(1 << 16)
+#define SYSCFG_MSR_ClVicBlkEn		(1 << 11)
+#define SYSCFG_MSR_SetDirtyEnO		(1 << 10)
+#define SYSCFG_MSR_SetDirtyEnS		(1 <<  9)
+#define SYSCFG_MSR_SetDirtyEnE		(1 <<  8)
+#define SYSCFG_MSR_SysVicLimitMask	((1 << 8) - (1 << 5))
+#define SYSCFG_MSR_SysAckLimitMask	((1 << 5) - (1 << 0))
+
+#define IORR0_BASE			0xC0010016
+#define IORR0_MASK			0xC0010017
+#define IORR1_BASE			0xC0010018
+#define IORR1_MASK			0xC0010019
+#define TOP_MEM				0xC001001A
+#define TOP_MEM2			0xC001001D
+
+#define TOP_MEM_MASK			0x007fffff
+#define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
+
+

Copied: coreboot-v3/include/arch/x86/mtrr.h (from rev 699, coreboot-v3/arch/x86/mtrr.h)
===================================================================
--- coreboot-v3/include/arch/x86/mtrr.h	                        (rev 0)
+++ coreboot-v3/include/arch/x86/mtrr.h	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,41 @@
+#ifndef ARCH_X86_MTRR_H
+#define ARCH_X86_MTRR_H
+
+/*  These are the region types  */
+#define MTRR_TYPE_UNCACHEABLE 0
+#define MTRR_TYPE_WRCOMB     1
+/*#define MTRR_TYPE_         2*/
+/*#define MTRR_TYPE_         3*/
+#define MTRR_TYPE_WRTHROUGH  4
+#define MTRR_TYPE_WRPROT     5
+#define MTRR_TYPE_WRBACK     6
+#define MTRR_NUM_TYPES       7
+
+#define MTRRcap_MSR     0x0fe
+#define MTRRdefType_MSR 0x2ff
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+#define NUM_FIXED_RANGES 88
+#define MTRRfix64K_00000_MSR 0x250
+#define MTRRfix16K_80000_MSR 0x258
+#define MTRRfix16K_A0000_MSR 0x259
+#define MTRRfix4K_C0000_MSR 0x268
+#define MTRRfix4K_C8000_MSR 0x269
+#define MTRRfix4K_D0000_MSR 0x26a
+#define MTRRfix4K_D8000_MSR 0x26b
+#define MTRRfix4K_E0000_MSR 0x26c
+#define MTRRfix4K_E8000_MSR 0x26d
+#define MTRRfix4K_F0000_MSR 0x26e
+#define MTRRfix4K_F8000_MSR 0x26f
+
+#if !defined (ASSEMBLY)
+
+void x86_setup_var_mtrrs(unsigned address_bits);
+void x86_setup_mtrrs(unsigned address_bits);
+int x86_mtrr_check(void);
+
+#endif
+
+#endif				/* ARCH_X86_MTRR_H */

Modified: coreboot-v3/mainboard/Kconfig
===================================================================
--- coreboot-v3/mainboard/Kconfig	2008-08-01 16:59:09 UTC (rev 701)
+++ coreboot-v3/mainboard/Kconfig	2008-08-01 17:03:22 UTC (rev 702)
@@ -42,6 +42,11 @@
 	help
 	  Select this option for various systems from the Artec Group.
 
+config VENDOR_GIGABYTE
+	bool "Gigabyte"
+	help
+	  Select this option for various systems from Gigabyte
+
 config VENDOR_EMULATION
 	bool "Emulated systems"
 	help
@@ -58,6 +63,7 @@
 source "mainboard/amd/Kconfig"
 source "mainboard/artecgroup/Kconfig"
 source "mainboard/emulation/Kconfig"
+source "mainboard/gigabyte/Kconfig"
 source "mainboard/pcengines/Kconfig"
 
 choice

Added: coreboot-v3/mainboard/gigabyte/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/Kconfig	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/Kconfig	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_GIGABYTE
+
+config BOARD_GIGABYTE_M57SLI
+	bool "M57SLI"
+	select ARCH_X86
+	select OPTION_TABLE
+	select CPU_AMD_K8
+	help
+	  Gigabyte M57SLI
+
+endchoice
+
+source "mainboard/gigabyte/m57sli/Kconfig"

Added: coreboot-v3/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Kconfig	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Kconfig	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config MAINBOARD_NAME
+	string
+	default gigabyte/m57sli
+	depends BOARD_GIGABYTE_M57SLI
+	help
+	  This is the default mainboard name.

Added: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006-2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
+
+INITRAM_OBJ =      $(src)/mainboard/$(MAINBOARDDIR)/initram.c
+
+STAGE2_MAINBOARD_OBJ = 
+
+$(obj)/coreboot.vpd:
+	$(Q)printf "  BUILD   DUMMY VPD\n"
+	$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
+

Added: coreboot-v3/mainboard/gigabyte/m57sli/dts
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/dts	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/dts	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/{
+	mainboard_vendor = "Gigabyte";
+	mainboard_name = "M57SLI";
+	cpus { };
+	apic at 0 {
+	};
+	domain at 0 {
+	};
+};

Added: coreboot-v3/mainboard/gigabyte/m57sli/initram.c
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/initram.c	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2007 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define _MAINOBJECT
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_k8.h>
+#include <spd.h>
+
+/** 
+  * main for initram for the Gigabyte m57sli.  
+  */
+int main(void)
+{
+	printk(BIOS_DEBUG, "Hi there from stage1\n");
+	post_code(POST_START_OF_MAIN);
+
+	printk(BIOS_DEBUG, "stage1 returns\n");
+	return 0;
+}

Added: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c	2008-08-01 17:03:22 UTC (rev 702)
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <arch/x86/msr.h>
+
+void hardware_stage1(void)
+{
+	post_code(POST_START_OF_MAIN);
+
+}
+
+void mainboard_pre_payload(void)
+{
+	banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}




From rminnich at gmail.com  Fri Aug  1 19:04:51 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 10:04:51 -0700
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <48933ED4.8060001@amd.com>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
	<48933ED4.8060001@amd.com>
Message-ID: <13426df10808011004k27334c5eh93c3f36cbd19a0cd@mail.gmail.com>

On Fri, Aug 1, 2008 at 9:50 AM, Marc Jones <Marc.Jones at amd.com> wrote:

>
>> -#endif                         /* ARCH_X86_MTRR_H */
>> Index: arch/x86/Makefile
>> ===================================================================
>> --- arch/x86/Makefile   (revision 699)
>> +++ arch/x86/Makefile   (working copy)
>> @@ -124,9 +124,12 @@
>>        STAGE0_ARCH_X86_OBJ += geodelx/stage1.o
>>        STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o
>>  else
>> -       STAGE0_CAR_OBJ = stage0_i586.o
>> +ifeq ($(CONFIG_CPU_AMD_K8),y)
>> +       STAGE0_CAR_OBJ = amd/stage0.o
>> +       STAGE0_ARCH_X86_OBJ += amdk8/stage1.o
>>  endif
>>  endif
>> +endif
>
> Add else and put the stage0_i586 on the end?

I took it out. There should be a valid value for the CPU. anything
else is an error. This mistake bit me so I don't want it getting
anyone else.



>
> I agree with getting the pieces in place as we go.
> The files looked fine to me but I didn't try to build it.....
>
> Acked-by: Marc Jones <marc.jones at amd.com>

Committed revision 702.

I added gigabyte/Kconfig per peter's note.

ron



From rminnich at gmail.com  Fri Aug  1 19:06:18 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 10:06:18 -0700
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <20080801164001.26470.qmail@stuge.se>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
	<20080801164001.26470.qmail@stuge.se>
Message-ID: <13426df10808011006y51fe60fdj88b59f0c4e798c9b@mail.gmail.com>

On Fri, Aug 1, 2008 at 9:40 AM, Peter Stuge <peter at stuge.se> wrote:
> On Fri, Aug 01, 2008 at 09:07:26AM -0700, ron minnich wrote:
>> This almost builds. dts is not built, any idea why?  I could use
>> help.
>
> Looking at it.
>
>
>> Anybody want to do the superio? Should be quick.
>
> What's needed here specifically?

This;

superio/ite/it8716f



> What about amdk8 vs amdfam10 ? Can we already do something clever?
> (Yes, yes, let's get it working first. :p)

note that the stage0.S is in arch/x86/amd, not amdk8. It supports fam10 and k8
ron



From peter at stuge.se  Fri Aug  1 19:12:28 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Aug 2008 19:12:28 +0200
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
Message-ID: <20080801171228.5774.qmail@stuge.se>

On Fri, Aug 01, 2008 at 09:07:26AM -0700, ron minnich wrote:
> This almost builds.

I need the attached patch (sans the trivial cleanup hunk) in order to
build up to missing statictree.


> dts is not built, any idea why?

On it.


//Peter
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From svn at coreboot.org  Fri Aug  1 19:16:45 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 19:16:45 +0200
Subject: [coreboot] r703 - in coreboot-v3/arch/x86: . amd amdk8
Message-ID: <mailman.1750.1355071348.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-01 19:16:45 +0200 (Fri, 01 Aug 2008)
New Revision: 703

Modified:
   coreboot-v3/arch/x86/Kconfig
   coreboot-v3/arch/x86/amd/stage0.S
   coreboot-v3/arch/x86/amdk8/stage1.c
Log:
v3: Clean up a Kconfig value and fixup K8 CAR defines to get CONFIG_ values

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig	2008-08-01 17:03:22 UTC (rev 702)
+++ coreboot-v3/arch/x86/Kconfig	2008-08-01 17:16:45 UTC (rev 703)
@@ -90,6 +90,6 @@
 	hex
 	default 0x1000 if CPU_I586
 	default 0x8000 if CPU_AMD_GEODELX
-	default 0x08000 if CPU_AMD_K8
+	default 0x8000 if CPU_AMD_K8
 	help
 	  This option sets the size of the area used for CAR.

Modified: coreboot-v3/arch/x86/amd/stage0.S
===================================================================
--- coreboot-v3/arch/x86/amd/stage0.S	2008-08-01 17:03:22 UTC (rev 702)
+++ coreboot-v3/arch/x86/amd/stage0.S	2008-08-01 17:16:45 UTC (rev 703)
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 #include "../macros.h"
-#define CacheSize DCACHE_RAM_SIZE
-#define CacheBase DCACHE_RAM_BASE
+#define CacheSize CONFIG_CARSIZE
+#define CacheBase CONFIG_CARBASE
 #define MEM_TOPK 2048
 #define ASSEMBLY
 

Modified: coreboot-v3/arch/x86/amdk8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amdk8/stage1.c	2008-08-01 17:03:22 UTC (rev 702)
+++ coreboot-v3/arch/x86/amdk8/stage1.c	2008-08-01 17:16:45 UTC (rev 703)
@@ -35,7 +35,7 @@
 	 * the data back over itself, and the wbinvd should then 
 	 * flush to memory. Let's see. 
 	 */
-	__asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
+	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
 	__asm__ __volatile__ ("wbinvd\n");
 	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
 	banner(BIOS_DEBUG, "disable_car: done");




From rminnich at gmail.com  Fri Aug  1 19:17:49 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 10:17:49 -0700
Subject: [coreboot] patch: k8 support in v3.
In-Reply-To: <20080801171228.5774.qmail@stuge.se>
References: <13426df10808010907t6a11be30vbe31d84e8fa0124c@mail.gmail.com>
	<20080801171228.5774.qmail@stuge.se>
Message-ID: <13426df10808011017w37083375rc80db720524e9ea@mail.gmail.com>

On Fri, Aug 1, 2008 at 10:12 AM, Peter Stuge <peter at stuge.se> wrote:
> On Fri, Aug 01, 2008 at 09:07:26AM -0700, ron minnich wrote:
>> This almost builds.
>
> I need the attached patch (sans the trivial cleanup hunk) in order to
> build up to missing statictree.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Committed revision 703.



From svn at coreboot.org  Fri Aug  1 19:26:07 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 19:26:07 +0200
Subject: [coreboot] r704 - in coreboot-v3/arch/x86: . amd amd/k8
Message-ID: <mailman.1751.1355071348.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-01 19:26:06 +0200 (Fri, 01 Aug 2008)
New Revision: 704

Added:
   coreboot-v3/arch/x86/amd/k8/
   coreboot-v3/arch/x86/amd/k8/stage1.c
Removed:
   coreboot-v3/arch/x86/amd/k8/stage1.c
   coreboot-v3/arch/x86/amdk8/
Log:
move amdk8 to amd/k8 per IRC discussion
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>



Deleted: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amdk8/stage1.c	2008-08-01 17:03:22 UTC (rev 702)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-01 17:26:06 UTC (rev 704)
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <types.h>
-#include <lib.h>
-#include <console.h>
-#include <msr.h>
-#include <amd_k8.h>
-
-/**
- * Disable Cache As RAM (CAR) after memory is setup.
- *
- * Unknown how to do this just yet. 
- */
-void disable_car(void)
-{
-	/* OK, here is the theory: we should be able to copy 
-	 * the data back over itself, and the wbinvd should then 
-	 * flush to memory. Let's see. 
-	 */
-	__asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
-	__asm__ __volatile__ ("wbinvd\n");
-	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
-	banner(BIOS_DEBUG, "disable_car: done");
-}

Copied: coreboot-v3/arch/x86/amd/k8/stage1.c (from rev 703, coreboot-v3/arch/x86/amdk8/stage1.c)
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c	                        (rev 0)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-01 17:26:06 UTC (rev 704)
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <msr.h>
+#include <amd_k8.h>
+
+/**
+ * Disable Cache As RAM (CAR) after memory is setup.
+ *
+ * Unknown how to do this just yet. 
+ */
+void disable_car(void)
+{
+	/* OK, here is the theory: we should be able to copy 
+	 * the data back over itself, and the wbinvd should then 
+	 * flush to memory. Let's see. 
+	 */
+	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
+	__asm__ __volatile__ ("wbinvd\n");
+	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
+	banner(BIOS_DEBUG, "disable_car: done");
+}




From rminnich at gmail.com  Fri Aug  1 19:27:42 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 10:27:42 -0700
Subject: [coreboot] patch: rename
Message-ID: <13426df10808011027y28965ae5o93b62f44f46468de@mail.gmail.com>

move amdk8 to amd/k8 per IRC discussion
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>
Committed revision 704.



From svn at coreboot.org  Fri Aug  1 19:40:23 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 19:40:23 +0200
Subject: [coreboot] r705 - in coreboot-v3: . mainboard/adl
	mainboard/adl/msm800sev mainboard/amd mainboard/amd/db800
	mainboard/amd/norwich mainboard/artecgroup
	mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62
	mainboard/emulation mainboard/emulation/qemu-x86
	mainboard/pcengines mainboard/pcengines/alix1c
	mainboard/pcengines/alix2c3
Message-ID: <mailman.1752.1355071348.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-08-01 19:40:22 +0200 (Fri, 01 Aug 2008)
New Revision: 705

Removed:
   coreboot-v3/mainboard/adl/msm800sev/Kconfig
   coreboot-v3/mainboard/amd/db800/Kconfig
   coreboot-v3/mainboard/amd/norwich/Kconfig
   coreboot-v3/mainboard/artecgroup/dbe61/Kconfig
   coreboot-v3/mainboard/artecgroup/dbe62/Kconfig
   coreboot-v3/mainboard/emulation/qemu-x86/Kconfig
   coreboot-v3/mainboard/pcengines/alix1c/Kconfig
   coreboot-v3/mainboard/pcengines/alix2c3/Kconfig
Modified:
   coreboot-v3/Makefile
   coreboot-v3/mainboard/adl/Kconfig
   coreboot-v3/mainboard/amd/Kconfig
   coreboot-v3/mainboard/artecgroup/Kconfig
   coreboot-v3/mainboard/emulation/Kconfig
   coreboot-v3/mainboard/emulation/qemu-x86/defconfig
   coreboot-v3/mainboard/pcengines/Kconfig
   coreboot-v3/mainboard/pcengines/alix1c/defconfig
   coreboot-v3/mainboard/pcengines/alix2c3/defconfig
Log:
Right now, our Kconfig files in the mainboard/ directory in the v3 tree 
are not exactly in the best shape.
- MAINBOARD_NAME is claimed to be the mainboard name, but it is used 
  exclusively as mainboard directory.
- MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to
  $VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes
  $VENDOR/$BOARD as board path.
- MAINBOARD_NAME has a help text which will never be displayed to
  the user.

The diffstat is encouraging: A total of 200 lines have been
removed completely.

Per-board Kconfig files have been deleted, the remnants making sense
have been merged into per-vendor Kconfig files and the never-shown help
texts have been removed.

If there are ever some real per-board options and not just tricks to
make the makefiles behave, we can resurrect the per-board Kconfig files.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/Makefile
===================================================================
--- coreboot-v3/Makefile	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/Makefile	2008-08-01 17:40:22 UTC (rev 705)
@@ -81,7 +81,7 @@
 	$(Q)printf "  DONE\n"
 
 ARCH:=$(shell echo $(CONFIG_ARCH))
-MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_NAME))
+MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_DIR))
 export MAINBOARDDIR
 
 COREBOOTINCLUDE    :=   -I$(src) -Iinclude \

Modified: coreboot-v3/mainboard/adl/Kconfig
===================================================================
--- coreboot-v3/mainboard/adl/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/adl/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -36,5 +36,8 @@
 
 endchoice
 
-source "mainboard/adl/msm800sev/Kconfig"
+config MAINBOARD_DIR
+	string
+	default adl/msm800sev
+	depends BOARD_ADL_MSM800SEV
 

Deleted: coreboot-v3/mainboard/adl/msm800sev/Kconfig
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/adl/msm800sev/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default adl/msm800sev
-	depends BOARD_ADL_MSM800SEV
-	help
-	  This is the name for the Advanced Digital Logic MSM800SEV mainboard.
-

Modified: coreboot-v3/mainboard/amd/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/amd/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -48,6 +48,13 @@
 
 endchoice
 
-source "mainboard/amd/db800/Kconfig"
-source "mainboard/amd/norwich/Kconfig"
+config MAINBOARD_DIR
+	string
+	default amd/db800
+	depends BOARD_AMD_DB800
 
+config MAINBOARD_DIR
+	string
+	default amd/norwich
+	depends BOARD_AMD_NORWICH
+

Deleted: coreboot-v3/mainboard/amd/db800/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/db800/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/amd/db800/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default amd/db800
-	depends BOARD_AMD_DB800
-	help
-	  This is the default mainboard name.
-

Deleted: coreboot-v3/mainboard/amd/norwich/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/norwich/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/amd/norwich/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default amd/norwich
-	depends BOARD_AMD_NORWICH
-	help
-	  This is the default mainboard name.
-

Modified: coreboot-v3/mainboard/artecgroup/Kconfig
===================================================================
--- coreboot-v3/mainboard/artecgroup/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/artecgroup/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -47,5 +47,12 @@
 
 endchoice
 
-source "mainboard/artecgroup/dbe61/Kconfig"
-source "mainboard/artecgroup/dbe62/Kconfig"
+config MAINBOARD_DIR
+	string
+	default artecgroup/dbe61
+	depends BOARD_ARTECGROUP_DBE61
+
+config MAINBOARD_DIR
+	string
+	default artecgroup/dbe62
+	depends BOARD_ARTECGROUP_DBE62

Deleted: coreboot-v3/mainboard/artecgroup/dbe61/Kconfig
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/artecgroup/dbe61/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default artecgroup/dbe61
-	depends BOARD_ARTECGROUP_DBE61
-	help
-	  This is the default mainboard name.
-

Deleted: coreboot-v3/mainboard/artecgroup/dbe62/Kconfig
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/artecgroup/dbe62/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default artecgroup/dbe62
-	depends BOARD_ARTECGROUP_DBE62
-	help
-	  This is the default mainboard name.

Modified: coreboot-v3/mainboard/emulation/Kconfig
===================================================================
--- coreboot-v3/mainboard/emulation/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/emulation/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -37,5 +37,8 @@
 
 endchoice
 
-source "mainboard/emulation/qemu-x86/Kconfig"
+config MAINBOARD_DIR
+	string
+	default emulation/qemu-x86
+	depends BOARD_EMULATION_QEMU_X86
 

Deleted: coreboot-v3/mainboard/emulation/qemu-x86/Kconfig
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/emulation/qemu-x86/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,29 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default emulation/qemu-x86
-	depends BOARD_EMULATION_QEMU_X86
-	help
-	  This is the default mainboard name.
-

Modified: coreboot-v3/mainboard/emulation/qemu-x86/defconfig
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/defconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/emulation/qemu-x86/defconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -19,7 +19,7 @@
 # CONFIG_VENDOR_ARTECGROUP is not set
 CONFIG_VENDOR_EMULATION=y
 # CONFIG_VENDOR_PCENGINES is not set
-CONFIG_MAINBOARD_NAME="emulation/qemu-x86"
+CONFIG_MAINBOARD_DIR="emulation/qemu-x86"
 CONFIG_BOARD_EMULATION_QEMU_X86=y
 # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_256=y

Modified: coreboot-v3/mainboard/pcengines/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/pcengines/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -48,6 +48,12 @@
 
 endchoice
 
-source "mainboard/pcengines/alix1c/Kconfig"
-source "mainboard/pcengines/alix2c3/Kconfig"
+config MAINBOARD_DIR
+	string
+	default pcengines/alix1c
+	depends BOARD_PCENGINES_ALIX1C
 
+config MAINBOARD_DIR
+	string
+	default pcengines/alix2c3
+	depends BOARD_PCENGINES_ALIX2C3

Deleted: coreboot-v3/mainboard/pcengines/alix1c/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/pcengines/alix1c/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default pcengines/alix1c
-	depends BOARD_PCENGINES_ALIX1C
-	help
-	  This is the default mainboard name.

Modified: coreboot-v3/mainboard/pcengines/alix1c/defconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/defconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/pcengines/alix1c/defconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -20,7 +20,7 @@
 # CONFIG_VENDOR_ARTECGROUP is not set
 # CONFIG_VENDOR_EMULATION is not set
 CONFIG_VENDOR_PCENGINES=y
-CONFIG_MAINBOARD_NAME="pcengines/alix1c"
+CONFIG_MAINBOARD_DIR="pcengines/alix1c"
 CONFIG_BOARD_PCENGINES_ALIX1C=y
 # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set

Deleted: coreboot-v3/mainboard/pcengines/alix2c3/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix2c3/Kconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/pcengines/alix2c3/Kconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default pcengines/alix2c3
-	depends BOARD_PCENGINES_ALIX2C3
-	help
-	  This is the default mainboard name.

Modified: coreboot-v3/mainboard/pcengines/alix2c3/defconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/alix2c3/defconfig	2008-08-01 17:26:06 UTC (rev 704)
+++ coreboot-v3/mainboard/pcengines/alix2c3/defconfig	2008-08-01 17:40:22 UTC (rev 705)
@@ -19,7 +19,7 @@
 # CONFIG_VENDOR_ARTECGROUP is not set
 # CONFIG_VENDOR_EMULATION is not set
 CONFIG_VENDOR_PCENGINES=y
-CONFIG_MAINBOARD_NAME="pcengines/alix2c3"
+CONFIG_MAINBOARD_DIR="pcengines/alix2c3"
 # CONFIG_BOARD_PCENGINES_ALIX1C is not set
 CONFIG_BOARD_PCENGINES_ALIX2C3=y
 # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set




From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  1 19:41:15 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 Aug 2008 19:41:15 +0200
Subject: [coreboot] [PATCH] v3 mainboard Kconfig cleanup
In-Reply-To: <13426df10808010840x35f64446taf3335d4ab08be36@mail.gmail.com>
References: <487562BA.2060501@gmx.net>
	<48775AED.50909@gmx.net>	<489321E4.6020004@gmx.net>
	<13426df10808010840x35f64446taf3335d4ab08be36@mail.gmail.com>
Message-ID: <48934ABB.6050001@gmx.net>

On 01.08.2008 17:40, ron minnich wrote:
> looks fine.
>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>   

Thanks, r705.

Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  1 19:57:36 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 Aug 2008 19:57:36 +0200
Subject: [coreboot] [PATCH] v3 mainboard Kconfig cleanup: M57SLI fixups
In-Reply-To: <13426df10808010840x35f64446taf3335d4ab08be36@mail.gmail.com>
References: <487562BA.2060501@gmx.net>
	<48775AED.50909@gmx.net>	<489321E4.6020004@gmx.net>
	<13426df10808010840x35f64446taf3335d4ab08be36@mail.gmail.com>
Message-ID: <48934E90.6030302@gmx.net>

Fix up the Gigabyte M57SLI target to conform to the new style
introduced in r605.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/m57sli/Kconfig	(Revision 705)
+++ corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/m57sli/Kconfig	(Arbeitskopie)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default gigabyte/m57sli
-	depends BOARD_GIGABYTE_M57SLI
-	help
-	  This is the default mainboard name.
Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/Kconfig
===================================================================
--- corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/Kconfig	(Revision 705)
+++ corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/Kconfig	(Arbeitskopie)
@@ -33,4 +33,7 @@
 
 endchoice
 
-source "mainboard/gigabyte/m57sli/Kconfig"
+config MAINBOARD_DIR
+	string
+	default gigabyte/m57sli
+	depends BOARD_GIGABYTE_M57SLI




-- 
http://www.hailfinger.org/




From peter at stuge.se  Fri Aug  1 20:00:30 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Aug 2008 20:00:30 +0200
Subject: [coreboot] [PATCH] v3 mainboard Kconfig cleanup: M57SLI fixups
In-Reply-To: <48934E90.6030302@gmx.net>
References: <487562BA.2060501@gmx.net> <48775AED.50909@gmx.net>
	<489321E4.6020004@gmx.net>
	<13426df10808010840x35f64446taf3335d4ab08be36@mail.gmail.com>
	<48934E90.6030302@gmx.net>
Message-ID: <20080801180030.20929.qmail@stuge.se>

On Fri, Aug 01, 2008 at 07:57:36PM +0200, Carl-Daniel Hailfinger wrote:
> Fix up the Gigabyte M57SLI target to conform to the new style
> introduced in r605.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Acked-by: Peter Stuge <peter at stuge.se>


> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/m57sli/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/m57sli/Kconfig	(Revision 705)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/m57sli/Kconfig	(Arbeitskopie)
> @@ -1,28 +0,0 @@
> -##
> -## This file is part of the coreboot project.
> -##
> -## Copyright (C) 2007 coresystems GmbH
> -## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
> -## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
> -##
> -## This program is free software; you can redistribute it and/or modify
> -## it under the terms of the GNU General Public License as published by
> -## the Free Software Foundation; either version 2 of the License, or
> -## (at your option) any later version.
> -##
> -## This program is distributed in the hope that it will be useful,
> -## but WITHOUT ANY WARRANTY; without even the implied warranty of
> -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -## GNU General Public License for more details.
> -##
> -## You should have received a copy of the GNU General Public License
> -## along with this program; if not, write to the Free Software
> -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> -##
> -
> -config MAINBOARD_NAME
> -	string
> -	default gigabyte/m57sli
> -	depends BOARD_GIGABYTE_M57SLI
> -	help
> -	  This is the default mainboard name.
> Index: corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/Kconfig
> ===================================================================
> --- corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/Kconfig	(Revision 705)
> +++ corebootv3-mainboard_Kconfig_cleanup/mainboard/gigabyte/Kconfig	(Arbeitskopie)
> @@ -33,4 +33,7 @@
>  
>  endchoice
>  
> -source "mainboard/gigabyte/m57sli/Kconfig"
> +config MAINBOARD_DIR
> +	string
> +	default gigabyte/m57sli
> +	depends BOARD_GIGABYTE_M57SLI
> 
> 
> 



From svn at coreboot.org  Fri Aug  1 20:00:55 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 20:00:55 +0200
Subject: [coreboot] r706 - in coreboot-v3: include/arch/x86
	include/arch/x86/amd include/arch/x86/amd/k8 northbridge/amd
Message-ID: <mailman.1753.1355071348.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-01 20:00:54 +0200 (Fri, 01 Aug 2008)
New Revision: 706

Added:
   coreboot-v3/include/arch/x86/amd/
   coreboot-v3/include/arch/x86/amd/k8/
   coreboot-v3/include/arch/x86/amd/k8/k8.h
   coreboot-v3/northbridge/amd/k8/
Removed:
   coreboot-v3/include/arch/x86/amd_k8.h
Log:
rename per IRC

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>


Copied: coreboot-v3/include/arch/x86/amd/k8/k8.h (from rev 703, coreboot-v3/include/arch/x86/amd_k8.h)
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h	                        (rev 0)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-08-01 18:00:54 UTC (rev 706)
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#define ROM_CODE_SEG		0x08
+#define ROM_DATA_SEG		0x10
+
+#define CACHE_RAM_CODE_SEG	0x18
+#define CACHE_RAM_DATA_SEG	0x20
+
+#define IORR_FIRST 0xC0010016
+#define IORR_LAST  0xC0010019
+
+#define MTRR_READ_MEM			(1 << 4)
+#define MTRR_WRITE_MEM			(1 << 3)
+
+#define SYSCFG_MSR			0xC0010010
+#define SYSCFG_MSR_TOM2En		(1 << 21)
+#define SYSCFG_MSR_MtrrVarDramEn	(1 << 20)
+#define SYSCFG_MSR_MtrrFixDramModEn	(1 << 19)
+#define SYSCFG_MSR_MtrrFixDramEn	(1 << 18)
+#define SYSCFG_MSR_UcLockEn		(1 << 17)
+#define SYSCFG_MSR_ChxToDirtyDis	(1 << 16)
+#define SYSCFG_MSR_ClVicBlkEn		(1 << 11)
+#define SYSCFG_MSR_SetDirtyEnO		(1 << 10)
+#define SYSCFG_MSR_SetDirtyEnS		(1 <<  9)
+#define SYSCFG_MSR_SetDirtyEnE		(1 <<  8)
+#define SYSCFG_MSR_SysVicLimitMask	((1 << 8) - (1 << 5))
+#define SYSCFG_MSR_SysAckLimitMask	((1 << 5) - (1 << 0))
+
+#define IORR0_BASE			0xC0010016
+#define IORR0_MASK			0xC0010017
+#define IORR1_BASE			0xC0010018
+#define IORR1_MASK			0xC0010019
+#define TOP_MEM				0xC001001A
+#define TOP_MEM2			0xC001001D
+
+#define TOP_MEM_MASK			0x007fffff
+#define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
+
+

Deleted: coreboot-v3/include/arch/x86/amd_k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd_k8.h	2008-08-01 17:40:22 UTC (rev 705)
+++ coreboot-v3/include/arch/x86/amd_k8.h	2008-08-01 18:00:54 UTC (rev 706)
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-#define ROM_CODE_SEG		0x08
-#define ROM_DATA_SEG		0x10
-
-#define CACHE_RAM_CODE_SEG	0x18
-#define CACHE_RAM_DATA_SEG	0x20
-
-#define IORR_FIRST 0xC0010016
-#define IORR_LAST  0xC0010019
-
-#define MTRR_READ_MEM			(1 << 4)
-#define MTRR_WRITE_MEM			(1 << 3)
-
-#define SYSCFG_MSR			0xC0010010
-#define SYSCFG_MSR_TOM2En		(1 << 21)
-#define SYSCFG_MSR_MtrrVarDramEn	(1 << 20)
-#define SYSCFG_MSR_MtrrFixDramModEn	(1 << 19)
-#define SYSCFG_MSR_MtrrFixDramEn	(1 << 18)
-#define SYSCFG_MSR_UcLockEn		(1 << 17)
-#define SYSCFG_MSR_ChxToDirtyDis	(1 << 16)
-#define SYSCFG_MSR_ClVicBlkEn		(1 << 11)
-#define SYSCFG_MSR_SetDirtyEnO		(1 << 10)
-#define SYSCFG_MSR_SetDirtyEnS		(1 <<  9)
-#define SYSCFG_MSR_SetDirtyEnE		(1 <<  8)
-#define SYSCFG_MSR_SysVicLimitMask	((1 << 8) - (1 << 5))
-#define SYSCFG_MSR_SysAckLimitMask	((1 << 5) - (1 << 0))
-
-#define IORR0_BASE			0xC0010016
-#define IORR0_MASK			0xC0010017
-#define IORR1_BASE			0xC0010018
-#define IORR1_MASK			0xC0010019
-#define TOP_MEM				0xC001001A
-#define TOP_MEM2			0xC001001D
-
-#define TOP_MEM_MASK			0x007fffff
-#define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
-
-




From svn at coreboot.org  Fri Aug  1 20:03:18 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 20:03:18 +0200
Subject: [coreboot] r707 - in coreboot-v3/mainboard/gigabyte: . m57sli
Message-ID: <mailman.1754.1355071348.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-08-01 20:03:18 +0200 (Fri, 01 Aug 2008)
New Revision: 707

Removed:
   coreboot-v3/mainboard/gigabyte/m57sli/Kconfig
Modified:
   coreboot-v3/mainboard/gigabyte/Kconfig
Log:
Fix up the Gigabyte M57SLI target to conform to the new style
introduced in r605.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/mainboard/gigabyte/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/Kconfig	2008-08-01 18:00:54 UTC (rev 706)
+++ coreboot-v3/mainboard/gigabyte/Kconfig	2008-08-01 18:03:18 UTC (rev 707)
@@ -33,4 +33,7 @@
 
 endchoice
 
-source "mainboard/gigabyte/m57sli/Kconfig"
+config MAINBOARD_DIR
+	string
+	default gigabyte/m57sli
+	depends BOARD_GIGABYTE_M57SLI

Deleted: coreboot-v3/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Kconfig	2008-08-01 18:00:54 UTC (rev 706)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Kconfig	2008-08-01 18:03:18 UTC (rev 707)
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 coresystems GmbH
-## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
-## Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config MAINBOARD_NAME
-	string
-	default gigabyte/m57sli
-	depends BOARD_GIGABYTE_M57SLI
-	help
-	  This is the default mainboard name.




From rminnich at gmail.com  Fri Aug  1 20:04:16 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 11:04:16 -0700
Subject: [coreboot] patch: sysconf for v3
Message-ID: <13426df10808011104w3bb0b657yeeb1ec61fcb3fcf@mail.gmail.com>

add sysconf.h for k8

Ackers, please commit for me if you can.


ron
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From info at coresystems.de  Fri Aug  1 20:05:24 2008
From: info at coresystems.de (coreboot information)
Date: Fri, 01 Aug 2008 20:05:24 +0200
Subject: [coreboot] r3442 build service
Message-ID: <E1KOz0G-0000iz-Lc@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3442 to
the coreboot source repository and caused the following 
changes:

Change Log:
fix warnings, make mptable struct members explicitly packed, as they're
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3442&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3442&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3442&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3442&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  1 20:15:34 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 Aug 2008 20:15:34 +0200
Subject: [coreboot] [PATCH] [RFC] v3: CS5536 cleanup
In-Reply-To: <4876558B.4030704@gmx.net>
References: <48205A47.5060403@gmx.net>
	<4822458B.4030506@gmx.net>	<486D6181.8070502@gmx.net>
	<48755BC9.5010304@gmx.net> <48762134.5010803@coresystems.de>
	<4876558B.4030704@gmx.net>
Message-ID: <489352C6.9090206@gmx.net>

Ping?

Regards,
Carl-Daniel

On 10.07.2008 20:31, Carl-Daniel Hailfinger wrote:
> On 10.07.2008 16:48, Stefan Reinauer wrote:
>   
>> Carl-Daniel Hailfinger wrote:
>>   
>>     
>>> On 04.07.2008 01:32, Carl-Daniel Hailfinger wrote:
>>>   
>>>     
>>>       
>>>> - Improve VPCI hiding debug message and add doxygen comments.
>>>> - Replace a hand-crafted open-coded VPCI hiding sequence.
>>>>
>>>> Build tested on all relevant targets.
>>>>
>>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>>
>>>>       
>>>>         
>>> And as attachment for Ron.
>>>     
>>>       
>> I suggest using pci_write_config32 to register 0x7C, because that is
>> exactly what this does.
>>   
>>     
>
> The one call I converted is the only one which does not use register
> 0x7C. All other calls will be using a to-be written function which takes
> a struct device * and uses pci_write_config32. Besides that, as long as
> we offer the unwanted_vpci array in the dts, the function in my patch is
> essential.
>
> If there are workable alternatives, I'd like to hear about them.
>
> Regards,
> Carl-Daniel
>   

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From rminnich at gmail.com  Fri Aug  1 20:30:04 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 11:30:04 -0700
Subject: [coreboot] [PATCH] [RFC] v3: CS5536 cleanup
In-Reply-To: <489352C6.9090206@gmx.net>
References: <48205A47.5060403@gmx.net> <4822458B.4030506@gmx.net>
	<486D6181.8070502@gmx.net> <48755BC9.5010304@gmx.net>
	<48762134.5010803@coresystems.de> <4876558B.4030704@gmx.net>
	<489352C6.9090206@gmx.net>
Message-ID: <13426df10808011130p14a3b1aep57bf79dbbc1b3822@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

recommend you get ward to test it as well on his alix.

ron



From info at coresystems.de  Fri Aug  1 20:51:18 2008
From: info at coresystems.de (coreboot information)
Date: Fri, 01 Aug 2008 20:51:18 +0200
Subject: [coreboot] r3443 build service
Message-ID: <E1KOzig-0004ky-5M@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3443 to
the coreboot source repository and caused the following 
changes:

Change Log:
clean up Config.lb in lib/ (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3443&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3443&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3443&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3443&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Fri Aug  1 20:52:53 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 11:52:53 -0700
Subject: [coreboot] patch: first cut at amd/k8/initram.c
Message-ID: <13426df10808011152j4926e36csa642c068c7b39fa8@mail.gmail.com>


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From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  1 20:55:40 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 Aug 2008 20:55:40 +0200
Subject: [coreboot] [PATCH] v3: verbose GeodeLX register printing
Message-ID: <48935C2C.2050204@gmx.net>

The Geode LX RAMinit code already has textual register names in the
debug routine. Use them for printout.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c
===================================================================
--- LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Revision 707)
+++ LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Arbeitskopie)
@@ -41,7 +41,6 @@
  * compare to a factory BIOS setting.
  * @param level printk level
  */
-
 void dumplxmsrs(void)
 {
 	const static unsigned long msrs[] = {
@@ -64,13 +63,15 @@
 	};
 	int i;
 
-	for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){
+	for (i = 0; i < ARRAY_SIZE(msrs); i++) {
 		struct msr msr;
 		msr = rdmsr(msrs[i]);
-		printk(BIOS_DEBUG, "(%lx): %x.%x\n",  msrs[i], msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s (%lx): %x.%x\n",  msrnames[i], msrs[i],
+			msr.hi, msr.lo);
 	}
 
 }
+
 /**
  * Halt and Catch Fire. Print an error, then loop, sending NULLs on
  * serial port, to ensure the message is visible.


-- 
http://www.hailfinger.org/




From peter at stuge.se  Fri Aug  1 21:02:46 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 Aug 2008 21:02:46 +0200
Subject: [coreboot] [PATCH] v3: verbose GeodeLX register printing
In-Reply-To: <48935C2C.2050204@gmx.net>
References: <48935C2C.2050204@gmx.net>
Message-ID: <20080801190246.9968.qmail@stuge.se>

On Fri, Aug 01, 2008 at 08:55:40PM +0200, Carl-Daniel Hailfinger wrote:
> The Geode LX RAMinit code already has textual register names in the
> debug routine. Use them for printout.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Sure.

Acked-by: Peter Stuge <peter at stuge.se>


> Index: LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c
> ===================================================================
> --- LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Revision 707)
> +++ LinuxBIOSv3-dbe62/northbridge/amd/geodelx/raminit.c	(Arbeitskopie)
> @@ -41,7 +41,6 @@
>   * compare to a factory BIOS setting.
>   * @param level printk level
>   */
> -
>  void dumplxmsrs(void)
>  {
>  	const static unsigned long msrs[] = {
> @@ -64,13 +63,15 @@
>  	};
>  	int i;
>  
> -	for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){
> +	for (i = 0; i < ARRAY_SIZE(msrs); i++) {
>  		struct msr msr;
>  		msr = rdmsr(msrs[i]);
> -		printk(BIOS_DEBUG, "(%lx): %x.%x\n",  msrs[i], msr.hi, msr.lo);
> +		printk(BIOS_DEBUG, "%s (%lx): %x.%x\n",  msrnames[i], msrs[i],
> +			msr.hi, msr.lo);
>  	}
>  
>  }
> +
>  /**
>   * Halt and Catch Fire. Print an error, then loop, sending NULLs on
>   * serial port, to ensure the message is visible.



From svn at coreboot.org  Fri Aug  1 21:22:35 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 21:22:35 +0200
Subject: [coreboot] r3461 - in trunk/coreboot-v2/src/mainboard: agami/aruma
	amd/serengeti_cheetah amd/serengeti_cheetah_fam10
	iwill/dk8_htx via/epia-m
Message-ID: <mailman.1755.1355071348.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-01 21:22:34 +0200 (Fri, 01 Aug 2008)
New Revision: 3461

Modified:
   trunk/coreboot-v2/src/mainboard/agami/aruma/fadt.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/fadt.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/fadt.c
   trunk/coreboot-v2/src/mainboard/via/epia-m/fadt.c
Log:
oops, forgot these in the cleanup..  (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/fadt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/agami/aruma/fadt.c	2008-08-01 13:08:33 UTC (rev 3460)
+++ trunk/coreboot-v2/src/mainboard/agami/aruma/fadt.c	2008-08-01 19:22:34 UTC (rev 3461)
@@ -22,13 +22,13 @@
 	header->length = 244;
 	header->revision = 1;
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "LXBACPI ", 8);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = 0;
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;
-	fadt->res1 = 0x0;
+
 	// 3=Workstation,4=Enterprise Server, 7=Performance Server
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/fadt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/fadt.c	2008-08-01 13:08:33 UTC (rev 3460)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/fadt.c	2008-08-01 19:22:34 UTC (rev 3461)
@@ -21,13 +21,12 @@
 	header->length = 244;
 	header->revision = 1;
 	memcpy(header->oem_id,OEM_ID,6);
-	memcpy(header->oem_table_id,"LXBACPI ",8);
+	memcpy(header->oem_table_id,"COREBOOT",8);
 	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
 	fadt->firmware_ctrl=(u32)facs;
 	fadt->dsdt= (u32)dsdt;
-	fadt->res1=0x0;
 	// 3=Workstation,4=Enterprise Server, 7=Performance Server
 	fadt->preferred_pm_profile=0x03;
 	fadt->sci_int=9;

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c	2008-08-01 13:08:33 UTC (rev 3460)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c	2008-08-01 19:22:34 UTC (rev 3461)
@@ -42,13 +42,12 @@
 	header->length = 244;
 	header->revision = 1;
 	memcpy(header->oem_id,OEM_ID,6);
-	memcpy(header->oem_table_id,"LXBACPI ",8);
+	memcpy(header->oem_table_id,"COREBOOT",8);
 	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
 	fadt->firmware_ctrl=(u32)facs;
 	fadt->dsdt= (u32)dsdt;
-	fadt->res1=0x0;
 	// 3=Workstation,4=Enterprise Server, 7=Performance Server
 	fadt->preferred_pm_profile=0x03;
 	fadt->sci_int=9;

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/fadt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/fadt.c	2008-08-01 13:08:33 UTC (rev 3460)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/fadt.c	2008-08-01 19:22:34 UTC (rev 3461)
@@ -21,13 +21,12 @@
 	header->length = 244;
 	header->revision = 1;
 	memcpy(header->oem_id,OEM_ID,6);
-	memcpy(header->oem_table_id,"LXBACPI ",8);
+	memcpy(header->oem_table_id,"COREBOOT",8);
 	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
 	fadt->firmware_ctrl=(u32)facs;
 	fadt->dsdt= (u32)dsdt;
-	fadt->res1=0x0;
 	// 3=Workstation,4=Enterprise Server, 7=Performance Server
 	fadt->preferred_pm_profile=0x03;
 	fadt->sci_int=9;

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/fadt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m/fadt.c	2008-08-01 13:08:33 UTC (rev 3460)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m/fadt.c	2008-08-01 19:22:34 UTC (rev 3461)
@@ -30,9 +30,9 @@
 	memcpy(header->signature,"FACP",4);
 	header->length = 244;
 	header->revision = 1;
-	memcpy(header->oem_id,"LXBIOS",6);
-	memcpy(header->oem_table_id,"LXBACPI ",8);
-	memcpy(header->asl_compiler_id,"LXB",8);
+	memcpy(header->oem_id,OEM_ID,6);
+	memcpy(header->oem_table_id,"COREBOOT",8);
+	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
 	fadt->firmware_ctrl=facs;




From info at coresystems.de  Fri Aug  1 21:32:00 2008
From: info at coresystems.de (coreboot information)
Date: Fri, 01 Aug 2008 21:32:00 +0200
Subject: [coreboot] r3444 build service
Message-ID: <E1KP0M4-0007LT-Hv@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3444 to
the coreboot source repository and caused the following 
changes:

Change Log:
clean up comment in onboard.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3444&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3444&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3444&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3444&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Aug  1 21:39:14 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 Aug 2008 21:39:14 +0200
Subject: [coreboot] r708 - coreboot-v3/northbridge/amd/geodelx
Message-ID: <mailman.1756.1355071348.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-08-01 21:39:13 +0200 (Fri, 01 Aug 2008)
New Revision: 708

Modified:
   coreboot-v3/northbridge/amd/geodelx/raminit.c
Log:
The Geode LX RAMinit code already has textual register names in the
debug routine. Use them for printout.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-08-01 18:03:18 UTC (rev 707)
+++ coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-08-01 19:39:13 UTC (rev 708)
@@ -41,7 +41,6 @@
  * compare to a factory BIOS setting.
  * @param level printk level
  */
-
 void dumplxmsrs(void)
 {
 	const static unsigned long msrs[] = {
@@ -64,13 +63,15 @@
 	};
 	int i;
 
-	for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){
+	for (i = 0; i < ARRAY_SIZE(msrs); i++) {
 		struct msr msr;
 		msr = rdmsr(msrs[i]);
-		printk(BIOS_DEBUG, "(%lx): %x.%x\n",  msrs[i], msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s (%lx): %x.%x\n",  msrnames[i], msrs[i],
+			msr.hi, msr.lo);
 	}
 
 }
+
 /**
  * Halt and Catch Fire. Print an error, then loop, sending NULLs on
  * serial port, to ensure the message is visible.




From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  1 21:40:09 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 Aug 2008 21:40:09 +0200
Subject: [coreboot] [PATCH] v3: verbose GeodeLX register printing
In-Reply-To: <20080801190246.9968.qmail@stuge.se>
References: <48935C2C.2050204@gmx.net> <20080801190246.9968.qmail@stuge.se>
Message-ID: <48936699.3040809@gmx.net>

On 01.08.2008 21:02, Peter Stuge wrote:
> On Fri, Aug 01, 2008 at 08:55:40PM +0200, Carl-Daniel Hailfinger wrote:
>   
>> The Geode LX RAMinit code already has textual register names in the
>> debug routine. Use them for printout.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> Sure.
>
> Acked-by: Peter Stuge <peter at stuge.se>
>   

Thanks, r708.

Regards,
Carl-Daniel



From info at coresystems.de  Fri Aug  1 22:08:39 2008
From: info at coresystems.de (coreboot information)
Date: Fri, 01 Aug 2008 22:08:39 +0200
Subject: [coreboot] r3445 build service
Message-ID: <E1KP0vX-0000DE-Bg@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3445 to
the coreboot source repository and caused the following 
changes:

Change Log:
fix typo in commend of generic_sdram.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3445&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3445&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3445&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3445&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Fri Aug  1 23:19:42 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 Aug 2008 23:19:42 +0200
Subject: [coreboot] lzma validity checker
Message-ID: <48937DEE.9070509@gmx.net>

Untested. Needs lzmadecode.c from coreboot v3.

Regards,
Carl-Daniel


/* 

Coreboot interface to memory-saving variant of LZMA decoder

(C)opyright 2006 Carl-Daniel Hailfinger
Released under the GNU GPL v2 or later

Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA
SDK 4.42, which is written and distributed to public domain by Igor Pavlov.

*/

#include "lzmadecode.c"

#define LZMA_SCRATCHPAD_SIZE 15980

int lzma_check(u8 *src)
{
	unsigned char properties[LZMA_PROPERTIES_SIZE];
	UInt32 outSize;
	SizeT inProcessed;
	SizeT outProcessed;
	int res;
	CLzmaDecoderState state;
	SizeT mallocneeds;
	unsigned char scratchpad[LZMA_SCRATCHPAD_SIZE];
	char *dst;

	memcpy(properties, src, LZMA_PROPERTIES_SIZE);
	outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
	dst = malloc(outSize);
	if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
		printf("Incorrect stream properties\n");
		return -1;
	}
	mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
	if (mallocneeds > LZMA_SCRATCHPAD_SIZE) {
		printf("Decoder scratchpad too small, have %i, need %i!\n",
				LZMA_SCRATCHPAD_SIZE, mallocneeds);
		return -1;
	}
	state.Probs = (CProb *)scratchpad;
	res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed,
		dst, outSize, &outProcessed);
	if (res != 0) {
		printf("Decoding error = %d\n", res);
		return -1;
	}
	return 0;
}


-- 
http://www.hailfinger.org/




From info at coresystems.de  Fri Aug  1 23:59:32 2008
From: info at coresystems.de (coreboot information)
Date: Fri, 01 Aug 2008 23:59:32 +0200
Subject: [coreboot] r3446 build service
Message-ID: <E1KP2eq-0000Xm-Sb@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3446 to
the coreboot source repository and caused the following 
changes:

Change Log:
fix typo in coreboot_ram.ld comment (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3446&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3446&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3446&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3446&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Aug  2 00:40:33 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 00:40:33 +0200
Subject: [coreboot] r3447 build service
Message-ID: <E1KP3IX-0002OI-FG@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3447 to
the coreboot source repository and caused the following 
changes:

Change Log:
fix warning in vga console code (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3447&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3447&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3447&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3447&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Aug  2 01:19:07 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 01:19:07 +0200
Subject: [coreboot] r709 - in coreboot-v3: arch/x86/amd
	mainboard/gigabyte/m57sli
Message-ID: <mailman.1757.1355071348.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-08-02 01:19:05 +0200 (Sat, 02 Aug 2008)
New Revision: 709

Modified:
   coreboot-v3/arch/x86/amd/stage0.S
   coreboot-v3/mainboard/gigabyte/m57sli/initram.c
Log:
v3: Fix up amd_k8.h -> amd/k8/k8.h includes after the previous svn mv

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/arch/x86/amd/stage0.S
===================================================================
--- coreboot-v3/arch/x86/amd/stage0.S	2008-08-01 19:39:13 UTC (rev 708)
+++ coreboot-v3/arch/x86/amd/stage0.S	2008-08-01 23:19:05 UTC (rev 709)
@@ -31,7 +31,7 @@
 #endif
 
 #include <mtrr.h>
-#include <amd_k8.h>
+#include <amd/k8/k8.h>
 
 	.code16
 	.globl _stage0

Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/initram.c	2008-08-01 19:39:13 UTC (rev 708)
+++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c	2008-08-01 23:19:05 UTC (rev 709)
@@ -29,7 +29,7 @@
 #include <string.h>
 #include <msr.h>
 #include <io.h>
-#include <amd_k8.h>
+#include <amd/k8/k8.h>
 #include <spd.h>
 
 /** 




From info at coresystems.de  Sat Aug  2 01:21:36 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 01:21:36 +0200
Subject: [coreboot] r3448 build service
Message-ID: <E1KP3wG-0003uQ-KE@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3448 to
the coreboot source repository and caused the following 
changes:

Change Log:
function prototypes don't need extern. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3448&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3448&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3448&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3448&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Sat Aug  2 01:38:22 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 16:38:22 -0700
Subject: [coreboot] [PATCH] v3: verbose GeodeLX register printing
In-Reply-To: <48936699.3040809@gmx.net>
References: <48935C2C.2050204@gmx.net> <20080801190246.9968.qmail@stuge.se>
	<48936699.3040809@gmx.net>
Message-ID: <13426df10808011638p72c52685ic2292a0df0b73389@mail.gmail.com>

The reason I did not print them is that it blew the machine up every time.

Please, someone, test this soon.

ron



From info at coresystems.de  Sat Aug  2 02:01:48 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 02:01:48 +0200
Subject: [coreboot] r3449 build service
Message-ID: <E1KP4ZA-0005Te-7D@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3449 to
the coreboot source repository and caused the following 
changes:

Change Log:
add some SPD values from specs. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3449&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3449&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3449&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3449&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Sat Aug  2 02:07:20 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 17:07:20 -0700
Subject: [coreboot] patch: compilable raminit.c
Message-ID: <13426df10808011707h291b9c4dyc6269f227c34aae5@mail.gmail.com>

but it needs more love.

drivers welcome.

ron
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From info at coresystems.de  Sat Aug  2 02:38:53 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 02:38:53 +0200
Subject: [coreboot] r3450 build service
Message-ID: <E1KP593-0006Vh-Np@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3450 to
the coreboot source repository and caused the following 
changes:

Change Log:
fix compile warnings of rom_stream.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3450&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3450&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3450&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3450&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Aug  2 03:44:28 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 03:44:28 +0200
Subject: [coreboot] r710 - coreboot-v3/arch/x86
Message-ID: <mailman.1758.1355071348.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-08-02 03:44:27 +0200 (Sat, 02 Aug 2008)
New Revision: 710

Modified:
   coreboot-v3/arch/x86/stage1.c
Log:
v3: Remove compiler warning about unused variable by only declaring when used

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/arch/x86/stage1.c
===================================================================
--- coreboot-v3/arch/x86/stage1.c	2008-08-01 23:19:05 UTC (rev 709)
+++ coreboot-v3/arch/x86/stage1.c	2008-08-02 01:44:27 UTC (rev 710)
@@ -114,8 +114,9 @@
 void __attribute__((stdcall)) stage1_main(u32 bist)
 {
 	int ret;
-	struct mem_file archive, result;
+	struct mem_file archive;
 #ifdef CONFIG_PAYLOAD_ELF_LOADER
+	struct mem_file result;
 	int elfboot_mem(struct lb_memory *mem, void *where, int size);
 #endif /* CONFIG_PAYLOAD_ELF_LOADER */
 	void *entry;




From svn at coreboot.org  Sat Aug  2 03:45:04 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 03:45:04 +0200
Subject: [coreboot] r711 - in coreboot-v3/arch/x86: . amd/k8
Message-ID: <mailman.1759.1355071348.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-08-02 03:45:04 +0200 (Sat, 02 Aug 2008)
New Revision: 711

Modified:
   coreboot-v3/arch/x86/Makefile
   coreboot-v3/arch/x86/amd/k8/stage1.c
Log:
v3: More amdk8 -> amd/k8 fixups

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-08-02 01:44:27 UTC (rev 710)
+++ coreboot-v3/arch/x86/Makefile	2008-08-02 01:45:04 UTC (rev 711)
@@ -126,7 +126,7 @@
 else
 ifeq ($(CONFIG_CPU_AMD_K8),y)
 	STAGE0_CAR_OBJ = amd/stage0.o
-	STAGE0_ARCH_X86_OBJ += amdk8/stage1.o
+	STAGE0_ARCH_X86_OBJ += amd/k8/stage1.o
 endif
 endif
 endif

Modified: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-02 01:44:27 UTC (rev 710)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-02 01:45:04 UTC (rev 711)
@@ -22,7 +22,7 @@
 #include <lib.h>
 #include <console.h>
 #include <msr.h>
-#include <amd_k8.h>
+#include <amd/k8/k8.h>
 
 /**
  * Disable Cache As RAM (CAR) after memory is setup.




From info at coresystems.de  Sat Aug  2 04:21:56 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 04:21:56 +0200
Subject: [coreboot] r3451 build service
Message-ID: <E1KP6km-0005wS-12@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3451 to
the coreboot source repository and caused the following 
changes:

Change Log:
coding style fixes (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3451&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3451&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3451&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3451&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Aug  2 04:55:07 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 04:55:07 +0200
Subject: [coreboot] r3452 build service
Message-ID: <E1KP7Gt-0006qb-CT@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3452 to
the coreboot source repository and caused the following 
changes:

Change Log:
drop unused code (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3452&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3452&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3452&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3452&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Sat Aug  2 05:09:31 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 05:09:31 +0200
Subject: [coreboot] v3: Port ITE IT8716F superio code from v2
Message-ID: <20080802030931.6445.qmail@stuge.se>

This is rather simple, but should work.

I don't think this code is really complete in v2, and the v3 port is
just changed to fit v3, nothing has been added.


//Peter
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From peter at stuge.se  Sat Aug  2 05:18:41 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 05:18:41 +0200
Subject: [coreboot] patch: v3.k8.wip1
In-Reply-To: <13426df10808011707h291b9c4dyc6269f227c34aae5@mail.gmail.com>
References: <13426df10808011707h291b9c4dyc6269f227c34aae5@mail.gmail.com>
Message-ID: <20080802031842.9236.qmail@stuge.se>

This is my current tree, it applies on top of v3.it8716f.patch.

Ron, sorry, but k8/raminit.c does not compile at all. Lots of fixes are still
needed to have it fit into v3. I've gone through about 1/8 of the file, it
errors out on line 576 for me now.

The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.

Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually have the first successful k8 build. :)


If we are going to do more of this intensive coop development it
might be a good idea use some temporary git repos if everyone can
work with that easily. It would be fine for me, and it would be nice
to not have to send these big patches back and forth. But unless
everyone can do it easily I don't think we should bother. Let's focus
on k8 here. :)


//Peter
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From rminnich at gmail.com  Sat Aug  2 05:22:23 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 20:22:23 -0700
Subject: [coreboot] v3: Port ITE IT8716F superio code from v2
In-Reply-To: <20080802030931.6445.qmail@stuge.se>
References: <20080802030931.6445.qmail@stuge.se>
Message-ID: <13426df10808012022p542fa059t10f9656e22f2eb27@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

many thanks.

ron



From rminnich at gmail.com  Sat Aug  2 05:24:36 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 20:24:36 -0700
Subject: [coreboot] patch: v3.k8.wip1
In-Reply-To: <20080802031842.9236.qmail@stuge.se>
References: <13426df10808011707h291b9c4dyc6269f227c34aae5@mail.gmail.com>
	<20080802031842.9236.qmail@stuge.se>
Message-ID: <13426df10808012024u30620c01gf523219195e3df9f@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

let's not revisit the SCM issue for now :-)

ron



From svn at coreboot.org  Sat Aug  2 05:29:04 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 05:29:04 +0200
Subject: [coreboot] r712 - in coreboot-v3: . superio superio/ite
	superio/ite/it8716f
Message-ID: <mailman.1760.1355071348.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-08-02 05:29:02 +0200 (Sat, 02 Aug 2008)
New Revision: 712

Added:
   coreboot-v3/superio/ite/
   coreboot-v3/superio/ite/it8716f/
   coreboot-v3/superio/ite/it8716f/Makefile
   coreboot-v3/superio/ite/it8716f/dts
   coreboot-v3/superio/ite/it8716f/it8716f.h
   coreboot-v3/superio/ite/it8716f/stage1.c
   coreboot-v3/superio/ite/it8716f/superio.c
Modified:
   coreboot-v3/Kconfig
Log:
v3: Port ITE IT8716F superio code from v2

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig	2008-08-02 01:45:04 UTC (rev 711)
+++ coreboot-v3/Kconfig	2008-08-02 03:29:02 UTC (rev 712)
@@ -86,6 +86,8 @@
 	boolean
 config SUPERIO_FINTEK_F71805F
 	boolean
+config SUPERIO_ITE_IT8716F
+	boolean
 
 # Source all northbridge/southbridge/superio Kconfig files:
 source northbridge/intel/i440bxemulation/Kconfig

Added: coreboot-v3/superio/ite/it8716f/Makefile
===================================================================
--- coreboot-v3/superio/ite/it8716f/Makefile	                        (rev 0)
+++ coreboot-v3/superio/ite/it8716f/Makefile	2008-08-02 03:29:02 UTC (rev 712)
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Peter Stuge <peter at stuge.se>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ifeq ($(CONFIG_SUPERIO_ITE_IT8716F),y)
+
+STAGE0_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/stage1.o
+STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
+
+# Always add to variables, as there could be more than one Super I/O.
+STAGE2_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/superio.o
+
+endif

Added: coreboot-v3/superio/ite/it8716f/dts
===================================================================
--- coreboot-v3/superio/ite/it8716f/dts	                        (rev 0)
+++ coreboot-v3/superio/ite/it8716f/dts	2008-08-02 03:29:02 UTC (rev 712)
@@ -0,0 +1,80 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Peter Stuge <peter at stuge.se>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+{
+	/* Floppy */
+	floppydev = "0x0";
+	floppyenable = "0";
+	floppyio = "0x3f0";
+	floppyirq = "0x60";
+	floppydrq = "0x02";
+
+	/* COM1 */
+	com1dev = "1";
+	com1enable = "0";
+	com1io = "0x3f8";
+	com1irq = "4";
+
+	/* COM2 */
+	com2dev = "2";
+	com2enable = "0";
+	com2io = "0x2f8";
+	com2irq = "3";
+
+	/* Parallel port */
+	ppdev = "3";
+	ppenable = "0";
+	ppio = "0x378";
+	ppirq = "7";
+
+	/* Environment controller */
+	ecdev = "4";
+	ecenable = "0";
+
+	/* Keyboard */
+	kbdev = "5";
+	kbenable = "0";
+	kbio = "0x60";
+	kbio2 = "0x62";
+	kbirq = "1";
+	kbirq2 = "12";
+
+	/* Mouse */
+	mousedev = "6";
+	mouseenable = "0";
+
+	/* GPIO */
+	gpiodev = "7";
+	gpioenable = "0";
+
+	/* MIDI port */
+	mididev = "8";
+	midienable = "0";
+
+	/* Game port */
+	gamedev = "9";
+	gameenable = "0";
+	gameio = "0x220";
+	gameio2 = "0x400";
+	gameirq = "9";
+
+	/* Consumer IR */
+	cirdev = "0xa";
+	cirenable = "0";
+};

Added: coreboot-v3/superio/ite/it8716f/it8716f.h
===================================================================
--- coreboot-v3/superio/ite/it8716f/it8716f.h	                        (rev 0)
+++ coreboot-v3/superio/ite/it8716f/it8716f.h	2008-08-02 03:29:02 UTC (rev 712)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2008 Peter Stuge <peter at stuge.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
+/* Status: Untested on real hardware, but it compiles. */
+
+#ifndef SUPERIO_ITE_IT8716F_IT8716F_H
+#define SUPERIO_ITE_IT8716F_IT8716F_H
+
+#define IT8716F_FDC  0x00 /* Floppy */
+#define IT8716F_SP1  0x01 /* Com1 */
+#define IT8716F_SP2  0x02 /* Com2 */
+#define IT8716F_PP   0x03 /* Parallel port */
+#define IT8716F_EC   0x04 /* Environment controller */
+#define IT8716F_KBCK 0x05 /* Keyboard */
+#define IT8716F_KBCM 0x06 /* Mouse */
+#define IT8716F_GPIO 0x07 /* GPIO */
+#define IT8716F_MIDI 0x08 /* MIDI port */
+#define IT8716F_GAME 0x09 /* GAME port */
+#define IT8716F_IR   0x0a /* Consumer IR */
+
+#endif /* SUPERIO_ITE_IT8716F_IT8716F_H */

Added: coreboot-v3/superio/ite/it8716f/stage1.c
===================================================================
--- coreboot-v3/superio/ite/it8716f/stage1.c	                        (rev 0)
+++ coreboot-v3/superio/ite/it8716f/stage1.c	2008-08-02 03:29:02 UTC (rev 712)
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ * Copyright (C) 2008 Peter Stuge <peter at stuge.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <io.h>
+#include <device/pnp.h>
+#include "it8716f.h"
+
+static void enter_ext(u8 dev)
+{
+	outb(0x87, dev);
+	outb(0x01, dev);
+	outb(0x55, dev);
+	outb(0x4e == dev ? 0xaa : 0x55, dev);
+}
+
+void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase)
+{
+	enter_ext(dev);
+	rawpnp_set_logical_device(dev, serial);
+	rawpnp_set_enable(dev, 0);
+	rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	rawpnp_set_enable(dev, 1);
+	rawpnp_write_config(dev, 0x02, 0x02);
+}

Added: coreboot-v3/superio/ite/it8716f/superio.c
===================================================================
--- coreboot-v3/superio/ite/it8716f/superio.c	                        (rev 0)
+++ coreboot-v3/superio/ite/it8716f/superio.c	2008-08-02 03:29:02 UTC (rev 712)
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2007 AMD
+ * (Written by Yinghai Lu <yinghai.lu at amd.com> for AMD)
+ * Copyright (C) 2007 Ward Vandewege <ward at gnu.org>
+ * Copyright (C) 2008 Peter Stuge <peter at stuge.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <io.h>
+#include <lib.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console.h>
+#include <string.h>
+#include <uart8250.h>
+#include <keyboard.h>
+#include <statictree.h>
+#include "it8716f.h"
+
+/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+static void pnp_enter_ext_func_mode(struct device *dev)
+{
+	outb(0x87, dev->path.u.pnp.port);
+	outb(0x01, dev->path.u.pnp.port);
+	outb(0x55, dev->path.u.pnp.port);
+
+	if (dev->path.u.pnp.port == 0x4e) {
+		outb(0xaa, dev->path.u.pnp.port);
+	} else {
+		outb(0x55, dev->path.u.pnp.port);
+	}
+}
+
+static void pnp_exit_ext_func_mode(struct device *dev)
+{
+	pnp_write_config(dev, 0x02, 0x02);
+}
+
+#ifdef HAVE_FANCTL
+extern void init_ec(u16 base);
+#else
+static void pnp_write_index(u16 port_base, u8 reg, u8 value)
+{
+	outb(reg, port_base);
+	outb(value, port_base + 1);
+}
+
+static u8 pnp_read_index(u16 port_base, u8 reg)
+{
+	outb(reg, port_base);
+	return inb(port_base + 1);
+}
+
+static void init_ec(u16 base)
+{
+	u8 value;
+
+	/* Read out current value of FAN_CTL control register (0x14). */
+	value = pnp_read_index(base, 0x14);
+	printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
+		     base + 0x14, value);
+
+	/* Set FAN_CTL control register (0x14) polarity to high, and
+	   activate fans 1, 2 and 3. */
+	pnp_write_index(base, 0x14, value | 0x87);
+	printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
+		     base + 0x14, value | 0x87);
+}
+#endif
+
+
+static void it8716f_pnp_set_resources(struct device *dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_resources(dev);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static void it8716f_pnp_enable_disable(struct device *dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static void it8716f_pnp_enable_resources(struct device *dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, dev->enabled);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static struct device_operations ops;
+static struct pnp_info pnp_dev_info[] = {
+	{&ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
+	{&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
+	{&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
+	{&ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
+	{&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
+	 {0x7f8, 0x4},},
+	{&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
+	 {0x7ff, 0x4},},
+	{&ops, IT8716F_KBCM, PNP_IRQ0,},
+	{&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
+	{&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
+	{&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
+	{&ops, IT8716F_IR,},
+};
+
+static void it8716f_setup_scan_bus(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+static void it8716f_init(struct device *dev)
+{
+	struct superio_ite_it8716f_dts_config *conf;
+	struct resource *res0, *res1;
+	struct pc_keyboard kbd;
+
+	if (!dev->enabled)
+		return;
+
+	conf = dev->device_configuration;
+
+	/* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */
+	switch (dev->path.u.pnp.device) {
+	case IT8716F_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+//		init_uart8250(res0->base, &conf->com1);
+		break;
+	case IT8716F_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+//		init_uart8250(res0->base, &conf->com2);
+		break;
+	case IT8716F_EC:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+#define EC_INDEX_PORT 5
+		init_ec(res0->base + EC_INDEX_PORT);
+		break;
+	case IT8716F_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &kbd);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.phase2_setup_scan_bus	 = it8716f_setup_scan_bus,
+	.phase4_read_resources	 = pnp_read_resources,
+	.phase4_set_resources	 = it8716f_pnp_set_resources,
+	.phase4_enable_disable	 = it8716f_pnp_enable_disable,
+	.phase5_enable_resources = it8716f_pnp_enable_resources,
+	.phase6_init		 = it8716f_init,
+};




From peter at stuge.se  Sat Aug  2 05:29:47 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 05:29:47 +0200
Subject: [coreboot] v3: Port ITE IT8716F superio code from v2
In-Reply-To: <13426df10808012022p542fa059t10f9656e22f2eb27@mail.gmail.com>
References: <20080802030931.6445.qmail@stuge.se>
	<13426df10808012022p542fa059t10f9656e22f2eb27@mail.gmail.com>
Message-ID: <20080802032947.12053.qmail@stuge.se>

On Fri, Aug 01, 2008 at 08:22:23PM -0700, ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

r712



From svn at coreboot.org  Sat Aug  2 05:34:05 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 05:34:05 +0200
Subject: [coreboot] r713 - in coreboot-v3: . arch/x86
	include/arch/x86/amd/k8 include/device mainboard/gigabyte
	mainboard/gigabyte/m57sli northbridge/amd/k8 southbridge
	southbridge/nvidia southbridge/nvidia/mcp55
Message-ID: <mailman.1761.1355071348.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-08-02 05:34:05 +0200 (Sat, 02 Aug 2008)
New Revision: 713

Added:
   coreboot-v3/include/arch/x86/amd/k8/raminit.h
   coreboot-v3/include/arch/x86/amd/k8/sysconf.h
   coreboot-v3/northbridge/amd/k8/Makefile
   coreboot-v3/northbridge/amd/k8/pci
   coreboot-v3/northbridge/amd/k8/raminit.c
   coreboot-v3/southbridge/nvidia/
   coreboot-v3/southbridge/nvidia/mcp55/
   coreboot-v3/southbridge/nvidia/mcp55/Makefile
   coreboot-v3/southbridge/nvidia/mcp55/dts
   coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
   coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
   coreboot-v3/southbridge/nvidia/mcp55/stage1.c
Modified:
   coreboot-v3/Kconfig
   coreboot-v3/arch/x86/Makefile
   coreboot-v3/include/arch/x86/amd/k8/k8.h
   coreboot-v3/include/device/pci_def.h
   coreboot-v3/include/device/pci_ids.h
   coreboot-v3/mainboard/gigabyte/Kconfig
   coreboot-v3/mainboard/gigabyte/m57sli/dts
Log:
v3: k8/m57sli wip1

This is not nearly complete, but just the current state of my tree.

k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.

The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.

Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig	2008-08-02 03:29:02 UTC (rev 712)
+++ coreboot-v3/Kconfig	2008-08-02 03:34:05 UTC (rev 713)
@@ -72,6 +72,8 @@
 # Northbridges:
 config NORTHBRIDGE_AMD_GEODELX
 	boolean
+config NORTHBRIDGE_AMD_K8
+	boolean
 config NORTHBRIDGE_INTEL_I440BXEMULATION
 	boolean
 
@@ -80,6 +82,8 @@
 	boolean
 config SOUTHBRIDGE_INTEL_I82371EB
 	boolean
+config SOUTHBRIDGE_NVIDIA_MCP55
+	boolean
 
 # Super I/Os:
 config SUPERIO_WINBOND_W83627HF

Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-08-02 03:29:02 UTC (rev 712)
+++ coreboot-v3/arch/x86/Makefile	2008-08-02 03:34:05 UTC (rev 713)
@@ -248,10 +248,13 @@
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
 
+
+# NOTE HACK. Stefan will fix this :-)
 $(obj)/arch/x86/amd/stage0.o: $(src)/arch/x86/amd/stage0.S
 	$(Q)mkdir -p $(dir $@)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
+		-I $(src)/include/arch/x86/amd/k8 \
 		-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
 		-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"

Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-08-02 03:29:02 UTC (rev 712)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-08-02 03:34:05 UTC (rev 713)
@@ -54,3 +54,231 @@
 #define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
 
 
+/* Definitions of various K8 registers */
+/* Function 0 */
+#define HT_TRANSACTION_CONTROL 0x68
+#define  HTTC_DIS_RD_B_P            (1 << 0)
+#define  HTTC_DIS_RD_DW_P           (1 << 1)
+#define  HTTC_DIS_WR_B_P            (1 << 2)
+#define  HTTC_DIS_WR_DW_P           (1 << 3)
+#define  HTTC_DIS_MTS               (1 << 4)
+#define  HTTC_CPU1_EN               (1 << 5)
+#define  HTTC_CPU_REQ_PASS_PW       (1 << 6)
+#define  HTTC_CPU_RD_RSP_PASS_PW    (1 << 7)
+#define  HTTC_DIS_P_MEM_C           (1 << 8)
+#define  HTTC_DIS_RMT_MEM_C         (1 << 9)
+#define  HTTC_DIS_FILL_P            (1 << 10)
+#define  HTTC_RSP_PASS_PW           (1 << 11)
+#define  HTTC_CHG_ISOC_TO_ORD       (1 << 12)
+#define  HTTC_BUF_REL_PRI_SHIFT     13
+#define  HTTC_BUF_REL_PRI_MASK      3
+#define   HTTC_BUF_REL_PRI_64       0
+#define   HTTC_BUF_REL_PRI_16       1
+#define   HTTC_BUF_REL_PRI_8        2
+#define   HTTC_BUF_REL_PRI_2        3
+#define  HTTC_LIMIT_CLDT_CFG        (1 << 15)
+#define  HTTC_LINT_EN               (1 << 16)
+#define  HTTC_APIC_EXT_BRD_CST      (1 << 17)
+#define  HTTC_APIC_EXT_ID           (1 << 18)
+#define  HTTC_APIC_EXT_SPUR         (1 << 19)
+#define  HTTC_SEQ_ID_SRC_NODE_EN    (1 << 20)
+#define  HTTC_DS_NP_REQ_LIMIT_SHIFT 21
+#define  HTTC_DS_NP_REQ_LIMIT_MASK  3
+#define   HTTC_DS_NP_REQ_LIMIT_NONE 0
+#define   HTTC_DS_NP_REQ_LIMIT_1    1
+#define   HTTC_DS_NP_REQ_LIMIT_4    2
+#define   HTTC_DS_NP_REQ_LIMIT_8    3
+#define  HTTC_MED_PRI_BYP_CNT_SHIFT 24
+#define  HTTC_MED_PRI_BYP_CNT_MASK  3
+#define  HTTC_HI_PRI_BYP_CNT_SHIFT  26
+#define  HTTC_HI_PRI_BYP_CNT_MASK   3
+
+
+/* Function 1 */
+#define PCI_IO_BASE0       0xc0
+#define PCI_IO_BASE1       0xc8
+#define PCI_IO_BASE2       0xd0
+#define PCI_IO_BASE3       0xd8
+#define PCI_IO_BASE_VGA_EN (1 << 4)
+#define PCI_IO_BASE_NO_ISA (1 << 5)
+
+
+/* Function 2 */
+#define DRAM_CSBASE	   0x40
+#define DRAM_CSMASK	   0x60
+#define DRAM_BANK_ADDR_MAP 0x80
+
+#define DRAM_TIMING_LOW	   0x88
+#define	 DTL_TCL_SHIFT	   0
+#define	 DTL_TCL_MASK	   0x7
+#define	  DTL_CL_2	   1
+#define	  DTL_CL_3	   2
+#define	  DTL_CL_2_5	   5
+#define	 DTL_TRC_SHIFT	   4
+#define	 DTL_TRC_MASK	   0xf
+#define	  DTL_TRC_BASE	   7
+#define	  DTL_TRC_MIN	   7
+#define	  DTL_TRC_MAX	   22
+#define	 DTL_TRFC_SHIFT	   8
+#define	 DTL_TRFC_MASK	   0xf
+#define	  DTL_TRFC_BASE	   9
+#define	  DTL_TRFC_MIN	   9
+#define	  DTL_TRFC_MAX	   24
+#define	 DTL_TRCD_SHIFT	   12
+#define	 DTL_TRCD_MASK	   0x7
+#define	  DTL_TRCD_BASE	   0
+#define	  DTL_TRCD_MIN	   2
+#define	  DTL_TRCD_MAX	   6
+#define	 DTL_TRRD_SHIFT	   16
+#define	 DTL_TRRD_MASK	   0x7
+#define	  DTL_TRRD_BASE	   0
+#define	  DTL_TRRD_MIN	   2
+#define	  DTL_TRRD_MAX	   4
+#define	 DTL_TRAS_SHIFT	   20
+#define	 DTL_TRAS_MASK	   0xf
+#define	  DTL_TRAS_BASE	   0
+#define	  DTL_TRAS_MIN	   5
+#define	  DTL_TRAS_MAX	   15
+#define	 DTL_TRP_SHIFT	   24
+#define	 DTL_TRP_MASK	   0x7
+#define	  DTL_TRP_BASE	   0
+#define	  DTL_TRP_MIN	   2
+#define	  DTL_TRP_MAX	   6
+#define	 DTL_TWR_SHIFT	   28
+#define	 DTL_TWR_MASK	   0x1
+#define	  DTL_TWR_BASE	   2
+#define	  DTL_TWR_MIN	   2
+#define	  DTL_TWR_MAX	   3
+
+#define DRAM_TIMING_HIGH   0x8c
+#define	 DTH_TWTR_SHIFT	   0
+#define	 DTH_TWTR_MASK	   0x1
+#define	  DTH_TWTR_BASE	   1
+#define	  DTH_TWTR_MIN	   1
+#define	  DTH_TWTR_MAX	   2
+#define	 DTH_TRWT_SHIFT	   4
+#define	 DTH_TRWT_MASK	   0x7
+#define	  DTH_TRWT_BASE	   1
+#define	  DTH_TRWT_MIN	   1
+#define	  DTH_TRWT_MAX	   6
+#define	 DTH_TREF_SHIFT	   8
+#define	 DTH_TREF_MASK	   0x1f
+#define	  DTH_TREF_100MHZ_4K 0x00
+#define	  DTH_TREF_133MHZ_4K 0x01
+#define	  DTH_TREF_166MHZ_4K 0x02
+#define	  DTH_TREF_200MHZ_4K 0x03
+#define	  DTH_TREF_100MHZ_8K 0x08
+#define	  DTH_TREF_133MHZ_8K 0x09
+#define	  DTH_TREF_166MHZ_8K 0x0A
+#define	  DTH_TREF_200MHZ_8K 0x0B
+#define	 DTH_TWCL_SHIFT	    20
+#define	 DTH_TWCL_MASK	    0x7
+#define	  DTH_TWCL_BASE	    1
+#define	  DTH_TWCL_MIN	    1
+#define	  DTH_TWCL_MAX	    2
+
+#define DRAM_CONFIG_LOW	   0x90
+#define	 DCL_DLL_Disable   (1<<0)
+#define	 DCL_D_DRV	   (1<<1)
+#define	 DCL_QFC_EN	   (1<<2)
+#define	 DCL_DisDqsHys	   (1<<3)
+#define	 DCL_Burst2Opt     (1<<5)
+#define	 DCL_DramInit	   (1<<8)
+#define	 DCL_DualDIMMen    (1<<9)
+#define	 DCL_DramEnable	   (1<<10)
+#define	 DCL_MemClrStatus  (1<<11)
+#define	 DCL_ESR	   (1<<12)
+#define	 DCL_SRS	   (1<<13)
+#define	 DCL_128BitEn	   (1<<16)
+#define	 DCL_DimmEccEn	   (1<<17)
+#define	 DCL_UnBufDimm	   (1<<18)
+#define	 DCL_32ByteEn	   (1<<19)
+#define	 DCL_x4DIMM_SHIFT  20
+#define	 DCL_DisInRcvrs    (1<<24)
+#define	 DCL_BypMax_SHIFT  25
+#define	 DCL_En2T          (1<<28)
+#define	 DCL_UpperCSMap    (1<<29)
+	
+#define DRAM_CONFIG_HIGH   0x94
+#define	 DCH_ASYNC_LAT_SHIFT  0
+#define	 DCH_ASYNC_LAT_MASK   0xf
+#define	  DCH_ASYNC_LAT_BASE  0
+#define	  DCH_ASYNC_LAT_MIN   0
+#define	  DCH_ASYNC_LAT_MAX   15
+#define	 DCH_RDPREAMBLE_SHIFT 8
+#define	 DCH_RDPREAMBLE_MASK  0xf
+#define	  DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
+#define	  DCH_RDPREAMBLE_MIN  ((2<<1)+0) /* 2.0 ns */
+#define	  DCH_RDPREAMBLE_MAX  ((9<<1)+1) /* 9.5 ns */
+#define	 DCH_IDLE_LIMIT_SHIFT 16
+#define	 DCH_IDLE_LIMIT_MASK  0x7
+#define	  DCH_IDLE_LIMIT_0    0
+#define	  DCH_IDLE_LIMIT_4    1
+#define	  DCH_IDLE_LIMIT_8    2
+#define	  DCH_IDLE_LIMIT_16   3
+#define	  DCH_IDLE_LIMIT_32   4
+#define	  DCH_IDLE_LIMIT_64   5
+#define	  DCH_IDLE_LIMIT_128  6
+#define	  DCH_IDLE_LIMIT_256  7
+#define	 DCH_DYN_IDLE_CTR_EN (1 << 19)
+#define	 DCH_MEMCLK_SHIFT     20
+#define	 DCH_MEMCLK_MASK      0x7
+#define	  DCH_MEMCLK_100MHZ   0
+#define	  DCH_MEMCLK_133MHZ   2
+#define	  DCH_MEMCLK_166MHZ   5
+#define	  DCH_MEMCLK_200MHZ   7
+#define	 DCH_MEMCLK_VALID     (1 << 25)
+#define	 DCH_MEMCLK_EN0	      (1 << 26) 
+#define	 DCH_MEMCLK_EN1	      (1 << 27) 
+#define	 DCH_MEMCLK_EN2	      (1 << 28) 
+#define	 DCH_MEMCLK_EN3	      (1 << 29) 
+
+/* Function 3 */
+#define MCA_NB_CONFIG      0x44
+#define   MNC_ECC_EN       (1 << 22)
+#define   MNC_CHIPKILL_EN  (1 << 23)
+#define SCRUB_CONTROL	   0x58
+#define	  SCRUB_NONE	    0
+#define	  SCRUB_40ns	    1
+#define	  SCRUB_80ns	    2
+#define	  SCRUB_160ns	    3
+#define	  SCRUB_320ns	    4
+#define	  SCRUB_640ns	    5
+#define	  SCRUB_1_28us	    6
+#define	  SCRUB_2_56us	    7
+#define	  SCRUB_5_12us	    8
+#define	  SCRUB_10_2us	    9
+#define	  SCRUB_20_5us	   10
+#define	  SCRUB_41_0us	   11
+#define	  SCRUB_81_9us	   12
+#define	  SCRUB_163_8us	   13
+#define	  SCRUB_327_7us	   14
+#define	  SCRUB_655_4us	   15
+#define	  SCRUB_1_31ms	   16
+#define	  SCRUB_2_62ms	   17
+#define	  SCRUB_5_24ms	   18 
+#define	  SCRUB_10_49ms	   19
+#define	  SCRUB_20_97ms	   20
+#define	  SCRUB_42ms	   21
+#define	  SCRUB_84ms	   22
+#define	 SC_DRAM_SCRUB_RATE_SHFIT  0
+#define	 SC_DRAM_SCRUB_RATE_MASK   0x1f
+#define	 SC_L2_SCRUB_RATE_SHIFT	   8
+#define	 SC_L2_SCRUB_RATE_MASK	   0x1f
+#define	 SC_L1D_SCRUB_RATE_SHIFT   16
+#define	 SC_L1D_SCRUB_RATE_MASK	   0x1f
+#define SCRUB_ADDR_LOW	   0x5C
+#define SCRUB_ADDR_HIGH	   0x60
+#define NORTHBRIDGE_CAP	   0xE8
+#define	 NBCAP_128Bit	      (1 << 0)
+#define	 NBCAP_MP	      (1 << 1)
+#define	 NBCAP_BIG_MP	      (1 << 2)
+#define	 NBCAP_ECC	      (1 << 3)
+#define	 NBCAP_CHIPKILL_ECC   (1 << 4)
+#define	 NBCAP_MEMCLK_SHIFT   5
+#define	 NBCAP_MEMCLK_MASK    3
+#define	 NBCAP_MEMCLK_100MHZ  3
+#define	 NBCAP_MEMCLK_133MHZ  2
+#define	 NBCAP_MEMCLK_166MHZ  1
+#define	 NBCAP_MEMCLK_200MHZ  0
+#define	 NBCAP_MEMCTRL	      (1 << 8)

Added: coreboot-v3/include/arch/x86/amd/k8/raminit.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/raminit.h	                        (rev 0)
+++ coreboot-v3/include/arch/x86/amd/k8/raminit.h	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,16 @@
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#include <device/device.h>
+
+#define NODE_NUMS 8
+
+#define DIMM_SOCKETS 4
+struct mem_controller {
+	unsigned node_id;
+	struct device *f0, *f1, *f2, *f3;
+	u16 channel0[DIMM_SOCKETS];
+	u16 channel1[DIMM_SOCKETS];
+};
+
+#endif /* RAMINIT_H */

Added: coreboot-v3/include/arch/x86/amd/k8/sysconf.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/sysconf.h	                        (rev 0)
+++ coreboot-v3/include/arch/x86/amd/k8/sysconf.h	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#ifndef AMD_K8_SYSCONF_H
+#define AMD_K8_SYSCONF_H
+
+#define HC_POSSIBLE_NUM 8
+
+struct amdk8_sysconf_t {
+	//ht
+	unsigned nodes;
+	unsigned hc_possible_num;
+	unsigned pci1234[HC_POSSIBLE_NUM];
+	unsigned hcdn[HC_POSSIBLE_NUM];
+	unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type
+	unsigned sbdn;
+	unsigned sblk;
+
+	unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234
+
+	int enabled_apic_ext_id;
+	unsigned lift_bsp_apicid;
+	int apicid_offset;
+
+	void *mb; // pointer for mb releated struct
+	
+};
+
+extern struct amdk8_sysconf_t sysconf;
+
+#endif

Modified: coreboot-v3/include/device/pci_def.h
===================================================================
--- coreboot-v3/include/device/pci_def.h	2008-08-02 03:29:02 UTC (rev 712)
+++ coreboot-v3/include/device/pci_def.h	2008-08-02 03:34:05 UTC (rev 713)
@@ -481,5 +481,6 @@
 #define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
 #define PCI_FUNC(devfn)		((devfn) & 0x07)
 #define PCI_BDF(bus,dev,func)	((bus) << 16 | (dev) << 11 | (func) << 8)
+#define PCI_ADDR(bus,dev,func,where) (PCI_BDF((bus),(dev),(func)) << 4 | (where & 0xfff))
 
 #endif /* DEVICE_PCI_DEF_H */

Modified: coreboot-v3/include/device/pci_ids.h
===================================================================
--- coreboot-v3/include/device/pci_ids.h	2008-08-02 03:29:02 UTC (rev 712)
+++ coreboot-v3/include/device/pci_ids.h	2008-08-02 03:34:05 UTC (rev 713)
@@ -155,4 +155,33 @@
 #define PCI_VENDOR_ID_CIRRUS			0x1013
 #define PCI_DEVICE_ID_CIRRUS_5446		0x00b8	/* Used by QEMU */
 
+#define PCI_VENDIR_ID_NVIDIA                    0x10de
+/*
+0360MCP55 LPC Bridge
+0361MCP55 LPC Bridge
+0362MCP55 LPC Bridge
+0363MCP55 LPC Bridge
+0364MCP55 LPC Bridge
+0365MCP55 LPC Bridge
+0366MCP55 LPC Bridge
+0367MCP55 LPC Bridge
+0368MCP55 SMBus
+0369MCP55 Memory Controller
+036aMCP55 Memory Controller
+036bMCP55 SMU
+036cMCP55 USB Controller
+036dMCP55 USB Controller
+036eMCP55 IDE
+0370MCP55 PCI bridge
+0371MCP55 High Definition Audio
+0372MCP55 Ethernet
+0373MCP55 Ethernet
+0374MCP55 PCI Express bridge
+0375MCP55 PCI Express bridge
+0376MCP55 PCI Express bridge
+0377MCP55 PCI Express bridge
+0378MCP55 PCI Express bridge
+037aMCP55 Memory Controller
+*/
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIBRIDGE 0x370
 #endif /* DEVICE_PCI_IDS_H */

Modified: coreboot-v3/mainboard/gigabyte/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/Kconfig	2008-08-02 03:29:02 UTC (rev 712)
+++ coreboot-v3/mainboard/gigabyte/Kconfig	2008-08-02 03:34:05 UTC (rev 713)
@@ -28,6 +28,9 @@
 	select ARCH_X86
 	select OPTION_TABLE
 	select CPU_AMD_K8
+	select NORTHBRIDGE_AMD_K8
+#	select SOUTHBRIDGE_NVIDIA_MCP55
+	select SUPERIO_ITE_IT8716F
 	help
 	  Gigabyte M57SLI
 

Modified: coreboot-v3/mainboard/gigabyte/m57sli/dts
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/dts	2008-08-02 03:29:02 UTC (rev 712)
+++ coreboot-v3/mainboard/gigabyte/m57sli/dts	2008-08-02 03:34:05 UTC (rev 713)
@@ -25,5 +25,8 @@
 	apic at 0 {
 	};
 	domain at 0 {
+		pci at 18,0 {
+			/config/("northbridge/amd/k8/pci");
+		};
 	};
 };

Added: coreboot-v3/northbridge/amd/k8/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/k8/Makefile	                        (rev 0)
+++ coreboot-v3/northbridge/amd/k8/Makefile	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
+
+STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/k8/raminit.o
+
+endif

Added: coreboot-v3/northbridge/amd/k8/pci
===================================================================
--- coreboot-v3/northbridge/amd/k8/pci	                        (rev 0)
+++ coreboot-v3/northbridge/amd/k8/pci	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "k8_ops";
+};

Added: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	                        (rev 0)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,4756 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
+ * Copyright (C) 2004 YingHai Lu
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+/*	This should be done by Eric
+	2004.11 yhlu add 4 rank DIMM support
+	2004.12 yhlu add D0 support
+	2005.02 yhlu add E0 memory hole support
+*/
+/* not yet 
+#if K8_REV_F_SUPPORT == 1
+        #include "raminit_f.c"
+#else
+ */
+
+#include <console.h>
+#include <mtrr.h>
+#include <amd/k8/raminit.h>
+#include <amd/k8/k8.h>
+#include <amd/k8/sysconf.h>
+#include <device/pci.h>
+
+#ifndef QRANK_DIMM_SUPPORT
+#define QRANK_DIMM_SUPPORT 0
+#endif
+
+static void hard_reset(void);
+
+static void setup_resource_map(const unsigned int *register_values, int max)
+{
+	printk(BIOS_DEBUG, "setting up resource map....");
+/*
+	int i;
+	for(i = 0; i < max; i += 3) {
+		struct device *dev;
+		unsigned where;
+		unsigned long reg;
+		printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+		dev = register_values[i] & ~0xfff;
+		where = register_values[i] & 0xfff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		pci_write_config32(dev, where, reg);
+	}
+*/
+	printk(BIOS_DEBUG, "done.\r\n");
+}
+
+static int controller_present(const struct mem_controller *ctrl)
+{
+        return pci_read_config32(ctrl->f0, 0) == 0x11001022;
+}
+
+static void sdram_set_registers(const struct mem_controller *ctrl)
+{
+	static const unsigned int register_values[] = {
+
+	/* Careful set limit registers before base registers which contain the enables */
+	/* DRAM Limit i Registers
+	 * F1:0x44 i = 0
+	 * F1:0x4C i = 1
+	 * F1:0x54 i = 2
+	 * F1:0x5C i = 3
+	 * F1:0x64 i = 4
+	 * F1:0x6C i = 5
+	 * F1:0x74 i = 6
+	 * F1:0x7C i = 7
+	 * [ 2: 0] Destination Node ID
+	 *	   000 = Node 0
+	 *	   001 = Node 1
+	 *	   010 = Node 2
+	 *	   011 = Node 3
+	 *	   100 = Node 4
+	 *	   101 = Node 5
+	 *	   110 = Node 6
+	 *	   111 = Node 7
+	 * [ 7: 3] Reserved
+	 * [10: 8] Interleave select
+	 *	   specifies the values of A[14:12] to use with interleave enable.
+	 * [15:11] Reserved
+	 * [31:16] DRAM Limit Address i Bits 39-24
+	 *	   This field defines the upper address bits of a 40 bit  address
+	 *	   that define the end of the DRAM region.
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+	/* DRAM Base i Registers
+	 * F1:0x40 i = 0
+	 * F1:0x48 i = 1
+	 * F1:0x50 i = 2
+	 * F1:0x58 i = 3
+	 * F1:0x60 i = 4
+	 * F1:0x68 i = 5
+	 * F1:0x70 i = 6
+	 * F1:0x78 i = 7
+	 * [ 0: 0] Read Enable
+	 *	   0 = Reads Disabled
+	 *	   1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *	   0 = Writes Disabled
+	 *	   1 = Writes Enabled
+	 * [ 7: 2] Reserved
+	 * [10: 8] Interleave Enable
+	 *	   000 = No interleave
+	 *	   001 = Interleave on A[12] (2 nodes)
+	 *	   010 = reserved
+	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+	 *	   100 = reserved
+	 *	   101 = reserved
+	 *	   110 = reserved
+	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+	 * [15:11] Reserved
+	 * [13:16] DRAM Base Address i Bits 39-24
+	 *	   This field defines the upper address bits of a 40-bit address
+	 *	   that define the start of the DRAM region.
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+	/* DRAM CS Base Address i Registers
+	 * F2:0x40 i = 0
+	 * F2:0x44 i = 1
+	 * F2:0x48 i = 2
+	 * F2:0x4C i = 3
+	 * F2:0x50 i = 4
+	 * F2:0x54 i = 5
+	 * F2:0x58 i = 6
+	 * F2:0x5C i = 7
+	 * [ 0: 0] Chip-Select Bank Enable
+	 *	   0 = Bank Disabled
+	 *	   1 = Bank Enabled
+	 * [ 8: 1] Reserved
+	 * [15: 9] Base Address (19-13)
+	 *	   An optimization used when all DIMM are the same size...
+	 * [20:16] Reserved
+	 * [31:21] Base Address (35-25)
+	 *	   This field defines the top 11 addresses bit of a 40-bit
+	 *	   address that define the memory address space.  These
+	 *	   bits decode 32-MByte blocks of memory.
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x58), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x5C), 0x001f01fe, 0x00000000,
+	/* DRAM CS Mask Address i Registers
+	 * F2:0x60 i = 0
+	 * F2:0x64 i = 1
+	 * F2:0x68 i = 2
+	 * F2:0x6C i = 3
+	 * F2:0x70 i = 4
+	 * F2:0x74 i = 5
+	 * F2:0x78 i = 6
+	 * F2:0x7C i = 7
+	 * Select bits to exclude from comparison with the DRAM Base address register.
+	 * [ 8: 0] Reserved
+	 * [15: 9] Address Mask (19-13)
+	 *	   Address to be excluded from the optimized case
+	 * [20:16] Reserved
+	 * [29:21] Address Mask (33-25)
+	 *	   The bits with an address mask of 1 are excluded from address comparison
+	 * [31:30] Reserved
+	 * 
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x78), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x7C), 0xC01f01ff, 0x00000000,
+	/* DRAM Bank Address Mapping Register
+	 * F2:0x80
+	 * Specify the memory module size
+	 * [ 2: 0] CS1/0 
+	 * [ 6: 4] CS3/2
+	 * [10: 8] CS5/4
+	 * [14:12] CS7/6
+	 *	   000 = 32Mbyte  (Rows = 12 & Col =  8)
+	 *	   001 = 64Mbyte  (Rows = 12 & Col =  9)
+	 *	   010 = 128Mbyte (Rows = 13 & Col =  9)|(Rows = 12 & Col = 10)
+	 *	   011 = 256Mbyte (Rows = 13 & Col = 10)|(Rows = 12 & Col = 11)
+	 *	   100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10)
+	 *	   101 = 1Gbyte	  (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12)
+	 *	   110 = 2Gbyte	  (Rows = 14 & Col = 12)
+	 *	   111 = reserved 
+	 * [ 3: 3] Reserved
+	 * [ 7: 7] Reserved
+	 * [11:11] Reserved
+	 * [31:15]
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000000,
+	/* DRAM Timing Low Register
+	 * F2:0x88
+	 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
+	 *	   000 = reserved
+	 *	   001 = CL 2
+	 *	   010 = CL 3
+	 *	   011 = reserved
+	 *	   100 = reserved
+	 *	   101 = CL 2.5
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [ 3: 3] Reserved
+	 * [ 7: 4] Trc (Row Cycle Time, Ras#-active to Ras#-active/bank auto refresh)
+	 *	   0000 =  7 bus clocks
+	 *	   0001 =  8 bus clocks
+	 *	   ...
+	 *	   1110 = 21 bus clocks
+	 *	   1111 = 22 bus clocks
+	 * [11: 8] Trfc (Row refresh Cycle time, Auto-refresh-active to RAS#-active or RAS#auto-refresh)
+	 *	   0000 = 9 bus clocks
+	 *	   0010 = 10 bus clocks
+	 *	   ....
+	 *	   1110 = 23 bus clocks
+	 *	   1111 = 24 bus clocks
+	 * [14:12] Trcd (Ras#-active to Case#-read/write Delay)
+	 *	   000 = reserved
+	 *	   001 = reserved
+	 *	   010 = 2 bus clocks
+	 *	   011 = 3 bus clocks
+	 *	   100 = 4 bus clocks
+	 *	   101 = 5 bus clocks
+	 *	   110 = 6 bus clocks
+	 *	   111 = reserved
+	 * [15:15] Reserved
+	 * [18:16] Trrd (Ras# to Ras# Delay)
+	 *	   000 = reserved
+	 *	   001 = reserved
+	 *	   010 = 2 bus clocks
+	 *	   011 = 3 bus clocks
+	 *	   100 = 4 bus clocks
+	 *	   101 = reserved
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [19:19] Reserved
+	 * [23:20] Tras (Minmum Ras# Active Time)
+	 *	   0000 to 0100 = reserved
+	 *	   0101 = 5 bus clocks
+	 *	   ...
+	 *	   1111 = 15 bus clocks
+	 * [26:24] Trp (Row Precharge Time)
+	 *	   000 = reserved
+	 *	   001 = reserved
+	 *	   010 = 2 bus clocks
+	 *	   011 = 3 bus clocks
+	 *	   100 = 4 bus clocks
+	 *	   101 = 5 bus clocks
+	 *	   110 = 6 bus clocks
+	 *	   111 = reserved
+	 * [27:27] Reserved
+	 * [28:28] Twr (Write Recovery Time)
+	 *	   0 = 2 bus clocks
+	 *	   1 = 3 bus clocks
+	 * [31:29] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x02522001 /* 0x03623125 */ ,
+	/* DRAM Timing High Register
+	 * F2:0x8C
+	 * [ 0: 0] Twtr (Write to Read Delay)
+	 *	   0 = 1 bus Clocks
+	 *	   1 = 2 bus Clocks
+	 * [ 3: 1] Reserved
+	 * [ 6: 4] Trwt (Read to Write Delay)
+	 *	   000 = 1 bus clocks
+	 *	   001 = 2 bus clocks
+	 *	   010 = 3 bus clocks
+	 *	   011 = 4 bus clocks
+	 *	   100 = 5 bus clocks
+	 *	   101 = 6 bus clocks
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [ 7: 7] Reserved
+	 * [12: 8] Tref (Refresh Rate)
+	 *	   00000 = 100Mhz 4K rows
+	 *	   00001 = 133Mhz 4K rows
+	 *	   00010 = 166Mhz 4K rows
+	 *	   00011 = 200Mhz 4K rows
+	 *	   01000 = 100Mhz 8K/16K rows
+	 *	   01001 = 133Mhz 8K/16K rows
+	 *	   01010 = 166Mhz 8K/16K rows
+	 *	   01011 = 200Mhz 8K/16K rows
+	 * [19:13] Reserved
+	 * [22:20] Twcl (Write CAS Latency)
+	 *	   000 = 1 Mem clock after CAS# (Unbuffered Dimms)
+	 *	   001 = 2 Mem clocks after CAS# (Registered Dimms)
+	 * [31:23] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
+	/* DRAM Config Low Register
+	 * F2:0x90
+	 * [ 0: 0] DLL Disable
+	 *	   0 = Enabled
+	 *	   1 = Disabled
+	 * [ 1: 1] D_DRV
+	 *	   0 = Normal Drive
+	 *	   1 = Weak Drive
+	 * [ 2: 2] QFC_EN
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [ 3: 3] Disable DQS Hystersis  (FIXME handle this one carefully)
+	 *	   0 = Enable DQS input filter 
+	 *	   1 = Disable DQS input filtering 
+	 * [ 7: 4] Reserved
+	 * [ 8: 8] DRAM_Init
+	 *	   0 = Initialization done or not yet started.
+	 *	   1 = Initiate DRAM intialization sequence
+	 * [ 9: 9] SO-Dimm Enable
+	 *	   0 = Do nothing
+	 *	   1 = SO-Dimms present
+	 * [10:10] DramEnable
+	 *	   0 = DRAM not enabled
+	 *	   1 = DRAM initialized and enabled
+	 * [11:11] Memory Clear Status
+	 *	   0 = Memory Clear function has not completed
+	 *	   1 = Memory Clear function has completed
+	 * [12:12] Exit Self-Refresh
+	 *	   0 = Exit from self-refresh done or not yet started
+	 *	   1 = DRAM exiting from self refresh
+	 * [13:13] Self-Refresh Status
+	 *	   0 = Normal Operation
+	 *	   1 = Self-refresh mode active
+	 * [15:14] Read/Write Queue Bypass Count
+	 *	   00 = 2
+	 *	   01 = 4
+	 *	   10 = 8
+	 *	   11 = 16
+	 * [16:16] 128-bit/64-Bit
+	 *	   0 = 64bit Interface to DRAM
+	 *	   1 = 128bit Interface to DRAM
+	 * [17:17] DIMM ECC Enable
+	 *	   0 = Some DIMMs do not have ECC
+	 *	   1 = ALL DIMMS have ECC bits
+	 * [18:18] UnBuffered DIMMs
+	 *	   0 = Buffered DIMMS
+	 *	   1 = Unbuffered DIMMS
+	 * [19:19] Enable 32-Byte Granularity
+	 *	   0 = Optimize for 64byte bursts
+	 *	   1 = Optimize for 32byte bursts
+	 * [20:20] DIMM 0 is x4
+	 * [21:21] DIMM 1 is x4
+	 * [22:22] DIMM 2 is x4
+	 * [23:23] DIMM 3 is x4
+	 *	   0 = DIMM is not x4
+	 *	   1 = x4 DIMM present
+	 * [24:24] Disable DRAM Receivers
+	 *	   0 = Receivers enabled
+	 *	   1 = Receivers disabled
+	 * [27:25] Bypass Max
+	 *	   000 = Arbiters chois is always respected
+	 *	   001 = Oldest entry in DCQ can be bypassed 1 time
+	 *	   010 = Oldest entry in DCQ can be bypassed 2 times
+	 *	   011 = Oldest entry in DCQ can be bypassed 3 times
+	 *	   100 = Oldest entry in DCQ can be bypassed 4 times
+	 *	   101 = Oldest entry in DCQ can be bypassed 5 times
+	 *	   110 = Oldest entry in DCQ can be bypassed 6 times
+	 *	   111 = Oldest entry in DCQ can be bypassed 7 times
+	 * [31:28] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
+	(4 << 25)|(0 << 24)| 
+	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
+	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| 
+	(2 << 14)|(0 << 13)|(0 << 12)| 
+	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
+	(0 << 3) |(0 << 1) |(0 << 0),
+	/* DRAM Config High Register
+	 * F2:0x94
+	 * [ 0: 3] Maximum Asynchronous Latency
+	 *	   0000 = 0 ns
+	 *	   ...
+	 *	   1111 = 15 ns
+	 * [ 7: 4] Reserved
+	 * [11: 8] Read Preamble
+	 *	   0000 = 2.0 ns
+	 *	   0001 = 2.5 ns
+	 *	   0010 = 3.0 ns
+	 *	   0011 = 3.5 ns
+	 *	   0100 = 4.0 ns
+	 *	   0101 = 4.5 ns
+	 *	   0110 = 5.0 ns
+	 *	   0111 = 5.5 ns
+	 *	   1000 = 6.0 ns
+	 *	   1001 = 6.5 ns
+	 *	   1010 = 7.0 ns
+	 *	   1011 = 7.5 ns
+	 *	   1100 = 8.0 ns
+	 *	   1101 = 8.5 ns
+	 *	   1110 = 9.0 ns
+	 *	   1111 = 9.5 ns
+	 * [15:12] Reserved
+	 * [18:16] Idle Cycle Limit
+	 *	   000 = 0 cycles
+	 *	   001 = 4 cycles
+	 *	   010 = 8 cycles
+	 *	   011 = 16 cycles
+	 *	   100 = 32 cycles
+	 *	   101 = 64 cycles
+	 *	   110 = 128 cycles
+	 *	   111 = 256 cycles
+	 * [19:19] Dynamic Idle Cycle Center Enable
+	 *	   0 = Use Idle Cycle Limit
+	 *	   1 = Generate a dynamic Idle cycle limit
+	 * [22:20] DRAM MEMCLK Frequency
+	 *	   000 = 100Mhz
+	 *	   001 = reserved
+	 *	   010 = 133Mhz
+	 *	   011 = reserved
+	 *	   100 = reserved
+	 *	   101 = 166Mhz
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [24:23] Reserved
+	 * [25:25] Memory Clock Ratio Valid (FIXME carefully enable memclk)
+	 *	   0 = Disable MemClks
+	 *	   1 = Enable MemClks
+	 * [26:26] Memory Clock 0 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [27:27] Memory Clock 1 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [28:28] Memory Clock 2 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [29:29] Memory Clock 3 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [31:30] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0,
+	(0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)|
+	(0 << 20)|(0 << 19)|(DCH_IDLE_LIMIT_16 << 16)|(0 << 8)|(0 << 0),
+	/* DRAM Delay Line Register
+	 * F2:0x98
+	 * Adjust the skew of the input DQS strobe relative to DATA
+	 * [15: 0] Reserved
+	 * [23:16] Delay Line Adjust
+	 *	   Adjusts the DLL derived PDL delay by one or more delay stages
+	 *	   in either the faster or slower direction.
+	 * [24:24} Adjust Slower
+	 *	   0 = Do Nothing
+	 *	   1 = Adj is used to increase the PDL delay
+	 * [25:25] Adjust Faster
+	 *	   0 = Do Nothing
+	 *	   1 = Adj is used to decrease the PDL delay
+	 * [31:26] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
+	/* MCA NB Status Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
+	/* MCA NB Status high reg */
+	PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
+	/* MCA NB address Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
+	/* MCA NB address high reg */
+	PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
+	/* DRAM Scrub Control Register
+	 * F3:0x58
+	 * [ 4: 0] DRAM Scrube Rate
+	 * [ 7: 5] reserved
+	 * [12: 8] L2 Scrub Rate
+	 * [15:13] reserved
+	 * [20:16] Dcache Scrub
+	 * [31:21] reserved
+	 *	   Scrub Rates
+	 *	   00000 = Do not scrub
+	 *	   00001 =  40.00 ns
+	 *	   00010 =  80.00 ns
+	 *	   00011 = 160.00 ns
+	 *	   00100 = 320.00 ns
+	 *	   00101 = 640.00 ns
+	 *	   00110 =   1.28 us
+	 *	   00111 =   2.56 us
+	 *	   01000 =   5.12 us
+	 *	   01001 =  10.20 us
+	 *	   01011 =  41.00 us
+	 *	   01100 =  81.90 us
+	 *	   01101 = 163.80 us
+	 *	   01110 = 327.70 us
+	 *	   01111 = 655.40 us
+	 *	   10000 =   1.31 ms
+	 *	   10001 =   2.62 ms
+	 *	   10010 =   5.24 ms
+	 *	   10011 =  10.49 ms
+	 *	   10100 =  20.97 ms
+	 *	   10101 =  42.00 ms
+	 *	   10110 =  84.00 ms
+	 *	   All Others = Reserved
+	 */
+	PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
+	/* DRAM Scrub Address Low Register
+	 * F3:0x5C
+	 * [ 0: 0] DRAM Scrubber Redirect Enable
+	 *	   0 = Do nothing
+	 *	   1 = Scrubber Corrects errors found in normal operation
+	 * [ 5: 1] Reserved
+	 * [31: 6] DRAM Scrub Address 31-6
+	 */
+	PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
+	/* DRAM Scrub Address High Register
+	 * F3:0x60
+	 * [ 7: 0] DRAM Scrubb Address 39-32
+	 * [31: 8] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
+	};
+	int i;
+	int max;
+
+        if (!controller_present(ctrl)) {
+                printk(BIOS_DEBUG, "No memory controller present\r\n");
+                return;
+        }
+	printk(BIOS_SPEW, "setting up CPU 0x%x northbridge registers ", ctrl->node_id);
+	max = sizeof(register_values)/sizeof(register_values[0]);
+	for(i = 0; i < max; i += 3) {
+		struct device *dev;
+		unsigned where;
+		unsigned long reg;
+                printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+		dev = (register_values[i] & ~0xfff) - PCI_BDF(0, 0x18, 0) + ctrl->f0;
+		where = register_values[i] & 0xfff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		pci_write_config32(dev, where, reg);
+	}
+	printk(BIOS_SPEW, "done.\r\n");
+}
+
+
+static void hw_enable_ecc(const struct mem_controller *ctrl)
+{
+	u32 dcl, nbcap;
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~DCL_DimmEccEn;
+	if (nbcap & NBCAP_ECC) {
+		dcl |= DCL_DimmEccEn;
+	}
+	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+		dcl &= ~DCL_DimmEccEn;
+	}
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	
+}
+
+static int is_dual_channel(const struct mem_controller *ctrl)
+{
+	u32 dcl;
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	return dcl & DCL_128BitEn;
+}
+
+static int is_opteron(const struct mem_controller *ctrl)
+{
+	/* Test to see if I am an Opteron.  
+	 * FIXME Socket 939 based Athlon64 have dual channel capability,
+	 * too, so we need a better test for Opterons
+	 */
+#warning "FIXME: Implement a better test for Opterons"
+	u32 nbcap;
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	return !!(nbcap & NBCAP_128Bit);
+}
+
+static int is_registered(const struct mem_controller *ctrl)
+{
+	/* Test to see if we are dealing with registered SDRAM.
+	 * If we are not registered we are unbuffered.
+	 * This function must be called after spd_handle_unbuffered_dimms.
+	 */
+	u32 dcl;
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	return !(dcl & DCL_UnBufDimm);
+}
+
+struct dimm_size {
+	unsigned long side1;
+	unsigned long side2;
+	unsigned long rows;
+	unsigned long col;
+#if QRANK_DIMM_SUPPORT == 1
+	unsigned long rank;
+#endif
+};
+
+static struct dimm_size spd_get_dimm_size(unsigned device)
+{
+	/* Calculate the log base 2 size of a DIMM in bits */
+	struct dimm_size sz;
+	int value, low;
+	sz.side1 = 0;
+	sz.side2 = 0;
+	sz.rows = 0;
+	sz.col = 0;
+#if QRANK_DIMM_SUPPORT == 1
+	sz.rank = 0;
+#endif
+
+	/* Note it might be easier to use byte 31 here, it has the DIMM size as
+	 * a multiple of 4MB.  The way we do it now we can size both
+	 * sides of an assymetric dimm.
+	 */
+	value = spd_read_byte(device, 3);	/* rows */
+	if (value < 0) goto hw_err;
+	if ((value & 0xf) == 0) goto val_err;
+	sz.side1 += value & 0xf;
+	sz.rows = value & 0xf;
+
+	value = spd_read_byte(device, 4);	/* columns */
+	if (value < 0) goto hw_err;
+	if ((value & 0xf) == 0) goto val_err;
+	sz.side1 += value & 0xf;
+	sz.col = value & 0xf;
+
+	value = spd_read_byte(device, 17);	/* banks */
+	if (value < 0) goto hw_err;
+	if ((value & 0xff) == 0) goto val_err;
+	sz.side1 += log2(value & 0xff);
+
+	/* Get the module data width and convert it to a power of two */
+	value = spd_read_byte(device, 7);	/* (high byte) */
+	if (value < 0) goto hw_err;
+	value &= 0xff;
+	value <<= 8;
+	
+	low = spd_read_byte(device, 6);	/* (low byte) */
+	if (low < 0) goto hw_err;
+	value = value | (low & 0xff);
+	if ((value != 72) && (value != 64)) goto val_err;
+	sz.side1 += log2(value);
+
+	/* side 2 */
+	value = spd_read_byte(device, 5);	/* number of physical banks */
+	if (value < 0) goto hw_err;
+	if (value == 1) goto out;
+	if ((value != 2) && (value != 4 )) {
+		goto val_err;
+	}
+#if QRANK_DIMM_SUPPORT == 1
+	sz.rank = value;
+#endif
+
+	/* Start with the symmetrical case */
+	sz.side2 = sz.side1;
+
+	value = spd_read_byte(device, 3);	/* rows */
+	if (value < 0) goto hw_err;
+	if ((value & 0xf0) == 0) goto out;	/* If symmetrical we are done */
+	sz.side2 -= (value & 0x0f);		/* Subtract out rows on side 1 */
+	sz.side2 += ((value >> 4) & 0x0f);	/* Add in rows on side 2 */
+
+	value = spd_read_byte(device, 4);	/* columns */
+	if (value < 0) goto hw_err;
+	if ((value & 0xff) == 0) goto val_err;
+	sz.side2 -= (value & 0x0f);		/* Subtract out columns on side 1 */
+	sz.side2 += ((value >> 4) & 0x0f);	/* Add in columsn on side 2 */
+
+	goto out;
+
+ val_err:
+	die("Bad SPD value\r\n");
+	/* If an hw_error occurs report that I have no memory */
+hw_err:
+	sz.side1 = 0;
+	sz.side2 = 0;
+	sz.rows = 0;
+	sz.col = 0;
+#if QRANK_DIMM_SUPPORT == 1
+	sz.rank = 0;
+#endif
+ out:
+	return sz;
+}
+
+
+static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
+{
+	u32 base0, base1;
+	u32 dch;
+
+	if (sz.side1 != sz.side2) {
+		sz.side2 = 0;
+	}
+	
+	/* For each base register.
+	 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
+	 * The initialize dimm size is in bits.
+	 * Set the base enable bit0.
+	 */
+	
+	base0 = base1 = 0;
+
+	/* Make certain side1 of the dimm is at least 32MB */
+	if (sz.side1 >= (25 +3)) {
+		base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
+	}
+	
+	/* Make certain side2 of the dimm is at least 32MB */
+	if (sz.side2 >= (25 + 3)) {
+		base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1;
+	}
+
+	/* Double the size if we are using dual channel memory */
+	if (is_dual_channel(ctrl)) {
+		base0 = (base0 << 1) | (base0 & 1);
+		base1 = (base1 << 1) | (base1 & 1);
+	}
+
+	/* Clear the reserved bits */
+	base0 &= ~0x001ffffe;
+	base1 &= ~0x001ffffe;
+
+	/* Set the appropriate DIMM base address register */
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+#if QRANK_DIMM_SUPPORT == 1
+	if(sz.rank == 4) {
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
+	}
+#endif
+
+	/* Enable the memory clocks for this DIMM */
+	if (base0) {
+		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+		dch |= DCH_MEMCLK_EN0 << index;
+#if QRANK_DIMM_SUPPORT == 1
+		if(sz.rank == 4) {
+			dch |= DCH_MEMCLK_EN0 << (index + 2);
+		}
+#endif
+		pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	}
+}
+
+static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
+{
+	static const unsigned cs_map_aa[] = {
+		/* (row=12, col=8)(14, 12) ---> (0, 0) (2, 4) */
+		0, 1, 3, 6, 0,
+		0, 2, 4, 7, 9,
+		0, 0, 5, 8,10,
+	};
+
+	u32 map;
+	u32 dch;
+
+	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+	map &= ~(0xf << (index * 4));
+#if QRANK_DIMM_SUPPORT == 1
+        if(sz.rank == 4) {
+                map &= ~(0xf << ( (index + 2) * 4));
+        }
+#endif
+
+
+	/* Make certain side1 of the dimm is at least 32MB */
+	if (sz.side1 >= (25 +3)) {
+		if(is_cpu_pre_d0()) {
+			map |= (sz.side1 - (25 + 3)) << (index *4);
+#if QRANK_DIMM_SUPPORT == 1
+	                if(sz.rank == 4) {
+         	              map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
+               		}
+#endif
+		}
+		else {
+			map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
+#if QRANK_DIMM_SUPPORT == 1
+		        if(sz.rank == 4) {
+                	       map |=  cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
+               		}
+#endif
+		}
+	}
+
+	pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
+	
+}
+
+static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
+{
+	int i;
+	
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		struct dimm_size sz;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		sz = spd_get_dimm_size(ctrl->channel0[i]);
+		if (sz.side1 == 0) {
+			return -1; /* Report SPD error */
+		}
+		set_dimm_size(ctrl, sz, i);
+		set_dimm_map (ctrl, sz, i);
+	}
+	return dimm_mask;
+}
+
+static void route_dram_accesses(const struct mem_controller *ctrl,
+	unsigned long base_k, unsigned long limit_k)
+{
+	/* Route the addresses to the controller node */
+	unsigned node_id;
+	unsigned limit;
+	unsigned base;
+	unsigned index;
+	unsigned limit_reg, base_reg;
+	struct device *device;
+
+	node_id = ctrl->node_id;
+	index = (node_id << 3);
+	limit = (limit_k << 2);
+	limit &= 0xffff0000;
+	limit -= 0x00010000;
+	limit |= ( 0 << 8) | (node_id << 0);
+	base = (base_k << 2);
+	base &= 0xffff0000;
+	base |= (0 << 8) | (1<<1) | (1<<0);
+
+	limit_reg = 0x44 + index;
+	base_reg = 0x40 + index;
+	for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
+		pci_write_config32(device, limit_reg, limit);
+		pci_write_config32(device, base_reg, base);
+	}
+}
+
+static void set_top_mem(unsigned tom_k, unsigned hole_startk)
+{
+	/* Error if I don't have memory */
+	if (!tom_k) {
+		die("No memory?");
+	}
+
+	/* Report the amount of memory. */
+	print_spew("RAM: 0x");
+	print_spew_hex32(tom_k);
+	print_spew(" KB\r\n");
+
+	/* Now set top of memory */
+	msr_t msr;
+	if(tom_k > (4*1024*1024)) {
+		msr.lo = (tom_k & 0x003fffff) << 10;
+		msr.hi = (tom_k & 0xffc00000) >> 22;
+		wrmsr(TOP_MEM2, msr);
+	}
+
+	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
+	 * so I can see my rom chip and other I/O devices.
+	 */
+	if (tom_k >= 0x003f0000) {
+#if HW_MEM_HOLE_SIZEK != 0
+                if(hole_startk != 0) {
+                        tom_k = hole_startk;
+                } else
+#endif
+                tom_k = 0x3f0000;
+	}
+	msr.lo = (tom_k & 0x003fffff) << 10;
+	msr.hi = (tom_k & 0xffc00000) >> 22;
+	wrmsr(TOP_MEM, msr);
+}
+
+static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
+{
+	/* 35 - 25 */
+	static const u8 csbase_low_shift[] = { 
+	/* 32MB */	(13 - 4),
+	/* 64MB */	(14 - 4),
+	/* 128MB */	(14 - 4), 
+	/* 256MB */	(15 - 4),
+	/* 512MB */	(15 - 4),
+	/* 1GB */	(16 - 4),
+	/* 2GB */	(16 - 4), 
+	};
+
+        static const u8 csbase_low_d0_shift[] = {
+        /* 32MB */      (13 - 4),
+        /* 64MB */      (14 - 4),
+        /* 128MB */     (14 - 4),
+	/* 128MB */     (15 - 4),
+        /* 256MB */     (15 - 4),
+        /* 512MB */     (15 - 4),
+        /* 256MB */     (16 - 4),
+        /* 512MB */     (16 - 4),
+        /* 1GB */       (16 - 4),
+	/* 1GB */       (17 - 4),
+        /* 2GB */       (17 - 4),
+        };
+
+	/* cs_base_high is not changed */
+
+	u32 csbase_inc;
+	int chip_selects, index;
+	int bits;
+	unsigned common_size;
+	unsigned common_cs_mode;
+	u32 csbase, csmask;
+
+	/* See if all of the memory chip selects are the same size
+	 * and if so count them.
+	 */
+	chip_selects = 0;
+	common_size = 0;
+	common_cs_mode = 0;
+	for(index = 0; index < 8; index++) {
+		unsigned size;
+		unsigned cs_mode;
+		u32 value;
+		
+		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+		
+		/* Is it enabled? */
+		if (!(value & 1)) {
+			continue;
+		}
+		chip_selects++;
+		size = value >> 21;
+		if (common_size == 0) {
+			common_size = size;
+		}
+		/* The size differed fail */
+		if (common_size != size) {
+			return 0;
+		}
+
+		value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+                cs_mode =( value >> ((index>>1)*4)) & 0xf;
+                if(cs_mode == 0 ) continue;
+                if(common_cs_mode == 0) {
+                	common_cs_mode = cs_mode;
+                }
+                /* The size differed fail */
+                if(common_cs_mode != cs_mode) {
+                        return 0;
+                }
+	}
+
+	/* Chip selects can only be interleaved when there is
+	 * more than one and their is a power of two of them.
+	 */
+	bits = log2(chip_selects);
+	if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
+		return 0;
+	}
+
+	/* Find the bits of csbase that we need to interleave on */
+	if(is_cpu_pre_d0()){
+		csbase_inc = 1 << csbase_low_shift[common_cs_mode];
+		if(is_dual_channel(ctrl)) {
+                /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
+	                if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
+//     		                printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\r\n");
+	                        return 0;
+                	}  
+			csbase_inc <<=1;
+		}
+	}
+	else {
+		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
+		if(is_dual_channel(ctrl)) {
+	                if( (bits==3) && (common_cs_mode > 8)) {
+//        	                printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\r\n");
+        	                return 0;
+			}
+			csbase_inc <<=1;
+                }   
+	}
+
+	/* Compute the initial values for csbase and csbask. 
+	 * In csbase just set the enable bit and the base to zero.
+	 * In csmask set the mask bits for the size and page level interleave.
+	 */
+	csbase = 0 | 1;
+	csmask = (((common_size  << bits) - 1) << 21);
+	csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc);
+	for(index = 0; index < 8; index++) {
+		u32 value;
+
+		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+		/* Is it enabled? */
+		if (!(value & 1)) {
+			continue;
+		}
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
+		pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
+		csbase += csbase_inc;
+	}
+	
+	printk(BIOS_SPEW, "Interleaved\n");
+
+	/* Return the memory size in K */
+	return common_size << (15 + bits);
+}
+
+static unsigned long order_chip_selects(const struct mem_controller *ctrl)
+{
+	unsigned long tom;
+
+	/* Remember which registers we have used in the high 8 bits of tom */
+	tom = 0;
+	for(;;) {
+		/* Find the largest remaining canidate */
+		unsigned index, canidate;
+		u32 csbase, csmask;
+		unsigned size;
+		csbase = 0;
+		canidate = 0;
+		for(index = 0; index < 8; index++) {
+			u32 value;
+			value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+
+			/* Is it enabled? */
+			if (!(value & 1)) {
+				continue;
+			}
+			
+			/* Is it greater? */
+			if (value <= csbase) {
+				continue;
+			}
+			
+			/* Has it already been selected */
+			if (tom & (1 << (index + 24))) {
+				continue;
+			}
+			/* I have a new canidate */
+			csbase = value;
+			canidate = index;
+		}
+		/* See if I have found a new canidate */
+		if (csbase == 0) {
+			break;
+		}
+
+		/* Remember the dimm size */
+		size = csbase >> 21;
+
+		/* Remember I have used this register */
+		tom |= (1 << (canidate + 24));
+
+		/* Recompute the cs base register value */
+		csbase = (tom << 21) | 1;
+
+		/* Increment the top of memory */
+		tom += size;
+
+		/* Compute the memory mask */
+		csmask = ((size -1) << 21);
+		csmask |= 0xfe00;		/* For now don't optimize */
+
+		/* Write the new base register */
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
+		/* Write the new mask register */
+		pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
+		
+	}
+	/* Return the memory size in K */
+	return (tom & ~0xff000000) << 15;
+}
+
+unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
+{
+	unsigned node_id;
+	unsigned end_k;
+	/* Find the last memory address used */
+	end_k = 0;
+	for(node_id = 0; node_id < max_node_id; node_id++) {
+		u32 limit, base;
+		unsigned index;
+		index = node_id << 3;
+		base = pci_read_config32(ctrl->f1, 0x40 + index);
+		/* Only look at the limit if the base is enabled */
+		if ((base & 3) == 3) {
+			limit = pci_read_config32(ctrl->f1, 0x44 + index);
+			end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
+		}
+	}
+	return end_k;
+}
+
+static void order_dimms(const struct mem_controller *ctrl)
+{
+	unsigned long tom_k, base_k;
+
+	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
+		tom_k = interleave_chip_selects(ctrl);
+	} else {
+		printk(BIOS_DEBUG, "Interleaving disabled\r\n");
+		tom_k = 0;
+	}
+	if (!tom_k) {
+		tom_k = order_chip_selects(ctrl);
+	}
+	/* Compute the memory base address */
+	base_k = memory_end_k(ctrl, ctrl->node_id);
+	tom_k += base_k;
+	route_dram_accesses(ctrl, base_k, tom_k);
+	set_top_mem(tom_k, 0);
+}
+
+static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
+{
+	printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index); 
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
+	dimm_mask &= ~(1 << index);
+	return dimm_mask;
+}
+
+static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask)
+{
+	int i;
+	int registered;
+	int unbuffered;
+	int has_dualch = is_opteron(ctrl);
+	u32 dcl;
+	unbuffered = 0;
+	registered = 0;
+	for(i = 0; (i < DIMM_SOCKETS); i++) {
+		int value;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		value = spd_read_byte(ctrl->channel0[i], 21);
+		if (value < 0) {
+			return -1;
+		}
+		/* Registered dimm ? */
+		if (value & (1 << 1)) {
+			registered = 1;
+		} 
+		/* Otherwise it must be an unbuffered dimm */
+		else {
+			unbuffered = 1;
+		}
+	}
+	if (unbuffered && registered) {
+		die("Mixed buffered and registered dimms not supported");
+	}
+
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~DCL_UnBufDimm;
+	if (unbuffered) {
+		if ((has_dualch) && (!is_cpu_pre_d0())) {
+			dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
+			
+			/* set DCL_En2T if you have non-equal DDR mem types! */
+			
+			if ((cpuid_eax(1) & 0x30) == 0x30) {
+				/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
+				dcl |= DCL_UpperCSMap;
+			}
+		} else {
+			dcl |= DCL_UnBufDimm;
+		}
+	}
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	if (is_registered(ctrl)) {
+		printk(BIOS_DEBUG, "Registered\r\n");
+	} else {
+		printk(BIOS_DEBUG, "Unbuffered\r\n");
+	}
+	return dimm_mask;
+}
+
+static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
+{
+	unsigned dimm_mask;
+	int i;
+	dimm_mask = 0;
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		int byte;
+		unsigned device;
+		device = ctrl->channel0[i];
+		if (device) {
+			byte = spd_read_byte(ctrl->channel0[i], 2);  /* Type */
+			if (byte == 7) {
+				dimm_mask |= (1 << i);
+			}
+		}
+		device = ctrl->channel1[i];
+		if (device) {
+			byte = spd_read_byte(ctrl->channel1[i], 2);
+			if (byte == 7) {
+				dimm_mask |= (1 << (i + DIMM_SOCKETS));
+			}
+		}
+	}
+	return dimm_mask;
+}
+
+static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask)
+{
+	int i;
+	u32 nbcap;
+	/* SPD addresses to verify are identical */
+	static const u8 addresses[] = {
+		2,	/* Type should be DDR SDRAM */
+		3,	/* *Row addresses */
+		4,	/* *Column addresses */
+		5,	/* *Physical Banks */
+		6,	/* *Module Data Width low */
+		7,	/* *Module Data Width high */
+		9,	/* *Cycle time at highest CAS Latency CL=X */
+		11,	/* *SDRAM Type */
+		13,	/* *SDRAM Width */
+		17,	/* *Logical Banks */
+		18,	/* *Supported CAS Latencies */
+		21,	/* *SDRAM Module Attributes */
+		23,	/* *Cycle time at CAS Latnecy (CLX - 0.5) */
+		26,	/* *Cycle time at CAS Latnecy (CLX - 1.0) */
+		27,	/* *tRP Row precharge time */
+		28,	/* *Minimum Row Active to Row Active Delay (tRRD) */
+		29,	/* *tRCD RAS to CAS */
+		30,	/* *tRAS Activate to Precharge */
+		41,	/* *Minimum Active to Active/Auto Refresh Time(Trc) */
+		42,	/* *Minimum Auto Refresh Command Time(Trfc) */
+	};
+	/* If the dimms are not in pairs do not do dual channels */
+	if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
+		((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { 
+		goto single_channel;
+	}
+	/* If the cpu is not capable of doing dual channels don't do dual channels */
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	if (!(nbcap & NBCAP_128Bit)) {
+		goto single_channel;
+	}
+	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+		unsigned device0, device1;
+		int value0, value1;
+		int j;
+		/* If I don't have a dimm skip this one */
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		device0 = ctrl->channel0[i];
+		device1 = ctrl->channel1[i];
+		for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
+			unsigned addr;
+			addr = addresses[j];
+			value0 = spd_read_byte(device0, addr);
+			if (value0 < 0) {
+				return -1;
+			}
+			value1 = spd_read_byte(device1, addr);
+			if (value1 < 0) {
+				return -1;
+			}
+			if (value0 != value1) {
+				goto single_channel;
+			}
+		}
+	}
+	printk(BIOS_SPEW, "Enabling dual channel memory\r\n");
+	u32 dcl;
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~DCL_32ByteEn;
+	dcl |= DCL_128BitEn;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	return dimm_mask;
+ single_channel:
+	dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
+	return dimm_mask;
+}
+
+struct mem_param {
+	u8 cycle_time;
+	u8 divisor; /* In 1/2 ns increments */
+	u8 tRC;
+	u8 tRFC;
+	u32 dch_memclk;
+	u16 dch_tref4k, dch_tref8k;
+	u8	 dtl_twr;
+	u8	 dtl_twtr;
+	u8  dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */
+ 	u8	 rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
+	char name[9];
+};
+
+static const struct mem_param *get_mem_param(unsigned min_cycle_time)
+{
+	static const struct mem_param speed[] = {
+		{
+			.name	    = "100Mhz\r\n",
+			.cycle_time = 0xa0,
+			.divisor    = (10 <<1),
+			.tRC	    = 0x46,
+			.tRFC	    = 0x50,
+			.dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_100MHZ_4K,
+			.dch_tref8k = DTH_TREF_100MHZ_8K,
+			.dtl_twr    = 2,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
+		},
+		{
+			.name	    = "133Mhz\r\n",
+			.cycle_time = 0x75,
+			.divisor    = (7<<1)+1,
+			.tRC	    = 0x41,
+			.tRFC	    = 0x4B,
+			.dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_133MHZ_4K,
+			.dch_tref8k = DTH_TREF_133MHZ_8K,
+			.dtl_twr    = 2,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
+		},
+		{
+			.name	    = "166Mhz\r\n",
+			.cycle_time = 0x60,
+			.divisor    = (6<<1),
+			.tRC	    = 0x3C,
+			.tRFC	    = 0x48,
+			.dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_166MHZ_4K,
+			.dch_tref8k = DTH_TREF_166MHZ_8K,
+			.dtl_twr    = 3,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }},
+			.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
+		},
+		{
+			.name	    = "200Mhz\r\n",
+			.cycle_time = 0x50,
+			.divisor    = (5<<1),
+			.tRC	    = 0x37,
+			.tRFC	    = 0x46,
+			.dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_200MHZ_4K,
+			.dch_tref8k = DTH_TREF_200MHZ_8K,
+			.dtl_twr    = 3,
+			.dtl_twtr   = 2,
+			.dtl_trwt   = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) }
+		},
+		{
+			.cycle_time = 0x00,
+		},
+	};
+	const struct mem_param *param;
+	for(param = &speed[0]; param->cycle_time ; param++) {
+		if (min_cycle_time > (param+1)->cycle_time) {
+			break;
+		}
+	}
+	if (!param->cycle_time) {
+		die("min_cycle_time to low");
+	}
+	print_spew(param->name);
+#ifdef DRAM_MIN_CYCLE_TIME
+	printk(BIOS_DEBUG, param->name);
+#endif
+	return param;
+}
+
+struct spd_set_memclk_result {
+	const struct mem_param *param;
+	long dimm_mask;
+};
+static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask)
+{
+	/* Compute the minimum cycle time for these dimms */
+	struct spd_set_memclk_result result;
+	unsigned min_cycle_time, min_latency, bios_cycle_time;
+	int i;
+	u32 value;
+
+	static const u8 latency_indicies[] = { 26, 23, 9 };
+	static const unsigned char min_cycle_times[] = {
+		[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
+		[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
+		[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
+		[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
+	};
+
+	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+
+	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
+	bios_cycle_time = min_cycle_times[
+		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
+	if (bios_cycle_time > min_cycle_time) {
+		min_cycle_time = bios_cycle_time;
+	}
+	min_latency = 2;
+
+	/* Compute the least latency with the fastest clock supported
+	 * by both the memory controller and the dimms.
+	 */
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		int new_cycle_time, new_latency;
+		int index;
+		int latencies;
+		int latency;
+
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+
+		/* First find the supported CAS latencies
+		 * Byte 18 for DDR SDRAM is interpreted:
+		 * bit 0 == CAS Latency = 1.0
+		 * bit 1 == CAS Latency = 1.5
+		 * bit 2 == CAS Latency = 2.0
+		 * bit 3 == CAS Latency = 2.5
+		 * bit 4 == CAS Latency = 3.0
+		 * bit 5 == CAS Latency = 3.5
+		 * bit 6 == TBD
+		 * bit 7 == TBD
+		 */
+		new_cycle_time = 0xa0;
+		new_latency = 5;
+
+		latencies = spd_read_byte(ctrl->channel0[i], 18);
+		if (latencies <= 0) continue;
+
+		/* Compute the lowest cas latency supported */
+		latency = log2(latencies) -2;
+
+		/* Loop through and find a fast clock with a low latency */
+		for(index = 0; index < 3; index++, latency++) {
+			int value;
+			if ((latency < 2) || (latency > 4) ||
+				(!(latencies & (1 << latency)))) {
+				continue;
+			}
+			value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+			if (value < 0) {
+				goto hw_error;
+			}
+
+			/* Only increase the latency if we decreas the clock */
+			if ((value >= min_cycle_time) && (value < new_cycle_time)) {
+				new_cycle_time = value;
+				new_latency = latency;
+			}
+		}
+		if (new_latency > 4){
+			continue;
+		}
+		/* Does min_latency need to be increased? */
+		if (new_cycle_time > min_cycle_time) {
+			min_cycle_time = new_cycle_time;
+		}
+		/* Does min_cycle_time need to be increased? */
+		if (new_latency > min_latency) {
+			min_latency = new_latency;
+		}
+	}
+	/* Make a second pass through the dimms and disable
+	 * any that cannot support the selected memclk and cas latency.
+	 */
+	
+	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+		int latencies;
+		int latency;
+		int index;
+		int value;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		latencies = spd_read_byte(ctrl->channel0[i], 18);
+		if (latencies < 0) goto hw_error;
+		if (latencies == 0) {
+			goto dimm_err;
+		}
+
+		/* Compute the lowest cas latency supported */
+		latency = log2(latencies) -2;
+
+		/* Walk through searching for the selected latency */
+		for(index = 0; index < 3; index++, latency++) {
+			if (!(latencies & (1 << latency))) {
+				continue;
+			}
+			if (latency == min_latency)
+				break;
+		}
+		/* If I can't find the latency or my index is bad error */
+		if ((latency != min_latency) || (index >= 3)) {
+			goto dimm_err;
+		}
+		
+		/* Read the min_cycle_time for this latency */
+		value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+		if (value < 0) goto hw_error;
+		
+		/* All is good if the selected clock speed 
+		 * is what I need or slower.
+		 */
+		if (value <= min_cycle_time) {
+			continue;
+		}
+		/* Otherwise I have an error, disable the dimm */
+	dimm_err:
+		dimm_mask = disable_dimm(ctrl, i, dimm_mask);
+	}
+#if 0
+//down speed for full load 4 rank support
+#if QRANK_DIMM_SUPPORT
+	if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
+		int ranks = 4;
+	        for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+			int val;
+                	if (!(dimm_mask & (1 << i))) {
+                        	continue;
+	                }
+        	        val = spd_read_byte(ctrl->channel0[i], 5);
+			if(val!=ranks) {
+				ranks = val;
+				break;
+			}
+		}
+		if(ranks==4) {
+			if(min_cycle_time <= 0x50 ) {
+				min_cycle_time = 0x60;
+			}
+		}
+		
+	}
+#endif
+#endif
+	/* Now that I know the minimum cycle time lookup the memory parameters */
+	result.param = get_mem_param(min_cycle_time);
+
+	/* Update DRAM Config High with our selected memory speed */
+	value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
+#if 0
+	/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed 
+	 * result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 
+	 * and higher speeds with certain DIMM loadings ---- cheating???*/
+	if(!is_cpu_pre_e0()) {
+		if(min_cycle_time==0x50) {
+			value |= 1<<31;
+		}
+	}
+#endif
+
+	value |= result.param->dch_memclk;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
+
+	static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
+	/* Update DRAM Timing Low with our selected cas latency */
+	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
+	value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
+	
+	result.dimm_mask = dimm_mask;
+	return result;
+ hw_error:
+	result.param = (const struct mem_param *)0;
+	result.dimm_mask = -1;
+	return result;
+}
+
+
+static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 41);
+	if (value < 0) return -1;
+	if ((value == 0) || (value == 0xff)) {
+		value = param->tRC;
+	}
+	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+	if (clocks < DTL_TRC_MIN) {
+		clocks = DTL_TRC_MIN;
+	}
+	if (clocks > DTL_TRC_MAX) {
+		return 0;
+	}
+
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
+	dtl |=	((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 42);
+	if (value < 0) return -1;
+	if ((value == 0) || (value == 0xff)) {
+		value = param->tRFC;
+	}
+	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+	if (clocks < DTL_TRFC_MIN) {
+		clocks = DTL_TRFC_MIN;
+	}
+	if (clocks > DTL_TRFC_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
+	dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+
+static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 29);
+	if (value < 0) return -1;
+	clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
+	if (clocks < DTL_TRCD_MIN) {
+		clocks = DTL_TRCD_MIN;
+	}
+	if (clocks > DTL_TRCD_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
+	dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 28);
+	if (value < 0) return -1;
+	clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
+	if (clocks < DTL_TRRD_MIN) {
+		clocks = DTL_TRRD_MIN;
+	}
+	if (clocks > DTL_TRRD_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
+	dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 30);
+	if (value < 0) return -1;
+	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+	if (clocks < DTL_TRAS_MIN) {
+		clocks = DTL_TRAS_MIN;
+	}
+	if (clocks > DTL_TRAS_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
+	dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 27);
+	if (value < 0) return -1;
+	clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
+	if (clocks < DTL_TRP_MIN) {
+		clocks = DTL_TRP_MIN;
+	}
+	if (clocks > DTL_TRP_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
+	dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dtl;
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
+	dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+}
+
+
+static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dth;
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
+	dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+}
+
+static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	u32 dth;
+	int value;
+	unsigned tref, old_tref;
+	value = spd_read_byte(ctrl->channel0[i], 3);
+	if (value < 0) return -1;
+	value &= 0xf;
+
+	tref = param->dch_tref8k;
+	if (value == 12) {
+		tref = param->dch_tref4k;
+	}
+
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
+	if ((value == 12) && (old_tref == param->dch_tref4k)) {
+		tref = param->dch_tref4k;
+	} else {
+		tref = param->dch_tref8k;
+	}
+	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
+	dth |= (tref << DTH_TREF_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	return 1;
+}
+
+
+static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	u32 dcl;
+	int value;
+#if QRANK_DIMM_SUPPORT == 1
+	int rank;
+#endif
+	int dimm;
+	value = spd_read_byte(ctrl->channel0[i], 13);
+	if (value < 0) {
+		return -1;
+	}
+
+#if QRANK_DIMM_SUPPORT == 1
+	rank = spd_read_byte(ctrl->channel0[i], 5);       /* number of physical banks */
+	if (rank < 0) {
+		return -1;	
+	}
+#endif
+
+	dimm = 1<<(DCL_x4DIMM_SHIFT+i);
+#if QRANK_DIMM_SUPPORT == 1
+	if(rank==4) {
+		dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
+	}
+#endif
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~dimm;
+	if (value == 4) {
+		dcl |= dimm;
+	}
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	return 1;
+}
+
+static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	u32 dcl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 11);
+	if (value < 0) {
+		return -1;
+	}
+	if (value != 2) {
+		dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+		dcl &= ~DCL_DimmEccEn;
+		pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	}
+	return 1;
+}
+
+static int count_dimms(const struct mem_controller *ctrl)
+{
+	int dimms;
+	unsigned index;
+	dimms = 0;
+	for(index = 0; index < 8; index += 2) {
+		u32 csbase;
+		csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2)));
+		if (csbase & 1) {
+			dimms += 1;
+		}
+	}
+	return dimms;
+}
+
+static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dth;
+
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
+	dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+}
+
+static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dth, dtl;
+	unsigned latency;
+	unsigned clocks;
+	int lat, mtype;
+
+	clocks = 0;
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
+
+	if (is_opteron(ctrl)) {
+		mtype = 0; /* dual channel */
+	} else if (is_registered(ctrl)) {
+		mtype = 1; /* registered 64bit interface */
+	} else {
+		mtype = 2; /* unbuffered 64bit interface */
+	}
+
+	switch (latency) {
+		case DTL_CL_2:
+			lat = 0;
+			break;
+		case DTL_CL_2_5:
+			lat = 1;
+			break;
+		case DTL_CL_3:
+			lat = 2;
+			break;
+		default:
+			die("Unknown LAT for Trwt");
+	}
+
+	clocks = param->dtl_trwt[lat][mtype];
+	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
+		die("Unknown Trwt\r\n");
+	}
+	
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
+	dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	return;
+}
+
+static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	/* Memory Clocks after CAS# */
+	u32 dth;
+	unsigned clocks;
+	if (is_registered(ctrl)) {
+		clocks = 2;
+	} else {
+		clocks = 1;
+	}
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
+	dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+}
+
+
+static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dch;
+	unsigned rdpreamble;
+	int slots, i;
+
+	slots = 0;
+
+	for(i = 0; i < 4; i++) {
+		if (ctrl->channel0[i]) {
+			slots += 1;
+		}
+	}
+
+	/* map to index to param.rdpreamble array */
+	if (is_registered(ctrl)) {
+		i = 0;
+	} else if (slots < 3) {
+		i = 1;
+	} else if (slots == 3) {
+		i = 2;
+	} else if (slots == 4) {
+		i = 3;
+	} else {
+		die("Unknown rdpreamble for this nr of slots");
+	}
+
+	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
+	rdpreamble = param->rdpreamble[i];
+
+	if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
+		die("Unknown rdpreamble");
+	}
+
+	dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+}
+
+static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dch;
+	unsigned async_lat;
+	int dimms;
+
+	dimms = count_dimms(ctrl);
+
+	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
+	async_lat = 0;
+	if (is_registered(ctrl)) {
+		if (dimms == 4) {
+			/* 9ns */
+			async_lat = 9;
+		} 
+		else {
+			/* 8ns */
+			async_lat = 8;
+		}
+	}
+	else {
+		if (dimms > 3) {
+			die("Too many unbuffered dimms");
+		}
+		else if (dimms == 3) {
+			/* 7ns */
+			async_lat = 7;
+		}
+		else {
+			/* 6ns */
+			async_lat = 6;
+		}
+	}
+	dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+}
+
+static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dch;
+	/* AMD says to Hardcode this */
+	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
+	dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
+	dch |= DCH_DYN_IDLE_CTR_EN;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+}
+
+static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
+{
+	int i;
+	
+	init_Tref(ctrl, param);
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		int rc;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		/* DRAM Timing Low Register */
+		if ((rc = update_dimm_Trc (ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trfc(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trcd(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trrd(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Tras(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trp (ctrl, param, i)) <= 0) goto dimm_err;
+
+		/* DRAM Timing High Register */
+		if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err;
+	
+
+		/* DRAM Config Low */
+		if ((rc = update_dimm_x4 (ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_ecc(ctrl, param, i)) <= 0) goto dimm_err;
+		continue;
+	dimm_err:
+		if (rc < 0) {
+			return -1;
+		}
+		dimm_mask = disable_dimm(ctrl, i, dimm_mask);
+	}
+	/* DRAM Timing Low Register */
+	set_Twr(ctrl, param);
+
+	/* DRAM Timing High Register */
+	set_Twtr(ctrl, param);
+	set_Trwt(ctrl, param);
+	set_Twcl(ctrl, param);
+
+	/* DRAM Config High */
+	set_read_preamble(ctrl, param);
+	set_max_async_latency(ctrl, param);
+	set_idle_cycle_limit(ctrl, param);
+	return dimm_mask;
+}
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) 
+{
+	struct spd_set_memclk_result result;
+	const struct mem_param *param;
+	long dimm_mask;
+	if (!controller_present(ctrl)) {
+		printk(BIOS_DEBUG, "No memory controller present\r\n");
+		return;
+	}
+	hw_enable_ecc(ctrl);
+	activate_spd_rom(ctrl);
+	dimm_mask = spd_detect_dimms(ctrl);
+	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
+		printk(BIOS_DEBUG, "No memory for this cpu\r\n");
+		return;
+	}
+	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);        
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	dimm_mask = spd_set_ram_size(ctrl , dimm_mask);           
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask); 
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	result = spd_set_memclk(ctrl, dimm_mask);
+	param     = result.param;
+	dimm_mask = result.dimm_mask;
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	dimm_mask = spd_set_dram_timing(ctrl, param , dimm_mask);
+	if (dimm_mask < 0)
+		goto hw_spd_err;
+	order_dimms(ctrl);
+	return;
+ hw_spd_err:
+	/* Unrecoverable error reading SPD data */
+	print_err("SPD error - reset\r\n");
+	hard_reset();
+	return;
+}
+
+#if HW_MEM_HOLE_SIZEK != 0
+static u32 hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
+{
+        int ii;
+        u32 carry_over;
+        struct device *dev;
+        u32 base, limit;
+        u32 basek;
+        u32 hoist;
+        int j;
+
+        carry_over = (4*1024*1024) - hole_startk;
+
+        for(ii=controllers - 1;ii>i;ii--) {
+                base  = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
+                if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+                        continue;
+                }
+		limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
+                for(j = 0; j < controllers; j++) {
+                        pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
+                        pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
+                }
+        }
+        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+        for(j = 0; j < controllers; j++) {
+                pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
+        }
+        dev = ctrl[i].f1;
+        base  = pci_read_config32(dev, 0x40 + (i << 3));
+        basek  = (base & 0xffff0000) >> 2;
+        if(basek == hole_startk) {
+                //don't need set memhole here, because hole off set will be 0, overflow
+                //so need to change base reg instead, new basek will be 4*1024*1024
+                base &= 0x0000ffff;
+                base |= (4*1024*1024)<<2;
+                for(j = 0; j < controllers; j++) {
+                        pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
+                }
+        }
+	else {
+        	hoist = /* hole start address */
+                	((hole_startk << 10) & 0xff000000) +
+	                /* hole address to memory controller address */
+        	        (((basek + carry_over) >> 6) & 0x0000ff00) +
+                	/* enable */
+	                1;
+	        pci_write_config32(dev, 0xf0, hoist);
+	}
+
+        return carry_over;
+}
+
+static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
+{
+
+        u32 hole_startk;
+        int i;
+
+        hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
+
+#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 
+	/* We need to double check if hole_startk is valid.
+	 * If it is equal to the dram base address in K (base_k), 
+	 * we need to decrease it.
+	 */
+        u32 basek_pri;
+        for(i=0; i<controllers; i++) {
+                        u32 base;
+                        unsigned base_k;
+                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+                                continue;
+                        }
+                        base_k = (base & 0xffff0000) >> 2;
+                        if(base_k == hole_startk) {
+				/* decrease memory hole startk to make sure it is
+				 * in the middle of the previous node 
+				 */
+                                hole_startk -= (base_k - basek_pri)>>1; 
+                                break; /* only one hole */
+                        }
+                        basek_pri = base_k;
+        }
+
+#endif
+        /* Find node number that needs the memory hole configured */
+        for(i=0; i<controllers; i++) {
+                        u32 base, limit;
+                        unsigned base_k, limit_k;
+                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+                                continue;
+                        }
+                        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+                        base_k = (base & 0xffff0000) >> 2;
+                        limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
+			if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
+                                unsigned end_k;
+                                hoist_memory(controllers, ctrl, hole_startk, i);
+                                end_k = memory_end_k(ctrl, controllers);
+                                set_top_mem(end_k, hole_startk);
+                                break; /* only one hole */
+                        }
+        }
+
+}
+
+#endif
+
+#define TIMEOUT_LOOPS 300000
+static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
+{
+	int i;
+
+	/* Error if I don't have memory */
+	if (memory_end_k(ctrl, controllers) == 0) {
+		die("No memory\r\n");
+	}
+
+	/* Before enabling memory start the memory clocks */
+	for(i = 0; i < controllers; i++) {
+		u32 dch;
+		if (!controller_present(ctrl + i))
+			continue;
+		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
+			dch |= DCH_MEMCLK_VALID;
+			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
+		}
+		else {
+			/* Disable dram receivers */
+			u32 dcl;
+			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			dcl |= DCL_DisInRcvrs;
+			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		}
+	}
+
+	/* And if necessary toggle the the reset on the dimms by hand */
+	memreset(controllers, ctrl);
+
+	/* We need to wait a mimmium of 20 MEMCLKS to enable the  InitDram */
+
+	for(i = 0; i < controllers; i++) {
+		u32 dcl, dch;
+		if (!controller_present(ctrl + i))
+			continue;
+		/* Skip everything if I don't have any memory on this controller */
+		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		if (!(dch & DCH_MEMCLK_VALID)) {
+			continue;
+		}
+
+		/* Toggle DisDqsHys to get it working */
+		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+		if (dcl & DCL_DimmEccEn) {
+			u32 mnc;
+			print_spew("ECC enabled\r\n");
+			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
+			mnc |= MNC_ECC_EN;
+			if (dcl & DCL_128BitEn) {
+				mnc |= MNC_CHIPKILL_EN;
+			}
+			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
+		}
+		dcl |= DCL_DisDqsHys;
+		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		dcl &= ~DCL_DisDqsHys;
+		dcl &= ~DCL_DLL_Disable;
+		dcl &= ~DCL_D_DRV;
+		dcl &= ~DCL_QFC_EN;
+		dcl |= DCL_DramInit;
+		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+
+	}
+	for(i = 0; i < controllers; i++) {
+		u32 dcl, dch;
+		if (!controller_present(ctrl + i))
+			continue;
+		/* Skip everything if I don't have any memory on this controller */
+		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		if (!(dch & DCH_MEMCLK_VALID)) {
+			continue;
+		}
+
+		printk(BIOS_DEBUG, "Initializing memory: ");
+
+		int loops = 0;
+		do {
+			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			loops += 1;
+			if ((loops & 1023) == 0) {
+				printk(BIOS_DEBUG, ".");
+			}
+		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
+		if (loops >= TIMEOUT_LOOPS) {
+			printk(BIOS_DEBUG, " failed\r\n");
+			continue;
+		}
+
+		if (!is_cpu_pre_c0()) {
+			/* Wait until it is safe to touch memory */
+			dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
+			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+			do {
+				dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
+		}
+
+		printk(BIOS_DEBUG, " done\r\n");
+	}
+
+#if HW_MEM_HOLE_SIZEK != 0
+         // init hw mem hole here
+        /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
+	if(!is_cpu_pre_e0())
+	        set_hw_mem_hole(controllers, ctrl);
+#endif
+
+	//FIXME add enable node interleaving here -- yhlu
+	/*needed?
+		1. check how many nodes we have , if not all has ram installed get out
+		2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
+		3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out
+		4. if all ready enable node_interleaving in f1 0x40..... of every node
+		5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
+	*/
+
+}
+
+static void set_sysinfo_in_ram(unsigned val)
+{
+}
+
+static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const u16 *spd_addr)
+{
+        int i;
+        int j;
+        struct mem_controller *ctrl;
+        for(i=0;i<controllers; i++) {
+                ctrl = &ctrl_a[i];
+                ctrl->node_id = i;
+                ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
+                ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
+                ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
+                ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
+
+                if(spd_addr == (void *)0) continue;
+
+                for(j=0;j<DIMM_SOCKETS;j++) {
+                        ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
+                        ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
+                }
+        }
+}
+#endif
+
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
+ * Copyright (C) 2004 YingHai Lu
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+/*	This should be done by Eric
+	2004.11 yhlu add 4 rank DIMM support
+	2004.12 yhlu add D0 support
+	2005.02 yhlu add E0 memory hole support
+*/
+/* not yet 
+#if K8_REV_F_SUPPORT == 1
+        #include "raminit_f.c"
+#else
+ */
+
+#include <mem.h>
+#include <cache.h>
+#include <mtrr.h>
+#include "raminit.h"
+#include "k8.h"
+#include "sysconf.h"
+
+#ifndef QRANK_DIMM_SUPPORT
+#define QRANK_DIMM_SUPPORT 0
+#endif
+
+static void hard_reset(void);
+
+static void setup_resource_map(const unsigned int *register_values, int max)
+{
+	int i;
+	printk(BIOS_DEBUG, "setting up resource map....");
+	for(i = 0; i < max; i += 3) {
+		struct device *dev;
+		unsigned where;
+		unsigned long reg;
+		printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+		dev = register_values[i] & ~0xfff;
+		where = register_values[i] & 0xfff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		pci_write_config32(dev, where, reg);
+	}
+	printk(BIOS_DEBUG, "done.\r\n");
+}
+
+static int controller_present(const struct mem_controller *ctrl)
+{
+        return pci_read_config32(ctrl->f0, 0) == 0x11001022;
+}
+
+static void sdram_set_registers(const struct mem_controller *ctrl)
+{
+	static const unsigned int register_values[] = {
+
+	/* Careful set limit registers before base registers which contain the enables */
+	/* DRAM Limit i Registers
+	 * F1:0x44 i = 0
+	 * F1:0x4C i = 1
+	 * F1:0x54 i = 2
+	 * F1:0x5C i = 3
+	 * F1:0x64 i = 4
+	 * F1:0x6C i = 5
+	 * F1:0x74 i = 6
+	 * F1:0x7C i = 7
+	 * [ 2: 0] Destination Node ID
+	 *	   000 = Node 0
+	 *	   001 = Node 1
+	 *	   010 = Node 2
+	 *	   011 = Node 3
+	 *	   100 = Node 4
+	 *	   101 = Node 5
+	 *	   110 = Node 6
+	 *	   111 = Node 7
+	 * [ 7: 3] Reserved
+	 * [10: 8] Interleave select
+	 *	   specifies the values of A[14:12] to use with interleave enable.
+	 * [15:11] Reserved
+	 * [31:16] DRAM Limit Address i Bits 39-24
+	 *	   This field defines the upper address bits of a 40 bit  address
+	 *	   that define the end of the DRAM region.
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+	/* DRAM Base i Registers
+	 * F1:0x40 i = 0
+	 * F1:0x48 i = 1
+	 * F1:0x50 i = 2
+	 * F1:0x58 i = 3
+	 * F1:0x60 i = 4
+	 * F1:0x68 i = 5
+	 * F1:0x70 i = 6
+	 * F1:0x78 i = 7
+	 * [ 0: 0] Read Enable
+	 *	   0 = Reads Disabled
+	 *	   1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *	   0 = Writes Disabled
+	 *	   1 = Writes Enabled
+	 * [ 7: 2] Reserved
+	 * [10: 8] Interleave Enable
+	 *	   000 = No interleave
+	 *	   001 = Interleave on A[12] (2 nodes)
+	 *	   010 = reserved
+	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+	 *	   100 = reserved
+	 *	   101 = reserved
+	 *	   110 = reserved
+	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+	 * [15:11] Reserved
+	 * [13:16] DRAM Base Address i Bits 39-24
+	 *	   This field defines the upper address bits of a 40-bit address
+	 *	   that define the start of the DRAM region.
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+	/* DRAM CS Base Address i Registers
+	 * F2:0x40 i = 0
+	 * F2:0x44 i = 1
+	 * F2:0x48 i = 2
+	 * F2:0x4C i = 3
+	 * F2:0x50 i = 4
+	 * F2:0x54 i = 5
+	 * F2:0x58 i = 6
+	 * F2:0x5C i = 7
+	 * [ 0: 0] Chip-Select Bank Enable
+	 *	   0 = Bank Disabled
+	 *	   1 = Bank Enabled
+	 * [ 8: 1] Reserved
+	 * [15: 9] Base Address (19-13)
+	 *	   An optimization used when all DIMM are the same size...
+	 * [20:16] Reserved
+	 * [31:21] Base Address (35-25)
+	 *	   This field defines the top 11 addresses bit of a 40-bit
+	 *	   address that define the memory address space.  These
+	 *	   bits decode 32-MByte blocks of memory.
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x58), 0x001f01fe, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x5C), 0x001f01fe, 0x00000000,
+	/* DRAM CS Mask Address i Registers
+	 * F2:0x60 i = 0
+	 * F2:0x64 i = 1
+	 * F2:0x68 i = 2
+	 * F2:0x6C i = 3
+	 * F2:0x70 i = 4
+	 * F2:0x74 i = 5
+	 * F2:0x78 i = 6
+	 * F2:0x7C i = 7
+	 * Select bits to exclude from comparison with the DRAM Base address register.
+	 * [ 8: 0] Reserved
+	 * [15: 9] Address Mask (19-13)
+	 *	   Address to be excluded from the optimized case
+	 * [20:16] Reserved
+	 * [29:21] Address Mask (33-25)
+	 *	   The bits with an address mask of 1 are excluded from address comparison
+	 * [31:30] Reserved
+	 * 
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x78), 0xC01f01ff, 0x00000000,
+	PCI_ADDR(0, 0x18, 2, 0x7C), 0xC01f01ff, 0x00000000,
+	/* DRAM Bank Address Mapping Register
+	 * F2:0x80
+	 * Specify the memory module size
+	 * [ 2: 0] CS1/0 
+	 * [ 6: 4] CS3/2
+	 * [10: 8] CS5/4
+	 * [14:12] CS7/6
+	 *	   000 = 32Mbyte  (Rows = 12 & Col =  8)
+	 *	   001 = 64Mbyte  (Rows = 12 & Col =  9)
+	 *	   010 = 128Mbyte (Rows = 13 & Col =  9)|(Rows = 12 & Col = 10)
+	 *	   011 = 256Mbyte (Rows = 13 & Col = 10)|(Rows = 12 & Col = 11)
+	 *	   100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10)
+	 *	   101 = 1Gbyte	  (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12)
+	 *	   110 = 2Gbyte	  (Rows = 14 & Col = 12)
+	 *	   111 = reserved 
+	 * [ 3: 3] Reserved
+	 * [ 7: 7] Reserved
+	 * [11:11] Reserved
+	 * [31:15]
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000000,
+	/* DRAM Timing Low Register
+	 * F2:0x88
+	 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
+	 *	   000 = reserved
+	 *	   001 = CL 2
+	 *	   010 = CL 3
+	 *	   011 = reserved
+	 *	   100 = reserved
+	 *	   101 = CL 2.5
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [ 3: 3] Reserved
+	 * [ 7: 4] Trc (Row Cycle Time, Ras#-active to Ras#-active/bank auto refresh)
+	 *	   0000 =  7 bus clocks
+	 *	   0001 =  8 bus clocks
+	 *	   ...
+	 *	   1110 = 21 bus clocks
+	 *	   1111 = 22 bus clocks
+	 * [11: 8] Trfc (Row refresh Cycle time, Auto-refresh-active to RAS#-active or RAS#auto-refresh)
+	 *	   0000 = 9 bus clocks
+	 *	   0010 = 10 bus clocks
+	 *	   ....
+	 *	   1110 = 23 bus clocks
+	 *	   1111 = 24 bus clocks
+	 * [14:12] Trcd (Ras#-active to Case#-read/write Delay)
+	 *	   000 = reserved
+	 *	   001 = reserved
+	 *	   010 = 2 bus clocks
+	 *	   011 = 3 bus clocks
+	 *	   100 = 4 bus clocks
+	 *	   101 = 5 bus clocks
+	 *	   110 = 6 bus clocks
+	 *	   111 = reserved
+	 * [15:15] Reserved
+	 * [18:16] Trrd (Ras# to Ras# Delay)
+	 *	   000 = reserved
+	 *	   001 = reserved
+	 *	   010 = 2 bus clocks
+	 *	   011 = 3 bus clocks
+	 *	   100 = 4 bus clocks
+	 *	   101 = reserved
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [19:19] Reserved
+	 * [23:20] Tras (Minmum Ras# Active Time)
+	 *	   0000 to 0100 = reserved
+	 *	   0101 = 5 bus clocks
+	 *	   ...
+	 *	   1111 = 15 bus clocks
+	 * [26:24] Trp (Row Precharge Time)
+	 *	   000 = reserved
+	 *	   001 = reserved
+	 *	   010 = 2 bus clocks
+	 *	   011 = 3 bus clocks
+	 *	   100 = 4 bus clocks
+	 *	   101 = 5 bus clocks
+	 *	   110 = 6 bus clocks
+	 *	   111 = reserved
+	 * [27:27] Reserved
+	 * [28:28] Twr (Write Recovery Time)
+	 *	   0 = 2 bus clocks
+	 *	   1 = 3 bus clocks
+	 * [31:29] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x02522001 /* 0x03623125 */ ,
+	/* DRAM Timing High Register
+	 * F2:0x8C
+	 * [ 0: 0] Twtr (Write to Read Delay)
+	 *	   0 = 1 bus Clocks
+	 *	   1 = 2 bus Clocks
+	 * [ 3: 1] Reserved
+	 * [ 6: 4] Trwt (Read to Write Delay)
+	 *	   000 = 1 bus clocks
+	 *	   001 = 2 bus clocks
+	 *	   010 = 3 bus clocks
+	 *	   011 = 4 bus clocks
+	 *	   100 = 5 bus clocks
+	 *	   101 = 6 bus clocks
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [ 7: 7] Reserved
+	 * [12: 8] Tref (Refresh Rate)
+	 *	   00000 = 100Mhz 4K rows
+	 *	   00001 = 133Mhz 4K rows
+	 *	   00010 = 166Mhz 4K rows
+	 *	   00011 = 200Mhz 4K rows
+	 *	   01000 = 100Mhz 8K/16K rows
+	 *	   01001 = 133Mhz 8K/16K rows
+	 *	   01010 = 166Mhz 8K/16K rows
+	 *	   01011 = 200Mhz 8K/16K rows
+	 * [19:13] Reserved
+	 * [22:20] Twcl (Write CAS Latency)
+	 *	   000 = 1 Mem clock after CAS# (Unbuffered Dimms)
+	 *	   001 = 2 Mem clocks after CAS# (Registered Dimms)
+	 * [31:23] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
+	/* DRAM Config Low Register
+	 * F2:0x90
+	 * [ 0: 0] DLL Disable
+	 *	   0 = Enabled
+	 *	   1 = Disabled
+	 * [ 1: 1] D_DRV
+	 *	   0 = Normal Drive
+	 *	   1 = Weak Drive
+	 * [ 2: 2] QFC_EN
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [ 3: 3] Disable DQS Hystersis  (FIXME handle this one carefully)
+	 *	   0 = Enable DQS input filter 
+	 *	   1 = Disable DQS input filtering 
+	 * [ 7: 4] Reserved
+	 * [ 8: 8] DRAM_Init
+	 *	   0 = Initialization done or not yet started.
+	 *	   1 = Initiate DRAM intialization sequence
+	 * [ 9: 9] SO-Dimm Enable
+	 *	   0 = Do nothing
+	 *	   1 = SO-Dimms present
+	 * [10:10] DramEnable
+	 *	   0 = DRAM not enabled
+	 *	   1 = DRAM initialized and enabled
+	 * [11:11] Memory Clear Status
+	 *	   0 = Memory Clear function has not completed
+	 *	   1 = Memory Clear function has completed
+	 * [12:12] Exit Self-Refresh
+	 *	   0 = Exit from self-refresh done or not yet started
+	 *	   1 = DRAM exiting from self refresh
+	 * [13:13] Self-Refresh Status
+	 *	   0 = Normal Operation
+	 *	   1 = Self-refresh mode active
+	 * [15:14] Read/Write Queue Bypass Count
+	 *	   00 = 2
+	 *	   01 = 4
+	 *	   10 = 8
+	 *	   11 = 16
+	 * [16:16] 128-bit/64-Bit
+	 *	   0 = 64bit Interface to DRAM
+	 *	   1 = 128bit Interface to DRAM
+	 * [17:17] DIMM ECC Enable
+	 *	   0 = Some DIMMs do not have ECC
+	 *	   1 = ALL DIMMS have ECC bits
+	 * [18:18] UnBuffered DIMMs
+	 *	   0 = Buffered DIMMS
+	 *	   1 = Unbuffered DIMMS
+	 * [19:19] Enable 32-Byte Granularity
+	 *	   0 = Optimize for 64byte bursts
+	 *	   1 = Optimize for 32byte bursts
+	 * [20:20] DIMM 0 is x4
+	 * [21:21] DIMM 1 is x4
+	 * [22:22] DIMM 2 is x4
+	 * [23:23] DIMM 3 is x4
+	 *	   0 = DIMM is not x4
+	 *	   1 = x4 DIMM present
+	 * [24:24] Disable DRAM Receivers
+	 *	   0 = Receivers enabled
+	 *	   1 = Receivers disabled
+	 * [27:25] Bypass Max
+	 *	   000 = Arbiters chois is always respected
+	 *	   001 = Oldest entry in DCQ can be bypassed 1 time
+	 *	   010 = Oldest entry in DCQ can be bypassed 2 times
+	 *	   011 = Oldest entry in DCQ can be bypassed 3 times
+	 *	   100 = Oldest entry in DCQ can be bypassed 4 times
+	 *	   101 = Oldest entry in DCQ can be bypassed 5 times
+	 *	   110 = Oldest entry in DCQ can be bypassed 6 times
+	 *	   111 = Oldest entry in DCQ can be bypassed 7 times
+	 * [31:28] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
+	(4 << 25)|(0 << 24)| 
+	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
+	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| 
+	(2 << 14)|(0 << 13)|(0 << 12)| 
+	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
+	(0 << 3) |(0 << 1) |(0 << 0),
+	/* DRAM Config High Register
+	 * F2:0x94
+	 * [ 0: 3] Maximum Asynchronous Latency
+	 *	   0000 = 0 ns
+	 *	   ...
+	 *	   1111 = 15 ns
+	 * [ 7: 4] Reserved
+	 * [11: 8] Read Preamble
+	 *	   0000 = 2.0 ns
+	 *	   0001 = 2.5 ns
+	 *	   0010 = 3.0 ns
+	 *	   0011 = 3.5 ns
+	 *	   0100 = 4.0 ns
+	 *	   0101 = 4.5 ns
+	 *	   0110 = 5.0 ns
+	 *	   0111 = 5.5 ns
+	 *	   1000 = 6.0 ns
+	 *	   1001 = 6.5 ns
+	 *	   1010 = 7.0 ns
+	 *	   1011 = 7.5 ns
+	 *	   1100 = 8.0 ns
+	 *	   1101 = 8.5 ns
+	 *	   1110 = 9.0 ns
+	 *	   1111 = 9.5 ns
+	 * [15:12] Reserved
+	 * [18:16] Idle Cycle Limit
+	 *	   000 = 0 cycles
+	 *	   001 = 4 cycles
+	 *	   010 = 8 cycles
+	 *	   011 = 16 cycles
+	 *	   100 = 32 cycles
+	 *	   101 = 64 cycles
+	 *	   110 = 128 cycles
+	 *	   111 = 256 cycles
+	 * [19:19] Dynamic Idle Cycle Center Enable
+	 *	   0 = Use Idle Cycle Limit
+	 *	   1 = Generate a dynamic Idle cycle limit
+	 * [22:20] DRAM MEMCLK Frequency
+	 *	   000 = 100Mhz
+	 *	   001 = reserved
+	 *	   010 = 133Mhz
+	 *	   011 = reserved
+	 *	   100 = reserved
+	 *	   101 = 166Mhz
+	 *	   110 = reserved
+	 *	   111 = reserved
+	 * [24:23] Reserved
+	 * [25:25] Memory Clock Ratio Valid (FIXME carefully enable memclk)
+	 *	   0 = Disable MemClks
+	 *	   1 = Enable MemClks
+	 * [26:26] Memory Clock 0 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [27:27] Memory Clock 1 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [28:28] Memory Clock 2 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [29:29] Memory Clock 3 Enable
+	 *	   0 = Disabled
+	 *	   1 = Enabled
+	 * [31:30] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0,
+	(0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)|
+	(0 << 20)|(0 << 19)|(DCH_IDLE_LIMIT_16 << 16)|(0 << 8)|(0 << 0),
+	/* DRAM Delay Line Register
+	 * F2:0x98
+	 * Adjust the skew of the input DQS strobe relative to DATA
+	 * [15: 0] Reserved
+	 * [23:16] Delay Line Adjust
+	 *	   Adjusts the DLL derived PDL delay by one or more delay stages
+	 *	   in either the faster or slower direction.
+	 * [24:24} Adjust Slower
+	 *	   0 = Do Nothing
+	 *	   1 = Adj is used to increase the PDL delay
+	 * [25:25] Adjust Faster
+	 *	   0 = Do Nothing
+	 *	   1 = Adj is used to decrease the PDL delay
+	 * [31:26] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
+	/* MCA NB Status Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
+	/* MCA NB Status high reg */
+	PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
+	/* MCA NB address Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
+	/* MCA NB address high reg */
+	PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
+	/* DRAM Scrub Control Register
+	 * F3:0x58
+	 * [ 4: 0] DRAM Scrube Rate
+	 * [ 7: 5] reserved
+	 * [12: 8] L2 Scrub Rate
+	 * [15:13] reserved
+	 * [20:16] Dcache Scrub
+	 * [31:21] reserved
+	 *	   Scrub Rates
+	 *	   00000 = Do not scrub
+	 *	   00001 =  40.00 ns
+	 *	   00010 =  80.00 ns
+	 *	   00011 = 160.00 ns
+	 *	   00100 = 320.00 ns
+	 *	   00101 = 640.00 ns
+	 *	   00110 =   1.28 us
+	 *	   00111 =   2.56 us
+	 *	   01000 =   5.12 us
+	 *	   01001 =  10.20 us
+	 *	   01011 =  41.00 us
+	 *	   01100 =  81.90 us
+	 *	   01101 = 163.80 us
+	 *	   01110 = 327.70 us
+	 *	   01111 = 655.40 us
+	 *	   10000 =   1.31 ms
+	 *	   10001 =   2.62 ms
+	 *	   10010 =   5.24 ms
+	 *	   10011 =  10.49 ms
+	 *	   10100 =  20.97 ms
+	 *	   10101 =  42.00 ms
+	 *	   10110 =  84.00 ms
+	 *	   All Others = Reserved
+	 */
+	PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
+	/* DRAM Scrub Address Low Register
+	 * F3:0x5C
+	 * [ 0: 0] DRAM Scrubber Redirect Enable
+	 *	   0 = Do nothing
+	 *	   1 = Scrubber Corrects errors found in normal operation
+	 * [ 5: 1] Reserved
+	 * [31: 6] DRAM Scrub Address 31-6
+	 */
+	PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
+	/* DRAM Scrub Address High Register
+	 * F3:0x60
+	 * [ 7: 0] DRAM Scrubb Address 39-32
+	 * [31: 8] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
+	};
+	int i;
+	int max;
+
+        if (!controller_present(ctrl)) {
+                printk(BIOS_DEBUG, "No memory controller present\r\n");
+                return;
+        }
+	printk(BIOS_SPEW, "setting up CPU 0x%x northbridge registers ", ctrl->node_id);
+	max = sizeof(register_values)/sizeof(register_values[0]);
+/*
+	for(i = 0; i < max; i += 3) {
+		struct device *dev;
+		unsigned where;
+		unsigned long reg;
+                printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+		dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
+		where = register_values[i] & 0xfff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		pci_write_config32(dev, where, reg);
+	}
+*/
+	printk(BIOS_SPEW, "done.\r\n");
+}
+
+
+static void hw_enable_ecc(const struct mem_controller *ctrl)
+{
+	u32 dcl, nbcap;
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~DCL_DimmEccEn;
+	if (nbcap & NBCAP_ECC) {
+		dcl |= DCL_DimmEccEn;
+	}
+	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+		dcl &= ~DCL_DimmEccEn;
+	}
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	
+}
+
+static int is_dual_channel(const struct mem_controller *ctrl)
+{
+	u32 dcl;
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	return dcl & DCL_128BitEn;
+}
+
+static int is_opteron(const struct mem_controller *ctrl)
+{
+	/* Test to see if I am an Opteron.  
+	 * FIXME Socket 939 based Athlon64 have dual channel capability,
+	 * too, so we need a better test for Opterons
+	 */
+#warning "FIXME: Implement a better test for Opterons"
+	u32 nbcap;
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	return !!(nbcap & NBCAP_128Bit);
+}
+
+static int is_registered(const struct mem_controller *ctrl)
+{
+	/* Test to see if we are dealing with registered SDRAM.
+	 * If we are not registered we are unbuffered.
+	 * This function must be called after spd_handle_unbuffered_dimms.
+	 */
+	u32 dcl;
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	return !(dcl & DCL_UnBufDimm);
+}
+
+struct dimm_size {
+	unsigned long side1;
+	unsigned long side2;
+	unsigned long rows;
+	unsigned long col;
+#if QRANK_DIMM_SUPPORT == 1
+	unsigned long rank;
+#endif
+};
+
+static struct dimm_size spd_get_dimm_size(unsigned device)
+{
+	/* Calculate the log base 2 size of a DIMM in bits */
+	struct dimm_size sz;
+	int value, low;
+	sz.side1 = 0;
+	sz.side2 = 0;
+	sz.rows = 0;
+	sz.col = 0;
+#if QRANK_DIMM_SUPPORT == 1
+	sz.rank = 0;
+#endif
+
+	/* Note it might be easier to use byte 31 here, it has the DIMM size as
+	 * a multiple of 4MB.  The way we do it now we can size both
+	 * sides of an assymetric dimm.
+	 */
+	value = spd_read_byte(device, 3);	/* rows */
+	if (value < 0) goto hw_err;
+	if ((value & 0xf) == 0) goto val_err;
+	sz.side1 += value & 0xf;
+	sz.rows = value & 0xf;
+
+	value = spd_read_byte(device, 4);	/* columns */
+	if (value < 0) goto hw_err;
+	if ((value & 0xf) == 0) goto val_err;
+	sz.side1 += value & 0xf;
+	sz.col = value & 0xf;
+
+	value = spd_read_byte(device, 17);	/* banks */
+	if (value < 0) goto hw_err;
+	if ((value & 0xff) == 0) goto val_err;
+	sz.side1 += log2(value & 0xff);
+
+	/* Get the module data width and convert it to a power of two */
+	value = spd_read_byte(device, 7);	/* (high byte) */
+	if (value < 0) goto hw_err;
+	value &= 0xff;
+	value <<= 8;
+	
+	low = spd_read_byte(device, 6);	/* (low byte) */
+	if (low < 0) goto hw_err;
+	value = value | (low & 0xff);
+	if ((value != 72) && (value != 64)) goto val_err;
+	sz.side1 += log2(value);
+
+	/* side 2 */
+	value = spd_read_byte(device, 5);	/* number of physical banks */
+	if (value < 0) goto hw_err;
+	if (value == 1) goto out;
+	if ((value != 2) && (value != 4 )) {
+		goto val_err;
+	}
+#if QRANK_DIMM_SUPPORT == 1
+	sz.rank = value;
+#endif
+
+	/* Start with the symmetrical case */
+	sz.side2 = sz.side1;
+
+	value = spd_read_byte(device, 3);	/* rows */
+	if (value < 0) goto hw_err;
+	if ((value & 0xf0) == 0) goto out;	/* If symmetrical we are done */
+	sz.side2 -= (value & 0x0f);		/* Subtract out rows on side 1 */
+	sz.side2 += ((value >> 4) & 0x0f);	/* Add in rows on side 2 */
+
+	value = spd_read_byte(device, 4);	/* columns */
+	if (value < 0) goto hw_err;
+	if ((value & 0xff) == 0) goto val_err;
+	sz.side2 -= (value & 0x0f);		/* Subtract out columns on side 1 */
+	sz.side2 += ((value >> 4) & 0x0f);	/* Add in columsn on side 2 */
+
+	goto out;
+
+ val_err:
+	die("Bad SPD value\r\n");
+	/* If an hw_error occurs report that I have no memory */
+hw_err:
+	sz.side1 = 0;
+	sz.side2 = 0;
+	sz.rows = 0;
+	sz.col = 0;
+#if QRANK_DIMM_SUPPORT == 1
+	sz.rank = 0;
+#endif
+ out:
+	return sz;
+}
+
+
+static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
+{
+	u32 base0, base1;
+	u32 dch;
+
+	if (sz.side1 != sz.side2) {
+		sz.side2 = 0;
+	}
+	
+	/* For each base register.
+	 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
+	 * The initialize dimm size is in bits.
+	 * Set the base enable bit0.
+	 */
+	
+	base0 = base1 = 0;
+
+	/* Make certain side1 of the dimm is at least 32MB */
+	if (sz.side1 >= (25 +3)) {
+		base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
+	}
+	
+	/* Make certain side2 of the dimm is at least 32MB */
+	if (sz.side2 >= (25 + 3)) {
+		base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1;
+	}
+
+	/* Double the size if we are using dual channel memory */
+	if (is_dual_channel(ctrl)) {
+		base0 = (base0 << 1) | (base0 & 1);
+		base1 = (base1 << 1) | (base1 & 1);
+	}
+
+	/* Clear the reserved bits */
+	base0 &= ~0x001ffffe;
+	base1 &= ~0x001ffffe;
+
+	/* Set the appropriate DIMM base address register */
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+#if QRANK_DIMM_SUPPORT == 1
+	if(sz.rank == 4) {
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
+	}
+#endif
+
+	/* Enable the memory clocks for this DIMM */
+	if (base0) {
+		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+		dch |= DCH_MEMCLK_EN0 << index;
+#if QRANK_DIMM_SUPPORT == 1
+		if(sz.rank == 4) {
+			dch |= DCH_MEMCLK_EN0 << (index + 2);
+		}
+#endif
+		pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	}
+}
+
+static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
+{
+	static const unsigned cs_map_aa[] = {
+		/* (row=12, col=8)(14, 12) ---> (0, 0) (2, 4) */
+		0, 1, 3, 6, 0,
+		0, 2, 4, 7, 9,
+		0, 0, 5, 8,10,
+	};
+
+	u32 map;
+	u32 dch;
+
+	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+	map &= ~(0xf << (index * 4));
+#if QRANK_DIMM_SUPPORT == 1
+        if(sz.rank == 4) {
+                map &= ~(0xf << ( (index + 2) * 4));
+        }
+#endif
+
+
+	/* Make certain side1 of the dimm is at least 32MB */
+	if (sz.side1 >= (25 +3)) {
+		if(is_cpu_pre_d0()) {
+			map |= (sz.side1 - (25 + 3)) << (index *4);
+#if QRANK_DIMM_SUPPORT == 1
+	                if(sz.rank == 4) {
+         	              map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
+               		}
+#endif
+		}
+		else {
+			map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
+#if QRANK_DIMM_SUPPORT == 1
+		        if(sz.rank == 4) {
+                	       map |=  cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
+               		}
+#endif
+		}
+	}
+
+	pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
+	
+}
+
+static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
+{
+	int i;
+	
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		struct dimm_size sz;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		sz = spd_get_dimm_size(ctrl->channel0[i]);
+		if (sz.side1 == 0) {
+			return -1; /* Report SPD error */
+		}
+		set_dimm_size(ctrl, sz, i);
+		set_dimm_map (ctrl, sz, i);
+	}
+	return dimm_mask;
+}
+
+static void route_dram_accesses(const struct mem_controller *ctrl,
+	unsigned long base_k, unsigned long limit_k)
+{
+	/* Route the addresses to the controller node */
+	unsigned node_id;
+	unsigned limit;
+	unsigned base;
+	unsigned index;
+	unsigned limit_reg, base_reg;
+	struct device *device;
+
+	node_id = ctrl->node_id;
+	index = (node_id << 3);
+	limit = (limit_k << 2);
+	limit &= 0xffff0000;
+	limit -= 0x00010000;
+	limit |= ( 0 << 8) | (node_id << 0);
+	base = (base_k << 2);
+	base &= 0xffff0000;
+	base |= (0 << 8) | (1<<1) | (1<<0);
+
+	limit_reg = 0x44 + index;
+	base_reg = 0x40 + index;
+	for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
+		pci_write_config32(device, limit_reg, limit);
+		pci_write_config32(device, base_reg, base);
+	}
+}
+
+static void set_top_mem(unsigned tom_k, unsigned hole_startk)
+{
+	/* Error if I don't have memory */
+	if (!tom_k) {
+		die("No memory?");
+	}
+
+	/* Report the amount of memory. */
+	print_spew("RAM: 0x");
+	print_spew_hex32(tom_k);
+	print_spew(" KB\r\n");
+
+	/* Now set top of memory */
+	msr_t msr;
+	if(tom_k > (4*1024*1024)) {
+		msr.lo = (tom_k & 0x003fffff) << 10;
+		msr.hi = (tom_k & 0xffc00000) >> 22;
+		wrmsr(TOP_MEM2, msr);
+	}
+
+	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
+	 * so I can see my rom chip and other I/O devices.
+	 */
+	if (tom_k >= 0x003f0000) {
+#if HW_MEM_HOLE_SIZEK != 0
+                if(hole_startk != 0) {
+                        tom_k = hole_startk;
+                } else
+#endif
+                tom_k = 0x3f0000;
+	}
+	msr.lo = (tom_k & 0x003fffff) << 10;
+	msr.hi = (tom_k & 0xffc00000) >> 22;
+	wrmsr(TOP_MEM, msr);
+}
+
+static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
+{
+	/* 35 - 25 */
+	static const u8 csbase_low_shift[] = { 
+	/* 32MB */	(13 - 4),
+	/* 64MB */	(14 - 4),
+	/* 128MB */	(14 - 4), 
+	/* 256MB */	(15 - 4),
+	/* 512MB */	(15 - 4),
+	/* 1GB */	(16 - 4),
+	/* 2GB */	(16 - 4), 
+	};
+
+        static const u8 csbase_low_d0_shift[] = {
+        /* 32MB */      (13 - 4),
+        /* 64MB */      (14 - 4),
+        /* 128MB */     (14 - 4),
+	/* 128MB */     (15 - 4),
+        /* 256MB */     (15 - 4),
+        /* 512MB */     (15 - 4),
+        /* 256MB */     (16 - 4),
+        /* 512MB */     (16 - 4),
+        /* 1GB */       (16 - 4),
+	/* 1GB */       (17 - 4),
+        /* 2GB */       (17 - 4),
+        };
+
+	/* cs_base_high is not changed */
+
+	u32 csbase_inc;
+	int chip_selects, index;
+	int bits;
+	unsigned common_size;
+	unsigned common_cs_mode;
+	u32 csbase, csmask;
+
+	/* See if all of the memory chip selects are the same size
+	 * and if so count them.
+	 */
+	chip_selects = 0;
+	common_size = 0;
+	common_cs_mode = 0;
+	for(index = 0; index < 8; index++) {
+		unsigned size;
+		unsigned cs_mode;
+		u32 value;
+		
+		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+		
+		/* Is it enabled? */
+		if (!(value & 1)) {
+			continue;
+		}
+		chip_selects++;
+		size = value >> 21;
+		if (common_size == 0) {
+			common_size = size;
+		}
+		/* The size differed fail */
+		if (common_size != size) {
+			return 0;
+		}
+
+		value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+                cs_mode =( value >> ((index>>1)*4)) & 0xf;
+                if(cs_mode == 0 ) continue;
+                if(common_cs_mode == 0) {
+                	common_cs_mode = cs_mode;
+                }
+                /* The size differed fail */
+                if(common_cs_mode != cs_mode) {
+                        return 0;
+                }
+	}
+
+	/* Chip selects can only be interleaved when there is
+	 * more than one and their is a power of two of them.
+	 */
+	bits = log2(chip_selects);
+	if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
+		return 0;
+	}
+
+	/* Find the bits of csbase that we need to interleave on */
+	if(is_cpu_pre_d0()){
+		csbase_inc = 1 << csbase_low_shift[common_cs_mode];
+		if(is_dual_channel(ctrl)) {
+                /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
+	                if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
+//     		                printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\r\n");
+	                        return 0;
+                	}  
+			csbase_inc <<=1;
+		}
+	}
+	else {
+		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
+		if(is_dual_channel(ctrl)) {
+	                if( (bits==3) && (common_cs_mode > 8)) {
+//        	                printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\r\n");
+        	                return 0;
+			}
+			csbase_inc <<=1;
+                }   
+	}
+
+	/* Compute the initial values for csbase and csbask. 
+	 * In csbase just set the enable bit and the base to zero.
+	 * In csmask set the mask bits for the size and page level interleave.
+	 */
+	csbase = 0 | 1;
+	csmask = (((common_size  << bits) - 1) << 21);
+	csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc);
+	for(index = 0; index < 8; index++) {
+		u32 value;
+
+		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+		/* Is it enabled? */
+		if (!(value & 1)) {
+			continue;
+		}
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
+		pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
+		csbase += csbase_inc;
+	}
+	
+	printk(BIOS_SPEW, "Interleaved\n");
+
+	/* Return the memory size in K */
+	return common_size << (15 + bits);
+}
+
+static unsigned long order_chip_selects(const struct mem_controller *ctrl)
+{
+	unsigned long tom;
+
+	/* Remember which registers we have used in the high 8 bits of tom */
+	tom = 0;
+	for(;;) {
+		/* Find the largest remaining canidate */
+		unsigned index, canidate;
+		u32 csbase, csmask;
+		unsigned size;
+		csbase = 0;
+		canidate = 0;
+		for(index = 0; index < 8; index++) {
+			u32 value;
+			value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+
+			/* Is it enabled? */
+			if (!(value & 1)) {
+				continue;
+			}
+			
+			/* Is it greater? */
+			if (value <= csbase) {
+				continue;
+			}
+			
+			/* Has it already been selected */
+			if (tom & (1 << (index + 24))) {
+				continue;
+			}
+			/* I have a new canidate */
+			csbase = value;
+			canidate = index;
+		}
+		/* See if I have found a new canidate */
+		if (csbase == 0) {
+			break;
+		}
+
+		/* Remember the dimm size */
+		size = csbase >> 21;
+
+		/* Remember I have used this register */
+		tom |= (1 << (canidate + 24));
+
+		/* Recompute the cs base register value */
+		csbase = (tom << 21) | 1;
+
+		/* Increment the top of memory */
+		tom += size;
+
+		/* Compute the memory mask */
+		csmask = ((size -1) << 21);
+		csmask |= 0xfe00;		/* For now don't optimize */
+
+		/* Write the new base register */
+		pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
+		/* Write the new mask register */
+		pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
+		
+	}
+	/* Return the memory size in K */
+	return (tom & ~0xff000000) << 15;
+}
+
+unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
+{
+	unsigned node_id;
+	unsigned end_k;
+	/* Find the last memory address used */
+	end_k = 0;
+	for(node_id = 0; node_id < max_node_id; node_id++) {
+		u32 limit, base;
+		unsigned index;
+		index = node_id << 3;
+		base = pci_read_config32(ctrl->f1, 0x40 + index);
+		/* Only look at the limit if the base is enabled */
+		if ((base & 3) == 3) {
+			limit = pci_read_config32(ctrl->f1, 0x44 + index);
+			end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
+		}
+	}
+	return end_k;
+}
+
+static void order_dimms(const struct mem_controller *ctrl)
+{
+	unsigned long tom_k, base_k;
+
+	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
+		tom_k = interleave_chip_selects(ctrl);
+	} else {
+		printk(BIOS_DEBUG, "Interleaving disabled\r\n");
+		tom_k = 0;
+	}
+	if (!tom_k) {
+		tom_k = order_chip_selects(ctrl);
+	}
+	/* Compute the memory base address */
+	base_k = memory_end_k(ctrl, ctrl->node_id);
+	tom_k += base_k;
+	route_dram_accesses(ctrl, base_k, tom_k);
+	set_top_mem(tom_k, 0);
+}
+
+static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
+{
+	printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index); 
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
+	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
+	dimm_mask &= ~(1 << index);
+	return dimm_mask;
+}
+
+static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask)
+{
+	int i;
+	int registered;
+	int unbuffered;
+	int has_dualch = is_opteron(ctrl);
+	u32 dcl;
+	unbuffered = 0;
+	registered = 0;
+	for(i = 0; (i < DIMM_SOCKETS); i++) {
+		int value;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		value = spd_read_byte(ctrl->channel0[i], 21);
+		if (value < 0) {
+			return -1;
+		}
+		/* Registered dimm ? */
+		if (value & (1 << 1)) {
+			registered = 1;
+		} 
+		/* Otherwise it must be an unbuffered dimm */
+		else {
+			unbuffered = 1;
+		}
+	}
+	if (unbuffered && registered) {
+		die("Mixed buffered and registered dimms not supported");
+	}
+
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~DCL_UnBufDimm;
+	if (unbuffered) {
+		if ((has_dualch) && (!is_cpu_pre_d0())) {
+			dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
+			
+			/* set DCL_En2T if you have non-equal DDR mem types! */
+			
+			if ((cpuid_eax(1) & 0x30) == 0x30) {
+				/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
+				dcl |= DCL_UpperCSMap;
+			}
+		} else {
+			dcl |= DCL_UnBufDimm;
+		}
+	}
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	if (is_registered(ctrl)) {
+		printk(BIOS_DEBUG, "Registered\r\n");
+	} else {
+		printk(BIOS_DEBUG, "Unbuffered\r\n");
+	}
+	return dimm_mask;
+}
+
+static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
+{
+	unsigned dimm_mask;
+	int i;
+	dimm_mask = 0;
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		int byte;
+		unsigned device;
+		device = ctrl->channel0[i];
+		if (device) {
+			byte = spd_read_byte(ctrl->channel0[i], 2);  /* Type */
+			if (byte == 7) {
+				dimm_mask |= (1 << i);
+			}
+		}
+		device = ctrl->channel1[i];
+		if (device) {
+			byte = spd_read_byte(ctrl->channel1[i], 2);
+			if (byte == 7) {
+				dimm_mask |= (1 << (i + DIMM_SOCKETS));
+			}
+		}
+	}
+	return dimm_mask;
+}
+
+static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask)
+{
+	int i;
+	u32 nbcap;
+	/* SPD addresses to verify are identical */
+	static const u8 addresses[] = {
+		2,	/* Type should be DDR SDRAM */
+		3,	/* *Row addresses */
+		4,	/* *Column addresses */
+		5,	/* *Physical Banks */
+		6,	/* *Module Data Width low */
+		7,	/* *Module Data Width high */
+		9,	/* *Cycle time at highest CAS Latency CL=X */
+		11,	/* *SDRAM Type */
+		13,	/* *SDRAM Width */
+		17,	/* *Logical Banks */
+		18,	/* *Supported CAS Latencies */
+		21,	/* *SDRAM Module Attributes */
+		23,	/* *Cycle time at CAS Latnecy (CLX - 0.5) */
+		26,	/* *Cycle time at CAS Latnecy (CLX - 1.0) */
+		27,	/* *tRP Row precharge time */
+		28,	/* *Minimum Row Active to Row Active Delay (tRRD) */
+		29,	/* *tRCD RAS to CAS */
+		30,	/* *tRAS Activate to Precharge */
+		41,	/* *Minimum Active to Active/Auto Refresh Time(Trc) */
+		42,	/* *Minimum Auto Refresh Command Time(Trfc) */
+	};
+	/* If the dimms are not in pairs do not do dual channels */
+	if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
+		((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { 
+		goto single_channel;
+	}
+	/* If the cpu is not capable of doing dual channels don't do dual channels */
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	if (!(nbcap & NBCAP_128Bit)) {
+		goto single_channel;
+	}
+	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+		unsigned device0, device1;
+		int value0, value1;
+		int j;
+		/* If I don't have a dimm skip this one */
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		device0 = ctrl->channel0[i];
+		device1 = ctrl->channel1[i];
+		for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
+			unsigned addr;
+			addr = addresses[j];
+			value0 = spd_read_byte(device0, addr);
+			if (value0 < 0) {
+				return -1;
+			}
+			value1 = spd_read_byte(device1, addr);
+			if (value1 < 0) {
+				return -1;
+			}
+			if (value0 != value1) {
+				goto single_channel;
+			}
+		}
+	}
+	printk(BIOS_SPEW, "Enabling dual channel memory\r\n");
+	u32 dcl;
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~DCL_32ByteEn;
+	dcl |= DCL_128BitEn;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	return dimm_mask;
+ single_channel:
+	dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
+	return dimm_mask;
+}
+
+struct mem_param {
+	u8 cycle_time;
+	u8 divisor; /* In 1/2 ns increments */
+	u8 tRC;
+	u8 tRFC;
+	u32 dch_memclk;
+	u16 dch_tref4k, dch_tref8k;
+	u8	 dtl_twr;
+	u8	 dtl_twtr;
+	u8  dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */
+ 	u8	 rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
+	char name[9];
+};
+
+static const struct mem_param *get_mem_param(unsigned min_cycle_time)
+{
+	static const struct mem_param speed[] = {
+		{
+			.name	    = "100Mhz\r\n",
+			.cycle_time = 0xa0,
+			.divisor    = (10 <<1),
+			.tRC	    = 0x46,
+			.tRFC	    = 0x50,
+			.dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_100MHZ_4K,
+			.dch_tref8k = DTH_TREF_100MHZ_8K,
+			.dtl_twr    = 2,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
+		},
+		{
+			.name	    = "133Mhz\r\n",
+			.cycle_time = 0x75,
+			.divisor    = (7<<1)+1,
+			.tRC	    = 0x41,
+			.tRFC	    = 0x4B,
+			.dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_133MHZ_4K,
+			.dch_tref8k = DTH_TREF_133MHZ_8K,
+			.dtl_twr    = 2,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
+		},
+		{
+			.name	    = "166Mhz\r\n",
+			.cycle_time = 0x60,
+			.divisor    = (6<<1),
+			.tRC	    = 0x3C,
+			.tRFC	    = 0x48,
+			.dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_166MHZ_4K,
+			.dch_tref8k = DTH_TREF_166MHZ_8K,
+			.dtl_twr    = 3,
+			.dtl_twtr   = 1,
+			.dtl_trwt   = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }},
+			.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
+		},
+		{
+			.name	    = "200Mhz\r\n",
+			.cycle_time = 0x50,
+			.divisor    = (5<<1),
+			.tRC	    = 0x37,
+			.tRFC	    = 0x46,
+			.dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
+			.dch_tref4k = DTH_TREF_200MHZ_4K,
+			.dch_tref8k = DTH_TREF_200MHZ_8K,
+			.dtl_twr    = 3,
+			.dtl_twtr   = 2,
+			.dtl_trwt   = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
+			.rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) }
+		},
+		{
+			.cycle_time = 0x00,
+		},
+	};
+	const struct mem_param *param;
+	for(param = &speed[0]; param->cycle_time ; param++) {
+		if (min_cycle_time > (param+1)->cycle_time) {
+			break;
+		}
+	}
+	if (!param->cycle_time) {
+		die("min_cycle_time to low");
+	}
+	print_spew(param->name);
+#ifdef DRAM_MIN_CYCLE_TIME
+	printk(BIOS_DEBUG, param->name);
+#endif
+	return param;
+}
+
+struct spd_set_memclk_result {
+	const struct mem_param *param;
+	long dimm_mask;
+};
+static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask)
+{
+	/* Compute the minimum cycle time for these dimms */
+	struct spd_set_memclk_result result;
+	unsigned min_cycle_time, min_latency, bios_cycle_time;
+	int i;
+	u32 value;
+
+	static const u8 latency_indicies[] = { 26, 23, 9 };
+	static const unsigned char min_cycle_times[] = {
+		[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
+		[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
+		[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
+		[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
+	};
+
+	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+
+	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
+	bios_cycle_time = min_cycle_times[
+		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
+	if (bios_cycle_time > min_cycle_time) {
+		min_cycle_time = bios_cycle_time;
+	}
+	min_latency = 2;
+
+	/* Compute the least latency with the fastest clock supported
+	 * by both the memory controller and the dimms.
+	 */
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		int new_cycle_time, new_latency;
+		int index;
+		int latencies;
+		int latency;
+
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+
+		/* First find the supported CAS latencies
+		 * Byte 18 for DDR SDRAM is interpreted:
+		 * bit 0 == CAS Latency = 1.0
+		 * bit 1 == CAS Latency = 1.5
+		 * bit 2 == CAS Latency = 2.0
+		 * bit 3 == CAS Latency = 2.5
+		 * bit 4 == CAS Latency = 3.0
+		 * bit 5 == CAS Latency = 3.5
+		 * bit 6 == TBD
+		 * bit 7 == TBD
+		 */
+		new_cycle_time = 0xa0;
+		new_latency = 5;
+
+		latencies = spd_read_byte(ctrl->channel0[i], 18);
+		if (latencies <= 0) continue;
+
+		/* Compute the lowest cas latency supported */
+		latency = log2(latencies) -2;
+
+		/* Loop through and find a fast clock with a low latency */
+		for(index = 0; index < 3; index++, latency++) {
+			int value;
+			if ((latency < 2) || (latency > 4) ||
+				(!(latencies & (1 << latency)))) {
+				continue;
+			}
+			value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+			if (value < 0) {
+				goto hw_error;
+			}
+
+			/* Only increase the latency if we decreas the clock */
+			if ((value >= min_cycle_time) && (value < new_cycle_time)) {
+				new_cycle_time = value;
+				new_latency = latency;
+			}
+		}
+		if (new_latency > 4){
+			continue;
+		}
+		/* Does min_latency need to be increased? */
+		if (new_cycle_time > min_cycle_time) {
+			min_cycle_time = new_cycle_time;
+		}
+		/* Does min_cycle_time need to be increased? */
+		if (new_latency > min_latency) {
+			min_latency = new_latency;
+		}
+	}
+	/* Make a second pass through the dimms and disable
+	 * any that cannot support the selected memclk and cas latency.
+	 */
+	
+	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+		int latencies;
+		int latency;
+		int index;
+		int value;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		latencies = spd_read_byte(ctrl->channel0[i], 18);
+		if (latencies < 0) goto hw_error;
+		if (latencies == 0) {
+			goto dimm_err;
+		}
+
+		/* Compute the lowest cas latency supported */
+		latency = log2(latencies) -2;
+
+		/* Walk through searching for the selected latency */
+		for(index = 0; index < 3; index++, latency++) {
+			if (!(latencies & (1 << latency))) {
+				continue;
+			}
+			if (latency == min_latency)
+				break;
+		}
+		/* If I can't find the latency or my index is bad error */
+		if ((latency != min_latency) || (index >= 3)) {
+			goto dimm_err;
+		}
+		
+		/* Read the min_cycle_time for this latency */
+		value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+		if (value < 0) goto hw_error;
+		
+		/* All is good if the selected clock speed 
+		 * is what I need or slower.
+		 */
+		if (value <= min_cycle_time) {
+			continue;
+		}
+		/* Otherwise I have an error, disable the dimm */
+	dimm_err:
+		dimm_mask = disable_dimm(ctrl, i, dimm_mask);
+	}
+#if 0
+//down speed for full load 4 rank support
+#if QRANK_DIMM_SUPPORT
+	if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
+		int ranks = 4;
+	        for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
+			int val;
+                	if (!(dimm_mask & (1 << i))) {
+                        	continue;
+	                }
+        	        val = spd_read_byte(ctrl->channel0[i], 5);
+			if(val!=ranks) {
+				ranks = val;
+				break;
+			}
+		}
+		if(ranks==4) {
+			if(min_cycle_time <= 0x50 ) {
+				min_cycle_time = 0x60;
+			}
+		}
+		
+	}
+#endif
+#endif
+	/* Now that I know the minimum cycle time lookup the memory parameters */
+	result.param = get_mem_param(min_cycle_time);
+
+	/* Update DRAM Config High with our selected memory speed */
+	value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
+#if 0
+	/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed 
+	 * result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 
+	 * and higher speeds with certain DIMM loadings ---- cheating???*/
+	if(!is_cpu_pre_e0()) {
+		if(min_cycle_time==0x50) {
+			value |= 1<<31;
+		}
+	}
+#endif
+
+	value |= result.param->dch_memclk;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
+
+	static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
+	/* Update DRAM Timing Low with our selected cas latency */
+	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
+	value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
+	
+	result.dimm_mask = dimm_mask;
+	return result;
+ hw_error:
+	result.param = (const struct mem_param *)0;
+	result.dimm_mask = -1;
+	return result;
+}
+
+
+static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 41);
+	if (value < 0) return -1;
+	if ((value == 0) || (value == 0xff)) {
+		value = param->tRC;
+	}
+	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+	if (clocks < DTL_TRC_MIN) {
+		clocks = DTL_TRC_MIN;
+	}
+	if (clocks > DTL_TRC_MAX) {
+		return 0;
+	}
+
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
+	dtl |=	((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 42);
+	if (value < 0) return -1;
+	if ((value == 0) || (value == 0xff)) {
+		value = param->tRFC;
+	}
+	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+	if (clocks < DTL_TRFC_MIN) {
+		clocks = DTL_TRFC_MIN;
+	}
+	if (clocks > DTL_TRFC_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
+	dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+
+static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 29);
+	if (value < 0) return -1;
+	clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
+	if (clocks < DTL_TRCD_MIN) {
+		clocks = DTL_TRCD_MIN;
+	}
+	if (clocks > DTL_TRCD_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
+	dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 28);
+	if (value < 0) return -1;
+	clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
+	if (clocks < DTL_TRRD_MIN) {
+		clocks = DTL_TRRD_MIN;
+	}
+	if (clocks > DTL_TRRD_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
+	dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 30);
+	if (value < 0) return -1;
+	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
+	if (clocks < DTL_TRAS_MIN) {
+		clocks = DTL_TRAS_MIN;
+	}
+	if (clocks > DTL_TRAS_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
+	dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	unsigned clocks, old_clocks;
+	u32 dtl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 27);
+	if (value < 0) return -1;
+	clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
+	if (clocks < DTL_TRP_MIN) {
+		clocks = DTL_TRP_MIN;
+	}
+	if (clocks > DTL_TRP_MAX) {
+		return 0;
+	}
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
+	if (old_clocks > clocks) {
+		clocks = old_clocks;
+	}
+	dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
+	dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	return 1;
+}
+
+static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dtl;
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
+	dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
+	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+}
+
+
+static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dth;
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
+	dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+}
+
+static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	u32 dth;
+	int value;
+	unsigned tref, old_tref;
+	value = spd_read_byte(ctrl->channel0[i], 3);
+	if (value < 0) return -1;
+	value &= 0xf;
+
+	tref = param->dch_tref8k;
+	if (value == 12) {
+		tref = param->dch_tref4k;
+	}
+
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
+	if ((value == 12) && (old_tref == param->dch_tref4k)) {
+		tref = param->dch_tref4k;
+	} else {
+		tref = param->dch_tref8k;
+	}
+	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
+	dth |= (tref << DTH_TREF_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	return 1;
+}
+
+
+static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	u32 dcl;
+	int value;
+#if QRANK_DIMM_SUPPORT == 1
+	int rank;
+#endif
+	int dimm;
+	value = spd_read_byte(ctrl->channel0[i], 13);
+	if (value < 0) {
+		return -1;
+	}
+
+#if QRANK_DIMM_SUPPORT == 1
+	rank = spd_read_byte(ctrl->channel0[i], 5);       /* number of physical banks */
+	if (rank < 0) {
+		return -1;	
+	}
+#endif
+
+	dimm = 1<<(DCL_x4DIMM_SHIFT+i);
+#if QRANK_DIMM_SUPPORT == 1
+	if(rank==4) {
+		dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
+	}
+#endif
+	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl &= ~dimm;
+	if (value == 4) {
+		dcl |= dimm;
+	}
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	return 1;
+}
+
+static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+{
+	u32 dcl;
+	int value;
+	value = spd_read_byte(ctrl->channel0[i], 11);
+	if (value < 0) {
+		return -1;
+	}
+	if (value != 2) {
+		dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+		dcl &= ~DCL_DimmEccEn;
+		pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	}
+	return 1;
+}
+
+static int count_dimms(const struct mem_controller *ctrl)
+{
+	int dimms;
+	unsigned index;
+	dimms = 0;
+	for(index = 0; index < 8; index += 2) {
+		u32 csbase;
+		csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2)));
+		if (csbase & 1) {
+			dimms += 1;
+		}
+	}
+	return dimms;
+}
+
+static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dth;
+
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
+	dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+}
+
+static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dth, dtl;
+	unsigned latency;
+	unsigned clocks;
+	int lat, mtype;
+
+	clocks = 0;
+	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
+
+	if (is_opteron(ctrl)) {
+		mtype = 0; /* dual channel */
+	} else if (is_registered(ctrl)) {
+		mtype = 1; /* registered 64bit interface */
+	} else {
+		mtype = 2; /* unbuffered 64bit interface */
+	}
+
+	switch (latency) {
+		case DTL_CL_2:
+			lat = 0;
+			break;
+		case DTL_CL_2_5:
+			lat = 1;
+			break;
+		case DTL_CL_3:
+			lat = 2;
+			break;
+		default:
+			die("Unknown LAT for Trwt");
+	}
+
+	clocks = param->dtl_trwt[lat][mtype];
+	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
+		die("Unknown Trwt\r\n");
+	}
+	
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
+	dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	return;
+}
+
+static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	/* Memory Clocks after CAS# */
+	u32 dth;
+	unsigned clocks;
+	if (is_registered(ctrl)) {
+		clocks = 2;
+	} else {
+		clocks = 1;
+	}
+	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
+	dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+}
+
+
+static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dch;
+	unsigned rdpreamble;
+	int slots, i;
+
+	slots = 0;
+
+	for(i = 0; i < 4; i++) {
+		if (ctrl->channel0[i]) {
+			slots += 1;
+		}
+	}
+
+	/* map to index to param.rdpreamble array */
+	if (is_registered(ctrl)) {
+		i = 0;
+	} else if (slots < 3) {
+		i = 1;
+	} else if (slots == 3) {
+		i = 2;
+	} else if (slots == 4) {
+		i = 3;
+	} else {
+		die("Unknown rdpreamble for this nr of slots");
+	}
+
+	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
+	rdpreamble = param->rdpreamble[i];
+
+	if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
+		die("Unknown rdpreamble");
+	}
+
+	dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+}
+
+static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dch;
+	unsigned async_lat;
+	int dimms;
+
+	dimms = count_dimms(ctrl);
+
+	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
+	async_lat = 0;
+	if (is_registered(ctrl)) {
+		if (dimms == 4) {
+			/* 9ns */
+			async_lat = 9;
+		} 
+		else {
+			/* 8ns */
+			async_lat = 8;
+		}
+	}
+	else {
+		if (dimms > 3) {
+			die("Too many unbuffered dimms");
+		}
+		else if (dimms == 3) {
+			/* 7ns */
+			async_lat = 7;
+		}
+		else {
+			/* 6ns */
+			async_lat = 6;
+		}
+	}
+	dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+}
+
+static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
+{
+	u32 dch;
+	/* AMD says to Hardcode this */
+	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
+	dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
+	dch |= DCH_DYN_IDLE_CTR_EN;
+	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+}
+
+static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
+{
+	int i;
+	
+	init_Tref(ctrl, param);
+	for(i = 0; i < DIMM_SOCKETS; i++) {
+		int rc;
+		if (!(dimm_mask & (1 << i))) {
+			continue;
+		}
+		/* DRAM Timing Low Register */
+		if ((rc = update_dimm_Trc (ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trfc(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trcd(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trrd(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Tras(ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_Trp (ctrl, param, i)) <= 0) goto dimm_err;
+
+		/* DRAM Timing High Register */
+		if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err;
+	
+
+		/* DRAM Config Low */
+		if ((rc = update_dimm_x4 (ctrl, param, i)) <= 0) goto dimm_err;
+		if ((rc = update_dimm_ecc(ctrl, param, i)) <= 0) goto dimm_err;
+		continue;
+	dimm_err:
+		if (rc < 0) {
+			return -1;
+		}
+		dimm_mask = disable_dimm(ctrl, i, dimm_mask);
+	}
+	/* DRAM Timing Low Register */
+	set_Twr(ctrl, param);
+
+	/* DRAM Timing High Register */
+	set_Twtr(ctrl, param);
+	set_Trwt(ctrl, param);
+	set_Twcl(ctrl, param);
+
+	/* DRAM Config High */
+	set_read_preamble(ctrl, param);
+	set_max_async_latency(ctrl, param);
+	set_idle_cycle_limit(ctrl, param);
+	return dimm_mask;
+}
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) 
+{
+	struct spd_set_memclk_result result;
+	const struct mem_param *param;
+	long dimm_mask;
+	if (!controller_present(ctrl)) {
+		printk(BIOS_DEBUG, "No memory controller present\r\n");
+		return;
+	}
+	hw_enable_ecc(ctrl);
+	activate_spd_rom(ctrl);
+	dimm_mask = spd_detect_dimms(ctrl);
+	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
+		printk(BIOS_DEBUG, "No memory for this cpu\r\n");
+		return;
+	}
+	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);        
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	dimm_mask = spd_set_ram_size(ctrl , dimm_mask);           
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask); 
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	result = spd_set_memclk(ctrl, dimm_mask);
+	param     = result.param;
+	dimm_mask = result.dimm_mask;
+	if (dimm_mask < 0) 
+		goto hw_spd_err;
+	dimm_mask = spd_set_dram_timing(ctrl, param , dimm_mask);
+	if (dimm_mask < 0)
+		goto hw_spd_err;
+	order_dimms(ctrl);
+	return;
+ hw_spd_err:
+	/* Unrecoverable error reading SPD data */
+	print_err("SPD error - reset\r\n");
+	hard_reset();
+	return;
+}
+
+#if HW_MEM_HOLE_SIZEK != 0
+static u32 hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
+{
+        int ii;
+        u32 carry_over;
+        struct device *dev;
+        u32 base, limit;
+        u32 basek;
+        u32 hoist;
+        int j;
+
+        carry_over = (4*1024*1024) - hole_startk;
+
+        for(ii=controllers - 1;ii>i;ii--) {
+                base  = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
+                if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+                        continue;
+                }
+		limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
+                for(j = 0; j < controllers; j++) {
+                        pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
+                        pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
+                }
+        }
+        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+        for(j = 0; j < controllers; j++) {
+                pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
+        }
+        dev = ctrl[i].f1;
+        base  = pci_read_config32(dev, 0x40 + (i << 3));
+        basek  = (base & 0xffff0000) >> 2;
+        if(basek == hole_startk) {
+                //don't need set memhole here, because hole off set will be 0, overflow
+                //so need to change base reg instead, new basek will be 4*1024*1024
+                base &= 0x0000ffff;
+                base |= (4*1024*1024)<<2;
+                for(j = 0; j < controllers; j++) {
+                        pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
+                }
+        }
+	else {
+        	hoist = /* hole start address */
+                	((hole_startk << 10) & 0xff000000) +
+	                /* hole address to memory controller address */
+        	        (((basek + carry_over) >> 6) & 0x0000ff00) +
+                	/* enable */
+	                1;
+	        pci_write_config32(dev, 0xf0, hoist);
+	}
+
+        return carry_over;
+}
+
+static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
+{
+
+        u32 hole_startk;
+        int i;
+
+        hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
+
+#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 
+	/* We need to double check if hole_startk is valid.
+	 * If it is equal to the dram base address in K (base_k), 
+	 * we need to decrease it.
+	 */
+        u32 basek_pri;
+        for(i=0; i<controllers; i++) {
+                        u32 base;
+                        unsigned base_k;
+                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+                                continue;
+                        }
+                        base_k = (base & 0xffff0000) >> 2;
+                        if(base_k == hole_startk) {
+				/* decrease memory hole startk to make sure it is
+				 * in the middle of the previous node 
+				 */
+                                hole_startk -= (base_k - basek_pri)>>1; 
+                                break; /* only one hole */
+                        }
+                        basek_pri = base_k;
+        }
+
+#endif
+        /* Find node number that needs the memory hole configured */
+        for(i=0; i<controllers; i++) {
+                        u32 base, limit;
+                        unsigned base_k, limit_k;
+                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+                                continue;
+                        }
+                        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+                        base_k = (base & 0xffff0000) >> 2;
+                        limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
+			if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
+                                unsigned end_k;
+                                hoist_memory(controllers, ctrl, hole_startk, i);
+                                end_k = memory_end_k(ctrl, controllers);
+                                set_top_mem(end_k, hole_startk);
+                                break; /* only one hole */
+                        }
+        }
+
+}
+
+#endif
+
+#define TIMEOUT_LOOPS 300000
+static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
+{
+	int i;
+
+	/* Error if I don't have memory */
+	if (memory_end_k(ctrl, controllers) == 0) {
+		die("No memory\r\n");
+	}
+
+	/* Before enabling memory start the memory clocks */
+	for(i = 0; i < controllers; i++) {
+		u32 dch;
+		if (!controller_present(ctrl + i))
+			continue;
+		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
+			dch |= DCH_MEMCLK_VALID;
+			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
+		}
+		else {
+			/* Disable dram receivers */
+			u32 dcl;
+			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			dcl |= DCL_DisInRcvrs;
+			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		}
+	}
+
+	/* And if necessary toggle the the reset on the dimms by hand */
+	memreset(controllers, ctrl);
+
+	/* We need to wait a mimmium of 20 MEMCLKS to enable the  InitDram */
+
+	for(i = 0; i < controllers; i++) {
+		u32 dcl, dch;
+		if (!controller_present(ctrl + i))
+			continue;
+		/* Skip everything if I don't have any memory on this controller */
+		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		if (!(dch & DCH_MEMCLK_VALID)) {
+			continue;
+		}
+
+		/* Toggle DisDqsHys to get it working */
+		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+		if (dcl & DCL_DimmEccEn) {
+			u32 mnc;
+			print_spew("ECC enabled\r\n");
+			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
+			mnc |= MNC_ECC_EN;
+			if (dcl & DCL_128BitEn) {
+				mnc |= MNC_CHIPKILL_EN;
+			}
+			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
+		}
+		dcl |= DCL_DisDqsHys;
+		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		dcl &= ~DCL_DisDqsHys;
+		dcl &= ~DCL_DLL_Disable;
+		dcl &= ~DCL_D_DRV;
+		dcl &= ~DCL_QFC_EN;
+		dcl |= DCL_DramInit;
+		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+
+	}
+	for(i = 0; i < controllers; i++) {
+		u32 dcl, dch;
+		if (!controller_present(ctrl + i))
+			continue;
+		/* Skip everything if I don't have any memory on this controller */
+		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		if (!(dch & DCH_MEMCLK_VALID)) {
+			continue;
+		}
+
+		printk(BIOS_DEBUG, "Initializing memory: ");
+
+		int loops = 0;
+		do {
+			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			loops += 1;
+			if ((loops & 1023) == 0) {
+				printk(BIOS_DEBUG, ".");
+			}
+		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
+		if (loops >= TIMEOUT_LOOPS) {
+			printk(BIOS_DEBUG, " failed\r\n");
+			continue;
+		}
+
+		if (!is_cpu_pre_c0()) {
+			/* Wait until it is safe to touch memory */
+			dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
+			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+			do {
+				dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
+		}
+
+		printk(BIOS_DEBUG, " done\r\n");
+	}
+
+#if HW_MEM_HOLE_SIZEK != 0
+         // init hw mem hole here
+        /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
+	if(!is_cpu_pre_e0())
+	        set_hw_mem_hole(controllers, ctrl);
+#endif
+
+	//FIXME add enable node interleaving here -- yhlu
+	/*needed?
+		1. check how many nodes we have , if not all has ram installed get out
+		2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
+		3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out
+		4. if all ready enable node_interleaving in f1 0x40..... of every node
+		5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
+	*/
+
+}
+
+static void set_sysinfo_in_ram(unsigned val)
+{
+}
+
+static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const u16 *spd_addr)
+{
+        int i;
+        int j;
+        struct mem_controller *ctrl;
+        for(i=0;i<controllers; i++) {
+                ctrl = &ctrl_a[i];
+                ctrl->node_id = i;
+                ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
+                ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
+                ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
+                ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
+
+                if(spd_addr == (void *)0) continue;
+
+                for(j=0;j<DIMM_SOCKETS;j++) {
+                        ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
+                        ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
+                }
+        }
+}
+#endif
+

Added: coreboot-v3/southbridge/nvidia/mcp55/Makefile
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/Makefile	                        (rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/Makefile	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,32 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
+
+STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/mcp55.o
+
+ifeq ($(CONFIG_PIRQ_TABLE),y)
+STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/irq_tables.o
+endif
+
+STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o
+
+endif

Added: coreboot-v3/southbridge/nvidia/mcp55/dts
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/dts	                        (rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/dts	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 YingHai Lu
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	ide0_enable = "0";
+	ide1_enable = "0";
+	sata0_enable = "0";
+	sata1_enable = "0";
+	mac_eeprom_smbus = "0";
+	mac_eeprom_addr "0";
+};
+

Added: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c	                        (rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,257 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "mcp55.h"
+
+static uint32_t final_reg;
+
+static device_t find_lpc_dev( device_t dev,  unsigned devfn)
+{
+
+	device_t lpc_dev;
+
+	lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
+
+	if ( !lpc_dev ) return lpc_dev;
+
+	if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
+		(lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
+		(lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
+		) ) {
+			uint32_t id;
+			id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
+			if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
+				(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
+				) {
+				lpc_dev = 0;
+			}
+	}
+
+	return lpc_dev;
+}
+
+static void mcp55_enable(device_t dev)
+{
+	device_t lpc_dev = 0;
+	device_t sm_dev = 0;
+	unsigned index = 0;
+	unsigned index2 = 0;
+	uint32_t reg_old, reg;
+	uint8_t byte;
+	unsigned deviceid;
+	unsigned vendorid;
+
+	struct southbridge_nvidia_mcp55_config *conf;
+	conf = dev->chip_info;
+	int i;
+
+	unsigned devfn;
+
+	if(dev->device==0x0000) {
+		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
+		deviceid = (vendorid>>16) & 0xffff;
+//		vendorid &= 0xffff;
+	} else {
+//		vendorid = dev->vendor;
+		deviceid = dev->device;
+	}
+
+	devfn = (dev->path.u.pci.devfn) & ~7;
+	switch(deviceid) {
+		case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
+			return;
+
+		case PCI_DEVICE_ID_NVIDIA_MCP55_SM2://?
+			index = 16;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
+			devfn -= (1<<3);
+			index = 8;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
+			devfn -= (1<<3);
+			index = 20;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: //two
+		case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE://two
+			devfn -= (7<<3);
+			index = 10;
+			for(i=0;i<2;i++) {
+				lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
+				if(!lpc_dev) continue;
+				index -= i;
+				devfn -= (i<<3);
+				break;
+			}
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
+			devfn -= (5<<3);
+			index = 11;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
+			devfn -= (3<<3);
+			index = 14;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: //three
+		case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
+			devfn -= (4<<3);
+			index = 22;
+			i = (dev->path.u.pci.devfn) & 7;
+			if(i>0) {
+				index -= (i+3);
+			}
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
+			devfn -= (5<<3);
+			index = 15;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
+			devfn -= (0x9<<3);  // to LPC
+			index2 = 9;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: //two
+			devfn -= (0xa<<3);  // to LPC
+			index2 = 8;
+			for(i=0;i<2;i++) {
+				lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
+				if(!lpc_dev) continue;
+				index2 -= i;
+				devfn -= (i<<3);
+				break;
+			}
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
+			devfn -= (0xc<<3);  // to LPC
+			index2 = 6;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
+			devfn -= (0xd<<3);  // to LPC
+			index2 = 5;
+			break;
+		case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
+			devfn -= (0xe<<3);  // to LPC
+			index2 = 4;
+			break;
+		default:
+			index = 0;
+	}
+
+	if(!lpc_dev)
+		lpc_dev = find_lpc_dev(dev, devfn);
+
+	if ( !lpc_dev )	return;
+
+	if(index2!=0) {
+		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
+		if(!sm_dev) return;
+
+		if ( sm_dev ) {
+			reg_old = reg =  pci_read_config32(sm_dev, 0xe4);
+
+			if (!dev->enabled) { //disable it
+				reg |= (1<<index2);
+			}
+
+			if (reg != reg_old) {
+				pci_write_config32(sm_dev, 0xe4, reg);
+			}
+		}
+
+		index2 = 0;
+		return;
+	}
+
+
+	if ( index == 0) {  // for LPC
+
+		// expose ioapic base
+		byte = pci_read_config8(lpc_dev, 0x74);
+		byte |= ((1<<1)); // expose the BAR
+		pci_write_config8(dev, 0x74, byte);
+
+		// expose trap base
+		byte = pci_read_config8(lpc_dev, 0xdd);
+		byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
+		pci_write_config8(dev, 0xdd, byte);
+
+		return;
+
+	}
+
+	if( index == 16) {
+		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
+		if(!sm_dev) return;
+
+		final_reg = pci_read_config32(sm_dev, 0xe8);
+		final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
+		pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
+#if 0
+		reg_old = reg = pci_read_config32(sm_dev, 0xe4);
+//		reg |= (1<<0);
+		reg &= ~(0x3f<<4);
+		if (reg != reg_old) {
+			printk_debug("mcp55.c pcie enabled\n");
+			pci_write_config32(sm_dev, 0xe4, reg);
+		}
+#endif
+	}
+
+	if (!dev->enabled) {
+		final_reg |= (1 << index);// disable it
+		//The reason for using final_reg, if diable func 1, the func 2 will be func 1 so We need disable them one time.
+	}
+
+	if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
+		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
+		if(!sm_dev) return;
+		reg_old = pci_read_config32(sm_dev, 0xe8);
+		if (final_reg != reg_old) {
+			pci_write_config32(sm_dev, 0xe8, final_reg);
+		}
+
+	}
+
+
+}
+
+struct device_operations nvidia_ops = {
+	.id = {.type = DEVICE_ID_PCI,
+		.u = {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
+			      .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIBRIDGE}}},
+	.constructor			= default_device_constructor,
+	.phase3_scan			= scan_static_bus,
+	.phase4_read_resources		= pci_dev_read_resources,
+	.phase4_set_resources		= pci_dev_set_resources,
+	.phase5_enable_resources	= mcp55_enable,
+	.phase6_init			= NULL,
+};
+
+

Added: coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.h	                        (rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.h	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MCP55_H
+#define MCP55_H
+
+void mcp55_enable(device_t dev);
+
+#endif /* MCP55_H */

Added: coreboot-v3/southbridge/nvidia/mcp55/stage1.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1.c	                        (rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-08-02 03:34:05 UTC (rev 713)
@@ -0,0 +1,427 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static int set_ht_link_mcp55(u8 ht_c_num)
+{
+	unsigned vendorid = 0x10de;
+	unsigned val = 0x01610109;
+	/* Nvidia mcp55 hardcode, hw can not set it automatically */
+	return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
+}
+
+static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
+{
+	int i;
+
+	unsigned val;
+
+	val = inl(control);
+	val &= 0xfffffffe;
+	outl(val, control);
+
+	outl(0, index); //index
+	for(i = 0; i < max; i++) {
+		unsigned long reg;
+		reg = register_values[i];
+		outl(reg, where);
+	}
+
+	val = inl(control);
+	val |= 1;
+	outl(val, control);
+
+}
+
+/* SIZE 0x100 */
+#define ANACTRL_IO_BASE	0x2800
+#define ANACTRL_REG_POS	0x68
+
+/* SIZE 0x100 */
+#define SYSCTRL_IO_BASE	0x2400
+#define SYSCTRL_REG_POS	0x64
+
+/* SIZE 0x100 */
+#define ACPICTRL_IO_BASE	0x2000
+#define ACPICTRL_REG_POS	0x60
+
+/*
+	16 1 1 1 1 8 :0
+	16 0 4 0 0 8 :1
+	16 0 4 2 2 4 :2
+	 4 4 4 4 4 8 :3
+	 8 8 4 0 0 8 :4
+	 8 0 4 4 4 8 :5
+*/
+
+#ifndef MCP55_PCI_E_X_0
+	#define MCP55_PCI_E_X_0	4
+#endif
+#ifndef MCP55_PCI_E_X_1
+	#define MCP55_PCI_E_X_1	4
+#endif
+#ifndef MCP55_PCI_E_X_2
+	#define MCP55_PCI_E_X_2	4
+#endif
+#ifndef MCP55_PCI_E_X_3
+	#define MCP55_PCI_E_X_3	4
+#endif
+
+#ifndef MCP55_USE_NIC
+	#define MCP55_USE_NIC	0
+#endif
+
+#ifndef MCP55_USE_AZA
+	#define MCP55_USE_AZA	0
+#endif
+
+#define MCP55_CHIP_REV	3
+
+static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
+{
+
+	static const unsigned int ctrl_devport_conf[] = {
+		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
+		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
+		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
+	};
+
+	int j;
+	for(j = 0; j < mcp55_num; j++ ) {
+		setup_resource_map_offset(ctrl_devport_conf,
+			sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+	}
+}
+
+static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
+{
+
+	static const unsigned int ctrl_devport_conf_clear[] = {
+		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
+		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
+	};
+
+	int j;
+	for(j = 0; j < mcp55_num; j++ ) {
+		setup_resource_map_offset(ctrl_devport_conf_clear,
+			sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+	}
+
+
+}
+static void delayx(u8 value) {
+#if 1
+	int i;
+	for(i=0;i<0x8000;i++) {
+		outb(value, 0x80);
+	}
+#endif
+}
+
+static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
+{
+	u32 tgio_ctrl;
+	u32 pll_ctrl;
+	u32 dword;
+	int i;
+	device_t dev;
+	dev = PCI_DEV(busnx, devnx+1, 1);
+	dword = pci_read_config32(dev, 0xe4);
+	dword |= 0x3f0; // disable it at first
+	pci_write_config32(dev, 0xe4, dword);
+
+	for(i=0; i<3; i++) {
+		tgio_ctrl = inl(anactrl_io_base + 0xcc);
+		tgio_ctrl &= ~(3<<9);
+		tgio_ctrl |= (i<<9);
+		outl(tgio_ctrl, anactrl_io_base + 0xcc);
+		pll_ctrl = inl(anactrl_io_base + 0x30);
+		pll_ctrl |= (1<<31);
+		outl(pll_ctrl, anactrl_io_base + 0x30);
+		do {
+			pll_ctrl = inl(anactrl_io_base + 0x30);
+		} while (!(pll_ctrl & 1));
+	}
+	tgio_ctrl = inl(anactrl_io_base + 0xcc);
+	tgio_ctrl &= ~((7<<4)|(1<<8));
+	tgio_ctrl |= (pci_e_x<<4)|(1<<8);
+	outl(tgio_ctrl, anactrl_io_base + 0xcc);
+
+//	wait 100us
+	delayx(1);
+
+	dword = pci_read_config32(dev, 0xe4);
+	dword &= ~(0x3f0); // enable
+	pci_write_config32(dev, 0xe4, dword);
+
+//	need to wait 100ms
+	delayx(1000);
+}
+
+static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
+{
+
+    static const unsigned int ctrl_conf_1[] = {
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
+
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
+
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
+
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
+	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+
+	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
+	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+    };
+
+    static const unsigned int ctrl_conf_1_1[] = {
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
+	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
+    };
+
+
+    static const unsigned int ctrl_conf_mcp55_only[] = {
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
+
+	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
+
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
+	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
+	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
+
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
+
+#if MCP55_USE_AZA == 1
+	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
+
+//	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
+#endif
+// play a while with GPIO in MCP55
+#ifdef MCP55_MB_SETUP
+	MCP55_MB_SETUP
+#endif
+
+#if MCP55_USE_AZA == 1
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
+#endif
+
+
+    };
+
+    static const unsigned int ctrl_conf_master_only[] = {
+
+	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
+
+	//Master MCP55 ????YHLU
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
+
+    };
+
+    static const unsigned int ctrl_conf_2[] = {
+	/* I didn't put pcie related stuff here */
+
+	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
+	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
+
+	RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
+
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
+
+
+#if MCP55_USE_NIC == 1
+	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
+
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
+#endif
+
+    };
+
+
+	int j, i;
+
+	for(j=0; j<mcp55_num; j++) {
+		mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
+
+		setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+		for(i=0; i<3; i++) { // three SATA
+			setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
+				PCI_DEV(busn[j], devn[j], i), io_base[j]);
+		}
+		if(busn[j] == 0) {
+			setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+		}
+
+		if( (busn[j] == 0) && (mcp55_num>1) ) {
+			setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+		}
+
+		setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
+				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+
+	}
+
+#if 0
+	for(j=0; j< mcp55_num; j++) {
+		// PCI-E (XSPLL) SS table 0x40, x044, 0x48
+		// SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8
+		// CPU   (PPLL)  SS table 0xc0, 0xc4, 0xc8
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
+			io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
+			io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
+		setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
+			io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
+	}
+#endif
+
+}
+
+#ifndef HT_CHAIN_NUM_MAX
+
+#define HT_CHAIN_NUM_MAX	4
+#define HT_CHAIN_BUSN_D	0x40
+#define HT_CHAIN_IOBASE_D	0x4000
+
+#endif
+
+static int mcp55_early_setup_x(void)
+{
+	/*find out how many mcp55 we have */
+	unsigned busn[HT_CHAIN_NUM_MAX];
+	unsigned devn[HT_CHAIN_NUM_MAX];
+	unsigned io_base[HT_CHAIN_NUM_MAX];
+	/*
+		FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation
+		Need to use same trick about pci1234 to verify node/link connection
+	*/
+	unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 };
+	int mcp55_num = 0;
+	unsigned busnx;
+	unsigned devnx;
+	int ht_c_index,j;
+
+	/* FIXME: multi pci segment handling */
+
+	/* Any system that only have IO55 without MCP55? */
+	for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) {
+		busnx = ht_c_index * HT_CHAIN_BUSN_D;
+		for(devnx=0;devnx<0x20;devnx++) {
+			u32 id;
+			device_t dev;
+			dev = PCI_DEV(busnx, devnx, 0);
+			id = pci_read_config32(dev, PCI_VENDOR_ID);
+			if(id == 0x036910de) {
+				busn[mcp55_num] = busnx;
+				devn[mcp55_num] = devnx;
+				io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55
+				mcp55_num++;
+				if(mcp55_num == MCP55_NUM) goto out;
+				break; // only one MCP55 on one chain
+			}
+		}
+	}
+
+out:
+	print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n");
+
+	mcp55_early_set_port(mcp55_num, busn, devn, io_base);
+	mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
+
+	mcp55_early_clear_port(mcp55_num, busn, devn, io_base);
+
+//	set_ht_link_mcp55(HT_CHAIN_NUM_MAX);
+
+	return 0;
+
+}
+
+
+




From peter at stuge.se  Sat Aug  2 05:34:58 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 05:34:58 +0200
Subject: [coreboot] patch: v3.k8.wip1
In-Reply-To: <13426df10808012024u30620c01gf523219195e3df9f@mail.gmail.com>
References: <13426df10808011707h291b9c4dyc6269f227c34aae5@mail.gmail.com>
	<20080802031842.9236.qmail@stuge.se>
	<13426df10808012024u30620c01gf523219195e3df9f@mail.gmail.com>
Message-ID: <20080802033458.13074.qmail@stuge.se>

On Fri, Aug 01, 2008 at 08:24:36PM -0700, ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

oh, ok. r713. :)

Thanks!


//Peter



From info at coresystems.de  Sat Aug  2 05:39:59 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 05:39:59 +0200
Subject: [coreboot] r3453 build service
Message-ID: <E1KP7yJ-0001W5-1b@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3453 to
the coreboot source repository and caused the following 
changes:

Change Log:
same spelling in all mtrr output.. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3453&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3453&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3453&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3453&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Sat Aug  2 06:32:49 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 Aug 2008 21:32:49 -0700
Subject: [coreboot] patch: v3.k8.wip1
In-Reply-To: <20080802033458.13074.qmail@stuge.se>
References: <13426df10808011707h291b9c4dyc6269f227c34aae5@mail.gmail.com>
	<20080802031842.9236.qmail@stuge.se>
	<13426df10808012024u30620c01gf523219195e3df9f@mail.gmail.com>
	<20080802033458.13074.qmail@stuge.se>
Message-ID: <13426df10808012132i7384c50ejb4c89dec86383e6b@mail.gmail.com>

no #include in mcp55.c :-)

anyway will try to fix it this weekend.

ron



From info at coresystems.de  Sat Aug  2 06:43:02 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 06:43:02 +0200
Subject: [coreboot] r3454 build service
Message-ID: <E1KP8xK-0007Rv-I4@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3454 to
the coreboot source repository and caused the following 
changes:

Change Log:
serial.inc is not used anywhere. drop it (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3454&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3454&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3454&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3454&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Aug  2 07:44:01 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 07:44:01 +0200
Subject: [coreboot] r3455 build service
Message-ID: <E1KP9uL-000205-6U@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3455 to
the coreboot source repository and caused the following 
changes:

Change Log:
match against all steppings of a CPU model, because these are _model_ drivers.
(trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3455&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3455&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3455&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3455&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From celtic at sairyx.org  Sat Aug  2 08:46:21 2008
From: celtic at sairyx.org (Arlen Cuss)
Date: Sat, 2 Aug 2008 16:46:21 +1000
Subject: [coreboot] MS-7125 / MSI K8N Neo4-F
Message-ID: <61e48c080808012346pabb5475i15ba0a65829a6e8d@mail.gmail.com>

Hi all,

I've got the aforementioned motherboard; MS-7125, listed under
`Desktops' on the wiki. I notice from [1] and possibly [2] that it's
not working. As others have mentioned, it's a K8 northbridge, CK804
southbridge, superiotool detects Winbond 83627THF/THG, with an Athlon
64. BIOS is socketed.

I'd like to contribute code by trying to make this mainboard work, but
as for development I'm not sure what's best (in terms of safely
flashing BIOSes, etc.), etc. Any tips or advice on how to go about
this, or if anyone's already working towards this goal?

Cheers,
Arlen

[1] http://coreboot.org/pipermail/coreboot/2007-August/023426.html
[2] http://linuxbios.org/pipermail/linuxbios/2006-May/014478.html



From info at coresystems.de  Sat Aug  2 10:20:52 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 10:20:52 +0200
Subject: [coreboot] r3456 build service
Message-ID: <E1KPCM8-0006f6-6Q@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3456 to
the coreboot source repository and caused the following 
changes:

Change Log:
use printk, when possible. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3456&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3456&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3456&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3456&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Aug  2 11:12:28 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 11:12:28 +0200
Subject: [coreboot] r3457 build service
Message-ID: <E1KPDA4-0000HF-Bu@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3457 to
the coreboot source repository and caused the following 
changes:

Change Log:
clean out obsoleted config.lb rules and output, fix indenting (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3457&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3457&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3457&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3457&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Aug  2 11:58:05 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 11:58:05 +0200
Subject: [coreboot] r3458 build service
Message-ID: <E1KPDsD-0002EA-28@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3458 to
the coreboot source repository and caused the following 
changes:

Change Log:
clarify in the printks what function is actually called. This little smart magic
drove me crazy during debugging. Fix Typos. Add a warning because the
on-chipset devices are hardcoded. For newer machines, a lot more memory space
will have special meanings, and we can't hardcode them all in an ifdef desert.

(trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3458&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3458&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3458&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3458&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Aug  2 12:41:45 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 12:41:45 +0200
Subject: [coreboot] r3459 build service
Message-ID: <E1KPEYT-0003hb-QS@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3459 to
the coreboot source repository and caused the following 
changes:

Change Log:
Typo, thanks to Idwer for spotting this. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3459&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3459&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3459&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3459&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Aug  2 13:26:52 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 13:26:52 +0200
Subject: [coreboot] r3460 build service
Message-ID: <E1KPFG8-0006GF-Q2@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3460 to
the coreboot source repository and caused the following 
changes:

Change Log:
a heuristics is something different

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3460&device=aruma&vendor=agami
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3460&device=serengeti_cheetah&vendor=amd
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3460&device=serengeti_cheetah_fam10&vendor=amd
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3460&device=dk8_htx&vendor=iwill


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Sat Aug  2 14:13:29 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 14:13:29 +0200
Subject: [coreboot] patch: v3.k8.wip1
In-Reply-To: <13426df10808012132i7384c50ejb4c89dec86383e6b@mail.gmail.com>
References: <13426df10808011707h291b9c4dyc6269f227c34aae5@mail.gmail.com>
	<20080802031842.9236.qmail@stuge.se>
	<13426df10808012024u30620c01gf523219195e3df9f@mail.gmail.com>
	<20080802033458.13074.qmail@stuge.se>
	<13426df10808012132i7384c50ejb4c89dec86383e6b@mail.gmail.com>
Message-ID: <20080802121329.9058.qmail@stuge.se>

On Fri, Aug 01, 2008 at 09:32:49PM -0700, ron minnich wrote:
> no #include in mcp55.c :-)

I didn't touch the mcp55 files at all, when they didn't build
straight away I simply commented out select SOUTHBRIDGE_NVIDIA_MCP55
so they weren't included.


> anyway will try to fix it this weekend.

Cool.


//Peter



From info at coresystems.de  Sat Aug  2 16:00:25 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 02 Aug 2008 16:00:25 +0200
Subject: [coreboot] r3461 build service
Message-ID: <E1KPHej-00063D-Hp@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stepan" checked in revision 3461 to
the coreboot source repository and caused the following 
changes:

Change Log:
oops, forgot these in the cleanup..  (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of agami:aruma has been fixed
Compilation of amd:serengeti_cheetah has been fixed
Compilation of amd:serengeti_cheetah_fam10 has been fixed
Compilation of iwill:dk8_htx has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From stepan at coresystems.de  Sat Aug  2 16:42:43 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 16:42:43 +0200
Subject: [coreboot] [PATCH] [v2] remove verbose introduction of elfboot.
Message-ID: <48947263.50207@coresystems.de>

see patch!

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
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From stepan at coresystems.de  Sat Aug  2 16:43:34 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 16:43:34 +0200
Subject: [coreboot] [PATCH] [v2] add returning to SIPI WAIT for MP systems
Message-ID: <48947296.4060809@coresystems.de>

See patch!

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Sat Aug  2 16:47:35 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 16:47:35 +0200
Subject: [coreboot] [PATCH] [v2] copying to ram cosmetics
Message-ID: <48947387.1060902@coresystems.de>

See patch!

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Sat Aug  2 16:50:05 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 16:50:05 +0200
Subject: [coreboot] [PATCH] [v2] cleanup console code
Message-ID: <4894741D.60806@coresystems.de>

See patch!

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From svn at coreboot.org  Sat Aug  2 16:58:50 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 16:58:50 +0200
Subject: [coreboot] r3462 - trunk/util/flashrom
Message-ID: <mailman.1762.1355071349.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-02 16:58:49 +0200 (Sat, 02 Aug 2008)
New Revision: 3462

Modified:
   trunk/util/flashrom/flashchips.c
Log:
tested another intel chip (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/util/flashrom/flashchips.c
===================================================================
--- trunk/util/flashrom/flashchips.c	2008-08-01 19:22:34 UTC (rev 3461)
+++ trunk/util/flashrom/flashchips.c	2008-08-02 14:58:49 UTC (rev 3462)
@@ -51,7 +51,7 @@
 	{"EON",		"EN29F002(A)(N)T",	EON_ID,		EN_29F002T,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
 	{"Fujitsu",	"MBM29F400TC",		FUJITSU_ID,	MBM29F400TC_STRANGE,	512,	64 * 1024,	TEST_UNTESTED,	probe_m29f400bt,	erase_m29f400bt,		write_coreboot_m29f400bt},
 	{"Intel",	"82802AB",		INTEL_ID,	173,			512,	64 * 1024,	TEST_OK_PREW,	probe_82802ab,		erase_82802ab,			write_82802ab},
-	{"Intel",	"82802AC",		INTEL_ID,	172,			1024,	64 * 1024,	TEST_UNTESTED,	probe_82802ab,		erase_82802ab,			write_82802ab},
+	{"Intel",	"82802AC",		INTEL_ID,	172,			1024,	64 * 1024,	TEST_OK_PREW,	probe_82802ab,		erase_82802ab,			write_82802ab},
 	{"Macronix",	"MX25L4005",		MX_ID,		MX_25L4005,		512,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
 	{"Macronix",	"MX25L8005",		MX_ID,		MX_25L8005,		1024,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
 	{"Macronix",	"MX25L1605",		MX_ID,		MX_25L1605,		2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},




From c-d.hailfinger.devel.2006 at gmx.net  Sat Aug  2 17:02:00 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Aug 2008 17:02:00 +0200
Subject: [coreboot] [PATCH] [v2] cleanup console code
In-Reply-To: <4894741D.60806@coresystems.de>
References: <4894741D.60806@coresystems.de>
Message-ID: <489476E8.9070409@gmx.net>

On 02.08.2008 16:50, Stefan Reinauer wrote:

> Index: src/arch/i386/lib/console_print.c
> ===================================================================
> --- src/arch/i386/lib/console_print.c	(revision 3461)
> +++ src/arch/i386/lib/console_print.c	(working copy)
> @@ -58,58 +58,59 @@
>  	}
>  }
>  
> -#define NOINLINE __attribute__((noinline))
> -static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
> -static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
> -static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
> -static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
> -static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
> +#define STATIC 

I don't understand that change. You unconditionally define STATIC
as empty token instead of simply removing it.

>  
> -static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
> -static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
> -static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
> -static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
> -static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
> +STATIC void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
> +STATIC void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
> +STATIC void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
> +STATIC void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
> +STATIC void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
>  
> -static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
> -static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
> -static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
> -static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
> -static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
> +STATIC void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
> +STATIC void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
> +STATIC void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
> +STATIC void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
> +STATIC void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
>  
> -static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
> -static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
> -static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
> -static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
> -static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
> +STATIC void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
> +STATIC void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
> +STATIC void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
> +STATIC void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
> +STATIC void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
>  
> -static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
> -static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
> -static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
> -static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
> -static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
> +STATIC void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
> +STATIC void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
> +STATIC void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
> +STATIC void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
> +STATIC void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
>  
> -static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
> -static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
> -static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
> -static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
> -static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
> +STATIC void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
> +STATIC void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
> +STATIC void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
> +STATIC void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
> +STATIC void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
>  
> -static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
> -static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
> -static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
> -static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
> -static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
> +STATIC void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
> +STATIC void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
> +STATIC void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
> +STATIC void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
> +STATIC void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
>  
> -static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
> -static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
> -static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
> -static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
> -static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
> +STATIC void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
> +STATIC void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
> +STATIC void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
> +STATIC void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
> +STATIC void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
>  
> -static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
> -static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
> -static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
> -static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
> -static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
> +STATIC void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
> +STATIC void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
> +STATIC void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
> +STATIC void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
> +STATIC void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
>  
> +STATIC void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
> +STATIC void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
> +STATIC void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
> +STATIC void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
> +STATIC void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
> +

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sat Aug  2 17:03:46 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Aug 2008 17:03:46 +0200
Subject: [coreboot] [PATCH] [v2] copying to ram cosmetics
In-Reply-To: <48947387.1060902@coresystems.de>
References: <48947387.1060902@coresystems.de>
Message-ID: <48947752.7090803@gmx.net>

On 02.08.2008 16:47, Stefan Reinauer wrote:
> See patch!
> This patch 
> * fixes a warning
> * puts some debug messages to spew because they're only useful to debug CAR
> * Print an explicit message "Uncompressing..." instad of "Copying..." when 
>   coreboot_ram.rom is compressed.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>   

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Sat Aug  2 17:04:40 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 17:04:40 +0200
Subject: [coreboot] [PATCH] [flashrom] Numony support
Message-ID: <48947788.3020409@coresystems.de>

See patch!

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From peter at stuge.se  Sat Aug  2 17:05:06 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 17:05:06 +0200
Subject: [coreboot] [PATCH] [v2] remove verbose introduction of elfboot.
In-Reply-To: <48947263.50207@coresystems.de>
References: <48947263.50207@coresystems.de>
Message-ID: <20080802150506.23165.qmail@stuge.se>

On Sat, Aug 02, 2008 at 04:42:43PM +0200, Stefan Reinauer wrote:
> -	printk_info("Version %s\n", BOOTLOADER_VERSION);
> -	printk_info("\n");
> +	printk_debug("\nelfboot: Attempting to load payload.\n");

Please keep the version number. Otherwise:

Acked-by: Peter Stuge <peter at stuge.se>
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From peter at stuge.se  Sat Aug  2 17:05:29 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 17:05:29 +0200
Subject: [coreboot] [PATCH] [v2] add returning to SIPI WAIT for MP
	systems
In-Reply-To: <48947296.4060809@coresystems.de>
References: <48947296.4060809@coresystems.de>
Message-ID: <20080802150529.23258.qmail@stuge.se>

On Sat, Aug 02, 2008 at 04:43:34PM +0200, Stefan Reinauer wrote:
> Go back to SIPI WAIT state for those CPUS defining the newly introduced
> CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with
> multiple cores.
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>


> Index: src/include/cpu/x86/lapic.h
> ===================================================================
> --- src/include/cpu/x86/lapic.h	(revision 3461)
> +++ src/include/cpu/x86/lapic.h	(working copy)
> @@ -51,6 +51,11 @@
>  	return lapic_read(LAPIC_ID) >> 24;
>  }
>  
> +
> +#if CONFIG_AP_IN_SIPI_WAIT != 1
> +/* If we need to go back to sipi wait, we use the long non-inlined version of
> + * this function in lapic_cpu_init.c
> + */
>  static inline __attribute__((always_inline)) void stop_this_cpu(void)
>  {
>  
> @@ -59,6 +64,7 @@
>  		hlt();
>  	}
>  }
> +#endif
>  
>  #if ! defined (__ROMCC__)
>  
> @@ -98,7 +104,7 @@
>  }
>  
>  
> -extern inline void lapic_write_atomic(unsigned long reg, unsigned long v)
> +static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
>  {
>  	xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
>  }
> Index: src/cpu/x86/lapic/lapic_cpu_init.c
> ===================================================================
> --- src/cpu/x86/lapic/lapic_cpu_init.c	(revision 3461)
> +++ src/cpu/x86/lapic/lapic_cpu_init.c	(working copy)
> @@ -1,6 +1,7 @@
>  /*
>  	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
>  	2005.12 yhlu add _RAMBASE above 1M support for SMP
> +	2008.05 stepan add support for going back to sipi wait state
>  */
>  
>  #include <cpu/x86/lapic.h>
> @@ -16,6 +17,7 @@
>  
>  #if CONFIG_SMP == 1
>  
> +#if _RAMBASE >= 0x100000
>  /* This is a lot more paranoid now, since Linux can NOT handle
>   * being told there is a CPU when none exists. So any errors 
>   * will return 0, meaning no CPU. 
> @@ -27,6 +29,7 @@
>  {
>  	return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 
>  }
> +#endif
>  
>  static void copy_secondary_start_to_1m_below(void) 
>  {
> @@ -277,9 +280,73 @@
>  	return result;
>  }
>  
> +#if CONFIG_AP_IN_SIPI_WAIT == 1
> +/**
> + * Normally this function is defined in lapic.h as an always inline function
> + * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
> + * I think all hyperthreading CPUs might need this version, but I could only
> + * verify this on the Intel Core Duo
> + */
> +void stop_this_cpu(void)
> +{
> +	int timeout;
> +	unsigned long send_status;
> +	unsigned long lapicid;
> +
> +	lapicid = lapic_read(LAPIC_ID) >> 24;
> +
> +	printk_debug("CPU %d going down...\n", lapicid);
> +
> +	/* send an LAPIC INIT to myself */
> +	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));
> +	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
> +
> +	/* wait for the ipi send to finish */
> +#if 0
> +	// When these two printk_spew calls are not removed, the
> +	// machine will hang when log level is SPEW. Why?
> +	printk_spew("Waiting for send to finish...\n");
> +#endif
> +	timeout = 0;
> +	do {
> +#if 0
> +		printk_spew("+");
> +#endif
> +		udelay(100);
> +		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
> +	} while (send_status && (timeout++ < 1000));
> +	if (timeout >= 1000) {
> +		printk_err("timed out\n");
> +	}
> +	mdelay(10);
> +
> +	printk_spew("Deasserting INIT.\n");
> +	/* Deassert the LAPIC INIT */
> +	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));	
> +	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
> +
> +	printk_spew("Waiting for send to finish...\n");
> +	timeout = 0;
> +	do {
> +		printk_spew("+");
> +		udelay(100);
> +		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
> +	} while (send_status && (timeout++ < 1000));
> +	if (timeout >= 1000) {
> +		printk_err("timed out\n");
> +	}
> +
> +	while(1) {
> +		hlt();
> +	}
> +}
> +#endif
> +
>  /* C entry point of secondary cpus */
>  void secondary_cpu_init(void)
>  {
> +	unsigned long cpunum;
> +
>  	atomic_inc(&active_cpus);
>  #if SERIAL_CPU_INIT == 1
>    #if CONFIG_MAX_CPUS>2
> @@ -294,6 +361,7 @@
>  #endif
>  
>  	atomic_dec(&active_cpus);
> +
>  	stop_this_cpu();
>  }
>  
> @@ -356,7 +424,6 @@
>  		if (!cpu->initialized) {
>  			printk_err("CPU 0x%02x did not initialize!\n", 
>  				cpu->path.u.apic.apic_id);
> -#warning "FIXME do I need a mainboard_cpu_fixup function?"
>  		}
>  	}
>  	printk_debug("All AP CPUs stopped\n");
> Index: src/config/Options.lb
> ===================================================================
> --- src/config/Options.lb	(revision 3461)
> +++ src/config/Options.lb	(working copy)
> @@ -574,6 +574,11 @@
>  	export always
>  	comment "Should multiple cpus per die be enabled?"
>  end
> +define CONFIG_AP_IN_SIPI_WAIT
> +	default 0
> +	export always
> +	comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
> +end
>  define HAVE_MP_TABLE
>  	default none
>  	export used
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From stepan at coresystems.de  Sat Aug  2 17:08:00 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 17:08:00 +0200
Subject: [coreboot] [PATCH] [v2] cleanup console code
In-Reply-To: <489476E8.9070409@gmx.net>
References: <4894741D.60806@coresystems.de> <489476E8.9070409@gmx.net>
Message-ID: <48947850.4070806@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 02.08.2008 16:50, Stefan Reinauer wrote:
>
>   
>> Index: src/arch/i386/lib/console_print.c
>> ===================================================================
>> --- src/arch/i386/lib/console_print.c	(revision 3461)
>> +++ src/arch/i386/lib/console_print.c	(working copy)
>> @@ -58,58 +58,59 @@
>>  	}
>>  }
>>  
>> -#define NOINLINE __attribute__((noinline))
>> -static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
>> -static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
>> -static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
>> -static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
>> -static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
>> +#define STATIC 
>>     
>
> I don't understand that change. You unconditionally define STATIC
> as empty token instead of simply removing it.
>   
Yes, absolutely. Someone put it there and was thinking something.

So this allows to put a method in place choosing when it would be 
required to really set those function prototypes static.


Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From peter at stuge.se  Sat Aug  2 17:08:03 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 17:08:03 +0200
Subject: [coreboot] [PATCH] [flashrom] Numony support
In-Reply-To: <48947788.3020409@coresystems.de>
References: <48947788.3020409@coresystems.de>
Message-ID: <20080802150803.24099.qmail@stuge.se>

On Sat, Aug 02, 2008 at 05:04:40PM +0200, Stefan Reinauer wrote:
> erased blockwise
..
> +int spi_chip_erase(struct flashchip *flash);

Please change the function names to match the functionality.

Maybe spi_chip_erase_all_blocks ?

With that changed, it's

Acked-by: Peter Stuge <peter at stuge.se>
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From svn at coreboot.org  Sat Aug  2 17:09:13 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 17:09:13 +0200
Subject: [coreboot] r3463 - trunk/coreboot-v2/src/cpu/x86/car
Message-ID: <mailman.1763.1355071349.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-02 17:09:12 +0200 (Sat, 02 Aug 2008)
New Revision: 3463

Modified:
   trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
Log:
This patch 
* fixes a warning
* puts some debug messages to spew because they're only useful to debug CAR
* print an explicit message "Uncompressing..." instad of "Copying..." when 
  coreboot_ram.rom is compressed.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2008-08-02 14:58:49 UTC (rev 3462)
+++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2008-08-02 15:09:12 UTC (rev 3463)
@@ -12,12 +12,14 @@
 static void copy_and_run(unsigned cpu_reset)
 {
 	uint8_t *src, *dst; 
+#if !CONFIG_COMPRESS
 	unsigned long dst_len;
+#endif
         unsigned long ilen, olen;
 
-	print_debug("Copying coreboot to RAM.\r\n");
 
 #if !CONFIG_COMPRESS 
+	print_debug("Copying coreboot to RAM.\r\n");
 	__asm__ volatile (
 		"leal _liseg, %0\n\t"
 		"leal _iseg, %1\n\t"
@@ -27,6 +29,7 @@
 	);
 	memcpy(src, dst, dst_len);
 #else 
+	print_debug("Uncompressing coreboot to RAM.\r\n");
 
         __asm__ volatile (
 	        "leal _liseg, %0\n\t"
@@ -35,11 +38,11 @@
         );
 
 #if CONFIG_USE_INIT		
-	printk_debug("src=%08x\r\n",src); 
-	printk_debug("dst=%08x\r\n",dst);
+	printk_spew("src=%08x\r\n",src); 
+	printk_spew("dst=%08x\r\n",dst);
 #else
-        print_debug("src="); print_debug_hex32(src); print_debug("\r\n");
-        print_debug("dst="); print_debug_hex32(dst); print_debug("\r\n");
+        print_spew("src="); print_spew_hex32((uint32_t)src); print_spew("\r\n");
+        print_spew("dst="); print_spew_hex32((uint32_t)dst); print_spew("\r\n");
 #endif
 	
 //	dump_mem(src, src+0x100);
@@ -49,9 +52,9 @@
 #endif
 //	dump_mem(dst, dst+0x100);
 #if CONFIG_USE_INIT
-	printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
+	printk_spew("linxbios_ram.bin length = %08x\r\n", olen);
 #else
-	print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
+	print_spew("linxbios_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");
 #endif
 	print_debug("Jumping to coreboot.\r\n");
 




From stepan at coresystems.de  Sat Aug  2 17:10:43 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 17:10:43 +0200
Subject: [coreboot] [PATCH] [v2] remove verbose introduction of elfboot.
In-Reply-To: <20080802150506.23165.qmail@stuge.se>
References: <48947263.50207@coresystems.de>
	<20080802150506.23165.qmail@stuge.se>
Message-ID: <489478F3.1030608@coresystems.de>

Peter Stuge wrote:
> On Sat, Aug 02, 2008 at 04:42:43PM +0200, Stefan Reinauer wrote:
>   
>> -	printk_info("Version %s\n", BOOTLOADER_VERSION);
>> -	printk_info("\n");
>> +	printk_debug("\nelfboot: Attempting to load payload.\n");
>>     
>
> Please keep the version number. Otherwise:
>
> Acked-by: Peter Stuge <peter at stuge.se>
>   
The version number of coreboot is v2 in that case. There are no other 
version numbers...


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From stepan at coresystems.de  Sat Aug  2 17:12:19 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 17:12:19 +0200
Subject: [coreboot] [PATCH] [flashrom] Numony support
In-Reply-To: <20080802150803.24099.qmail@stuge.se>
References: <48947788.3020409@coresystems.de>
	<20080802150803.24099.qmail@stuge.se>
Message-ID: <48947953.3050300@coresystems.de>

Peter Stuge wrote:
> On Sat, Aug 02, 2008 at 05:04:40PM +0200, Stefan Reinauer wrote:
>   
>> erased blockwise
>>     
> ..
>   
>> +int spi_chip_erase(struct flashchip *flash);
>>     
>
> Please change the function names to match the functionality.
>   
It erases the chip?

Since it does not do blockwise erase on all chipsets, pretending it did 
would be bad.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Sat Aug  2 17:13:58 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 17:13:58 +0200
Subject: [coreboot] r3464 - trunk/util/flashrom
Message-ID: <mailman.1764.1355071349.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-02 17:13:58 +0200 (Sat, 02 Aug 2008)
New Revision: 3464

Modified:
   trunk/util/flashrom/flashrom.c
Log:
update copyright year (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-08-02 15:09:12 UTC (rev 3463)
+++ trunk/util/flashrom/flashrom.c	2008-08-02 15:13:58 UTC (rev 3464)
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2000 Silicon Integrated System Corporation
  * Copyright (C) 2004 Tyan Corp <yhlu at tyan.com>
- * Copyright (C) 2005-2007 coresystems GmbH 
+ * Copyright (C) 2005-2008 coresystems GmbH 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by




From svn at coreboot.org  Sat Aug  2 17:15:23 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 17:15:23 +0200
Subject: [coreboot] r3465 - in trunk/coreboot-v2/src: config cpu/x86/lapic
	include/cpu/x86
Message-ID: <mailman.1765.1355071349.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-02 17:15:23 +0200 (Sat, 02 Aug 2008)
New Revision: 3465

Modified:
   trunk/coreboot-v2/src/config/Options.lb
   trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
   trunk/coreboot-v2/src/include/cpu/x86/lapic.h
Log:
Go back to SIPI WAIT state for those CPUS defining the newly introduced
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with
multiple cores.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2008-08-02 15:13:58 UTC (rev 3464)
+++ trunk/coreboot-v2/src/config/Options.lb	2008-08-02 15:15:23 UTC (rev 3465)
@@ -574,6 +574,11 @@
 	export always
 	comment "Should multiple cpus per die be enabled?"
 end
+define CONFIG_AP_IN_SIPI_WAIT
+	default 0
+	export always
+	comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
+end
 define HAVE_MP_TABLE
 	default none
 	export used

Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2008-08-02 15:13:58 UTC (rev 3464)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2008-08-02 15:15:23 UTC (rev 3465)
@@ -1,6 +1,7 @@
 /*
 	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
 	2005.12 yhlu add _RAMBASE above 1M support for SMP
+	2008.05 stepan add support for going back to sipi wait state
 */
 
 #include <cpu/x86/lapic.h>
@@ -16,6 +17,7 @@
 
 #if CONFIG_SMP == 1
 
+#if _RAMBASE >= 0x100000
 /* This is a lot more paranoid now, since Linux can NOT handle
  * being told there is a CPU when none exists. So any errors 
  * will return 0, meaning no CPU. 
@@ -27,6 +29,7 @@
 {
 	return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 
 }
+#endif
 
 static void copy_secondary_start_to_1m_below(void) 
 {
@@ -277,9 +280,73 @@
 	return result;
 }
 
+#if CONFIG_AP_IN_SIPI_WAIT == 1
+/**
+ * Normally this function is defined in lapic.h as an always inline function
+ * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
+ * I think all hyperthreading CPUs might need this version, but I could only
+ * verify this on the Intel Core Duo
+ */
+void stop_this_cpu(void)
+{
+	int timeout;
+	unsigned long send_status;
+	unsigned long lapicid;
+
+	lapicid = lapic_read(LAPIC_ID) >> 24;
+
+	printk_debug("CPU %d going down...\n", lapicid);
+
+	/* send an LAPIC INIT to myself */
+	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));
+	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
+
+	/* wait for the ipi send to finish */
+#if 0
+	// When these two printk_spew calls are not removed, the
+	// machine will hang when log level is SPEW. Why?
+	printk_spew("Waiting for send to finish...\n");
+#endif
+	timeout = 0;
+	do {
+#if 0
+		printk_spew("+");
+#endif
+		udelay(100);
+		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
+	} while (send_status && (timeout++ < 1000));
+	if (timeout >= 1000) {
+		printk_err("timed out\n");
+	}
+	mdelay(10);
+
+	printk_spew("Deasserting INIT.\n");
+	/* Deassert the LAPIC INIT */
+	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));	
+	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
+
+	printk_spew("Waiting for send to finish...\n");
+	timeout = 0;
+	do {
+		printk_spew("+");
+		udelay(100);
+		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
+	} while (send_status && (timeout++ < 1000));
+	if (timeout >= 1000) {
+		printk_err("timed out\n");
+	}
+
+	while(1) {
+		hlt();
+	}
+}
+#endif
+
 /* C entry point of secondary cpus */
 void secondary_cpu_init(void)
 {
+	unsigned long cpunum;
+
 	atomic_inc(&active_cpus);
 #if SERIAL_CPU_INIT == 1
   #if CONFIG_MAX_CPUS>2
@@ -294,6 +361,7 @@
 #endif
 
 	atomic_dec(&active_cpus);
+
 	stop_this_cpu();
 }
 
@@ -356,7 +424,6 @@
 		if (!cpu->initialized) {
 			printk_err("CPU 0x%02x did not initialize!\n", 
 				cpu->path.u.apic.apic_id);
-#warning "FIXME do I need a mainboard_cpu_fixup function?"
 		}
 	}
 	printk_debug("All AP CPUs stopped\n");

Modified: trunk/coreboot-v2/src/include/cpu/x86/lapic.h
===================================================================
--- trunk/coreboot-v2/src/include/cpu/x86/lapic.h	2008-08-02 15:13:58 UTC (rev 3464)
+++ trunk/coreboot-v2/src/include/cpu/x86/lapic.h	2008-08-02 15:15:23 UTC (rev 3465)
@@ -51,6 +51,11 @@
 	return lapic_read(LAPIC_ID) >> 24;
 }
 
+
+#if CONFIG_AP_IN_SIPI_WAIT != 1
+/* If we need to go back to sipi wait, we use the long non-inlined version of
+ * this function in lapic_cpu_init.c
+ */
 static inline __attribute__((always_inline)) void stop_this_cpu(void)
 {
 
@@ -59,6 +64,7 @@
 		hlt();
 	}
 }
+#endif
 
 #if ! defined (__ROMCC__)
 
@@ -98,7 +104,7 @@
 }
 
 
-extern inline void lapic_write_atomic(unsigned long reg, unsigned long v)
+static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
 {
 	xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
 }




From rminnich at gmail.com  Sat Aug  2 18:14:52 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Aug 2008 09:14:52 -0700
Subject: [coreboot] [PATCH] [v2] cleanup console code
In-Reply-To: <48947850.4070806@coresystems.de>
References: <4894741D.60806@coresystems.de> <489476E8.9070409@gmx.net>
	<48947850.4070806@coresystems.de>
Message-ID: <13426df10808020914j4d2740d1wf28f3605e9dfe84c@mail.gmail.com>

On Sat, Aug 2, 2008 at 8:08 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
> Carl-Daniel Hailfinger wrote:
>>
>> On 02.08.2008 16:50, Stefan Reinauer wrote:
>>
>>
>>>
>>> Index: src/arch/i386/lib/console_print.c
>>> ===================================================================
>>> --- src/arch/i386/lib/console_print.c   (revision 3461)
>>> +++ src/arch/i386/lib/console_print.c   (working copy)
>>> @@ -58,58 +58,59 @@
>>>        }
>>>  }
>>>  -#define NOINLINE __attribute__((noinline))
>>> -static void print_emerg_char(unsigned char byte) {
>>> __console_tx_char(BIOS_EMERG, byte); }
>>> -static void print_emerg_hex8(unsigned char value){
>>> __console_tx_hex8(BIOS_EMERG, value); }
>>> -static void print_emerg_hex16(unsigned short value){
>>> __console_tx_hex16(BIOS_EMERG, value); }
>>> -static void print_emerg_hex32(unsigned int value) {
>>> __console_tx_hex32(BIOS_EMERG, value); }
>>> -static void print_emerg(const char *str) {
>>> __console_tx_string(BIOS_EMERG, str); }
>>> +#define STATIC
>>
>> I don't understand that change. You unconditionally define STATIC
>> as empty token instead of simply removing it.
>>
>
> Yes, absolutely. Someone put it there and was thinking something.

romcc.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Sat Aug  2 18:39:45 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Aug 2008 18:39:45 +0200
Subject: [coreboot] [PATCH] [flashrom] Numony support
In-Reply-To: <48947788.3020409@coresystems.de>
References: <48947788.3020409@coresystems.de>
Message-ID: <48948DD1.4070906@gmx.net>

On 02.08.2008 17:04, Stefan Reinauer wrote:

> Add support for Numonyx M25PE80. This chip requires to be erased blockwise, as
> the c7 method is unreliable, either for ICH7 or for this chip.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>   

Please don't commit yet. There's another chip erase command which may be
more reliable. More later.

Regards,
Carl-Daniel




From uwe at hermann-uwe.de  Sat Aug  2 19:00:36 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Aug 2008 19:00:36 +0200
Subject: [coreboot] [PATCH] [v2] remove verbose introduction of elfboot.
In-Reply-To: <489478F3.1030608@coresystems.de>
References: <48947263.50207@coresystems.de>
	<20080802150506.23165.qmail@stuge.se>
	<489478F3.1030608@coresystems.de>
Message-ID: <20080802170035.GA10143@greenwood>

On Sat, Aug 02, 2008 at 05:10:43PM +0200, Stefan Reinauer wrote:
> Peter Stuge wrote:
>> On Sat, Aug 02, 2008 at 04:42:43PM +0200, Stefan Reinauer wrote:
>>   
>>> -	printk_info("Version %s\n", BOOTLOADER_VERSION);
>>> -	printk_info("\n");
>>> +	printk_debug("\nelfboot: Attempting to load payload.\n");
>>>     
>>
>> Please keep the version number. Otherwise:
>>
>> Acked-by: Peter Stuge <peter at stuge.se>
>>   
> The version number of coreboot is v2 in that case. There are no other  
> version numbers...

Jep, I'd drop the version number.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Sat Aug  2 19:05:19 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 2 Aug 2008 19:05:19 +0200
Subject: [coreboot] r3463 - trunk/coreboot-v2/src/cpu/x86/car
In-Reply-To: <E1KPIjy-00017F-Km@mi011.mc1.hosteurope.de>
References: <E1KPIjy-00017F-Km@mi011.mc1.hosteurope.de>
Message-ID: <20080802170519.GB10143@greenwood>

On Sat, Aug 02, 2008 at 05:09:13PM +0200, svn at coreboot.org wrote:
>  #if CONFIG_USE_INIT
> -	printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
> +	printk_spew("linxbios_ram.bin length = %08x\r\n", olen);
>  #else
> -	print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
> +	print_spew("linxbios_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");

Should we also fix this while we're at it? "linx" -> "linux", or even
better "linxbios" -> "coreboot"?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From peter at stuge.se  Sat Aug  2 19:21:17 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 19:21:17 +0200
Subject: [coreboot] r3463 - trunk/coreboot-v2/src/cpu/x86/car
In-Reply-To: <20080802170519.GB10143@greenwood>
References: <E1KPIjy-00017F-Km@mi011.mc1.hosteurope.de>
	<20080802170519.GB10143@greenwood>
Message-ID: <20080802172117.27305.qmail@stuge.se>

On Sat, Aug 02, 2008 at 07:05:19PM +0200, Uwe Hermann wrote:
> On Sat, Aug 02, 2008 at 05:09:13PM +0200, svn at coreboot.org wrote:
> >  #if CONFIG_USE_INIT
> > -	printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
> > +	printk_spew("linxbios_ram.bin length = %08x\r\n", olen);
> >  #else
> > -	print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
> > +	print_spew("linxbios_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");
> 
> Should we also fix this while we're at it? "linx" -> "linux", or even
> better "linxbios" -> "coreboot"?

That would be great.


//Peter



From stepan at coresystems.de  Sat Aug  2 20:31:21 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 Aug 2008 20:31:21 +0200
Subject: [coreboot] [PATCH] [flashrom] Numony support
In-Reply-To: <48948DD1.4070906@gmx.net>
References: <48947788.3020409@coresystems.de> <48948DD1.4070906@gmx.net>
Message-ID: <4894A7F9.8090007@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 02.08.2008 17:04, Stefan Reinauer wrote:
>
>   
>> Add support for Numonyx M25PE80. This chip requires to be erased blockwise, as
>> the c7 method is unreliable, either for ICH7 or for this chip.
>>
>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>   
>>     
>
> Please don't commit yet. There's another chip erase command which may be
> more reliable. More later.
>   

The method I sent can be considered 100% reliable. A script measuring 
data in 200 flash writes has not revealed a single failure.

What other method are you suggesting? Are you coming up with a patch? 
I'd gladly test anything as long as it's more generic than what I sent.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866





From c-d.hailfinger.devel.2006 at gmx.net  Sat Aug  2 20:47:58 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Aug 2008 20:47:58 +0200
Subject: [coreboot] [PATCH] v3: convert stage2 and initram makefile
 rules from object to source files
In-Reply-To: <47C9ADD4.2070009@gmx.net>
References: <47C9ADD4.2070009@gmx.net>
Message-ID: <4894ABDE.4030801@gmx.net>

On 01.03.2008 20:26, Carl-Daniel Hailfinger wrote:
> Convert stage2 and initram makefile rules from object to source files. 
> This creates a clearer distinction between source files in the source 
> tree we want to have compiled and indirectly created object/source files 
> in the object tree.
>
> It also will make enable us to move to whole-program 
> optimization/compilation which should yield substantial size savings.
> Then again, we may be able to do that without the makefile conversion as 
> well.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

Updated patch for svn HEAD follows.

Index: corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile
===================================================================
--- corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile	(Arbeitskopie)
@@ -21,7 +21,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
 STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o 
Index: corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile
===================================================================
--- corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile	(Arbeitskopie)
@@ -20,6 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c
 
 endif
Index: corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile
===================================================================
--- corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile	(Arbeitskopie)
@@ -25,6 +25,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
 
 endif
Index: corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile
===================================================================
--- corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile	(Arbeitskopie)
@@ -24,6 +24,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
 
 endif
Index: corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile	(Arbeitskopie)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile	(Arbeitskopie)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile	(Arbeitskopie)
@@ -28,10 +28,10 @@
 # directory and is built from what was auto.c in v2.
 #
 
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
 
-STAGE2_MAINBOARD_OBJ = vga.o
+STAGE2_MAINBOARD_SRC = vga.c
 
 #
 # VPD or SIP ROM or... how does NVIDIA call it?
Index: corebootv3-makefilerewrite/device/Makefile
===================================================================
--- corebootv3-makefilerewrite/device/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/device/Makefile	(Arbeitskopie)
@@ -24,6 +24,6 @@
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
-STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \
-		    pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o
+STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
+		    pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c
 
Index: corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile
===================================================================
--- corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile	(Arbeitskopie)
@@ -21,9 +21,9 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
-		      $(obj)/northbridge/amd/geodelx/vsmsetup.o \
-		      $(obj)/util/x86emu/vm86_gdt.o \
-		      $(obj)/northbridge/amd/geodelx/grphinit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \
+		      $(src)/northbridge/amd/geodelx/vsmsetup.c \
+		      $(src)/util/x86emu/vm86_gdt.c \
+		      $(src)/northbridge/amd/geodelx/grphinit.c
 
 endif
Index: corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile	(Arbeitskopie)
@@ -21,6 +21,6 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c
 
 endif
Index: corebootv3-makefilerewrite/arch/x86/Makefile
===================================================================
--- corebootv3-makefilerewrite/arch/x86/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/arch/x86/Makefile	(Arbeitskopie)
@@ -178,27 +178,32 @@
 # TODO: This should be compressed with the default compressor.
 #
 
-STAGE2_LIB_OBJ       = stage2.o clog2.o mem.o tables.o delay.o \
-		       compute_ip_checksum.o string.o
+STAGE2_LIB_SRC       = stage2.c clog2.c mem.c tables.c delay.c \
+		       compute_ip_checksum.c string.c
 
-STAGE2_ARCH_X86_OBJ  = archtables.o coreboot_table.o udelay_io.o
-STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
-STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
+STAGE2_ARCH_X86_SRC  = archtables.c coreboot_table.c udelay_io.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
+STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_ARCH_X86_OBJ += pirq_routing.o
+STAGE2_ARCH_X86_SRC += pirq_routing.c
 endif
 
 STAGE2_DYNAMIC_OBJ   = statictree.o
 
-STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \
-	      $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \
-	      $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
+	      $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
+	      $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
+	      $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
 
-STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ)
+STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
 
+STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
+
+# This one is special, but only due to slightly incorrect rules and dependencies.
+# Don't change the dependencies for now.
+STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
 # x86emu wants libgcc
@@ -214,7 +219,7 @@
 
 STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
 
-$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED)
+$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
 	$(Q)# leave a .o with full symbols in it for debugging.
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
@@ -260,9 +265,9 @@
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
 
-$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
+$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@)) (XIP)\n"
-	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
+	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
 	$(Q)# initram links against stage0
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \



-- 
http://www.hailfinger.org/




From svn at coreboot.org  Sat Aug  2 21:17:43 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 21:17:43 +0200
Subject: [coreboot] r3466 - in trunk/coreboot-v2/src: cpu/amd/car
	cpu/x86/car northbridge/amd/amdk8
Message-ID: <mailman.1766.1355071349.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-02 21:17:42 +0200 (Sat, 02 Aug 2008)
New Revision: 3466

Modified:
   trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
   trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c
Log:
adapt Uncompressing.. patch for AMD code. Also replace "linxbios" by "coreboot"
in a number of places.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c	2008-08-02 15:15:23 UTC (rev 3465)
+++ trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c	2008-08-02 19:17:42 UTC (rev 3466)
@@ -23,9 +23,9 @@
 	uint8_t *src, *dst; 
         unsigned long ilen, olen;
 
-	print_debug("Copying coreboot to RAM.\r\n");
 
 #if !CONFIG_COMPRESS 
+	print_debug("Copying coreboot to RAM.\r\n");
 	__asm__ volatile (
 		"leal _liseg, %0\n\t"
 		"leal _iseg, %1\n\t"
@@ -35,6 +35,7 @@
 	);
 	memcpy(dst, src, olen);
 #else 
+	print_debug("Uncompressing coreboot to RAM.\r\n");
 
         __asm__ volatile (
 	        "leal _liseg, %0\n\t"
@@ -48,12 +49,12 @@
 //	dump_mem(src, src+0x100);
 
 	olen = unrv2b(src, dst, &ilen);
-	print_debug_cp_run("linxbios_ram.nrv2b length = ", ilen);
+	print_debug_cp_run("coreboot_ram.nrv2b length = ", ilen);
 
 #endif
 //	dump_mem(dst, dst+0x100);
 
-	print_debug_cp_run("linxbios_ram.bin   length = ", olen);
+	print_debug_cp_run("coreboot_ram.bin   length = ", olen);
 
 	print_debug("Jumping to coreboot.\r\n");
 
@@ -98,12 +99,12 @@
 //      dump_mem(src, src+0x100);
 
         olen = unrv2b(src, dst, &ilen);
-//        print_debug_cp_run("linxbios_apc.nrv2b length = ", ilen);
+//        print_debug_cp_run("coreboot_apc.nrv2b length = ", ilen);
 
 #endif
 //      dump_mem(dst, dst+0x100);
 
-//        print_debug_cp_run("linxbios_apc.bin   length = ", olen);
+//        print_debug_cp_run("coreboot_apc.bin   length = ", olen);
 
 //        print_debug("Jumping to coreboot AP code in CAR.\r\n");
 

Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2008-08-02 15:15:23 UTC (rev 3465)
+++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2008-08-02 19:17:42 UTC (rev 3466)
@@ -52,9 +52,9 @@
 #endif
 //	dump_mem(dst, dst+0x100);
 #if CONFIG_USE_INIT
-	printk_spew("linxbios_ram.bin length = %08x\r\n", olen);
+	printk_spew("coreboot_ram.bin length = %08x\r\n", olen);
 #else
-	print_spew("linxbios_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");
+	print_spew("coreboot_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");
 #endif
 	print_debug("Jumping to coreboot.\r\n");
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c	2008-08-02 15:15:23 UTC (rev 3465)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c	2008-08-02 19:17:42 UTC (rev 3466)
@@ -92,7 +92,7 @@
  *     pci1234[0] will record the south bridge link and bus range
  *     pci1234[i] will record HT chain i.
  *
- * For example, on the Tyan S2885 linxbios_ram will put the AMD8151 chain (HT
+ * For example, on the Tyan S2885 coreboot_ram will put the AMD8151 chain (HT
  * link 0) into the register 0xE0, and the AMD8131/8111 HT chain into the
  * register 0xE4.
  *




From peter at stuge.se  Sat Aug  2 21:58:43 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 21:58:43 +0200
Subject: [coreboot] [PATCH] [flashrom] Numony support
In-Reply-To: <48947953.3050300@coresystems.de>
	<48947788.3020409@coresystems.de>
References: <48947788.3020409@coresystems.de>
	<20080802150803.24099.qmail@stuge.se>
	<48947953.3050300@coresystems.de> <48947788.3020409@coresystems.de>
Message-ID: <20080802195843.6978.qmail@stuge.se>

On Sat, Aug 02, 2008 at 05:04:40PM +0200, Stefan Reinauer wrote:
> Add support for Numonyx M25PE80. This chip requires to be erased
> blockwise, as the c7 method is unreliable, either for ICH7 or for
> this chip.
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>


On Sat, Aug 02, 2008 at 05:12:19PM +0200, Stefan Reinauer wrote:
> >>erased blockwise
> >..
> >>+int spi_chip_erase(struct flashchip *flash);
> >
> >Please change the function names to match the functionality.
> 
> It erases the chip?
> 
> Since it does not do blockwise erase on all chipsets, pretending it
> did would be bad.

Right you are. This is the best solution at the moment!


//Peter
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From c-d.hailfinger.devel.2006 at gmx.net  Sat Aug  2 22:12:49 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Aug 2008 22:12:49 +0200
Subject: [coreboot] [PATCH] v3: convert stage2 and initram makefile
 rules from object to source files
In-Reply-To: <4894ABDE.4030801@gmx.net>
References: <47C9ADD4.2070009@gmx.net> <4894ABDE.4030801@gmx.net>
Message-ID: <4894BFC1.1060300@gmx.net>

On 02.08.2008 20:47, Carl-Daniel Hailfinger wrote:
> On 01.03.2008 20:26, Carl-Daniel Hailfinger wrote:
>   
>> Convert stage2 and initram makefile rules from object to source files. 
>> This creates a clearer distinction between source files in the source 
>> tree we want to have compiled and indirectly created object/source files 
>> in the object tree.
>>
>> It also will make enable us to move to whole-program 
>> optimization/compilation which should yield substantial size savings.
>> Then again, we may be able to do that without the makefile conversion as 
>> well.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>   
>>     
>
> Updated patch for svn HEAD follows.
>   

Thanks to Peter for the review on IRC. Updated patch follows.

Index: corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile
===================================================================
--- corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile	(Arbeitskopie)
@@ -21,10 +21,10 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o 
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c
 endif
 
 STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
Index: corebootv3-makefilerewrite/southbridge/nvidia/mcp55/Makefile
===================================================================
--- corebootv3-makefilerewrite/southbridge/nvidia/mcp55/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/southbridge/nvidia/mcp55/Makefile	(Arbeitskopie)
@@ -21,10 +21,10 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/mcp55.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/mcp55.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/irq_tables.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/irq_tables.c
 endif
 
 STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o
Index: corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile
===================================================================
--- corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile	(Arbeitskopie)
@@ -20,6 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c
 
 endif
Index: corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile
===================================================================
--- corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile	(Arbeitskopie)
@@ -25,6 +25,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
 
 endif
Index: corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile
===================================================================
--- corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile	(Arbeitskopie)
@@ -24,6 +24,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
 
 endif
Index: corebootv3-makefilerewrite/superio/ite/it8716f/Makefile
===================================================================
--- corebootv3-makefilerewrite/superio/ite/it8716f/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/superio/ite/it8716f/Makefile	(Arbeitskopie)
@@ -24,6 +24,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c
 
 endif
Index: corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile	(Arbeitskopie)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile	(Arbeitskopie)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/amd/db800/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/amd/db800/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/amd/db800/Makefile	(Arbeitskopie)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/pcengines/alix2c3/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/pcengines/alix2c3/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/pcengines/alix2c3/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/gigabyte/m57sli/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/gigabyte/m57sli/Makefile	(Arbeitskopie)
@@ -21,9 +21,9 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =      $(src)/mainboard/$(MAINBOARDDIR)/initram.c
+INITRAM_SRC =      $(src)/mainboard/$(MAINBOARDDIR)/initram.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile	(Arbeitskopie)
@@ -28,10 +28,10 @@
 # directory and is built from what was auto.c in v2.
 #
 
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
 
-STAGE2_MAINBOARD_OBJ = vga.o
+STAGE2_MAINBOARD_SRC = vga.c
 
 #
 # VPD or SIP ROM or... how does NVIDIA call it?
Index: corebootv3-makefilerewrite/device/Makefile
===================================================================
--- corebootv3-makefilerewrite/device/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/device/Makefile	(Arbeitskopie)
@@ -24,6 +24,6 @@
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
-STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \
-		    pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o
+STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
+		    pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c
 
Index: corebootv3-makefilerewrite/northbridge/amd/k8/Makefile
===================================================================
--- corebootv3-makefilerewrite/northbridge/amd/k8/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/northbridge/amd/k8/Makefile	(Arbeitskopie)
@@ -21,6 +21,6 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/k8/raminit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/raminit.c
 
 endif
Index: corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile
===================================================================
--- corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile	(Arbeitskopie)
@@ -21,9 +21,9 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
-		      $(obj)/northbridge/amd/geodelx/vsmsetup.o \
-		      $(obj)/util/x86emu/vm86_gdt.o \
-		      $(obj)/northbridge/amd/geodelx/grphinit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \
+		      $(src)/northbridge/amd/geodelx/vsmsetup.c \
+		      $(src)/util/x86emu/vm86_gdt.c \
+		      $(src)/northbridge/amd/geodelx/grphinit.c
 
 endif
Index: corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile	(Arbeitskopie)
@@ -21,6 +21,6 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c
 
 endif
Index: corebootv3-makefilerewrite/arch/x86/Makefile
===================================================================
--- corebootv3-makefilerewrite/arch/x86/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/arch/x86/Makefile	(Arbeitskopie)
@@ -178,27 +178,32 @@
 # TODO: This should be compressed with the default compressor.
 #
 
-STAGE2_LIB_OBJ       = stage2.o clog2.o mem.o tables.o delay.o \
-		       compute_ip_checksum.o string.o
+STAGE2_LIB_SRC       = stage2.c clog2.c mem.c tables.c delay.c \
+		       compute_ip_checksum.c string.c
 
-STAGE2_ARCH_X86_OBJ  = archtables.o coreboot_table.o udelay_io.o
-STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
-STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
+STAGE2_ARCH_X86_SRC  = archtables.c coreboot_table.c udelay_io.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
+STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_ARCH_X86_OBJ += pirq_routing.o
+STAGE2_ARCH_X86_SRC += pirq_routing.c
 endif
 
 STAGE2_DYNAMIC_OBJ   = statictree.o
 
-STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \
-	      $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \
-	      $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
+	      $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
+	      $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
+	      $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
 
-STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ)
+STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
 
+STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
+
+# This one is special because the static tree object ends up in the mainboard
+# dir of the object tree.
+STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
 # x86emu wants libgcc
@@ -214,7 +219,7 @@
 
 STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
 
-$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED)
+$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
 	$(Q)# leave a .o with full symbols in it for debugging.
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
@@ -260,9 +265,9 @@
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
 
-$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
+$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@)) (XIP)\n"
-	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
+	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
 	$(Q)# initram links against stage0
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \


-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Sat Aug  2 22:27:27 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Aug 2008 13:27:27 -0700
Subject: [coreboot] [PATCH] v3: convert stage2 and initram makefile
	rules from object to source files
In-Reply-To: <4894BFC1.1060300@gmx.net>
References: <47C9ADD4.2070009@gmx.net> <4894ABDE.4030801@gmx.net>
	<4894BFC1.1060300@gmx.net>
Message-ID: <13426df10808021327g3a1e1ef8w8dc9a4a325791027@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Sat Aug  2 22:56:12 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 Aug 2008 22:56:12 +0200
Subject: [coreboot] r714 - in coreboot-v3: arch/x86 device
	mainboard/adl/msm800sev mainboard/amd/db800
	mainboard/amd/norwich mainboard/artecgroup/dbe61
	mainboard/artecgroup/dbe62 mainboard/emulation/qemu-x86
	mainboard/gigabyte/m57sli mainboard/pcengines/alix1c
	mainboard/pcengines/alix2c3 northbridge/amd/geodelx
	northbridge/amd/k8 northbridge/intel/i440bxemulation
	southbridge/amd/cs5536 southbridge/intel/i82371eb
	southbridge/nvidia/mcp55 superio/fintek/f71805f
	superio/ite/it8716f superio/winbond/w83627hf
Message-ID: <mailman.1767.1355071349.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-08-02 22:56:11 +0200 (Sat, 02 Aug 2008)
New Revision: 714

Modified:
   coreboot-v3/arch/x86/Makefile
   coreboot-v3/device/Makefile
   coreboot-v3/mainboard/adl/msm800sev/Makefile
   coreboot-v3/mainboard/amd/db800/Makefile
   coreboot-v3/mainboard/amd/norwich/Makefile
   coreboot-v3/mainboard/artecgroup/dbe61/Makefile
   coreboot-v3/mainboard/artecgroup/dbe62/Makefile
   coreboot-v3/mainboard/emulation/qemu-x86/Makefile
   coreboot-v3/mainboard/gigabyte/m57sli/Makefile
   coreboot-v3/mainboard/pcengines/alix1c/Makefile
   coreboot-v3/mainboard/pcengines/alix2c3/Makefile
   coreboot-v3/northbridge/amd/geodelx/Makefile
   coreboot-v3/northbridge/amd/k8/Makefile
   coreboot-v3/northbridge/intel/i440bxemulation/Makefile
   coreboot-v3/southbridge/amd/cs5536/Makefile
   coreboot-v3/southbridge/intel/i82371eb/Makefile
   coreboot-v3/southbridge/nvidia/mcp55/Makefile
   coreboot-v3/superio/fintek/f71805f/Makefile
   coreboot-v3/superio/ite/it8716f/Makefile
   coreboot-v3/superio/winbond/w83627hf/Makefile
Log:
Convert stage2 and initram makefile rules from object to source files. 
This creates a clearer distinction between source files in the source 
tree we want to have compiled and indirectly created object/source files 
in the object tree.

It also will make enable us to move to whole-program 
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as 
well.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/arch/x86/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -178,27 +178,32 @@
 # TODO: This should be compressed with the default compressor.
 #
 
-STAGE2_LIB_OBJ       = stage2.o clog2.o mem.o tables.o delay.o \
-		       compute_ip_checksum.o string.o
+STAGE2_LIB_SRC       = stage2.c clog2.c mem.c tables.c delay.c \
+		       compute_ip_checksum.c string.c
 
-STAGE2_ARCH_X86_OBJ  = archtables.o coreboot_table.o udelay_io.o
-STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
-STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
+STAGE2_ARCH_X86_SRC  = archtables.c coreboot_table.c udelay_io.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
+STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_ARCH_X86_OBJ += pirq_routing.o
+STAGE2_ARCH_X86_SRC += pirq_routing.c
 endif
 
 STAGE2_DYNAMIC_OBJ   = statictree.o
 
-STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \
-	      $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \
-	      $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
+	      $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
+	      $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
+	      $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
 
-STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ)
+STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
 
+STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
+
+# This one is special because the static tree object ends up in the mainboard
+# dir of the object tree.
+STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
 # x86emu wants libgcc
@@ -214,7 +219,7 @@
 
 STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
 
-$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED)
+$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
 	$(Q)# leave a .o with full symbols in it for debugging.
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
@@ -260,9 +265,9 @@
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
 
-$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
+$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@)) (XIP)\n"
-	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
+	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
 	$(Q)# initram links against stage0
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \

Modified: coreboot-v3/device/Makefile
===================================================================
--- coreboot-v3/device/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/device/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -24,6 +24,6 @@
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
-STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \
-		    pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o
+STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
+		    pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c
 

Modified: coreboot-v3/mainboard/adl/msm800sev/Makefile
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/adl/msm800sev/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/mainboard/amd/db800/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/db800/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/amd/db800/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/mainboard/amd/norwich/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/norwich/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/amd/norwich/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/artecgroup/dbe61/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/artecgroup/dbe62/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/emulation/qemu-x86/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -28,10 +28,10 @@
 # directory and is built from what was auto.c in v2.
 #
 
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
 
-STAGE2_MAINBOARD_OBJ = vga.o
+STAGE2_MAINBOARD_SRC = vga.c
 
 #
 # VPD or SIP ROM or... how does NVIDIA call it?

Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,9 +21,9 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =      $(src)/mainboard/$(MAINBOARDDIR)/initram.c
+INITRAM_SRC =      $(src)/mainboard/$(MAINBOARDDIR)/initram.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/mainboard/pcengines/alix1c/Makefile
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/pcengines/alix1c/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/mainboard/pcengines/alix2c3/Makefile
===================================================================
--- coreboot-v3/mainboard/pcengines/alix2c3/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/pcengines/alix2c3/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"

Modified: coreboot-v3/northbridge/amd/geodelx/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/northbridge/amd/geodelx/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,9 +21,9 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
-		      $(obj)/northbridge/amd/geodelx/vsmsetup.o \
-		      $(obj)/util/x86emu/vm86_gdt.o \
-		      $(obj)/northbridge/amd/geodelx/grphinit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \
+		      $(src)/northbridge/amd/geodelx/vsmsetup.c \
+		      $(src)/util/x86emu/vm86_gdt.c \
+		      $(src)/northbridge/amd/geodelx/grphinit.c
 
 endif

Modified: coreboot-v3/northbridge/amd/k8/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/k8/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/northbridge/amd/k8/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,6 +21,6 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/k8/raminit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/raminit.c
 
 endif

Modified: coreboot-v3/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/northbridge/intel/i440bxemulation/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,6 +21,6 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c
 
 endif

Modified: coreboot-v3/southbridge/amd/cs5536/Makefile
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/southbridge/amd/cs5536/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,10 +21,10 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o 
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c
 endif
 
 STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o

Modified: coreboot-v3/southbridge/intel/i82371eb/Makefile
===================================================================
--- coreboot-v3/southbridge/intel/i82371eb/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/southbridge/intel/i82371eb/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -20,6 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c
 
 endif

Modified: coreboot-v3/southbridge/nvidia/mcp55/Makefile
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/southbridge/nvidia/mcp55/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -21,10 +21,10 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/mcp55.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/mcp55.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/irq_tables.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/irq_tables.c
 endif
 
 STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o

Modified: coreboot-v3/superio/fintek/f71805f/Makefile
===================================================================
--- coreboot-v3/superio/fintek/f71805f/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/superio/fintek/f71805f/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -24,6 +24,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
 
 endif

Modified: coreboot-v3/superio/ite/it8716f/Makefile
===================================================================
--- coreboot-v3/superio/ite/it8716f/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/superio/ite/it8716f/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -24,6 +24,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c
 
 endif

Modified: coreboot-v3/superio/winbond/w83627hf/Makefile
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/Makefile	2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/superio/winbond/w83627hf/Makefile	2008-08-02 20:56:11 UTC (rev 714)
@@ -25,6 +25,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
 
 endif




From rminnich at gmail.com  Sat Aug  2 23:04:51 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Aug 2008 14:04:51 -0700
Subject: [coreboot] v3 : mcp55.c patch
Message-ID: <13426df10808021404m6d627760gc22b5fba60eed28a@mail.gmail.com>

this is much closer. There are more functions to bring in before it
will work at all.

ron
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From c-d.hailfinger.devel.2006 at gmx.net  Sat Aug  2 23:08:50 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 Aug 2008 23:08:50 +0200
Subject: [coreboot] [PATCH] v3: convert stage2 and initram
 makefile	rules from object to source files
In-Reply-To: <13426df10808021327g3a1e1ef8w8dc9a4a325791027@mail.gmail.com>
References: <47C9ADD4.2070009@gmx.net>
	<4894ABDE.4030801@gmx.net>	<4894BFC1.1060300@gmx.net>
	<13426df10808021327g3a1e1ef8w8dc9a4a325791027@mail.gmail.com>
Message-ID: <4894CCE2.6010809@gmx.net>

On 02.08.2008 22:27, ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>   

Thanks, r714.

Regards,
Carl-Daniel



From rminnich at gmail.com  Sat Aug  2 23:20:19 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 Aug 2008 14:20:19 -0700
Subject: [coreboot] last for the day
Message-ID: <13426df10808021420v7a25c6e7o483d03a22054b7b5@mail.gmail.com>

this at least gets through with a countable number of errors.

Final fixes tomorrow.

ron
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From cristi.magherusan at net.utcluj.ro  Sat Aug  2 23:39:14 2008
From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Sun, 03 Aug 2008 00:39:14 +0300
Subject: [coreboot] patch for buildrom's unifdef makefile
Message-ID: <1217713154.9635.9.camel@kiwi>

Unifef's build target used to depend on the .o binary file, instead of
the .c source.

This trivial patch includes a patch for the unifdef makefile and
modifies the build script to apply it.

Signed-off-by: Cristi M?gheru?an

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From peter at stuge.se  Sat Aug  2 23:47:29 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 Aug 2008 23:47:29 +0200
Subject: [coreboot] patch for buildrom's unifdef makefile
In-Reply-To: <1217713154.9635.9.camel@kiwi>
References: <1217713154.9635.9.camel@kiwi>
Message-ID: <20080802214729.3552.qmail@stuge.se>

On Sun, Aug 03, 2008 at 12:39:14AM +0300, Cristi Magherusan wrote:
> Unifef's build target used to depend on the .o binary file, instead of
> the .c source.
> 
> This trivial patch includes a patch for the unifdef makefile and
> modifies the build script to apply it.
> 
> Signed-off-by: Cristi M??gheru??an

Acked-by: Peter Stuge <peter at stuge.se>

(sorry for mangling your name here, will make it right in the commit)


> diff --git a/packages/unifdef/patches/series b/packages/unifdef/patches/series
> new file mode 100644
> index 0000000..d350737
> --- /dev/null
> +++ b/packages/unifdef/patches/series
> @@ -0,0 +1 @@
> +unifdef-build-fix.patch
> diff --git a/packages/unifdef/patches/unifdef-build-fix.patch b/packages/unifdef/patches/unifdef-build-fix.patch
> new file mode 100644
> index 0000000..33a6791
> --- /dev/null
> +++ b/packages/unifdef/patches/unifdef-build-fix.patch
> @@ -0,0 +1,14 @@
> +diff -Naur unifdef-1.0.orig/Makefile unifdef-1.0/Makefile
> +--- unifdef-1.0.orig/Makefile	2000-02-12 05:54:36.000000000 +0200
> ++++ unifdef-1.0/Makefile	2008-08-02 23:20:26.000000000 +0300
> +@@ -2,8 +2,8 @@
> + CFLAGS = -O2 
> + DEST   = /usr
> + 
> +-unifdef: unifdef.o
> +-	$(CC) unifdef.o -o unifdef
> ++unifdef: unifdef.c
> ++	$(CC) unifdef.c -o unifdef
> + 
> + clean:
> + 	rm -f unifdef *.o
> diff --git a/packages/unifdef/unifdef.mk b/packages/unifdef/unifdef.mk
> index b6e344f..d1bc7b3 100644
> --- a/packages/unifdef/unifdef.mk
> +++ b/packages/unifdef/unifdef.mk
> @@ -5,6 +5,8 @@ UNIFDEF_SRC_DIR=$(UNIFDEF_DIR)/unifdef-1.0
>  UNIFDEF_STAMP_DIR=$(UNIFDEF_DIR)/stamps
>  UNIFDEF_LOG_DIR=$(UNIFDEF_DIR)/logs
>  
> +UNIFDEF_PATCHES=$(PACKAGE_DIR)/unifdef/patches
> +
>  ifeq ($(CONFIG_VERBOSE),y)
>  UNIFDEF_BUILD_LOG=/dev/stdout
>  UNIFDEF_CONFIG_LOG=/dev/stdout
> @@ -21,9 +23,14 @@ $(UNIFDEF_STAMP_DIR)/.unpacked: $(SOURCE_DIR)/$(UNIFDEF_SOURCE) | $(UNIFDEF_STAM
>  	@ tar -C $(UNIFDEF_DIR) -zxf $(SOURCE_DIR)/$(UNIFDEF_SOURCE)
>  	@ rm -f $(UNIFDEF_SRC_DIR)/unifdef 
>  	@ rm -f $(UNIFDEF_SRC_DIR)/unifdef.o
> -	@ touch $@	
> +	@ touch $@
> +
> +$(UNIFDEF_STAMP_DIR)/.patched: $(UNIFDEF_STAMP_DIR)/.unpacked
> +	@ echo "Patching unifdef..."
> +	@ $(BIN_DIR)/doquilt.sh $(UNIFDEF_SRC_DIR) $(UNIFDEF_PATCHES)
> +	@ touch $@
>  
> -$(UNIFDEF_SRC_DIR)/unifdef: $(UNIFDEF_STAMP_DIR) $(UNIFDEF_LOG_DIR) $(UNIFDEF_STAMP_DIR)/.unpacked
> +$(UNIFDEF_SRC_DIR)/unifdef: $(UNIFDEF_STAMP_DIR) $(UNIFDEF_LOG_DIR) $(UNIFDEF_STAMP_DIR)/.patched
>  	@ echo "Building unifdef (host)..."
>  	@ $(MAKE) -C $(UNIFDEF_SRC_DIR) CC=$(HOST_CC) > $(UNIFDEF_BUILD_LOG) 2>&1
>  



From ward at gnu.org  Sun Aug  3 00:04:19 2008
From: ward at gnu.org (Ward Vandewege)
Date: Sat, 2 Aug 2008 18:04:19 -0400
Subject: [coreboot] patch for buildrom's unifdef makefile
In-Reply-To: <1217713154.9635.9.camel@kiwi>
References: <1217713154.9635.9.camel@kiwi>
Message-ID: <20080802220419.GA8922@localdomain>

On Sun, Aug 03, 2008 at 12:39:14AM +0300, Cristi Magherusan wrote:
> Unifef's build target used to depend on the .o binary file, instead of
> the .c source.
> 
> This trivial patch includes a patch for the unifdef makefile and
> modifies the build script to apply it.
> 
> Signed-off-by: Cristi M?gheru?an

Very good, this fixes doing a make distclean after a make.

Acked-by: Ward Vandewege <ward at gnu.org>

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From svn at coreboot.org  Sun Aug  3 00:14:30 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  3 Aug 2008 00:14:30 +0200
Subject: [coreboot] r213 - in buildrom-devel/packages/unifdef: . patches
Message-ID: <mailman.1768.1355071349.16123.coreboot@coreboot.org>

Author: ward
Date: 2008-08-03 00:14:30 +0200 (Sun, 03 Aug 2008)
New Revision: 213

Added:
   buildrom-devel/packages/unifdef/patches/
   buildrom-devel/packages/unifdef/patches/series
   buildrom-devel/packages/unifdef/patches/unifdef-build-fix.patch
Modified:
   buildrom-devel/packages/unifdef/unifdef.mk
Log:

Unifef's build target used to depend on the .o binary file, instead of
the .c source.

This trivial patch includes a patch for the unifdef makefile and
modifies the build script to apply it.

Signed-off-by: Cristi M?\196?\131gheru?\200?\153an <cristi.magherusan at net.utcluj.ro>
Acked-by: Peter Stuge <peter at stuge.se>
Acked-by: Ward Vandewege <ward at gnu.org>



Added: buildrom-devel/packages/unifdef/patches/series
===================================================================
--- buildrom-devel/packages/unifdef/patches/series	                        (rev 0)
+++ buildrom-devel/packages/unifdef/patches/series	2008-08-02 22:14:30 UTC (rev 213)
@@ -0,0 +1 @@
+unifdef-build-fix.patch

Added: buildrom-devel/packages/unifdef/patches/unifdef-build-fix.patch
===================================================================
--- buildrom-devel/packages/unifdef/patches/unifdef-build-fix.patch	                        (rev 0)
+++ buildrom-devel/packages/unifdef/patches/unifdef-build-fix.patch	2008-08-02 22:14:30 UTC (rev 213)
@@ -0,0 +1,14 @@
+diff -Naur unifdef-1.0.orig/Makefile unifdef-1.0/Makefile
+--- unifdef-1.0.orig/Makefile	2000-02-12 05:54:36.000000000 +0200
++++ unifdef-1.0/Makefile	2008-08-02 23:20:26.000000000 +0300
+@@ -2,8 +2,8 @@
+ CFLAGS = -O2 
+ DEST   = /usr
+ 
+-unifdef: unifdef.o
+-	$(CC) unifdef.o -o unifdef
++unifdef: unifdef.c
++	$(CC) unifdef.c -o unifdef
+ 
+ clean:
+ 	rm -f unifdef *.o

Modified: buildrom-devel/packages/unifdef/unifdef.mk
===================================================================
--- buildrom-devel/packages/unifdef/unifdef.mk	2008-07-07 15:24:19 UTC (rev 212)
+++ buildrom-devel/packages/unifdef/unifdef.mk	2008-08-02 22:14:30 UTC (rev 213)
@@ -5,6 +5,8 @@
 UNIFDEF_STAMP_DIR=$(UNIFDEF_DIR)/stamps
 UNIFDEF_LOG_DIR=$(UNIFDEF_DIR)/logs
 
+UNIFDEF_PATCHES=$(PACKAGE_DIR)/unifdef/patches
+
 ifeq ($(CONFIG_VERBOSE),y)
 UNIFDEF_BUILD_LOG=/dev/stdout
 UNIFDEF_CONFIG_LOG=/dev/stdout
@@ -21,9 +23,14 @@
 	@ tar -C $(UNIFDEF_DIR) -zxf $(SOURCE_DIR)/$(UNIFDEF_SOURCE)
 	@ rm -f $(UNIFDEF_SRC_DIR)/unifdef 
 	@ rm -f $(UNIFDEF_SRC_DIR)/unifdef.o
-	@ touch $@	
+	@ touch $@
 
-$(UNIFDEF_SRC_DIR)/unifdef: $(UNIFDEF_STAMP_DIR) $(UNIFDEF_LOG_DIR) $(UNIFDEF_STAMP_DIR)/.unpacked
+$(UNIFDEF_STAMP_DIR)/.patched: $(UNIFDEF_STAMP_DIR)/.unpacked
+	@ echo "Patching unifdef..."
+	@ $(BIN_DIR)/doquilt.sh $(UNIFDEF_SRC_DIR) $(UNIFDEF_PATCHES)
+	@ touch $@
+
+$(UNIFDEF_SRC_DIR)/unifdef: $(UNIFDEF_STAMP_DIR) $(UNIFDEF_LOG_DIR) $(UNIFDEF_STAMP_DIR)/.patched
 	@ echo "Building unifdef (host)..."
 	@ $(MAKE) -C $(UNIFDEF_SRC_DIR) CC=$(HOST_CC) > $(UNIFDEF_BUILD_LOG) 2>&1
 




From ward at gnu.org  Sun Aug  3 00:15:38 2008
From: ward at gnu.org (Ward Vandewege)
Date: Sat, 2 Aug 2008 18:15:38 -0400
Subject: [coreboot] patch for buildrom's unifdef makefile
In-Reply-To: <20080802220419.GA8922@localdomain>
References: <1217713154.9635.9.camel@kiwi> <20080802220419.GA8922@localdomain>
Message-ID: <20080802221538.GA9598@localdomain>

On Sat, Aug 02, 2008 at 06:04:19PM -0400, Ward Vandewege wrote:
> On Sun, Aug 03, 2008 at 12:39:14AM +0300, Cristi Magherusan wrote:
> > Unifef's build target used to depend on the .o binary file, instead of
> > the .c source.
> > 
> > This trivial patch includes a patch for the unifdef makefile and
> > modifies the build script to apply it.
> > 
> > Signed-off-by: Cristi M?gheru?an
> 
> Very good, this fixes doing a make distclean after a make.
> 
> Acked-by: Ward Vandewege <ward at gnu.org>

Committed in r213.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From svn at coreboot.org  Sun Aug  3 12:35:07 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  3 Aug 2008 12:35:07 +0200
Subject: [coreboot] r3467 - in trunk/coreboot-v2/src: arch/i386/lib pc80
Message-ID: <mailman.1769.1355071349.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-03 12:35:06 +0200 (Sun, 03 Aug 2008)
New Revision: 3467

Modified:
   trunk/coreboot-v2/src/arch/i386/lib/console.c
   trunk/coreboot-v2/src/arch/i386/lib/console_print.c
   trunk/coreboot-v2/src/pc80/serial.c
Log:
fix lots of warnings for cache as ram builds (trivial)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/arch/i386/lib/console.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/console.c	2008-08-02 19:17:42 UTC (rev 3466)
+++ trunk/coreboot-v2/src/arch/i386/lib/console.c	2008-08-03 10:35:06 UTC (rev 3467)
@@ -13,9 +13,11 @@
 
 #include "console_printk.c"
 
+#if CONFIG_USE_INIT == 0
 // do_printk
 #include "../../../console/vtxprintf.c"
 #include "printk_init.c"
+#endif
 
 #endif /* CONFIG_USE_PRINTK_IN_CAR */
 
@@ -23,7 +25,6 @@
 #define COREBOOT_EXTRA_VERSION ""
 #endif
 
-
 static void console_init(void)
 {
 	static const char console_test[] = 

Modified: trunk/coreboot-v2/src/arch/i386/lib/console_print.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/console_print.c	2008-08-02 19:17:42 UTC (rev 3466)
+++ trunk/coreboot-v2/src/arch/i386/lib/console_print.c	2008-08-03 10:35:06 UTC (rev 3467)
@@ -58,58 +58,67 @@
 	}
 }
 
-#define NOINLINE __attribute__((noinline))
-static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
-static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
-static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
-static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
-static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
+/* Actually this should say defined(__ROMCC__) but that define is explicitly
+ * set in some auto.c files to trigger the simple device_t version to be used.
+ * So __GNUCC__ does the right thing here.
+ */
+#if defined (__GNUCC__)
+#define STATIC
+#else
+#define STATIC static
+#endif
 
-static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
-static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
-static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
-static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
-static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
+STATIC void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
+STATIC void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
+STATIC void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
+STATIC void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
+STATIC void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
 
-static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
-static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
-static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
-static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
-static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
+STATIC void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
+STATIC void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
+STATIC void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
+STATIC void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
+STATIC void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
 
-static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
-static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
-static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
-static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
-static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
+STATIC void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
+STATIC void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
+STATIC void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
+STATIC void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
+STATIC void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
 
-static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
-static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
-static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
-static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
-static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
+STATIC void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
+STATIC void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
+STATIC void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
+STATIC void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
+STATIC void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
 
-static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
-static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
-static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
-static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
-static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
+STATIC void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
+STATIC void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
+STATIC void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
+STATIC void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
+STATIC void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
 
-static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
-static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
-static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
-static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
-static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
+STATIC void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
+STATIC void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
+STATIC void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
+STATIC void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
+STATIC void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
 
-static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
-static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
-static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
-static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
-static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
+STATIC void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
+STATIC void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
+STATIC void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
+STATIC void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
+STATIC void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
 
-static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
-static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
-static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
-static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
-static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
+STATIC void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
+STATIC void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
+STATIC void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
+STATIC void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
+STATIC void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
 
+STATIC void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
+STATIC void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
+STATIC void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
+STATIC void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
+STATIC void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
+

Modified: trunk/coreboot-v2/src/pc80/serial.c
===================================================================
--- trunk/coreboot-v2/src/pc80/serial.c	2008-08-02 19:17:42 UTC (rev 3466)
+++ trunk/coreboot-v2/src/pc80/serial.c	2008-08-03 10:35:06 UTC (rev 3467)
@@ -91,8 +91,13 @@
 #endif
 	outb(UART_LCS, TTYS0_BASE + UART_LCR);
 }
+
 #else
+/* CONFIG_USE_PRINTK_IN_CAR == 1 */
+#if CONFIG_USE_INIT == 0
 #include "../lib/uart8250.c"
+#endif
+
 extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
 static void uart_init(void)
 {




From svn at coreboot.org  Sun Aug  3 12:38:27 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  3 Aug 2008 12:38:27 +0200
Subject: [coreboot] r3468 - trunk/coreboot-v2/src/boot
Message-ID: <mailman.1770.1355071349.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-03 12:38:26 +0200 (Sun, 03 Aug 2008)
New Revision: 3468

Modified:
   trunk/coreboot-v2/src/boot/elfboot.c
Log:
Remove welcome message from elfboot. None of the other subsystems have their
own welcome message.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/boot/elfboot.c
===================================================================
--- trunk/coreboot-v2/src/boot/elfboot.c	2008-08-03 10:35:06 UTC (rev 3467)
+++ trunk/coreboot-v2/src/boot/elfboot.c	2008-08-03 10:38:26 UTC (rev 3468)
@@ -609,11 +609,7 @@
 	int i, result;
 
 	result = 0;
-	printk_info("\n");
-	printk_info("Welcome to %s, the open sourced starter.\n", BOOTLOADER);
-	printk_info("January 2002, Eric Biederman.\n");
-	printk_info("Version %s\n", BOOTLOADER_VERSION);
-	printk_info("\n");
+	printk_debug("\nelfboot: Attempting to load payload.\n");
 	post_code(0xf8);
 
 	if (stream_init() < 0) {




From c-d.hailfinger.devel.2006 at gmx.net  Sun Aug  3 12:46:32 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Aug 2008 12:46:32 +0200
Subject: [coreboot] last for the day
In-Reply-To: <13426df10808021420v7a25c6e7o483d03a22054b7b5@mail.gmail.com>
References: <13426df10808021420v7a25c6e7o483d03a22054b7b5@mail.gmail.com>
Message-ID: <48958C88.80606@gmx.net>

On 02.08.2008 23:20, ron minnich wrote:
> this at least gets through with a countable number of errors.
>
> Final fixes tomorrow.
>
> Get it to at least mostly compile
>
> Somehow there were two copies of the file in the file -- svn weirdness?
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Sun Aug  3 12:57:51 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Aug 2008 12:57:51 +0200
Subject: [coreboot] v3 : mcp55.c patch
In-Reply-To: <13426df10808021404m6d627760gc22b5fba60eed28a@mail.gmail.com>
References: <13426df10808021404m6d627760gc22b5fba60eed28a@mail.gmail.com>
Message-ID: <48958F2F.6060109@gmx.net>

On 02.08.2008 23:04, ron minnich wrote:
> this is much closer. There are more functions to bring in before it
> will work at all.
>
> mcp55.c compiles. stage1.c does not. Nevertheless this is worth getting committed for others to see
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

I'm not entirely happy about the quality of the underlying code, but
your patch is a real improvement.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel



From r.marek at assembler.cz  Sun Aug  3 17:36:26 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 03 Aug 2008 17:36:26 +0200
Subject: [coreboot] VIA picks up the pace
In-Reply-To: <m1k5f7o2bk.fsf@frodo.ebiederm.org>
References: <4888D7F4.6010606@gmx.net> <m1k5f7o2bk.fsf@frodo.ebiederm.org>
Message-ID: <4895D07A.6070504@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

Please check the Linux VIA portal. There are freely downloadable PDFs with docs
for VX800/CX700. Plus more driver code.

http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241
http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iD8DBQFIldB63J9wPJqZRNURArujAJ9HgV6p/8Xes5z44sHA6dZzcXOsgACg4KHU
psvtGfAA2tui+WfY9Ijv8LU=
=xNhw
-----END PGP SIGNATURE-----



From uwe at hermann-uwe.de  Sun Aug  3 18:56:49 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 3 Aug 2008 18:56:49 +0200
Subject: [coreboot] last for the day
In-Reply-To: <13426df10808021420v7a25c6e7o483d03a22054b7b5@mail.gmail.com>
References: <13426df10808021420v7a25c6e7o483d03a22054b7b5@mail.gmail.com>
Message-ID: <20080803165649.GB6389@greenwood>

On Sat, Aug 02, 2008 at 02:20:19PM -0700, ron minnich wrote:
> @@ -871,12 +871,10 @@
>  	}
>  
>  	/* Report the amount of memory. */
> -	print_spew("RAM: 0x");
> -	print_spew_hex32(tom_k);
> -	print_spew(" KB\r\n");
> +	printk(BIOS_SPEW, "RAM: 0x%x DB\n", tom_k);

DB -> KB

Also, we partially use \n and partially \r\n in printk in v3, is there
some reason for that? Shall we move everything to \n only?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Sun Aug  3 19:03:13 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 3 Aug 2008 19:03:13 +0200
Subject: [coreboot] v3 : mcp55.c patch
In-Reply-To: <13426df10808021404m6d627760gc22b5fba60eed28a@mail.gmail.com>
References: <13426df10808021404m6d627760gc22b5fba60eed28a@mail.gmail.com>
Message-ID: <20080803170313.GC6389@greenwood>

On Sat, Aug 02, 2008 at 02:04:51PM -0700, ron minnich wrote:
> Index: southbridge/nvidia/mcp55/stage1.c
> ===================================================================
> --- southbridge/nvidia/mcp55/stage1.c	(revision 713)
> +++ southbridge/nvidia/mcp55/stage1.c	(working copy)
> @@ -19,6 +19,17 @@
>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>   */
>  
> +#include <console.h>
> +#include <io.h>
> +#include <device/device.h>
> +#include <device/pci.h>


> +#include <device/pci_ids.h>
> +#include <device/pci_ops.h>

These two are not needed, pci.h already includes them.


> -static uint32_t final_reg;
> +static u32 final_reg;

Is the static really needed or a romcc artifact?

  
Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Sun Aug  3 19:07:50 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 3 Aug 2008 19:07:50 +0200
Subject: [coreboot] r3463 - trunk/coreboot-v2/src/cpu/x86/car
In-Reply-To: <20080802172117.27305.qmail@stuge.se>
References: <E1KPIjy-00017F-Km@mi011.mc1.hosteurope.de>
	<20080802170519.GB10143@greenwood>
	<20080802172117.27305.qmail@stuge.se>
Message-ID: <20080803170749.GD6389@greenwood>

On Sat, Aug 02, 2008 at 07:21:17PM +0200, Peter Stuge wrote:
> On Sat, Aug 02, 2008 at 07:05:19PM +0200, Uwe Hermann wrote:
> > On Sat, Aug 02, 2008 at 05:09:13PM +0200, svn at coreboot.org wrote:
> > >  #if CONFIG_USE_INIT
> > > -	printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
> > > +	printk_spew("linxbios_ram.bin length = %08x\r\n", olen);
> > >  #else
> > > -	print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
> > > +	print_spew("linxbios_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");
> > 
> > Should we also fix this while we're at it? "linx" -> "linux", or even
> > better "linxbios" -> "coreboot"?
> 
> That would be great.

Done in r3466.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From c-d.hailfinger.devel.2006 at gmx.net  Sun Aug  3 20:17:50 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Aug 2008 20:17:50 +0200
Subject: [coreboot] last for the day
In-Reply-To: <20080803165649.GB6389@greenwood>
References: <13426df10808021420v7a25c6e7o483d03a22054b7b5@mail.gmail.com>
	<20080803165649.GB6389@greenwood>
Message-ID: <4895F64E.8050404@gmx.net>

On 03.08.2008 18:56, Uwe Hermann wrote:
> On Sat, Aug 02, 2008 at 02:20:19PM -0700, ron minnich wrote:
>   
>> @@ -871,12 +871,10 @@
>>  	}
>>  
>>  	/* Report the amount of memory. */
>> -	print_spew("RAM: 0x");
>> -	print_spew_hex32(tom_k);
>> -	print_spew(" KB\r\n");
>> +	printk(BIOS_SPEW, "RAM: 0x%x DB\n", tom_k);
>>     
>
> DB -> KB
>
> Also, we partially use \n and partially \r\n in printk in v3, is there
> some reason for that? Shall we move everything to \n only?
>   

The \r\n is a a legacy from v2. The future is \n only.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Sun Aug  3 21:36:53 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  3 Aug 2008 21:36:53 +0200
Subject: [coreboot] r715 - coreboot-v3/northbridge/amd/k8
Message-ID: <mailman.1771.1355071349.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-03 21:36:53 +0200 (Sun, 03 Aug 2008)
New Revision: 715

Modified:
   coreboot-v3/northbridge/amd/k8/raminit.c
Log:
This mostly compiles. 

Also, per Uwe, remove the \r\n for \n

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-02 20:56:11 UTC (rev 714)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-03 19:36:53 UTC (rev 715)
@@ -52,7 +52,7 @@
 		struct device *dev;
 		unsigned where;
 		unsigned long reg;
-		printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+		printk(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]);
 		dev = register_values[i] & ~0xfff;
 		where = register_values[i] & 0xfff;
 		reg = pci_read_config32(dev, where);
@@ -61,7 +61,7 @@
 		pci_write_config32(dev, where, reg);
 	}
 */
-	printk(BIOS_DEBUG, "done.\r\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static int controller_present(const struct mem_controller *ctrl)
@@ -543,7 +543,7 @@
 	int max;
 
         if (!controller_present(ctrl)) {
-                printk(BIOS_DEBUG, "No memory controller present\r\n");
+                printk(BIOS_DEBUG, "No memory controller present\n");
                 return;
         }
 	printk(BIOS_SPEW, "setting up CPU 0x%x northbridge registers ", ctrl->node_id);
@@ -552,7 +552,7 @@
 		struct device *dev;
 		unsigned where;
 		unsigned long reg;
-                printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+                printk(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]);
 		dev = (register_values[i] & ~0xfff) - PCI_BDF(0, 0x18, 0) + ctrl->f0;
 		where = register_values[i] & 0xfff;
 		reg = pci_read_config32(dev, where);
@@ -560,7 +560,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	printk(BIOS_SPEW, "done.\r\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
 
@@ -695,7 +695,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	sz.side1 = 0;
@@ -857,7 +857,7 @@
 
 	limit_reg = 0x44 + index;
 	base_reg = 0x40 + index;
-	for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
+	for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) {
 		pci_write_config32(device, limit_reg, limit);
 		pci_write_config32(device, base_reg, base);
 	}
@@ -871,12 +871,10 @@
 	}
 
 	/* Report the amount of memory. */
-	print_spew("RAM: 0x");
-	print_spew_hex32(tom_k);
-	print_spew(" KB\r\n");
+	printk(BIOS_SPEW, "RAM: 0x%x KB\n", tom_k);
 
 	/* Now set top of memory */
-	msr_t msr;
+	struct msr msr;
 	if(tom_k > (4*1024*1024)) {
 		msr.lo = (tom_k & 0x003fffff) << 10;
 		msr.hi = (tom_k & 0xffc00000) >> 22;
@@ -988,7 +986,7 @@
 		if(is_dual_channel(ctrl)) {
                 /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
 	                if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-//     		                printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\r\n");
+//     		                printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\n");
 	                        return 0;
                 	}  
 			csbase_inc <<=1;
@@ -998,7 +996,7 @@
 		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
 		if(is_dual_channel(ctrl)) {
 	                if( (bits==3) && (common_cs_mode > 8)) {
-//        	                printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\r\n");
+//        	                printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n");
         	                return 0;
 			}
 			csbase_inc <<=1;
@@ -1124,7 +1122,7 @@
 	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
-		printk(BIOS_DEBUG, "Interleaving disabled\r\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
 	if (!tom_k) {
@@ -1195,9 +1193,9 @@
 	}
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	if (is_registered(ctrl)) {
-		printk(BIOS_DEBUG, "Registered\r\n");
+		printk(BIOS_DEBUG, "Registered\n");
 	} else {
-		printk(BIOS_DEBUG, "Unbuffered\r\n");
+		printk(BIOS_DEBUG, "Unbuffered\n");
 	}
 	return dimm_mask;
 }
@@ -1291,7 +1289,7 @@
 			}
 		}
 	}
-	printk(BIOS_SPEW, "Enabling dual channel memory\r\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	u32 dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_32ByteEn;
@@ -1321,7 +1319,7 @@
 {
 	static const struct mem_param speed[] = {
 		{
-			.name	    = "100Mhz\r\n",
+			.name	    = "100Mhz\n",
 			.cycle_time = 0xa0,
 			.divisor    = (10 <<1),
 			.tRC	    = 0x46,
@@ -1335,7 +1333,7 @@
 			.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
 		},
 		{
-			.name	    = "133Mhz\r\n",
+			.name	    = "133Mhz\n",
 			.cycle_time = 0x75,
 			.divisor    = (7<<1)+1,
 			.tRC	    = 0x41,
@@ -1349,7 +1347,7 @@
 			.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
 		},
 		{
-			.name	    = "166Mhz\r\n",
+			.name	    = "166Mhz\n",
 			.cycle_time = 0x60,
 			.divisor    = (6<<1),
 			.tRC	    = 0x3C,
@@ -1363,7 +1361,7 @@
 			.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
 		},
 		{
-			.name	    = "200Mhz\r\n",
+			.name	    = "200Mhz\n",
 			.cycle_time = 0x50,
 			.divisor    = (5<<1),
 			.tRC	    = 0x37,
@@ -1389,7 +1387,7 @@
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	print_spew(param->name);
+	printk(BIOS_SPEW, param->name);
 #ifdef DRAM_MIN_CYCLE_TIME
 	printk(BIOS_DEBUG, param->name);
 #endif
@@ -1914,7 +1912,7 @@
 
 	clocks = param->dtl_trwt[lat][mtype];
 	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
-		die("Unknown Trwt\r\n");
+		die("Unknown Trwt\n");
 	}
 	
 	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
@@ -2082,14 +2080,14 @@
 	const struct mem_param *param;
 	long dimm_mask;
 	if (!controller_present(ctrl)) {
-		printk(BIOS_DEBUG, "No memory controller present\r\n");
+		printk(BIOS_DEBUG, "No memory controller present\n");
 		return;
 	}
 	hw_enable_ecc(ctrl);
 	activate_spd_rom(ctrl);
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk(BIOS_DEBUG, "No memory for this cpu\r\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);        
@@ -2113,7 +2111,7 @@
 	return;
  hw_spd_err:
 	/* Unrecoverable error reading SPD data */
-	print_err("SPD error - reset\r\n");
+	print_err("SPD error - reset\n");
 	hard_reset();
 	return;
 }
@@ -2235,7 +2233,7 @@
 
 	/* Error if I don't have memory */
 	if (memory_end_k(ctrl, controllers) == 0) {
-		die("No memory\r\n");
+		die("No memory\n");
 	}
 
 	/* Before enabling memory start the memory clocks */
@@ -2276,7 +2274,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			u32 mnc;
-			print_spew("ECC enabled\r\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_128BitEn) {
@@ -2315,7 +2313,7 @@
 			}
 		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk(BIOS_DEBUG, " failed\r\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -2328,7 +2326,7 @@
 			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
 		}
 
-		printk(BIOS_DEBUG, " done\r\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if HW_MEM_HOLE_SIZEK != 0
@@ -2361,10 +2359,10 @@
         for(i=0;i<controllers; i++) {
                 ctrl = &ctrl_a[i];
                 ctrl->node_id = i;
-                ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
-                ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
-                ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
-                ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
+                ctrl->f0 = PCI_BDF(0, 0x18+i, 0);
+                ctrl->f1 = PCI_BDF(0, 0x18+i, 1);
+                ctrl->f2 = PCI_BDF(0, 0x18+i, 2);
+                ctrl->f3 = PCI_BDF(0, 0x18+i, 3);
 
                 if(spd_addr == (void *)0) continue;
 
@@ -2374,2383 +2372,3 @@
                 }
         }
 }
-#endif
-
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Linux Networx
- * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
- * Copyright (C) 2004 YingHai Lu
- * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-/*	This should be done by Eric
-	2004.11 yhlu add 4 rank DIMM support
-	2004.12 yhlu add D0 support
-	2005.02 yhlu add E0 memory hole support
-*/
-/* not yet 
-#if K8_REV_F_SUPPORT == 1
-        #include "raminit_f.c"
-#else
- */
-
-#include <mem.h>
-#include <cache.h>
-#include <mtrr.h>
-#include "raminit.h"
-#include "k8.h"
-#include "sysconf.h"
-
-#ifndef QRANK_DIMM_SUPPORT
-#define QRANK_DIMM_SUPPORT 0
-#endif
-
-static void hard_reset(void);
-
-static void setup_resource_map(const unsigned int *register_values, int max)
-{
-	int i;
-	printk(BIOS_DEBUG, "setting up resource map....");
-	for(i = 0; i < max; i += 3) {
-		struct device *dev;
-		unsigned where;
-		unsigned long reg;
-		printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
-		dev = register_values[i] & ~0xfff;
-		where = register_values[i] & 0xfff;
-		reg = pci_read_config32(dev, where);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-		pci_write_config32(dev, where, reg);
-	}
-	printk(BIOS_DEBUG, "done.\r\n");
-}
-
-static int controller_present(const struct mem_controller *ctrl)
-{
-        return pci_read_config32(ctrl->f0, 0) == 0x11001022;
-}
-
-static void sdram_set_registers(const struct mem_controller *ctrl)
-{
-	static const unsigned int register_values[] = {
-
-	/* Careful set limit registers before base registers which contain the enables */
-	/* DRAM Limit i Registers
-	 * F1:0x44 i = 0
-	 * F1:0x4C i = 1
-	 * F1:0x54 i = 2
-	 * F1:0x5C i = 3
-	 * F1:0x64 i = 4
-	 * F1:0x6C i = 5
-	 * F1:0x74 i = 6
-	 * F1:0x7C i = 7
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 7: 3] Reserved
-	 * [10: 8] Interleave select
-	 *	   specifies the values of A[14:12] to use with interleave enable.
-	 * [15:11] Reserved
-	 * [31:16] DRAM Limit Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40 bit  address
-	 *	   that define the end of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-	/* DRAM Base i Registers
-	 * F1:0x40 i = 0
-	 * F1:0x48 i = 1
-	 * F1:0x50 i = 2
-	 * F1:0x58 i = 3
-	 * F1:0x60 i = 4
-	 * F1:0x68 i = 5
-	 * F1:0x70 i = 6
-	 * F1:0x78 i = 7
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 7: 2] Reserved
-	 * [10: 8] Interleave Enable
-	 *	   000 = No interleave
-	 *	   001 = Interleave on A[12] (2 nodes)
-	 *	   010 = reserved
-	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
-	 *	   100 = reserved
-	 *	   101 = reserved
-	 *	   110 = reserved
-	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-	 * [15:11] Reserved
-	 * [13:16] DRAM Base Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40-bit address
-	 *	   that define the start of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
-	/* DRAM CS Base Address i Registers
-	 * F2:0x40 i = 0
-	 * F2:0x44 i = 1
-	 * F2:0x48 i = 2
-	 * F2:0x4C i = 3
-	 * F2:0x50 i = 4
-	 * F2:0x54 i = 5
-	 * F2:0x58 i = 6
-	 * F2:0x5C i = 7
-	 * [ 0: 0] Chip-Select Bank Enable
-	 *	   0 = Bank Disabled
-	 *	   1 = Bank Enabled
-	 * [ 8: 1] Reserved
-	 * [15: 9] Base Address (19-13)
-	 *	   An optimization used when all DIMM are the same size...
-	 * [20:16] Reserved
-	 * [31:21] Base Address (35-25)
-	 *	   This field defines the top 11 addresses bit of a 40-bit
-	 *	   address that define the memory address space.  These
-	 *	   bits decode 32-MByte blocks of memory.
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x58), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x5C), 0x001f01fe, 0x00000000,
-	/* DRAM CS Mask Address i Registers
-	 * F2:0x60 i = 0
-	 * F2:0x64 i = 1
-	 * F2:0x68 i = 2
-	 * F2:0x6C i = 3
-	 * F2:0x70 i = 4
-	 * F2:0x74 i = 5
-	 * F2:0x78 i = 6
-	 * F2:0x7C i = 7
-	 * Select bits to exclude from comparison with the DRAM Base address register.
-	 * [ 8: 0] Reserved
-	 * [15: 9] Address Mask (19-13)
-	 *	   Address to be excluded from the optimized case
-	 * [20:16] Reserved
-	 * [29:21] Address Mask (33-25)
-	 *	   The bits with an address mask of 1 are excluded from address comparison
-	 * [31:30] Reserved
-	 * 
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x78), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x7C), 0xC01f01ff, 0x00000000,
-	/* DRAM Bank Address Mapping Register
-	 * F2:0x80
-	 * Specify the memory module size
-	 * [ 2: 0] CS1/0 
-	 * [ 6: 4] CS3/2
-	 * [10: 8] CS5/4
-	 * [14:12] CS7/6
-	 *	   000 = 32Mbyte  (Rows = 12 & Col =  8)
-	 *	   001 = 64Mbyte  (Rows = 12 & Col =  9)
-	 *	   010 = 128Mbyte (Rows = 13 & Col =  9)|(Rows = 12 & Col = 10)
-	 *	   011 = 256Mbyte (Rows = 13 & Col = 10)|(Rows = 12 & Col = 11)
-	 *	   100 = 512Mbyte (Rows = 13 & Col = 11)|(Rows = 14 & Col = 10)
-	 *	   101 = 1Gbyte	  (Rows = 14 & Col = 11)|(Rows = 13 & Col = 12)
-	 *	   110 = 2Gbyte	  (Rows = 14 & Col = 12)
-	 *	   111 = reserved 
-	 * [ 3: 3] Reserved
-	 * [ 7: 7] Reserved
-	 * [11:11] Reserved
-	 * [31:15]
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000000,
-	/* DRAM Timing Low Register
-	 * F2:0x88
-	 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
-	 *	   000 = reserved
-	 *	   001 = CL 2
-	 *	   010 = CL 3
-	 *	   011 = reserved
-	 *	   100 = reserved
-	 *	   101 = CL 2.5
-	 *	   110 = reserved
-	 *	   111 = reserved
-	 * [ 3: 3] Reserved
-	 * [ 7: 4] Trc (Row Cycle Time, Ras#-active to Ras#-active/bank auto refresh)
-	 *	   0000 =  7 bus clocks
-	 *	   0001 =  8 bus clocks
-	 *	   ...
-	 *	   1110 = 21 bus clocks
-	 *	   1111 = 22 bus clocks
-	 * [11: 8] Trfc (Row refresh Cycle time, Auto-refresh-active to RAS#-active or RAS#auto-refresh)
-	 *	   0000 = 9 bus clocks
-	 *	   0010 = 10 bus clocks
-	 *	   ....
-	 *	   1110 = 23 bus clocks
-	 *	   1111 = 24 bus clocks
-	 * [14:12] Trcd (Ras#-active to Case#-read/write Delay)
-	 *	   000 = reserved
-	 *	   001 = reserved
-	 *	   010 = 2 bus clocks
-	 *	   011 = 3 bus clocks
-	 *	   100 = 4 bus clocks
-	 *	   101 = 5 bus clocks
-	 *	   110 = 6 bus clocks
-	 *	   111 = reserved
-	 * [15:15] Reserved
-	 * [18:16] Trrd (Ras# to Ras# Delay)
-	 *	   000 = reserved
-	 *	   001 = reserved
-	 *	   010 = 2 bus clocks
-	 *	   011 = 3 bus clocks
-	 *	   100 = 4 bus clocks
-	 *	   101 = reserved
-	 *	   110 = reserved
-	 *	   111 = reserved
-	 * [19:19] Reserved
-	 * [23:20] Tras (Minmum Ras# Active Time)
-	 *	   0000 to 0100 = reserved
-	 *	   0101 = 5 bus clocks
-	 *	   ...
-	 *	   1111 = 15 bus clocks
-	 * [26:24] Trp (Row Precharge Time)
-	 *	   000 = reserved
-	 *	   001 = reserved
-	 *	   010 = 2 bus clocks
-	 *	   011 = 3 bus clocks
-	 *	   100 = 4 bus clocks
-	 *	   101 = 5 bus clocks
-	 *	   110 = 6 bus clocks
-	 *	   111 = reserved
-	 * [27:27] Reserved
-	 * [28:28] Twr (Write Recovery Time)
-	 *	   0 = 2 bus clocks
-	 *	   1 = 3 bus clocks
-	 * [31:29] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x02522001 /* 0x03623125 */ ,
-	/* DRAM Timing High Register
-	 * F2:0x8C
-	 * [ 0: 0] Twtr (Write to Read Delay)
-	 *	   0 = 1 bus Clocks
-	 *	   1 = 2 bus Clocks
-	 * [ 3: 1] Reserved
-	 * [ 6: 4] Trwt (Read to Write Delay)
-	 *	   000 = 1 bus clocks
-	 *	   001 = 2 bus clocks
-	 *	   010 = 3 bus clocks
-	 *	   011 = 4 bus clocks
-	 *	   100 = 5 bus clocks
-	 *	   101 = 6 bus clocks
-	 *	   110 = reserved
-	 *	   111 = reserved
-	 * [ 7: 7] Reserved
-	 * [12: 8] Tref (Refresh Rate)
-	 *	   00000 = 100Mhz 4K rows
-	 *	   00001 = 133Mhz 4K rows
-	 *	   00010 = 166Mhz 4K rows
-	 *	   00011 = 200Mhz 4K rows
-	 *	   01000 = 100Mhz 8K/16K rows
-	 *	   01001 = 133Mhz 8K/16K rows
-	 *	   01010 = 166Mhz 8K/16K rows
-	 *	   01011 = 200Mhz 8K/16K rows
-	 * [19:13] Reserved
-	 * [22:20] Twcl (Write CAS Latency)
-	 *	   000 = 1 Mem clock after CAS# (Unbuffered Dimms)
-	 *	   001 = 2 Mem clocks after CAS# (Registered Dimms)
-	 * [31:23] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
-	/* DRAM Config Low Register
-	 * F2:0x90
-	 * [ 0: 0] DLL Disable
-	 *	   0 = Enabled
-	 *	   1 = Disabled
-	 * [ 1: 1] D_DRV
-	 *	   0 = Normal Drive
-	 *	   1 = Weak Drive
-	 * [ 2: 2] QFC_EN
-	 *	   0 = Disabled
-	 *	   1 = Enabled
-	 * [ 3: 3] Disable DQS Hystersis  (FIXME handle this one carefully)
-	 *	   0 = Enable DQS input filter 
-	 *	   1 = Disable DQS input filtering 
-	 * [ 7: 4] Reserved
-	 * [ 8: 8] DRAM_Init
-	 *	   0 = Initialization done or not yet started.
-	 *	   1 = Initiate DRAM intialization sequence
-	 * [ 9: 9] SO-Dimm Enable
-	 *	   0 = Do nothing
-	 *	   1 = SO-Dimms present
-	 * [10:10] DramEnable
-	 *	   0 = DRAM not enabled
-	 *	   1 = DRAM initialized and enabled
-	 * [11:11] Memory Clear Status
-	 *	   0 = Memory Clear function has not completed
-	 *	   1 = Memory Clear function has completed
-	 * [12:12] Exit Self-Refresh
-	 *	   0 = Exit from self-refresh done or not yet started
-	 *	   1 = DRAM exiting from self refresh
-	 * [13:13] Self-Refresh Status
-	 *	   0 = Normal Operation
-	 *	   1 = Self-refresh mode active
-	 * [15:14] Read/Write Queue Bypass Count
-	 *	   00 = 2
-	 *	   01 = 4
-	 *	   10 = 8
-	 *	   11 = 16
-	 * [16:16] 128-bit/64-Bit
-	 *	   0 = 64bit Interface to DRAM
-	 *	   1 = 128bit Interface to DRAM
-	 * [17:17] DIMM ECC Enable
-	 *	   0 = Some DIMMs do not have ECC
-	 *	   1 = ALL DIMMS have ECC bits
-	 * [18:18] UnBuffered DIMMs
-	 *	   0 = Buffered DIMMS
-	 *	   1 = Unbuffered DIMMS
-	 * [19:19] Enable 32-Byte Granularity
-	 *	   0 = Optimize for 64byte bursts
-	 *	   1 = Optimize for 32byte bursts
-	 * [20:20] DIMM 0 is x4
-	 * [21:21] DIMM 1 is x4
-	 * [22:22] DIMM 2 is x4
-	 * [23:23] DIMM 3 is x4
-	 *	   0 = DIMM is not x4
-	 *	   1 = x4 DIMM present
-	 * [24:24] Disable DRAM Receivers
-	 *	   0 = Receivers enabled
-	 *	   1 = Receivers disabled
-	 * [27:25] Bypass Max
-	 *	   000 = Arbiters chois is always respected
-	 *	   001 = Oldest entry in DCQ can be bypassed 1 time
-	 *	   010 = Oldest entry in DCQ can be bypassed 2 times
-	 *	   011 = Oldest entry in DCQ can be bypassed 3 times
-	 *	   100 = Oldest entry in DCQ can be bypassed 4 times
-	 *	   101 = Oldest entry in DCQ can be bypassed 5 times
-	 *	   110 = Oldest entry in DCQ can be bypassed 6 times
-	 *	   111 = Oldest entry in DCQ can be bypassed 7 times
-	 * [31:28] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
-	(4 << 25)|(0 << 24)| 
-	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
-	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| 
-	(2 << 14)|(0 << 13)|(0 << 12)| 
-	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
-	(0 << 3) |(0 << 1) |(0 << 0),
-	/* DRAM Config High Register
-	 * F2:0x94
-	 * [ 0: 3] Maximum Asynchronous Latency
-	 *	   0000 = 0 ns
-	 *	   ...
-	 *	   1111 = 15 ns
-	 * [ 7: 4] Reserved
-	 * [11: 8] Read Preamble
-	 *	   0000 = 2.0 ns
-	 *	   0001 = 2.5 ns
-	 *	   0010 = 3.0 ns
-	 *	   0011 = 3.5 ns
-	 *	   0100 = 4.0 ns
-	 *	   0101 = 4.5 ns
-	 *	   0110 = 5.0 ns
-	 *	   0111 = 5.5 ns
-	 *	   1000 = 6.0 ns
-	 *	   1001 = 6.5 ns
-	 *	   1010 = 7.0 ns
-	 *	   1011 = 7.5 ns
-	 *	   1100 = 8.0 ns
-	 *	   1101 = 8.5 ns
-	 *	   1110 = 9.0 ns
-	 *	   1111 = 9.5 ns
-	 * [15:12] Reserved
-	 * [18:16] Idle Cycle Limit
-	 *	   000 = 0 cycles
-	 *	   001 = 4 cycles
-	 *	   010 = 8 cycles
-	 *	   011 = 16 cycles
-	 *	   100 = 32 cycles
-	 *	   101 = 64 cycles
-	 *	   110 = 128 cycles
-	 *	   111 = 256 cycles
-	 * [19:19] Dynamic Idle Cycle Center Enable
-	 *	   0 = Use Idle Cycle Limit
-	 *	   1 = Generate a dynamic Idle cycle limit
-	 * [22:20] DRAM MEMCLK Frequency
-	 *	   000 = 100Mhz
-	 *	   001 = reserved
-	 *	   010 = 133Mhz
-	 *	   011 = reserved
-	 *	   100 = reserved
-	 *	   101 = 166Mhz
-	 *	   110 = reserved
-	 *	   111 = reserved
-	 * [24:23] Reserved
-	 * [25:25] Memory Clock Ratio Valid (FIXME carefully enable memclk)
-	 *	   0 = Disable MemClks
-	 *	   1 = Enable MemClks
-	 * [26:26] Memory Clock 0 Enable
-	 *	   0 = Disabled
-	 *	   1 = Enabled
-	 * [27:27] Memory Clock 1 Enable
-	 *	   0 = Disabled
-	 *	   1 = Enabled
-	 * [28:28] Memory Clock 2 Enable
-	 *	   0 = Disabled
-	 *	   1 = Enabled
-	 * [29:29] Memory Clock 3 Enable
-	 *	   0 = Disabled
-	 *	   1 = Enabled
-	 * [31:30] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0,
-	(0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)|
-	(0 << 20)|(0 << 19)|(DCH_IDLE_LIMIT_16 << 16)|(0 << 8)|(0 << 0),
-	/* DRAM Delay Line Register
-	 * F2:0x98
-	 * Adjust the skew of the input DQS strobe relative to DATA
-	 * [15: 0] Reserved
-	 * [23:16] Delay Line Adjust
-	 *	   Adjusts the DLL derived PDL delay by one or more delay stages
-	 *	   in either the faster or slower direction.
-	 * [24:24} Adjust Slower
-	 *	   0 = Do Nothing
-	 *	   1 = Adj is used to increase the PDL delay
-	 * [25:25] Adjust Faster
-	 *	   0 = Do Nothing
-	 *	   1 = Adj is used to decrease the PDL delay
-	 * [31:26] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
-	/* MCA NB Status Low reg */
-	PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
-	/* MCA NB Status high reg */
-	PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
-	/* MCA NB address Low reg */
-	PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
-	/* MCA NB address high reg */
-	PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
-	/* DRAM Scrub Control Register
-	 * F3:0x58
-	 * [ 4: 0] DRAM Scrube Rate
-	 * [ 7: 5] reserved
-	 * [12: 8] L2 Scrub Rate
-	 * [15:13] reserved
-	 * [20:16] Dcache Scrub
-	 * [31:21] reserved
-	 *	   Scrub Rates
-	 *	   00000 = Do not scrub
-	 *	   00001 =  40.00 ns
-	 *	   00010 =  80.00 ns
-	 *	   00011 = 160.00 ns
-	 *	   00100 = 320.00 ns
-	 *	   00101 = 640.00 ns
-	 *	   00110 =   1.28 us
-	 *	   00111 =   2.56 us
-	 *	   01000 =   5.12 us
-	 *	   01001 =  10.20 us
-	 *	   01011 =  41.00 us
-	 *	   01100 =  81.90 us
-	 *	   01101 = 163.80 us
-	 *	   01110 = 327.70 us
-	 *	   01111 = 655.40 us
-	 *	   10000 =   1.31 ms
-	 *	   10001 =   2.62 ms
-	 *	   10010 =   5.24 ms
-	 *	   10011 =  10.49 ms
-	 *	   10100 =  20.97 ms
-	 *	   10101 =  42.00 ms
-	 *	   10110 =  84.00 ms
-	 *	   All Others = Reserved
-	 */
-	PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
-	/* DRAM Scrub Address Low Register
-	 * F3:0x5C
-	 * [ 0: 0] DRAM Scrubber Redirect Enable
-	 *	   0 = Do nothing
-	 *	   1 = Scrubber Corrects errors found in normal operation
-	 * [ 5: 1] Reserved
-	 * [31: 6] DRAM Scrub Address 31-6
-	 */
-	PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
-	/* DRAM Scrub Address High Register
-	 * F3:0x60
-	 * [ 7: 0] DRAM Scrubb Address 39-32
-	 * [31: 8] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
-	};
-	int i;
-	int max;
-
-        if (!controller_present(ctrl)) {
-                printk(BIOS_DEBUG, "No memory controller present\r\n");
-                return;
-        }
-	printk(BIOS_SPEW, "setting up CPU 0x%x northbridge registers ", ctrl->node_id);
-	max = sizeof(register_values)/sizeof(register_values[0]);
-/*
-	for(i = 0; i < max; i += 3) {
-		struct device *dev;
-		unsigned where;
-		unsigned long reg;
-                printk(BIOS_DEBUG, "%08x <- %08x\r\n", register_values[i], register_values[i+2]);
-		dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
-		where = register_values[i] & 0xfff;
-		reg = pci_read_config32(dev, where);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-		pci_write_config32(dev, where, reg);
-	}
-*/
-	printk(BIOS_SPEW, "done.\r\n");
-}
-
-
-static void hw_enable_ecc(const struct mem_controller *ctrl)
-{
-	u32 dcl, nbcap;
-	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-	dcl &= ~DCL_DimmEccEn;
-	if (nbcap & NBCAP_ECC) {
-		dcl |= DCL_DimmEccEn;
-	}
-	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
-		dcl &= ~DCL_DimmEccEn;
-	}
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-	
-}
-
-static int is_dual_channel(const struct mem_controller *ctrl)
-{
-	u32 dcl;
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-	return dcl & DCL_128BitEn;
-}
-
-static int is_opteron(const struct mem_controller *ctrl)
-{
-	/* Test to see if I am an Opteron.  
-	 * FIXME Socket 939 based Athlon64 have dual channel capability,
-	 * too, so we need a better test for Opterons
-	 */
-#warning "FIXME: Implement a better test for Opterons"
-	u32 nbcap;
-	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
-	return !!(nbcap & NBCAP_128Bit);
-}
-
-static int is_registered(const struct mem_controller *ctrl)
-{
-	/* Test to see if we are dealing with registered SDRAM.
-	 * If we are not registered we are unbuffered.
-	 * This function must be called after spd_handle_unbuffered_dimms.
-	 */
-	u32 dcl;
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-	return !(dcl & DCL_UnBufDimm);
-}
-
-struct dimm_size {
-	unsigned long side1;
-	unsigned long side2;
-	unsigned long rows;
-	unsigned long col;
-#if QRANK_DIMM_SUPPORT == 1
-	unsigned long rank;
-#endif
-};
-
-static struct dimm_size spd_get_dimm_size(unsigned device)
-{
-	/* Calculate the log base 2 size of a DIMM in bits */
-	struct dimm_size sz;
-	int value, low;
-	sz.side1 = 0;
-	sz.side2 = 0;
-	sz.rows = 0;
-	sz.col = 0;
-#if QRANK_DIMM_SUPPORT == 1
-	sz.rank = 0;
-#endif
-
-	/* Note it might be easier to use byte 31 here, it has the DIMM size as
-	 * a multiple of 4MB.  The way we do it now we can size both
-	 * sides of an assymetric dimm.
-	 */
-	value = spd_read_byte(device, 3);	/* rows */
-	if (value < 0) goto hw_err;
-	if ((value & 0xf) == 0) goto val_err;
-	sz.side1 += value & 0xf;
-	sz.rows = value & 0xf;
-
-	value = spd_read_byte(device, 4);	/* columns */
-	if (value < 0) goto hw_err;
-	if ((value & 0xf) == 0) goto val_err;
-	sz.side1 += value & 0xf;
-	sz.col = value & 0xf;
-
-	value = spd_read_byte(device, 17);	/* banks */
-	if (value < 0) goto hw_err;
-	if ((value & 0xff) == 0) goto val_err;
-	sz.side1 += log2(value & 0xff);
-
-	/* Get the module data width and convert it to a power of two */
-	value = spd_read_byte(device, 7);	/* (high byte) */
-	if (value < 0) goto hw_err;
-	value &= 0xff;
-	value <<= 8;
-	
-	low = spd_read_byte(device, 6);	/* (low byte) */
-	if (low < 0) goto hw_err;
-	value = value | (low & 0xff);
-	if ((value != 72) && (value != 64)) goto val_err;
-	sz.side1 += log2(value);
-
-	/* side 2 */
-	value = spd_read_byte(device, 5);	/* number of physical banks */
-	if (value < 0) goto hw_err;
-	if (value == 1) goto out;
-	if ((value != 2) && (value != 4 )) {
-		goto val_err;
-	}
-#if QRANK_DIMM_SUPPORT == 1
-	sz.rank = value;
-#endif
-
-	/* Start with the symmetrical case */
-	sz.side2 = sz.side1;
-
-	value = spd_read_byte(device, 3);	/* rows */
-	if (value < 0) goto hw_err;
-	if ((value & 0xf0) == 0) goto out;	/* If symmetrical we are done */
-	sz.side2 -= (value & 0x0f);		/* Subtract out rows on side 1 */
-	sz.side2 += ((value >> 4) & 0x0f);	/* Add in rows on side 2 */
-
-	value = spd_read_byte(device, 4);	/* columns */
-	if (value < 0) goto hw_err;
-	if ((value & 0xff) == 0) goto val_err;
-	sz.side2 -= (value & 0x0f);		/* Subtract out columns on side 1 */
-	sz.side2 += ((value >> 4) & 0x0f);	/* Add in columsn on side 2 */
-
-	goto out;
-
- val_err:
-	die("Bad SPD value\r\n");
-	/* If an hw_error occurs report that I have no memory */
-hw_err:
-	sz.side1 = 0;
-	sz.side2 = 0;
-	sz.rows = 0;
-	sz.col = 0;
-#if QRANK_DIMM_SUPPORT == 1
-	sz.rank = 0;
-#endif
- out:
-	return sz;
-}
-
-
-static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
-{
-	u32 base0, base1;
-	u32 dch;
-
-	if (sz.side1 != sz.side2) {
-		sz.side2 = 0;
-	}
-	
-	/* For each base register.
-	 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
-	 * The initialize dimm size is in bits.
-	 * Set the base enable bit0.
-	 */
-	
-	base0 = base1 = 0;
-
-	/* Make certain side1 of the dimm is at least 32MB */
-	if (sz.side1 >= (25 +3)) {
-		base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1;
-	}
-	
-	/* Make certain side2 of the dimm is at least 32MB */
-	if (sz.side2 >= (25 + 3)) {
-		base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1;
-	}
-
-	/* Double the size if we are using dual channel memory */
-	if (is_dual_channel(ctrl)) {
-		base0 = (base0 << 1) | (base0 & 1);
-		base1 = (base1 << 1) | (base1 & 1);
-	}
-
-	/* Clear the reserved bits */
-	base0 &= ~0x001ffffe;
-	base1 &= ~0x001ffffe;
-
-	/* Set the appropriate DIMM base address register */
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
-#if QRANK_DIMM_SUPPORT == 1
-	if(sz.rank == 4) {
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
-	}
-#endif
-
-	/* Enable the memory clocks for this DIMM */
-	if (base0) {
-		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-		dch |= DCH_MEMCLK_EN0 << index;
-#if QRANK_DIMM_SUPPORT == 1
-		if(sz.rank == 4) {
-			dch |= DCH_MEMCLK_EN0 << (index + 2);
-		}
-#endif
-		pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
-	}
-}
-
-static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index)
-{
-	static const unsigned cs_map_aa[] = {
-		/* (row=12, col=8)(14, 12) ---> (0, 0) (2, 4) */
-		0, 1, 3, 6, 0,
-		0, 2, 4, 7, 9,
-		0, 0, 5, 8,10,
-	};
-
-	u32 map;
-	u32 dch;
-
-	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
-	map &= ~(0xf << (index * 4));
-#if QRANK_DIMM_SUPPORT == 1
-        if(sz.rank == 4) {
-                map &= ~(0xf << ( (index + 2) * 4));
-        }
-#endif
-
-
-	/* Make certain side1 of the dimm is at least 32MB */
-	if (sz.side1 >= (25 +3)) {
-		if(is_cpu_pre_d0()) {
-			map |= (sz.side1 - (25 + 3)) << (index *4);
-#if QRANK_DIMM_SUPPORT == 1
-	                if(sz.rank == 4) {
-         	              map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
-               		}
-#endif
-		}
-		else {
-			map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
-#if QRANK_DIMM_SUPPORT == 1
-		        if(sz.rank == 4) {
-                	       map |=  cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
-               		}
-#endif
-		}
-	}
-
-	pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
-	
-}
-
-static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
-{
-	int i;
-	
-	for(i = 0; i < DIMM_SOCKETS; i++) {
-		struct dimm_size sz;
-		if (!(dimm_mask & (1 << i))) {
-			continue;
-		}
-		sz = spd_get_dimm_size(ctrl->channel0[i]);
-		if (sz.side1 == 0) {
-			return -1; /* Report SPD error */
-		}
-		set_dimm_size(ctrl, sz, i);
-		set_dimm_map (ctrl, sz, i);
-	}
-	return dimm_mask;
-}
-
-static void route_dram_accesses(const struct mem_controller *ctrl,
-	unsigned long base_k, unsigned long limit_k)
-{
-	/* Route the addresses to the controller node */
-	unsigned node_id;
-	unsigned limit;
-	unsigned base;
-	unsigned index;
-	unsigned limit_reg, base_reg;
-	struct device *device;
-
-	node_id = ctrl->node_id;
-	index = (node_id << 3);
-	limit = (limit_k << 2);
-	limit &= 0xffff0000;
-	limit -= 0x00010000;
-	limit |= ( 0 << 8) | (node_id << 0);
-	base = (base_k << 2);
-	base &= 0xffff0000;
-	base |= (0 << 8) | (1<<1) | (1<<0);
-
-	limit_reg = 0x44 + index;
-	base_reg = 0x40 + index;
-	for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
-		pci_write_config32(device, limit_reg, limit);
-		pci_write_config32(device, base_reg, base);
-	}
-}
-
-static void set_top_mem(unsigned tom_k, unsigned hole_startk)
-{
-	/* Error if I don't have memory */
-	if (!tom_k) {
-		die("No memory?");
-	}
-
-	/* Report the amount of memory. */
-	print_spew("RAM: 0x");
-	print_spew_hex32(tom_k);
-	print_spew(" KB\r\n");
-
-	/* Now set top of memory */
-	msr_t msr;
-	if(tom_k > (4*1024*1024)) {
-		msr.lo = (tom_k & 0x003fffff) << 10;
-		msr.hi = (tom_k & 0xffc00000) >> 22;
-		wrmsr(TOP_MEM2, msr);
-	}
-
-	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
-	 * so I can see my rom chip and other I/O devices.
-	 */
-	if (tom_k >= 0x003f0000) {
-#if HW_MEM_HOLE_SIZEK != 0
-                if(hole_startk != 0) {
-                        tom_k = hole_startk;
-                } else
-#endif
-                tom_k = 0x3f0000;
-	}
-	msr.lo = (tom_k & 0x003fffff) << 10;
-	msr.hi = (tom_k & 0xffc00000) >> 22;
-	wrmsr(TOP_MEM, msr);
-}
-
-static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
-{
-	/* 35 - 25 */
-	static const u8 csbase_low_shift[] = { 
-	/* 32MB */	(13 - 4),
-	/* 64MB */	(14 - 4),
-	/* 128MB */	(14 - 4), 
-	/* 256MB */	(15 - 4),
-	/* 512MB */	(15 - 4),
-	/* 1GB */	(16 - 4),
-	/* 2GB */	(16 - 4), 
-	};
-
-        static const u8 csbase_low_d0_shift[] = {
-        /* 32MB */      (13 - 4),
-        /* 64MB */      (14 - 4),
-        /* 128MB */     (14 - 4),
-	/* 128MB */     (15 - 4),
-        /* 256MB */     (15 - 4),
-        /* 512MB */     (15 - 4),
-        /* 256MB */     (16 - 4),
-        /* 512MB */     (16 - 4),
-        /* 1GB */       (16 - 4),
-	/* 1GB */       (17 - 4),
-        /* 2GB */       (17 - 4),
-        };
-
-	/* cs_base_high is not changed */
-
-	u32 csbase_inc;
-	int chip_selects, index;
-	int bits;
-	unsigned common_size;
-	unsigned common_cs_mode;
-	u32 csbase, csmask;
-
-	/* See if all of the memory chip selects are the same size
-	 * and if so count them.
-	 */
-	chip_selects = 0;
-	common_size = 0;
-	common_cs_mode = 0;
-	for(index = 0; index < 8; index++) {
-		unsigned size;
-		unsigned cs_mode;
-		u32 value;
-		
-		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
-		
-		/* Is it enabled? */
-		if (!(value & 1)) {
-			continue;
-		}
-		chip_selects++;
-		size = value >> 21;
-		if (common_size == 0) {
-			common_size = size;
-		}
-		/* The size differed fail */
-		if (common_size != size) {
-			return 0;
-		}
-
-		value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
-                cs_mode =( value >> ((index>>1)*4)) & 0xf;
-                if(cs_mode == 0 ) continue;
-                if(common_cs_mode == 0) {
-                	common_cs_mode = cs_mode;
-                }
-                /* The size differed fail */
-                if(common_cs_mode != cs_mode) {
-                        return 0;
-                }
-	}
-
-	/* Chip selects can only be interleaved when there is
-	 * more than one and their is a power of two of them.
-	 */
-	bits = log2(chip_selects);
-	if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
-		return 0;
-	}
-
-	/* Find the bits of csbase that we need to interleave on */
-	if(is_cpu_pre_d0()){
-		csbase_inc = 1 << csbase_low_shift[common_cs_mode];
-		if(is_dual_channel(ctrl)) {
-                /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
-	                if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-//     		                printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\r\n");
-	                        return 0;
-                	}  
-			csbase_inc <<=1;
-		}
-	}
-	else {
-		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
-		if(is_dual_channel(ctrl)) {
-	                if( (bits==3) && (common_cs_mode > 8)) {
-//        	                printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\r\n");
-        	                return 0;
-			}
-			csbase_inc <<=1;
-                }   
-	}
-
-	/* Compute the initial values for csbase and csbask. 
-	 * In csbase just set the enable bit and the base to zero.
-	 * In csmask set the mask bits for the size and page level interleave.
-	 */
-	csbase = 0 | 1;
-	csmask = (((common_size  << bits) - 1) << 21);
-	csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc);
-	for(index = 0; index < 8; index++) {
-		u32 value;
-
-		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
-		/* Is it enabled? */
-		if (!(value & 1)) {
-			continue;
-		}
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
-		pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
-		csbase += csbase_inc;
-	}
-	
-	printk(BIOS_SPEW, "Interleaved\n");
-
-	/* Return the memory size in K */
-	return common_size << (15 + bits);
-}
-
-static unsigned long order_chip_selects(const struct mem_controller *ctrl)
-{
-	unsigned long tom;
-
-	/* Remember which registers we have used in the high 8 bits of tom */
-	tom = 0;
-	for(;;) {
-		/* Find the largest remaining canidate */
-		unsigned index, canidate;
-		u32 csbase, csmask;
-		unsigned size;
-		csbase = 0;
-		canidate = 0;
-		for(index = 0; index < 8; index++) {
-			u32 value;
-			value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
-
-			/* Is it enabled? */
-			if (!(value & 1)) {
-				continue;
-			}
-			
-			/* Is it greater? */
-			if (value <= csbase) {
-				continue;
-			}
-			
-			/* Has it already been selected */
-			if (tom & (1 << (index + 24))) {
-				continue;
-			}
-			/* I have a new canidate */
-			csbase = value;
-			canidate = index;
-		}
-		/* See if I have found a new canidate */
-		if (csbase == 0) {
-			break;
-		}
-
-		/* Remember the dimm size */
-		size = csbase >> 21;
-
-		/* Remember I have used this register */
-		tom |= (1 << (canidate + 24));
-
-		/* Recompute the cs base register value */
-		csbase = (tom << 21) | 1;
-
-		/* Increment the top of memory */
-		tom += size;
-
-		/* Compute the memory mask */
-		csmask = ((size -1) << 21);
-		csmask |= 0xfe00;		/* For now don't optimize */
-
-		/* Write the new base register */
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
-		/* Write the new mask register */
-		pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
-		
-	}
-	/* Return the memory size in K */
-	return (tom & ~0xff000000) << 15;
-}
-
-unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
-{
-	unsigned node_id;
-	unsigned end_k;
-	/* Find the last memory address used */
-	end_k = 0;
-	for(node_id = 0; node_id < max_node_id; node_id++) {
-		u32 limit, base;
-		unsigned index;
-		index = node_id << 3;
-		base = pci_read_config32(ctrl->f1, 0x40 + index);
-		/* Only look at the limit if the base is enabled */
-		if ((base & 3) == 3) {
-			limit = pci_read_config32(ctrl->f1, 0x44 + index);
-			end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
-		}
-	}
-	return end_k;
-}
-
-static void order_dimms(const struct mem_controller *ctrl)
-{
-	unsigned long tom_k, base_k;
-
-	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
-		tom_k = interleave_chip_selects(ctrl);
-	} else {
-		printk(BIOS_DEBUG, "Interleaving disabled\r\n");
-		tom_k = 0;
-	}
-	if (!tom_k) {
-		tom_k = order_chip_selects(ctrl);
-	}
-	/* Compute the memory base address */
-	base_k = memory_end_k(ctrl, ctrl->node_id);
-	tom_k += base_k;
-	route_dram_accesses(ctrl, base_k, tom_k);
-	set_top_mem(tom_k, 0);
-}
-
-static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
-{
-	printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index); 
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
-	dimm_mask &= ~(1 << index);
-	return dimm_mask;
-}
-
-static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask)
-{
-	int i;
-	int registered;
-	int unbuffered;
-	int has_dualch = is_opteron(ctrl);
-	u32 dcl;
-	unbuffered = 0;
-	registered = 0;
-	for(i = 0; (i < DIMM_SOCKETS); i++) {
-		int value;
-		if (!(dimm_mask & (1 << i))) {
-			continue;
-		}
-		value = spd_read_byte(ctrl->channel0[i], 21);
-		if (value < 0) {
-			return -1;
-		}
-		/* Registered dimm ? */
-		if (value & (1 << 1)) {
-			registered = 1;
-		} 
-		/* Otherwise it must be an unbuffered dimm */
-		else {
-			unbuffered = 1;
-		}
-	}
-	if (unbuffered && registered) {
-		die("Mixed buffered and registered dimms not supported");
-	}
-
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-	dcl &= ~DCL_UnBufDimm;
-	if (unbuffered) {
-		if ((has_dualch) && (!is_cpu_pre_d0())) {
-			dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
-			
-			/* set DCL_En2T if you have non-equal DDR mem types! */
-			
-			if ((cpuid_eax(1) & 0x30) == 0x30) {
-				/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
-				dcl |= DCL_UpperCSMap;
-			}
-		} else {
-			dcl |= DCL_UnBufDimm;
-		}
-	}
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-	if (is_registered(ctrl)) {
-		printk(BIOS_DEBUG, "Registered\r\n");
-	} else {
-		printk(BIOS_DEBUG, "Unbuffered\r\n");
-	}
-	return dimm_mask;
-}
-
-static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
-{
-	unsigned dimm_mask;
-	int i;
-	dimm_mask = 0;
-	for(i = 0; i < DIMM_SOCKETS; i++) {
-		int byte;
-		unsigned device;
-		device = ctrl->channel0[i];
-		if (device) {
-			byte = spd_read_byte(ctrl->channel0[i], 2);  /* Type */
-			if (byte == 7) {
-				dimm_mask |= (1 << i);
-			}
-		}
-		device = ctrl->channel1[i];
-		if (device) {
-			byte = spd_read_byte(ctrl->channel1[i], 2);
-			if (byte == 7) {
-				dimm_mask |= (1 << (i + DIMM_SOCKETS));
-			}
-		}
-	}
-	return dimm_mask;
-}
-
-static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask)
-{
-	int i;
-	u32 nbcap;
-	/* SPD addresses to verify are identical */
-	static const u8 addresses[] = {
-		2,	/* Type should be DDR SDRAM */
-		3,	/* *Row addresses */
-		4,	/* *Column addresses */
-		5,	/* *Physical Banks */
-		6,	/* *Module Data Width low */
-		7,	/* *Module Data Width high */
-		9,	/* *Cycle time at highest CAS Latency CL=X */
-		11,	/* *SDRAM Type */
-		13,	/* *SDRAM Width */
-		17,	/* *Logical Banks */
-		18,	/* *Supported CAS Latencies */
-		21,	/* *SDRAM Module Attributes */
-		23,	/* *Cycle time at CAS Latnecy (CLX - 0.5) */
-		26,	/* *Cycle time at CAS Latnecy (CLX - 1.0) */
-		27,	/* *tRP Row precharge time */
-		28,	/* *Minimum Row Active to Row Active Delay (tRRD) */
-		29,	/* *tRCD RAS to CAS */
-		30,	/* *tRAS Activate to Precharge */
-		41,	/* *Minimum Active to Active/Auto Refresh Time(Trc) */
-		42,	/* *Minimum Auto Refresh Command Time(Trfc) */
-	};
-	/* If the dimms are not in pairs do not do dual channels */
-	if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
-		((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { 
-		goto single_channel;
-	}
-	/* If the cpu is not capable of doing dual channels don't do dual channels */
-	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
-	if (!(nbcap & NBCAP_128Bit)) {
-		goto single_channel;
-	}
-	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
-		unsigned device0, device1;
-		int value0, value1;
-		int j;
-		/* If I don't have a dimm skip this one */
-		if (!(dimm_mask & (1 << i))) {
-			continue;
-		}
-		device0 = ctrl->channel0[i];
-		device1 = ctrl->channel1[i];
-		for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
-			unsigned addr;
-			addr = addresses[j];
-			value0 = spd_read_byte(device0, addr);
-			if (value0 < 0) {
-				return -1;
-			}
-			value1 = spd_read_byte(device1, addr);
-			if (value1 < 0) {
-				return -1;
-			}
-			if (value0 != value1) {
-				goto single_channel;
-			}
-		}
-	}
-	printk(BIOS_SPEW, "Enabling dual channel memory\r\n");
-	u32 dcl;
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-	dcl &= ~DCL_32ByteEn;
-	dcl |= DCL_128BitEn;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-	return dimm_mask;
- single_channel:
-	dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
-	return dimm_mask;
-}
-
-struct mem_param {
-	u8 cycle_time;
-	u8 divisor; /* In 1/2 ns increments */
-	u8 tRC;
-	u8 tRFC;
-	u32 dch_memclk;
-	u16 dch_tref4k, dch_tref8k;
-	u8	 dtl_twr;
-	u8	 dtl_twtr;
-	u8  dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */
- 	u8	 rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
-	char name[9];
-};
-
-static const struct mem_param *get_mem_param(unsigned min_cycle_time)
-{
-	static const struct mem_param speed[] = {
-		{
-			.name	    = "100Mhz\r\n",
-			.cycle_time = 0xa0,
-			.divisor    = (10 <<1),
-			.tRC	    = 0x46,
-			.tRFC	    = 0x50,
-			.dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
-			.dch_tref4k = DTH_TREF_100MHZ_4K,
-			.dch_tref8k = DTH_TREF_100MHZ_8K,
-			.dtl_twr    = 2,
-			.dtl_twtr   = 1,
-			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
-			.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
-		},
-		{
-			.name	    = "133Mhz\r\n",
-			.cycle_time = 0x75,
-			.divisor    = (7<<1)+1,
-			.tRC	    = 0x41,
-			.tRFC	    = 0x4B,
-			.dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
-			.dch_tref4k = DTH_TREF_133MHZ_4K,
-			.dch_tref8k = DTH_TREF_133MHZ_8K,
-			.dtl_twr    = 2,
-			.dtl_twtr   = 1,
-			.dtl_trwt   = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
-			.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
-		},
-		{
-			.name	    = "166Mhz\r\n",
-			.cycle_time = 0x60,
-			.divisor    = (6<<1),
-			.tRC	    = 0x3C,
-			.tRFC	    = 0x48,
-			.dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
-			.dch_tref4k = DTH_TREF_166MHZ_4K,
-			.dch_tref8k = DTH_TREF_166MHZ_8K,
-			.dtl_twr    = 3,
-			.dtl_twtr   = 1,
-			.dtl_trwt   = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }},
-			.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
-		},
-		{
-			.name	    = "200Mhz\r\n",
-			.cycle_time = 0x50,
-			.divisor    = (5<<1),
-			.tRC	    = 0x37,
-			.tRFC	    = 0x46,
-			.dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
-			.dch_tref4k = DTH_TREF_200MHZ_4K,
-			.dch_tref8k = DTH_TREF_200MHZ_8K,
-			.dtl_twr    = 3,
-			.dtl_twtr   = 2,
-			.dtl_trwt   = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }},
-			.rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) }
-		},
-		{
-			.cycle_time = 0x00,
-		},
-	};
-	const struct mem_param *param;
-	for(param = &speed[0]; param->cycle_time ; param++) {
-		if (min_cycle_time > (param+1)->cycle_time) {
-			break;
-		}
-	}
-	if (!param->cycle_time) {
-		die("min_cycle_time to low");
-	}
-	print_spew(param->name);
-#ifdef DRAM_MIN_CYCLE_TIME
-	printk(BIOS_DEBUG, param->name);
-#endif
-	return param;
-}
-
-struct spd_set_memclk_result {
-	const struct mem_param *param;
-	long dimm_mask;
-};
-static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask)
-{
-	/* Compute the minimum cycle time for these dimms */
-	struct spd_set_memclk_result result;
-	unsigned min_cycle_time, min_latency, bios_cycle_time;
-	int i;
-	u32 value;
-
-	static const u8 latency_indicies[] = { 26, 23, 9 };
-	static const unsigned char min_cycle_times[] = {
-		[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
-		[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
-		[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
-		[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
-	};
-
-	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
-
-	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
-	bios_cycle_time = min_cycle_times[
-		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
-	if (bios_cycle_time > min_cycle_time) {
-		min_cycle_time = bios_cycle_time;
-	}
-	min_latency = 2;
-
-	/* Compute the least latency with the fastest clock supported
-	 * by both the memory controller and the dimms.
-	 */
-	for(i = 0; i < DIMM_SOCKETS; i++) {
-		int new_cycle_time, new_latency;
-		int index;
-		int latencies;
-		int latency;
-
-		if (!(dimm_mask & (1 << i))) {
-			continue;
-		}
-
-		/* First find the supported CAS latencies
-		 * Byte 18 for DDR SDRAM is interpreted:
-		 * bit 0 == CAS Latency = 1.0
-		 * bit 1 == CAS Latency = 1.5
-		 * bit 2 == CAS Latency = 2.0
-		 * bit 3 == CAS Latency = 2.5
-		 * bit 4 == CAS Latency = 3.0
-		 * bit 5 == CAS Latency = 3.5
-		 * bit 6 == TBD
-		 * bit 7 == TBD
-		 */
-		new_cycle_time = 0xa0;
-		new_latency = 5;
-
-		latencies = spd_read_byte(ctrl->channel0[i], 18);
-		if (latencies <= 0) continue;
-
-		/* Compute the lowest cas latency supported */
-		latency = log2(latencies) -2;
-
-		/* Loop through and find a fast clock with a low latency */
-		for(index = 0; index < 3; index++, latency++) {
-			int value;
-			if ((latency < 2) || (latency > 4) ||
-				(!(latencies & (1 << latency)))) {
-				continue;
-			}
-			value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
-			if (value < 0) {
-				goto hw_error;
-			}
-
-			/* Only increase the latency if we decreas the clock */
-			if ((value >= min_cycle_time) && (value < new_cycle_time)) {
-				new_cycle_time = value;
-				new_latency = latency;
-			}
-		}
-		if (new_latency > 4){
-			continue;
-		}
-		/* Does min_latency need to be increased? */
-		if (new_cycle_time > min_cycle_time) {
-			min_cycle_time = new_cycle_time;
-		}
-		/* Does min_cycle_time need to be increased? */
-		if (new_latency > min_latency) {
-			min_latency = new_latency;
-		}
-	}
-	/* Make a second pass through the dimms and disable
-	 * any that cannot support the selected memclk and cas latency.
-	 */
-	
-	for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
-		int latencies;
-		int latency;
-		int index;
-		int value;
-		if (!(dimm_mask & (1 << i))) {
-			continue;
-		}
-		latencies = spd_read_byte(ctrl->channel0[i], 18);
-		if (latencies < 0) goto hw_error;
-		if (latencies == 0) {
-			goto dimm_err;
-		}
-
-		/* Compute the lowest cas latency supported */
-		latency = log2(latencies) -2;
-
-		/* Walk through searching for the selected latency */
-		for(index = 0; index < 3; index++, latency++) {
-			if (!(latencies & (1 << latency))) {
-				continue;
-			}
-			if (latency == min_latency)
-				break;
-		}
-		/* If I can't find the latency or my index is bad error */
-		if ((latency != min_latency) || (index >= 3)) {
-			goto dimm_err;
-		}
-		
-		/* Read the min_cycle_time for this latency */
-		value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
-		if (value < 0) goto hw_error;
-		
-		/* All is good if the selected clock speed 
-		 * is what I need or slower.
-		 */
-		if (value <= min_cycle_time) {
-			continue;
-		}
-		/* Otherwise I have an error, disable the dimm */
-	dimm_err:
-		dimm_mask = disable_dimm(ctrl, i, dimm_mask);
-	}
-#if 0
-//down speed for full load 4 rank support
-#if QRANK_DIMM_SUPPORT
-	if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
-		int ranks = 4;
-	        for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
-			int val;
-                	if (!(dimm_mask & (1 << i))) {
-                        	continue;
-	                }
-        	        val = spd_read_byte(ctrl->channel0[i], 5);
-			if(val!=ranks) {
-				ranks = val;
-				break;
-			}
-		}
-		if(ranks==4) {
-			if(min_cycle_time <= 0x50 ) {
-				min_cycle_time = 0x60;
-			}
-		}
-		
-	}
-#endif
-#endif
-	/* Now that I know the minimum cycle time lookup the memory parameters */
-	result.param = get_mem_param(min_cycle_time);
-
-	/* Update DRAM Config High with our selected memory speed */
-	value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-	value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
-#if 0
-	/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed 
-	 * result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 
-	 * and higher speeds with certain DIMM loadings ---- cheating???*/
-	if(!is_cpu_pre_e0()) {
-		if(min_cycle_time==0x50) {
-			value |= 1<<31;
-		}
-	}
-#endif
-
-	value |= result.param->dch_memclk;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
-
-	static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
-	/* Update DRAM Timing Low with our selected cas latency */
-	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
-	value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
-	
-	result.dimm_mask = dimm_mask;
-	return result;
- hw_error:
-	result.param = (const struct mem_param *)0;
-	result.dimm_mask = -1;
-	return result;
-}
-
-
-static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	unsigned clocks, old_clocks;
-	u32 dtl;
-	int value;
-	value = spd_read_byte(ctrl->channel0[i], 41);
-	if (value < 0) return -1;
-	if ((value == 0) || (value == 0xff)) {
-		value = param->tRC;
-	}
-	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
-	if (clocks < DTL_TRC_MIN) {
-		clocks = DTL_TRC_MIN;
-	}
-	if (clocks > DTL_TRC_MAX) {
-		return 0;
-	}
-
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
-	if (old_clocks > clocks) {
-		clocks = old_clocks;
-	}
-	dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
-	dtl |=	((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
-	return 1;
-}
-
-static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	unsigned clocks, old_clocks;
-	u32 dtl;
-	int value;
-	value = spd_read_byte(ctrl->channel0[i], 42);
-	if (value < 0) return -1;
-	if ((value == 0) || (value == 0xff)) {
-		value = param->tRFC;
-	}
-	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
-	if (clocks < DTL_TRFC_MIN) {
-		clocks = DTL_TRFC_MIN;
-	}
-	if (clocks > DTL_TRFC_MAX) {
-		return 0;
-	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
-	if (old_clocks > clocks) {
-		clocks = old_clocks;
-	}
-	dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
-	dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
-	return 1;
-}
-
-
-static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	unsigned clocks, old_clocks;
-	u32 dtl;
-	int value;
-	value = spd_read_byte(ctrl->channel0[i], 29);
-	if (value < 0) return -1;
-	clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
-	if (clocks < DTL_TRCD_MIN) {
-		clocks = DTL_TRCD_MIN;
-	}
-	if (clocks > DTL_TRCD_MAX) {
-		return 0;
-	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
-	if (old_clocks > clocks) {
-		clocks = old_clocks;
-	}
-	dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
-	dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
-	return 1;
-}
-
-static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	unsigned clocks, old_clocks;
-	u32 dtl;
-	int value;
-	value = spd_read_byte(ctrl->channel0[i], 28);
-	if (value < 0) return -1;
-	clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1);
-	if (clocks < DTL_TRRD_MIN) {
-		clocks = DTL_TRRD_MIN;
-	}
-	if (clocks > DTL_TRRD_MAX) {
-		return 0;
-	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
-	if (old_clocks > clocks) {
-		clocks = old_clocks;
-	}
-	dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
-	dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
-	return 1;
-}
-
-static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	unsigned clocks, old_clocks;
-	u32 dtl;
-	int value;
-	value = spd_read_byte(ctrl->channel0[i], 30);
-	if (value < 0) return -1;
-	clocks = ((value << 1) + param->divisor - 1)/param->divisor;
-	if (clocks < DTL_TRAS_MIN) {
-		clocks = DTL_TRAS_MIN;
-	}
-	if (clocks > DTL_TRAS_MAX) {
-		return 0;
-	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
-	if (old_clocks > clocks) {
-		clocks = old_clocks;
-	}
-	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
-	dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
-	return 1;
-}
-
-static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	unsigned clocks, old_clocks;
-	u32 dtl;
-	int value;
-	value = spd_read_byte(ctrl->channel0[i], 27);
-	if (value < 0) return -1;
-	clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
-	if (clocks < DTL_TRP_MIN) {
-		clocks = DTL_TRP_MIN;
-	}
-	if (clocks > DTL_TRP_MAX) {
-		return 0;
-	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
-	if (old_clocks > clocks) {
-		clocks = old_clocks;
-	}
-	dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
-	dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
-	return 1;
-}
-
-static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	u32 dtl;
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
-	dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
-}
-
-
-static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	u32 dth;
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
-	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
-	dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
-}
-
-static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	u32 dth;
-	int value;
-	unsigned tref, old_tref;
-	value = spd_read_byte(ctrl->channel0[i], 3);
-	if (value < 0) return -1;
-	value &= 0xf;
-
-	tref = param->dch_tref8k;
-	if (value == 12) {
-		tref = param->dch_tref4k;
-	}
-
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
-	old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
-	if ((value == 12) && (old_tref == param->dch_tref4k)) {
-		tref = param->dch_tref4k;
-	} else {
-		tref = param->dch_tref8k;
-	}
-	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
-	dth |= (tref << DTH_TREF_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
-	return 1;
-}
-
-
-static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	u32 dcl;
-	int value;
-#if QRANK_DIMM_SUPPORT == 1
-	int rank;
-#endif
-	int dimm;
-	value = spd_read_byte(ctrl->channel0[i], 13);
-	if (value < 0) {
-		return -1;
-	}
-
-#if QRANK_DIMM_SUPPORT == 1
-	rank = spd_read_byte(ctrl->channel0[i], 5);       /* number of physical banks */
-	if (rank < 0) {
-		return -1;	
-	}
-#endif
-
-	dimm = 1<<(DCL_x4DIMM_SHIFT+i);
-#if QRANK_DIMM_SUPPORT == 1
-	if(rank==4) {
-		dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
-	}
-#endif
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-	dcl &= ~dimm;
-	if (value == 4) {
-		dcl |= dimm;
-	}
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-	return 1;
-}
-
-static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-	u32 dcl;
-	int value;
-	value = spd_read_byte(ctrl->channel0[i], 11);
-	if (value < 0) {
-		return -1;
-	}
-	if (value != 2) {
-		dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
-		dcl &= ~DCL_DimmEccEn;
-		pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-	}
-	return 1;
-}
-
-static int count_dimms(const struct mem_controller *ctrl)
-{
-	int dimms;
-	unsigned index;
-	dimms = 0;
-	for(index = 0; index < 8; index += 2) {
-		u32 csbase;
-		csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2)));
-		if (csbase & 1) {
-			dimms += 1;
-		}
-	}
-	return dimms;
-}
-
-static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	u32 dth;
-
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
-	dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
-	dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
-}
-
-static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	u32 dth, dtl;
-	unsigned latency;
-	unsigned clocks;
-	int lat, mtype;
-
-	clocks = 0;
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
-	latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
-
-	if (is_opteron(ctrl)) {
-		mtype = 0; /* dual channel */
-	} else if (is_registered(ctrl)) {
-		mtype = 1; /* registered 64bit interface */
-	} else {
-		mtype = 2; /* unbuffered 64bit interface */
-	}
-
-	switch (latency) {
-		case DTL_CL_2:
-			lat = 0;
-			break;
-		case DTL_CL_2_5:
-			lat = 1;
-			break;
-		case DTL_CL_3:
-			lat = 2;
-			break;
-		default:
-			die("Unknown LAT for Trwt");
-	}
-
-	clocks = param->dtl_trwt[lat][mtype];
-	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
-		die("Unknown Trwt\r\n");
-	}
-	
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
-	dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
-	dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
-	return;
-}
-
-static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	/* Memory Clocks after CAS# */
-	u32 dth;
-	unsigned clocks;
-	if (is_registered(ctrl)) {
-		clocks = 2;
-	} else {
-		clocks = 1;
-	}
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
-	dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
-	dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
-}
-
-
-static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	u32 dch;
-	unsigned rdpreamble;
-	int slots, i;
-
-	slots = 0;
-
-	for(i = 0; i < 4; i++) {
-		if (ctrl->channel0[i]) {
-			slots += 1;
-		}
-	}
-
-	/* map to index to param.rdpreamble array */
-	if (is_registered(ctrl)) {
-		i = 0;
-	} else if (slots < 3) {
-		i = 1;
-	} else if (slots == 3) {
-		i = 2;
-	} else if (slots == 4) {
-		i = 3;
-	} else {
-		die("Unknown rdpreamble for this nr of slots");
-	}
-
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
-	rdpreamble = param->rdpreamble[i];
-
-	if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
-		die("Unknown rdpreamble");
-	}
-
-	dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
-}
-
-static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	u32 dch;
-	unsigned async_lat;
-	int dimms;
-
-	dimms = count_dimms(ctrl);
-
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-	dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
-	async_lat = 0;
-	if (is_registered(ctrl)) {
-		if (dimms == 4) {
-			/* 9ns */
-			async_lat = 9;
-		} 
-		else {
-			/* 8ns */
-			async_lat = 8;
-		}
-	}
-	else {
-		if (dimms > 3) {
-			die("Too many unbuffered dimms");
-		}
-		else if (dimms == 3) {
-			/* 7ns */
-			async_lat = 7;
-		}
-		else {
-			/* 6ns */
-			async_lat = 6;
-		}
-	}
-	dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
-}
-
-static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
-{
-	u32 dch;
-	/* AMD says to Hardcode this */
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
-	dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
-	dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
-	dch |= DCH_DYN_IDLE_CTR_EN;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
-}
-
-static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
-{
-	int i;
-	
-	init_Tref(ctrl, param);
-	for(i = 0; i < DIMM_SOCKETS; i++) {
-		int rc;
-		if (!(dimm_mask & (1 << i))) {
-			continue;
-		}
-		/* DRAM Timing Low Register */
-		if ((rc = update_dimm_Trc (ctrl, param, i)) <= 0) goto dimm_err;
-		if ((rc = update_dimm_Trfc(ctrl, param, i)) <= 0) goto dimm_err;
-		if ((rc = update_dimm_Trcd(ctrl, param, i)) <= 0) goto dimm_err;
-		if ((rc = update_dimm_Trrd(ctrl, param, i)) <= 0) goto dimm_err;
-		if ((rc = update_dimm_Tras(ctrl, param, i)) <= 0) goto dimm_err;
-		if ((rc = update_dimm_Trp (ctrl, param, i)) <= 0) goto dimm_err;
-
-		/* DRAM Timing High Register */
-		if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err;
-	
-
-		/* DRAM Config Low */
-		if ((rc = update_dimm_x4 (ctrl, param, i)) <= 0) goto dimm_err;
-		if ((rc = update_dimm_ecc(ctrl, param, i)) <= 0) goto dimm_err;
-		continue;
-	dimm_err:
-		if (rc < 0) {
-			return -1;
-		}
-		dimm_mask = disable_dimm(ctrl, i, dimm_mask);
-	}
-	/* DRAM Timing Low Register */
-	set_Twr(ctrl, param);
-
-	/* DRAM Timing High Register */
-	set_Twtr(ctrl, param);
-	set_Trwt(ctrl, param);
-	set_Twcl(ctrl, param);
-
-	/* DRAM Config High */
-	set_read_preamble(ctrl, param);
-	set_max_async_latency(ctrl, param);
-	set_idle_cycle_limit(ctrl, param);
-	return dimm_mask;
-}
-
-static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) 
-{
-	struct spd_set_memclk_result result;
-	const struct mem_param *param;
-	long dimm_mask;
-	if (!controller_present(ctrl)) {
-		printk(BIOS_DEBUG, "No memory controller present\r\n");
-		return;
-	}
-	hw_enable_ecc(ctrl);
-	activate_spd_rom(ctrl);
-	dimm_mask = spd_detect_dimms(ctrl);
-	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk(BIOS_DEBUG, "No memory for this cpu\r\n");
-		return;
-	}
-	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);        
-	if (dimm_mask < 0) 
-		goto hw_spd_err;
-	dimm_mask = spd_set_ram_size(ctrl , dimm_mask);           
-	if (dimm_mask < 0) 
-		goto hw_spd_err;
-	dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask); 
-	if (dimm_mask < 0) 
-		goto hw_spd_err;
-	result = spd_set_memclk(ctrl, dimm_mask);
-	param     = result.param;
-	dimm_mask = result.dimm_mask;
-	if (dimm_mask < 0) 
-		goto hw_spd_err;
-	dimm_mask = spd_set_dram_timing(ctrl, param , dimm_mask);
-	if (dimm_mask < 0)
-		goto hw_spd_err;
-	order_dimms(ctrl);
-	return;
- hw_spd_err:
-	/* Unrecoverable error reading SPD data */
-	print_err("SPD error - reset\r\n");
-	hard_reset();
-	return;
-}
-
-#if HW_MEM_HOLE_SIZEK != 0
-static u32 hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
-{
-        int ii;
-        u32 carry_over;
-        struct device *dev;
-        u32 base, limit;
-        u32 basek;
-        u32 hoist;
-        int j;
-
-        carry_over = (4*1024*1024) - hole_startk;
-
-        for(ii=controllers - 1;ii>i;ii--) {
-                base  = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
-                if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                        continue;
-                }
-		limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
-                for(j = 0; j < controllers; j++) {
-                        pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
-                        pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
-                }
-        }
-        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
-        for(j = 0; j < controllers; j++) {
-                pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
-        }
-        dev = ctrl[i].f1;
-        base  = pci_read_config32(dev, 0x40 + (i << 3));
-        basek  = (base & 0xffff0000) >> 2;
-        if(basek == hole_startk) {
-                //don't need set memhole here, because hole off set will be 0, overflow
-                //so need to change base reg instead, new basek will be 4*1024*1024
-                base &= 0x0000ffff;
-                base |= (4*1024*1024)<<2;
-                for(j = 0; j < controllers; j++) {
-                        pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
-                }
-        }
-	else {
-        	hoist = /* hole start address */
-                	((hole_startk << 10) & 0xff000000) +
-	                /* hole address to memory controller address */
-        	        (((basek + carry_over) >> 6) & 0x0000ff00) +
-                	/* enable */
-	                1;
-	        pci_write_config32(dev, 0xf0, hoist);
-	}
-
-        return carry_over;
-}
-
-static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
-{
-
-        u32 hole_startk;
-        int i;
-
-        hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
-
-#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 
-	/* We need to double check if hole_startk is valid.
-	 * If it is equal to the dram base address in K (base_k), 
-	 * we need to decrease it.
-	 */
-        u32 basek_pri;
-        for(i=0; i<controllers; i++) {
-                        u32 base;
-                        unsigned base_k;
-                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
-                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                                continue;
-                        }
-                        base_k = (base & 0xffff0000) >> 2;
-                        if(base_k == hole_startk) {
-				/* decrease memory hole startk to make sure it is
-				 * in the middle of the previous node 
-				 */
-                                hole_startk -= (base_k - basek_pri)>>1; 
-                                break; /* only one hole */
-                        }
-                        basek_pri = base_k;
-        }
-
-#endif
-        /* Find node number that needs the memory hole configured */
-        for(i=0; i<controllers; i++) {
-                        u32 base, limit;
-                        unsigned base_k, limit_k;
-                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
-                        if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-                                continue;
-                        }
-                        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
-                        base_k = (base & 0xffff0000) >> 2;
-                        limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
-			if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
-                                unsigned end_k;
-                                hoist_memory(controllers, ctrl, hole_startk, i);
-                                end_k = memory_end_k(ctrl, controllers);
-                                set_top_mem(end_k, hole_startk);
-                                break; /* only one hole */
-                        }
-        }
-
-}
-
-#endif
-
-#define TIMEOUT_LOOPS 300000
-static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
-{
-	int i;
-
-	/* Error if I don't have memory */
-	if (memory_end_k(ctrl, controllers) == 0) {
-		die("No memory\r\n");
-	}
-
-	/* Before enabling memory start the memory clocks */
-	for(i = 0; i < controllers; i++) {
-		u32 dch;
-		if (!controller_present(ctrl + i))
-			continue;
-		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
-		if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
-			dch |= DCH_MEMCLK_VALID;
-			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
-		}
-		else {
-			/* Disable dram receivers */
-			u32 dcl;
-			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
-			dcl |= DCL_DisInRcvrs;
-			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
-		}
-	}
-
-	/* And if necessary toggle the the reset on the dimms by hand */
-	memreset(controllers, ctrl);
-
-	/* We need to wait a mimmium of 20 MEMCLKS to enable the  InitDram */
-
-	for(i = 0; i < controllers; i++) {
-		u32 dcl, dch;
-		if (!controller_present(ctrl + i))
-			continue;
-		/* Skip everything if I don't have any memory on this controller */
-		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
-		if (!(dch & DCH_MEMCLK_VALID)) {
-			continue;
-		}
-
-		/* Toggle DisDqsHys to get it working */
-		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
-		if (dcl & DCL_DimmEccEn) {
-			u32 mnc;
-			print_spew("ECC enabled\r\n");
-			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
-			mnc |= MNC_ECC_EN;
-			if (dcl & DCL_128BitEn) {
-				mnc |= MNC_CHIPKILL_EN;
-			}
-			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
-		}
-		dcl |= DCL_DisDqsHys;
-		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
-		dcl &= ~DCL_DisDqsHys;
-		dcl &= ~DCL_DLL_Disable;
-		dcl &= ~DCL_D_DRV;
-		dcl &= ~DCL_QFC_EN;
-		dcl |= DCL_DramInit;
-		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
-
-	}
-	for(i = 0; i < controllers; i++) {
-		u32 dcl, dch;
-		if (!controller_present(ctrl + i))
-			continue;
-		/* Skip everything if I don't have any memory on this controller */
-		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
-		if (!(dch & DCH_MEMCLK_VALID)) {
-			continue;
-		}
-
-		printk(BIOS_DEBUG, "Initializing memory: ");
-
-		int loops = 0;
-		do {
-			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
-			loops += 1;
-			if ((loops & 1023) == 0) {
-				printk(BIOS_DEBUG, ".");
-			}
-		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
-		if (loops >= TIMEOUT_LOOPS) {
-			printk(BIOS_DEBUG, " failed\r\n");
-			continue;
-		}
-
-		if (!is_cpu_pre_c0()) {
-			/* Wait until it is safe to touch memory */
-			dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
-			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
-			do {
-				dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
-			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
-		}
-
-		printk(BIOS_DEBUG, " done\r\n");
-	}
-
-#if HW_MEM_HOLE_SIZEK != 0
-         // init hw mem hole here
-        /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
-	if(!is_cpu_pre_e0())
-	        set_hw_mem_hole(controllers, ctrl);
-#endif
-
-	//FIXME add enable node interleaving here -- yhlu
-	/*needed?
-		1. check how many nodes we have , if not all has ram installed get out
-		2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
-		3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out
-		4. if all ready enable node_interleaving in f1 0x40..... of every node
-		5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
-	*/
-
-}
-
-static void set_sysinfo_in_ram(unsigned val)
-{
-}
-
-static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const u16 *spd_addr)
-{
-        int i;
-        int j;
-        struct mem_controller *ctrl;
-        for(i=0;i<controllers; i++) {
-                ctrl = &ctrl_a[i];
-                ctrl->node_id = i;
-                ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
-                ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
-                ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
-                ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
-
-                if(spd_addr == (void *)0) continue;
-
-                for(j=0;j<DIMM_SOCKETS;j++) {
-                        ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
-                        ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
-                }
-        }
-}
-#endif
-




From rminnich at gmail.com  Sun Aug  3 21:37:53 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 12:37:53 -0700
Subject: [coreboot] last for the day
In-Reply-To: <20080803165649.GB6389@greenwood>
References: <13426df10808021420v7a25c6e7o483d03a22054b7b5@mail.gmail.com>
	<20080803165649.GB6389@greenwood>
Message-ID: <13426df10808031237m4f2317fo574b0e27329deea7@mail.gmail.com>

On Sun, Aug 3, 2008 at 9:56 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Sat, Aug 02, 2008 at 02:20:19PM -0700, ron minnich wrote:
>> @@ -871,12 +871,10 @@
>>       }
>>
>>       /* Report the amount of memory. */
>> -     print_spew("RAM: 0x");
>> -     print_spew_hex32(tom_k);
>> -     print_spew(" KB\r\n");
>> +     printk(BIOS_SPEW, "RAM: 0x%x DB\n", tom_k);
>
> DB -> KB
>
> Also, we partially use \n and partially \r\n in printk in v3, is there
> some reason for that? Shall we move everything to \n only?

Good catch, I fixed these as well.

Committed revision 715.

ron



From svn at coreboot.org  Sun Aug  3 21:39:36 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  3 Aug 2008 21:39:36 +0200
Subject: [coreboot] r716 - coreboot-v3/southbridge/nvidia/mcp55
Message-ID: <mailman.1772.1355071349.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-03 21:39:35 +0200 (Sun, 03 Aug 2008)
New Revision: 716

Modified:
   coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
   coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
   coreboot-v3/southbridge/nvidia/mcp55/stage1.c
Log:
Closer to compiling. Will be bringing in the rest of the functions for this part today. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c	2008-08-03 19:36:53 UTC (rev 715)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c	2008-08-03 19:39:35 UTC (rev 716)
@@ -21,32 +21,36 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <console/console.h>
+#include <console.h>
 
-#include <arch/io.h>
+#include <io.h>
 
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
 #include "mcp55.h"
 
-static uint32_t final_reg;
+static u32 final_reg;
 
-static device_t find_lpc_dev( device_t dev,  unsigned devfn)
+static struct device *find_lpc_dev( struct device *dev,  unsigned devfn)
 {
 
-	device_t lpc_dev;
+	struct device *lpc_dev;
 
 	lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
 
 	if ( !lpc_dev ) return lpc_dev;
-
-	if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
-		(lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
-		(lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
+	/* it had better be a PCI device */
+	if ( lpc_dev->id.type != DEVICE_ID_PCI)
+	  return lpc_dev;
+	/* the range makes it hard to use the library function. Sorry. 
+	 * I realize this is not pretty. It would be nice if we could 
+	 * use anonymous unions. 
+	 */
+	if ((lpc_dev->id.u.pci.vendor != PCI_VENDOR_ID_NVIDIA) || (
+		(lpc_dev->id.u.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
+		(lpc_dev->id.u.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
 		) ) {
-			uint32_t id;
+			u32 id;
 			id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
 			if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
 				(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
@@ -58,30 +62,31 @@
 	return lpc_dev;
 }
 
-static void mcp55_enable(device_t dev)
+static void mcp55_enable(struct device *dev)
 {
-	device_t lpc_dev = 0;
-	device_t sm_dev = 0;
+	struct device *lpc_dev = 0;
+	struct device *sm_dev = 0;
 	unsigned index = 0;
 	unsigned index2 = 0;
-	uint32_t reg_old, reg;
-	uint8_t byte;
+	u32 reg_old, reg;
+	u8 byte;
 	unsigned deviceid;
 	unsigned vendorid;
 
 	struct southbridge_nvidia_mcp55_config *conf;
-	conf = dev->chip_info;
+	conf = dev->device_configuration;
 	int i;
 
 	unsigned devfn;
 
-	if(dev->device==0x0000) {
+	/* sorry. Again, anonymous unions etc. would make this easier. */
+	if(dev->id.u.pci.device==0x0000) {
 		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
 		deviceid = (vendorid>>16) & 0xffff;
 //		vendorid &= 0xffff;
 	} else {
 //		vendorid = dev->vendor;
-		deviceid = dev->device;
+		deviceid = dev->id.u.pci.device;
 	}
 
 	devfn = (dev->path.u.pci.devfn) & ~7;
@@ -245,7 +250,7 @@
 struct device_operations nvidia_ops = {
 	.id = {.type = DEVICE_ID_PCI,
 		.u = {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
-			      .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIBRIDGE}}},
+			      .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}},
 	.constructor			= default_device_constructor,
 	.phase3_scan			= scan_static_bus,
 	.phase4_read_resources		= pci_dev_read_resources,

Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.h	2008-08-03 19:36:53 UTC (rev 715)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.h	2008-08-03 19:39:35 UTC (rev 716)
@@ -22,6 +22,6 @@
 #ifndef MCP55_H
 #define MCP55_H
 
-void mcp55_enable(device_t dev);
 
+
 #endif /* MCP55_H */

Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-08-03 19:36:53 UTC (rev 715)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-08-03 19:39:35 UTC (rev 716)
@@ -19,6 +19,17 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <console.h>
+#include <io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <amd/k8/k8.h>
+#include "mcp55.h"
+
+#warning fix disgusting define of MCP55_NUM it is mainboard dependent
+#define MCP55_NUM 1
 static int set_ht_link_mcp55(u8 ht_c_num)
 {
 	unsigned vendorid = 0x10de;
@@ -107,7 +118,7 @@
 	for(j = 0; j < mcp55_num; j++ ) {
 		setup_resource_map_offset(ctrl_devport_conf,
 			sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
-			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+			PCI_BDF(busn[j], devn[j], 0) , io_base[j]);
 	}
 }
 
@@ -124,7 +135,7 @@
 	for(j = 0; j < mcp55_num; j++ ) {
 		setup_resource_map_offset(ctrl_devport_conf_clear,
 			sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
-			PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+			PCI_BDF(busn[j], devn[j], 0) , io_base[j]);
 	}
 
 
@@ -144,8 +155,10 @@
 	u32 pll_ctrl;
 	u32 dword;
 	int i;
-	device_t dev;
-	dev = PCI_DEV(busnx, devnx+1, 1);
+	//struct device dev;
+	struct device *dev;
+#error dev is not set up
+	//	dev = PCI_BDF(busnx, devnx+1, 1);
 	dword = pci_read_config32(dev, 0xe4);
 	dword |= 0x3f0; // disable it at first
 	pci_write_config32(dev, 0xe4, dword);
@@ -328,23 +341,23 @@
 		mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
 
 		setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
 		for(i=0; i<3; i++) { // three SATA
 			setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
-				PCI_DEV(busn[j], devn[j], i), io_base[j]);
+				PCI_BDF(busn[j], devn[j], i), io_base[j]);
 		}
 		if(busn[j] == 0) {
 			setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
 		}
 
 		if( (busn[j] == 0) && (mcp55_num>1) ) {
 			setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
 		}
 
 		setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
-				PCI_DEV(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
 
 	}
 
@@ -395,8 +408,9 @@
 		busnx = ht_c_index * HT_CHAIN_BUSN_D;
 		for(devnx=0;devnx<0x20;devnx++) {
 			u32 id;
-			device_t dev;
-			dev = PCI_DEV(busnx, devnx, 0);
+			struct device *dev;
+#error dev is not set up
+			//			dev = PCI_BDF(busnx, devnx, 0);
 			id = pci_read_config32(dev, PCI_VENDOR_ID);
 			if(id == 0x036910de) {
 				busn[mcp55_num] = busnx;
@@ -410,7 +424,7 @@
 	}
 
 out:
-	print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n");
+	printk(BIOS_DEBUG, "mcp55_num: %d\n", mcp55_num);
 
 	mcp55_early_set_port(mcp55_num, busn, devn, io_base);
 	mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);




From rminnich at gmail.com  Sun Aug  3 21:40:20 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 12:40:20 -0700
Subject: [coreboot] v3 : mcp55.c patch
In-Reply-To: <20080803170313.GC6389@greenwood>
References: <13426df10808021404m6d627760gc22b5fba60eed28a@mail.gmail.com>
	<20080803170313.GC6389@greenwood>
Message-ID: <13426df10808031240w24d31645g79a6280d5fa6b118@mail.gmail.com>

On Sun, Aug 3, 2008 at 10:03 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Sat, Aug 02, 2008 at 02:04:51PM -0700, ron minnich wrote:
>> Index: southbridge/nvidia/mcp55/stage1.c
>> ===================================================================
>> --- southbridge/nvidia/mcp55/stage1.c (revision 713)
>> +++ southbridge/nvidia/mcp55/stage1.c (working copy)
>> @@ -19,6 +19,17 @@
>>   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>>   */
>>
>> +#include <console.h>
>> +#include <io.h>
>> +#include <device/device.h>
>> +#include <device/pci.h>
>
>
>> +#include <device/pci_ids.h>
>> +#include <device/pci_ops.h>
>
> These two are not needed, pci.h already includes them.

fixed.

>
>
>> -static uint32_t final_reg;
>> +static u32 final_reg;
>
> Is the static really needed or a romcc artifact?
>

not needed, but a good idea in general.

Committed revision 716.

ron



From uwe at hermann-uwe.de  Sun Aug  3 22:57:58 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 3 Aug 2008 22:57:58 +0200
Subject: [coreboot] [PATCH] Support for the ASI MB-5BLGP (Neoware
	Eon	4000s)
In-Reply-To: <20080710115531.GC23984@greenwood>
References: <20080710115531.GC23984@greenwood>
Message-ID: <20080803205758.GE6389@greenwood>

On Thu, Jul 10, 2008 at 01:55:31PM +0200, Uwe Hermann wrote:
> Hi,
> 
> here's a patch for the Neoware Eon 4000s thin client, based on the info
> from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html

*ping*

Can I get an Acked-by for this so we can commit a new board?
It's been tested to work on hardware with 'irqpoll', might need some
more investigations to fixup IRQs so it'll also work without 'irqpoll',
but this is definately committable IMHO.


> 
> 
> Thanks, Uwe.
> -- 
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

> Initia support for the ASI MB-5BLGP (Neoware Eon 4000s).
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
> 
> Index: src/mainboard/asi/mb_5blgp/Config.lb
> ===================================================================
> --- src/mainboard/asi/mb_5blgp/Config.lb	(Revision 0)
> +++ src/mainboard/asi/mb_5blgp/Config.lb	(Revision 0)
> @@ -0,0 +1,137 @@
> +##
> +## This file is part of the coreboot project.
> +##
> +## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +if USE_FALLBACK_IMAGE
> +	default ROM_SECTION_SIZE = FALLBACK_SIZE
> +	default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
> +else
> +	default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
> +	default ROM_SECTION_OFFSET = 0
> +end
> +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
> +				    + ROM_SECTION_OFFSET + 1)
> +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
> +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
> +default XIP_ROM_SIZE = 64 * 1024
> +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
> +arch i386 end
> +driver mainboard.o
> +if HAVE_PIRQ_TABLE
> +	object irq_tables.o
> +end
> +makerule ./failover.E
> +	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
> +	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
> +end
> +makerule ./failover.inc
> +	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
> +	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
> +end
> +makerule ./auto.E
> +	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
> +	depends	"$(MAINBOARD)/auto.c ./romcc"
> +	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
> +end
> +makerule ./auto.inc
> +	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
> +	depends "$(MAINBOARD)/auto.c ./romcc"
> +	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
> +end
> +mainboardinit cpu/x86/16bit/entry16.inc
> +mainboardinit cpu/x86/32bit/entry32.inc
> +ldscript /cpu/x86/16bit/entry16.lds
> +ldscript /cpu/x86/32bit/entry32.lds
> +if USE_FALLBACK_IMAGE
> +	mainboardinit cpu/x86/16bit/reset16.inc
> +	ldscript /cpu/x86/16bit/reset16.lds
> +else
> +	mainboardinit cpu/x86/32bit/reset32.inc
> +	ldscript /cpu/x86/32bit/reset32.lds
> +end
> +mainboardinit arch/i386/lib/cpu_reset.inc
> +mainboardinit arch/i386/lib/id.inc
> +ldscript /arch/i386/lib/id.lds
> +if USE_FALLBACK_IMAGE
> +	ldscript /arch/i386/lib/failover.lds
> +	mainboardinit ./failover.inc
> +end
> +mainboardinit cpu/x86/fpu/enable_fpu.inc
> +mainboardinit cpu/amd/model_gx1/cpu_setup.inc
> +mainboardinit cpu/amd/model_gx1/gx_setup.inc
> +mainboardinit ./auto.inc
> +
> +dir /pc80
> +config chip.h
> +
> +chip northbridge/amd/gx1		# Northbridge
> +  device pci_domain 0 on		# PCI domain
> +    device pci 0.0 on end		# Host bridge
> +    chip southbridge/amd/cs5530		# Southbridge
> +      device pci 0f.0 on end		# Ethernet
> +      device pci 12.0 on		# ISA bridge
> +        chip superio/nsc/pc87351	# Super I/O
> +          device pnp 2e.0 off		# Floppy
> +            io 0x60 = 0x3f0
> +            irq 0x70 = 6
> +            drq 0x74 = 2
> +          end
> +          device pnp 2e.1 on		# Parallel port
> +            io 0x60 = 0x378
> +            irq 0x70 = 7
> +          end
> +          device pnp 2e.2 on		# COM2
> +            io 0x60 = 0x2f8
> +            irq 0x70 = 3
> +          end
> +          device pnp 2e.e on		# COM1
> +            io 0x60 = 0x3f8
> +            irq 0x70 = 4
> +          end
> +          device pnp 2e.4 on		# System wake-up control (SWC)
> +            irq 0x60 = 0x500
> +          end
> +          device pnp 2e.5 on		# PS/2 mouse
> +            irq 0x70 = 12
> +          end
> +          device pnp 2e.6 on		# PS/2 keyboard
> +            io 0x60 = 0x60
> +            io 0x62 = 0x64
> +            irq 0x70 = 1
> +          end
> +          device pnp 2e.7 on		# GPIO
> +            irq 0x60 = 0x800
> +          end
> +          device pnp 2e.8 on		# Fan speed control
> +            irq 0x60 = 0x900
> +          end
> +        end
> +      end
> +      device pci 12.1 off end		# SMI
> +      device pci 12.2 on end		# IDE
> +      device pci 12.3 on end		# Audio
> +      device pci 12.4 on end		# VGA
> +      device pci 13.0 on end		# USB
> +      register "ide0_enable" = "1"
> +      register "ide1_enable" = "0"	# No connector on this board
> +    end
> +  end
> +  chip cpu/amd/model_gx1		# CPU
> +  end
> +end
> Index: src/mainboard/asi/mb_5blgp/irq_tables.c
> ===================================================================
> --- src/mainboard/asi/mb_5blgp/irq_tables.c	(Revision 0)
> +++ src/mainboard/asi/mb_5blgp/irq_tables.c	(Revision 0)
> @@ -0,0 +1,46 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <arch/pirq_routing.h>
> +
> +const struct irq_routing_table intel_irq_routing_table = {
> +	PIRQ_SIGNATURE,
> +	PIRQ_VERSION,
> +	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
> +	0x00,			/* Interrupt router bus */
> +	(0x12 << 3) | 0x0,	/* Interrupt router device */
> +	0x8800,			/* IRQs devoted exclusively to PCI usage */
> +	0x1078,			/* Vendor */
> +	0x2,			/* Device */
> +	0,			/* Crap (miniport) */
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
> +	0x96,			/* Checksum */
> +	{
> +		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
> +		{0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */
> +		{0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */
> +		{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */
> +	}
> +};
> +
> +unsigned long write_pirq_routing_table(unsigned long addr)
> +{
> +	return copy_pirq_routing_table(addr);
> +}
> Index: src/mainboard/asi/mb_5blgp/Options.lb
> ===================================================================
> --- src/mainboard/asi/mb_5blgp/Options.lb	(Revision 0)
> +++ src/mainboard/asi/mb_5blgp/Options.lb	(Revision 0)
> @@ -0,0 +1,105 @@
> +##
> +## This file is part of the coreboot project.
> +##
> +## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +uses HAVE_MP_TABLE
> +uses HAVE_PIRQ_TABLE
> +uses USE_FALLBACK_IMAGE
> +uses HAVE_FALLBACK_BOOT
> +uses HAVE_HARD_RESET
> +uses HAVE_OPTION_TABLE
> +uses USE_OPTION_TABLE
> +uses CONFIG_ROM_PAYLOAD
> +uses IRQ_SLOT_COUNT
> +uses MAINBOARD
> +uses MAINBOARD_VENDOR
> +uses MAINBOARD_PART_NUMBER
> +uses COREBOOT_EXTRA_VERSION
> +uses ARCH
> +uses FALLBACK_SIZE
> +uses STACK_SIZE
> +uses HEAP_SIZE
> +uses ROM_SIZE
> +uses ROM_SECTION_SIZE
> +uses ROM_IMAGE_SIZE
> +uses ROM_SECTION_SIZE
> +uses ROM_SECTION_OFFSET
> +uses CONFIG_ROM_PAYLOAD_START
> +uses PAYLOAD_SIZE
> +uses _ROMBASE
> +uses _RAMBASE
> +uses XIP_ROM_SIZE
> +uses XIP_ROM_BASE
> +uses CROSS_COMPILE
> +uses CC
> +uses HOSTCC
> +uses OBJCOPY
> +uses DEFAULT_CONSOLE_LOGLEVEL
> +uses MAXIMUM_CONSOLE_LOGLEVEL
> +uses CONFIG_CONSOLE_SERIAL8250
> +uses TTYS0_BAUD
> +uses TTYS0_BASE
> +uses TTYS0_LCS
> +uses CONFIG_COMPRESSED_PAYLOAD_LZMA
> +uses CONFIG_UDELAY_TSC
> +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
> +uses CONFIG_VIDEO_MB
> +uses CONFIG_SPLASH_GRAPHIC
> +uses CONFIG_GX1_VIDEO
> +uses CONFIG_GX1_VIDEOMODE
> +uses PIRQ_ROUTE
> +
> +## Enable VGA with a splash screen (only 640x480 to run on most monitors).
> +## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
> +## Note: Higher resolutions might need faster SDRAM speed.
> +default CONFIG_GX1_VIDEO = 1
> +default CONFIG_GX1_VIDEOMODE = 0
> +default CONFIG_SPLASH_GRAPHIC = 1
> +default CONFIG_VIDEO_MB = 2
> +
> +default ROM_SIZE = 256 * 1024
> +default HAVE_PIRQ_TABLE = 1
> +default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
> +default PIRQ_ROUTE = 1
> +default HAVE_FALLBACK_BOOT = 1
> +default HAVE_MP_TABLE = 0
> +default HAVE_HARD_RESET = 0
> +default CONFIG_UDELAY_TSC = 1
> +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
> +default HAVE_OPTION_TABLE = 0
> +default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
> +default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
> +default ROM_IMAGE_SIZE = 64 * 1024
> +default FALLBACK_SIZE = 128 * 1024
> +default STACK_SIZE = 8 * 1024
> +default HEAP_SIZE = 16 * 1024
> +default USE_OPTION_TABLE = 0
> +default _RAMBASE = 0x00004000
> +default CONFIG_ROM_PAYLOAD = 1
> +default CROSS_COMPILE = ""
> +default CC = "$(CROSS_COMPILE)gcc "
> +default HOSTCC = "gcc"
> +default CONFIG_CONSOLE_SERIAL8250 = 1
> +default TTYS0_BAUD = 115200
> +default TTYS0_BASE = 0x3f8
> +default TTYS0_LCS = 0x3		# 8n1
> +default DEFAULT_CONSOLE_LOGLEVEL = 9
> +default MAXIMUM_CONSOLE_LOGLEVEL = 9
> +
> +end
> Index: src/mainboard/asi/mb_5blgp/auto.c
> ===================================================================
> --- src/mainboard/asi/mb_5blgp/auto.c	(Revision 0)
> +++ src/mainboard/asi/mb_5blgp/auto.c	(Revision 0)
> @@ -0,0 +1,45 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#define ASSEMBLY 1
> +
> +#include <stdint.h>
> +#include <arch/io.h>
> +#include <device/pnp_def.h>
> +#include <arch/romcc_io.h>
> +#include <arch/hlt.h>
> +#include "pc80/serial.c"
> +#include "arch/i386/lib/console.c"
> +#include "ram/ramtest.c"
> +#include "northbridge/amd/gx1/raminit.c"
> +#include "cpu/x86/bist.h"
> +#include "superio/nsc/pc87351/pc87351_early_serial.c"
> +
> +#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
> +
> +static void main(unsigned long bist)
> +{
> +	pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
> +	uart_init();
> +	console_init();
> +	report_bist_failure(bist);
> +	sdram_init();
> +	/* ram_check(0, 640 * 1024); */
> +}
> Index: src/mainboard/asi/mb_5blgp/chip.h
> ===================================================================
> --- src/mainboard/asi/mb_5blgp/chip.h	(Revision 0)
> +++ src/mainboard/asi/mb_5blgp/chip.h	(Revision 0)
> @@ -0,0 +1,22 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +extern struct chip_operations mainboard_asi_mb_5blgp_ops;
> +struct mainboard_asi_mb_5blgp_config {};
> Index: src/mainboard/asi/mb_5blgp/mainboard.c
> ===================================================================
> --- src/mainboard/asi/mb_5blgp/mainboard.c	(Revision 0)
> +++ src/mainboard/asi/mb_5blgp/mainboard.c	(Revision 0)
> @@ -0,0 +1,26 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <device/device.h>
> +#include "chip.h"
> +
> +struct chip_operations mainboard_asi_mb_5blgp_ops = {
> +	CHIP_NAME("ASI MB-5BLGP Mainboard")
> +};
> Index: targets/asi/mb_5blgp/Config.lb
> ===================================================================
> --- targets/asi/mb_5blgp/Config.lb	(Revision 0)
> +++ targets/asi/mb_5blgp/Config.lb	(Revision 0)
> @@ -0,0 +1,54 @@
> +##
> +## This file is part of the coreboot project.
> +##
> +## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
> +
> +target mb_5blgp
> +mainboard asi/mb_5blgp
> +
> +option ROM_SIZE = 256 * 1024
> +
> +option MAINBOARD_VENDOR = "ASI"
> +option MAINBOARD_PART_NUMBER = "MB-5BLGP"
> +
> +option IRQ_SLOT_COUNT = 3
> +
> +## Enable VGA with a splash screen (only 640x480 to run on most monitors).
> +## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
> +## Note: Higher resolutions might need faster SDRAM speed.
> +option CONFIG_GX1_VIDEO = 1
> +option CONFIG_GX1_VIDEOMODE = 0
> +option CONFIG_SPLASH_GRAPHIC = 1
> +option CONFIG_VIDEO_MB = 2
> +
> +option DEFAULT_CONSOLE_LOGLEVEL = 9
> +option MAXIMUM_CONSOLE_LOGLEVEL = 9
> +
> +romimage "normal"
> +	option USE_FALLBACK_IMAGE = 0
> +	option COREBOOT_EXTRA_VERSION = ".0Normal"
> +	payload ../payload.elf
> +end
> +
> +romimage "fallback"
> +	option USE_FALLBACK_IMAGE = 1
> +	option COREBOOT_EXTRA_VERSION = ".0Fallback"
> +	payload ../payload.elf
> +end
> +
> +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

> -- 
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From c-d.hailfinger.devel.2006 at gmx.net  Sun Aug  3 23:00:33 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Aug 2008 23:00:33 +0200
Subject: [coreboot] [PATCH] v3: move to anonymous unions
Message-ID: <48961C71.5010604@gmx.net>

The named unions in the device tree code are obnoxious and degrade
readability. Move to anonymous unions.

Build tested on all targets. Boot tested on qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c
===================================================================
--- corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c	(Revision 716)
+++ corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c	(Arbeitskopie)
@@ -696,7 +696,7 @@
 
 struct device_operations cs5536_ops = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
 			      .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
 	.constructor			= default_device_constructor,
 	.phase3_scan			= scan_static_bus,
@@ -708,7 +708,7 @@
 
 struct device_operations cs5536_ide = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
 			      .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}},
 	.constructor		 = default_device_constructor,
 #warning FIXME: what has to go in phase3_scan?
Index: corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c	(Revision 716)
+++ corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c	(Arbeitskopie)
@@ -45,10 +45,11 @@
 	/* the range makes it hard to use the library function. Sorry. 
 	 * I realize this is not pretty. It would be nice if we could 
 	 * use anonymous unions. 
+	 * We now use anonymous unions. Fix up the code? 
 	 */
-	if ((lpc_dev->id.u.pci.vendor != PCI_VENDOR_ID_NVIDIA) || (
-		(lpc_dev->id.u.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
-		(lpc_dev->id.u.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
+	if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_NVIDIA) || (
+		(lpc_dev->id.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
+		(lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
 		) ) {
 			u32 id;
 			id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
@@ -80,16 +81,16 @@
 	unsigned devfn;
 
 	/* sorry. Again, anonymous unions etc. would make this easier. */
-	if(dev->id.u.pci.device==0x0000) {
+	if(dev->id.pci.device==0x0000) {
 		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
 		deviceid = (vendorid>>16) & 0xffff;
 //		vendorid &= 0xffff;
 	} else {
 //		vendorid = dev->vendor;
-		deviceid = dev->id.u.pci.device;
+		deviceid = dev->id.pci.device;
 	}
 
-	devfn = (dev->path.u.pci.devfn) & ~7;
+	devfn = (dev->path.pci.devfn) & ~7;
 	switch(deviceid) {
 		case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
 			return;
@@ -129,7 +130,7 @@
 		case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
 			devfn -= (4<<3);
 			index = 22;
-			i = (dev->path.u.pci.devfn) & 7;
+			i = (dev->path.pci.devfn) & 7;
 			if(i>0) {
 				index -= (i+3);
 			}
@@ -249,7 +250,7 @@
 
 struct device_operations nvidia_ops = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
+		{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
 			      .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}},
 	.constructor			= default_device_constructor,
 	.phase3_scan			= scan_static_bus,
Index: corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c	(Revision 716)
+++ corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c	(Arbeitskopie)
@@ -85,7 +85,7 @@
 /* You can override or extend each operation as needed for the device. */
 struct device_operations i82371eb_isa = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = 0x8086,.device = 0x7000}}},
+		{.pci = {.vendor = 0x8086,.device = 0x7000}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
 	.phase4_read_resources	 = pci_dev_read_resources,
@@ -98,7 +98,7 @@
 
 struct device_operations i82371eb_ide = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = 0x8086,.device = 0x7010}}},
+		{.pci = {.vendor = 0x8086,.device = 0x7010}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
 	.phase4_read_resources	 = pci_dev_read_resources,
@@ -111,7 +111,7 @@
 
 struct device_operations i82371eb_acpi = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = 0x8086,.device = 0x7113}}},
+		{.pci = {.vendor = 0x8086,.device = 0x7113}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
 	.phase4_read_resources	 = pci_dev_read_resources,
Index: corebootv3-anonymous_unions/include/device/path.h
===================================================================
--- corebootv3-anonymous_unions/include/device/path.h	(Revision 716)
+++ corebootv3-anonymous_unions/include/device/path.h	(Arbeitskopie)
@@ -100,7 +100,7 @@
 		struct cpu_path		cpu;
 		struct cpu_bus_path	cpu_bus;
 		struct ioport_path		ioport;
-	} u;
+	};
 };
 
 
Index: corebootv3-anonymous_unions/include/device/device.h
===================================================================
--- corebootv3-anonymous_unions/include/device/device.h	(Revision 716)
+++ corebootv3-anonymous_unions/include/device/device.h	(Arbeitskopie)
@@ -108,7 +108,7 @@
 		struct apic_cluster_id	apic_cluster;
 		struct cpu_id			cpu;
 		struct cpu_bus_id		cpu_bus;
-	} u;
+	};
 };
 
 
Index: corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c
===================================================================
--- corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c	(Revision 716)
+++ corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c	(Arbeitskopie)
@@ -36,13 +36,13 @@
 
 static void pnp_enter_ext_func_mode(struct device * dev) 
 {
-        outb(0x87, dev->path.u.pnp.port);
-        outb(0x87, dev->path.u.pnp.port);
+        outb(0x87, dev->path.pnp.port);
+        outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_ext_func_mode(struct device * dev) 
 {
-        outb(0xaa, dev->path.u.pnp.port);
+        outb(0xaa, dev->path.pnp.port);
 }
 
 static void pnp_write_index(u16 port_base, u8 reg, u8 value)
@@ -73,7 +73,7 @@
 #warning Fix CMOS handling
 	// get_option(&power_on, "power_on_after_fail");
 	pnp_enter_ext_func_mode(dev);
-	pnp_write_index(dev->path.u.pnp.port,7,0x0a); 
+	pnp_write_index(dev->path.pnp.port,7,0x0a); 
 	value = pnp_read_config(dev, 0xE4);
 	value &= ~(3<<5);
 	if(power_on) {
@@ -128,7 +128,7 @@
 	}
 
 	conf = dev->device_configuration;
-	switch(dev->path.u.pnp.device) {
+	switch(dev->path.pnp.device) {
 	case W83627HF_SP1: 
 		res0 = find_resource(dev, PNP_IDX_IO0);
 #warning init_uart8250
@@ -167,7 +167,7 @@
 {       
         pnp_enter_ext_func_mode(dev);  
 	pnp_enable_resources(dev);               
-        switch(dev->path.u.pnp.device) {
+        switch(dev->path.pnp.device) {
 	case W83627HF_HWM:
 		printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n");
 		enable_hwm_smbus(dev);
Index: corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c
===================================================================
--- corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c	(Revision 716)
+++ corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c	(Arbeitskopie)
@@ -41,12 +41,12 @@
 
 static void pnp_enter_conf_state(struct device *dev) 
 {
-	outb(0x87, dev->path.u.pnp.port);
+	outb(0x87, dev->path.pnp.port);
 }
 
 static void pnp_exit_conf_state(struct device *dev) 
 {
-	outb(0xaa, dev->path.u.pnp.port);
+	outb(0xaa, dev->path.pnp.port);
 }
 
 void f71805f_pnp_set_resources(struct device *dev)
@@ -79,7 +79,7 @@
 	if (!dev->enabled)
 		return;
 	
-	switch (dev->path.u.pnp.device) {
+	switch (dev->path.pnp.device) {
 	case F71805F_SP1: 
 		res0 = find_resource(dev, PNP_IDX_IO0);
 		//TODO: needed? fix or remove?
Index: corebootv3-anonymous_unions/superio/ite/it8716f/superio.c
===================================================================
--- corebootv3-anonymous_unions/superio/ite/it8716f/superio.c	(Revision 716)
+++ corebootv3-anonymous_unions/superio/ite/it8716f/superio.c	(Arbeitskopie)
@@ -37,14 +37,14 @@
 /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
 static void pnp_enter_ext_func_mode(struct device *dev)
 {
-	outb(0x87, dev->path.u.pnp.port);
-	outb(0x01, dev->path.u.pnp.port);
-	outb(0x55, dev->path.u.pnp.port);
+	outb(0x87, dev->path.pnp.port);
+	outb(0x01, dev->path.pnp.port);
+	outb(0x55, dev->path.pnp.port);
 
-	if (dev->path.u.pnp.port == 0x4e) {
-		outb(0xaa, dev->path.u.pnp.port);
+	if (dev->path.pnp.port == 0x4e) {
+		outb(0xaa, dev->path.pnp.port);
 	} else {
-		outb(0x55, dev->path.u.pnp.port);
+		outb(0x55, dev->path.pnp.port);
 	}
 }
 
@@ -142,7 +142,7 @@
 	conf = dev->device_configuration;
 
 	/* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */
-	switch (dev->path.u.pnp.device) {
+	switch (dev->path.pnp.device) {
 	case IT8716F_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
 //		init_uart8250(res0->base, &conf->com1);
Index: corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c
===================================================================
--- corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c	(Revision 716)
+++ corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c	(Arbeitskopie)
@@ -44,7 +44,7 @@
 
 struct device_operations qemuvga_pci_ops_dev = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
+		{.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
 			      .device = PCI_DEVICE_ID_CIRRUS_5446}}},
 	.constructor			= default_device_constructor,
 	.phase3_scan			= 0,
Index: corebootv3-anonymous_unions/device/pcie_device.c
===================================================================
--- corebootv3-anonymous_unions/device/pcie_device.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/pcie_device.c	(Arbeitskopie)
@@ -42,8 +42,8 @@
 	struct device *child;
 	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
 	for (child = bus->children; child; child = child->sibling) {
-		if ((child->path.u.pci.devfn < min_devfn) ||
-		    (child->path.u.pci.devfn > max_devfn)) {
+		if ((child->path.pci.devfn < min_devfn) ||
+		    (child->path.pci.devfn > max_devfn)) {
 			continue;
 		}
 		pcie_tune_dev(child);
Index: corebootv3-anonymous_unions/device/hypertransport.c
===================================================================
--- corebootv3-anonymous_unions/device/hypertransport.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/hypertransport.c	(Arbeitskopie)
@@ -50,7 +50,7 @@
 	 */
 	while (last && last->sibling &&
 	       (last->sibling->path.type == DEVICE_PATH_PCI) &&
-	       (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) {
+	       (last->sibling->path.pci.devfn > last->path.pci.devfn)) {
 		last = last->sibling;
 	}
 	if (first) {
@@ -344,7 +344,7 @@
 		u32 id;
 		dummy.bus = bus;
 		dummy.path.type = DEVICE_PATH_PCI;
-		dummy.path.u.pci.devfn = PCI_DEVFN(0, 0);
+		dummy.path.pci.devfn = PCI_DEVFN(0, 0);
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 		if (!((id == 0xffffffff) || (id == 0x00000000) ||
 		      (id == 0x0000ffff) || (id == 0xffff0000))) {
@@ -361,7 +361,7 @@
 		unsigned int pos, flags;
 		dummy.bus = bus;
 		dummy.path.type = DEVICE_PATH_PCI;
-		dummy.path.u.pci.devfn = devfn;
+		dummy.path.pci.devfn = devfn;
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 		if ((id == 0xffffffff) || (id == 0x00000000) ||
 		    (id == 0x0000ffff) || (id == 0xffff0000)) {
@@ -498,9 +498,9 @@
 		/* Update the unitid in the device structure. */
 		static_count = 1;
 		for (func = dev; func; func = func->sibling) {
-			func->path.u.pci.devfn += (next_unitid << 3);
-			static_count = (func->path.u.pci.devfn >> 3)
-			    - (dev->path.u.pci.devfn >> 3) + 1;
+			func->path.pci.devfn += (next_unitid << 3);
+			static_count = (func->path.pci.devfn >> 3)
+			    - (dev->path.pci.devfn >> 3) + 1;
 			last_func = func;
 		}
 
@@ -557,7 +557,7 @@
 				   flags);
 
 		for (func = real_last_dev; func; func = func->sibling) {
-			func->path.u.pci.devfn -=
+			func->path.pci.devfn -=
 			    ((real_last_unitid -
 			      HT_CHAIN_END_UNITID_BASE) << 3);
 			last_func = func;
Index: corebootv3-anonymous_unions/device/pnp_device.c
===================================================================
--- corebootv3-anonymous_unions/device/pnp_device.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/pnp_device.c	(Arbeitskopie)
@@ -32,19 +32,19 @@
 
 void pnp_write_config(struct device *dev, u8 reg, u8 value)
 {
-	outb(reg, dev->path.u.pnp.port);
-	outb(value, dev->path.u.pnp.port + 1);
+	outb(reg, dev->path.pnp.port);
+	outb(value, dev->path.pnp.port + 1);
 }
 
 u8 pnp_read_config(struct device *dev, u8 reg)
 {
-	outb(reg, dev->path.u.pnp.port);
-	return inb(dev->path.u.pnp.port + 1);
+	outb(reg, dev->path.pnp.port);
+	return inb(dev->path.pnp.port + 1);
 }
 
 void pnp_set_logical_device(struct device *dev)
 {
-	pnp_write_config(dev, 0x07, dev->path.u.pnp.device);
+	pnp_write_config(dev, 0x07, dev->path.pnp.device);
 }
 
 void pnp_set_enable(struct device *dev, int enable)
@@ -238,11 +238,11 @@
 	int i;
 
 	path.type = DEVICE_PATH_PNP;
-	path.u.pnp.port = base_dev->path.u.pnp.port;
+	path.pnp.port = base_dev->path.pnp.port;
 
 	/* Setup the ops and resources on the newly allocated devices. */
 	for (i = 0; i < functions; i++) {
-		path.u.pnp.device = info[i].function;
+		path.pnp.device = info[i].function;
 		dev = alloc_find_dev(base_dev->bus, &path, &id);
 
 		/* Don't initialize a device multiple times. */
Index: corebootv3-anonymous_unions/device/pcix_device.c
===================================================================
--- corebootv3-anonymous_unions/device/pcix_device.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/pcix_device.c	(Arbeitskopie)
@@ -66,8 +66,8 @@
 	struct device *child;
 	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
 	for (child = bus->children; child; child = child->sibling) {
-		if ((child->path.u.pci.devfn < min_devfn) ||
-		    (child->path.u.pci.devfn > max_devfn)) {
+		if ((child->path.pci.devfn < min_devfn) ||
+		    (child->path.pci.devfn > max_devfn)) {
 			continue;
 		}
 		pcix_tune_dev(child);
Index: corebootv3-anonymous_unions/device/agp_device.c
===================================================================
--- corebootv3-anonymous_unions/device/agp_device.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/agp_device.c	(Arbeitskopie)
@@ -40,8 +40,8 @@
 	struct device *child;
 	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
 	for (child = bus->children; child; child = child->sibling) {
-		if ((child->path.u.pci.devfn < min_devfn) ||
-		    (child->path.u.pci.devfn > max_devfn)) {
+		if ((child->path.pci.devfn < min_devfn) ||
+		    (child->path.pci.devfn > max_devfn)) {
 			continue;
 		}
 		agp_tune_dev(child);
Index: corebootv3-anonymous_unions/device/pci_rom.c
===================================================================
--- corebootv3-anonymous_unions/device/pci_rom.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/pci_rom.c	(Arbeitskopie)
@@ -45,8 +45,8 @@
 		 * or readonly.
 		 */
 		init_archive(&archive);
-		sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor,
-				dev->id.u.pci.device);
+		sprintf(pcifile, "pci%04x,%04x.rom", dev->id.pci.vendor,
+				dev->id.pci.device);
 
 		ret = find_file(&archive, pcifile, &result);
 		if (ret) {
@@ -108,7 +108,7 @@
 
 	printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n",
 	       rom_data->vendor, rom_data->device);
-	if (dev->id.u.pci.vendor != rom_data->vendor || dev->id.u.pci.device != rom_data->device) {
+	if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device != rom_data->device) {
 		printk(BIOS_ERR,
 		       "Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
 		       rom_data->vendor, rom_data->device);
Index: corebootv3-anonymous_unions/device/pci_device.c
===================================================================
--- corebootv3-anonymous_unions/device/pci_device.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/pci_device.c	(Arbeitskopie)
@@ -894,8 +894,8 @@
 			continue;
 		}
 		printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%02x\n",
-		       __func__, (*list)->dtsname, (*list)->path.u.pci.devfn);
-		if ((*list)->path.u.pci.devfn == devfn) {
+		       __func__, (*list)->dtsname, (*list)->path.pci.devfn);
+		if ((*list)->path.pci.devfn == devfn) {
 			/* Unlink from the list. */
 			dev = *list;
 			*list = (*list)->sibling;
@@ -948,7 +948,7 @@
 		struct device_id devid;
 		dummy.bus = bus;
 		dummy.path.type = DEVICE_PATH_PCI;
-		dummy.path.u.pci.devfn = devfn;
+		dummy.path.pci.devfn = devfn;
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 		/* Have we found something?
 		 * Some broken boards return 0 if a slot is empty.
@@ -960,8 +960,8 @@
 			return NULL;
 		}
 		devid.type = DEVICE_ID_PCI;
-		devid.u.pci.vendor = id & 0xffff;
-		devid.u.pci.device = id >> 16;
+		devid.pci.vendor = id & 0xffff;
+		devid.pci.device = id >> 16;
 		dev = alloc_dev(bus, &dummy.path, &devid);
 	} else {
 		/* Enable/disable the device. Once we have found the device
@@ -1013,8 +1013,8 @@
 
 	/* Store the interesting information in the device structure. */
 	dev->id.type = DEVICE_ID_PCI;
-	dev->id.u.pci.vendor = id & 0xffff;
-	dev->id.u.pci.device = (id >> 16) & 0xffff;
+	dev->id.pci.vendor = id & 0xffff;
+	dev->id.pci.device = (id >> 16) & 0xffff;
 	dev->hdr_type = hdr_type;
 	/* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
 	dev->class = class >> 8;
Index: corebootv3-anonymous_unions/device/device_util.c
===================================================================
--- corebootv3-anonymous_unions/device/device_util.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/device_util.c	(Arbeitskopie)
@@ -81,7 +81,7 @@
 	for (dev = all_devices; dev; dev = dev->next) {
 		if ((dev->path.type == DEVICE_PATH_PCI) &&
 		    (dev->bus->secondary == bus) &&
-		    (dev->path.u.pci.devfn == devfn)) {
+		    (dev->path.pci.devfn == devfn)) {
 			result = dev;
 			break;
 		}
@@ -104,7 +104,7 @@
 	for (dev = all_devices; dev; dev = dev->next) {
 		if ((dev->path.type == DEVICE_PATH_I2C) &&
 		    (dev->bus->secondary == bus) &&
-		    (dev->path.u.i2c.device == addr)) {
+		    (dev->path.i2c.device == addr)) {
 			result = dev;
 			break;
 		}
@@ -155,8 +155,8 @@
 	struct device_id id;
 
 	id.type = DEVICE_ID_PCI;
-	id.u.pci.vendor = vendor;
-	id.u.pci.device = device;
+	id.pci.vendor = vendor;
+	id.pci.device = device;
 	return dev_find_device(&id, from);
 }
 
@@ -197,48 +197,48 @@
 			sprintf(buffer, "PCI: %04x:%02x:%02x.%01x",
 				dev->bus->secondary >> 8,
 				dev->bus->secondary & 0xff,
-				PCI_SLOT(dev->path.u.pci.devfn),
-				PCI_FUNC(dev->path.u.pci.devfn));
+				PCI_SLOT(dev->path.pci.devfn),
+				PCI_FUNC(dev->path.pci.devfn));
 #else
 			sprintf(buffer, "PCI: %02x:%02x.%01x",
 				dev->bus->secondary,
-				PCI_SLOT(dev->path.u.pci.devfn),
-				PCI_FUNC(dev->path.u.pci.devfn));
+				PCI_SLOT(dev->path.pci.devfn),
+				PCI_FUNC(dev->path.pci.devfn));
 #endif
 			break;
 		case DEVICE_PATH_PNP:
 			sprintf(buffer, "PNP: %04x.%01x",
-				dev->path.u.pnp.port, dev->path.u.pnp.device);
+				dev->path.pnp.port, dev->path.pnp.device);
 			break;
 		case DEVICE_PATH_I2C:
 			sprintf(buffer, "I2C: %02x:%02x",
-				dev->bus->secondary, dev->path.u.i2c.device);
+				dev->bus->secondary, dev->path.i2c.device);
 			break;
 		case DEVICE_PATH_APIC:
-			sprintf(buffer, "APIC: %02x", dev->path.u.apic.apic_id);
+			sprintf(buffer, "APIC: %02x", dev->path.apic.apic_id);
 			break;
 		case DEVICE_PATH_PCI_DOMAIN:
 			sprintf(buffer, "PCI_DOMAIN: %04x",
-				dev->path.u.pci_domain.domain);
+				dev->path.pci_domain.domain);
 			break;
 		case DEVICE_PATH_PCI_BUS:
 			sprintf(buffer, "PCI_BUS: %04x",
-				dev->path.u.pci_bus.bus);
+				dev->path.pci_bus.bus);
 			break;
 		case DEVICE_PATH_APIC_CLUSTER:
 			sprintf(buffer, "APIC_CLUSTER: %01x",
-				dev->path.u.apic_cluster.cluster);
+				dev->path.apic_cluster.cluster);
 			break;
 		case DEVICE_PATH_CPU:
-			sprintf(buffer, "CPU: %02x", dev->path.u.cpu.id);
+			sprintf(buffer, "CPU: %02x", dev->path.cpu.id);
 			break;
 		case DEVICE_PATH_CPU_BUS:
 			sprintf(buffer, "CPU_BUS: %02x",
-				dev->path.u.cpu_bus.id);
+				dev->path.cpu_bus.id);
 			break;
 		case DEVICE_PATH_IOPORT:
 			sprintf(buffer, "IOPORT: %02x",
-				dev->path.u.ioport.iobase);
+				dev->path.ioport.iobase);
 			break;
 		default:
 			printk(BIOS_ERR, "%s: Unknown device path type: %d\n",
@@ -262,36 +262,36 @@
 			memcpy(buffer, "Root Device", 12);
 			break;
 		case DEVICE_ID_PCI:
-			sprintf(buffer, "PCI: %04x:%04x", id->u.pci.vendor,
-				id->u.pci.device);
+			sprintf(buffer, "PCI: %04x:%04x", id->pci.vendor,
+				id->pci.device);
 			break;
 		case DEVICE_ID_PNP:
-			sprintf(buffer, "PNP: %04x", id->u.pnp.device);
+			sprintf(buffer, "PNP: %04x", id->pnp.device);
 			break;
 		case DEVICE_ID_I2C:
-			sprintf(buffer, "I2C: %04x", id->u.i2c.id);
+			sprintf(buffer, "I2C: %04x", id->i2c.id);
 			break;
 		case DEVICE_ID_APIC:
-			sprintf(buffer, "APIC: %02x:%02x", id->u.apic.vendor,
-				id->u.apic.device);
+			sprintf(buffer, "APIC: %02x:%02x", id->apic.vendor,
+				id->apic.device);
 			break;
 		case DEVICE_ID_PCI_DOMAIN:
 			sprintf(buffer, "PCI_DOMAIN: %04x:%04x",
-				id->u.pci_domain.vendor,
-				id->u.pci_domain.device);
+				id->pci_domain.vendor,
+				id->pci_domain.device);
 			break;
 		case DEVICE_ID_APIC_CLUSTER:
 			sprintf(buffer, "APIC_CLUSTER: %02x:%02x",
-				id->u.apic_cluster.vendor,
-				id->u.apic_cluster.device);
+				id->apic_cluster.vendor,
+				id->apic_cluster.device);
 			break;
 		case DEVICE_ID_CPU:
-			sprintf(buffer, "CPU", id->u.cpu.cpuid[0],
-				id->u.cpu.cpuid[1], id->u.cpu.cpuid[2]);
+			sprintf(buffer, "CPU", id->cpu.cpuid[0],
+				id->cpu.cpuid[1], id->cpu.cpuid[2]);
 			break;
 		case DEVICE_ID_CPU_BUS:
 			sprintf(buffer, "CPU_BUS: %02x:%02x",
-				id->u.cpu_bus.vendor, id->u.cpu_bus.device);
+				id->cpu_bus.vendor, id->cpu_bus.device);
 			break;
 		default:
 			printk(BIOS_ERR, "%s: Unknown device ID type: %d\n",
@@ -321,34 +321,34 @@
 			equal = 1;
 			break;
 		case DEVICE_PATH_PCI:
-			equal = (path1->u.pci.devfn == path2->u.pci.devfn);
+			equal = (path1->pci.devfn == path2->pci.devfn);
 			break;
 		case DEVICE_PATH_PNP:
-			equal = (path1->u.pnp.port == path2->u.pnp.port) &&
-			    (path1->u.pnp.device == path2->u.pnp.device);
+			equal = (path1->pnp.port == path2->pnp.port) &&
+			    (path1->pnp.device == path2->pnp.device);
 			break;
 		case DEVICE_PATH_I2C:
-			equal = (path1->u.i2c.device == path2->u.i2c.device);
+			equal = (path1->i2c.device == path2->i2c.device);
 			break;
 		case DEVICE_PATH_APIC:
 			equal =
-			    (path1->u.apic.apic_id == path2->u.apic.apic_id);
+			    (path1->apic.apic_id == path2->apic.apic_id);
 			break;
 		case DEVICE_PATH_PCI_DOMAIN:
 			equal =
-			    (path1->u.pci_domain.domain ==
-			     path2->u.pci_domain.domain);
+			    (path1->pci_domain.domain ==
+			     path2->pci_domain.domain);
 			break;
 		case DEVICE_PATH_APIC_CLUSTER:
 			equal =
-			    (path1->u.apic_cluster.cluster ==
-			     path2->u.apic_cluster.cluster);
+			    (path1->apic_cluster.cluster ==
+			     path2->apic_cluster.cluster);
 			break;
 		case DEVICE_PATH_CPU:
-			equal = (path1->u.cpu.id == path2->u.cpu.id);
+			equal = (path1->cpu.id == path2->cpu.id);
 			break;
 		case DEVICE_PATH_CPU_BUS:
-			equal = (path1->u.cpu_bus.id == path2->u.cpu_bus.id);
+			equal = (path1->cpu_bus.id == path2->cpu_bus.id);
 			break;
 		default:
 			printk(BIOS_ERR, "Unknown device type: %d\n",
@@ -370,41 +370,41 @@
 			equal = 1;
 			break;
 		case DEVICE_ID_PCI:
-			equal = (path1->u.pci.vendor == path2->u.pci.vendor)
-			    && (path1->u.pci.device == path2->u.pci.device);
+			equal = (path1->pci.vendor == path2->pci.vendor)
+			    && (path1->pci.device == path2->pci.device);
 			break;
 		case DEVICE_ID_PNP:
-			equal = (path1->u.pnp.device == path2->u.pnp.device);
+			equal = (path1->pnp.device == path2->pnp.device);
 			break;
 		case DEVICE_ID_I2C:
-			equal = (path1->u.i2c.id == path2->u.i2c.id);
+			equal = (path1->i2c.id == path2->i2c.id);
 			break;
 		case DEVICE_ID_APIC:
-			equal = (path1->u.apic.vendor == path2->u.apic.vendor)
-			    && (path1->u.apic.device == path2->u.apic.device);
+			equal = (path1->apic.vendor == path2->apic.vendor)
+			    && (path1->apic.device == path2->apic.device);
 			break;
 		case DEVICE_ID_PCI_DOMAIN:
 			equal =
-			    (path1->u.pci_domain.vendor ==
-			     path2->u.pci_domain.vendor)
-			    && (path1->u.pci_domain.device ==
-				path2->u.pci_domain.device);
+			    (path1->pci_domain.vendor ==
+			     path2->pci_domain.vendor)
+			    && (path1->pci_domain.device ==
+				path2->pci_domain.device);
 			break;
 		case DEVICE_ID_APIC_CLUSTER:
 			equal =
-			    (path1->u.apic_cluster.vendor ==
-			     path2->u.apic_cluster.vendor)
-			    && (path1->u.apic_cluster.device ==
-				path2->u.apic_cluster.device);
+			    (path1->apic_cluster.vendor ==
+			     path2->apic_cluster.vendor)
+			    && (path1->apic_cluster.device ==
+				path2->apic_cluster.device);
 			break;
 		case DEVICE_ID_CPU:
-			equal = (path1->u.cpu.cpuid == path2->u.cpu.cpuid);
+			equal = (path1->cpu.cpuid == path2->cpu.cpuid);
 			break;
 		case DEVICE_ID_CPU_BUS:
 			equal =
-			    (path1->u.cpu_bus.vendor == path2->u.cpu_bus.vendor)
-			    && (path1->u.cpu_bus.device ==
-				path2->u.cpu_bus.device);
+			    (path1->cpu_bus.vendor == path2->cpu_bus.vendor)
+			    && (path1->cpu_bus.device ==
+				path2->cpu_bus.device);
 			break;
 		default:
 			printk(BIOS_ERR, "Unknown device type: %d\n",
Index: corebootv3-anonymous_unions/device/pci_ops.c
===================================================================
--- corebootv3-anonymous_unions/device/pci_ops.c	(Revision 716)
+++ corebootv3-anonymous_unions/device/pci_ops.c	(Arbeitskopie)
@@ -50,40 +50,40 @@
 {
 	struct bus *pbus = get_pbus(dev);
 	return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary,
-					dev->path.u.pci.devfn, where);
+					dev->path.pci.devfn, where);
 }
 
 u16 pci_read_config16(struct device *dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
 	return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary,
-					 dev->path.u.pci.devfn, where);
+					 dev->path.pci.devfn, where);
 }
 
 u32 pci_read_config32(struct device *dev, unsigned int where)
 {
 	struct bus *pbus = get_pbus(dev);
 	return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary,
-					 dev->path.u.pci.devfn, where);
+					 dev->path.pci.devfn, where);
 }
 
 void pci_write_config8(struct device *dev, unsigned int where, u8 val)
 {
 	struct bus *pbus = get_pbus(dev);
 	ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary,
-				  dev->path.u.pci.devfn, where, val);
+				  dev->path.pci.devfn, where, val);
 }
 
 void pci_write_config16(struct device *dev, unsigned int where, u16 val)
 {
 	struct bus *pbus = get_pbus(dev);
 	ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary,
-				   dev->path.u.pci.devfn, where, val);
+				   dev->path.pci.devfn, where, val);
 }
 
 void pci_write_config32(struct device *dev, unsigned int where, u32 val)
 {
 	struct bus *pbus = get_pbus(dev);
 	ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary,
-				   dev->path.u.pci.devfn, where, val);
+				   dev->path.pci.devfn, where, val);
 }
Index: corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c
===================================================================
--- corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c	(Revision 716)
+++ corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c	(Arbeitskopie)
@@ -224,7 +224,7 @@
 /** Operations for when the northbridge is running a PCI domain. */
 struct device_operations geodelx_north_domain = {
 	.id = {.type = DEVICE_ID_PCI_DOMAIN,
-		.u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
+		{.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
 				     .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
 	.constructor			= default_device_constructor,
 	.phase2_setup_scan_bus		= geodelx_pci_domain_phase2,
@@ -239,7 +239,7 @@
 /** Operations for when the northbridge is running an APIC cluster. */
 struct device_operations geodelx_north_apic = {
 	.id = {.type = DEVICE_ID_APIC_CLUSTER,
-		.u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,
+		{.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,
 				       .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
 	.constructor			= default_device_constructor,
 	.phase3_scan			= 0,
@@ -257,7 +257,7 @@
  */
 struct device_operations geodelx_north_pci = {
 	.id = {.type = DEVICE_ID_PCI,
-		.u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
 			      .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
 	.constructor			= default_device_constructor,
 	.phase3_scan			= 0,
Index: corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c	(Revision 716)
+++ corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c	(Arbeitskopie)
@@ -68,7 +68,7 @@
 /* See mainboard/emulation/qemu-x86 for an example of how these are used. */
 struct device_operations i440bx_domain = {
 	.id = {.type = DEVICE_ID_PCI_DOMAIN,
-		.u = {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
+		{.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = pci_domain_scan_bus,
 	.phase4_read_resources	 = pci_domain_read_resources,
Index: corebootv3-anonymous_unions/util/dtc/flattree.c
===================================================================
--- corebootv3-anonymous_unions/util/dtc/flattree.c	(Revision 716)
+++ corebootv3-anonymous_unions/util/dtc/flattree.c	(Arbeitskopie)
@@ -551,19 +551,19 @@
 	if (path && path[1]) {
 		path++;
 		if (!strncmp(tree->name, "cpu", 3)){
-			fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={ .id = 0x%s }}},\n", 
+			fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,{.cpu={ .id = 0x%s }}},\n", 
 				path);
 		}
 		if (!strncmp(tree->name, "bus", 3)){
-			fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = 0x%s }}},\n", 
+			fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,{.pci_bus={ .bus = 0x%s }}},\n", 
 				path);
 		}
 		if (!strncmp(tree->name, "apic", 4)){
-			fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,.u={.apic={ 0x%s }}},\n", 
+			fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,{.apic={ 0x%s }}},\n", 
 				path);
 		}
 		if (!strncmp(tree->name, "domain", 6)){
-			fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0x%s }}},\n", 
+			fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%s }}},\n", 
 				path);
 		}
 		if (!strncmp(tree->name, "pci", 3)){
@@ -580,11 +580,11 @@
 			else
 				fn = "0";
 
-			fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", 
+			fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", 
 				dev, fn);
 		}
 		if (!strncmp(tree->name, "ioport", 6)){
-			fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=0x%s}}},\n", 
+			fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x%s}}},\n", 
 				path);
 		}
 	}
Index: corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c
===================================================================
--- corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c	(Revision 716)
+++ corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c	(Arbeitskopie)
@@ -64,7 +64,7 @@
 		dev = dev_find_pci_device(X86_DX, X86_CX, dev);
 		if (dev != 0) {
 			X86_BH = dev->bus->secondary;
-			X86_BL = dev->path.u.pci.devfn;
+			X86_BL = dev->path.pci.devfn;
 			X86_AH = SUCCESSFUL;
 			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
 			ret = 1;
@@ -79,7 +79,7 @@
 		dev = dev_find_class(X86_ECX, dev);
 		if (dev != 0) {
 			X86_BH = dev->bus->secondary;
-			X86_BL = dev->path.u.pci.devfn;
+			X86_BL = dev->path.pci.devfn;
 			X86_AH = SUCCESSFUL;
 			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
 			ret = 1;
Index: corebootv3-anonymous_unions/util/x86emu/vm86.c
===================================================================
--- corebootv3-anonymous_unions/util/x86emu/vm86.c	(Revision 716)
+++ corebootv3-anonymous_unions/util/x86emu/vm86.c	(Arbeitskopie)
@@ -249,7 +249,7 @@
 		*(unsigned char *) i = 0;
 	}
 
-	real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.u.pci.devfn);
+	real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn);
 }
 
 
@@ -603,7 +603,7 @@
 			// busnum is an unsigned char;
 			// devfn is an int, so we mask it off. 
 			busdevfn = (dev->bus->secondary << 8)
-				| (dev->path.u.pci.devfn & 0xff);
+				| (dev->path.pci.devfn & 0xff);
 			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			*pebx = busdevfn;
 			retval = 0;
Index: corebootv3-anonymous_unions/util/x86emu/biosemu.c
===================================================================
--- corebootv3-anonymous_unions/util/x86emu/biosemu.c	(Revision 716)
+++ corebootv3-anonymous_unions/util/x86emu/biosemu.c	(Arbeitskopie)
@@ -323,7 +323,7 @@
 	int i;
 	unsigned short initialcs = (addr & 0xF0000) >> 4;
 	unsigned short initialip = (addr + 3) & 0xFFFF;
-	unsigned short devfn = dev->bus->secondary << 8 | dev->path.u.pci.devfn;
+	unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn;
 	X86EMU_intrFuncs intFuncs[256];
 
 	X86EMU_setMemBase(0, 0x100000);
Index: corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c
===================================================================
--- corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c	(Revision 716)
+++ corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c	(Arbeitskopie)
@@ -94,7 +94,7 @@
 struct device_operations geodelx_cpuops = {
 	{.id = {.type = DEVICE_ID_PCI,
 		/* TODO: This is incorrect, these are _not_ PCI IDs! */
-		.u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},
+		{.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},
 	 .ops = &geodelx_cpuops}	.constructor	= default_device_constructor,
 	.phase3_scan	= NULL,
 	.phase6_init	= lx_init,


-- 
http://www.hailfinger.org/

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From c-d.hailfinger.devel.2006 at gmx.net  Sun Aug  3 23:12:18 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 Aug 2008 23:12:18 +0200
Subject: [coreboot] [PATCH] Support for the ASI MB-5BLGP (Neoware	Eon
 4000s)
In-Reply-To: <20080803205758.GE6389@greenwood>
References: <20080710115531.GC23984@greenwood>
	<20080803205758.GE6389@greenwood>
Message-ID: <48961F32.2060506@gmx.net>

On 03.08.2008 22:57, Uwe Hermann wrote:
> On Thu, Jul 10, 2008 at 01:55:31PM +0200, Uwe Hermann wrote:
>   
>> Hi,
>>
>> here's a patch for the Neoware Eon 4000s thin client, based on the info
>> from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html
>>     
>
> *ping*
>
> Can I get an Acked-by for this so we can commit a new board?
> It's been tested to work on hardware with 'irqpoll', might need some
> more investigations to fixup IRQs so it'll also work without 'irqpoll',
> but this is definately committable IMHO.
>   

If you fix the typo in the commit message (InitiaL):
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel

>> Initia support for the ASI MB-5BLGP (Neoware Eon 4000s).
>>
>> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
>>
>> Index: src/mainboard/asi/mb_5blgp/Config.lb
>> ===================================================================
>> --- src/mainboard/asi/mb_5blgp/Config.lb	(Revision 0)
>> +++ src/mainboard/asi/mb_5blgp/Config.lb	(Revision 0)
>> @@ -0,0 +1,137 @@
>> +##
>> +## This file is part of the coreboot project.
>> +##
>> +## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
>> +##
>> +## This program is free software; you can redistribute it and/or modify
>> +## it under the terms of the GNU General Public License as published by
>> +## the Free Software Foundation; either version 2 of the License, or
>> +## (at your option) any later version.
>> +##
>> +## This program is distributed in the hope that it will be useful,
>> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
>> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> +## GNU General Public License for more details.
>> +##
>> +## You should have received a copy of the GNU General Public License
>> +## along with this program; if not, write to the Free Software
>> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> +##
>> +
>> +if USE_FALLBACK_IMAGE
>> +	default ROM_SECTION_SIZE = FALLBACK_SIZE
>> +	default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
>> +else
>> +	default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
>> +	default ROM_SECTION_OFFSET = 0
>> +end
>> +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
>> +				    + ROM_SECTION_OFFSET + 1)
>> +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
>> +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
>> +default XIP_ROM_SIZE = 64 * 1024
>> +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
>> +arch i386 end
>> +driver mainboard.o
>> +if HAVE_PIRQ_TABLE
>> +	object irq_tables.o
>> +end
>> +makerule ./failover.E
>> +	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
>> +	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
>> +end
>> +makerule ./failover.inc
>> +	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
>> +	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
>> +end
>> +makerule ./auto.E
>> +	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
>> +	depends	"$(MAINBOARD)/auto.c ./romcc"
>> +	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
>> +end
>> +makerule ./auto.inc
>> +	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
>> +	depends "$(MAINBOARD)/auto.c ./romcc"
>> +	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
>> +end
>> +mainboardinit cpu/x86/16bit/entry16.inc
>> +mainboardinit cpu/x86/32bit/entry32.inc
>> +ldscript /cpu/x86/16bit/entry16.lds
>> +ldscript /cpu/x86/32bit/entry32.lds
>> +if USE_FALLBACK_IMAGE
>> +	mainboardinit cpu/x86/16bit/reset16.inc
>> +	ldscript /cpu/x86/16bit/reset16.lds
>> +else
>> +	mainboardinit cpu/x86/32bit/reset32.inc
>> +	ldscript /cpu/x86/32bit/reset32.lds
>> +end
>> +mainboardinit arch/i386/lib/cpu_reset.inc
>> +mainboardinit arch/i386/lib/id.inc
>> +ldscript /arch/i386/lib/id.lds
>> +if USE_FALLBACK_IMAGE
>> +	ldscript /arch/i386/lib/failover.lds
>> +	mainboardinit ./failover.inc
>> +end
>> +mainboardinit cpu/x86/fpu/enable_fpu.inc
>> +mainboardinit cpu/amd/model_gx1/cpu_setup.inc
>> +mainboardinit cpu/amd/model_gx1/gx_setup.inc
>> +mainboardinit ./auto.inc
>> +
>> +dir /pc80
>> +config chip.h
>> +
>> +chip northbridge/amd/gx1		# Northbridge
>> +  device pci_domain 0 on		# PCI domain
>> +    device pci 0.0 on end		# Host bridge
>> +    chip southbridge/amd/cs5530		# Southbridge
>> +      device pci 0f.0 on end		# Ethernet
>> +      device pci 12.0 on		# ISA bridge
>> +        chip superio/nsc/pc87351	# Super I/O
>> +          device pnp 2e.0 off		# Floppy
>> +            io 0x60 = 0x3f0
>> +            irq 0x70 = 6
>> +            drq 0x74 = 2
>> +          end
>> +          device pnp 2e.1 on		# Parallel port
>> +            io 0x60 = 0x378
>> +            irq 0x70 = 7
>> +          end
>> +          device pnp 2e.2 on		# COM2
>> +            io 0x60 = 0x2f8
>> +            irq 0x70 = 3
>> +          end
>> +          device pnp 2e.e on		# COM1
>> +            io 0x60 = 0x3f8
>> +            irq 0x70 = 4
>> +          end
>> +          device pnp 2e.4 on		# System wake-up control (SWC)
>> +            irq 0x60 = 0x500
>> +          end
>> +          device pnp 2e.5 on		# PS/2 mouse
>> +            irq 0x70 = 12
>> +          end
>> +          device pnp 2e.6 on		# PS/2 keyboard
>> +            io 0x60 = 0x60
>> +            io 0x62 = 0x64
>> +            irq 0x70 = 1
>> +          end
>> +          device pnp 2e.7 on		# GPIO
>> +            irq 0x60 = 0x800
>> +          end
>> +          device pnp 2e.8 on		# Fan speed control
>> +            irq 0x60 = 0x900
>> +          end
>> +        end
>> +      end
>> +      device pci 12.1 off end		# SMI
>> +      device pci 12.2 on end		# IDE
>> +      device pci 12.3 on end		# Audio
>> +      device pci 12.4 on end		# VGA
>> +      device pci 13.0 on end		# USB
>> +      register "ide0_enable" = "1"
>> +      register "ide1_enable" = "0"	# No connector on this board
>> +    end
>> +  end
>> +  chip cpu/amd/model_gx1		# CPU
>> +  end
>> +end
>> Index: src/mainboard/asi/mb_5blgp/irq_tables.c
>> ===================================================================
>> --- src/mainboard/asi/mb_5blgp/irq_tables.c	(Revision 0)
>> +++ src/mainboard/asi/mb_5blgp/irq_tables.c	(Revision 0)
>> @@ -0,0 +1,46 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + */
>> +
>> +#include <arch/pirq_routing.h>
>> +
>> +const struct irq_routing_table intel_irq_routing_table = {
>> +	PIRQ_SIGNATURE,
>> +	PIRQ_VERSION,
>> +	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
>> +	0x00,			/* Interrupt router bus */
>> +	(0x12 << 3) | 0x0,	/* Interrupt router device */
>> +	0x8800,			/* IRQs devoted exclusively to PCI usage */
>> +	0x1078,			/* Vendor */
>> +	0x2,			/* Device */
>> +	0,			/* Crap (miniport) */
>> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
>> +	0x96,			/* Checksum */
>> +	{
>> +		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
>> +		{0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */
>> +		{0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */
>> +		{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */
>> +	}
>> +};
>> +
>> +unsigned long write_pirq_routing_table(unsigned long addr)
>> +{
>> +	return copy_pirq_routing_table(addr);
>> +}
>> Index: src/mainboard/asi/mb_5blgp/Options.lb
>> ===================================================================
>> --- src/mainboard/asi/mb_5blgp/Options.lb	(Revision 0)
>> +++ src/mainboard/asi/mb_5blgp/Options.lb	(Revision 0)
>> @@ -0,0 +1,105 @@
>> +##
>> +## This file is part of the coreboot project.
>> +##
>> +## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
>> +##
>> +## This program is free software; you can redistribute it and/or modify
>> +## it under the terms of the GNU General Public License as published by
>> +## the Free Software Foundation; either version 2 of the License, or
>> +## (at your option) any later version.
>> +##
>> +## This program is distributed in the hope that it will be useful,
>> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
>> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> +## GNU General Public License for more details.
>> +##
>> +## You should have received a copy of the GNU General Public License
>> +## along with this program; if not, write to the Free Software
>> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> +##
>> +
>> +uses HAVE_MP_TABLE
>> +uses HAVE_PIRQ_TABLE
>> +uses USE_FALLBACK_IMAGE
>> +uses HAVE_FALLBACK_BOOT
>> +uses HAVE_HARD_RESET
>> +uses HAVE_OPTION_TABLE
>> +uses USE_OPTION_TABLE
>> +uses CONFIG_ROM_PAYLOAD
>> +uses IRQ_SLOT_COUNT
>> +uses MAINBOARD
>> +uses MAINBOARD_VENDOR
>> +uses MAINBOARD_PART_NUMBER
>> +uses COREBOOT_EXTRA_VERSION
>> +uses ARCH
>> +uses FALLBACK_SIZE
>> +uses STACK_SIZE
>> +uses HEAP_SIZE
>> +uses ROM_SIZE
>> +uses ROM_SECTION_SIZE
>> +uses ROM_IMAGE_SIZE
>> +uses ROM_SECTION_SIZE
>> +uses ROM_SECTION_OFFSET
>> +uses CONFIG_ROM_PAYLOAD_START
>> +uses PAYLOAD_SIZE
>> +uses _ROMBASE
>> +uses _RAMBASE
>> +uses XIP_ROM_SIZE
>> +uses XIP_ROM_BASE
>> +uses CROSS_COMPILE
>> +uses CC
>> +uses HOSTCC
>> +uses OBJCOPY
>> +uses DEFAULT_CONSOLE_LOGLEVEL
>> +uses MAXIMUM_CONSOLE_LOGLEVEL
>> +uses CONFIG_CONSOLE_SERIAL8250
>> +uses TTYS0_BAUD
>> +uses TTYS0_BASE
>> +uses TTYS0_LCS
>> +uses CONFIG_COMPRESSED_PAYLOAD_LZMA
>> +uses CONFIG_UDELAY_TSC
>> +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
>> +uses CONFIG_VIDEO_MB
>> +uses CONFIG_SPLASH_GRAPHIC
>> +uses CONFIG_GX1_VIDEO
>> +uses CONFIG_GX1_VIDEOMODE
>> +uses PIRQ_ROUTE
>> +
>> +## Enable VGA with a splash screen (only 640x480 to run on most monitors).
>> +## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
>> +## Note: Higher resolutions might need faster SDRAM speed.
>> +default CONFIG_GX1_VIDEO = 1
>> +default CONFIG_GX1_VIDEOMODE = 0
>> +default CONFIG_SPLASH_GRAPHIC = 1
>> +default CONFIG_VIDEO_MB = 2
>> +
>> +default ROM_SIZE = 256 * 1024
>> +default HAVE_PIRQ_TABLE = 1
>> +default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
>> +default PIRQ_ROUTE = 1
>> +default HAVE_FALLBACK_BOOT = 1
>> +default HAVE_MP_TABLE = 0
>> +default HAVE_HARD_RESET = 0
>> +default CONFIG_UDELAY_TSC = 1
>> +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
>> +default HAVE_OPTION_TABLE = 0
>> +default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
>> +default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
>> +default ROM_IMAGE_SIZE = 64 * 1024
>> +default FALLBACK_SIZE = 128 * 1024
>> +default STACK_SIZE = 8 * 1024
>> +default HEAP_SIZE = 16 * 1024
>> +default USE_OPTION_TABLE = 0
>> +default _RAMBASE = 0x00004000
>> +default CONFIG_ROM_PAYLOAD = 1
>> +default CROSS_COMPILE = ""
>> +default CC = "$(CROSS_COMPILE)gcc "
>> +default HOSTCC = "gcc"
>> +default CONFIG_CONSOLE_SERIAL8250 = 1
>> +default TTYS0_BAUD = 115200
>> +default TTYS0_BASE = 0x3f8
>> +default TTYS0_LCS = 0x3		# 8n1
>> +default DEFAULT_CONSOLE_LOGLEVEL = 9
>> +default MAXIMUM_CONSOLE_LOGLEVEL = 9
>> +
>> +end
>> Index: src/mainboard/asi/mb_5blgp/auto.c
>> ===================================================================
>> --- src/mainboard/asi/mb_5blgp/auto.c	(Revision 0)
>> +++ src/mainboard/asi/mb_5blgp/auto.c	(Revision 0)
>> @@ -0,0 +1,45 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + */
>> +
>> +#define ASSEMBLY 1
>> +
>> +#include <stdint.h>
>> +#include <arch/io.h>
>> +#include <device/pnp_def.h>
>> +#include <arch/romcc_io.h>
>> +#include <arch/hlt.h>
>> +#include "pc80/serial.c"
>> +#include "arch/i386/lib/console.c"
>> +#include "ram/ramtest.c"
>> +#include "northbridge/amd/gx1/raminit.c"
>> +#include "cpu/x86/bist.h"
>> +#include "superio/nsc/pc87351/pc87351_early_serial.c"
>> +
>> +#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
>> +
>> +static void main(unsigned long bist)
>> +{
>> +	pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
>> +	uart_init();
>> +	console_init();
>> +	report_bist_failure(bist);
>> +	sdram_init();
>> +	/* ram_check(0, 640 * 1024); */
>> +}
>> Index: src/mainboard/asi/mb_5blgp/chip.h
>> ===================================================================
>> --- src/mainboard/asi/mb_5blgp/chip.h	(Revision 0)
>> +++ src/mainboard/asi/mb_5blgp/chip.h	(Revision 0)
>> @@ -0,0 +1,22 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + */
>> +
>> +extern struct chip_operations mainboard_asi_mb_5blgp_ops;
>> +struct mainboard_asi_mb_5blgp_config {};
>> Index: src/mainboard/asi/mb_5blgp/mainboard.c
>> ===================================================================
>> --- src/mainboard/asi/mb_5blgp/mainboard.c	(Revision 0)
>> +++ src/mainboard/asi/mb_5blgp/mainboard.c	(Revision 0)
>> @@ -0,0 +1,26 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + */
>> +
>> +#include <device/device.h>
>> +#include "chip.h"
>> +
>> +struct chip_operations mainboard_asi_mb_5blgp_ops = {
>> +	CHIP_NAME("ASI MB-5BLGP Mainboard")
>> +};
>> Index: targets/asi/mb_5blgp/Config.lb
>> ===================================================================
>> --- targets/asi/mb_5blgp/Config.lb	(Revision 0)
>> +++ targets/asi/mb_5blgp/Config.lb	(Revision 0)
>> @@ -0,0 +1,54 @@
>> +##
>> +## This file is part of the coreboot project.
>> +##
>> +## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
>> +##
>> +## This program is free software; you can redistribute it and/or modify
>> +## it under the terms of the GNU General Public License as published by
>> +## the Free Software Foundation; either version 2 of the License, or
>> +## (at your option) any later version.
>> +##
>> +## This program is distributed in the hope that it will be useful,
>> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
>> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> +## GNU General Public License for more details.
>> +##
>> +## You should have received a copy of the GNU General Public License
>> +## along with this program; if not, write to the Free Software
>> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> +##
>> +
>> +target mb_5blgp
>> +mainboard asi/mb_5blgp
>> +
>> +option ROM_SIZE = 256 * 1024
>> +
>> +option MAINBOARD_VENDOR = "ASI"
>> +option MAINBOARD_PART_NUMBER = "MB-5BLGP"
>> +
>> +option IRQ_SLOT_COUNT = 3
>> +
>> +## Enable VGA with a splash screen (only 640x480 to run on most monitors).
>> +## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
>> +## Note: Higher resolutions might need faster SDRAM speed.
>> +option CONFIG_GX1_VIDEO = 1
>> +option CONFIG_GX1_VIDEOMODE = 0
>> +option CONFIG_SPLASH_GRAPHIC = 1
>> +option CONFIG_VIDEO_MB = 2
>> +
>> +option DEFAULT_CONSOLE_LOGLEVEL = 9
>> +option MAXIMUM_CONSOLE_LOGLEVEL = 9
>> +
>> +romimage "normal"
>> +	option USE_FALLBACK_IMAGE = 0
>> +	option COREBOOT_EXTRA_VERSION = ".0Normal"
>> +	payload ../payload.elf
>> +end
>> +
>> +romimage "fallback"
>> +	option USE_FALLBACK_IMAGE = 1
>> +	option COREBOOT_EXTRA_VERSION = ".0Fallback"
>> +	payload ../payload.elf
>> +end
>> +
>> +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
>>     
>
>   
>> -- 
>> coreboot mailing list
>> coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>     
>
>   


-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Mon Aug  4 00:18:45 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 15:18:45 -0700
Subject: [coreboot] patch: k8north more fixes etc. for compilation
Message-ID: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>

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From rminnich at gmail.com  Mon Aug  4 00:19:45 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 15:19:45 -0700
Subject: [coreboot] [PATCH] v3: move to anonymous unions
In-Reply-To: <48961C71.5010604@gmx.net>
References: <48961C71.5010604@gmx.net>
Message-ID: <13426df10808031519m16fcb7efx648f5c6ae6b8fd0@mail.gmail.com>

I like the change but please, NOBODY ack this until you test it on
something! this is a far-reaching change.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 00:36:31 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 00:36:31 +0200
Subject: [coreboot] patch: k8north more fixes etc. for compilation
In-Reply-To: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>
References: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>
Message-ID: <489632EF.3060705@gmx.net>

On 04.08.2008 00:18, ron minnich wrote:
> This is much closer to compiling. 
> Need to get spd in. 
> now use the new options stuff from LAR. 
> Added correct defines for nvidia. 
> mv macros.h to include/arch/x86
> Other basic cleanup to get things to build. 
>
> Still need to resolve the struct device thing. Probably going to write a 
> small function that takes bus, dev, fn and creates an un-connected struct device
> for stage 1 use only. This will get us there; we need to get working, then we
> can see the beautician. 
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Same comment as before: Ugly base code, but the patch improves the
situation.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Mon Aug  4 00:42:02 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 00:42:02 +0200
Subject: [coreboot] r717 - in coreboot-v3: . arch/x86 arch/x86/amd
	arch/x86/amd/k8 include/arch/x86/amd/k8 include/device
	mainboard/gigabyte/m57sli northbridge/amd/k8
Message-ID: <mailman.1773.1355071350.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-04 00:42:01 +0200 (Mon, 04 Aug 2008)
New Revision: 717

Removed:
   coreboot-v3/arch/x86/macros.h
Modified:
   coreboot-v3/Rules.make
   coreboot-v3/arch/x86/amd/k8/stage1.c
   coreboot-v3/arch/x86/amd/stage0.S
   coreboot-v3/arch/x86/mc146818rtc.c
   coreboot-v3/include/arch/x86/amd/k8/k8.h
   coreboot-v3/include/arch/x86/amd/k8/sysconf.h
   coreboot-v3/include/device/pci_ids.h
   coreboot-v3/mainboard/gigabyte/m57sli/Makefile
   coreboot-v3/northbridge/amd/k8/raminit.c
Log:
We're getting closer. It has been pointed out that this code is not pretty. I agree. Get 
it working, then we'll get it pretty. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Modified: coreboot-v3/Rules.make
===================================================================
--- coreboot-v3/Rules.make	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/Rules.make	2008-08-03 22:42:01 UTC (rev 717)
@@ -42,6 +42,13 @@
 		--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
 		--option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c 
 
+$(obj)/mainboard/$(MAINBOARDDIR)/option_table.h: $(obj)/util/options/build_opt_tbl $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout
+	$(Q)printf "  OPTIONS $(subst $(shell pwd)/,,$(@))\n"
+	$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
+	$(Q)$(obj)/util/options/build_opt_tbl -b \
+		--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
+		--header $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c 
+
 $(obj)/option_table: $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o
 	$(Q)printf "  OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(OBJCOPY) -O binary $< $@ 

Modified: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-03 22:42:01 UTC (rev 717)
@@ -22,6 +22,7 @@
 #include <lib.h>
 #include <console.h>
 #include <msr.h>
+#include <macros.h>
 #include <amd/k8/k8.h>
 
 /**

Modified: coreboot-v3/arch/x86/amd/stage0.S
===================================================================
--- coreboot-v3/arch/x86/amd/stage0.S	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/arch/x86/amd/stage0.S	2008-08-03 22:42:01 UTC (rev 717)
@@ -17,11 +17,11 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
-#include "../macros.h"
+#define ASSEMBLY
+#include <macros.h>
 #define CacheSize CONFIG_CARSIZE
 #define CacheBase CONFIG_CARBASE
 #define MEM_TOPK 2048
-#define ASSEMBLY
 
 /* leave some space for global variable to pass to RAM stage */
 #define GlobalVarSize 32

Deleted: coreboot-v3/arch/x86/macros.h
===================================================================
--- coreboot-v3/arch/x86/macros.h	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/arch/x86/macros.h	2008-08-03 22:42:01 UTC (rev 717)
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 Ron G. Minnich <rminnich at lanl.gov>
- * Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#ifndef ARCH_X86_MACROS_H
-#define ARCH_X86_MACROS_H
-
-#define port80_post(value)	\
-	movb	$value, %al;	\
-	outb	%al, $0x80
-
-#endif /* ARCH_X86_MACROS_H */

Modified: coreboot-v3/arch/x86/mc146818rtc.c
===================================================================
--- coreboot-v3/arch/x86/mc146818rtc.c	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/arch/x86/mc146818rtc.c	2008-08-03 22:42:01 UTC (rev 717)
@@ -322,4 +322,14 @@
 	return (byte & RTC_NORMAL_BOOT_FLAG_SET);
 }
 
+unsigned read_option(unsigned start, unsigned size, unsigned def)
+{
+#ifdef CONFIG_OPTION_TABLE
+	unsigned byte;
+	byte = CMOS_READ(start/8);
+	return (byte >> (start & 7U)) & ((1U << size) - 1U);
+#else
+	return def;
+#endif
+}
 

Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-08-03 22:42:01 UTC (rev 717)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2006-2007 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -282,3 +282,124 @@
 #define	 NBCAP_MEMCLK_166MHZ  1
 #define	 NBCAP_MEMCLK_200MHZ  0
 #define	 NBCAP_MEMCTRL	      (1 << 8)
+
+/* resources for the routing in the northbridge. These may be family specific; 
+ * the were in v2. 
+ */
+#define RES_DEBUG 0
+#define RES_PCI_IO 0x10
+#define RES_PORT_IO_8 0x22
+#define RES_PORT_IO_32 0x20
+#define RES_MEM_IO 0x40
+
+#ifndef ASSEMBLY
+/* cpu version -- no support for f0 yet */
+static inline int is_cpu_rev_a0(void)
+{
+	return (cpuid_eax(1) & 0xfffef) == 0x0f00;
+}
+static inline int is_cpu_pre_c0(void)
+{
+        return (cpuid_eax(1) & 0xfffef) < 0x0f48;
+}
+
+static inline int is_cpu_c0(void)
+{
+        return (cpuid_eax(1) & 0xfffef) == 0x0f48;
+}
+
+static inline int is_cpu_pre_b3(void)
+{
+        return (cpuid_eax(1) & 0xfffef) < 0x0f41;
+}
+
+static inline int is_cpu_b3(void)
+{
+        return (cpuid_eax(1) & 0xfffef) == 0x0f41;
+}
+//AMD_D0_SUPPORT
+static inline int is_cpu_pre_d0(void)
+{
+        return (cpuid_eax(1) & 0xfff0f) < 0x10f00;
+}
+
+static inline int is_cpu_d0(void)
+{
+        return (cpuid_eax(1) & 0xfff0f) == 0x10f00;
+}
+
+//AMD_E0_SUPPORT
+static inline int is_cpu_pre_e0(void)
+{
+        return (cpuid_eax(1) & 0xfff0f) < 0x20f00;
+}
+
+static inline int is_cpu_e0(void)
+{
+        return (cpuid_eax(1) & 0xfff00) == 0x20f00;
+}
+
+
+/* note: we'd like to have this sysinfo common to all K8, there's no need to
+ * have one different kind per different kind of k8 at this point. 
+ */
+//#include "raminit.h"
+
+struct dimm_size {
+        u8 per_rank; // it is rows + col + bank_lines + data lines */
+        u8 rows;
+        u8 col;
+        u8 bank; //1, 2, 3 mean 2, 4, 8
+        u8 rank;
+} __attribute__((packed));
+
+struct mem_info { // pernode
+        u32 dimm_mask;
+        struct dimm_size sz[DIMM_SOCKETS];
+        u32 x4_mask;
+        u32 x16_mask;
+	u32 single_rank_mask;
+        u32 page_1k_mask;
+//        u32 ecc_mask;
+//        u32 registered_mask;
+        u8 is_opteron;
+        u8 is_registered;
+        u8 is_ecc;
+        u8 is_Width128;
+        u8 memclk_set; // we need to use this to retrieve the mem param
+	u8 rsv[3];
+} __attribute__((packed));
+
+struct link_pair_st {
+        struct device * udev;
+        u32 upos;
+        u32 uoffs;
+        struct device * dev;
+        u32 pos;
+        u32 offs;
+
+} __attribute__((packed));
+
+struct sys_info {
+        u8 ctrl_present[NODE_NUMS];
+        struct mem_info meminfo[NODE_NUMS];
+	struct mem_controller ctrl[NODE_NUMS];
+	u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
+        u32 tom_k;
+        u32 tom2_k;
+
+	u32 mem_base[NODE_NUMS];
+	u32 cs_base[NODE_NUMS*8]; //8 cs_idx
+	u32 hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it
+
+	u8 dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
+	u8 dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
+	u32 nodes;
+        struct link_pair_st link_pair[16];// enough? only in_conherent
+        u32 link_pair_num;
+        u32 ht_c_num;
+	u32 sbdn;
+	u32 sblk;
+	u32 sbbusn;
+} __attribute__((packed));
+#endif /* ! ASSEMBLY */

Modified: coreboot-v3/include/arch/x86/amd/k8/sysconf.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/sysconf.h	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/include/arch/x86/amd/k8/sysconf.h	2008-08-03 22:42:01 UTC (rev 717)
@@ -22,7 +22,7 @@
 
 #define HC_POSSIBLE_NUM 8
 
-struct amdk8_sysconf_t {
+struct amdk8_sysconf{
 	//ht
 	unsigned nodes;
 	unsigned hc_possible_num;

Modified: coreboot-v3/include/device/pci_ids.h
===================================================================
--- coreboot-v3/include/device/pci_ids.h	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/include/device/pci_ids.h	2008-08-03 22:42:01 UTC (rev 717)
@@ -155,33 +155,32 @@
 #define PCI_VENDOR_ID_CIRRUS			0x1013
 #define PCI_DEVICE_ID_CIRRUS_5446		0x00b8	/* Used by QEMU */
 
-#define PCI_VENDIR_ID_NVIDIA                    0x10de
-/*
-0360MCP55 LPC Bridge
-0361MCP55 LPC Bridge
-0362MCP55 LPC Bridge
-0363MCP55 LPC Bridge
-0364MCP55 LPC Bridge
-0365MCP55 LPC Bridge
-0366MCP55 LPC Bridge
-0367MCP55 LPC Bridge
-0368MCP55 SMBus
-0369MCP55 Memory Controller
-036aMCP55 Memory Controller
-036bMCP55 SMU
-036cMCP55 USB Controller
-036dMCP55 USB Controller
-036eMCP55 IDE
-0370MCP55 PCI bridge
-0371MCP55 High Definition Audio
-0372MCP55 Ethernet
-0373MCP55 Ethernet
-0374MCP55 PCI Express bridge
-0375MCP55 PCI Express bridge
-0376MCP55 PCI Express bridge
-0377MCP55 PCI Express bridge
-0378MCP55 PCI Express bridge
-037aMCP55 Memory Controller
-*/
-#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIBRIDGE 0x370
+#define PCI_VENDOR_ID_NVIDIA                    0x10de
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC          0x0360
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE        0x0361
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2        0x0362
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3        0x0363
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4        0x0364
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5        0x0365
+#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6        0x0366
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO          0x0367
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2          0x0368
+#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE          0x036E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0        0x037E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1        0x037F
+#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC          0x0372
+#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE   0x0373
+#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA          0x0371
+#define PCI_DEVICE_ID_NVIDIA_MCP55_USB          0x036C
+#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2         0x036D
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI          0x0370
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C     0x0374
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E       0x0375
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A       0x0376
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F       0x0377
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D       0x0378
+#define PCI_DEVICE_ID_NVIDIA_MCP55_HT           0x0369
+#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM         0x036A
+#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU          0x036B
+
 #endif /* DEVICE_PCI_IDS_H */

Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-08-03 22:42:01 UTC (rev 717)
@@ -19,7 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
+STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \
+			$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
 
 INITRAM_SRC =      $(src)/mainboard/$(MAINBOARDDIR)/initram.c
 

Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-03 19:39:35 UTC (rev 716)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-03 22:42:01 UTC (rev 717)
@@ -32,15 +32,25 @@
 
 #include <console.h>
 #include <mtrr.h>
+#include <macros.h>
+#include <spd.h>
+#include <cpu.h>
+#include <msr.h>
 #include <amd/k8/raminit.h>
 #include <amd/k8/k8.h>
 #include <amd/k8/sysconf.h>
 #include <device/pci.h>
+#include <mc146818rtc.h>
+#include <lib.h>
 
 #ifndef QRANK_DIMM_SUPPORT
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
+#ifndef HW_MEM_HOLE_SIZEK
+#define HW_MEM_HOLE_SIZEK 64*1024*1024
+#endif
+
 static void hard_reset(void);
 
 static void setup_resource_map(const unsigned int *register_values, int max)
@@ -566,14 +576,14 @@
 
 static void hw_enable_ecc(const struct mem_controller *ctrl)
 {
-	u32 dcl, nbcap;
+	u32 dcl, nbcap, opt = 1;
 	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_DimmEccEn;
 	if (nbcap & NBCAP_ECC) {
 		dcl |= DCL_DimmEccEn;
 	}
-	if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+	if (get_option(&opt, "ECC_memory") || opt) {
 		dcl &= ~DCL_DimmEccEn;
 	}
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
@@ -610,16 +620,6 @@
 	return !(dcl & DCL_UnBufDimm);
 }
 
-struct dimm_size {
-	unsigned long side1;
-	unsigned long side2;
-	unsigned long rows;
-	unsigned long col;
-#if QRANK_DIMM_SUPPORT == 1
-	unsigned long rank;
-#endif
-};
-
 static struct dimm_size spd_get_dimm_size(unsigned device)
 {
 	/* Calculate the log base 2 size of a DIMM in bits */
@@ -1118,8 +1118,9 @@
 static void order_dimms(const struct mem_controller *ctrl)
 {
 	unsigned long tom_k, base_k;
+	int opt = 1;
 
-	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
+	if (get_option(&opt, "interleave_chip_selects") || opt) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
 		printk(BIOS_DEBUG, "Interleaving disabled\n");
@@ -1405,6 +1406,7 @@
 	unsigned min_cycle_time, min_latency, bios_cycle_time;
 	int i;
 	u32 value;
+	u32 max_mem_clk_index = 0;
 
 	static const u8 latency_indicies[] = { 26, 23, 9 };
 	static const unsigned char min_cycle_times[] = {
@@ -1417,8 +1419,9 @@
 	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
 
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
-	bios_cycle_time = min_cycle_times[
-		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
+
+	get_option(&max_mem_clk_index, "max_mem_clk");
+	bios_cycle_time = min_cycle_times[max_mem_clk_index];
 	if (bios_cycle_time > min_cycle_time) {
 		min_cycle_time = bios_cycle_time;
 	}
@@ -2111,7 +2114,7 @@
 	return;
  hw_spd_err:
 	/* Unrecoverable error reading SPD data */
-	print_err("SPD error - reset\n");
+	printk(BIOS_ERR, "SPD error - reset\n");
 	hard_reset();
 	return;
 }




From rminnich at gmail.com  Mon Aug  4 00:43:03 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 15:43:03 -0700
Subject: [coreboot] patch: k8north more fixes etc. for compilation
In-Reply-To: <489632EF.3060705@gmx.net>
References: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>
	<489632EF.3060705@gmx.net>
Message-ID: <13426df10808031543y2d305d1ei514e3187a33acc1f@mail.gmail.com>

On Sun, Aug 3, 2008 at 3:36 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 04.08.2008 00:18, ron minnich wrote:
>> This is much closer to compiling.
>> Need to get spd in.
>> now use the new options stuff from LAR.
>> Added correct defines for nvidia.
>> mv macros.h to include/arch/x86
>> Other basic cleanup to get things to build.
>>
>> Still need to resolve the struct device thing. Probably going to write a
>> small function that takes bus, dev, fn and creates an un-connected struct device
>> for stage 1 use only. This will get us there; we need to get working, then we
>> can see the beautician.
>>
>> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>
> Same comment as before: Ugly base code, but the patch improves the
> situation.
>
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>

I have no argument with your comments here. We'll fix it! ;-)

Committed revision 717.



From philip.aston at ntlworld.com  Mon Aug  4 00:43:42 2008
From: philip.aston at ntlworld.com (Philip Aston)
Date: Sun, 03 Aug 2008 23:43:42 +0100
Subject: [coreboot] Testing flashrom on MS6178
Message-ID: <1217803423.16531.30.camel@localhost>

Here is the initial result using flashrom on MS6178 version 1.1:

Flashrom will create a backup copy of the BIOS.

However, it is not possible to write to the chip using flashrom -w.

(1) attempting to write coreboot to the chip:

"Calibrating delay loop... OK.

No coreboot table found.

Found chipset "Intel ICH", enabling flash write... OK.

Found chip "Intel 82802AB" (512 KB) at physical address 0xfff80000.

Note: If the following flash access fails, try -m <vendor>:<mainboard>.

Programming page: 

0000 at address: 0x00000000BLOCK ERASE failed at 0x0

0001 at address: 0x00010000BLOCK ERASE failed at 0x10000

0002 at address: 0x00020000BLOCK ERASE failed at 0x20000

0003 at address: 0x00030000BLOCK ERASE failed at 0x30000

0004 at address: 0x00040000SKIPPED

0005 at address: 0x00050000BLOCK ERASE failed at 0x50000

0006 at address: 0x00060000BLOCK ERASE failed at 0x60000

0007 at address: 0x00070000DONE BLOCK 0x70000"


(2) In case I had provided an incorrect file address, I then provided
the path in full. I am satisfied that I had the file correctly named on
both occasions, however the result was slightly different:


"Calibrating delay loop... OK.

No coreboot table found.

Found chipset "Intel ICH", enabling flash write... OK.

Found chip "Intel 82802AB" (512 KB) at physical address 0xfff80000.

Note: If the following flash access fails, try -m <vendor>:<mainboard>.

Programming page: 

0000 at address: 0x00000000BLOCK ERASE failed at 0x0

0001 at address: 0x00010000BLOCK ERASE failed at 0x10000

0002 at address: 0x00020000BLOCK ERASE failed at 0x20000

0003 at address: 0x00030000BLOCK ERASE failed at 0x30000

0004 at address: 0x00040000SKIPPED

0005 at address: 0x00050000BLOCK ERASE failed at 0x50000

0006 at address: 0x00060000BLOCK ERASE failed at 0x60000

0007 at address: 0x00070000SKIPPED"



(3) I have other versions of the factory bios, so I tried to write one
of them. The result was similar, but, instead of the line
?Note:...<mainboard>" 

output was:

?Flash image seems to be a legacy BIOS. Disabling checks.?

The lines that ?followed were identical to (1).

Finally, I tried writing the original factory bios back to the chip
(which has worked using uniflash). The result was the same as (3).


On reboot, I found that either the bios had not altered- or just
possibly the restoration of the factory bios had worked. After all those
"fail" messages that seems unlikely.

I have a spare flash chip. Interestingly, this (earlier) bios has booted
the system without encountering the hardware detection problem that has
killed this board's performance, but some applications aren't working.
Reverting to the original chip, performance seems improved but the same
applications are not working. I am looking into this.

I will carry out further testing if required.










From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 00:57:10 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 00:57:10 +0200
Subject: [coreboot] patch: k8north more fixes etc. for compilation
In-Reply-To: <13426df10808031543y2d305d1ei514e3187a33acc1f@mail.gmail.com>
References: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>	<489632EF.3060705@gmx.net>
	<13426df10808031543y2d305d1ei514e3187a33acc1f@mail.gmail.com>
Message-ID: <489637C6.1080700@gmx.net>

On 04.08.2008 00:43, ron minnich wrote:
> On Sun, Aug 3, 2008 at 3:36 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> On 04.08.2008 00:18, ron minnich wrote:
>>     
>>> This is much closer to compiling.
>>> Need to get spd in.
>>> now use the new options stuff from LAR.
>>> Added correct defines for nvidia.
>>> mv macros.h to include/arch/x86
>>> Other basic cleanup to get things to build.
>>>
>>> Still need to resolve the struct device thing. Probably going to write a
>>> small function that takes bus, dev, fn and creates an un-connected struct device
>>> for stage 1 use only. This will get us there; we need to get working, then we
>>> can see the beautician.
>>>
>>> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>>>       
>> Same comment as before: Ugly base code, but the patch improves the
>> situation.
>>
>> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> I have no argument with your comments here. We'll fix it! ;-)
>   

I'm confident we will.

> Committed revision 717.
>   

You forgot to svn add macros.h at the new location (or use svn mv in the
first place).

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Mon Aug  4 01:14:58 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 16:14:58 -0700
Subject: [coreboot] patch: k8north more fixes etc. for compilation
In-Reply-To: <489637C6.1080700@gmx.net>
References: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>
	<489632EF.3060705@gmx.net>
	<13426df10808031543y2d305d1ei514e3187a33acc1f@mail.gmail.com>
	<489637C6.1080700@gmx.net>
Message-ID: <13426df10808031614n6e10c8d3hcef4c7fbcdd6583@mail.gmail.com>

weird. I used svn move.


In fact it showed up in my diff.

hmm.

ron



From rminnich at gmail.com  Mon Aug  4 01:19:52 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 16:19:52 -0700
Subject: [coreboot] next series on the north
Message-ID: <13426df10808031619r2b302c24yfbd4f5b797a3831@mail.gmail.com>

see patch.

ron
-------------- next part --------------
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From svn at coreboot.org  Mon Aug  4 01:36:45 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 01:36:45 +0200
Subject: [coreboot] r718 - coreboot-v3/include/arch/x86
Message-ID: <mailman.1774.1355071350.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-04 01:36:44 +0200 (Mon, 04 Aug 2008)
New Revision: 718

Added:
   coreboot-v3/include/arch/x86/macros.h
Log:
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Added: coreboot-v3/include/arch/x86/macros.h
===================================================================
--- coreboot-v3/include/arch/x86/macros.h	                        (rev 0)
+++ coreboot-v3/include/arch/x86/macros.h	2008-08-03 23:36:44 UTC (rev 718)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 Ron G. Minnich <rminnich at lanl.gov>
+ * Copyright (C) 2007 Stefan Reinauer <stepan at coresystems.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef ARCH_X86_MACROS_H
+#define ARCH_X86_MACROS_H
+
+#define port80_post(value)	\
+	movb	$value, %al;	\
+	outb	%al, $0x80
+
+
+
+#endif /* ARCH_X86_MACROS_H */




From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 01:59:46 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 01:59:46 +0200
Subject: [coreboot] v3 and partially memory-mapped ROMs
Message-ID: <48964672.4010803@gmx.net>

Hi,

this problem has been mentioned by me in the past, but I'd like to
remind people of it now that we're working on a M57SLI port to v3.

The LAR code and lots of other places can't cope with partially mapped
ROMs. There are two options:
- Rewrite the LAR+string code to use accessor functions: Ugly, makes the
code completely unreadable, severe performance penalty, people will wash
their eyes with bleach after reading it, makes sure the person writing
the code will be the only one to ever understand it.
- Require the bootblock and initram to be in the mapped area and mirror
the complete ROM into RAM after RAM is enabled: No overhead except for
stage2 and payloads, existing LAR+string code can be used after a small
audit, faster decompression for unmapped areas (up to a factor of two
for the M57SLI rev2, up to a factor of four for other chipsets),
needless copying of all unused (fallback, alternative payload) ROM areas.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Mon Aug  4 02:21:58 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Aug 2008 02:21:58 +0200
Subject: [coreboot] [PATCH] v3: move to anonymous unions
In-Reply-To: <13426df10808031519m16fcb7efx648f5c6ae6b8fd0@mail.gmail.com>
References: <48961C71.5010604@gmx.net>
	<13426df10808031519m16fcb7efx648f5c6ae6b8fd0@mail.gmail.com>
Message-ID: <20080804002158.5899.qmail@stuge.se>

On Sun, Aug 03, 2008 at 03:19:45PM -0700, ron minnich wrote:
> I like the change but please, NOBODY ack this until you test it on
> something! this is a far-reaching change.

I like it to. I expect it to work, but better test.


//Peter



From ward at gnu.org  Mon Aug  4 02:23:32 2008
From: ward at gnu.org (Ward Vandewege)
Date: Sun, 3 Aug 2008 20:23:32 -0400
Subject: [coreboot] patch: k8north more fixes etc. for compilation
In-Reply-To: <13426df10808031614n6e10c8d3hcef4c7fbcdd6583@mail.gmail.com>
References: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>
	<489632EF.3060705@gmx.net>
	<13426df10808031543y2d305d1ei514e3187a33acc1f@mail.gmail.com>
	<489637C6.1080700@gmx.net>
	<13426df10808031614n6e10c8d3hcef4c7fbcdd6583@mail.gmail.com>
Message-ID: <20080804002332.GA15426@localdomain>

On Sun, Aug 03, 2008 at 04:14:58PM -0700, ron minnich wrote:
> weird. I used svn move.
> 
> In fact it showed up in my diff.
> 
> hmm.

Can you fix it? v3 build is now broken:

$ make
  CP      build/config.h
  GEN     build/build.h
  BUILD   DUMMY VPD
  CC      build/lib/uart8250.o
  CC      build/lib/mem.o
  CC      build/lib/lar.o
  CC      build/lib/delay.o
  CC      build/lib/vtxprintf.o
  CC      build/lib/vsprintf.o
  CC      build/lib/console.o
  CC      build/lib/string.o
  CC      build/lib/lzma.o
  CC      build/arch/x86/stage1.o
  CC      build/arch/x86/serial.o
  CC      build/arch/x86/speaker.o
  CC      build/arch/x86/udelay_io.o
  CC      build/arch/x86/mc146818rtc.o
  CC      build/arch/x86/post_code.o
  CC      build/arch/x86/geodelx/stage1.o
  CC      build/arch/x86/../../northbridge/amd/geodelx/geodelxinit.o
  CC      build/arch/x86/geodelx/stage0.o
arch/x86/geodelx/stage0.S:28:23:
error: ../macros.h: No such file or directory
make: ***
[build/arch/x86/geodelx/stage0.o]
Error 1


Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From svn at coreboot.org  Mon Aug  4 02:39:29 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 02:39:29 +0200
Subject: [coreboot] r719 - in coreboot-v3/arch/x86: . geodelx
Message-ID: <mailman.1775.1355071350.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-04 02:39:28 +0200 (Mon, 04 Aug 2008)
New Revision: 719

Modified:
   coreboot-v3/arch/x86/geodelx/stage0.S
   coreboot-v3/arch/x86/stage0_i586.S
Log:
Trivial fix: fix include name for macros.h

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/arch/x86/geodelx/stage0.S
===================================================================
--- coreboot-v3/arch/x86/geodelx/stage0.S	2008-08-03 23:36:44 UTC (rev 718)
+++ coreboot-v3/arch/x86/geodelx/stage0.S	2008-08-04 00:39:28 UTC (rev 719)
@@ -25,7 +25,7 @@
 
 /* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
 
-#include "../macros.h"
+#include <macros.h>
 #include <amd_geodelx.h>
 
 	.code16

Modified: coreboot-v3/arch/x86/stage0_i586.S
===================================================================
--- coreboot-v3/arch/x86/stage0_i586.S	2008-08-03 23:36:44 UTC (rev 718)
+++ coreboot-v3/arch/x86/stage0_i586.S	2008-08-04 00:39:28 UTC (rev 719)
@@ -24,7 +24,7 @@
 
 # init code - switch cpu to pmode and enable cache as ram.
 
-#include "macros.h"
+#include <macros.h>
 
 #define ROM_CODE_SEG 0x08
 #define ROM_DATA_SEG 0x10




From rminnich at gmail.com  Mon Aug  4 02:40:14 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 17:40:14 -0700
Subject: [coreboot] patch: k8north more fixes etc. for compilation
In-Reply-To: <20080804002332.GA15426@localdomain>
References: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>
	<489632EF.3060705@gmx.net>
	<13426df10808031543y2d305d1ei514e3187a33acc1f@mail.gmail.com>
	<489637C6.1080700@gmx.net>
	<13426df10808031614n6e10c8d3hcef4c7fbcdd6583@mail.gmail.com>
	<20080804002332.GA15426@localdomain>
Message-ID: <13426df10808031740p3b8c6f8i2623dc653a4b91c7@mail.gmail.com>

yes, I am self-acking this one as it is a trivial fix. Sorry for the problem.

Please test.Committed revision 719.

ron



From ward at gnu.org  Mon Aug  4 02:45:22 2008
From: ward at gnu.org (Ward Vandewege)
Date: Sun, 3 Aug 2008 20:45:22 -0400
Subject: [coreboot] patch: k8north more fixes etc. for compilation
In-Reply-To: <13426df10808031740p3b8c6f8i2623dc653a4b91c7@mail.gmail.com>
References: <13426df10808031518i129661dan93e699ee9519912d@mail.gmail.com>
	<489632EF.3060705@gmx.net>
	<13426df10808031543y2d305d1ei514e3187a33acc1f@mail.gmail.com>
	<489637C6.1080700@gmx.net>
	<13426df10808031614n6e10c8d3hcef4c7fbcdd6583@mail.gmail.com>
	<20080804002332.GA15426@localdomain>
	<13426df10808031740p3b8c6f8i2623dc653a4b91c7@mail.gmail.com>
Message-ID: <20080804004522.GA19554@localdomain>

On Sun, Aug 03, 2008 at 05:40:14PM -0700, ron minnich wrote:
> yes, I am self-acking this one as it is a trivial fix. Sorry for the problem.
> 
> Please test.Committed revision 719.

Yep, fixed, thanks.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From rminnich at gmail.com  Mon Aug  4 04:19:38 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Aug 2008 19:19:38 -0700
Subject: [coreboot] patch: include/arch/x86/cpu.h
Message-ID: <13426df10808031919r3288f859ubef3e49d333e795e@mail.gmail.com>

standardize resource maps.

Good idea? bad idea?

ron
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From r.marek at assembler.cz  Mon Aug  4 10:40:15 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 04 Aug 2008 10:40:15 +0200
Subject: [coreboot] K8M890 VT8237S status update
In-Reply-To: <4865A403.1090305@assembler.cz>
References: <48654443.7020701@assembler.cz>	<13426df10806271527y126ef564s568535ad60bf6c15@mail.gmail.com>
	<4865A403.1090305@assembler.cz>
Message-ID: <4896C06F.5010908@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
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Hi all,

I'm posting yet another WIP patch. Still no progress on SATA, powernow-k8 and
slow SPI access (slow boot when executing from flash). I did not try VGA yet.

Other stuff works fine: IDE, USB, PCI slots, serial, ACPI, APIC, network.

This patch (compared to older WIP patch) adds support for the integrated network
adapter without any external configuration flash plus it programs the chipset to
handle the LDTSTOP signal, so the CPU is switched to maxFID/maxVID - but
frequency changes are not working in Linux yet.

The network address is "00:00:DE:AD:BE:EF" as default. PHY has addr 1 as
recommended.

I need to ask VIA for some details. Will do that soon.

Rudolf

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From stepan at coresystems.de  Mon Aug  4 12:41:57 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 04 Aug 2008 12:41:57 +0200
Subject: [coreboot] v3 and partially memory-mapped ROMs
In-Reply-To: <48964672.4010803@gmx.net>
References: <48964672.4010803@gmx.net>
Message-ID: <4896DCF5.2000103@coresystems.de>

Carl-Daniel Hailfinger wrote:
> Hi,
>
> this problem has been mentioned by me in the past, but I'd like to
> remind people of it now that we're working on a M57SLI port to v3.
>
> The LAR code and lots of other places can't cope with partially mapped
> ROMs. There are two options:
>   
Are you talking about ROMs that can not be mapped completely at all?
Have you encountered any of these anywhere? If so I would like to know
what systems that were.

In any other case, the bootblock's duty is to enable full mapping of the
chip.



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 13:58:47 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 13:58:47 +0200
Subject: [coreboot] v3 and partially memory-mapped ROMs
In-Reply-To: <4896DCF5.2000103@coresystems.de>
References: <48964672.4010803@gmx.net> <4896DCF5.2000103@coresystems.de>
Message-ID: <4896EEF7.5050001@gmx.net>

On 04.08.2008 12:41, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> Hi,
>>
>> this problem has been mentioned by me in the past, but I'd like to
>> remind people of it now that we're working on a M57SLI port to v3.
>>
>> The LAR code and lots of other places can't cope with partially mapped
>> ROMs. There are two options:
>>   
>>     
> Are you talking about ROMs that can not be mapped completely at all?
>   

Yes.

> Have you encountered any of these anywhere? If so I would like to know
> what systems that were.
>   

Gigabyte M57SLI rev 2.0 uses the LPC-to-SPI translation feature of the
IT8716F which can only map the top (not a movable window!) 512 kBytes of
the SPI chip in memory space. There's an additional 128 kByte region
(from 4G-1152kB to 4G-1024kB, not movable) which is sort of a "register
space" compatibility feature. Everything outside these "standard" areas
needs to be read with explicit read commands in 3-byte chunks.

So any modded M57SLI with a chip greater than 512kB has this problem. I
tried every possible undocumented workaround to no avail, and contacted
ITE with no response.

> In any other case, the bootblock's duty is to enable full mapping of the
> chip.
>   

Fully agreed.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From ward at gnu.org  Mon Aug  4 14:13:47 2008
From: ward at gnu.org (Ward Vandewege)
Date: Mon, 4 Aug 2008 08:13:47 -0400
Subject: [coreboot] v3 and partially memory-mapped ROMs
In-Reply-To: <4896EEF7.5050001@gmx.net>
References: <48964672.4010803@gmx.net> <4896DCF5.2000103@coresystems.de>
	<4896EEF7.5050001@gmx.net>
Message-ID: <20080804121347.GA7288@localdomain>

On Mon, Aug 04, 2008 at 01:58:47PM +0200, Carl-Daniel Hailfinger wrote:
> Gigabyte M57SLI rev 2.0 uses the LPC-to-SPI translation feature of the
> IT8716F which can only map the top (not a movable window!) 512 kBytes of
> the SPI chip in memory space. There's an additional 128 kByte region
> (from 4G-1152kB to 4G-1024kB, not movable) which is sort of a "register
> space" compatibility feature. Everything outside these "standard" areas
> needs to be read with explicit read commands in 3-byte chunks.
> 
> So any modded M57SLI with a chip greater than 512kB has this problem. I
> tried every possible undocumented workaround to no avail, and contacted
> ITE with no response.

There is a patch by Ronald Hoogeboom with a workaround, which allows booting
from larger rom chips:

  http://article.gmane.org/gmane.linux.bios/33492

I'd still like to put it in the tree.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From arne.gleditsch at dolphinics.no  Mon Aug  4 14:18:03 2008
From: arne.gleditsch at dolphinics.no (Arne Georg Gleditsch)
Date: Mon, 04 Aug 2008 14:18:03 +0200
Subject: [coreboot] Fam10h support for Tyan S2912-E
Message-ID: <kjmvdyhug78.fsf@pelargir.dolphinics.no>

Hi,

I have a S2912 system that I'd like to run coreboot on.  As I understand
it, both the S2912 and Fam10h is supported seperately, but some porting
is required to make the combination work.  I'd like to work on getting
this configuration operational.  If anyone has any pointers on how to
tackle it, that would be more than welcome.

Thanks in advance,

-- 
								Arne.



From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 15:33:34 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 15:33:34 +0200
Subject: [coreboot] v3 and partially memory-mapped ROMs
In-Reply-To: <20080804121347.GA7288@localdomain>
References: <48964672.4010803@gmx.net> <4896DCF5.2000103@coresystems.de>
	<4896EEF7.5050001@gmx.net> <20080804121347.GA7288@localdomain>
Message-ID: <4897052E.6030000@gmx.net>

On 04.08.2008 14:13, Ward Vandewege wrote:
> On Mon, Aug 04, 2008 at 01:58:47PM +0200, Carl-Daniel Hailfinger wrote:
>   
>> Gigabyte M57SLI rev 2.0 uses the LPC-to-SPI translation feature of the
>> IT8716F which can only map the top (not a movable window!) 512 kBytes of
>> the SPI chip in memory space. There's an additional 128 kByte region
>> (from 4G-1152kB to 4G-1024kB, not movable) which is sort of a "register
>> space" compatibility feature. Everything outside these "standard" areas
>> needs to be read with explicit read commands in 3-byte chunks.
>>
>> So any modded M57SLI with a chip greater than 512kB has this problem. I
>> tried every possible undocumented workaround to no avail, and contacted
>> ITE with no response.
>>     
>
> There is a patch by Ronald Hoogeboom with a workaround, which allows booting
> from larger rom chips:
>
>   http://article.gmane.org/gmane.linux.bios/33492
>
> I'd still like to put it in the tree.
>   

I'm no longer opposing to put this in v2 (v2 is already complicated and
support for this will make it worse), but I shall make very sure that we
use a clean solution in v3.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From ward at gnu.org  Mon Aug  4 16:04:48 2008
From: ward at gnu.org (Ward Vandewege)
Date: Mon, 4 Aug 2008 10:04:48 -0400
Subject: [coreboot] v3 and partially memory-mapped ROMs
In-Reply-To: <4897052E.6030000@gmx.net>
References: <48964672.4010803@gmx.net> <4896DCF5.2000103@coresystems.de>
	<4896EEF7.5050001@gmx.net> <20080804121347.GA7288@localdomain>
	<4897052E.6030000@gmx.net>
Message-ID: <20080804140448.GA12829@localdomain>

On Mon, Aug 04, 2008 at 03:33:34PM +0200, Carl-Daniel Hailfinger wrote:
> >> Gigabyte M57SLI rev 2.0 uses the LPC-to-SPI translation feature of the
> >> IT8716F which can only map the top (not a movable window!) 512 kBytes of
> >> the SPI chip in memory space. There's an additional 128 kByte region
> >> (from 4G-1152kB to 4G-1024kB, not movable) which is sort of a "register
> >> space" compatibility feature. Everything outside these "standard" areas
> >> needs to be read with explicit read commands in 3-byte chunks.
> >>
> >> So any modded M57SLI with a chip greater than 512kB has this problem. I
> >> tried every possible undocumented workaround to no avail, and contacted
> >> ITE with no response.
> >>     
> >
> > There is a patch by Ronald Hoogeboom with a workaround, which allows booting
> > from larger rom chips:
> >
> >   http://article.gmane.org/gmane.linux.bios/33492
> >
> > I'd still like to put it in the tree.
> >   
> 
> I'm no longer opposing to put this in v2 (v2 is already complicated and
> support for this will make it worse), but I shall make very sure that we
> use a clean solution in v3.

I agree! Will test again and commit for v2.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From klaus.stammermann at ibnoetzold.de  Mon Aug  4 16:07:29 2008
From: klaus.stammermann at ibnoetzold.de (Klaus Stammermann)
Date: Mon, 4 Aug 2008 16:07:29 +0200 (CEST)
Subject: [coreboot] Problems with newer revision
Message-ID: <44776.87.122.15.241.1217858849.squirrel@www.ibnoetzold.de>

Hi

I tried to use coreboot on VIA EPIA ME6000G. With revision 2184 system
starts but with newest revision there are some problems.

Because of changing path to repository in past a diff on my sandbox
doesn't work. Could anyone explain why there are changes so my board
starts only with an old revision?

I know you can't test new revisions with all boards, but there where about
1300 new one. Does no one use this board or is there no development for
ME6000G anymore?

Some information would be nice to see what I am going to do on my project.

Greetings
Klaus



From peter at stuge.se  Mon Aug  4 17:12:02 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Aug 2008 17:12:02 +0200
Subject: [coreboot] Problems with newer revision
In-Reply-To: <44776.87.122.15.241.1217858849.squirrel@www.ibnoetzold.de>
References: <44776.87.122.15.241.1217858849.squirrel@www.ibnoetzold.de>
Message-ID: <20080804151202.16936.qmail@stuge.se>

Hi Klaus,

On Mon, Aug 04, 2008 at 04:07:29PM +0200, Klaus Stammermann wrote:
> I tried to use coreboot on VIA EPIA ME6000G. With revision 2184
> system starts but with newest revision there are some problems.

What problems?


> I know you can't test new revisions with all boards,

Actually there is infrastructure to do just that, but it's not super
easy to integrate with yet.


> but there where about 1300 new one. Does no one use this board or
> is there no development for ME6000G anymore?

I think both those statements are true. It's a rather old board. I
had an EPIA-MII, but the caps blew and I haven't been able to source
new ones easily enough.


> Some information would be nice to see what I am going to do on my
> project.

I'm sorry, but I'm not sure what the problem is. Maybe it's
acceptable for you to keep using the old revision? If not you'll of
course have to rebase your local patch and help find the problem with
newer revs on the board. Could you send your changes to the mailing
list?

And - what if any output do you get from running newer revisions on
your board?

//Peter



From rminnich at gmail.com  Mon Aug  4 17:24:28 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 08:24:28 -0700
Subject: [coreboot] Problems with newer revision
In-Reply-To: <44776.87.122.15.241.1217858849.squirrel@www.ibnoetzold.de>
References: <44776.87.122.15.241.1217858849.squirrel@www.ibnoetzold.de>
Message-ID: <13426df10808040824r15b18be1t80ce7ffc4420236@mail.gmail.com>

On Mon, Aug 4, 2008 at 7:07 AM, Klaus Stammermann
<klaus.stammermann at ibnoetzold.de> wrote:
> Hi
>
> I tried to use coreboot on VIA EPIA ME6000G. With revision 2184 system
> starts but with newest revision there are some problems.
>
> Because of changing path to repository in past a diff on my sandbox
> doesn't work. Could anyone explain why there are changes so my board
> starts only with an old revision?
>
> I know you can't test new revisions with all boards, but there where about
> 1300 new one. Does no one use this board or is there no development for
> ME6000G anymore?


unless you have a need for a new rev on an old board, just stick with
the old rev. It's not possible to keep all new revs compatible with
all old boards. Sometimes a chipset bug requires a fix on a new board
that breaks an old board and there is no way to verify the breakage.

ron



From svn at coreboot.org  Mon Aug  4 17:40:45 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 17:40:45 +0200
Subject: [coreboot] r3469 - in trunk/coreboot-v2: src/mainboard/asi
	src/mainboard/asi/mb_5blgp targets/asi targets/asi/mb_5blgp
Message-ID: <mailman.1776.1355071350.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-08-04 17:40:45 +0200 (Mon, 04 Aug 2008)
New Revision: 3469

Added:
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c
   trunk/coreboot-v2/targets/asi/mb_5blgp/
   trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb
Log:
Initial support for the ASI MB-5BLGP (Neoware Eon 4000s).

This works fine in Linux if you use the 'irqpoll' kernel command
line option.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb	2008-08-04 15:40:45 UTC (rev 3469)
@@ -0,0 +1,137 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+	default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+	default ROM_SECTION_OFFSET = 0
+end
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
+				    + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE
+	object irq_tables.o
+end
+makerule ./failover.E
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
+	depends	"$(MAINBOARD)/auto.c ./romcc"
+	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	depends "$(MAINBOARD)/auto.c ./romcc"
+	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/amd/model_gx1/cpu_setup.inc
+mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit ./auto.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 0f.0 on end		# Ethernet
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc87351	# Super I/O
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.2 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.e on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.4 on		# System wake-up control (SWC)
+            irq 0x60 = 0x500
+          end
+          device pnp 2e.5 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.6 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.7 on		# GPIO
+            irq 0x60 = 0x800
+          end
+          device pnp 2e.8 on		# Fan speed control
+            irq 0x60 = 0x900
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "0"	# No connector on this board
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	2008-08-04 15:40:45 UTC (rev 3469)
@@ -0,0 +1,105 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_VIDEO_MB
+uses CONFIG_SPLASH_GRAPHIC
+uses CONFIG_GX1_VIDEO
+uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
+
+## Enable VGA with a splash screen (only 640x480 to run on most monitors).
+## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
+## Note: Higher resolutions might need faster SDRAM speed.
+default CONFIG_GX1_VIDEO = 1
+default CONFIG_GX1_VIDEOMODE = 0
+default CONFIG_SPLASH_GRAPHIC = 1
+default CONFIG_VIDEO_MB = 2
+
+default ROM_SIZE = 256 * 1024
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default PIRQ_ROUTE = 1
+default HAVE_FALLBACK_BOOT = 1
+default HAVE_MP_TABLE = 0
+default HAVE_HARD_RESET = 0
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default HAVE_OPTION_TABLE = 0
+default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 16 * 1024
+default USE_OPTION_TABLE = 0
+default _RAMBASE = 0x00004000
+default CONFIG_ROM_PAYLOAD = 1
+default CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc "
+default HOSTCC = "gcc"
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default TTYS0_BAUD = 115200
+default TTYS0_BASE = 0x3f8
+default TTYS0_LCS = 0x3		# 8n1
+default DEFAULT_CONSOLE_LOGLEVEL = 9
+default MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+end

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c	2008-08-04 15:40:45 UTC (rev 3469)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/amd/gx1/raminit.c"
+#include "cpu/x86/bist.h"
+#include "superio/nsc/pc87351/pc87351_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
+
+static void main(unsigned long bist)
+{
+	pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	uart_init();
+	console_init();
+	report_bist_failure(bist);
+	sdram_init();
+	/* ram_check(0, 640 * 1024); */
+}

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/chip.h	2008-08-04 15:40:45 UTC (rev 3469)
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_asi_mb_5blgp_ops;
+struct mainboard_asi_mb_5blgp_config {};

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c	2008-08-04 15:40:45 UTC (rev 3469)
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x12 << 3) | 0x0,	/* Interrupt router device */
+	0x8800,			/* IRQs devoted exclusively to PCI usage */
+	0x1078,			/* Vendor */
+	0x2,			/* Device */
+	0,			/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x96,			/* Checksum */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */
+		{0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */
+		{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/mainboard.c	2008-08-04 15:40:45 UTC (rev 3469)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_asi_mb_5blgp_ops = {
+	CHIP_NAME("ASI MB-5BLGP Mainboard")
+};

Added: trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/targets/asi/mb_5blgp/Config.lb	2008-08-04 15:40:45 UTC (rev 3469)
@@ -0,0 +1,54 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target mb_5blgp
+mainboard asi/mb_5blgp
+
+option ROM_SIZE = 256 * 1024
+
+option MAINBOARD_VENDOR = "ASI"
+option MAINBOARD_PART_NUMBER = "MB-5BLGP"
+
+option IRQ_SLOT_COUNT = 3
+
+## Enable VGA with a splash screen (only 640x480 to run on most monitors).
+## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
+## Note: Higher resolutions might need faster SDRAM speed.
+option CONFIG_GX1_VIDEO = 1
+option CONFIG_GX1_VIDEOMODE = 0
+option CONFIG_SPLASH_GRAPHIC = 1
+option CONFIG_VIDEO_MB = 2
+
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE = 0
+	option COREBOOT_EXTRA_VERSION = ".0Normal"
+	payload ../payload.elf
+end
+
+romimage "fallback"
+	option USE_FALLBACK_IMAGE = 1
+	option COREBOOT_EXTRA_VERSION = ".0Fallback"
+	payload ../payload.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"




From uwe at hermann-uwe.de  Mon Aug  4 17:42:23 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 4 Aug 2008 17:42:23 +0200
Subject: [coreboot] [PATCH] Support for the ASI MB-5BLGP (Neoware
	Eon	4000s)
In-Reply-To: <48961F32.2060506@gmx.net>
References: <20080710115531.GC23984@greenwood>
	<20080803205758.GE6389@greenwood> <48961F32.2060506@gmx.net>
Message-ID: <20080804154221.GA21502@greenwood>

On Sun, Aug 03, 2008 at 11:12:18PM +0200, Carl-Daniel Hailfinger wrote:
> If you fix the typo in the commit message (InitiaL):
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Thanks, r3469.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Mon Aug  4 18:01:20 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 09:01:20 -0700
Subject: [coreboot] patch: resource map proposal.
Message-ID: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>

This is a possible mod to change the way resource maps are done.

Unify the big mess into a little mess.
This code has all the functionality of the 4 or 5 rmap functions from v2 ..

This includes my proposed pci config patch.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
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From peter at stuge.se  Mon Aug  4 18:40:54 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Aug 2008 18:40:54 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
Message-ID: <20080804164054.8397.qmail@stuge.se>

On Mon, Aug 04, 2008 at 09:01:20AM -0700, ron minnich wrote:
> This is a possible mod to change the way resource maps are done. 
> 
> Unify the big mess into a little mess. 
> This code has all the functionality of the 4 or 5 rmap functions from v2 ..

Awesome. But..


> +void setup_resource_map_x_offset(const rmap *rm, u32 max,
> +                                 u32 offset_dev, u32 offset_pciio, 
> +                                 u32 offset_io)
> +{
> +	u32 i;
> +
> +	printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
> +
> +	for(i = 0; i < max; i++, rm++) {
> +          switch (rm->type){
> +		case PCIRM: 
> +			{
> +                          u32 dev;
> +                          unsigned where;
> +                          unsigned long reg;
> +			  printk(BIOS_DEBUG, "(%x,%x+%x,%x,%x) & %08x | %08x+%08x\n", r->pcm.bus,r->pcm.dev+offset_dev,
> +                                 r->pcm.fn,r->pcm.reg,
> +				 r->pcm.and,r->pcm.or, offset_pciio);

This will not build. r is undeclared. :) When fixed,

Acked-by: Peter Stuge <peter at stuge.se>


//Peter



From Marc.Jones at amd.com  Mon Aug  4 19:00:32 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Mon, 4 Aug 2008 11:00:32 -0600
Subject: [coreboot] Fam10h support for Tyan S2912-E
In-Reply-To: <kjmvdyhug78.fsf@pelargir.dolphinics.no>
References: <kjmvdyhug78.fsf@pelargir.dolphinics.no>
Message-ID: <489735B0.2000701@amd.com>

Arne Georg Gleditsch wrote:
> Hi,
> 
> I have a S2912 system that I'd like to run coreboot on.  As I understand
> it, both the S2912 and Fam10h is supported seperately, but some porting
> is required to make the combination work.  I'd like to work on getting
> this configuration operational.  If anyone has any pointers on how to
> tackle it, that would be more than welcome.
> 
> Thanks in advance,
> 

Hi Arne,

If you are prepared to do firmware development (socketed ROM, etc) the 
port should not be too difficult. The amd/serengeti_cheetah_fam10 
mainboard should be a good example to work from. It is helpful if you 
have access to motherboard and chipset documents.

Marc



-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors




From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 19:27:05 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 19:27:05 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
Message-ID: <48973BE9.9070104@gmx.net>

On 04.08.2008 18:01, ron minnich wrote:
> This is a possible mod to change the way resource maps are done.
>
> Unify the big mess into a little mess.
> This code has all the functionality of the 4 or 5 rmap functions from v2 ..
>
> This includes my proposed pci config patch.
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   

Can you hold off committing a bit? I think I can come up with a cleaner
alternative to the pci config patch (hopefully without any code changes).

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Mon Aug  4 19:32:05 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Aug 2008 19:32:05 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <48973BE9.9070104@gmx.net>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net>
Message-ID: <20080804173205.23196.qmail@stuge.se>

On Mon, Aug 04, 2008 at 07:27:05PM +0200, Carl-Daniel Hailfinger wrote:
> > This includes my proposed pci config patch.
> 
> Can you hold off committing a bit? I think I can come up with a
> cleaner alternative to the pci config patch (hopefully without any
> code changes).

Please stop creating wait states.

Apply Ron's patch to your local tree, work there, then send a patch
to apply on top of Ron's commit.


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 19:50:32 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 19:50:32 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <20080804173205.23196.qmail@stuge.se>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>	<48973BE9.9070104@gmx.net>
	<20080804173205.23196.qmail@stuge.se>
Message-ID: <48974168.3040507@gmx.net>

On 04.08.2008 19:32, Peter Stuge wrote:
> On Mon, Aug 04, 2008 at 07:27:05PM +0200, Carl-Daniel Hailfinger wrote:
>   
>>> This includes my proposed pci config patch.
>>>       
>> Can you hold off committing a bit? I think I can come up with a
>> cleaner alternative to the pci config patch (hopefully without any
>> code changes).
>>     
>
> Please stop creating wait states.
>
> Apply Ron's patch to your local tree, work there, then send a patch
> to apply on top of Ron's commit.
>   

If I'm successful, I'll be undoing 50% of Ron's patch.

-	pci_write_config32(a, b, c);
+	pci_cf8_conf1.write32(NULL, 0, a, b, c);

Can't we just use a macro for that stuff?
#define PCI_WRITE_CONFIG32_EARLY(a,b,c) pci_cf8_conf1.write32(NULL, 0, a, b, c);


Do this, and 50% of Ron's changes are obsolete.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Mon Aug  4 19:56:03 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Aug 2008 19:56:03 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <48974168.3040507@gmx.net>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net> <20080804173205.23196.qmail@stuge.se>
	<48974168.3040507@gmx.net>
Message-ID: <20080804175603.30768.qmail@stuge.se>

On Mon, Aug 04, 2008 at 07:50:32PM +0200, Carl-Daniel Hailfinger wrote:
> > a patch to apply on top of Ron's commit.
> 
> If I'm successful, I'll be undoing 50% of Ron's patch.

That doesn't matter. This is early work in progress.
Key word: progress


> -	pci_write_config32(a, b, c);
> +	pci_cf8_conf1.write32(NULL, 0, a, b, c);
> 
> Can't we just use a macro for that stuff?
> #define PCI_WRITE_CONFIG32_EARLY(a,b,c) pci_cf8_conf1.write32(NULL, 0, a, b, c);

Sorry, I don't see the point. I expect pci_cf8_* to change at least
once anyway. I think time is better spent elsewhere.


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 20:11:39 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 20:11:39 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <20080804175603.30768.qmail@stuge.se>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>	<48973BE9.9070104@gmx.net>
	<20080804173205.23196.qmail@stuge.se>	<48974168.3040507@gmx.net>
	<20080804175603.30768.qmail@stuge.se>
Message-ID: <4897465B.9010309@gmx.net>

On 04.08.2008 19:56, Peter Stuge wrote:
> On Mon, Aug 04, 2008 at 07:50:32PM +0200, Carl-Daniel Hailfinger wrote:
>   
>>> a patch to apply on top of Ron's commit.
>>>       
>> If I'm successful, I'll be undoing 50% of Ron's patch.
>>     
>
> That doesn't matter. This is early work in progress.
> Key word: progress
>   

If something has to be rolled back, it's the opposite of progress.


>> -	pci_write_config32(a, b, c);
>> +	pci_cf8_conf1.write32(NULL, 0, a, b, c);
>>
>> Can't we just use a macro for that stuff?
>> #define PCI_WRITE_CONFIG32_EARLY(a,b,c) pci_cf8_conf1.write32(NULL, 0, a, b, c);
>>     
>
> Sorry, I don't see the point. I expect pci_cf8_* to change at least
> once anyway. I think time is better spent elsewhere.
>   

That's why I don't want it committed in the first place. The least
intrusive change would be the following #define at the beginning of each
affected C file:

> #define pci_write_config32(a,b,c) pci_cf8_conf1.write32(NULL, 0, a, b, c);
>   


No other code changes needed. It reduces code churn and keeps the
familiar interface. With that change, I see no reason to hold the commit
back.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Mon Aug  4 20:27:27 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 11:27:27 -0700
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <4897465B.9010309@gmx.net>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net> <20080804173205.23196.qmail@stuge.se>
	<48974168.3040507@gmx.net> <20080804175603.30768.qmail@stuge.se>
	<4897465B.9010309@gmx.net>
Message-ID: <13426df10808041127w3b5bf512h90fba065a43f907f@mail.gmail.com>

On Mon, Aug 4, 2008 at 11:11 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

>> #define pci_write_config32(a,b,c) pci_cf8_conf1.write32(NULL, 0, a, b, c);


Yeah I can do that. I think it is more confusing but I'm not picky.
I'd rather see the raw form as a reminder.

But if the other form is preferred it takes me about 2 seconds to change :-)



ron



From stepan at coresystems.de  Mon Aug  4 20:36:27 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 04 Aug 2008 20:36:27 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <4897465B.9010309@gmx.net>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>	<48973BE9.9070104@gmx.net>	<20080804173205.23196.qmail@stuge.se>	<48974168.3040507@gmx.net>	<20080804175603.30768.qmail@stuge.se>
	<4897465B.9010309@gmx.net>
Message-ID: <48974C2B.7040704@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 04.08.2008 19:56, Peter Stuge wrote:
>   
>
> Please stop creating wait states.
> Apply Ron's patch to your local tree, work there, then send a patch
> to apply on top of Ron's commit.
>> On Mon, Aug 04, 2008 at 07:50:32PM +0200, Carl-Daniel Hailfinger wrote:
>>   
>>     
>>>> a patch to apply on top of Ron's commit.
>>>>       
>>>>         
>>> If I'm successful, I'll be undoing 50% of Ron's patch.
>>>     
>>>       
>> That doesn't matter. This is early work in progress.
>> Key word: progress
>>   
>>     
>
> If something has to be rolled back, it's the opposite of progress.
>
>   
More so are endless discussions of what could happen if one had more 
time. In fact, they're the reason we do not have a reasonably working 
version of v3 yet.


Stefan



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From stepan at coresystems.de  Mon Aug  4 20:44:28 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 04 Aug 2008 20:44:28 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
Message-ID: <48974E0C.4070903@coresystems.de>

ron minnich wrote:
> This is a possible mod to change the way resource maps are done.
>
> Unify the big mess into a little mess.
> This code has all the functionality of the 4 or 5 rmap functions from v2 ..
>
> This includes my proposed pci config patch.
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   

I don't understand the patch. Why does having a single function for 
"resource maps" require pci_read_configXY to be renamed? And how does 
that reduce the mess?

-	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	nbcap = pci_cf8_conf1.read32(NULL, 0, ctrl->f3, NORTHBRIDGE_CAP);
+	dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);


I never saw a conf2 system since 1994, so putting this in the name is an 
anachronism. No conf2 system could ever work anyways without 
signigicantly changing the code.





-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From peter at stuge.se  Mon Aug  4 21:06:55 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 4 Aug 2008 21:06:55 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <48974E0C.4070903@coresystems.de>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48974E0C.4070903@coresystems.de>
Message-ID: <20080804190655.18050.qmail@stuge.se>

On Mon, Aug 04, 2008 at 08:44:28PM +0200, Stefan Reinauer wrote:
> I don't understand the patch. Why does having a single function for
> "resource maps" require pci_read_configXY to be renamed?

These are two unrelated changes. I don't think that matters so much
right now.


//Peter
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From uwe at hermann-uwe.de  Mon Aug  4 21:36:24 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 4 Aug 2008 21:36:24 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <20080804175603.30768.qmail@stuge.se>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net> <20080804173205.23196.qmail@stuge.se>
	<48974168.3040507@gmx.net> <20080804175603.30768.qmail@stuge.se>
Message-ID: <20080804193624.GB21502@greenwood>

On Mon, Aug 04, 2008 at 07:56:03PM +0200, Peter Stuge wrote:
> On Mon, Aug 04, 2008 at 07:50:32PM +0200, Carl-Daniel Hailfinger wrote:
> > > a patch to apply on top of Ron's commit.
> > 
> > If I'm successful, I'll be undoing 50% of Ron's patch.
> 
> That doesn't matter. This is early work in progress.
> Key word: progress

Doesn't mean we have to commit everything right away though, too. A
certain amount of time for reviews and discussions before committing
anything is needed and a good idea (doesn't have to be weeks, but at
least a few hours or a day or so shouldn't be a problem).

(I'm not commenting on this specific patch or technical issue, but I
cannot agree with the general idea of "no delays, commit everything ASAP
no matter what").


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From jordan.crouse at amd.com  Mon Aug  4 21:46:41 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Mon, 4 Aug 2008 13:46:41 -0600
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <20080804193624.GB21502@greenwood>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net> <20080804173205.23196.qmail@stuge.se>
	<48974168.3040507@gmx.net> <20080804175603.30768.qmail@stuge.se>
	<20080804193624.GB21502@greenwood>
Message-ID: <20080804194641.GD6674@cosmic.amd.com>

On 04/08/08 21:36 +0200, Uwe Hermann wrote:
> On Mon, Aug 04, 2008 at 07:56:03PM +0200, Peter Stuge wrote:
> > On Mon, Aug 04, 2008 at 07:50:32PM +0200, Carl-Daniel Hailfinger wrote:
> > > > a patch to apply on top of Ron's commit.
> > > 
> > > If I'm successful, I'll be undoing 50% of Ron's patch.
> > 
> > That doesn't matter. This is early work in progress.
> > Key word: progress
> 
> Doesn't mean we have to commit everything right away though, too. A
> certain amount of time for reviews and discussions before committing
> anything is needed and a good idea (doesn't have to be weeks, but at
> least a few hours or a day or so shouldn't be a problem).
> 
> (I'm not commenting on this specific patch or technical issue, but I
> cannot agree with the general idea of "no delays, commit everything ASAP
> no matter what").

We need to find the middle ground.  Development doesn't have to stop 
for everybody to give the patch a checkmark.  We do _not_ need to be
on the same page for the project to proceed.  Discussion is good,
but not mandatory.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From svn at coreboot.org  Mon Aug  4 22:19:53 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 22:19:53 +0200
Subject: [coreboot] r50 - in trunk/filo-0.5: i386 main
Message-ID: <mailman.1777.1355071350.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-04 22:19:53 +0200 (Mon, 04 Aug 2008)
New Revision: 50

Modified:
   trunk/filo-0.5/i386/linux_load.c
   trunk/filo-0.5/main/elfload.c
Log:
see what's lying around in my old filo tree... Clear out Epia-M PCMCIA
registers so Linux can properly use the onboard CF as a hot plug disk instead
of IDE emulation.


Modified: trunk/filo-0.5/i386/linux_load.c
===================================================================
--- trunk/filo-0.5/i386/linux_load.c	2008-06-22 01:53:33 UTC (rev 49)
+++ trunk/filo-0.5/i386/linux_load.c	2008-08-04 20:19:53 UTC (rev 50)
@@ -15,6 +15,9 @@
 #include <arch/stdint.h>
 #include "context.h"
 #include "segment.h"
+#ifdef PCMCIA_CF
+#include <pci.h>
+#endif
 
 #define DEBUG_THIS DEBUG_LINUXLOAD
 #include <debug.h>
@@ -568,6 +571,10 @@
 #ifdef VGA_CONSOLE
     extern int cursor_x, cursor_y;
 #endif
+#ifdef PCMCIA_CF
+    uint32_t cf_bar;
+    int i;
+#endif
 
     ctx = init_context(phys_to_virt(STACK_LOC), 4096, 0);
 
@@ -607,7 +614,12 @@
     params->orig_x = cursor_x;
     params->orig_y = cursor_y;
 #endif
-    
+#ifdef PCMCIA_CF
+    cf_bar = phys_to_virt(pci_read32(PCI_ADDR(0, 0xa, 1)));
+    for( i = 0x836 ; i < 0x840 ; i++){
+        *(unsigned char *)(cf_bar+i) = 0;
+    }
+#endif
     /* Go... */
     ctx = switch_to(ctx);
 

Modified: trunk/filo-0.5/main/elfload.c
===================================================================
--- trunk/filo-0.5/main/elfload.c	2008-06-22 01:53:33 UTC (rev 49)
+++ trunk/filo-0.5/main/elfload.c	2008-08-04 20:19:53 UTC (rev 50)
@@ -12,6 +12,9 @@
 #include <sys_info.h>
 #include <ipchecksum.h>
 #include <fs.h>
+#ifdef PCMCIA_CF
+#include <pci.h>
+#endif
 #define DEBUG_THIS DEBUG_ELFBOOT
 #include <debug.h>
 
@@ -284,6 +287,10 @@
     Elf_Bhdr *boot_notes = NULL;
     int retval = -1;
     int image_retval;
+#ifdef PCMCIA_CF
+    uint32_t cf_bar;
+    int i;
+#endif
 
     image_name = image_version = 0;
 
@@ -340,6 +347,13 @@
 
     boot_notes = build_boot_notes(info, cmdline);
 
+#if PCMCIA_CF
+    cf_bar = phys_to_virt(pci_read32(PCI_ADDR(0, 0xa, 1)));
+    for( i = 0x836 ; i < 0x840 ; i++){
+        *(unsigned char *)(cf_bar+i) = 0;
+    }
+#endif
+
     debug("current time: %lu\n", currticks());
 
     debug("entry point is %#x\n", ehdr.e_entry);




From rminnich at gmail.com  Mon Aug  4 22:20:48 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 13:20:48 -0700
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <48974E0C.4070903@coresystems.de>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48974E0C.4070903@coresystems.de>
Message-ID: <13426df10808041320i766d46c0i93e856dcade25420@mail.gmail.com>

let's take it in two pieces.

Everyone ok with the resource map patch? It's pretty simple.

second piece.

On Mon, Aug 4, 2008 at 11:44 AM, Stefan Reinauer <stepan at coresystems.de> wrote:

> I don't understand the patch. Why does having a single function for
> "resource maps" require pci_read_configXY to be renamed? And how does that
> reduce the mess?

The resource map and the configXY are totally unrelated.

romcc-based code used to have:
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);

This worked in v2 due to abuse of cpp and a few other bits. I was
never comfortable with it -- more magic than I like. in romcc and CAR
code, a device_t was a u32; in other code, it was a struct device *.
icky.

In v3 pci_read_config32 takes a struct device *. We don't have them in
stage 1. So to make this work, I do this:

nbcap = pci_cf8_conf1.read32(NULL, 0, ctrl->f3, NORTHBRIDGE_CAP);

Which will work fine.

I'm not that concerned with syntactic sugar to cover this up, such as
the define at front. I'm actually *more* comfortable with this, since
it makes it
very clear what's going on. Nobody will come along later and get confused.


> I never saw a conf2 system since 1994, so putting this in the name is an
> anachronism. No conf2 system could ever work anyways without signigicantly
> changing the code.

I did not pick the name, it's the name of the struct with the function
pointers.

I've got an ack from peter and I'd like to commit. Yes these are two
patches but --key point -- they'll work and we can keep going.

Thanks

ron



From stepan at coresystems.de  Mon Aug  4 22:40:15 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 04 Aug 2008 22:40:15 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808041320i766d46c0i93e856dcade25420@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>	<48974E0C.4070903@coresystems.de>
	<13426df10808041320i766d46c0i93e856dcade25420@mail.gmail.com>
Message-ID: <4897692F.1080201@coresystems.de>

ron minnich wrote:
> romcc-based code used to have:
> nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
>
> This worked in v2 due to abuse of cpp and a few other bits.
I think that was very elegant actually, given the assumption that we 
need a device_t (I still like that better than struct device) to do a 
simple pci config read/write,... but...
> I was
> never comfortable with it -- more magic than I like. in romcc and CAR
> code, a device_t was a u32; in other code, it was a struct device *.
> icky.
>
> In v3 pci_read_config32 takes a struct device *. We don't have them in
> stage 1. So to make this work, I do this:
>
> nbcap = pci_cf8_conf1.read32(NULL, 0, ctrl->f3, NORTHBRIDGE_CAP);
>
> Which will work fine.
>   
The obvious question: Do we need to use device_t as an input to that 
function at all? Why don't we instead use simple pci functions taking a 
u32 as an input? We're a bios, after all, not an OS. Are we?

> I did not pick the name, it's the name of the struct with the function
> pointers.
>
> I've got an ack from peter and I'd like to commit. Yes these are two
> patches but --key point -- they'll work and we can keep going.
>   
Sure, keep going. I'll wait and see what comes out of this in the end.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From rminnich at gmail.com  Mon Aug  4 22:49:07 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 13:49:07 -0700
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <4897692F.1080201@coresystems.de>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48974E0C.4070903@coresystems.de>
	<13426df10808041320i766d46c0i93e856dcade25420@mail.gmail.com>
	<4897692F.1080201@coresystems.de>
Message-ID: <13426df10808041349o314a7cc0ie7da689e2f3dfff9@mail.gmail.com>

On Mon, Aug 4, 2008 at 1:40 PM, Stefan Reinauer <stepan at coresystems.de> wrote:

> The obvious question: Do we need to use device_t as an input to that
> function at all? Why don't we instead use simple pci functions taking a u32
> as an input? We're a bios, after all, not an OS. Are we?

That's a fine question. The convention could be that we call those
functions as follows:
blahblah(device->bus, device->devfn, etc. etc. )

works for me. But let's revisit it later.

I am fine with overloading but only in languages that really allow it ;-)

ron



From c-d.hailfinger.devel.2006 at gmx.net  Mon Aug  4 22:50:50 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 Aug 2008 22:50:50 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808041127w3b5bf512h90fba065a43f907f@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>	<48973BE9.9070104@gmx.net>
	<20080804173205.23196.qmail@stuge.se>	<48974168.3040507@gmx.net>
	<20080804175603.30768.qmail@stuge.se>	<4897465B.9010309@gmx.net>
	<13426df10808041127w3b5bf512h90fba065a43f907f@mail.gmail.com>
Message-ID: <48976BAA.9040304@gmx.net>

On 04.08.2008 20:27, ron minnich wrote:
> On Mon, Aug 4, 2008 at 11:11 AM, Carl-Daniel Hailfinger wrote:
>
>   
>>> #define pci_write_config32(a,b,c) pci_cf8_conf1.write32(NULL, 0, a, b, c);
>>>       
>
> Yeah I can do that. I think it is more confusing but I'm not picky.
> I'd rather see the raw form as a reminder.
>   

I can't argue with that one.

> But if the other form is preferred it takes me about 2 seconds to change :-)
>   

Peter already gave you an Ack for the patch (see his comment about
compilation, though).
If you remove the pci_write_config part of the patch and/or replace it
with a macro, the patch is also
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

I do have some minor comments, but feel free to commit without
addressing them. Cut-and-paste reduced to the areas I want to comment on.

> +/**
> + * setup a resource map. 
> + * for PCRM entries, add a pci device offset, and a pci "OR value offset"
>   

"for PCIRM entries,..."
"OR value offset is not entirely clear.


> + * for IO8 and IO32 entries, add an io base offset. 
> + * This function combines a bunch of seperate functions that were scattered
> + * throughout v2. It may be awkward but it does allow for one rmap for 
> + * all settings, which is handy. See include/arch/x86/cpu.h for usage on 
> + * how to set up a resource map. 
> + *
> + * @param rm The resource map
> + * @param max The map size
> + * @param offset_dev pci device offset. This can be useful on e.g. k8
> + *        we have a number of similar devices which need the same setups
> + *        we can use one map for more than one device. NOTE: 
> + *        offset_dev IS NOT ASSUMED TO BE OFFSET BY FN (i.e. it is not << 3)
>   

* offset_dev IS NOT ASSUMED TO BE SHIFTED BY FN (i.e. it is not << 3)


> + * @param offset_pciio added to the OR value for setting up PCI IO
> + * @param offset_io offset from the io base in the resource map
> + */
> +
> +void setup_resource_map_x_offset(const rmap *rm, u32 max,
> +                                 u32 offset_dev, u32 offset_pciio, 
> +                                 u32 offset_io)
>   

I had some trouble understanding the comments, but after rereading them
they look pretty ok.

> /* pci config map */
> struct pcm

struct pcicm would be a bit more readable.

> struct io8

Maybe struct io8_modify or struct io8_change? Not urgent.

> /* convenience initializer */
> #define PCM(abus,adev,afn,areg,aand,aor) {.type = PCIRM, {.pcm ={.bus=abus,.dev=adev,.fn=afn,.reg=areg,.and=aand,.or=aor}}}
> #define EIO8(aport, aand, aor) {.type=IO8, {.io8 = {.port = aport, .and = aand, .or = aor}}}
> #define EIO32(aport, aand, aaor) {.type = IO32, {.io32 = {.port = aport, .and = aand, .or = aor}}}

Consistent naming, please. If "E" stands for initializer, please use
EPCIRM instead of PCM.

Overall, I like the patch and want to see it in the tree. Your work is
very valuable. I hope you didn't get the impression that I want to stall
you.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Mon Aug  4 22:54:31 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 04 Aug 2008 22:54:31 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808041349o314a7cc0ie7da689e2f3dfff9@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>	
	<48974E0C.4070903@coresystems.de>	
	<13426df10808041320i766d46c0i93e856dcade25420@mail.gmail.com>	
	<4897692F.1080201@coresystems.de>
	<13426df10808041349o314a7cc0ie7da689e2f3dfff9@mail.gmail.com>
Message-ID: <48976C87.3020501@coresystems.de>

ron minnich wrote:
> On Mon, Aug 4, 2008 at 1:40 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
>
>   
>> The obvious question: Do we need to use device_t as an input to that
>> function at all? Why don't we instead use simple pci functions taking a u32
>> as an input? We're a bios, after all, not an OS. Are we?
>>     
>
> That's a fine question. The convention could be that we call those
> functions as follows:
> blahblah(device->bus, device->devfn, etc. etc. )
>   

pci_read_config32(PCI_DEV(0,0x1f,0), reg); ?

Maps to about 5 assembler instructions.
> works for me. But let's revisit it later.
>
> I am fine with overloading but only in languages that really allow it ;-)
Overloading? I'm talking about simplifying, not inventing an OS ;-)


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From rminnich at gmail.com  Mon Aug  4 22:55:23 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 13:55:23 -0700
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <48976BAA.9040304@gmx.net>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net> <20080804173205.23196.qmail@stuge.se>
	<48974168.3040507@gmx.net> <20080804175603.30768.qmail@stuge.se>
	<4897465B.9010309@gmx.net>
	<13426df10808041127w3b5bf512h90fba065a43f907f@mail.gmail.com>
	<48976BAA.9040304@gmx.net>
Message-ID: <13426df10808041355v6a421077g5e3db82697006b6@mail.gmail.com>

On Mon, Aug 4, 2008 at 1:50 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Overall, I like the patch and want to see it in the tree. Your work is
> very valuable. I hope you didn't get the impression that I want to stall
> you.
>

not at all!

thanks

ron



From svn at coreboot.org  Mon Aug  4 23:00:49 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 23:00:49 +0200
Subject: [coreboot] r3470 - trunk/payloads/libpayload/include
Message-ID: <mailman.1778.1355071350.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-08-04 23:00:49 +0200 (Mon, 04 Aug 2008)
New Revision: 3470

Modified:
   trunk/payloads/libpayload/include/libpayload.h
Log:
Add missing #include.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/payloads/libpayload/include/libpayload.h
===================================================================
--- trunk/payloads/libpayload/include/libpayload.h	2008-08-04 15:40:45 UTC (rev 3469)
+++ trunk/payloads/libpayload/include/libpayload.h	2008-08-04 21:00:49 UTC (rev 3470)
@@ -37,6 +37,7 @@
 #include <sysinfo.h>
 #include <stdarg.h>
 #include <lar.h>
+#include <pci.h>
 
 #define MIN(a,b) ((a) < (b) ? (a) : (b))
 #define MAX(a,b) ((a) > (b) ? (a) : (b))




From svn at coreboot.org  Mon Aug  4 23:02:07 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 23:02:07 +0200
Subject: [coreboot] r3471 - trunk/payloads/coreinfo
Message-ID: <mailman.1779.1355071350.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-08-04 23:02:07 +0200 (Mon, 04 Aug 2008)
New Revision: 3471

Modified:
   trunk/payloads/coreinfo/pci_module.c
Log:
Remove duplicated code which is already in libpayload (trivial).
Build-tested against the latest libpayload.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/payloads/coreinfo/pci_module.c
===================================================================
--- trunk/payloads/coreinfo/pci_module.c	2008-08-04 21:00:49 UTC (rev 3470)
+++ trunk/payloads/coreinfo/pci_module.c	2008-08-04 21:02:07 UTC (rev 3471)
@@ -18,6 +18,7 @@
  */
 
 #include <arch/io.h>
+#include <libpayload.h>
 #include "coreinfo.h"
 
 #ifdef CONFIG_MODULE_PCI
@@ -30,17 +31,6 @@
 static struct pci_devices devices[64];
 static int devices_index;
 
-#define REG_VENDOR_ID   0x00
-#define REG_HEADER_TYPE 0x0e
-#define REG_PRIMARY_BUS 0x18
-
-#define HEADER_TYPE_NORMAL  0
-#define HEADER_TYPE_BRIDGE  1
-#define HEADER_TYPE_CARDBUS 2
-
-#define PCI_ADDR(_bus, _dev, _reg) \
-	(0x80000000 | (_bus << 16) | (_dev << 8) | (_reg & ~3))
-
 /* Number of entries to show in the list */
 #define MENU_VISIBLE 16
 
@@ -94,20 +84,6 @@
 	quicksort(&(list[index]), len - index);
 }
 
-static void pci_read_dword(unsigned int bus, unsigned int devfn,
-			   unsigned int reg, unsigned int *val)
-{
-	outl(PCI_ADDR(bus, devfn, reg), 0xcf8);
-	*val = inl(0xcfc);
-}
-
-static void pci_read_byte(unsigned int bus, unsigned int devfn,
-			  unsigned int reg, unsigned char *val)
-{
-	outl(PCI_ADDR(bus, devfn, reg), 0xcf8);
-	*val = inb(0xcfc + (reg & 3));
-}
-
 static void show_config_space(WINDOW *win, int row, int col, int index)
 {
 	unsigned char cspace[64];




From svn at coreboot.org  Mon Aug  4 23:13:36 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 23:13:36 +0200
Subject: [coreboot] r51 - in trunk/filo-0.5: drivers/flash fs i386 include
	main
Message-ID: <mailman.1780.1355071350.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-04 23:13:36 +0200 (Mon, 04 Aug 2008)
New Revision: 51

Modified:
   trunk/filo-0.5/drivers/flash/lxflash.c
   trunk/filo-0.5/drivers/flash/lxflash.h
   trunk/filo-0.5/fs/blockdev.c
   trunk/filo-0.5/fs/vfs.c
   trunk/filo-0.5/i386/artecboot.c
   trunk/filo-0.5/i386/ldscript
   trunk/filo-0.5/i386/linux_load.c
   trunk/filo-0.5/i386/switch.S
   trunk/filo-0.5/include/fs.h
   trunk/filo-0.5/main/elfload.c
Log:
merge from may 2008 artec branch.


Modified: trunk/filo-0.5/drivers/flash/lxflash.c
===================================================================
--- trunk/filo-0.5/drivers/flash/lxflash.c	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/drivers/flash/lxflash.c	2008-08-04 21:13:36 UTC (rev 51)
@@ -34,7 +34,7 @@
 
 static FLASH_INFO g_flashInfo;		// flash info structure
 static uint32_t	g_deviceID = 0;		// flash memory ID
-static uint32_t	g_chipID = 0;		// chip ID
+static int32_t	g_chipID = -1;		// chip ID
 static uint16_t	g_baseAddr = 0;		// port mapped controller IO base address
 
 static uint8_t g_eccTest[MAX_ECC_SIZE];	// used to retrieve/store ECC
@@ -44,6 +44,8 @@
 static uint8_t g_pageBuf[MAX_PAGE_SIZE];
 static uint8_t *g_pBBT=NULL;
 
+static msr_t g_orig_flsh;
+
 ////////////////////////////////////////////////////////////////////////////////
 // ECC structs and routines
 
@@ -518,71 +520,78 @@
 ////////////////////////////////////////////////////////////////////////////////
 // 
 
+int NAND_close(void)
+{
+	if (g_chipID >= 0)
+		wrmsr(MSR_DIVIL_LBAR_FLSH0 + g_chipID, g_orig_flsh);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// 
+
 int NAND_initChip(int chipNum)
 {
 	msr_t msr;
 
+	if (g_chipID == chipNum) return 0;
+	if (g_chipID != -1) NAND_close();
+	
 	memset(&g_flashInfo, 0, sizeof(g_flashInfo));
 
-	g_chipID = chipNum;
+	g_chipID = -1;
 
 	///////////////////////////////////////////////////////////////////////////////////
 	// init the MSR_DIVIL_BALL_OPTS register, enable flash mode
 	
 	msr = rdmsr(MSR_DIVIL_BALL_OPTS);
-	msr.lo &= ~PIN_OPT_IDE;
-	wrmsr(MSR_DIVIL_BALL_OPTS, msr);
-	msr = rdmsr(MSR_DIVIL_BALL_OPTS);
-	debug("MSR_DIVIL_BALL_OPTS = 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
+	
+	if (msr.lo & PIN_OPT_IDE) {
+		printf("NAND controller not enabled!\n");
+		return -1;
+	}
+	
 	///////////////////////////////////////////////////////////////////////////////////
-	// init the MSR_DIVIL_LBAR_FLSHx register, I/O mapped mode, set base address
+	// init the MSR_DIVIL_LBAR_FLSHx register, I/O mapped mode, set a hardcoded base address
+	// Later we restore initial state
 	
+	g_orig_flsh = rdmsr(MSR_DIVIL_LBAR_FLSH0 + chipNum);
+	if (!(g_orig_flsh.hi & NOR_NAND)) {
+		printf("CS%d set up for NOR, aborting!\n", chipNum);
+		return -1;
+	}
+	
 	msr.hi = SET_FLSH_HIGH;
 	msr.lo = SET_FLSH_LOW;
-	wrmsr(MSR_DIVIL_LBAR_FLSH0 + g_chipID, msr);
+	wrmsr(MSR_DIVIL_LBAR_FLSH0 + chipNum, msr);
 	g_baseAddr = SET_FLSH_LOW;	// set the IO base address
 
 	// read the register back
-	msr = rdmsr(MSR_DIVIL_LBAR_FLSH0 + g_chipID);
-	debug("MSR_DIVIL_LBAR_FLSH%d = 0x%08x 0x%08x\n", (int)g_chipID, msr.hi, msr.lo);
+	msr = rdmsr(MSR_DIVIL_LBAR_FLSH0 + chipNum);
+	debug("MSR_DIVIL_LBAR_FLSH%d = 0x%08x 0x%08x\n", (int)chipNum, msr.hi, msr.lo);
 
-	///////////////////////////////////////////////////////////////////////////////////
-	// init the MSR_NANDF_DATA NAND timing register
-
-	msr.hi = 0;
-	msr.lo = SET_NANDF_DATA_LOW;
-	wrmsr(MSR_NANDF_DATA, msr);
-
-	msr = rdmsr(MSR_NANDF_DATA);
-	debug("MSR_NANDF_DATA = 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
-	///////////////////////////////////////////////////////////////////////////////////
-	// init the MSR_NANDF_CTL NAND timing register
-
-	msr.hi = 0;
-	msr.lo = SET_NANDF_CTL_LOW;
-	wrmsr(MSR_NANDF_CTL, msr);
-
-	msr = rdmsr(MSR_NANDF_CTL);
-	debug("MSR_NANDF_CTL = 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
 	// read out flash chip ID
 	g_deviceID = NAND_readFlashID();
 	
 	switch(g_deviceID)	// allow only known flash chips
 	{
 	case SAMSUNG_NAND_64MB:
-	case SST_NAND_64MB:
-
+	case ST_NAND_64MB:
+		
 		g_flashInfo.numBlocks = 4096;
 		g_flashInfo.pagesPerBlock = 32;
 		g_flashInfo.dataBytesPerPage = 512;
 		g_flashInfo.flashType = FLASH_NAND;
 
 		break;
+
+	case ST_NAND_128MB:
+
+		g_flashInfo.numBlocks = 1024;
+		g_flashInfo.pagesPerBlock = 64;
+		g_flashInfo.dataBytesPerPage = 2048;
+		g_flashInfo.flashType = FLASH_NAND;
 		
-	case SST_NAND_512MB:
+	case ST_NAND_512MB:
 
 		g_flashInfo.numBlocks = 4096;
 		g_flashInfo.pagesPerBlock = 64;
@@ -608,6 +617,8 @@
 	debug("bad block table allocated, size %d\n", g_flashInfo.numBlocks);
 	memset(g_pBBT, BLOCK_UNKNOWN, g_flashInfo.numBlocks);
 
+	g_chipID = chipNum;
+	
 	printf("Geode LX flash driver initialized, device ID 0x%x\n", g_deviceID);
 	debug("FlashChip = 0x%x\n", g_chipID);
 	debug("NumBlocks = 0x%x\n", g_flashInfo.numBlocks);

Modified: trunk/filo-0.5/drivers/flash/lxflash.h
===================================================================
--- trunk/filo-0.5/drivers/flash/lxflash.h	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/drivers/flash/lxflash.h	2008-08-04 21:13:36 UTC (rev 51)
@@ -45,6 +45,7 @@
 #define MSR_DIVIL_LBAR_FLSH1	0x51400011	// Flash Chip Select 1
 #define MSR_DIVIL_LBAR_FLSH2	0x51400012	// Flash Chip Select 2
 #define MSR_DIVIL_LBAR_FLSH3	0x51400013	// Flash Chip Select 3
+#define NOR_NAND				(1UL<<1)	// 1 for NAND, 0 for NOR
 
 #define MSR_DIVIL_BALL_OPTS		0x51400015
 #define PIN_OPT_IDE				(1UL<<0)	// 0 for flash, 1 for IDE
@@ -56,8 +57,6 @@
 
 #define SET_FLSH_HIGH			0x0000FFF3
 #define SET_FLSH_LOW			0x0000C000
-#define SET_NANDF_DATA_LOW		0x01200120
-#define SET_NANDF_CTL_LOW		0x00000120
 
 // ThinCan defaults
 
@@ -138,8 +137,9 @@
 #define FLASH_NAND					1
 
 #define SAMSUNG_NAND_64MB			0xc0a576ec
-#define SST_NAND_64MB				0x76207620
-#define SST_NAND_512MB				0x9580dc20
+#define ST_NAND_64MB				0x76207620
+#define ST_NAND_512MB				0x9580dc20
+#define ST_NAND_128MB				0x1d80f120
 
 #define ERROR_SUCCESS				0
 #define ERROR_BAD_PARAMS			-1

Modified: trunk/filo-0.5/fs/blockdev.c
===================================================================
--- trunk/filo-0.5/fs/blockdev.c	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/fs/blockdev.c	2008-08-04 21:13:36 UTC (rev 51)
@@ -196,7 +196,7 @@
     uint32_t disk_size = 0;
 
     /* Don't re-open the device that's already open */
-    if (strcmp(name, dev_name) == 0) {
+    if (strcmp(name, dev_name) == 0 && dev_type != -1 ) {
 	debug("already open\n");
 	*reopen = 1;
 	return 1;
@@ -207,6 +207,10 @@
 	debug("failed to parse device name: %s\n", name);
 	return 0;
     }
+    
+    /* If we have another dev open, close it first! */
+    if (dev_type != type && dev_type != -1)
+    	devclose();
 
     /* Do simple sanity check first */
     if (offset & DEV_SECTOR_MASK) {
@@ -313,6 +317,17 @@
     return 1;
 }
 
+void devclose(void)
+{
+#ifdef FLASH_DISK
+	/* Try to close NAND if it was left open */
+	if (dev_type == DISK_FLASH)
+		NAND_close();
+#endif
+	
+	dev_type = -1;
+}
+
 /* Read a sector from opened device with simple/stupid buffer cache */
 static void *read_sector(unsigned long sector)
 {

Modified: trunk/filo-0.5/fs/vfs.c
===================================================================
--- trunk/filo-0.5/fs/vfs.c	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/fs/vfs.c	2008-08-04 21:13:36 UTC (rev 51)
@@ -202,5 +202,6 @@
 
 void file_close(void)
 {
+	devclose();
 }
 

Modified: trunk/filo-0.5/i386/artecboot.c
===================================================================
--- trunk/filo-0.5/i386/artecboot.c	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/i386/artecboot.c	2008-08-04 21:13:36 UTC (rev 51)
@@ -53,6 +53,7 @@
 	if(file_read(&bootHdr, sizeof(ARTECBOOT_HEADER)) != sizeof(ARTECBOOT_HEADER))
 	{
 		printf("Boot error: failed reading the boot image header\n");
+		file_close();
 		return LOADER_NOT_SUPPORT;
 	}
 	
@@ -60,6 +61,7 @@
 	if(bootHdr.magicHeader != ARTECBOOT_HEADER_MAGIC)
 	{
 		debug("No Artecboot signature found, aborting\n");
+		file_close();
 		return LOADER_NOT_SUPPORT;
 	}
 
@@ -67,6 +69,7 @@
 	if(bootHdr.bootVersion > CURRENT_VERSION)
 	{
 		printf("Boot error: incompatible version number: %x\n", bootHdr.bootVersion);
+		file_close();
 		return LOADER_NOT_SUPPORT;
 	}
 	
@@ -150,5 +153,6 @@
 		return LOADER_NOT_SUPPORT;
 	}
 	
+	file_close();
 	return 0;
 }

Modified: trunk/filo-0.5/i386/ldscript
===================================================================
--- trunk/filo-0.5/i386/ldscript	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/i386/ldscript	2008-08-04 21:13:36 UTC (rev 51)
@@ -6,9 +6,12 @@
 /* Initial load address
  * To be loaded by GRUB, this must be >= 1MB
  */
-BASE_ADDR = 0x100000;
+/* When started from General Software BIOS */
+//BASE_ADDR = 0x40000;
+/* When started from LinuxBIOS */
+BASE_ADDR = 0x100000;          
 
-/* 32KB heap and 16k stack */
+/* 32KB heap and 16KB stack */
 HEAP_SIZE = 32768;
 STACK_SIZE = 16384;
 
@@ -31,6 +34,7 @@
     .note : { *(.note.ELFBoot) }
 
     /* Normal sections */
+    .boot : { *(.boot) *(.boot.*) }
     .text : { *(.text) *(.text.*) }
     .rodata : {
 	. = ALIGN(4);

Modified: trunk/filo-0.5/i386/linux_load.c
===================================================================
--- trunk/filo-0.5/i386/linux_load.c	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/i386/linux_load.c	2008-08-04 21:13:36 UTC (rev 51)
@@ -640,8 +640,10 @@
 	return -1;
 
     kern_addr = load_linux_header(&hdr);
-    if (kern_addr == 0)
-	return LOADER_NOT_SUPPORT;
+    if (kern_addr == 0) {
+    	file_close();
+    	return LOADER_NOT_SUPPORT;
+    }
 
     params = phys_to_virt(LINUX_PARAM_LOC);
     init_linux_params(params, &hdr);
@@ -653,6 +655,7 @@
     if (kern_size == 0) {
 	if (initrd_file)
 	    free(initrd_file);
+	file_close();
 	return -1;
     }
 
@@ -660,10 +663,13 @@
 	if (load_initrd(&hdr, info, kern_addr+kern_size, params, initrd_file)
 		!= 0) {
 	    free(initrd_file);
+	    file_close();
 	    return -1;
 	}
 	free(initrd_file);
     }
+    
+    file_close();
 
     hardware_setup();
 

Modified: trunk/filo-0.5/i386/switch.S
===================================================================
--- trunk/filo-0.5/i386/switch.S	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/i386/switch.S	2008-08-04 21:13:36 UTC (rev 51)
@@ -1,6 +1,6 @@
 	.globl	entry, __switch_context, __exit_context, halt
 
-	.text
+	.section ".boot", "xa"
 	.align	4
 
 /*

Modified: trunk/filo-0.5/include/fs.h
===================================================================
--- trunk/filo-0.5/include/fs.h	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/include/fs.h	2008-08-04 21:13:36 UTC (rev 51)
@@ -22,6 +22,7 @@
 #ifdef FLASH_DISK
 int flash_probe(int drive);
 int flash_read(int drive, sector_t sector, void *buffer);
+int NAND_close(void);
 #endif
 
 #define DISK_IDE 1
@@ -30,6 +31,7 @@
 #define DISK_FLASH 4
 
 int devopen(const char *name, int *reopen);
+void devclose(void);
 int devread(unsigned long sector, unsigned long byte_offset,
 	unsigned long byte_len, void *buf);
 void dev_set_partition(unsigned long start, unsigned long size);

Modified: trunk/filo-0.5/main/elfload.c
===================================================================
--- trunk/filo-0.5/main/elfload.c	2008-08-04 20:19:53 UTC (rev 50)
+++ trunk/filo-0.5/main/elfload.c	2008-08-04 21:13:36 UTC (rev 51)
@@ -345,6 +345,8 @@
 	    goto out;
     }
 
+    file_close();
+    
     boot_notes = build_boot_notes(info, cmdline);
 
 #if PCMCIA_CF
@@ -373,5 +375,6 @@
 	free(image_name);
     if (image_version)
 	free(image_version);
+    file_close();
     return retval;
 }




From svn at coreboot.org  Mon Aug  4 23:14:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 Aug 2008 23:14:40 +0200
Subject: [coreboot] r52 - trunk/filo-0.5
Message-ID: <mailman.1781.1355071350.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-08-04 23:14:40 +0200 (Mon, 04 Aug 2008)
New Revision: 52

Modified:
   trunk/filo-0.5/Makefile
Log:
push version


Modified: trunk/filo-0.5/Makefile
===================================================================
--- trunk/filo-0.5/Makefile	2008-08-04 21:13:36 UTC (rev 51)
+++ trunk/filo-0.5/Makefile	2008-08-04 21:14:40 UTC (rev 52)
@@ -13,7 +13,7 @@
 endif
 
 PROGRAM_NAME = FILO
-PROGRAM_VERSION = 0.5.5
+PROGRAM_VERSION = 0.5.6
 
 BUILD_INFO = ($(shell whoami)@$(shell hostname)) $(shell LANG=C date)
 




From c-d.hailfinger.devel.2006 at gmx.net  Tue Aug  5 01:58:04 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 Aug 2008 01:58:04 +0200
Subject: [coreboot] [PATCH] flashrom: More SPI erase functions
Message-ID: <4897978C.10202@gmx.net>

As promised to Stefan, here's the flashrom patch I've been talking about.

Add additional SPI sector erase and chip erase command functions to
flashrom. Not all chips support all commands, so allow the implementer
to select the matching function.
Fix a layering violation in ICH SPI code to be less bad. Still not
perfect, but the new code is shorter, more generic and architecturally
more sound.
TODO (in a separate patch):
- move the generic sector erase code to spi.c
- decide which erase command to use based on info about the chip
- create a generic spi_erase_all_sectors function which calls the
generic sector erase function

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-spi_erase/flash.h
===================================================================
--- flashrom-spi_erase/flash.h	(Revision 3471)
+++ flashrom-spi_erase/flash.h	(Arbeitskopie)
@@ -417,7 +417,10 @@
 int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
 void spi_write_enable();
 void spi_write_disable();
+int spi_chip_erase_60(struct flashchip *flash);
 int spi_chip_erase_c7(struct flashchip *flash);
+int spi_block_erase_52(const struct flashchip *flash, unsigned long addr);
+int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr);
 int spi_chip_write(struct flashchip *flash, uint8_t *buf);
 int spi_chip_read(struct flashchip *flash, uint8_t *buf);
 uint8_t spi_read_status_register();
Index: flashrom-spi_erase/spi.c
===================================================================
--- flashrom-spi_erase/spi.c	(Revision 3471)
+++ flashrom-spi_erase/spi.c	(Arbeitskopie)
@@ -266,6 +266,22 @@
 	}
 }
 	
+int spi_chip_erase_60(struct flashchip *flash)
+{
+	const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60};
+	
+	spi_disable_blockprotect();
+	spi_write_enable();
+	/* Send CE (Chip Erase) */
+	spi_command(sizeof(cmd), 0, cmd, NULL);
+	/* Wait until the Write-In-Progress bit is cleared.
+	 * This usually takes 1-85 s, so wait in 1 s steps.
+	 */
+	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+		sleep(1);
+	return 0;
+}
+
 int spi_chip_erase_c7(struct flashchip *flash)
 {
 	const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7};
@@ -282,6 +298,24 @@
 	return 0;
 }
 
+int spi_block_erase_52(const struct flashchip *flash, unsigned long addr)
+{
+	unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52};
+
+	cmd[1] = (addr & 0x00ff0000) >> 16;
+	cmd[2] = (addr & 0x0000ff00) >> 8;
+	cmd[3] = (addr & 0x000000ff);
+	spi_write_enable();
+	/* Send BE (Block Erase) */
+	spi_command(sizeof(cmd), 0, cmd, NULL);
+	/* Wait until the Write-In-Progress bit is cleared.
+	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
+	 */
+	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+		usleep(100 * 1000);
+	return 0;
+}
+
 /* Block size is usually
  * 64k for Macronix
  * 32k for SST
Index: flashrom-spi_erase/ichspi.c
===================================================================
--- flashrom-spi_erase/ichspi.c	(Revision 3471)
+++ flashrom-spi_erase/ichspi.c	(Arbeitskopie)
@@ -452,17 +452,8 @@
 
 static int ich_spi_erase_block(struct flashchip *flash, int offset)
 {
-	printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n",
-		     offset, 1);
-
-	if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) {
-		printf_debug("Error erasing sector at 0x%x", offset);
-		return -1;
-	}
-
-	printf("DONE BLOCK 0x%x\n", offset);
-
-	return 0;
+	/* FIMXE: call the chip-specific spi_block_erase_XX instead. */
+	return spi_block_erase_d8(flash, offset);
 }
 
 static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, int maxdata)


-- 
http://www.hailfinger.org/




From svn at coreboot.org  Tue Aug  5 03:19:38 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 Aug 2008 03:19:38 +0200
Subject: [coreboot] r720 - in coreboot-v3: arch/x86 include/arch/x86
	northbridge/amd/k8
Message-ID: <mailman.1782.1355071350.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-05 03:19:37 +0200 (Tue, 05 Aug 2008)
New Revision: 720

Added:
   coreboot-v3/arch/x86/resourcemap.c
Modified:
   coreboot-v3/include/arch/x86/cpu.h
   coreboot-v3/northbridge/amd/k8/raminit.c
Log:
With a bug fix from peter and a suggest change by Carl-Daniel

Resource map and a way to use the pci config stuff from stage 1, done in 
a way that will work in stage 2 (but only for systems that use type 1
config cycles; will fail for type MEM config cycles). 

We need to rethink the PCI config stuff per Stepan's comment, in part 
because the device tree now includes things that are NOT PCI devices. 
Stepan's suggestion, to make the functions take busdevfn as the 
parameter, makes a lot of sense. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Peter Stuge <peter at stuge.s


Added: coreboot-v3/arch/x86/resourcemap.c
===================================================================
--- coreboot-v3/arch/x86/resourcemap.c	                        (rev 0)
+++ coreboot-v3/arch/x86/resourcemap.c	2008-08-05 01:19:37 UTC (rev 720)
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * setup a resource map. 
+ * for PCRM entries, add a pci device offset, and a pci "OR value offset"
+ * for IO8 and IO32 entries, add an io base offset. 
+ * This function combines a bunch of seperate functions that were scattered
+ * throughout v2. It may be awkward but it does allow for one rmap for 
+ * all settings, which is handy. See include/arch/x86/cpu.h for usage on 
+ * how to set up a resource map. 
+ *
+ * @param rm The resource map
+ * @param max The map size
+ * @param offset_dev pci device offset. This can be useful on e.g. k8
+ *        we have a number of similar devices which need the same setups
+ *        we can use one map for more than one device. NOTE: 
+ *        offset_dev IS NOT ASSUMED TO BE OFFSET BY FN (i.e. it is not << 3)
+ * @param offset_pciio added to the OR value for setting up PCI IO
+ * @param offset_io offset from the io base in the resource map
+ */
+
+/* NOTE: By doing the config write in this manner we guarantee that this
+ * will work in stage1 or stage2.
+ */
+#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
+#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
+
+void setup_resource_map_x_offset(const rmap *rm, u32 max,
+                                 u32 offset_dev, u32 offset_pciio, 
+                                 u32 offset_io)
+{
+	u32 i;
+
+	printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
+
+	for(i = 0; i < max; i++, rm++) {
+          switch (rm->type){
+		case PCIRM: 
+			{
+                          u32 dev;
+                          unsigned where;
+                          unsigned long reg;
+			  printk(BIOS_DEBUG, "(%x,%x+%x,%x,%x) & %08x | %08x+%08x\n", rm->pcm.bus,rm->pcm.dev+offset_dev,
+                                 rm->pcm.fn,rm->pcm.reg,
+				 rm->pcm.and,rm->pcm.or, offset_pciio);
+                          dev = rm->pcm.dev;
+                          dev += offset_dev;
+                          where = rm->pcm.reg;
+                          dev <<= 3;
+                          dev |= rm->pcm.fn;
+                          reg = pci_config_read32(rm->pcm.bus, dev, where);
+                          reg &= rm->pcm.and;
+                          reg |= rm->pcm.or + offset_pciio; 
+                          pci_config_write32(rm->pcm.bus, dev, where, reg);
+			}
+			break;
+		case IO8:
+			{
+                          u32 where;
+                          u8 reg;
+                          printk(BIOS_DEBUG, "(%04x+%04x) &  %02x | %02xx\n", rm->port, offset_io, rm->pcm.and,rm->pcm.or);
+                          where = rm->port + offset_io;
+                          reg = inb(where);
+                          reg &= rm->and;
+                          reg |= rm->or;
+                          outb(reg, where);
+			}
+			break;
+		case IO32:
+			{
+                          u32 where;
+                          u32 reg;
+                          printk(BIOS_DEBUG, "(%04x+%04x) &  %02x | %02xx\n", rm->port, offset_io, rm->pcm.and,rm->pcm.or);
+                          where = rm->port + offset_io;
+                          reg = inl(where);
+                          reg &= rm->and;
+                          reg |= rm->or;
+                          outl(reg, where);
+			}
+			break;
+		} // switch
+
+
+	}
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+/**
+ * setup a resource map
+
+ * @param rm The resource map
+ * @param max The map size
+ */
+
+void setup_resource_map(const struct rmap *rm, u32 max)
+{
+
+  setup_resource_map_x_offset(rm, max);
+}
+

Modified: coreboot-v3/include/arch/x86/cpu.h
===================================================================
--- coreboot-v3/include/arch/x86/cpu.h	2008-08-04 00:39:28 UTC (rev 719)
+++ coreboot-v3/include/arch/x86/cpu.h	2008-08-05 01:19:37 UTC (rev 720)
@@ -206,4 +206,49 @@
 #define PRINTK_BUF_ADDR_RAM 0x90000
 #endif
 
+/* resource maps. These started out as special for the K8 but now have more general usage */
+/* it's not totally clear that the type and union are a great idea, but see the v2 code: 
+ * there are tables that are combinations of all three (or the code supports it anyway)
+ */
+/* types of resource maps */
+#define PCIRM	'p'
+#define IO8	'8'
+#define IO32	'I'
+
+/* pci config map */
+struct pcm {
+	u8 bus, dev, fn, reg;
+	u32 and;
+	u32 or;
+};
+
+struct io8 {
+	u16 port;
+	u8 and, or;
+};
+
+struct io32 {
+	u16 port;
+	u32 and, or;
+};
+
+
+/* convenience initializer */
+#define PCM(abus,adev,afn,areg,aand,aor) {.type = PCIRM, {.pcm ={.bus=abus,.dev=adev,.fn=afn,.reg=areg,.and=aand,.or=aor}}}
+#define EIO8(aport, aand, aor) {.type=IO8, {.io8 = {.port = aport, .and = aand, .or = aor}}}
+#define EIO32(aport, aand, aaor) {.type = IO32, {.io32 = {.port = aport, .and = aand, .or = aor}}}
+struct rmap {
+	int type;
+	union {
+		struct pcm pcm;
+		struct io8 io8;
+		struct io32 io32;
+	};
+};
+
+void setup_resource_map_x_offset(const struct rmap *rm, u32 max,
+                                 u32 offset_dev, u32 offset_pciio, 
+                                 u32 offset_io);
+void setup_resource_map(const struct rmap *rm, u32 max);
+
 #endif /* ARCH_X86_CPU_H */

Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-04 00:39:28 UTC (rev 719)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-05 01:19:37 UTC (rev 720)
@@ -51,38 +51,23 @@
 #define HW_MEM_HOLE_SIZEK 64*1024*1024
 #endif
 
+
+/* now THIS is a kludge but ... it will do for now until we work this out. */
+extern const struct pci_bus_operations pci_cf8_conf1;
 static void hard_reset(void);
 
-static void setup_resource_map(const unsigned int *register_values, int max)
-{
-	printk(BIOS_DEBUG, "setting up resource map....");
-/*
-	int i;
-	for(i = 0; i < max; i += 3) {
-		struct device *dev;
-		unsigned where;
-		unsigned long reg;
-		printk(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]);
-		dev = register_values[i] & ~0xfff;
-		where = register_values[i] & 0xfff;
-		reg = pci_read_config32(dev, where);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-		pci_write_config32(dev, where, reg);
-	}
-*/
-	printk(BIOS_DEBUG, "done.\n");
-}
+#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
+#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
 
+
 static int controller_present(const struct mem_controller *ctrl)
 {
-        return pci_read_config32(ctrl->f0, 0) == 0x11001022;
+        return pci_config_read32(0, ctrl->f0, 0) == 0x11001022;
 }
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
-	static const unsigned int register_values[] = {
-
+	static struct rmap rm[] = {
 	/* Careful set limit registers before base registers which contain the enables */
 	/* DRAM Limit i Registers
 	 * F1:0x44 i = 0
@@ -110,14 +95,14 @@
 	 *	   This field defines the upper address bits of a 40 bit  address
 	 *	   that define the end of the DRAM region.
 	 */
-	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+	PCM(0, 0x18, 1, 0x44, 0x0000f8f8, 0x00000000),
+	PCM(0, 0x18, 1, 0x4C, 0x0000f8f8, 0x00000001),
+	PCM(0, 0x18, 1, 0x54, 0x0000f8f8, 0x00000002),
+	PCM(0, 0x18, 1, 0x5C, 0x0000f8f8, 0x00000003),
+	PCM(0, 0x18, 1, 0x64, 0x0000f8f8, 0x00000004),
+	PCM(0, 0x18, 1, 0x6C, 0x0000f8f8, 0x00000005),
+	PCM(0, 0x18, 1, 0x74, 0x0000f8f8, 0x00000006),
+	PCM(0, 0x18, 1, 0x7C, 0x0000f8f8, 0x00000007),
 	/* DRAM Base i Registers
 	 * F1:0x40 i = 0
 	 * F1:0x48 i = 1
@@ -148,14 +133,14 @@
 	 *	   This field defines the upper address bits of a 40-bit address
 	 *	   that define the start of the DRAM region.
 	 */
-	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+	PCM(0, 0x18, 1, 0x40, 0x0000f8fc, 0x00000000),
+	PCM(0, 0x18, 1, 0x48, 0x0000f8fc, 0x00000000),
+	PCM(0, 0x18, 1, 0x50, 0x0000f8fc, 0x00000000),
+	PCM(0, 0x18, 1, 0x58, 0x0000f8fc, 0x00000000),
+	PCM(0, 0x18, 1, 0x60, 0x0000f8fc, 0x00000000),
+	PCM(0, 0x18, 1, 0x68, 0x0000f8fc, 0x00000000),
+	PCM(0, 0x18, 1, 0x70, 0x0000f8fc, 0x00000000),
+	PCM(0, 0x18, 1, 0x78, 0x0000f8fc, 0x00000000),
 
 	/* DRAM CS Base Address i Registers
 	 * F2:0x40 i = 0
@@ -178,14 +163,14 @@
 	 *	   address that define the memory address space.  These
 	 *	   bits decode 32-MByte blocks of memory.
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x58), 0x001f01fe, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x5C), 0x001f01fe, 0x00000000,
+	PCM(0, 0x18, 2, 0x40, 0x001f01fe, 0x00000000),
+	PCM(0, 0x18, 2, 0x44, 0x001f01fe, 0x00000000),
+	PCM(0, 0x18, 2, 0x48, 0x001f01fe, 0x00000000),
+	PCM(0, 0x18, 2, 0x4C, 0x001f01fe, 0x00000000),
+	PCM(0, 0x18, 2, 0x50, 0x001f01fe, 0x00000000),
+	PCM(0, 0x18, 2, 0x54, 0x001f01fe, 0x00000000),
+	PCM(0, 0x18, 2, 0x58, 0x001f01fe, 0x00000000),
+	PCM(0, 0x18, 2, 0x5C, 0x001f01fe, 0x00000000),
 	/* DRAM CS Mask Address i Registers
 	 * F2:0x60 i = 0
 	 * F2:0x64 i = 1
@@ -205,14 +190,14 @@
 	 * [31:30] Reserved
 	 * 
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x78), 0xC01f01ff, 0x00000000,
-	PCI_ADDR(0, 0x18, 2, 0x7C), 0xC01f01ff, 0x00000000,
+	PCM(0, 0x18, 2, 0x60, 0xC01f01ff, 0x00000000),
+	PCM(0, 0x18, 2, 0x64, 0xC01f01ff, 0x00000000),
+	PCM(0, 0x18, 2, 0x68, 0xC01f01ff, 0x00000000),
+	PCM(0, 0x18, 2, 0x6C, 0xC01f01ff, 0x00000000),
+	PCM(0, 0x18, 2, 0x70, 0xC01f01ff, 0x00000000),
+	PCM(0, 0x18, 2, 0x74, 0xC01f01ff, 0x00000000),
+	PCM(0, 0x18, 2, 0x78, 0xC01f01ff, 0x00000000),
+	PCM(0, 0x18, 2, 0x7C, 0xC01f01ff, 0x00000000),
 	/* DRAM Bank Address Mapping Register
 	 * F2:0x80
 	 * Specify the memory module size
@@ -233,7 +218,7 @@
 	 * [11:11] Reserved
 	 * [31:15]
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000000,
+	PCM(0, 0x18, 2, 0x80, 0xffff8888, 0x00000000),
 	/* DRAM Timing Low Register
 	 * F2:0x88
 	 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
@@ -298,7 +283,7 @@
 	 *	   1 = 3 bus clocks
 	 * [31:29] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x02522001 /* 0x03623125 */ ,
+	PCM(0, 0x18, 2, 0x88, 0xe8088008, 0x02522001 /* 0x03623125 */ ),
 	/* DRAM Timing High Register
 	 * F2:0x8C
 	 * [ 0: 0] Twtr (Write to Read Delay)
@@ -330,7 +315,7 @@
 	 *	   001 = 2 Mem clocks after CAS# (Registered Dimms)
 	 * [31:23] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
+	PCM(0, 0x18, 2, 0x8c, 0xff8fe08e, ((0 << 20)|(0 << 8)|(0 << 4)|(0 << 0))),
 	/* DRAM Config Low Register
 	 * F2:0x90
 	 * [ 0: 0] DLL Disable
@@ -401,13 +386,13 @@
 	 *	   111 = Oldest entry in DCQ can be bypassed 7 times
 	 * [31:28] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
-	(4 << 25)|(0 << 24)| 
-	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
-	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| 
-	(2 << 14)|(0 << 13)|(0 << 12)| 
-	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
-	(0 << 3) |(0 << 1) |(0 << 0),
+	PCM(0, 0x18, 2, 0x90, 0xf0000000, \
+	(4 << 25)|(0 << 24)| \
+	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| \
+	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| \
+	(2 << 14)|(0 << 13)|(0 << 12)| \
+	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| \
+	(0 << 3) |(0 << 1) |(0 << 0)),
 	/* DRAM Config High Register
 	 * F2:0x94
 	 * [ 0: 3] Maximum Asynchronous Latency
@@ -472,9 +457,9 @@
 	 *	   1 = Enabled
 	 * [31:30] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0,
-	(0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)|
-	(0 << 20)|(0 << 19)|(DCH_IDLE_LIMIT_16 << 16)|(0 << 8)|(0 << 0),
+	PCM(0, 0x18, 2, 0x94, 0xc180f0f0,\
+	(0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)|\
+	(0 << 20)|(0 << 19)|(DCH_IDLE_LIMIT_16 << 16)|(0 << 8)|(0 << 0)),
 	/* DRAM Delay Line Register
 	 * F2:0x98
 	 * Adjust the skew of the input DQS strobe relative to DATA
@@ -490,15 +475,15 @@
 	 *	   1 = Adj is used to decrease the PDL delay
 	 * [31:26] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
+	PCM(0, 0x18, 2, 0x98, 0xfc00ffff, 0x00000000),
 	/* MCA NB Status Low reg */
-	PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
+	PCM(0, 0x18, 3, 0x48, 0x00f00000, 0x00000000),
 	/* MCA NB Status high reg */
-	PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
+	PCM(0, 0x18, 3, 0x4c, 0x01801e8c, 0x00000000),
 	/* MCA NB address Low reg */
-	PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
+	PCM(0, 0x18, 3, 0x50, 0x00000007, 0x00000000),
 	/* MCA NB address high reg */
-	PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
+	PCM(0, 0x18, 3, 0x54, 0xffffff00, 0x00000000),
 	/* DRAM Scrub Control Register
 	 * F3:0x58
 	 * [ 4: 0] DRAM Scrube Rate
@@ -532,7 +517,7 @@
 	 *	   10110 =  84.00 ms
 	 *	   All Others = Reserved
 	 */
-	PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
+	PCM(0, 0x18, 3, 0x58, 0xffe0e0e0, 0x00000000),
 	/* DRAM Scrub Address Low Register
 	 * F3:0x5C
 	 * [ 0: 0] DRAM Scrubber Redirect Enable
@@ -541,13 +526,13 @@
 	 * [ 5: 1] Reserved
 	 * [31: 6] DRAM Scrub Address 31-6
 	 */
-	PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
+	PCM(0, 0x18, 3, 0x5C, 0x0000003e, 0x00000000),
 	/* DRAM Scrub Address High Register
 	 * F3:0x60
 	 * [ 7: 0] DRAM Scrubb Address 39-32
 	 * [31: 8] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
+	PCM(0, 0x18, 3, 0x60, 0xffffff00, 0x00000000),
 	};
 	int i;
 	int max;
@@ -557,19 +542,8 @@
                 return;
         }
 	printk(BIOS_SPEW, "setting up CPU 0x%x northbridge registers ", ctrl->node_id);
-	max = sizeof(register_values)/sizeof(register_values[0]);
-	for(i = 0; i < max; i += 3) {
-		struct device *dev;
-		unsigned where;
-		unsigned long reg;
-                printk(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]);
-		dev = (register_values[i] & ~0xfff) - PCI_BDF(0, 0x18, 0) + ctrl->f0;
-		where = register_values[i] & 0xfff;
-		reg = pci_read_config32(dev, where);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-		pci_write_config32(dev, where, reg);
-	}
+	max = sizeof(rm)/sizeof(rm[0]);
+	setup_resource_map(rm, max);
 	printk(BIOS_SPEW, "done.\n");
 }
 
@@ -577,8 +551,8 @@
 static void hw_enable_ecc(const struct mem_controller *ctrl)
 {
 	u32 dcl, nbcap, opt = 1;
-	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
+	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_DimmEccEn;
 	if (nbcap & NBCAP_ECC) {
 		dcl |= DCL_DimmEccEn;
@@ -586,14 +560,14 @@
 	if (get_option(&opt, "ECC_memory") || opt) {
 		dcl &= ~DCL_DimmEccEn;
 	}
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	
 }
 
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
 	u32 dcl;
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	return dcl & DCL_128BitEn;
 }
 
@@ -605,7 +579,7 @@
 	 */
 #warning "FIXME: Implement a better test for Opterons"
 	u32 nbcap;
-	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
 	return !!(nbcap & NBCAP_128Bit);
 }
 
@@ -616,7 +590,7 @@
 	 * This function must be called after spd_handle_unbuffered_dimms.
 	 */
 	u32 dcl;
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	return !(dcl & DCL_UnBufDimm);
 }
 
@@ -748,25 +722,25 @@
 	base1 &= ~0x001ffffe;
 
 	/* Set the appropriate DIMM base address register */
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
+	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
 #if QRANK_DIMM_SUPPORT == 1
 	if(sz.rank == 4) {
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
+		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
+		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
 	}
 #endif
 
 	/* Enable the memory clocks for this DIMM */
 	if (base0) {
-		dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+		dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 		dch |= DCH_MEMCLK_EN0 << index;
 #if QRANK_DIMM_SUPPORT == 1
 		if(sz.rank == 4) {
 			dch |= DCH_MEMCLK_EN0 << (index + 2);
 		}
 #endif
-		pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+		pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 	}
 }
 
@@ -782,7 +756,7 @@
 	u32 map;
 	u32 dch;
 
-	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+	map = pci_config_read32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
 	map &= ~(0xf << (index * 4));
 #if QRANK_DIMM_SUPPORT == 1
         if(sz.rank == 4) {
@@ -811,7 +785,7 @@
 		}
 	}
 
-	pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
+	pci_config_write32(0, ctrl->f2, DRAM_BANK_ADDR_MAP, map);
 	
 }
 
@@ -843,7 +817,7 @@
 	unsigned base;
 	unsigned index;
 	unsigned limit_reg, base_reg;
-	struct device *device;
+	u32 device;
 
 	node_id = ctrl->node_id;
 	index = (node_id << 3);
@@ -858,8 +832,8 @@
 	limit_reg = 0x44 + index;
 	base_reg = 0x40 + index;
 	for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) {
-		pci_write_config32(device, limit_reg, limit);
-		pci_write_config32(device, base_reg, base);
+		pci_config_write32(0, device, limit_reg, limit);
+		pci_config_write32(0, device, base_reg, base);
 	}
 }
 
@@ -944,7 +918,7 @@
 		unsigned cs_mode;
 		u32 value;
 		
-		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+		value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
 		
 		/* Is it enabled? */
 		if (!(value & 1)) {
@@ -960,7 +934,7 @@
 			return 0;
 		}
 
-		value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+		value = pci_config_read32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
                 cs_mode =( value >> ((index>>1)*4)) & 0xf;
                 if(cs_mode == 0 ) continue;
                 if(common_cs_mode == 0) {
@@ -1013,13 +987,13 @@
 	for(index = 0; index < 8; index++) {
 		u32 value;
 
-		value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+		value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
 		/* Is it enabled? */
 		if (!(value & 1)) {
 			continue;
 		}
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
-		pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
+		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
+		pci_config_write32(0, ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
 		csbase += csbase_inc;
 	}
 	
@@ -1036,15 +1010,15 @@
 	/* Remember which registers we have used in the high 8 bits of tom */
 	tom = 0;
 	for(;;) {
-		/* Find the largest remaining canidate */
-		unsigned index, canidate;
+		/* Find the largest remaining candidate */
+		unsigned index, candidate;
 		u32 csbase, csmask;
 		unsigned size;
 		csbase = 0;
-		canidate = 0;
+		candidate = 0;
 		for(index = 0; index < 8; index++) {
 			u32 value;
-			value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+			value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
 
 			/* Is it enabled? */
 			if (!(value & 1)) {
@@ -1060,11 +1034,11 @@
 			if (tom & (1 << (index + 24))) {
 				continue;
 			}
-			/* I have a new canidate */
+			/* I have a new candidate */
 			csbase = value;
-			canidate = index;
+			candidate = index;
 		}
-		/* See if I have found a new canidate */
+		/* See if I have found a new candidate */
 		if (csbase == 0) {
 			break;
 		}
@@ -1073,7 +1047,7 @@
 		size = csbase >> 21;
 
 		/* Remember I have used this register */
-		tom |= (1 << (canidate + 24));
+		tom |= (1 << (candidate + 24));
 
 		/* Recompute the cs base register value */
 		csbase = (tom << 21) | 1;
@@ -1086,9 +1060,9 @@
 		csmask |= 0xfe00;		/* For now don't optimize */
 
 		/* Write the new base register */
-		pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
+		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
 		/* Write the new mask register */
-		pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
+		pci_config_write32(0, ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
 		
 	}
 	/* Return the memory size in K */
@@ -1105,10 +1079,10 @@
 		u32 limit, base;
 		unsigned index;
 		index = node_id << 3;
-		base = pci_read_config32(ctrl->f1, 0x40 + index);
+		base = pci_config_read32(0, ctrl->f1, 0x40 + index);
 		/* Only look at the limit if the base is enabled */
 		if ((base & 3) == 3) {
-			limit = pci_read_config32(ctrl->f1, 0x44 + index);
+			limit = pci_config_read32(0, ctrl->f1, 0x44 + index);
 			end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 		}
 	}
@@ -1139,8 +1113,8 @@
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
 {
 	printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index); 
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
-	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
+	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
+	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
 	dimm_mask &= ~(1 << index);
 	return dimm_mask;
 }
@@ -1176,7 +1150,7 @@
 		die("Mixed buffered and registered dimms not supported");
 	}
 
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_UnBufDimm;
 	if (unbuffered) {
 		if ((has_dualch) && (!is_cpu_pre_d0())) {
@@ -1192,7 +1166,7 @@
 			dcl |= DCL_UnBufDimm;
 		}
 	}
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	if (is_registered(ctrl)) {
 		printk(BIOS_DEBUG, "Registered\n");
 	} else {
@@ -1260,7 +1234,7 @@
 		goto single_channel;
 	}
 	/* If the cpu is not capable of doing dual channels don't do dual channels */
-	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
 	if (!(nbcap & NBCAP_128Bit)) {
 		goto single_channel;
 	}
@@ -1292,10 +1266,10 @@
 	}
 	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	u32 dcl;
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_32ByteEn;
 	dcl |= DCL_128BitEn;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	return dimm_mask;
  single_channel:
 	dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
@@ -1416,7 +1390,7 @@
 		[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
 	};
 
-	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	value = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
 
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
 
@@ -1567,7 +1541,7 @@
 	result.param = get_mem_param(min_cycle_time);
 
 	/* Update DRAM Config High with our selected memory speed */
-	value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	value = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
 #if 0
 	/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed 
@@ -1581,14 +1555,14 @@
 #endif
 
 	value |= result.param->dch_memclk;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, value);
 
 	static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
 	/* Update DRAM Timing Low with our selected cas latency */
-	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	value = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
 	value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, value);
 	
 	result.dimm_mask = dimm_mask;
 	return result;
@@ -1617,14 +1591,14 @@
 		return 0;
 	}
 
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
 	dtl |=	((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1645,14 +1619,14 @@
 	if (clocks > DTL_TRFC_MAX) {
 		return 0;
 	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
 	dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1671,14 +1645,14 @@
 	if (clocks > DTL_TRCD_MAX) {
 		return 0;
 	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
 	dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1696,14 +1670,14 @@
 	if (clocks > DTL_TRRD_MAX) {
 		return 0;
 	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
 	dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1721,14 +1695,14 @@
 	if (clocks > DTL_TRAS_MAX) {
 		return 0;
 	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
 	dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1746,34 +1720,34 @@
 	if (clocks > DTL_TRP_MAX) {
 		return 0;
 	}
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
 	dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
 static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	u32 dtl;
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
 	dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
-	pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 }
 
 
 static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	u32 dth;
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
 	dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 }
 
 static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
@@ -1790,7 +1764,7 @@
 		tref = param->dch_tref4k;
 	}
 
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
 	if ((value == 12) && (old_tref == param->dch_tref4k)) {
 		tref = param->dch_tref4k;
@@ -1799,7 +1773,7 @@
 	}
 	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
 	dth |= (tref << DTH_TREF_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 	return 1;
 }
 
@@ -1830,12 +1804,12 @@
 		dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
 	}
 #endif
-	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~dimm;
 	if (value == 4) {
 		dcl |= dimm;
 	}
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	return 1;
 }
 
@@ -1848,9 +1822,9 @@
 		return -1;
 	}
 	if (value != 2) {
-		dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+		dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
 		dcl &= ~DCL_DimmEccEn;
-		pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+		pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	}
 	return 1;
 }
@@ -1862,7 +1836,7 @@
 	dimms = 0;
 	for(index = 0; index < 8; index += 2) {
 		u32 csbase;
-		csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2)));
+		csbase = pci_config_read32(0, ctrl->f2, (DRAM_CSBASE + (index << 2)));
 		if (csbase & 1) {
 			dimms += 1;
 		}
@@ -1874,10 +1848,10 @@
 {
 	u32 dth;
 
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
 	dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 }
 
 static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1888,7 +1862,7 @@
 	int lat, mtype;
 
 	clocks = 0;
-	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
 	latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
 
 	if (is_opteron(ctrl)) {
@@ -1918,10 +1892,10 @@
 		die("Unknown Trwt\n");
 	}
 	
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
 	dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 	return;
 }
 
@@ -1935,10 +1909,10 @@
 	} else {
 		clocks = 1;
 	}
-	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
 	dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 }
 
 
@@ -1969,7 +1943,7 @@
 		die("Unknown rdpreamble for this nr of slots");
 	}
 
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
 	rdpreamble = param->rdpreamble[i];
 
@@ -1978,7 +1952,7 @@
 	}
 
 	dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1989,7 +1963,7 @@
 
 	dimms = count_dimms(ctrl);
 
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
 	async_lat = 0;
 	if (is_registered(ctrl)) {
@@ -2016,18 +1990,18 @@
 		}
 	}
 	dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
 static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	u32 dch;
 	/* AMD says to Hardcode this */
-	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+	dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
 	dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
 	dch |= DCH_DYN_IDLE_CTR_EN;
-	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
 static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
@@ -2124,7 +2098,7 @@
 {
         int ii;
         u32 carry_over;
-        struct device *dev;
+        u32 dev;
         u32 base, limit;
         u32 basek;
         u32 hoist;
@@ -2133,22 +2107,22 @@
         carry_over = (4*1024*1024) - hole_startk;
 
         for(ii=controllers - 1;ii>i;ii--) {
-                base  = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
+                base  = pci_config_read32(0, ctrl[0].f1, 0x40 + (ii << 3));
                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
                         continue;
                 }
-		limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
+		limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (ii << 3));
                 for(j = 0; j < controllers; j++) {
-                        pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
-                        pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
+                        pci_config_write32(0, ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
+                        pci_config_write32(0, ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
                 }
         }
-        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+        limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (i << 3));
         for(j = 0; j < controllers; j++) {
-                pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
+                pci_config_write32(0, ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
         }
         dev = ctrl[i].f1;
-        base  = pci_read_config32(dev, 0x40 + (i << 3));
+        base  = pci_config_read32(0, dev, 0x40 + (i << 3));
         basek  = (base & 0xffff0000) >> 2;
         if(basek == hole_startk) {
                 //don't need set memhole here, because hole off set will be 0, overflow
@@ -2156,7 +2130,7 @@
                 base &= 0x0000ffff;
                 base |= (4*1024*1024)<<2;
                 for(j = 0; j < controllers; j++) {
-                        pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
+                        pci_config_write32(0, ctrl[j].f1, 0x40 + (i<<3), base);
                 }
         }
 	else {
@@ -2166,7 +2140,7 @@
         	        (((basek + carry_over) >> 6) & 0x0000ff00) +
                 	/* enable */
 	                1;
-	        pci_write_config32(dev, 0xf0, hoist);
+	        pci_config_write32(0, dev, 0xf0, hoist);
 	}
 
         return carry_over;
@@ -2179,7 +2153,8 @@
         int i;
 
         hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
-
+#warning "fix HW_MEM_HOLE_SIZE_AUTO_INC 1"
+#define HW_MEM_HOLE_SIZE_AUTO_INC 1
 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 
 	/* We need to double check if hole_startk is valid.
 	 * If it is equal to the dram base address in K (base_k), 
@@ -2189,7 +2164,7 @@
         for(i=0; i<controllers; i++) {
                         u32 base;
                         unsigned base_k;
-                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+                        base  = pci_config_read32(0, ctrl[0].f1, 0x40 + (i << 3));
                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
                                 continue;
                         }
@@ -2209,11 +2184,11 @@
         for(i=0; i<controllers; i++) {
                         u32 base, limit;
                         unsigned base_k, limit_k;
-                        base  = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+                        base  = pci_config_read32(0, ctrl[0].f1, 0x40 + (i << 3));
                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
                                 continue;
                         }
-                        limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+                        limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (i << 3));
                         base_k = (base & 0xffff0000) >> 2;
                         limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 			if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
@@ -2244,17 +2219,17 @@
 		u32 dch;
 		if (!controller_present(ctrl + i))
 			continue;
-		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
 		if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
 			dch |= DCH_MEMCLK_VALID;
-			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
+			pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
 		}
 		else {
 			/* Disable dram receivers */
 			u32 dcl;
-			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 			dcl |= DCL_DisInRcvrs;
-			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+			pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 		}
 	}
 
@@ -2268,31 +2243,31 @@
 		if (!controller_present(ctrl + i))
 			continue;
 		/* Skip everything if I don't have any memory on this controller */
-		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
 		if (!(dch & DCH_MEMCLK_VALID)) {
 			continue;
 		}
 
 		/* Toggle DisDqsHys to get it working */
-		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+		dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			u32 mnc;
 			printk(BIOS_SPEW, "ECC enabled\n");
-			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
+			mnc = pci_config_read32(0, ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_128BitEn) {
 				mnc |= MNC_CHIPKILL_EN;
 			}
-			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
+			pci_config_write32(0, ctrl[i].f3, MCA_NB_CONFIG, mnc);
 		}
 		dcl |= DCL_DisDqsHys;
-		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 		dcl &= ~DCL_DisDqsHys;
 		dcl &= ~DCL_DLL_Disable;
 		dcl &= ~DCL_D_DRV;
 		dcl &= ~DCL_QFC_EN;
 		dcl |= DCL_DramInit;
-		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 
 	}
 	for(i = 0; i < controllers; i++) {
@@ -2300,7 +2275,7 @@
 		if (!controller_present(ctrl + i))
 			continue;
 		/* Skip everything if I don't have any memory on this controller */
-		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+		dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
 		if (!(dch & DCH_MEMCLK_VALID)) {
 			continue;
 		}
@@ -2309,7 +2284,7 @@
 
 		int loops = 0;
 		do {
-			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+			dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops += 1;
 			if ((loops & 1023) == 0) {
 				printk(BIOS_DEBUG, ".");
@@ -2323,9 +2298,9 @@
 		if (!is_cpu_pre_c0()) {
 			/* Wait until it is safe to touch memory */
 			dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
-			pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+			pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 			do {
-				dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+				dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
 		}
 




From rminnich at gmail.com  Tue Aug  5 03:20:49 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 18:20:49 -0700
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808041355v6a421077g5e3db82697006b6@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net> <20080804173205.23196.qmail@stuge.se>
	<48974168.3040507@gmx.net> <20080804175603.30768.qmail@stuge.se>
	<4897465B.9010309@gmx.net>
	<13426df10808041127w3b5bf512h90fba065a43f907f@mail.gmail.com>
	<48976BAA.9040304@gmx.net>
	<13426df10808041355v6a421077g5e3db82697006b6@mail.gmail.com>
Message-ID: <13426df10808041820xcca28ecwb425bb72391b9017@mail.gmail.com>

With a bug fix from peter and a suggest change by Carl-Daniel

Resource map and a way to use the pci config stuff from stage 1, done in
a way that will work in stage 2 (but only for systems that use type 1
config cycles; will fail for type MEM config cycles).

We need to rethink the PCI config stuff per Stepan's comment, in part
because the device tree now includes things that are NOT PCI devices.
Stepan's suggestion, to make the functions take busdevfn as the
parameter, makes a lot of sense.

Committed revision 720.



From svn at coreboot.org  Tue Aug  5 03:24:38 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 Aug 2008 03:24:38 +0200
Subject: [coreboot] r721 - coreboot-v3/northbridge/amd/k8
Message-ID: <mailman.1783.1355071350.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-05 03:24:38 +0200 (Tue, 05 Aug 2008)
New Revision: 721

Modified:
   coreboot-v3/northbridge/amd/k8/raminit.c
Log:
Self-acking fix of a stupid typo. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-05 01:19:37 UTC (rev 720)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-05 01:24:38 UTC (rev 721)
@@ -56,8 +56,8 @@
 extern const struct pci_bus_operations pci_cf8_conf1;
 static void hard_reset(void);
 
-#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
-#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
+#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL,  bus, dev, where)
+#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
 
 
 static int controller_present(const struct mem_controller *ctrl)




From peter at stuge.se  Tue Aug  5 03:31:04 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Aug 2008 03:31:04 +0200
Subject: [coreboot] patch: resource map proposal.
In-Reply-To: <13426df10808041820xcca28ecwb425bb72391b9017@mail.gmail.com>
References: <13426df10808040901s1e2a9d97o8cc16d53ca1c6470@mail.gmail.com>
	<48973BE9.9070104@gmx.net> <20080804173205.23196.qmail@stuge.se>
	<48974168.3040507@gmx.net> <20080804175603.30768.qmail@stuge.se>
	<4897465B.9010309@gmx.net>
	<13426df10808041127w3b5bf512h90fba065a43f907f@mail.gmail.com>
	<48976BAA.9040304@gmx.net>
	<13426df10808041355v6a421077g5e3db82697006b6@mail.gmail.com>
	<13426df10808041820xcca28ecwb425bb72391b9017@mail.gmail.com>
Message-ID: <20080805013104.12854.qmail@stuge.se>

On Mon, Aug 04, 2008 at 06:20:49PM -0700, ron minnich wrote:
> Committed revision 720.

Cool.


> We need to rethink the PCI config stuff per Stepan's comment, in
> part because the device tree now includes things that are NOT PCI
> devices. Stepan's suggestion, to make the functions take busdevfn
> as the parameter, makes a lot of sense.

Didn't we want to use a flat tree in early code? Was that just me?


//Peter



From rminnich at gmail.com  Tue Aug  5 04:38:18 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 19:38:18 -0700
Subject: [coreboot] K8 state of v3 tree
Message-ID: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>

Current state of tree. This all compiles with only errors for stuff
not yet defined.

Too many fixes in here to list them all :-)
but:
convert mcp55 over to new resource maps.
fix my misunderstanding of one aspect of resource map setup
Fix typo in config_{read,write} naming.
Fix random mistakes in include files.

YHLU: question: is REV F a proper superset of all K8? If we do REV F compatible
code, and test for REV A-E in our coded and take appropriate action,
will the code work properly? Can we have e.g.
the same mem_controller struct for all K8?

I'd like to avoid the files we had in v2 with stuff like xyz_f and
just have one common set of K8 files.
It's even ok if, e.g., there are struct members in the mem_controller
struct that are only used on rev f
or dual core, and unused otherwise. I'd like to simplify the tangle we
had in v2.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
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From peter at stuge.se  Tue Aug  5 04:46:54 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Aug 2008 04:46:54 +0200
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
Message-ID: <20080805024654.30068.qmail@stuge.se>

On Mon, Aug 04, 2008 at 07:38:18PM -0700, ron minnich wrote:
> Current state of tree. This all compiles with only errors for stuff
> not yet defined.
..
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Looked through it, looks good.

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Tue Aug  5 04:48:54 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 Aug 2008 04:48:54 +0200
Subject: [coreboot] r722 - in coreboot-v3: arch/x86 arch/x86/amd/k8
	include/arch/x86 include/arch/x86/amd/k8 mainboard/gigabyte
	northbridge/amd/k8 southbridge/nvidia/mcp55
Message-ID: <mailman.1784.1355071350.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-05 04:48:54 +0200 (Tue, 05 Aug 2008)
New Revision: 722

Modified:
   coreboot-v3/arch/x86/amd/k8/stage1.c
   coreboot-v3/arch/x86/resourcemap.c
   coreboot-v3/include/arch/x86/amd/k8/k8.h
   coreboot-v3/include/arch/x86/amd/k8/raminit.h
   coreboot-v3/include/arch/x86/cpu.h
   coreboot-v3/mainboard/gigabyte/Kconfig
   coreboot-v3/northbridge/amd/k8/raminit.c
   coreboot-v3/southbridge/nvidia/mcp55/stage1.c
Log:
State of the tree for K8
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-08-05 02:48:54 UTC (rev 722)
@@ -23,6 +23,7 @@
 #include <console.h>
 #include <msr.h>
 #include <macros.h>
+#include <cpu.h>
 #include <amd/k8/k8.h>
 
 /**

Modified: coreboot-v3/arch/x86/resourcemap.c
===================================================================
--- coreboot-v3/arch/x86/resourcemap.c	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/arch/x86/resourcemap.c	2008-08-05 02:48:54 UTC (rev 722)
@@ -29,10 +29,8 @@
  *
  * @param rm The resource map
  * @param max The map size
- * @param offset_dev pci device offset. This can be useful on e.g. k8
- *        we have a number of similar devices which need the same setups
- *        we can use one map for more than one device. NOTE: 
- *        offset_dev IS NOT ASSUMED TO BE OFFSET BY FN (i.e. it is not << 3)
+ * @param offset_bdf pci device offset. Note this is a u32 in 
+ * 			busdevfn format. See PCI_BDF macro if you are not sure what that is. 
  * @param offset_pciio added to the OR value for setting up PCI IO
  * @param offset_io offset from the io base in the resource map
  */
@@ -40,11 +38,11 @@
 /* NOTE: By doing the config write in this manner we guarantee that this
  * will work in stage1 or stage2.
  */
-#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
-#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
+#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
+#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
 
 void setup_resource_map_x_offset(const rmap *rm, u32 max,
-                                 u32 offset_dev, u32 offset_pciio, 
+                                 u32 offset_bdf, u32 offset_pciio, 
                                  u32 offset_io)
 {
 	u32 i;
@@ -53,26 +51,30 @@
 
 	for(i = 0; i < max; i++, rm++) {
           switch (rm->type){
-		case PCIRM: 
+		case TPCIRM: 
 			{
                           u32 dev;
                           unsigned where;
                           unsigned long reg;
-			  printk(BIOS_DEBUG, "(%x,%x+%x,%x,%x) & %08x | %08x+%08x\n", rm->pcm.bus,rm->pcm.dev+offset_dev,
-                                 rm->pcm.fn,rm->pcm.reg,
+			u8 offset_devfn = offset_bdf;
+#warning make sure offset_bus is right for extended PCI addressing
+			u32 offset_bus = offset_bdf >> 8;
+			  printk(BIOS_DEBUG, "(%x+%x,%x+%x,%x+%x,%x) & %08x | %08x+%08x\n", rm->pcm.bus,
+				offset_bus, rm->pcm.dev+offset_devfn>>3,
+                                 rm->pcm.fn, offset_devfn&3, rm->pcm.reg,
 				 rm->pcm.and,rm->pcm.or, offset_pciio);
                           dev = rm->pcm.dev;
-                          dev += offset_dev;
-                          where = rm->pcm.reg;
+                        where = rm->pcm.reg;
                           dev <<= 3;
                           dev |= rm->pcm.fn;
-                          reg = pci_config_read32(rm->pcm.bus, dev, where);
+                            dev += offset_devfn;
+                          reg = pci_read_config32(rm->pcm.bus + offset_bus, dev, where);
                           reg &= rm->pcm.and;
                           reg |= rm->pcm.or + offset_pciio; 
-                          pci_config_write32(rm->pcm.bus, dev, where, reg);
+                          pci_write_config32(rm->pcm.bus, dev, where, reg);
 			}
 			break;
-		case IO8:
+		case TIO8:
 			{
                           u32 where;
                           u8 reg;
@@ -84,7 +86,7 @@
                           outb(reg, where);
 			}
 			break;
-		case IO32:
+		case TIO32:
 			{
                           u32 where;
                           u32 reg;

Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-08-05 02:48:54 UTC (rev 722)
@@ -17,6 +17,12 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
+
+/* Until we resolve a better way to do this, work around it with a value "too large to fail" */
+#warning clean up setting of DIMM_SOCKETS and NODE_NUMS
+#define DIMM_SOCKETS 4
+#define NODE_NUMS 16
+
 #define ROM_CODE_SEG		0x08
 #define ROM_DATA_SEG		0x10
 
@@ -347,6 +353,7 @@
 
 struct dimm_size {
         u8 per_rank; // it is rows + col + bank_lines + data lines */
+	u8 side1, side2;
         u8 rows;
         u8 col;
         u8 bank; //1, 2, 3 mean 2, 4, 8
@@ -370,11 +377,18 @@
 	u8 rsv[3];
 } __attribute__((packed));
 
+struct mem_controller {
+	unsigned node_id;
+	u32 f0, f1, f2, f3;
+	u32 channel0[DIMM_SOCKETS];
+	u32 channel1[DIMM_SOCKETS];
+};
+
 struct link_pair_st {
-        struct device * udev;
+  u32 udev;
         u32 upos;
         u32 uoffs;
-        struct device * dev;
+        u32 dev;
         u32 pos;
         u32 offs;
 

Modified: coreboot-v3/include/arch/x86/amd/k8/raminit.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/raminit.h	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/include/arch/x86/amd/k8/raminit.h	2008-08-05 02:48:54 UTC (rev 722)
@@ -8,7 +8,7 @@
 #define DIMM_SOCKETS 4
 struct mem_controller {
 	unsigned node_id;
-	struct device *f0, *f1, *f2, *f3;
+	u32 f0, f1, f2, f3;
 	u16 channel0[DIMM_SOCKETS];
 	u16 channel1[DIMM_SOCKETS];
 };

Modified: coreboot-v3/include/arch/x86/cpu.h
===================================================================
--- coreboot-v3/include/arch/x86/cpu.h	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/include/arch/x86/cpu.h	2008-08-05 02:48:54 UTC (rev 722)
@@ -211,9 +211,9 @@
  * there are tables that are combinations of all three (or the code supports it anyway)
  */
 /* types of resource maps */
-#define PCIRM	'p'
-#define IO8	'8'
-#define IO32	'I'
+#define TPCIRM	'p'
+#define TIO8	'8'
+#define TIO32	'I'
 
 /* pci config map */
 struct pcm {
@@ -234,9 +234,9 @@
 
 
 /* convenience initializer */
-#define PCM(abus,adev,afn,areg,aand,aor) {.type = PCIRM, {.pcm ={.bus=abus,.dev=adev,.fn=afn,.reg=areg,.and=aand,.or=aor}}}
-#define EIO8(aport, aand, aor) {.type=IO8, {.io8 = {.port = aport, .and = aand, .or = aor}}}
-#define EIO32(aport, aand, aaor) {.type = IO32, {.io32 = {.port = aport, .and = aand, .or = aor}}}
+#define PCM(abus,adev,afn,areg,aand,aor) {.type = TPCIRM, {.pcm ={.bus=abus,.dev=adev,.fn=afn,.reg=areg,.and=aand,.or=aor}}}
+#define IO8(aport, aand, aor) {.type=TIO8, {.io8 = {.port = aport, .and = aand, .or = aor}}}
+#define IO32(aport, aand, aor) {.type = TIO32, {.io32 = {.port = aport, .and = aand, .or = aor}}}
 struct rmap {
 	int type;
 	union {

Modified: coreboot-v3/mainboard/gigabyte/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/Kconfig	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/mainboard/gigabyte/Kconfig	2008-08-05 02:48:54 UTC (rev 722)
@@ -29,7 +29,7 @@
 	select OPTION_TABLE
 	select CPU_AMD_K8
 	select NORTHBRIDGE_AMD_K8
-#	select SOUTHBRIDGE_NVIDIA_MCP55
+	select SOUTHBRIDGE_NVIDIA_MCP55
 	select SUPERIO_ITE_IT8716F
 	help
 	  Gigabyte M57SLI

Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-05 02:48:54 UTC (rev 722)
@@ -36,7 +36,6 @@
 #include <spd.h>
 #include <cpu.h>
 #include <msr.h>
-#include <amd/k8/raminit.h>
 #include <amd/k8/k8.h>
 #include <amd/k8/sysconf.h>
 #include <device/pci.h>
@@ -56,13 +55,13 @@
 extern const struct pci_bus_operations pci_cf8_conf1;
 static void hard_reset(void);
 
-#define pci_config_read32(bus, dev, where) pci_cf8_conf1.read32(NULL,  bus, dev, where)
-#define pci_config_write32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
+#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL,  bus, dev, where)
+#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
 
 
 static int controller_present(const struct mem_controller *ctrl)
 {
-        return pci_config_read32(0, ctrl->f0, 0) == 0x11001022;
+        return pci_read_config32(0, ctrl->f0, 0) == 0x11001022;
 }
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
@@ -551,8 +550,8 @@
 static void hw_enable_ecc(const struct mem_controller *ctrl)
 {
 	u32 dcl, nbcap, opt = 1;
-	nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
-	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+	nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
+	dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_DimmEccEn;
 	if (nbcap & NBCAP_ECC) {
 		dcl |= DCL_DimmEccEn;
@@ -560,14 +559,14 @@
 	if (get_option(&opt, "ECC_memory") || opt) {
 		dcl &= ~DCL_DimmEccEn;
 	}
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	
 }
 
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
 	u32 dcl;
-	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	return dcl & DCL_128BitEn;
 }
 
@@ -579,7 +578,7 @@
 	 */
 #warning "FIXME: Implement a better test for Opterons"
 	u32 nbcap;
-	nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
+	nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
 	return !!(nbcap & NBCAP_128Bit);
 }
 
@@ -590,7 +589,7 @@
 	 * This function must be called after spd_handle_unbuffered_dimms.
 	 */
 	u32 dcl;
-	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	return !(dcl & DCL_UnBufDimm);
 }
 
@@ -722,25 +721,25 @@
 	base1 &= ~0x001ffffe;
 
 	/* Set the appropriate DIMM base address register */
-	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
-	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+	pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
+	pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
 #if QRANK_DIMM_SUPPORT == 1
 	if(sz.rank == 4) {
-		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
-		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
+		pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
+		pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
 	}
 #endif
 
 	/* Enable the memory clocks for this DIMM */
 	if (base0) {
-		dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+		dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 		dch |= DCH_MEMCLK_EN0 << index;
 #if QRANK_DIMM_SUPPORT == 1
 		if(sz.rank == 4) {
 			dch |= DCH_MEMCLK_EN0 << (index + 2);
 		}
 #endif
-		pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+		pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 	}
 }
 
@@ -756,7 +755,7 @@
 	u32 map;
 	u32 dch;
 
-	map = pci_config_read32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
+	map = pci_read_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
 	map &= ~(0xf << (index * 4));
 #if QRANK_DIMM_SUPPORT == 1
         if(sz.rank == 4) {
@@ -785,7 +784,7 @@
 		}
 	}
 
-	pci_config_write32(0, ctrl->f2, DRAM_BANK_ADDR_MAP, map);
+	pci_write_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP, map);
 	
 }
 
@@ -832,8 +831,8 @@
 	limit_reg = 0x44 + index;
 	base_reg = 0x40 + index;
 	for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) {
-		pci_config_write32(0, device, limit_reg, limit);
-		pci_config_write32(0, device, base_reg, base);
+		pci_write_config32(0, device, limit_reg, limit);
+		pci_write_config32(0, device, base_reg, base);
 	}
 }
 
@@ -918,7 +917,7 @@
 		unsigned cs_mode;
 		u32 value;
 		
-		value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
+		value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
 		
 		/* Is it enabled? */
 		if (!(value & 1)) {
@@ -934,7 +933,7 @@
 			return 0;
 		}
 
-		value = pci_config_read32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
+		value = pci_read_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
                 cs_mode =( value >> ((index>>1)*4)) & 0xf;
                 if(cs_mode == 0 ) continue;
                 if(common_cs_mode == 0) {
@@ -987,13 +986,13 @@
 	for(index = 0; index < 8; index++) {
 		u32 value;
 
-		value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
+		value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
 		/* Is it enabled? */
 		if (!(value & 1)) {
 			continue;
 		}
-		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
-		pci_config_write32(0, ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
+		pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
+		pci_write_config32(0, ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
 		csbase += csbase_inc;
 	}
 	
@@ -1018,7 +1017,7 @@
 		candidate = 0;
 		for(index = 0; index < 8; index++) {
 			u32 value;
-			value = pci_config_read32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
+			value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
 
 			/* Is it enabled? */
 			if (!(value & 1)) {
@@ -1060,9 +1059,9 @@
 		csmask |= 0xfe00;		/* For now don't optimize */
 
 		/* Write the new base register */
-		pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
+		pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
 		/* Write the new mask register */
-		pci_config_write32(0, ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
+		pci_write_config32(0, ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
 		
 	}
 	/* Return the memory size in K */
@@ -1079,10 +1078,10 @@
 		u32 limit, base;
 		unsigned index;
 		index = node_id << 3;
-		base = pci_config_read32(0, ctrl->f1, 0x40 + index);
+		base = pci_read_config32(0, ctrl->f1, 0x40 + index);
 		/* Only look at the limit if the base is enabled */
 		if ((base & 3) == 3) {
-			limit = pci_config_read32(0, ctrl->f1, 0x44 + index);
+			limit = pci_read_config32(0, ctrl->f1, 0x44 + index);
 			end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 		}
 	}
@@ -1113,8 +1112,8 @@
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
 {
 	printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index); 
-	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
-	pci_config_write32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
+	pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
+	pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
 	dimm_mask &= ~(1 << index);
 	return dimm_mask;
 }
@@ -1150,7 +1149,7 @@
 		die("Mixed buffered and registered dimms not supported");
 	}
 
-	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_UnBufDimm;
 	if (unbuffered) {
 		if ((has_dualch) && (!is_cpu_pre_d0())) {
@@ -1166,7 +1165,7 @@
 			dcl |= DCL_UnBufDimm;
 		}
 	}
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	if (is_registered(ctrl)) {
 		printk(BIOS_DEBUG, "Registered\n");
 	} else {
@@ -1234,7 +1233,7 @@
 		goto single_channel;
 	}
 	/* If the cpu is not capable of doing dual channels don't do dual channels */
-	nbcap = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
+	nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
 	if (!(nbcap & NBCAP_128Bit)) {
 		goto single_channel;
 	}
@@ -1266,10 +1265,10 @@
 	}
 	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	u32 dcl;
-	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_32ByteEn;
 	dcl |= DCL_128BitEn;
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	return dimm_mask;
  single_channel:
 	dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
@@ -1390,7 +1389,7 @@
 		[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
 	};
 
-	value = pci_config_read32(0, ctrl->f3, NORTHBRIDGE_CAP);
+	value = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
 
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
 
@@ -1541,7 +1540,7 @@
 	result.param = get_mem_param(min_cycle_time);
 
 	/* Update DRAM Config High with our selected memory speed */
-	value = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+	value = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
 #if 0
 	/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed 
@@ -1555,14 +1554,14 @@
 #endif
 
 	value |= result.param->dch_memclk;
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, value);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, value);
 
 	static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
 	/* Update DRAM Timing Low with our selected cas latency */
-	value = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	value = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
 	value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, value);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, value);
 	
 	result.dimm_mask = dimm_mask;
 	return result;
@@ -1591,14 +1590,14 @@
 		return 0;
 	}
 
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
 	dtl |=	((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1619,14 +1618,14 @@
 	if (clocks > DTL_TRFC_MAX) {
 		return 0;
 	}
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
 	dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1645,14 +1644,14 @@
 	if (clocks > DTL_TRCD_MAX) {
 		return 0;
 	}
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
 	dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1670,14 +1669,14 @@
 	if (clocks > DTL_TRRD_MAX) {
 		return 0;
 	}
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
 	dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1695,14 +1694,14 @@
 	if (clocks > DTL_TRAS_MAX) {
 		return 0;
 	}
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
 	dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
@@ -1720,34 +1719,34 @@
 	if (clocks > DTL_TRP_MAX) {
 		return 0;
 	}
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
 	if (old_clocks > clocks) {
 		clocks = old_clocks;
 	}
 	dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
 	dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 	return 1;
 }
 
 static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	u32 dtl;
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
 	dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
 }
 
 
 static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	u32 dth;
-	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
 	dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 }
 
 static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
@@ -1764,7 +1763,7 @@
 		tref = param->dch_tref4k;
 	}
 
-	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
 	if ((value == 12) && (old_tref == param->dch_tref4k)) {
 		tref = param->dch_tref4k;
@@ -1773,7 +1772,7 @@
 	}
 	dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
 	dth |= (tref << DTH_TREF_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 	return 1;
 }
 
@@ -1804,12 +1803,12 @@
 		dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
 	}
 #endif
-	dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+	dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~dimm;
 	if (value == 4) {
 		dcl |= dimm;
 	}
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	return 1;
 }
 
@@ -1822,9 +1821,9 @@
 		return -1;
 	}
 	if (value != 2) {
-		dcl = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_LOW);
+		dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
 		dcl &= ~DCL_DimmEccEn;
-		pci_config_write32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
+		pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
 	}
 	return 1;
 }
@@ -1836,7 +1835,7 @@
 	dimms = 0;
 	for(index = 0; index < 8; index += 2) {
 		u32 csbase;
-		csbase = pci_config_read32(0, ctrl->f2, (DRAM_CSBASE + (index << 2)));
+		csbase = pci_read_config32(0, ctrl->f2, (DRAM_CSBASE + (index << 2)));
 		if (csbase & 1) {
 			dimms += 1;
 		}
@@ -1848,10 +1847,10 @@
 {
 	u32 dth;
 
-	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
 	dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 }
 
 static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1862,7 +1861,7 @@
 	int lat, mtype;
 
 	clocks = 0;
-	dtl = pci_config_read32(0, ctrl->f2, DRAM_TIMING_LOW);
+	dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
 	latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
 
 	if (is_opteron(ctrl)) {
@@ -1892,10 +1891,10 @@
 		die("Unknown Trwt\n");
 	}
 	
-	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
 	dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 	return;
 }
 
@@ -1909,10 +1908,10 @@
 	} else {
 		clocks = 1;
 	}
-	dth = pci_config_read32(0, ctrl->f2, DRAM_TIMING_HIGH);
+	dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
 	dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
 	dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
+	pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
 }
 
 
@@ -1943,7 +1942,7 @@
 		die("Unknown rdpreamble for this nr of slots");
 	}
 
-	dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+	dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
 	rdpreamble = param->rdpreamble[i];
 
@@ -1952,7 +1951,7 @@
 	}
 
 	dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1963,7 +1962,7 @@
 
 	dimms = count_dimms(ctrl);
 
-	dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+	dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
 	async_lat = 0;
 	if (is_registered(ctrl)) {
@@ -1990,18 +1989,18 @@
 		}
 	}
 	dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
 static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
 {
 	u32 dch;
 	/* AMD says to Hardcode this */
-	dch = pci_config_read32(0, ctrl->f2, DRAM_CONFIG_HIGH);
+	dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
 	dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
 	dch |= DCH_DYN_IDLE_CTR_EN;
-	pci_config_write32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
+	pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
 static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
@@ -2107,22 +2106,22 @@
         carry_over = (4*1024*1024) - hole_startk;
 
         for(ii=controllers - 1;ii>i;ii--) {
-                base  = pci_config_read32(0, ctrl[0].f1, 0x40 + (ii << 3));
+                base  = pci_read_config32(0, ctrl[0].f1, 0x40 + (ii << 3));
                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
                         continue;
                 }
-		limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (ii << 3));
+		limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (ii << 3));
                 for(j = 0; j < controllers; j++) {
-                        pci_config_write32(0, ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
-                        pci_config_write32(0, ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
+                        pci_write_config32(0, ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
+                        pci_write_config32(0, ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
                 }
         }
-        limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (i << 3));
+        limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (i << 3));
         for(j = 0; j < controllers; j++) {
-                pci_config_write32(0, ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
+                pci_write_config32(0, ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
         }
         dev = ctrl[i].f1;
-        base  = pci_config_read32(0, dev, 0x40 + (i << 3));
+        base  = pci_read_config32(0, dev, 0x40 + (i << 3));
         basek  = (base & 0xffff0000) >> 2;
         if(basek == hole_startk) {
                 //don't need set memhole here, because hole off set will be 0, overflow
@@ -2130,7 +2129,7 @@
                 base &= 0x0000ffff;
                 base |= (4*1024*1024)<<2;
                 for(j = 0; j < controllers; j++) {
-                        pci_config_write32(0, ctrl[j].f1, 0x40 + (i<<3), base);
+                        pci_write_config32(0, ctrl[j].f1, 0x40 + (i<<3), base);
                 }
         }
 	else {
@@ -2140,7 +2139,7 @@
         	        (((basek + carry_over) >> 6) & 0x0000ff00) +
                 	/* enable */
 	                1;
-	        pci_config_write32(0, dev, 0xf0, hoist);
+	        pci_write_config32(0, dev, 0xf0, hoist);
 	}
 
         return carry_over;
@@ -2164,7 +2163,7 @@
         for(i=0; i<controllers; i++) {
                         u32 base;
                         unsigned base_k;
-                        base  = pci_config_read32(0, ctrl[0].f1, 0x40 + (i << 3));
+                        base  = pci_read_config32(0, ctrl[0].f1, 0x40 + (i << 3));
                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
                                 continue;
                         }
@@ -2184,11 +2183,11 @@
         for(i=0; i<controllers; i++) {
                         u32 base, limit;
                         unsigned base_k, limit_k;
-                        base  = pci_config_read32(0, ctrl[0].f1, 0x40 + (i << 3));
+                        base  = pci_read_config32(0, ctrl[0].f1, 0x40 + (i << 3));
                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
                                 continue;
                         }
-                        limit = pci_config_read32(0, ctrl[0].f1, 0x44 + (i << 3));
+                        limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (i << 3));
                         base_k = (base & 0xffff0000) >> 2;
                         limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 			if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
@@ -2219,17 +2218,17 @@
 		u32 dch;
 		if (!controller_present(ctrl + i))
 			continue;
-		dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
+		dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
 		if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
 			dch |= DCH_MEMCLK_VALID;
-			pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
+			pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
 		}
 		else {
 			/* Disable dram receivers */
 			u32 dcl;
-			dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+			dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 			dcl |= DCL_DisInRcvrs;
-			pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+			pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 		}
 	}
 
@@ -2243,31 +2242,31 @@
 		if (!controller_present(ctrl + i))
 			continue;
 		/* Skip everything if I don't have any memory on this controller */
-		dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
+		dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
 		if (!(dch & DCH_MEMCLK_VALID)) {
 			continue;
 		}
 
 		/* Toggle DisDqsHys to get it working */
-		dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+		dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			u32 mnc;
 			printk(BIOS_SPEW, "ECC enabled\n");
-			mnc = pci_config_read32(0, ctrl[i].f3, MCA_NB_CONFIG);
+			mnc = pci_read_config32(0, ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_128BitEn) {
 				mnc |= MNC_CHIPKILL_EN;
 			}
-			pci_config_write32(0, ctrl[i].f3, MCA_NB_CONFIG, mnc);
+			pci_write_config32(0, ctrl[i].f3, MCA_NB_CONFIG, mnc);
 		}
 		dcl |= DCL_DisDqsHys;
-		pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 		dcl &= ~DCL_DisDqsHys;
 		dcl &= ~DCL_DLL_Disable;
 		dcl &= ~DCL_D_DRV;
 		dcl &= ~DCL_QFC_EN;
 		dcl |= DCL_DramInit;
-		pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+		pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 
 	}
 	for(i = 0; i < controllers; i++) {
@@ -2275,7 +2274,7 @@
 		if (!controller_present(ctrl + i))
 			continue;
 		/* Skip everything if I don't have any memory on this controller */
-		dch = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
+		dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
 		if (!(dch & DCH_MEMCLK_VALID)) {
 			continue;
 		}
@@ -2284,7 +2283,7 @@
 
 		int loops = 0;
 		do {
-			dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+			dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops += 1;
 			if ((loops & 1023) == 0) {
 				printk(BIOS_DEBUG, ".");
@@ -2298,9 +2297,9 @@
 		if (!is_cpu_pre_c0()) {
 			/* Wait until it is safe to touch memory */
 			dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
-			pci_config_write32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+			pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 			do {
-				dcl = pci_config_read32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
+				dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
 			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
 		}
 

Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-08-05 01:24:38 UTC (rev 721)
+++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c	2008-08-05 02:48:54 UTC (rev 722)
@@ -23,10 +23,11 @@
 #include <io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
+#include <cpu.h>
 #include <amd/k8/k8.h>
 #include "mcp55.h"
+#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
+#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
 
 #warning fix disgusting define of MCP55_NUM it is mainboard dependent
 #define MCP55_NUM 1
@@ -107,35 +108,33 @@
 
 static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
 {
-
-	static const unsigned int ctrl_devport_conf[] = {
-		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
-		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
+	static const struct rmap ctrl_devport_conf[] = {
+	PCM(0, 1, 1, ANACTRL_REG_POS, ~0x0000ff00, ANACTRL_IO_BASE),
+	PCM(0, 1, 1, SYSCTRL_REG_POS, ~0x0000ff00, SYSCTRL_IO_BASE),
+	PCM(0, 1, 1, ACPICTRL_REG_POS, ~0x0000ff00, ACPICTRL_IO_BASE),
 	};
 
 	int j;
 	for(j = 0; j < mcp55_num; j++ ) {
-		setup_resource_map_offset(ctrl_devport_conf,
+		setup_resource_map_x_offset(ctrl_devport_conf,
 			sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
-			PCI_BDF(busn[j], devn[j], 0) , io_base[j]);
+			PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0);
 	}
 }
-
 static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
 {
 
-	static const unsigned int ctrl_devport_conf_clear[] = {
-		PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
-		PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
+	static const struct rmap ctrl_devport_conf_clear[] = {
+	PCM(0, 1, 1, ANACTRL_REG_POS, ~0x0000ff00, 0),
+	PCM(0, 1, 1, SYSCTRL_REG_POS, ~0x0000ff00, 0),
+	PCM(0, 1, 1, ACPICTRL_REG_POS, ~0x0000ff00, 0),
 	};
 
 	int j;
 	for(j = 0; j < mcp55_num; j++ ) {
-		setup_resource_map_offset(ctrl_devport_conf_clear,
+		setup_resource_map_x_offset(ctrl_devport_conf_clear,
 			sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
-			PCI_BDF(busn[j], devn[j], 0) , io_base[j]);
+			PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0);
 	}
 
 
@@ -155,13 +154,11 @@
 	u32 pll_ctrl;
 	u32 dword;
 	int i;
-	//struct device dev;
-	struct device *dev;
-#error dev is not set up
+	u32 dev;
 	//	dev = PCI_BDF(busnx, devnx+1, 1);
-	dword = pci_read_config32(dev, 0xe4);
+	dword = pci_read_config32(busnx, (devnx+1)<<3 | 1, 0xe4);
 	dword |= 0x3f0; // disable it at first
-	pci_write_config32(dev, 0xe4, dword);
+	pci_write_config32(busnx,  (devnx+1)<<3 | 1, 0xe4, dword);
 
 	for(i=0; i<3; i++) {
 		tgio_ctrl = inl(anactrl_io_base + 0xcc);
@@ -183,9 +180,9 @@
 //	wait 100us
 	delayx(1);
 
-	dword = pci_read_config32(dev, 0xe4);
+	dword = pci_read_config32(busnx,  (devnx+1)<<3 | 1, 0xe4);
 	dword &= ~(0x3f0); // enable
-	pci_write_config32(dev, 0xe4, dword);
+	pci_write_config32(busnx,  (devnx+1)<<3 | 1, 0xe4, dword);
 
 //	need to wait 100ms
 	delayx(1000);
@@ -194,102 +191,100 @@
 static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
 {
 
-    static const unsigned int ctrl_conf_1[] = {
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
+    static const struct rmap ctrl_conf_1[] = {
+	IO32(ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000),
+	IO32(ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000),
+	IO32(ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200),
+	IO32(ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002),
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
+	IO32(ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230),
+	IO32(ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222),
+	IO32(ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000),
+	IO32(ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000),
+	IO32(ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000),
+	IO32(ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000),
+	IO32(ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200),
+	IO32(ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000),
+	IO32(ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400),
+	IO32(ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000),
+	IO32(ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000),
+	IO32(ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010),
+	IO32(ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500),
+	IO32(ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000),
+	IO32(ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000),
+	IO32(ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00),
+	IO32(ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000),
 
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
+	PCM(0, 0, 0, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 0, 0, 0x48, 0xFFFFDCED, 0x00002002), 
+	PCM(0, 0, 0, 0x78, 0xFFFFFF8E, 0x00000011), 
+	PCM(0, 0, 0, 0x80, 0xFFFF0000, 0x00009923), 
+	PCM(0, 0, 0, 0x88, 0xFFFFFFFE, 0x00000000), 
+	PCM(0, 0, 0, 0x8C, 0xFFFF0000, 0x0000007F), 
+	PCM(0, 0, 0, 0xDC, 0xFFFEFFFF, 0x00010000), 
 
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+	PCM(0, 1, 0, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 1, 0, 0x74, 0xFFFFFF7B, 0x00000084), 
+	PCM(0, 1, 0, 0xF8, 0xFFFFFFCF, 0x00000010), 
 
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+	PCM(0, 1, 1, 0xC4, 0xFFFFFFFE, 0x00000001), 
+	PCM(0, 1, 1, 0xF0, 0x7FFFFFFD, 0x00000002), 
+	PCM(0, 1, 1, 0xF8, 0xFFFFFFCF, 0x00000010), 
 
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
-	RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+	PCM(0, 8, 0, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 8, 0, 0x68, 0xFFFFFF00, 0x000000FF), 
+	PCM(0, 8, 0, 0xF8, 0xFFFFFFBF, 0x00000040), //Enable bridge mode
 
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
-	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
+	PCM(0, 9, 0, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 9, 0, 0x68, 0xFFFFFF00, 0x000000FF), 
+	PCM(0, 9, 0, 0xF8, 0xFFFFFFBF, 0x00000040), //Enable bridge mode
     };
 
-    static const unsigned int ctrl_conf_1_1[] = {
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
-	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
+    static const struct rmap ctrl_conf_1_1[] = {
+	PCM(0, 5, 0, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 5, 0, 0x50, 0xFFFFFFFC, 0x00000003), 
+	PCM(0, 5, 0, 0x64, 0xFFFFFFFE, 0x00000001), 
+	PCM(0, 5, 0, 0x70, 0xFFF0FFFF, 0x00040000), 
+	PCM(0, 5, 0, 0xAC, 0xFFFFF0FF, 0x00000100), 
+	PCM(0, 5, 0, 0x7C, 0xFFFFFFEF, 0x00000000), 
+	PCM(0, 5, 0, 0xC8, 0xFF00FF00, 0x000A000A), 
+	PCM(0, 5, 0, 0xD0, 0xF0FFFFFF, 0x03000000), 
+	PCM(0, 5, 0, 0xE0, 0xF0FFFFFF, 0x03000000), 
     };
 
+    static const struct rmap ctrl_conf_mcp55_only[] = {
+	PCM(0, 1, 1, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 1, 1, 0xE0, 0xFFFFFEFF, 0x00000000), 
+	PCM(0, 1, 1, 0xE4, 0xFFFFFFFB, 0x00000000), 
+	PCM(0, 1, 1, 0xE8, 0xFFA9C8FF, 0x00003000), 
 
-    static const unsigned int ctrl_conf_mcp55_only[] = {
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
+	PCM(0, 4, 0, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 4, 0, 0xF8, 0xFFFFFFCF, 0x00000010), 
 
-	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
+	PCM(0, 2, 0, 0x40, 0x00000000, 0xCB8410DE), 
 
-	RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
+	PCM(0, 2, 1, 0x40, 0x00000000, 0xCB8410DE), 
+	PCM(0, 2, 1, 0x64, 0xF87FFFFF, 0x05000000), 
+	PCM(0, 2, 1, 0x78, 0xFFC07FFF, 0x00360000), 
+	PCM(0, 2, 1, 0x68, 0xFE00D03F, 0x013F2C00), 
+	PCM(0, 2, 1, 0x70, 0xFFF7FFFF, 0x00080000), 
+	PCM(0, 2, 1, 0x7C, 0xFFFFF00F, 0x00000570), 
+	PCM(0, 2, 1, 0xF8, 0xFFFFFFCF, 0x00000010), 
 
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
-	RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
+	PCM(0, 6, 0, 0x04, 0xFFFFFEFB, 0x00000104), 
+	PCM(0, 6, 0, 0x3C, 0xF5FFFFFF, 0x0A000000), 
+	PCM(0, 6, 0, 0x40, 0x00C8FFFF, 0x07330000), 
+	PCM(0, 6, 0, 0x48, 0xFFFFFFF8, 0x00000005), 
+	PCM(0, 6, 0, 0x4C, 0xFE02FFFF, 0x004C0000), 
+	PCM(0, 6, 0, 0x74, 0xFFFFFFC0, 0x00000000), 
+	PCM(0, 6, 0, 0xC0, 0x00000000, 0xCB8410DE), 
+	PCM(0, 6, 0, 0xC4, 0xFFFFFFF8, 0x00000007), 
 
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
-	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
-
+	PCM(0, 1, 0, 0x78, 0xC0FFFFFF, 0x19000000), 
 #if MCP55_USE_AZA == 1
-	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
+	PCM(0, 6, 1, 0x40, 0x00000000, 0xCB8410DE), 
 
-//	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
+//	PCM(0, 1, 1, 0xE4), ~(1<<14, 1<<14)),
 #endif
 // play a while with GPIO in MCP55
 #ifdef MCP55_MB_SETUP
@@ -297,39 +292,39 @@
 #endif
 
 #if MCP55_USE_AZA == 1
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
+	IO8(SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2)),
+	IO8(SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2)),
+	IO8(SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2)),
 #endif
 
 
     };
 
-    static const unsigned int ctrl_conf_master_only[] = {
+    static const struct rmap ctrl_conf_master_only[] = {
 
-	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
+	IO32(ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000),
 
 	//Master MCP55 ????YHLU
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
+	IO8( SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2)),
 
     };
 
-    static const unsigned int ctrl_conf_2[] = {
+    static const struct rmap ctrl_conf_2[] = {
 	/* I didn't put pcie related stuff here */
 
-	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
+	PCM(0, 0, 0, 0x74, 0xFFFFF00F, 0x000009D0),
+	PCM(0, 1, 0, 0x74, 0xFFFF7FFF, 0x00008000),
 
-	RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
+	IO32(SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000),
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
+	IO32(ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012),
 
 
 #if MCP55_USE_NIC == 1
-	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
+	PCM(0, 1, 1, 0xe4, ~((1<<22)|(1<<20)), (1<<22)|(1<<20)),
 
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(0<<0)),
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(1<<0)),
+	IO8(SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(0<<0))),
+	IO8(SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff),  ((0<<4)|(1<<2)|(1<<0))),
 #endif
 
     };
@@ -341,23 +336,23 @@
 		mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
 
 		setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
-				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
 		for(i=0; i<3; i++) { // three SATA
 			setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
-				PCI_BDF(busn[j], devn[j], i), io_base[j]);
+				PCI_BDF(busn[j], devn[j], i), io_base[j], 0);
 		}
 		if(busn[j] == 0) {
 			setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
-				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
 		}
 
 		if( (busn[j] == 0) && (mcp55_num>1) ) {
 			setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
-				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
 		}
 
 		setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
-				PCI_BDF(busn[j], devn[j], 0), io_base[j]);
+				PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
 
 	}
 
@@ -408,10 +403,8 @@
 		busnx = ht_c_index * HT_CHAIN_BUSN_D;
 		for(devnx=0;devnx<0x20;devnx++) {
 			u32 id;
-			struct device *dev;
-#error dev is not set up
 			//			dev = PCI_BDF(busnx, devnx, 0);
-			id = pci_read_config32(dev, PCI_VENDOR_ID);
+			id = pci_read_config32(busnx, devnx<<3, PCI_VENDOR_ID);
 			if(id == 0x036910de) {
 				busn[mcp55_num] = busnx;
 				devn[mcp55_num] = devnx;




From rminnich at gmail.com  Tue Aug  5 04:50:55 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 19:50:55 -0700
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <20080805024654.30068.qmail@stuge.se>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<20080805024654.30068.qmail@stuge.se>
Message-ID: <13426df10808041950kfb522e3h6ba682c8b9100bd1@mail.gmail.com>

Committed revision 722.

Thanks. Will continue to fill it out tomorrow.

ron



From peter at stuge.se  Tue Aug  5 04:56:06 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Aug 2008 04:56:06 +0200
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <13426df10808041950kfb522e3h6ba682c8b9100bd1@mail.gmail.com>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<20080805024654.30068.qmail@stuge.se>
	<13426df10808041950kfb522e3h6ba682c8b9100bd1@mail.gmail.com>
Message-ID: <20080805025606.1296.qmail@stuge.se>

On Mon, Aug 04, 2008 at 07:50:55PM -0700, ron minnich wrote:
> Committed revision 722.
> 
> Thanks. Will continue to fill it out tomorrow.

mainboard/gigabyte/m57sli/cmos.layout is missing


//Peter



From peter at stuge.se  Tue Aug  5 04:57:46 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Aug 2008 04:57:46 +0200
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <20080805025606.1296.qmail@stuge.se>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<20080805024654.30068.qmail@stuge.se>
	<13426df10808041950kfb522e3h6ba682c8b9100bd1@mail.gmail.com>
	<20080805025606.1296.qmail@stuge.se>
Message-ID: <20080805025746.1662.qmail@stuge.se>

On Tue, Aug 05, 2008 at 04:56:06AM +0200, Peter Stuge wrote:
> mainboard/gigabyte/m57sli/cmos.layout is missing

I once again commented out mcp55 to see how far it would go;

  DTC     build/statictree.h
  DTC     mainboard/gigabyte/m57sli/dts (dts->lbh)
  CC      build/superio/ite/it8716f/stage1.o
  CC      build/device/pnp_raw.o
  CC      build/stage0.init
/usr/lib/gcc/i686-pc-linux-gnu/4.2.2/../../../../i686-pc-linux-gnu/bin/as: /unrecognized option '-T'
make: *** [/home/stuge/co/v3/build/stage0.init] Error 1


//Peter



From svn at coreboot.org  Tue Aug  5 04:59:00 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 Aug 2008 04:59:00 +0200
Subject: [coreboot] r723 - coreboot-v3/mainboard/gigabyte/m57sli
Message-ID: <mailman.1785.1355071350.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-08-05 04:59:00 +0200 (Tue, 05 Aug 2008)
New Revision: 723

Added:
   coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout
Log:
trivial forgot to add it
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Added: coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout	                        (rev 0)
+++ coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout	2008-08-05 02:59:00 UTC (rev 723)
@@ -0,0 +1,119 @@
+## 
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+




From rminnich at gmail.com  Tue Aug  5 04:59:59 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 19:59:59 -0700
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <20080805025746.1662.qmail@stuge.se>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<20080805024654.30068.qmail@stuge.se>
	<13426df10808041950kfb522e3h6ba682c8b9100bd1@mail.gmail.com>
	<20080805025606.1296.qmail@stuge.se>
	<20080805025746.1662.qmail@stuge.se>
Message-ID: <13426df10808041959n11791d9o7cf5f7b6f40a3876@mail.gmail.com>

On Mon, Aug 4, 2008 at 7:57 PM, Peter Stuge <peter at stuge.se> wrote:
> On Tue, Aug 05, 2008 at 04:56:06AM +0200, Peter Stuge wrote:
>> mainboard/gigabyte/m57sli/cmos.layout is missing
>
> I once again commented out mcp55 to see how far it would go;
>
>  DTC     build/statictree.h
>  DTC     mainboard/gigabyte/m57sli/dts (dts->lbh)
>  CC      build/superio/ite/it8716f/stage1.o
>  CC      build/device/pnp_raw.o
>  CC      build/stage0.init
> /usr/lib/gcc/i686-pc-linux-gnu/4.2.2/../../../../i686-pc-linux-gnu/bin/as: /unrecognized option '-T'
> make: *** [/home/stuge/co/v3/build/stage0.init] Error 1
>

can you run
make Q=  V=1

thanks

ron



From rminnich at gmail.com  Tue Aug  5 05:49:08 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Aug 2008 20:49:08 -0700
Subject: [coreboot] help with K8
Message-ID: <13426df10808042049v3ff00e6uc17f83d45e4289fc@mail.gmail.com>

I can always use good help :=)

anyone want to look at this?
  HOSTCC  build/util/options/build_opt_tbl
  OPTIONS build/mainboard/gigabyte/m57sli/option_table.c
Error - Range end (122) does not match define (125) in line
checksum 392 983 984

I don't even understand the error ... in line ?

ron



From zrfail at gmail.com  Tue Aug  5 06:44:55 2008
From: zrfail at gmail.com (Zhang Rui)
Date: Tue, 5 Aug 2008 12:44:55 +0800
Subject: [coreboot] Minimal seabios for coreboot
In-Reply-To: <20080722030921.GA26108@morn.localdomain>
References: <20080722030921.GA26108@morn.localdomain>
Message-ID: <92cbc4c70808042144n7ea7b241g82fdcbe4c3777abd@mail.gmail.com>

2008/7/22, Kevin O'Connor <kevin at koconnor.net>:
> Hi,
>
> Several people have raised the possibility of replacing the coreboot
> BIOS emulation for option roms with SeaBIOS.
[...]
> So, I can see a mode where coreboot would lzma uncompress a minimal
> seabios into 0xf0000, call into seabios, seabios would then init
> itself and return to coreboot.  Then coreboot would finish
> initialization and launch the payload from flash.
>
> I can see where the above would be useful if the payload is always
> coming out of flash.  However, if the user ever needs to boot using
> seabios (or via a scsi/pxe option rom) then I think seabios needs to
> be the payload and needs to drive the bootup.
>

so if I want to write the int13 for scsi booting, should I write
interrupt function in coreboot and inject it to int13, or just write
codes in seabios?

> If there is interest in doing this, we'll need to figure out how to
> work out the interactions.  Zhang Rui is currently working on having
> seabios return to coreboot.  As for code integration - I'd like to
> avoid forking the seabios code.  Perhaps it would be okay to simply
> copy a seabios binary into the svn repo with directions on how to
> build it manually.  (This is what qemu and bochs do for their bios
> blobs.)
>
Maybe this is the simplest way.



From zrfail at gmail.com  Tue Aug  5 06:50:54 2008
From: zrfail at gmail.com (Zhang Rui)
Date: Tue, 5 Aug 2008 12:50:54 +0800
Subject: [coreboot] How can I call the interrupt of SeaBIOS in coreboot?
In-Reply-To: <20080717020831.GE27822@morn.localdomain>
References: <92cbc4c70807150821l575ab6dg56ac82825cbe7fed@mail.gmail.com>
	<20080715173710.GB14605@morn.localdomain>
	<92cbc4c70807161858yb7a83e4i66eee86675f04660@mail.gmail.com>
	<20080717020831.GE27822@morn.localdomain>
Message-ID: <92cbc4c70808042150w45f30606p6a1f786bb81a0d31@mail.gmail.com>

Hello,
	I am blocked with calling interrupt in coreboot.
	I tryed these ways:
	1. use "asm("int $0x19 \n");".  Qemu has no output when executeed
here and nothing happens. The reason is that it should jump to real
mode before calling int 19.

	2. write a function boot_coreboot() in seabios. like:

	void VISIBLE32 boot_coreboot()
	{
		struct bregs br;
		dprintf(1, "boot_coreboot: begin\n");
		memset(&br, 0, sizeof(br));
		dprintf(1, "boot_coreboot: call int 19\n");
		call16_int(0x19, &br);
		dprintf(1, "boot_coreboot: end\n");
	}
	
	then call boot_coreboot() in seabios. It booted successfully.

	I have read the source code of call16_int, it jump to real mode and
jump to the int 19 handler function directly, but do not use "int
$0x19" asm code. why?



	3. write asm code to jump to real mode and call int 19.
	but in coreboot there is compiling errors when I write asm codes with
lables in it in vm86.c.
	for a simple example:
	__asm__ __volatile__ (
			/* paranoia -- does ecx get saved? not sure. This is
			 * the easiest safe thing to do. */
			"	pushal			\n"
			"	ljmp 	$0x28, $cbint16bit\n"
			"cbint16bit:		\n"
			"	.code16			\n"
			"	popal\n"
			);

	will cause errors:
	{standard input}: Assembler messages:
	{standard input}:746: Error: symbol `cbint16bit' is already defined
	
	in seabios there is compiling errors because of ".code16":
	out/../src/post.c:349: relocation truncated to fit: R_386_16 against `.text'

	what is wrong here?


2008/7/17, Kevin O'Connor <kevin at koconnor.net>:
> On Thu, Jul 17, 2008 at 09:58:59AM +0800, Zhang Rui wrote:
> [...]
> > If I manually change to 16bit mode then call int19 in coreboot,  will it be OK?
> > If it does, the 16bit mode option rom codes can use the int handler of SeaBIOS?
>
> It should work.
>



From klaus123 at ibnoetzold.de  Tue Aug  5 08:29:51 2008
From: klaus123 at ibnoetzold.de (Klaus Stammermann)
Date: Tue, 5 Aug 2008 08:29:51 +0200 (CEST)
Subject: [coreboot] Problems with newer revision
Message-ID: <4562.213.61.222.30.1217917791.squirrel@www.ibnoetzold.de>

Hi Peter

>On Mon, Aug 04, 2008 at 04:07:29PM +0200, Klaus Stammermann wrote:
>> I tried to use coreboot on VIA EPIA ME6000G. With revision 2184
>> system starts but with newest revision there are some problems.

>What problems?
Sorry, but at my last posting my email prog used wrong email adress. With
this adress I wrote my problems some time ago. I had to just irq polling
and the x-server couldn't find video card. For more information you could
look to mailing list.

>> I know you can't test new revisions with all boards,

>Actually there is infrastructure to do just that, but it's not super
>easy to integrate with yet.
No problem

>> but there where about 1300 new one. Does no one use this board or
>> is there no development for ME6000G anymore?

>I think both those statements are true. It's a rather old board. I
>had an EPIA-MII, but the caps blew and I haven't been able to source
>new ones easily enough.


>> Some information would be nice to see what I am going to do on my
>> project.

>I'm sorry, but I'm not sure what the problem is. Maybe it's
>acceptable for you to keep using the old revision? If not you'll of
>course have to rebase your local patch and help find the problem with
>newer revs on the board. Could you send your changes to the mailing
>list?

Maybe the old rev works so good I could use old sources. I will test and
look what changes could be interesting for me. If I will do changes on
sources to work better with coreboot on my board I will post these changes
here. But at first I have to look if anything important does not run.

Klaus



From arne.gleditsch at dolphinics.no  Tue Aug  5 09:27:47 2008
From: arne.gleditsch at dolphinics.no (Arne Georg Gleditsch)
Date: Tue, 05 Aug 2008 09:27:47 +0200
Subject: [coreboot] Fam10h support for Tyan S2912-E
In-Reply-To: <489735B0.2000701@amd.com> (Marc Jones's message of "Mon, 4 Aug
	2008 11:00:32 -0600")
References: <kjmvdyhug78.fsf@pelargir.dolphinics.no> <489735B0.2000701@amd.com>
Message-ID: <kjmej53vs3w.fsf@pelargir.dolphinics.no>

Marc Jones <Marc.Jones at amd.com> writes:
> Hi Arne,
>
> If you are prepared to do firmware development (socketed ROM, etc) the
> port should not be too difficult. The amd/serengeti_cheetah_fam10
> mainboard should be a good example to work from. It is helpful if you
> have access to motherboard and chipset documents.

I have a RD1-PMC4 BIOS savior from a previos project that I've installed
on the system.  The vendor BIOS is twice the size of the BIOS Savior
flash, but I'm not sure if this is important or not.  The BIOS Savior
has had coreboot installed previously.

I was kind of hoping that the presence of a regular S2912 port would
make the need for mb/chipset docs less pressing.  Pointers to relevant
docs would be much appreciated.  (I think I have most of what I need as
far as platform/AMD docs go.)

Do you think it would make more sense to start out from the
cheetah_fam10 codebase or the regular s2912 codebase?  My initial
impulse was to adapt the s2912 codebase according to the diff between
the cheetah and cheetah_fam10 targets and see how far that got me.

Thanks!

-- 
								Arne.



From yinghailu at gmail.com  Tue Aug  5 10:41:02 2008
From: yinghailu at gmail.com (yhlu)
Date: Tue, 5 Aug 2008 01:41:02 -0700
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
Message-ID: <2ea3fae10808050141qaa320bdr8ccb307326026f28@mail.gmail.com>

On Mon, Aug 4, 2008 at 7:38 PM, ron minnich <rminnich at gmail.com> wrote:
> Current state of tree. This all compiles with only errors for stuff
> not yet defined.
>
> Too many fixes in here to list them all :-)
> but:
> convert mcp55 over to new resource maps.
> fix my misunderstanding of one aspect of resource map setup
> Fix typo in config_{read,write} naming.
> Fix random mistakes in include files.
>
> YHLU: question: is REV F a proper superset of all K8? If we do REV F compatible
> code, and test for REV A-E in our coded and take appropriate action,
> will the code work properly? Can we have e.g.
> the same mem_controller struct for all K8?

No. REV A-E got DDR1. REV F got DDR2

>
> I'd like to avoid the files we had in v2 with stuff like xyz_f and
> just have one common set of K8 files.
> It's even ok if, e.g., there are struct members in the mem_controller
> struct that are only used on rev f
> or dual core, and unused otherwise. I'd like to simplify the tangle we
> had in v2.

YH



From peter at stuge.se  Tue Aug  5 14:40:39 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 Aug 2008 14:40:39 +0200
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <13426df10808041959n11791d9o7cf5f7b6f40a3876@mail.gmail.com>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<20080805024654.30068.qmail@stuge.se>
	<13426df10808041950kfb522e3h6ba682c8b9100bd1@mail.gmail.com>
	<20080805025606.1296.qmail@stuge.se>
	<20080805025746.1662.qmail@stuge.se>
	<13426df10808041959n11791d9o7cf5f7b6f40a3876@mail.gmail.com>
Message-ID: <20080805124039.29571.qmail@stuge.se>

On Mon, Aug 04, 2008 at 07:59:59PM -0700, ron minnich wrote:
> can you run
> make Q=  V=1

first plain:

$ make
  CP      build/config.h
  GEN     build/build.h
  HOSTCC  build/util/options/build_opt_tbl
  OPTIONS build/mainboard/gigabyte/m57sli/option_table.c
  CC      build/stage0.init
/usr/lib/gcc/i686-pc-linux-gnu/4.2.2/../../../../i686-pc-linux-gnu/bin/as: unrecognized option '-T'
make: *** [/home/stuge/co/v3/build/stage0.init] Error 1

then loud:

$ make Q= V=1
mkdir -p /home/stuge/co/v3/build
printf "  CP      build/config.h\n"
  CP      build/config.h
cp /home/stuge/co/v3/.tmpconfig.h /home/stuge/co/v3/build/config.h
printf "  GEN     build/build.h\n"
  GEN     build/build.h
printf "#define COREBOOT_VERSION \"3.0."722"\"\n" > /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_EXTRA_VERSION \"\"\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> /home/stuge/co/v3/build/build.h
printf "\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_COMPILER \"gcc (GCC) 4.2.2 (Gentoo 4.2.2 p1.0)\"\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_ASSEMBLER \"GNU assembler (GNU Binutils) 2.18\"\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_LINKER \"GNU ld (GNU Binutils) 2.18\"\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_COMPILE_BY \"stuge\"\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_COMPILE_HOST \"n410c\"\n" >> /home/stuge/co/v3/build/build.h
printf "#define COREBOOT_COMPILE_DOMAIN \"stuge.se\"\n" >> /home/stuge/co/v3/build/build.h
mkdir -p /home/stuge/co/v3/build/util/options/
printf "  HOSTCC  build/util/options/build_opt_tbl\n"
  HOSTCC  build/util/options/build_opt_tbl
gcc -Wall -Wstrict-prototypes -g -fomit-frame-pointer -Wno-unused -Wno-sign-compare -o /home/stuge/co/v3/build/util/options/build_opt_tbl /home/stuge/co/v3/build/util/options/build_opt_tbl.o
printf "  OPTIONS build/mainboard/gigabyte/m57sli/option_table.c\n"
  OPTIONS build/mainboard/gigabyte/m57sli/option_table.c
mkdir -p /home/stuge/co/v3/build/mainboard/gigabyte/m57sli
/home/stuge/co/v3/build/util/options/build_opt_tbl -b \
                --config /home/stuge/co/v3/mainboard/gigabyte/m57sli/cmos.layout \
                --option /home/stuge/co/v3/build/mainboard/gigabyte/m57sli/option_table.c 
# We need to be careful. If stage0.o gets bigger than
# 0x4000 - 0x100, we will end up with a 4 gig file.
# I wonder if that behavior is on purpose.
# Note: we invoke gcc (instead of ld directly) here, as we hit
# strange problems in the past. It seems that only gcc knows how
# to properly invoke ld.
printf "  CC      build/stage0.init\n"
  CC      build/stage0.init
gcc -nostdlib -static -T /home/stuge/co/v3/arch/x86/ldscript.ld \
                /home/stuge/co/v3/build/lib/uart8250.o /home/stuge/co/v3/build/lib/mem.o /home/stuge/co/v3/build/lib/lar.o /home/stuge/co/v3/build/lib/delay.o /home/stuge/co/v3/build/lib/vtxprintf.o /home/stuge/co/v3/build/lib/vsprintf.o /home/stuge/co/v3/build/lib/console.o /home/stuge/co/v3/build/lib/string.o /home/stuge/co/v3/build/lib/lzma.o /home/stuge/co/v3/build/arch/x86/stage1.o /home/stuge/co/v3/build/arch/x86/serial.o /home/stuge/co/v3/build/arch/x86/speaker.o /home/stuge/co/v3/build/arch/x86/udelay_io.o /home/stuge/co/v3/build/arch/x86/mc146818rtc.o /home/stuge/co/v3/build/arch/x86/post_code.o /home/stuge/co/v3/build/arch/x86/amd/k8/stage1.o /home/stuge/co/v3/build/arch/x86/amd/stage0.o /home/stuge/co/v3/build/mainboard/gigabyte/m57sli/stage1.o /home/stuge/co/v3/build/mainboard/gigabyte/m57sli/option_table.c /home/stuge/co/v3/build/superio/ite/it8716f/stage1.o /home/stuge/co/v3/build/device/pnp_raw.o -o /home/stuge/co/v3/build/stage0.o
/usr/lib/gcc/i686-pc-linux-gnu/4.2.2/../../../../i686-pc-linux-gnu/bin/as: unrecognized option '-T'
make: *** [/home/stuge/co/v3/build/stage0.init] Error 1


//Peter



From uwe at hermann-uwe.de  Tue Aug  5 14:57:15 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 5 Aug 2008 14:57:15 +0200
Subject: [coreboot] [PATCH] coreinfo: Make hard-coded strings configurable
	for Bayou	use
Message-ID: <20080805125714.GA23027@greenwood>

See patch.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From jordan.crouse at amd.com  Tue Aug  5 16:05:30 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 5 Aug 2008 08:05:30 -0600
Subject: [coreboot] coreinfo: Make hard-coded strings configurable for
	Bayou use
In-Reply-To: <20080805125714.GA23027@greenwood>
References: <20080805125714.GA23027@greenwood>
Message-ID: <20080805140530.GF6674@cosmic.amd.com>

On 05/08/08 14:57 +0200, Uwe Hermann wrote:
> See patch.
> 
> 
> Uwe.
> -- 
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

> Move out some hardcoded strings in coreinfo to become Kconfig variables.
> This is useful for use with (e.g.) Bayou in order let the user customize the
> payload name, description, version, etc.
> 
> For instance, instead of using stock coreinfo and calling the payload
> "coreinfo" and the Bayou menu item "Show system information" a user might
> only be interested in an NVRAM dump payload. Thus, he/she can enable
> only the NVRAM coreinfo module via Kconfig, and tell Kconfig to call
> the payload "NVRAMdumper" and the Bayou menu item "Show NVRAM contents".
> 
> This is build-tested, and tested against Bayou in QEMU.
> 
> Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>

Only one question - what about internationalization?  It doesn't seem
fair that English gets the default and everybody else has to change 
the kconfig.

Otherwise...

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From svn at coreboot.org  Tue Aug  5 16:36:21 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 Aug 2008 16:36:21 +0200
Subject: [coreboot] r3472 - trunk/payloads/coreinfo
Message-ID: <mailman.1786.1355071350.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-08-05 16:36:20 +0200 (Tue, 05 Aug 2008)
New Revision: 3472

Modified:
   trunk/payloads/coreinfo/Kconfig
   trunk/payloads/coreinfo/coreinfo.c
Log:
Move out some hardcoded strings in coreinfo to become Kconfig variables.
This is useful for use with (e.g.) Bayou in order let the user customize the
payload name, description, version, etc.

For instance, instead of using stock coreinfo and calling the payload
"coreinfo" and the Bayou menu item "Show system information" a user might
only be interested in an NVRAM dump payload. Thus, he/she can enable
only the NVRAM coreinfo module via Kconfig, and tell Kconfig to call
the payload "NVRAMdumper" and the Bayou menu item "Show NVRAM contents".

This is build-tested, and tested against Bayou in QEMU.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>



Modified: trunk/payloads/coreinfo/Kconfig
===================================================================
--- trunk/payloads/coreinfo/Kconfig	2008-08-04 21:02:07 UTC (rev 3471)
+++ trunk/payloads/coreinfo/Kconfig	2008-08-05 14:36:20 UTC (rev 3472)
@@ -36,6 +36,30 @@
 
 	  This option will increase the ELF file size by ca. 256 bytes.
 
+config PAYLOAD_INFO_NAME
+	string "Payload name"
+	default "coreinfo"
+	help
+	  The name of this payload for use in (e.g.) Bayou.
+
+config PAYLOAD_INFO_LISTNAME
+	string "Payload menu entry name"
+	default "System Information"
+	help
+	  The name of this payload's menu entry for use in (e.g.) Bayou.
+
+config PAYLOAD_INFO_DESC
+	string "Payload description"
+	default "Display information about the system"
+	help
+	  The description of this payload for use in (e.g.) Bayou.
+
+config PAYLOAD_INFO_VERSION
+	string "Payload version"
+	default "0.1"
+	help
+	  The version number of this payload.
+
 endmenu
 
 menu "Modules"

Modified: trunk/payloads/coreinfo/coreinfo.c
===================================================================
--- trunk/payloads/coreinfo/coreinfo.c	2008-08-04 21:02:07 UTC (rev 3471)
+++ trunk/payloads/coreinfo/coreinfo.c	2008-08-05 14:36:20 UTC (rev 3472)
@@ -221,7 +221,7 @@
 {
 	int key;
 
-	center(0, "coreinfo v0.1");
+	center(0, CONFIG_PAYLOAD_INFO_NAME " " CONFIG_PAYLOAD_INFO_VERSION);
 	refresh();
 
 	print_menu();
@@ -301,6 +301,6 @@
 	return 0;
 }
 
-PAYLOAD_INFO(name, "coreinfo");
-PAYLOAD_INFO(listname, "System Information");
-PAYLOAD_INFO(desc, "Display information about the system");
+PAYLOAD_INFO(name, CONFIG_PAYLOAD_INFO_NAME);
+PAYLOAD_INFO(listname, CONFIG_PAYLOAD_INFO_LISTNAME);
+PAYLOAD_INFO(desc, CONFIG_PAYLOAD_INFO_DESC);




From svn at coreboot.org  Tue Aug  5 16:48:17 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 05 Aug 2008 14:48:17 -0000
Subject: [coreboot] #111: Add i18n support for translating strings e.g. for
 bayou / coreinfo
Message-ID: <039.f7a84366a47130a205095d07380b80aa@coreboot.org>

#111: Add i18n support for translating strings e.g. for bayou / coreinfo
---------------------------------+------------------------------------------
   Reporter:  uwe                |          Owner:  somebody
       Type:  enhancement        |         Status:  new     
   Priority:  major              |      Milestone:          
  Component:  bayou              |        Version:          
   Keywords:                     |   Dependencies:          
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 At some point we might want to translate bayou menu item strings, coreinfo
 strings, etc. etc. into other languages, probably with totally different
 character sets (think chinese).

 For this we'll likely need lots of infrastructure, including a small UTF
 lib, fonts, VESA support, and more.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/111>
coreboot <http://www.coreboot.org/>


From uwe at hermann-uwe.de  Tue Aug  5 16:50:17 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 5 Aug 2008 16:50:17 +0200
Subject: [coreboot] coreinfo: Make hard-coded strings configurable for
	Bayou use
In-Reply-To: <20080805140530.GF6674@cosmic.amd.com>
References: <20080805125714.GA23027@greenwood>
	<20080805140530.GF6674@cosmic.amd.com>
Message-ID: <20080805145017.GA21474@greenwood>

On Tue, Aug 05, 2008 at 08:05:30AM -0600, Jordan Crouse wrote:
> Only one question - what about internationalization?  It doesn't seem
> fair that English gets the default and everybody else has to change 
> the kconfig.
> 
> Otherwise...
> 
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Thanks, r3472.

For the i18n, as per IRC discussion, we'll probably have to do quite
some work, including VESA, fonts, UTF libs, whatnot...

I added a ticket here:
http://tracker.coreboot.org/trac/coreboot/ticket/111


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Tue Aug  5 17:48:40 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Aug 2008 08:48:40 -0700
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <2ea3fae10808050141qaa320bdr8ccb307326026f28@mail.gmail.com>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<2ea3fae10808050141qaa320bdr8ccb307326026f28@mail.gmail.com>
Message-ID: <13426df10808050848k5c1adf6emff7c0b110b1cda0c@mail.gmail.com>

On Tue, Aug 5, 2008 at 1:41 AM, yhlu <yinghailu at gmail.com> wrote:

> No. REV A-E got DDR1. REV F got DDR2
>

OK but can I use the same data structures and just live with the fact
that on A-E some parts are unused and on F other parts are unused?

ron



From Marc.Jones at amd.com  Tue Aug  5 17:55:57 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Tue, 5 Aug 2008 09:55:57 -0600
Subject: [coreboot] Fam10h support for Tyan S2912-E
In-Reply-To: <kjmej53vs3w.fsf@pelargir.dolphinics.no>
References: <kjmvdyhug78.fsf@pelargir.dolphinics.no>	<489735B0.2000701@amd.com>
	<kjmej53vs3w.fsf@pelargir.dolphinics.no>
Message-ID: <4898780D.4020400@amd.com>

Arne Georg Gleditsch wrote:
> Marc Jones <Marc.Jones at amd.com> writes:

I have a RD1-PMC4 BIOS savior from a previos project that I've installed
>  My initial
> impulse was to adapt the s2912 codebase according to the diff between
> the cheetah and cheetah_fam10 targets and see how far that got me.

I think that is a good way to go.
Marc


-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors




From yinghailu at gmail.com  Tue Aug  5 21:23:30 2008
From: yinghailu at gmail.com (yhlu)
Date: Tue, 5 Aug 2008 12:23:30 -0700
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <13426df10808050848k5c1adf6emff7c0b110b1cda0c@mail.gmail.com>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<2ea3fae10808050141qaa320bdr8ccb307326026f28@mail.gmail.com>
	<13426df10808050848k5c1adf6emff7c0b110b1cda0c@mail.gmail.com>
Message-ID: <2ea3fae10808051223v69e74695q26b5456e9d60d8b9@mail.gmail.com>

On Tue, Aug 5, 2008 at 8:48 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, Aug 5, 2008 at 1:41 AM, yhlu <yinghailu at gmail.com> wrote:
>
>> No. REV A-E got DDR1. REV F got DDR2
>>
>
> OK but can I use the same data structures and just live with the fact
> that on A-E some parts are unused and on F other parts are unused?
>
Yes

YH



From rminnich at gmail.com  Tue Aug  5 21:54:28 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Aug 2008 12:54:28 -0700
Subject: [coreboot] K8 state of v3 tree
In-Reply-To: <2ea3fae10808051223v69e74695q26b5456e9d60d8b9@mail.gmail.com>
References: <13426df10808041938t6598a72bnfa6917262d6d8fba@mail.gmail.com>
	<2ea3fae10808050141qaa320bdr8ccb307326026f28@mail.gmail.com>
	<13426df10808050848k5c1adf6emff7c0b110b1cda0c@mail.gmail.com>
	<2ea3fae10808051223v69e74695q26b5456e9d60d8b9@mail.gmail.com>
Message-ID: <13426df10808051254i5baa3ea6pc94cdfc4d34fa15c@mail.gmail.com>

On Tue, Aug 5, 2008 at 12:23 PM, yhlu <yinghailu at gmail.com> wrote:
> On Tue, Aug 5, 2008 at 8:48 AM, ron minnich <rminnich at gmail.com> wrote:
>> On Tue, Aug 5, 2008 at 1:41 AM, yhlu <yinghailu at gmail.com> wrote:
>>
>>> No. REV A-E got DDR1. REV F got DDR2
>>>
>>
>> OK but can I use the same data structures and just live with the fact
>> that on A-E some parts are unused and on F other parts are unused?
>>
> Yes
>

Thanks! This is good news ...

ron



From stepan at coresystems.de  Wed Aug  6 01:09:54 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 06 Aug 2008 01:09:54 +0200
Subject: [coreboot] [PATCH] libpayload: use correct compiler
Message-ID: <4898DDC2.40102@coresystems.de>

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Index: util/kconfig/lxdialog/Makefile
===================================================================
--- util/kconfig/lxdialog/Makefile    (revision 372)
+++ util/kconfig/lxdialog/Makefile    (working copy)
@@ -25,7 +25,7 @@
          util.o lxdialog.o msgbox.o
 
 lxdialog: dochecklxdialog $(lxdialog-objs)
-    $(CC) $(HOST_LOADLIBES) -o lxdialog $(lxdialog-objs)
+    $(Q)$(HOSTCC) $(HOST_LOADLIBES) -o lxdialog $(lxdialog-objs)
 
 %.o: %.c
     $(Q)$(HOSTCC) $(HOST_EXTRACFLAGS) $^ -c -o $@

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From peter at stuge.se  Wed Aug  6 01:15:36 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 Aug 2008 01:15:36 +0200
Subject: [coreboot] [PATCH] libpayload: use correct compiler
In-Reply-To: <4898DDC2.40102@coresystems.de>
References: <4898DDC2.40102@coresystems.de>
Message-ID: <20080805231536.519.qmail@stuge.se>

On Wed, Aug 06, 2008 at 01:09:54AM +0200, Stefan Reinauer wrote:
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>


> Index: util/kconfig/lxdialog/Makefile
> ===================================================================
> --- util/kconfig/lxdialog/Makefile    (revision 372)
> +++ util/kconfig/lxdialog/Makefile    (working copy)
> @@ -25,7 +25,7 @@
>          util.o lxdialog.o msgbox.o
> 
> lxdialog: dochecklxdialog $(lxdialog-objs)
> -    $(CC) $(HOST_LOADLIBES) -o lxdialog $(lxdialog-objs)
> +    $(Q)$(HOSTCC) $(HOST_LOADLIBES) -o lxdialog $(lxdialog-objs)
> 
> %.o: %.c
>     $(Q)$(HOSTCC) $(HOST_EXTRACFLAGS) $^ -c -o $@
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From rminnich at gmail.com  Wed Aug  6 02:23:51 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 Aug 2008 17:23:51 -0700
Subject: [coreboot] patch: add in smbus support for mcp55
Message-ID: <13426df10808051723x389e95e2xbb4f224ab991057e@mail.gmail.com>

This patch adds in a bit more support, this is the mcp55 smbus.

This also illustrates the need to figure out the pci stuff in a better
way. It works for now, but we need to do better.

But we'll figure out it once we have a full port under our belts, and
we can come up with something that works right. We're still
getting over the v2 practice of including .c files :-) [Which, lest we
forget, was the best way to do things given that we did NOT have
cache as ram -- I intend no criticism at all!]

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
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From kevin at koconnor.net  Wed Aug  6 02:24:42 2008
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 5 Aug 2008 20:24:42 -0400
Subject: [coreboot] Minimal seabios for coreboot
In-Reply-To: <92cbc4c70808042144n7ea7b241g82fdcbe4c3777abd@mail.gmail.com>
References: <20080722030921.GA26108@morn.localdomain>
	<92cbc4c70808042144n7ea7b241g82fdcbe4c3777abd@mail.gmail.com>
Message-ID: <20080806002442.GA14665@morn.localdomain>

On Tue, Aug 05, 2008 at 12:44:55PM +0800, Zhang Rui wrote:
> 2008/7/22, Kevin O'Connor <kevin at koconnor.net>:
> > I can see where the above would be useful if the payload is always
> > coming out of flash.  However, if the user ever needs to boot using
> > seabios (or via a scsi/pxe option rom) then I think seabios needs to
> > be the payload and needs to drive the bootup.
> >
> 
> so if I want to write the int13 for scsi booting, should I write
> interrupt function in coreboot and inject it to int13, or just write
> codes in seabios?

I'm not sure what you mean.  The difficulty is going to be in passing
the information from the coreboot option rom scan to seabios so that
seabios can properly boot the machine (and fail over to an alternative
boot source if necessary).  I suppose one could add the legacy bios
bootup rules to coreboot, but I don't like that idea much.

-Kevin



From kevin at koconnor.net  Wed Aug  6 02:34:21 2008
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 5 Aug 2008 20:34:21 -0400
Subject: [coreboot] How can I call the interrupt of SeaBIOS in coreboot?
In-Reply-To: <92cbc4c70808042150w45f30606p6a1f786bb81a0d31@mail.gmail.com>
References: <92cbc4c70807150821l575ab6dg56ac82825cbe7fed@mail.gmail.com>
	<20080715173710.GB14605@morn.localdomain>
	<92cbc4c70807161858yb7a83e4i66eee86675f04660@mail.gmail.com>
	<20080717020831.GE27822@morn.localdomain>
	<92cbc4c70808042150w45f30606p6a1f786bb81a0d31@mail.gmail.com>
Message-ID: <20080806003421.GB14665@morn.localdomain>

On Tue, Aug 05, 2008 at 12:50:54PM +0800, Zhang Rui wrote:
> Hello,
> 	I am blocked with calling interrupt in coreboot.
> 	I tryed these ways:
> 	1. use "asm("int $0x19 \n");".  Qemu has no output when executeed
> here and nothing happens. The reason is that it should jump to real
> mode before calling int 19.

Right.  You'd need to call "int 0x19" after transitioning to real
mode.

> 	2. write a function boot_coreboot() in seabios. like:
> 
> 	void VISIBLE32 boot_coreboot()
> 	{
> 		struct bregs br;
> 		dprintf(1, "boot_coreboot: begin\n");
> 		memset(&br, 0, sizeof(br));
> 		dprintf(1, "boot_coreboot: call int 19\n");
> 		call16_int(0x19, &br);
> 		dprintf(1, "boot_coreboot: end\n");
> 	}
> 	
> 	then call boot_coreboot() in seabios. It booted successfully.
> 
> 	I have read the source code of call16_int, it jump to real mode and
> jump to the int 19 handler function directly, but do not use "int
> $0x19" asm code. why?

No.  The call_int16(0x19, ...) function will call irq_trampoline_0x19
in real mode (see src/util.h).  The irq_trampoline_0x19 code is
defined in src/romlayout.S (see macro "IRQ_TRAMPOLINE 19") which runs
"int 0x19".

> 	3. write asm code to jump to real mode and call int 19.
> 	but in coreboot there is compiling errors when I write asm codes with
> lables in it in vm86.c.
> 	for a simple example:
> 	__asm__ __volatile__ (
> 			/* paranoia -- does ecx get saved? not sure. This is
> 			 * the easiest safe thing to do. */
> 			"	pushal			\n"
> 			"	ljmp 	$0x28, $cbint16bit\n"
> 			"cbint16bit:		\n"
> 			"	.code16			\n"
> 			"	popal\n"
> 			);
> 
> 	will cause errors:
> 	{standard input}: Assembler messages:
> 	{standard input}:746: Error: symbol `cbint16bit' is already defined
> 	
> 	in seabios there is compiling errors because of ".code16":
> 	out/../src/post.c:349: relocation truncated to fit: R_386_16 against `.text'
> 
> 	what is wrong here?

I'm guessing you didn't issue a ".code32" after the ".code16".  Not
putting the assembler back into 32bit mode will totally confuse it.

Also, you may be running into trouble with the segmented memory model
- the 32bit code runs at 0xfxxxx and uses 32bit offsets, while the
16bit code runs at 0xf000:xxxx and uses 16bit offsets.

I'm not sure why you'd want to do this in seabios though - option 2
above would be the preferred way to call int19.

-Kevin



From stepan at coresystems.de  Wed Aug  6 11:28:17 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 06 Aug 2008 11:28:17 +0200
Subject: [coreboot] [PATCH] libpayload: complete + simplify pci functions
Message-ID: <48996EB1.1030504@coresystems.de>

see patch

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From peter at stuge.se  Wed Aug  6 11:32:02 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 Aug 2008 11:32:02 +0200
Subject: [coreboot] [PATCH] libpayload: complete + simplify pci functions
In-Reply-To: <48996EB1.1030504@coresystems.de>
References: <48996EB1.1030504@coresystems.de>
Message-ID: <20080806093202.726.qmail@stuge.se>

On Wed, Aug 06, 2008 at 11:28:17AM +0200, Stefan Reinauer wrote:
> +int pci_find_device(u16 vid, u16 did, pcidev_t * dev)
>  {
>  	return find_on_bus(0, vid, did, dev);
>  }

Shouldn't pci_find_device() scan all buses?

Looks good otherwise.


//Peter



From stepan at coresystems.de  Wed Aug  6 11:37:18 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 06 Aug 2008 11:37:18 +0200
Subject: [coreboot] [PATCH] libpayload: complete + simplify pci functions
In-Reply-To: <20080806093202.726.qmail@stuge.se>
References: <48996EB1.1030504@coresystems.de>
	<20080806093202.726.qmail@stuge.se>
Message-ID: <489970CE.3090206@coresystems.de>

Peter Stuge wrote:
> On Wed, Aug 06, 2008 at 11:28:17AM +0200, Stefan Reinauer wrote:
>   
>> +int pci_find_device(u16 vid, u16 did, pcidev_t * dev)
>>  {
>>  	return find_on_bus(0, vid, did, dev);
>>  }
>>     
>
> Shouldn't pci_find_device() scan all buses?
>
> Looks good otherwise.
>   
I didn't change that behavior.

All I need for now is a complete set of 8/16/32bit accesses to the
config space without passing pointers around.

I might look into more issues as they appear, but I decided to leave
those two functions alone for now, so I don't touch side cases I might
not know.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug  6 13:34:45 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 Aug 2008 13:34:45 +0200
Subject: [coreboot] patch: add in smbus support for mcp55
In-Reply-To: <13426df10808051723x389e95e2xbb4f224ab991057e@mail.gmail.com>
References: <13426df10808051723x389e95e2xbb4f224ab991057e@mail.gmail.com>
Message-ID: <48998C55.5000302@gmx.net>

On 06.08.2008 02:23, ron minnich wrote:
> This patch adds in a bit more support, this is the mcp55 smbus.
>
> This also illustrates the need to figure out the pci stuff in a better
> way. It works for now, but we need to do better.
>
> But we'll figure out it once we have a full port under our belts, and
> we can come up with something that works right. We're still
> getting over the v2 practice of including .c files :-) [Which, lest we
> forget, was the best way to do things given that we did NOT have
> cache as ram -- I intend no criticism at all!]
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   

A few comments below. In general, using printk more often would be nice
since we're not constrained by romcc anymore. IMO we also should settle
for a delay mechanism which doesn't clobber POST codes.

> Index: southbridge/nvidia/mcp55/mcp55_smbus.h
> ===================================================================
> --- southbridge/nvidia/mcp55/mcp55_smbus.h	(revision 0)
> +++ southbridge/nvidia/mcp55/mcp55_smbus.h	(revision 0)
> @@ -0,0 +1,194 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2004 Tyan Computer
> + * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
> + * Copyright (C) 2006,2007 AMD
> + * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <device/smbus_def.h>
> +
> +#define SMBHSTSTAT	0x1
> +#define SMBHSTPRTCL	0x0
> +#define SMBHSTCMD	0x3
> +#define SMBXMITADD	0x2
> +#define SMBHSTDAT0	0x4
> +#define SMBHSTDAT1	0x5
> +
> +/* Between 1-10 seconds, We should never timeout normally
> + * Longer than this is just painful when a timeout condition occurs.
> + */
> +#define SMBUS_TIMEOUT	(100*1000*10)
> +
> +static inline void smbus_delay(void)
> +{
> +	outb(0x80, 0x80);
> +}

Can we use inb(0x80) or outb(0x80,0x84) instead? That way, we won't mess
us POST code logging.

> +
> +static int smbus_wait_until_ready(unsigned smbus_io_base)

Can we use explicit length types like u16 instead of unsigned? That
applies to almost all functions.

> +{
> +	unsigned long loops;
> +	loops = SMBUS_TIMEOUT;
> +	do {
> +		unsigned char val;
> +		smbus_delay();
> +		val = inb(smbus_io_base + SMBHSTSTAT);
> +		val &= 0x1f;
> +		if (val == 0) {
> +			return 0;
> +		}
> +		outb(val,smbus_io_base + SMBHSTSTAT);
> +	} while(--loops);
> +	return -2;

The -2 is a magic value. A #define would be appreciated.

> +}
> +
> +static int smbus_wait_until_done(unsigned smbus_io_base)

u16

> +{
> +	unsigned long loops;
> +	loops = SMBUS_TIMEOUT;
> +	do {
> +		unsigned char val;
> +		smbus_delay();
> +
> +		val = inb(smbus_io_base + SMBHSTSTAT);
> +		if ( (val & 0xff) != 0) {
> +			return 0;
> +		}
> +	} while(--loops);
> +	return -3;

Magic value.

> +}

Missing empty line between functions.

> +static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)

u16/u32

> +{
> +	unsigned char global_status_register;
> +	unsigned char byte;
> +
> +	/* set the device I'm talking too */
> +	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
> +	smbus_delay();
> +
> +	/* byte data recv */
> +	outb(0x05, smbus_io_base + SMBHSTPRTCL);
> +	smbus_delay();
> +
> +	/* poll for transaction completion */
> +	if (smbus_wait_until_done(smbus_io_base) < 0) {
> +		return -3;

Magic value.


> +	}
> +
> +	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */

Do we want to lose a check here or do we want to check loosely?

> +
> +	/* read results of transaction */
> +	byte = inb(smbus_io_base + SMBHSTCMD);
> +
> +	if (global_status_register != 0x80) { // lose check, otherwise it should be 0
> +		return -1;

Magic value.

> +	}
> +	return byte;
> +}

Missing empty line between functions.

> +static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)

u16/u32

> +{
> +	unsigned global_status_register;
> +
> +	outb(val, smbus_io_base + SMBHSTDAT0);
> +	smbus_delay();
> +
> +	/* set the command... */
> +	outb(val, smbus_io_base + SMBHSTCMD);
> +	smbus_delay();
> +
> +	/* set the device I'm talking too */
> +	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
> +	smbus_delay();
> +
> +	/* set up for a byte data write */
> +	outb(0x04, smbus_io_base + SMBHSTPRTCL);
> +	smbus_delay();
> +
> +	/* poll for transaction completion */
> +	if (smbus_wait_until_done(smbus_io_base) < 0) {
> +		return -3;

Magic value.

> +	}
> +	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
> +
> +	if (global_status_register != 0x80) {
> +		return -1;

Magic value.

> +	}
> +	return 0;
> +}

Missing empty line between functions.

> +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)

u16/u32/u8

> +{
> +	unsigned char global_status_register;
> +	unsigned char byte;
> +
> +	/* set the device I'm talking too */
> +	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
> +	smbus_delay();
> +	/* set the command/address... */
> +	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
> +	smbus_delay();
> +	/* byte data read */
> +	outb(0x07, smbus_io_base + SMBHSTPRTCL);
> +	smbus_delay();
> +
> +	/* poll for transaction completion */
> +	if (smbus_wait_until_done(smbus_io_base) < 0) {
> +		return -3;
> +	}
> +
> +	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
> +
> +	/* read results of transaction */
> +	byte = inb(smbus_io_base + SMBHSTDAT0);
> +
> +	if (global_status_register != 0x80) { // lose check, otherwise it should be 0
> +		return -1;
> +	}
> +	return byte;
> +}
> +
> +

Two empty lines.

> +static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)

u16/u32/u8

> +{
> +	unsigned global_status_register;
> +
> +	outb(val, smbus_io_base + SMBHSTDAT0);
> +	smbus_delay();
> +
> +	/* set the device I'm talking too */
> +	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
> +	smbus_delay();
> +
> +	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
> +	smbus_delay();
> +
> +	/* set up for a byte data write */
> +	outb(0x06, smbus_io_base + SMBHSTPRTCL);
> +	smbus_delay();
> +
> +	/* poll for transaction completion */
> +	if (smbus_wait_until_done(smbus_io_base) < 0) {
> +		return -3;
> +	}
> +	global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
> +
> +	if (global_status_register != 0x80) {
> +		return -1;
> +	}
> +	return 0;
> +}
> +
> Index: southbridge/nvidia/mcp55/stage1_smbus.c
> ===================================================================
> --- southbridge/nvidia/mcp55/stage1_smbus.c	(revision 0)
> +++ southbridge/nvidia/mcp55/stage1_smbus.c	(revision 0)
> @@ -0,0 +1,93 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2004 Tyan Computer
> + * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
> + * Copyright (C) 2006,2007 AMD
> + * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <console.h>
> +#include <io.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include "mcp55.h"
> +#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
> +#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
> +#define pci_read_config16(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where)
> +#define pci_write_config16(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
> +#include "mcp55_smbus.h"
> +
> +#define SMBUS0_IO_BASE	0x1000
> +#define SMBUS1_IO_BASE	(0x1000+(1<<8))
> +/*SIZE 0x40 */
> +
> +static void enable_smbus(void)
> +{
> +	u32 dev;
> +	dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
> +#if 0
> +	if (dev == PCI_DEV_INVALID) {
> +		die("SMBUS controller not found\r\n");
> +	}
> +
> +	print_debug("SMBus controller enabled\r\n");

printk

> +#endif
> +	/* set smbus iobase */
> +	pci_write_config32(0, dev, 0x20, SMBUS0_IO_BASE | 1);
> +	pci_write_config32(0, dev, 0x24, SMBUS1_IO_BASE | 1);
> +	/* Set smbus iospace enable */
> +	pci_write_config16(0, dev, 0x4, 0x01);
> +	/* clear any lingering errors, so the transaction will run */
> +	outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
> +	outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
> +}
> +
> +static int smbus_recv_byte(unsigned device)

u32?

> +{
> +	return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
> +}

Missing empty line between functions.

> +static int smbus_send_byte(unsigned device, unsigned char val)

u32?

> +{
> +	return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
> +}

Missing empty line between functions.

> +static int smbus_read_byte(unsigned device, unsigned address)

u32?

> +{
> +	return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
> +}

Missing empty line between functions.

> +static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)

u32/u16?

> +{
> +	return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
> +}
> +
> +static int smbusx_recv_byte(unsigned smb_index, unsigned device)

u8/u32?

> +{
> +	return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device);
> +}

Missing empty line between functions.

> +static int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val)
> +{
> +	return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val);
> +}

Missing empty line between functions.

> +static int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address)
> +{
> +	return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address);
> +}

Missing empty line between functions.

> +static int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val)
> +{
> +	return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val);
> +}
> +
> Index: mainboard/gigabyte/m57sli/Makefile
> ===================================================================
> --- mainboard/gigabyte/m57sli/Makefile	(revision 719)
> +++ mainboard/gigabyte/m57sli/Makefile	(working copy)
> @@ -20,7 +20,8 @@
>  ##
>  
>  STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \
> -			$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
> +			$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c \
> +			$(obj)/southbridge/nvidia/mcp55/stage1_smbus.o
>  
>  INITRAM_SRC =      $(src)/mainboard/$(MAINBOARDDIR)/initram.c
>  

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug  6 15:18:43 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 Aug 2008 15:18:43 +0200
Subject: [coreboot] K8 and Fam10 CAR
Message-ID: <4899A4B3.4050501@gmx.net>

Hi Marc,

I'm currently working to unify K8 and Fam10 CAR to use the same code at
runtime (as opposed to buildtime #ifdefs). While this may not be a goal
for v2, I definitely want to try it for v3.

A few questions/comments about the CAR code:
- Only Fam10 APs are treated specially. APs of older generations seem to
be unhandled. Did older generations treat each core as BSP (code seems
to suggest that) or were there other special provisions?
- "Errata 193: Disable clean copybacks to L3 cache to allow cached ROM."
Erratum 193 seems to be unlisted in public data sheets. If it is the
famous L3 problem, we might want to enable the workaround only on
affected revisions.
- CAR goes from 0xC8000 to 0xCFFFF. Assuming GlobalVarSize=0 (untrue,
but easier to calculate), BSP stack will be from 0xCC000 to 0xCFFFF and
AP stacks will be below 0xCBFFF.
* With the current settings (32k CAR total, 1k per AP, 16K for the BSP)
the scheme will fall apart if the highest NodeID shifted by the number
of CoreID bits is 16 or higher. The BKDG indicates that the number of
CoreID bits is 2, so a NodeID of 4 or higher will break.
* There is no good place to store the printk() buffer in CAR. On Geode
and i586, the printk buffer runs from the lowest address of the CAR area
to the middle. Keeping that design will result in the AP stacks
colliding with the printk buffer. Limiting the size of the printk buffer
dynamically would work unless there are more than 15 cores in the
system, where even a printk buffer of zero size would clobber one AP
stack. The other alternative is to keep the printk buffer size fixed and
let the AP stacks eat into BSP stack space.
- Is there any reason on any K8 or later processor supported by the
current CAR code not to use 64k CAR?
- Is 1k enough stack for the APs, given some stack-heavy functions in v3?
- Can the K8 processors work reliably with 0x1e1e1e1e settings in the
fixed MTRR or can the Fam10 processors work with 0x06060606?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Wed Aug  6 16:09:14 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 6 Aug 2008 07:09:14 -0700
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <4899A4B3.4050501@gmx.net>
References: <4899A4B3.4050501@gmx.net>
Message-ID: <13426df10808060709u11b44d29m873fe42244347598@mail.gmail.com>

On Wed, Aug 6, 2008 at 6:18 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi Marc,
>
> I'm currently working to unify K8 and Fam10 CAR to use the same code at
> runtime (as opposed to buildtime #ifdefs). While this may not be a goal
> for v2, I definitely want to try it for v3.


just be careful. It is a lot of work for a gain I am not sure I
understand. Once you have CAR working for a given CPU, it seems to me
we cast it in stone and leave it forever. I'd like to better
understand the value of doing this.

thanks

ron



From rminnich at gmail.com  Wed Aug  6 16:13:20 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 6 Aug 2008 07:13:20 -0700
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <4899A4B3.4050501@gmx.net>
References: <4899A4B3.4050501@gmx.net>
Message-ID: <13426df10808060713r58cc9658ide24051f118a95f5@mail.gmail.com>

oh yeah. Be aware that on v3 we return from car to the main code, so
the stack has to be preserved. We may want to move the CAR area to a
real memory area as we did on V3. But is this possible?

We also need to get disable_car() working.

ron



From jordan.crouse at amd.com  Wed Aug  6 16:24:29 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 6 Aug 2008 08:24:29 -0600
Subject: [coreboot] libpayload: complete + simplify pci functions
In-Reply-To: <48996EB1.1030504@coresystems.de>
References: <48996EB1.1030504@coresystems.de>
Message-ID: <20080806142429.GN6674@cosmic.amd.com>

On 06/08/08 11:28 +0200, Stefan Reinauer wrote:
> see patch
> 
> -- 
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
> 

> add missing pci functions and change to a simpler, more common interface
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Don't forget to fixup coreinfo too.

Jordan




From jordan.crouse at amd.com  Wed Aug  6 16:26:18 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 6 Aug 2008 08:26:18 -0600
Subject: [coreboot] libpayload: complete + simplify pci functions
In-Reply-To: <489970CE.3090206@coresystems.de>
References: <48996EB1.1030504@coresystems.de>
	<20080806093202.726.qmail@stuge.se>
	<489970CE.3090206@coresystems.de>
Message-ID: <20080806142618.GO6674@cosmic.amd.com>

On 06/08/08 11:37 +0200, Stefan Reinauer wrote:
> Peter Stuge wrote:
> > On Wed, Aug 06, 2008 at 11:28:17AM +0200, Stefan Reinauer wrote:
> >   
> >> +int pci_find_device(u16 vid, u16 did, pcidev_t * dev)
> >>  {
> >>  	return find_on_bus(0, vid, did, dev);
> >>  }
> >>     
> >
> > Shouldn't pci_find_device() scan all buses?
> >
> > Looks good otherwise.
> >   
> I didn't change that behavior.
> 
> All I need for now is a complete set of 8/16/32bit accesses to the
> config space without passing pointers around.
> 
> I might look into more issues as they appear, but I decided to leave
> those two functions alone for now, so I don't touch side cases I might
> not know.

The original code was mine - patches welcome to extend the
behavior if we think it is needed.  So far, Uwe and I haven't
had any problems.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From peter at stuge.se  Wed Aug  6 16:30:53 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 Aug 2008 16:30:53 +0200
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <13426df10808060709u11b44d29m873fe42244347598@mail.gmail.com>
References: <4899A4B3.4050501@gmx.net>
	<13426df10808060709u11b44d29m873fe42244347598@mail.gmail.com>
Message-ID: <20080806143053.18137.qmail@stuge.se>

On Wed, Aug 06, 2008 at 07:09:14AM -0700, ron minnich wrote:
> > unify K8 and Fam10 CAR to use the same code at runtime
> 
> I'd like to better understand the value of doing this.

At least the m57sli and serengeti_cheetah boards can run with either
k8 or fam10 processors. It'd be nice to have a single coreboot to
rule them all.


//Peter



From rminnich at gmail.com  Wed Aug  6 16:43:18 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 6 Aug 2008 07:43:18 -0700
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <20080806143053.18137.qmail@stuge.se>
References: <4899A4B3.4050501@gmx.net>
	<13426df10808060709u11b44d29m873fe42244347598@mail.gmail.com>
	<20080806143053.18137.qmail@stuge.se>
Message-ID: <13426df10808060743x7673daa8p7da7c64fbae36b82@mail.gmail.com>

On Wed, Aug 6, 2008 at 7:30 AM, Peter Stuge <peter at stuge.se> wrote:

> At least the m57sli and serengeti_cheetah boards can run with either
> k8 or fam10 processors. It'd be nice to have a single coreboot to
> rule them all.
>

that's an excellent reason, so I'm now on board.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug  6 17:03:12 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 Aug 2008 17:03:12 +0200
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <13426df10808060743x7673daa8p7da7c64fbae36b82@mail.gmail.com>
References: <4899A4B3.4050501@gmx.net>	<13426df10808060709u11b44d29m873fe42244347598@mail.gmail.com>	<20080806143053.18137.qmail@stuge.se>
	<13426df10808060743x7673daa8p7da7c64fbae36b82@mail.gmail.com>
Message-ID: <4899BD30.2020807@gmx.net>

On 06.08.2008 16:43, ron minnich wrote:
> On Wed, Aug 6, 2008 at 7:30 AM, Peter Stuge <peter at stuge.se> wrote:
>   
>> At least the m57sli and serengeti_cheetah boards can run with either
>> k8 or fam10 processors. It'd be nice to have a single coreboot to
>> rule them all.
>>     
>
> that's an excellent reason, so I'm now on board.
>   

Peter eloquently expressed my motivation. I have nothing more to add.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Wed Aug  6 17:12:02 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 Aug 2008 17:12:02 +0200
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <13426df10808060713r58cc9658ide24051f118a95f5@mail.gmail.com>
References: <4899A4B3.4050501@gmx.net>
	<13426df10808060713r58cc9658ide24051f118a95f5@mail.gmail.com>
Message-ID: <4899BF42.6050504@gmx.net>

On 06.08.2008 16:13, ron minnich wrote:
> oh yeah. Be aware that on v3 we return from car to the main code, so
> the stack has to be preserved. We may want to move the CAR area to a
> real memory area as we did on V3. But is this possible?
>   

In theory, it should work. In practice, at least some SimNow version
choked on the patches I had which moved the CAR area. I shall dig them
up again and have someone check them on real hardware. Of course it is
possible that my patches were faulty. To be honest, I have the feeling I
forgot to change some other code which references the old location.

> We also need to get disable_car() working.
>   

Yes, definitely.

Hmmm... found the patch. Attached.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

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From stepan at coresystems.de  Wed Aug  6 17:20:15 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 06 Aug 2008 17:20:15 +0200
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <4899BF42.6050504@gmx.net>
References: <4899A4B3.4050501@gmx.net>	<13426df10808060713r58cc9658ide24051f118a95f5@mail.gmail.com>
	<4899BF42.6050504@gmx.net>
Message-ID: <4899C12F.2040309@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 06.08.2008 16:13, ron minnich wrote:
>   
>> oh yeah. Be aware that on v3 we return from car to the main code, so
>> the stack has to be preserved. We may want to move the CAR area to a
>> real memory area as we did on V3. But is this possible?
>>   
>>     
>
> In theory, it should work. In practice, at least some SimNow version
> choked on the patches I had which moved the CAR area. I shall dig them
> up again and have someone check them on real hardware. Of course it is
> possible that my patches were faulty. To be honest, I have the feeling I
> forgot to change some other code which references the old location.
>   
Yes, DCACHE_RAM_BASE is referenced when the sys_info structure is copied
from cache to ram, and a couple of other places.
So you need to also fix up the mainboard Option.lb



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Wed Aug  6 17:32:48 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 Aug 2008 17:32:48 +0200
Subject: [coreboot] r214 - buildrom-devel/packages/geodevsa
Message-ID: <mailman.1787.1355071351.16123.coreboot@coreboot.org>

Author: ward
Date: 2008-08-06 17:32:47 +0200 (Wed, 06 Aug 2008)
New Revision: 214

Modified:
   buildrom-devel/packages/geodevsa/amdvsa.inc
Log:

Make sure that we create $(SOURCE_DIR) prior to downloading AMD's precompiled
VSA, in case it does not exist yet.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: buildrom-devel/packages/geodevsa/amdvsa.inc
===================================================================
--- buildrom-devel/packages/geodevsa/amdvsa.inc	2008-08-02 22:14:30 UTC (rev 213)
+++ buildrom-devel/packages/geodevsa/amdvsa.inc	2008-08-06 15:32:47 UTC (rev 214)
@@ -11,6 +11,7 @@
 # Jordan
 
 $(SOURCE_DIR)/$(AMDVSA_BIN):
+	@ mkdir -p $(SOURCE_DIR)
 	@ echo "Fetching the AMD VSA binary..."
 	wget $(WGET_Q) -P $(SOURCE_DIR) $(AMDVSA_URL)/$(AMDVSA_BIN).gz -O $@.gz
 	@ if file $@.gz | grep -q "gzip"; then \




From stepan at coresystems.de  Wed Aug  6 17:47:37 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 06 Aug 2008 17:47:37 +0200
Subject: [coreboot] [PATCH] libpayload: add cmos option handling
Message-ID: <4899C799.901@coresystems.de>

See patch

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From jordan.crouse at amd.com  Wed Aug  6 17:55:10 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 6 Aug 2008 09:55:10 -0600
Subject: [coreboot] libpayload: add cmos option handling
In-Reply-To: <4899C799.901@coresystems.de>
References: <4899C799.901@coresystems.de>
Message-ID: <20080806155510.GB27372@cosmic.amd.com>

On 06/08/08 17:47 +0200, Stefan Reinauer wrote:
> See patch
> 
> -- 
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
> 

> add get_option to libpayload, so coreboot cmos options can be queried.
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Sweet!

> Index: include/sysinfo.h
> ===================================================================
> --- include/sysinfo.h	(revision 372)
> +++ include/sysinfo.h	(working copy)
> @@ -43,6 +43,11 @@
>  		unsigned long long base;
>  		unsigned long long size;
>  	} memrange[SYSINFO_MAX_MEM_RANGES];
> +
> +	struct cb_cmos_option_table *option_table;
> +	u32 cmos_range_start;
> +	u32 cmos_range_end;
> +	u32 cmos_checksum_location;
>  };
>  
>  extern struct sysinfo_t lib_sysinfo;
> Index: include/coreboot_tables.h
> ===================================================================
> --- include/coreboot_tables.h	(revision 372)
> +++ include/coreboot_tables.h	(working copy)
> @@ -128,8 +128,58 @@
>  #define CB_TAG_CONSOLE_SROM       4
>  #define CB_TAG_CONSOLE_EHCI       5
>  
> -/* Still to come: CMOS information. */
> +#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
> +struct cb_cmos_option_table {
> +	u32 tag;
> +	u32 size;
> +	u32 header_length;
> +};
>  
> +#define CB_TAG_OPTION         0x00c9
> +#define CMOS_MAX_NAME_LENGTH    32
> +struct cb_cmos_entries {
> +	u32 tag;
> +	u32 size;
> +	u32 bit;
> +	u32 length;
> +	u32 config;
> +	u32 config_id;
> +	u8 name[CMOS_MAX_NAME_LENGTH];
> +};
> +
> +
> +#define CB_TAG_OPTION_ENUM    0x00ca
> +#define CMOS_MAX_TEXT_LENGTH 32
> +struct cb_cmos_enums {
> +	u32 tag;
> +	u32 size;
> +	u32 config_id;
> +	u32 value;
> +	u8 text[CMOS_MAX_TEXT_LENGTH];
> +};
> +
> +#define CB_TAG_OPTION_DEFAULTS 0x00cb
> +#define CMOS_IMAGE_BUFFER_SIZE 128
> +struct cb_cmos_defaults {
> +	u32 tag;
> +	u32 size;
> +	u32 name_length;
> +	u8 name[CMOS_MAX_NAME_LENGTH];
> +	u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
> +};
> +
> +#define CB_TAG_OPTION_CHECKSUM 0x00cc
> +#define CHECKSUM_NONE	0
> +#define CHECKSUM_PCBIOS	1
> +struct	cb_cmos_checksum {
> +	u32 tag;
> +	u32 size;
> +	u32 range_start;
> +	u32 range_end;
> +	u32 location;
> +	u32 type;
> +};
> +
>  /* Helpful macros */
>  
>  #define MEM_RANGE_COUNT(_rec) \
> Index: i386/coreboot.c
> ===================================================================
> --- i386/coreboot.c	(revision 372)
> +++ i386/coreboot.c	(working copy)
> @@ -74,6 +74,21 @@
>  	info->ser_ioport = ser->ioport;
>  }
>  
> +#ifdef CONFIG_NVRAM
> +static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info)
> +{
> +	info->option_table = (struct cb_cmos_option_table *)ptr;
> +}
> +
> +static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
> +{
> +	struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr;
> +	info->cmos_range_start = cmos_cksum->range_start;
> +	info->cmos_range_end = cmos_cksum->range_end;
> +	info->cmos_checksum_location = cmos_cksum->location;
> +}
> +#endif
> +
>  static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
>  {
>  	struct cb_header *header;
> @@ -115,6 +130,14 @@
>  		case CB_TAG_SERIAL:
>  			cb_parse_serial(ptr, info);
>  			break;
> +#ifdef CONFIG_NVRAM
> +		case CB_TAG_CMOS_OPTION_TABLE:
> +			cb_parse_optiontable(ptr, info);
> +			break;
> +		case CB_TAG_OPTION_CHECKSUM:
> +			cb_parse_checksum(ptr, info);
> +			break;
> +#endif
>  		}
>  
>  		ptr += rec->size;
> Index: drivers/Makefile.inc
> ===================================================================
> --- drivers/Makefile.inc	(revision 380)
> +++ drivers/Makefile.inc	(working copy)
> @@ -35,6 +35,7 @@
>  TARGETS-$(CONFIG_SERIAL_CONSOLE) += drivers/serial.o
>  TARGETS-$(CONFIG_PC_KEYBOARD) += drivers/keyboard.o
>  TARGETS-$(CONFIG_NVRAM) += drivers/nvram.o
> +TARGETS-$(CONFIG_NVRAM) += drivers/options.o
>  
>  # Video console drivers
>  TARGETS-$(CONFIG_VIDEO_CONSOLE) += drivers/video/video.o
> Index: drivers/options.c
> ===================================================================
> --- drivers/options.c	(revision 0)
> +++ drivers/options.c	(revision 0)
> @@ -0,0 +1,106 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include <libpayload.h>
> +#include <coreboot_tables.h>
> +
> +static int options_checksum_valid(void)
> +{
> +	int i;
> +	int range_start = lib_sysinfo.cmos_range_start;
> +	int range_end = lib_sysinfo.cmos_range_end;
> +	int checksum_location = lib_sysinfo.cmos_checksum_location;
> +	u16 checksum = 0, checksum_old;
> +
> +	for(i = range_start; i <= range_end; i++) {
> +		checksum += nvram_read(i);
> +	}
> +	checksum = (~checksum)&0xffff;
> +
> +	checksum_old = ((nvram_read(checksum_location)<<8) | nvram_read(checksum_location+1));
> +
> +	return (checksum_old == checksum);
> +}
> +
> +static int get_cmos_value(u32 bitnum, u32 len, void *valptr)
> +{
> +	u8 *value = (u8 *)valptr;
> +	int offs = 0;
> +	u32 addr, bit;
> +	u8 reg8;
> +
> +	value = valptr;
> +
> +	/* Convert to byte borders */
> +	addr=(bitnum / 8);
> +	bit=(bitnum % 8);
> +
> +	/* Handle single byte or less */
> +	if(len <= 8) {
> +		reg8 = nvram_read(addr);
> +		reg8 >>= bit;
> +		value[0] = reg8 & ((1 << len) -1);
> +		return 0;
> +	}
> +
> +	/* When handling more than a byte, copy whole bytes */
> +	while (len > 0) {
> +		len -= 8;
> +		value[offs++]=nvram_read(addr++);
> +	}
> +
> +	return 0;
> +}
> +
> +int get_option(void *dest, char *name)
> +{
> +	struct cb_cmos_option_table *option_table = lib_sysinfo.option_table;
> +	struct cb_cmos_entries *cmos_entry;
> +	int len = strnlen(name, CMOS_MAX_NAME_LENGTH);
> +	
> +	/* cmos entries are located right after the option table */
> +	cmos_entry=(struct cb_cmos_entries*)((unsigned char *)option_table + option_table->header_length);
> +
> +	for (   cmos_entry = (struct cb_cmos_entries*)((unsigned char *)option_table + option_table->header_length);
> +		cmos_entry->tag == CB_TAG_OPTION;
> +		cmos_entry = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size)) {
> +		if (memcmp(cmos_entry->name, name, len))
> +			continue;
> +		if(get_cmos_value(cmos_entry->bit, cmos_entry->length, dest))
> +			return 1;
> +
> +		if(!options_checksum_valid())
> +			return 1;
> +
> +		return 0;
> +	}
> +
> +	printf("ERROR: No such CMOS option (%s)\n", name);
> +	return 1;
> +}

> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From Marc.Jones at amd.com  Wed Aug  6 18:54:17 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Wed, 6 Aug 2008 10:54:17 -0600
Subject: [coreboot] K8 and Fam10 CAR
In-Reply-To: <4899A4B3.4050501@gmx.net>
References: <4899A4B3.4050501@gmx.net>
Message-ID: <4899D739.3080700@amd.com>

Carl-Daniel Hailfinger wrote:
> Hi Marc,
> 
> I'm currently working to unify K8 and Fam10 CAR to use the same code at
> runtime (as opposed to buildtime #ifdefs). While this may not be a goal
> for v2, I definitely want to try it for v3.
> 
> A few questions/comments about the CAR code:
> - Only Fam10 APs are treated specially. APs of older generations seem to
> be unhandled. Did older generations treat each core as BSP (code seems
> to suggest that) or were there other special provisions?

I don't know. I haven't used or worked on that code. YH would be the 
better person to ask. For the fam10 code there are some settings that 
can only be set from the AP cores.


> - "Errata 193: Disable clean copybacks to L3 cache to allow cached ROM."
> Erratum 193 seems to be unlisted in public data sheets. If it is the
> famous L3 problem, we might want to enable the workaround only on
> affected revisions.

This is an errata for early silicon which is why it isn't in the public 
rev guide. It is a fix for caching instructions while in CAR mode. It 
can be removed. All Ax support could be removed.

> - CAR goes from 0xC8000 to 0xCFFFF. Assuming GlobalVarSize=0 (untrue,
> but easier to calculate), BSP stack will be from 0xCC000 to 0xCFFFF and
> AP stacks will be below 0xCBFFF.
> * With the current settings (32k CAR total, 1k per AP, 16K for the BSP)
> the scheme will fall apart if the highest NodeID shifted by the number
> of CoreID bits is 16 or higher. The BKDG indicates that the number of
> CoreID bits is 2, so a NodeID of 4 or higher will break.


Yes. This was sufficient for the K8 and was not changed when I added 
fam10. 8 dual core K8 was the most you could have. It could probably be 
expended into the rest of the shadow hole (up to FFFFF) if needed. The 
reason to keep it in the hole is for memory eye finding that will happen 
from 1MB to TOM.


> * There is no good place to store the printk() buffer in CAR. On Geode
> and i586, the printk buffer runs from the lowest address of the CAR area
> to the middle. Keeping that design will result in the AP stacks
> colliding with the printk buffer. Limiting the size of the printk buffer
> dynamically would work unless there are more than 15 cores in the
> system, where even a printk buffer of zero size would clobber one AP
> stack. The other alternative is to keep the printk buffer size fixed and
> let the AP stacks eat into BSP stack space.

This was the problem I mentioned when you were doing the printk() 
buffer. You are not guaranteed the use of the cache.

> - Is there any reason on any K8 or later processor supported by the
> current CAR code not to use 64k CAR?

To leave room for APs? There may have been some concern about small 
cache versions be introduced?

> - Is 1k enough stack for the APs, given some stack-heavy functions in v3?

I don't know for sure but I would expect it to be ok.

> - Can the K8 processors work reliably with 0x1e1e1e1e settings in the
> fixed MTRR or can the Fam10 processors work with 0x06060606?

No.


Marc


-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors




From ward at gnu.org  Wed Aug  6 21:04:22 2008
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 6 Aug 2008 15:04:22 -0400
Subject: [coreboot] [PATCH] [mkelfimage] integrate buildrom patches
Message-ID: <20080806190422.GA9735@localdomain>

This patch applies to our mkelfimage tree at svn://coreboot.org/repos/trunk/util/mkelfimage.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator
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From jordan.crouse at amd.com  Wed Aug  6 22:22:20 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 6 Aug 2008 14:22:20 -0600
Subject: [coreboot] integrate buildrom patches
In-Reply-To: <20080806190422.GA9735@localdomain>
References: <20080806190422.GA9735@localdomain>
Message-ID: <20080806202220.GC546@cosmic.amd.com>

On 06/08/08 15:04 -0400, Ward Vandewege wrote:
> This patch applies to our mkelfimage tree at svn://coreboot.org/repos/trunk/util/mkelfimage.
> 
> Thanks,
> Ward.

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

> -- 
> Ward Vandewege <ward at fsf.org>
> Free Software Foundation - Senior Systems Administrator


> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From svn at coreboot.org  Wed Aug  6 22:37:38 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 Aug 2008 22:37:38 +0200
Subject: [coreboot] r3473 - in trunk/util/mkelfImage: . linux-i386 linux-ia64
Message-ID: <mailman.1788.1355071351.16123.coreboot@coreboot.org>

Author: ward
Date: 2008-08-06 22:37:38 +0200 (Wed, 06 Aug 2008)
New Revision: 3473

Modified:
   trunk/util/mkelfImage/configure
   trunk/util/mkelfImage/configure.ac
   trunk/util/mkelfImage/linux-i386/convert.h
   trunk/util/mkelfImage/linux-i386/convert.lds
   trunk/util/mkelfImage/linux-i386/head.S
   trunk/util/mkelfImage/linux-i386/mkelf-linux-i386.c
   trunk/util/mkelfImage/linux-ia64/mkelf-linux-ia64.c
Log:

Add the contents of buildrom's

  packages/mkelfimage/mkelfimage-autoconf.patch
  packages/mkelfimage/mkelfImage-2.7-x86_64.patch

to our svn copy of mkelfimage.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>

These are the original commit messages from the buildrom svn tree:

-----------------------------------------------------------------------
r61 | jcrouse | 2007-11-28 13:06:23 -0500 (Wed, 28 Nov 2007) | 9 lines

[BUILDROM]  Fixup mkelfimage

My patch makes it so all targets use vmlinux and 2.7.  Including
the mkelfimage patch from Yhinghai Lu.

Signed-off-by: Myles Watson <myles at pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>

------------------------------------------------------------------------
r80 | jcrouse | 2007-12-10 13:56:40 -0500 (Mon, 10 Dec 2007) | 8 lines

[BUILDROM] Fix breakage in the new mkelfimage autoconf scripts

Whack the autoconf scripts in mkelfimage to allow us to pass our
stack protection flags in.

Signed-off-by: Jordan Crouse <jordan.crouse at amd.com>
Acked-by: Corey Osgood <corey.osgood at gmail.com>

------------------------------------------------------------------------



Modified: trunk/util/mkelfImage/configure
===================================================================
--- trunk/util/mkelfImage/configure	2008-08-05 14:36:20 UTC (rev 3472)
+++ trunk/util/mkelfImage/configure	2008-08-06 20:37:38 UTC (rev 3473)
@@ -1,26 +1,55 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.59.
+# Generated by GNU Autoconf 2.61.
 #
-# Copyright (C) 2003 Free Software Foundation, Inc.
+# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
+# 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 # This configure script is free software; the Free Software Foundation
 # gives unlimited permission to copy, distribute and modify it.
 ## --------------------- ##
 ## M4sh Initialization.  ##
 ## --------------------- ##
 
-# Be Bourne compatible
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
 if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
   emulate sh
   NULLCMD=:
   # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
   # is contrary to our usage.  Disable this feature.
   alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in
+  *posix*) set -o posix ;;
+esac
+
 fi
-DUALCASE=1; export DUALCASE # for MKS sh
 
+
+
+
+# PATH needs CR
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  echo "#! /bin/sh" >conf$$.sh
+  echo  "exit 0"   >>conf$$.sh
+  chmod +x conf$$.sh
+  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+    PATH_SEPARATOR=';'
+  else
+    PATH_SEPARATOR=:
+  fi
+  rm -f conf$$.sh
+fi
+
 # Support unset when possible.
 if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
   as_unset=unset
@@ -29,8 +58,43 @@
 fi
 
 
+# IFS
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+as_nl='
+'
+IFS=" ""	$as_nl"
+
+# Find who we are.  Look in the path if we contain no directory separator.
+case $0 in
+  *[\\/]* ) as_myself=$0 ;;
+  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+done
+IFS=$as_save_IFS
+
+     ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+  as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+  echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+  { (exit 1); exit 1; }
+fi
+
 # Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
+for as_var in ENV MAIL MAILPATH
+do ($as_unset $as_var) >/dev/null 2>&1 && $as_unset $as_var
+done
 PS1='$ '
 PS2='> '
 PS4='+ '
@@ -44,18 +108,19 @@
   if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
     eval $as_var=C; export $as_var
   else
-    $as_unset $as_var
+    ($as_unset $as_var) >/dev/null 2>&1 && $as_unset $as_var
   fi
 done
 
 # Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
   as_expr=expr
 else
   as_expr=false
 fi
 
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
   as_basename=basename
 else
   as_basename=false
@@ -63,157 +128,388 @@
 
 
 # Name of the executable.
-as_me=`$as_basename "$0" ||
+as_me=`$as_basename -- "$0" ||
 $as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
 	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)$' \| \
-	 .     : '\(.\)' 2>/dev/null ||
+	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
 echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-  	  /^X\/\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\/\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
+    sed '/^.*\/\([^/][^/]*\)\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
 
+# CDPATH.
+$as_unset CDPATH
 
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
 
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
+if test "x$CONFIG_SHELL" = x; then
+  if (eval ":") 2>/dev/null; then
+  as_have_required=yes
+else
+  as_have_required=no
 fi
 
+  if test $as_have_required = yes && 	 (eval ":
+(as_func_return () {
+  (exit \$1)
+}
+as_func_success () {
+  as_func_return 0
+}
+as_func_failure () {
+  as_func_return 1
+}
+as_func_ret_success () {
+  return 0
+}
+as_func_ret_failure () {
+  return 1
+}
 
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
+exitcode=0
+if as_func_success; then
+  :
+else
+  exitcode=1
+  echo as_func_success failed.
+fi
 
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
+if as_func_failure; then
+  exitcode=1
+  echo as_func_failure succeeded.
+fi
+
+if as_func_ret_success; then
+  :
+else
+  exitcode=1
+  echo as_func_ret_success failed.
+fi
+
+if as_func_ret_failure; then
+  exitcode=1
+  echo as_func_ret_failure succeeded.
+fi
+
+if ( set x; as_func_ret_success y && test x = \"\$1\" ); then
+  :
+else
+  exitcode=1
+  echo positional parameters were not saved.
+fi
+
+test \$exitcode = 0) || { (exit 1); exit 1; }
+
+(
+  as_lineno_1=\$LINENO
+  as_lineno_2=\$LINENO
+  test \"x\$as_lineno_1\" != \"x\$as_lineno_2\" &&
+  test \"x\`expr \$as_lineno_1 + 1\`\" = \"x\$as_lineno_2\") || { (exit 1); exit 1; }
+") 2> /dev/null; then
+  :
+else
+  as_candidate_shells=
     as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
 for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
 do
   IFS=$as_save_IFS
   test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-	 case $as_dir in
+  case $as_dir in
 	 /*)
-	   if ("$as_dir/$as_base" -c '
+	   for as_base in sh bash ksh sh5; do
+	     as_candidate_shells="$as_candidate_shells $as_dir/$as_base"
+	   done;;
+       esac
+done
+IFS=$as_save_IFS
+
+
+      for as_shell in $as_candidate_shells $SHELL; do
+	 # Try only shells that exist, to save several forks.
+	 if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
+		{ ("$as_shell") 2> /dev/null <<\_ASEOF
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+  emulate sh
+  NULLCMD=:
+  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in
+  *posix*) set -o posix ;;
+esac
+
+fi
+
+
+:
+_ASEOF
+}; then
+  CONFIG_SHELL=$as_shell
+	       as_have_required=yes
+	       if { "$as_shell" 2> /dev/null <<\_ASEOF
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+  emulate sh
+  NULLCMD=:
+  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in
+  *posix*) set -o posix ;;
+esac
+
+fi
+
+
+:
+(as_func_return () {
+  (exit $1)
+}
+as_func_success () {
+  as_func_return 0
+}
+as_func_failure () {
+  as_func_return 1
+}
+as_func_ret_success () {
+  return 0
+}
+as_func_ret_failure () {
+  return 1
+}
+
+exitcode=0
+if as_func_success; then
+  :
+else
+  exitcode=1
+  echo as_func_success failed.
+fi
+
+if as_func_failure; then
+  exitcode=1
+  echo as_func_failure succeeded.
+fi
+
+if as_func_ret_success; then
+  :
+else
+  exitcode=1
+  echo as_func_ret_success failed.
+fi
+
+if as_func_ret_failure; then
+  exitcode=1
+  echo as_func_ret_failure succeeded.
+fi
+
+if ( set x; as_func_ret_success y && test x = "$1" ); then
+  :
+else
+  exitcode=1
+  echo positional parameters were not saved.
+fi
+
+test $exitcode = 0) || { (exit 1); exit 1; }
+
+(
   as_lineno_1=$LINENO
   as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
   test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-	     $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
-	     $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
-	     CONFIG_SHELL=$as_dir/$as_base
-	     export CONFIG_SHELL
-	     exec "$CONFIG_SHELL" "$0" ${1+"$@"}
-	   fi;;
-	 esac
-       done
-done
-;;
-  esac
+  test "x`expr $as_lineno_1 + 1`" = "x$as_lineno_2") || { (exit 1); exit 1; }
 
+_ASEOF
+}; then
+  break
+fi
+
+fi
+
+      done
+
+      if test "x$CONFIG_SHELL" != x; then
+  for as_var in BASH_ENV ENV
+        do ($as_unset $as_var) >/dev/null 2>&1 && $as_unset $as_var
+        done
+        export CONFIG_SHELL
+        exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"}
+fi
+
+
+    if test $as_have_required = no; then
+  echo This script requires a shell more modern than all the
+      echo shells that I found on your system.  Please install a
+      echo modern shell, or manually run the script under such a
+      echo shell if you do have one.
+      { (exit 1); exit 1; }
+fi
+
+
+fi
+
+fi
+
+
+
+(eval "as_func_return () {
+  (exit \$1)
+}
+as_func_success () {
+  as_func_return 0
+}
+as_func_failure () {
+  as_func_return 1
+}
+as_func_ret_success () {
+  return 0
+}
+as_func_ret_failure () {
+  return 1
+}
+
+exitcode=0
+if as_func_success; then
+  :
+else
+  exitcode=1
+  echo as_func_success failed.
+fi
+
+if as_func_failure; then
+  exitcode=1
+  echo as_func_failure succeeded.
+fi
+
+if as_func_ret_success; then
+  :
+else
+  exitcode=1
+  echo as_func_ret_success failed.
+fi
+
+if as_func_ret_failure; then
+  exitcode=1
+  echo as_func_ret_failure succeeded.
+fi
+
+if ( set x; as_func_ret_success y && test x = \"\$1\" ); then
+  :
+else
+  exitcode=1
+  echo positional parameters were not saved.
+fi
+
+test \$exitcode = 0") || {
+  echo No shell found that supports shell functions.
+  echo Please tell autoconf at gnu.org about your system,
+  echo including any error possibly output before this
+  echo message
+}
+
+
+
+  as_lineno_1=$LINENO
+  as_lineno_2=$LINENO
+  test "x$as_lineno_1" != "x$as_lineno_2" &&
+  test "x`expr $as_lineno_1 + 1`" = "x$as_lineno_2" || {
+
   # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
   # uniformly replaced by the line number.  The first 'sed' inserts a
-  # line-number line before each line; the second 'sed' does the real
-  # work.  The second script uses 'N' to pair each line-number line
-  # with the numbered line, and appends trailing '-' during
-  # substitution so that $LINENO is not a special case at line end.
+  # line-number line after each line using $LINENO; the second 'sed'
+  # does the real work.  The second script uses 'N' to pair each
+  # line-number line with the line containing $LINENO, and appends
+  # trailing '-' during substitution so that $LINENO is not a special
+  # case at line end.
   # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
-  # second 'sed' script.  Blame Lee E. McMahon for sed's syntax.  :-)
-  sed '=' <$as_myself |
+  # scripts with optimization help from Paolo Bonzini.  Blame Lee
+  # E. McMahon (1931-1989) for sed's syntax.  :-)
+  sed -n '
+    p
+    /[$]LINENO/=
+  ' <$as_myself |
     sed '
+      s/[$]LINENO.*/&-/
+      t lineno
+      b
+      :lineno
       N
-      s,$,-,
-      : loop
-      s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
+      :loop
+      s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/
       t loop
-      s,-$,,
-      s,^['$as_cr_digits']*\n,,
+      s/-\n.*//
     ' >$as_me.lineno &&
-  chmod +x $as_me.lineno ||
+  chmod +x "$as_me.lineno" ||
     { echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2
    { (exit 1); exit 1; }; }
 
   # Don't try to exec as it changes $[0], causing all sort of problems
   # (the dirname of $[0] is not the place where we might find the
-  # original and so on.  Autoconf is especially sensible to this).
-  . ./$as_me.lineno
+  # original and so on.  Autoconf is especially sensitive to this).
+  . "./$as_me.lineno"
   # Exit status is that of the last command.
   exit
 }
 
 
-case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
-  *c*,-n*) ECHO_N= ECHO_C='
-' ECHO_T='	' ;;
-  *c*,*  ) ECHO_N=-n ECHO_C= ECHO_T= ;;
-  *)       ECHO_N= ECHO_C='\c' ECHO_T= ;;
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+  as_dirname=dirname
+else
+  as_dirname=false
+fi
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in
+-n*)
+  case `echo 'x\c'` in
+  *c*) ECHO_T='	';;	# ECHO_T is single tab character.
+  *)   ECHO_C='\c';;
+  esac;;
+*)
+  ECHO_N='-n';;
 esac
 
-if expr a : '\(a\)' >/dev/null 2>&1; then
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
   as_expr=expr
 else
   as_expr=false
 fi
 
 rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+  rm -f conf$$.dir/conf$$.file
+else
+  rm -f conf$$.dir
+  mkdir conf$$.dir
+fi
 echo >conf$$.file
 if ln -s conf$$.file conf$$ 2>/dev/null; then
-  # We could just check for DJGPP; but this test a) works b) is more generic
-  # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
-  if test -f conf$$.exe; then
-    # Don't use ln at all; we don't have any links
+  as_ln_s='ln -s'
+  # ... but there are two gotchas:
+  # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+  # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+  # In both cases, we have to default to `cp -p'.
+  ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
     as_ln_s='cp -p'
-  else
-    as_ln_s='ln -s'
-  fi
 elif ln conf$$.file conf$$ 2>/dev/null; then
   as_ln_s=ln
 else
   as_ln_s='cp -p'
 fi
-rm -f conf$$ conf$$.exe conf$$.file
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
 
 if mkdir -p . 2>/dev/null; then
   as_mkdir_p=:
@@ -222,7 +518,28 @@
   as_mkdir_p=false
 fi
 
-as_executable_p="test -f"
+if test -x / >/dev/null 2>&1; then
+  as_test_x='test -x'
+else
+  if ls -dL / >/dev/null 2>&1; then
+    as_ls_L_option=L
+  else
+    as_ls_L_option=
+  fi
+  as_test_x='
+    eval sh -c '\''
+      if test -d "$1"; then
+        test -d "$1/.";
+      else
+	case $1 in
+        -*)set "./$1";;
+	esac;
+	case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in
+	???[sx]*):;;*)false;;esac;fi
+    '\'' sh
+  '
+fi
+as_executable_p=$as_test_x
 
 # Sed expression to map a string onto a valid CPP name.
 as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
@@ -231,39 +548,27 @@
 as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
 
 
-# IFS
-# We need space, tab and new line, in precisely that order.
-as_nl='
-'
-IFS=" 	$as_nl"
 
-# CDPATH.
-$as_unset CDPATH
+exec 7<&0 </dev/null 6>&1
 
-
 # Name of the host.
 # hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
 # so uname gets run too.
 ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
 
-exec 6>&1
-
 #
 # Initializations.
 #
 ac_default_prefix=/usr/local
+ac_clean_files=
 ac_config_libobj_dir=.
+LIBOBJS=
 cross_compiling=no
 subdirs=
 MFLAGS=
 MAKEFLAGS=
 SHELL=${CONFIG_SHELL-/bin/sh}
 
-# Maximum number of lines to put in a shell here document.
-# This variable seems obsolete.  It should probably be removed, and
-# only ac_max_sed_lines should be used.
-: ${ac_max_here_lines=38}
-
 # Identity of this package.
 PACKAGE_NAME=
 PACKAGE_TARNAME=
@@ -275,43 +580,137 @@
 # Factoring default headers for most tests.
 ac_includes_default="\
 #include <stdio.h>
-#if HAVE_SYS_TYPES_H
+#ifdef HAVE_SYS_TYPES_H
 # include <sys/types.h>
 #endif
-#if HAVE_SYS_STAT_H
+#ifdef HAVE_SYS_STAT_H
 # include <sys/stat.h>
 #endif
-#if STDC_HEADERS
+#ifdef STDC_HEADERS
 # include <stdlib.h>
 # include <stddef.h>
 #else
-# if HAVE_STDLIB_H
+# ifdef HAVE_STDLIB_H
 #  include <stdlib.h>
 # endif
 #endif
-#if HAVE_STRING_H
-# if !STDC_HEADERS && HAVE_MEMORY_H
+#ifdef HAVE_STRING_H
+# if !defined STDC_HEADERS && defined HAVE_MEMORY_H
 #  include <memory.h>
 # endif
 # include <string.h>
 #endif
-#if HAVE_STRINGS_H
+#ifdef HAVE_STRINGS_H
 # include <strings.h>
 #endif
-#if HAVE_INTTYPES_H
+#ifdef HAVE_INTTYPES_H
 # include <inttypes.h>
-#else
-# if HAVE_STDINT_H
-#  include <stdint.h>
-# endif
 #endif
-#if HAVE_UNISTD_H
+#ifdef HAVE_STDINT_H
+# include <stdint.h>
+#endif
+#ifdef HAVE_UNISTD_H
 # include <unistd.h>
 #endif"
 
-ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT MKDIR RM CP LN TAR RPM SED FIND CPP EGREP LD ac_ct_LD AS ac_ct_AS OBJCOPY ac_ct_OBJCOPY I386_CC I386_CPP I386_LD I386_AS I386_OBJCOPY IA64_CC IA64_CPP IA64_LD IA64_AS IA64_OBJCOPY HOST_CC HOST_CFLAGS I386_CFLAGS I386_ASFLAGS I386_LDFLAGS IA64_CFLAGS IA64_ASFLAGS IA64_LDFLAGS LIBOBJS LTLIBOBJS'
+ac_subst_vars='SHELL
+PATH_SEPARATOR
+PACKAGE_NAME
+PACKAGE_TARNAME
+PACKAGE_VERSION
+PACKAGE_STRING
+PACKAGE_BUGREPORT
+exec_prefix
+prefix
+program_transform_name
+bindir
+sbindir
+libexecdir
+datarootdir
+datadir
+sysconfdir
+sharedstatedir
+localstatedir
+includedir
+oldincludedir
+docdir
+infodir
+htmldir
+dvidir
+pdfdir
+psdir
+libdir
+localedir
+mandir
+DEFS
+ECHO_C
+ECHO_N
+ECHO_T
+LIBS
+build_alias
+host_alias
+target_alias
+build
+build_cpu
+build_vendor
+build_os
+host
+host_cpu
+host_vendor
+host_os
+CC
+CFLAGS
+LDFLAGS
+CPPFLAGS
+ac_ct_CC
+EXEEXT
+OBJEXT
+MKDIR
+RM
+CP
+LN
+TAR
+RPM
+SED
+FIND
+CPP
+GREP
+EGREP
+LD
+AS
+OBJCOPY
+I386_CC
+I386_CPP
+I386_LD
+I386_AS
+I386_OBJCOPY
+IA64_CC
+IA64_CPP
+IA64_LD
+IA64_AS
+IA64_OBJCOPY
+HOST_CC
+HOST_CFLAGS
+I386_CFLAGS
+I386_ASFLAGS
+I386_LDFLAGS
+IA64_CFLAGS
+IA64_ASFLAGS
+IA64_LDFLAGS
+LIBOBJS
+LTLIBOBJS'
 ac_subst_files=''
+      ac_precious_vars='build_alias
+host_alias
+target_alias
+CC
+CFLAGS
+LDFLAGS
+LIBS
+CPPFLAGS
+CPP'
 
+
 # Initialize some variables set by options.
 ac_init_help=
 ac_init_version=false
@@ -337,34 +736,48 @@
 # and all the variables that are supposed to be based on exec_prefix
 # by default will actually change.
 # Use braces instead of parens because sh, perl, etc. also accept them.
+# (The list follows the same order as the GNU Coding Standards.)
 bindir='${exec_prefix}/bin'
 sbindir='${exec_prefix}/sbin'
 libexecdir='${exec_prefix}/libexec'
-datadir='${prefix}/share'
+datarootdir='${prefix}/share'
+datadir='${datarootdir}'
 sysconfdir='${prefix}/etc'
 sharedstatedir='${prefix}/com'
 localstatedir='${prefix}/var'
-libdir='${exec_prefix}/lib'
 includedir='${prefix}/include'
 oldincludedir='/usr/include'
-infodir='${prefix}/info'
-mandir='${prefix}/man'
+docdir='${datarootdir}/doc/${PACKAGE}'
+infodir='${datarootdir}/info'
+htmldir='${docdir}'
+dvidir='${docdir}'
+pdfdir='${docdir}'
+psdir='${docdir}'
+libdir='${exec_prefix}/lib'
+localedir='${datarootdir}/locale'
+mandir='${datarootdir}/man'
 
 ac_prev=
+ac_dashdash=
 for ac_option
 do
   # If the previous option needs an argument, assign it.
   if test -n "$ac_prev"; then
-    eval "$ac_prev=\$ac_option"
+    eval $ac_prev=\$ac_option
     ac_prev=
     continue
   fi
 
-  ac_optarg=`expr "x$ac_option" : 'x[^=]*=\(.*\)'`
+  case $ac_option in
+  *=*)	ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
+  *)	ac_optarg=yes ;;
+  esac
 
   # Accept the important Cygnus configure options, so we can diagnose typos.
 
-  case $ac_option in
+  case $ac_dashdash$ac_option in
+  --)
+    ac_dashdash=yes ;;
 
   -bindir | --bindir | --bindi | --bind | --bin | --bi)
     ac_prev=bindir ;;
@@ -386,33 +799,45 @@
   --config-cache | -C)
     cache_file=config.cache ;;
 
-  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+  -datadir | --datadir | --datadi | --datad)
     ac_prev=datadir ;;
-  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
-  | --da=*)
+  -datadir=* | --datadir=* | --datadi=* | --datad=*)
     datadir=$ac_optarg ;;
 
+  -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \
+  | --dataroo | --dataro | --datar)
+    ac_prev=datarootdir ;;
+  -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \
+  | --dataroot=* | --dataroo=* | --dataro=* | --datar=*)
+    datarootdir=$ac_optarg ;;
+
   -disable-* | --disable-*)
     ac_feature=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
     # Reject names that are not valid shell variable names.
-    expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+    expr "x$ac_feature" : ".*[^-._$as_cr_alnum]" >/dev/null &&
       { echo "$as_me: error: invalid feature name: $ac_feature" >&2
    { (exit 1); exit 1; }; }
-    ac_feature=`echo $ac_feature | sed 's/-/_/g'`
-    eval "enable_$ac_feature=no" ;;
+    ac_feature=`echo $ac_feature | sed 's/[-.]/_/g'`
+    eval enable_$ac_feature=no ;;
 
+  -docdir | --docdir | --docdi | --doc | --do)
+    ac_prev=docdir ;;
+  -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*)
+    docdir=$ac_optarg ;;
+
+  -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv)
+    ac_prev=dvidir ;;
+  -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*)
+    dvidir=$ac_optarg ;;
+
   -enable-* | --enable-*)
     ac_feature=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
     # Reject names that are not valid shell variable names.
-    expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+    expr "x$ac_feature" : ".*[^-._$as_cr_alnum]" >/dev/null &&
       { echo "$as_me: error: invalid feature name: $ac_feature" >&2
    { (exit 1); exit 1; }; }
-    ac_feature=`echo $ac_feature | sed 's/-/_/g'`
-    case $ac_option in
-      *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "enable_$ac_feature='$ac_optarg'" ;;
+    ac_feature=`echo $ac_feature | sed 's/[-.]/_/g'`
+    eval enable_$ac_feature=\$ac_optarg ;;
 
   -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
   | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
@@ -439,6 +864,12 @@
   -host=* | --host=* | --hos=* | --ho=*)
     host_alias=$ac_optarg ;;
 
+  -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht)
+    ac_prev=htmldir ;;
+  -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \
+  | --ht=*)
+    htmldir=$ac_optarg ;;
+
   -includedir | --includedir | --includedi | --included | --include \
   | --includ | --inclu | --incl | --inc)
     ac_prev=includedir ;;
@@ -463,13 +894,16 @@
   | --libexe=* | --libex=* | --libe=*)
     libexecdir=$ac_optarg ;;
 
+  -localedir | --localedir | --localedi | --localed | --locale)
+    ac_prev=localedir ;;
+  -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*)
+    localedir=$ac_optarg ;;
+
   -localstatedir | --localstatedir | --localstatedi | --localstated \
-  | --localstate | --localstat | --localsta | --localst \
-  | --locals | --local | --loca | --loc | --lo)
+  | --localstate | --localstat | --localsta | --localst | --locals)
     ac_prev=localstatedir ;;
   -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
-  | --localstate=* | --localstat=* | --localsta=* | --localst=* \
-  | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+  | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*)
     localstatedir=$ac_optarg ;;
 
   -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
@@ -534,6 +968,16 @@
   | --progr-tra=* | --program-tr=* | --program-t=*)
     program_transform_name=$ac_optarg ;;
 
+  -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd)
+    ac_prev=pdfdir ;;
+  -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*)
+    pdfdir=$ac_optarg ;;
+
+  -psdir | --psdir | --psdi | --psd | --ps)
+    ac_prev=psdir ;;
+  -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*)
+    psdir=$ac_optarg ;;
+
   -q | -quiet | --quiet | --quie | --qui | --qu | --q \
   | -silent | --silent | --silen | --sile | --sil)
     silent=yes ;;
@@ -586,24 +1030,20 @@
   -with-* | --with-*)
     ac_package=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
     # Reject names that are not valid shell variable names.
-    expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+    expr "x$ac_package" : ".*[^-._$as_cr_alnum]" >/dev/null &&
       { echo "$as_me: error: invalid package name: $ac_package" >&2
    { (exit 1); exit 1; }; }
-    ac_package=`echo $ac_package| sed 's/-/_/g'`
-    case $ac_option in
-      *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "with_$ac_package='$ac_optarg'" ;;
+    ac_package=`echo $ac_package | sed 's/[-.]/_/g'`
+    eval with_$ac_package=\$ac_optarg ;;
 
   -without-* | --without-*)
     ac_package=`expr "x$ac_option" : 'x-*without-\(.*\)'`
     # Reject names that are not valid shell variable names.
-    expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+    expr "x$ac_package" : ".*[^-._$as_cr_alnum]" >/dev/null &&
       { echo "$as_me: error: invalid package name: $ac_package" >&2
    { (exit 1); exit 1; }; }
-    ac_package=`echo $ac_package | sed 's/-/_/g'`
-    eval "with_$ac_package=no" ;;
+    ac_package=`echo $ac_package | sed 's/[-.]/_/g'`
+    eval with_$ac_package=no ;;
 
   --x)
     # Obsolete; use --with-x.
@@ -634,8 +1074,7 @@
     expr "x$ac_envvar" : ".*[^_$as_cr_alnum]" >/dev/null &&
       { echo "$as_me: error: invalid variable name: $ac_envvar" >&2
    { (exit 1); exit 1; }; }
-    ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`
-    eval "$ac_envvar='$ac_optarg'"
+    eval $ac_envvar=\$ac_optarg
     export $ac_envvar ;;
 
   *)
@@ -655,29 +1094,21 @@
    { (exit 1); exit 1; }; }
 fi
 
-# Be sure to have absolute paths.
-for ac_var in exec_prefix prefix
+# Be sure to have absolute directory names.
+for ac_var in	exec_prefix prefix bindir sbindir libexecdir datarootdir \
+		datadir sysconfdir sharedstatedir localstatedir includedir \
+		oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
+		libdir localedir mandir
 do
-  eval ac_val=$`echo $ac_var`
+  eval ac_val=\$$ac_var
   case $ac_val in
-    [\\/$]* | ?:[\\/]* | NONE | '' ) ;;
-    *)  { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
-   { (exit 1); exit 1; }; };;
+    [\\/$]* | ?:[\\/]* )  continue;;
+    NONE | '' ) case $ac_var in *prefix ) continue;; esac;;
   esac
+  { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
+   { (exit 1); exit 1; }; }
 done
 
-# Be sure to have absolute paths.
-for ac_var in bindir sbindir libexecdir datadir sysconfdir sharedstatedir \
-	      localstatedir libdir includedir oldincludedir infodir mandir
-do
-  eval ac_val=$`echo $ac_var`
-  case $ac_val in
-    [\\/$]* | ?:[\\/]* ) ;;
-    *)  { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
 # There might be people who depend on the old broken behavior: `$host'
 # used to hold the argument of --host etc.
 # FIXME: To remove some day.
@@ -702,74 +1133,76 @@
 test "$silent" = yes && exec 6>/dev/null
 
 
+ac_pwd=`pwd` && test -n "$ac_pwd" &&
+ac_ls_di=`ls -di .` &&
+ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` ||
+  { echo "$as_me: error: Working directory cannot be determined" >&2
+   { (exit 1); exit 1; }; }
+test "X$ac_ls_di" = "X$ac_pwd_ls_di" ||
+  { echo "$as_me: error: pwd does not report name of working directory" >&2
+   { (exit 1); exit 1; }; }
+
+
 # Find the source files, if location was not specified.
 if test -z "$srcdir"; then
   ac_srcdir_defaulted=yes
-  # Try the directory containing this script, then its parent.
-  ac_confdir=`(dirname "$0") 2>/dev/null ||
+  # Try the directory containing this script, then the parent directory.
+  ac_confdir=`$as_dirname -- "$0" ||
 $as_expr X"$0" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
 	 X"$0" : 'X\(//\)[^/]' \| \
 	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
+	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
 echo X"$0" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
   srcdir=$ac_confdir
-  if test ! -r $srcdir/$ac_unique_file; then
+  if test ! -r "$srcdir/$ac_unique_file"; then
     srcdir=..
   fi
 else
   ac_srcdir_defaulted=no
 fi
-if test ! -r $srcdir/$ac_unique_file; then
-  if test "$ac_srcdir_defaulted" = yes; then
-    { echo "$as_me: error: cannot find sources ($ac_unique_file) in $ac_confdir or .." >&2
+if test ! -r "$srcdir/$ac_unique_file"; then
+  test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .."
+  { echo "$as_me: error: cannot find sources ($ac_unique_file) in $srcdir" >&2
    { (exit 1); exit 1; }; }
-  else
-    { echo "$as_me: error: cannot find sources ($ac_unique_file) in $srcdir" >&2
+fi
+ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work"
+ac_abs_confdir=`(
+	cd "$srcdir" && test -r "./$ac_unique_file" || { echo "$as_me: error: $ac_msg" >&2
    { (exit 1); exit 1; }; }
-  fi
+	pwd)`
+# When building in place, set srcdir=.
+if test "$ac_abs_confdir" = "$ac_pwd"; then
+  srcdir=.
 fi
-(cd $srcdir && test -r ./$ac_unique_file) 2>/dev/null ||
-  { echo "$as_me: error: sources are in $srcdir, but \`cd $srcdir' does not work" >&2
-   { (exit 1); exit 1; }; }
-srcdir=`echo "$srcdir" | sed 's%\([^\\/]\)[\\/]*$%\1%'`
-ac_env_build_alias_set=${build_alias+set}
-ac_env_build_alias_value=$build_alias
-ac_cv_env_build_alias_set=${build_alias+set}
-ac_cv_env_build_alias_value=$build_alias
-ac_env_host_alias_set=${host_alias+set}
-ac_env_host_alias_value=$host_alias
-ac_cv_env_host_alias_set=${host_alias+set}
-ac_cv_env_host_alias_value=$host_alias
-ac_env_target_alias_set=${target_alias+set}
-ac_env_target_alias_value=$target_alias
-ac_cv_env_target_alias_set=${target_alias+set}
-ac_cv_env_target_alias_value=$target_alias
-ac_env_CC_set=${CC+set}
-ac_env_CC_value=$CC
-ac_cv_env_CC_set=${CC+set}
-ac_cv_env_CC_value=$CC
-ac_env_CFLAGS_set=${CFLAGS+set}
-ac_env_CFLAGS_value=$CFLAGS
-ac_cv_env_CFLAGS_set=${CFLAGS+set}
-ac_cv_env_CFLAGS_value=$CFLAGS
-ac_env_LDFLAGS_set=${LDFLAGS+set}
-ac_env_LDFLAGS_value=$LDFLAGS
-ac_cv_env_LDFLAGS_set=${LDFLAGS+set}
-ac_cv_env_LDFLAGS_value=$LDFLAGS
-ac_env_CPPFLAGS_set=${CPPFLAGS+set}
-ac_env_CPPFLAGS_value=$CPPFLAGS
-ac_cv_env_CPPFLAGS_set=${CPPFLAGS+set}
-ac_cv_env_CPPFLAGS_value=$CPPFLAGS
-ac_env_CPP_set=${CPP+set}
-ac_env_CPP_value=$CPP
-ac_cv_env_CPP_set=${CPP+set}
-ac_cv_env_CPP_value=$CPP
+# Remove unnecessary trailing slashes from srcdir.
+# Double slashes in file names in object file debugging info
+# mess up M-x gdb in Emacs.
+case $srcdir in
+*/) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;;
+esac
+for ac_var in $ac_precious_vars; do
+  eval ac_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_env_${ac_var}_value=\$${ac_var}
+  eval ac_cv_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_cv_env_${ac_var}_value=\$${ac_var}
+done
 
 #
 # Report the --help message.
@@ -798,9 +1231,6 @@
   -n, --no-create         do not create output files
       --srcdir=DIR        find the sources in DIR [configure dir or \`..']
 
-_ACEOF
-
-  cat <<_ACEOF
 Installation directories:
   --prefix=PREFIX         install architecture-independent files in PREFIX
 			  [$ac_default_prefix]
@@ -818,15 +1248,22 @@
   --bindir=DIR           user executables [EPREFIX/bin]
   --sbindir=DIR          system admin executables [EPREFIX/sbin]
   --libexecdir=DIR       program executables [EPREFIX/libexec]
-  --datadir=DIR          read-only architecture-independent data [PREFIX/share]
   --sysconfdir=DIR       read-only single-machine data [PREFIX/etc]
   --sharedstatedir=DIR   modifiable architecture-independent data [PREFIX/com]
   --localstatedir=DIR    modifiable single-machine data [PREFIX/var]
   --libdir=DIR           object code libraries [EPREFIX/lib]
   --includedir=DIR       C header files [PREFIX/include]
   --oldincludedir=DIR    C header files for non-gcc [/usr/include]
-  --infodir=DIR          info documentation [PREFIX/info]
-  --mandir=DIR           man documentation [PREFIX/man]
+  --datarootdir=DIR      read-only arch.-independent data root [PREFIX/share]
+  --datadir=DIR          read-only architecture-independent data [DATAROOTDIR]
+  --infodir=DIR          info documentation [DATAROOTDIR/info]
+  --localedir=DIR        locale-dependent data [DATAROOTDIR/locale]
+  --mandir=DIR           man documentation [DATAROOTDIR/man]
+  --docdir=DIR           documentation root [DATAROOTDIR/doc/PACKAGE]
+  --htmldir=DIR          html documentation [DOCDIR]
+  --dvidir=DIR           dvi documentation [DOCDIR]
+  --pdfdir=DIR           pdf documentation [DOCDIR]
+  --psdir=DIR            ps documentation [DOCDIR]
 _ACEOF
 
   cat <<\_ACEOF
@@ -852,126 +1289,95 @@
   CFLAGS      C compiler flags
   LDFLAGS     linker flags, e.g. -L<lib dir> if you have libraries in a
               nonstandard directory <lib dir>
-  CPPFLAGS    C/C++ preprocessor flags, e.g. -I<include dir> if you have
-              headers in a nonstandard directory <include dir>
+  LIBS        libraries to pass to the linker, e.g. -l<library>
+  CPPFLAGS    C/C++/Objective C preprocessor flags, e.g. -I<include dir> if
+              you have headers in a nonstandard directory <include dir>
   CPP         C preprocessor
 
 Use these variables to override the choices made by `configure' or to help
 it to find libraries and programs with nonstandard names/locations.
 
 _ACEOF
+ac_status=$?
 fi
 
 if test "$ac_init_help" = "recursive"; then
   # If there are subdirs, report their specific --help.
-  ac_popdir=`pwd`
   for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
-    test -d $ac_dir || continue
+    test -d "$ac_dir" || continue
     ac_builddir=.
 
-if test "$ac_dir" != .; then
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
   ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
+  # A ".." for each direc