[coreboot] brainstorm: new LPC dongle from Artec Group
stepan at coresystems.de
Fri Aug 8 15:02:13 CEST 2008
we're using two of the dongles at coresystems; and they're in use many
times every day. Thank you guys for creating this device. It almost
completely replaced the Galep V here for non-SPI systems.
With parallel abuild, a compile+flash cycle for an 8MBit image takes
about 30s, the dongle part takes about 25s of that time.
Peter Stuge wrote:
> On Fri, Aug 08, 2008 at 02:15:39PM +0300, Martin-Éric Racine wrote:
>> In conjunction with item #2 above, we are hereby giving the Coreboot
>> community an opportunity to influence the design of this new product.
> I have a few thoughts, in order of importance they are:
> * By far the most important one: Use a more intelligent USB chip
> USB can do 480Mbps so transfering half a megabyte should not need to
> take several seconds. There is obviously a huge opportunity for
> improvement here, and as it happens this is also the main bottleneck
> in the dongle when doing intensive development.
> The most elegant solution is to implement USB completely in the FPGA,
> but a separate chip is likely more economical. Key point is that it
> must not be a dumb serial chip.
* Possibly, in connection with this, use SRAM or DRAM to store or cache
the images transferred from the host side. I think writing the flash
takes about as long as transferring it over serial port, so using a
faster USB (network instead of serial) chip would only move the bottle neck.
* One habit of the dongle is very ugly; the need to reset it after
loading it. I think it would be a good idea to have the dongle reset
itself (or, the lpc part of itself) after the write process is complete.
* 0x3f8 serial port logging support on lpc. (Sorry, I never looked into
* A couple of jumper pins could be preconfigured as host side software
programmable GPIOs for tasks like triggering a reset on the target system.
* Deliver the dongle with a PLCC plug header, or offer it as an option.
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