[coreboot] k8 status
Marc.Jones at amd.com
Mon Aug 25 22:56:56 CEST 2008
Carl-Daniel Hailfinger wrote:
> Hi Marc,
> we need your Fam10h expertise for this.
> On 24.08.2008 20:32, ron minnich wrote:
>> On Sun, Aug 24, 2008 at 11:27 AM, Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>>> On 24.08.2008 19:49, ron minnich wrote:
>>>> Note there are things left to do that are not at first obvious
>>>> 1. all core0's in initram have to load microcode
>>> This is going to hurt. You know that we only have 1k stack on all APs
>>> (that includes core0 of every non-BSP)? With some ugly trickery, I think
>>> 2k stack are possible, but you don't want to go there. Our v3 functions
>>> are not really optimized to fit into a small stack.
>> fam10 requires microcode load prior to ram setup. We have to make this work.
> OK. It's unfortunate, but we can make it work.
1K of stack should still be plenty. If it is being used up we need to
understand why. Each core should be able to snoop any cache so global
vars and structs shouldn't be getting passed on the stack. They should
be in the BSP cache/stack only.
>>> Can't we postpone microcode loading to stage2 or at least past initram?
>> AMD tells me not for fam10, so we might as well get it right from the start.
>> question: if BSP brings up ram, can't APs use that BSP ram? Is there
>> any reason this would not work?
> I think Marc answered parts of this in the thread titled "[coreboot] K8
> and Fam10 CAR". Other parts may be answered in the thread titled
> "[coreboot] AMD64 BKDG questions". These two threads are marked for
> re-reading in my mail folder because they have lots of valuable info.
> Looking at http://linuxbios.org/data/yhlu/LinuxBIOS_CAR_09142006.pdf
> your idea would probably need some re-architecting of the v3 code.
The BSP does all the memory init. It doesn't matter what CPU it is on.
It makes one contiguous memory space and is shared by all cores. If the
microcode is in the BSP cache (or in system memory later) the APs can
load it, BUT I don't think that using the cache is too important. In my
experience on fam10, it doesn't take long for the APs to load microcode
off the ROM since they do it all at once.
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
More information about the coreboot