[coreboot] [PATCH] v3: fix PCI bus scan / device tree interaction

[Carl-Daniel Hailfinger]

On 29.08.2008 18:27, Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [080829 12:54]:
>   
>> On 29.08.2008 12:41, Stefan Reinauer wrote:
>>     
>>> Carl-Daniel Hailfinger wrote:
>>>   
>>>       
>>>> +	 * dev->link[0] for a PCI domain is the domain link.
>>>> +	 * The child of the domain link is the PCI bus device.
>>>>   
>>>>     
>>>>         
>>> "PCI bus device" - is that the host bridge?
>>>   
>>>       
>> Let me illustrate this with an excerpt of our device tree.
>>
>> We call pci_domain_scan_bus(dev_domain_0, ...) and dev_domain_0->link[0]
>> is the PCI domain link. However, pci_scan_bus() expects to be called
>> with dev_bus_0->link[0] which equals
>> dev_domain_0->link[0].children->link[0]. "pci bus device" refers to
>> dev_bus_0.
>>     
>  
> Ok, so why do we have 
>
> a) a pci domain
> b) a pci bus "device" whatever that is supposed to depict
> c) a pci bridge (host bridge)
>
> all describing the same physical entity.
>
> We had weird stuff in v2, but now it's not fixed, it's just different
> weird. 
>
>   
>> Can multiple buses be directly below a domain or do these buses hang off
>> a bridge on a bus? For the latter case, this should be handled by
>> pci_scan_bridge.
>>     
>
> A PCI domain is not a physical device. It doesnt even virtually exist on
> x86, at least not on pre-PCIe systems.
>   

OK, let me rephrase my question and answer it in part withe the help of
the relevant standards.
Is it possible to have multiple top-level PCI Buses? Yes, but only in
the sense that top-level Buses are attached to different Host Bridges.

The PCI-to-PCI Bridge Architecture 1.2
<http://www.pcisig.com/members/downloads/specifications/conventional/ppb12.pdf>
standard says that each PCI Bridge has exactly one primary and one
secondary interface, each with exactly one Bus attached. So it is not
possible to have multiple PCI Buses directly below a PCI Bridge.

That means for my patch:
IFF we only have one top-level PCI Bus (anything else is impossible with
only one Host Bridge) my patch is completely correct. However, IFF there
are multiple independent Host Bridges which do NOT share a PCI bus, we
need to implement a function which iterates over these Host Bridges.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/