[coreboot] [PATCH] v3: fix PCI bus scan / device tree interaction

Stefan Reinauer stepan at coresystems.de
Sat Aug 30 00:53:04 CEST 2008

Carl-Daniel Hailfinger wrote:
> IFF we only have one top-level PCI Bus (anything else is impossible with
> only one Host Bridge) my patch is completely correct. However, IFF there
> are multiple independent Host Bridges which do NOT share a PCI bus, we
> need to implement a function which iterates over these Host Bridges.
Which happens on non-x86 systems and occasionally can happen on x86 PCIe.

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