From gregg.drwho8 at gmail.com  Mon Dec  1 01:33:19 2008
From: gregg.drwho8 at gmail.com (Gregg Levine)
Date: Sun, 30 Nov 2008 19:33:19 -0500
Subject: [coreboot] Baremetal bootloader project
Message-ID: <18d205ed0811301633s18a34cb7r3f16090f87774c9c@mail.gmail.com>

Hello!
During the ramp up that brought us to the coreboot project, one Steven
James contributed a project he called Baremetal, and described it as a
bootloader of sorts. During that time period I actually did get it to
build, but sadly never did get around to test it.

Was this project imported along with everything else to the coreboot
storage point that we access using subversion? (As it happens I have
now gotten one of the currently available loaders to work using Qemu.)

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature was once found posting rude
 messages in English in the Moscow subway."



From corey.osgood at gmail.com  Mon Dec  1 02:56:43 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sun, 30 Nov 2008 20:56:43 -0500
Subject: [coreboot] Baremetal bootloader project
In-Reply-To: <18d205ed0811301633s18a34cb7r3f16090f87774c9c@mail.gmail.com>
References: <18d205ed0811301633s18a34cb7r3f16090f87774c9c@mail.gmail.com>
Message-ID: <dd3c80060811301756o82a23b9ob3bb8c36747a4a0f@mail.gmail.com>

IIRC, baremetal was/is a simple "Hello World"-esque payload that was
intended as something to base future payloads on. I'm pretty sure it's in
the linuxbios-v1 repository.

-Corey

On Sun, Nov 30, 2008 at 7:33 PM, Gregg Levine <gregg.drwho8 at gmail.com>wrote:

> Hello!
> During the ramp up that brought us to the coreboot project, one Steven
> James contributed a project he called Baremetal, and described it as a
> bootloader of sorts. During that time period I actually did get it to
> build, but sadly never did get around to test it.
>
> Was this project imported along with everything else to the coreboot
> storage point that we access using subversion? (As it happens I have
> now gotten one of the currently available loaders to work using Qemu.)
>
> -----
> Gregg C Levine gregg.drwho8 at gmail.com
> "This signature was once found posting rude
>  messages in English in the Moscow subway."
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From fengyuning1984 at gmail.com  Mon Dec  1 05:05:49 2008
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Mon, 1 Dec 2008 12:05:49 +0800
Subject: [coreboot] [PATCH] flashrom: sector-based flashing
In-Reply-To: <a505dc9d0811290423n46e2eadchf34bff292f0eb263@mail.gmail.com>
References: <48F01FA7.7030206@gmx.net>
	<13426df10810102107r6b06ee3bh736b3bf5c3e3e8@mail.gmail.com>
	<48F11E1A.9050609@gmx.net> <49105043.4010404@gmx.net>
	<20081105092119.17748.qmail@stuge.se> <49117CF7.2090307@gmx.net>
	<49309797.1050203@gmx.net>
	<a505dc9d0811290423n46e2eadchf34bff292f0eb263@mail.gmail.com>
Message-ID: <a505dc9d0811302005x1b3b4ae6uca7882687d8363ca@mail.gmail.com>

On Sat, Nov 29, 2008 at 8:23 PM, FENG Yu Ning <fengyuning1984 at gmail.com> wrote:
> On Sat, Nov 29, 2008 at 9:15 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> Index: flashrom-eraseblocks/flashrom.c
>> ===================================================================
>> --- flashrom-eraseblocks/flashrom.c     (Revision 3776)
>> +++ flashrom-eraseblocks/flashrom.c     (Arbeitskopie)
>> @@ -534,11 +534,33 @@
>>
>>        if (erase_it) {
>>                printf("Erasing flash chip.\n");
>> -               if (!flash->erase) {
>> -                       fprintf(stderr, "Error: flashrom has no erase function for this flash chip.\n");
>> +               if (!flash->block_erase && flash->eraseblocks[0].count) {
>> +                       fprintf(stderr, "Hint: flashrom knows the eraseblock "
>> +                               "layout, but there is no blockwise erase "
>> +                               "function for this flash chip. "
>> +                               "Using whole-chip erase.\n");
>> +               }
>> +               if (flash->block_erase && !flash->eraseblocks[0].count) {
>> +                       fprintf(stderr, "Hint: flashrom has a blockwise erase "
>> +                               "function for this flash chip, but the "
>> +                               "eraseblock layout is unknown. "
>> +                               "Using whole-chip erase.\n");
>> +               }
>> +               if (flash->block_erase && flash->eraseblocks[0].count) {
>> +                       unsigned long done = 0;
>> +                       int i, j;
>> +                       for (i = 0; done < flash->total_size * 1024; i++) {
>> +                               for (j = 0; j < flash->eraseblocks[i].count; j++) {
>> +                                       flash->block_erase(flash, done + flash->eraseblocks[i].size * j);
>> +                               }
>> +                               done += flash->eraseblocks[i].count * flash->eraseblocks[i].size;
>> +                       }
>> +               } else if (flash->erase) {
>> +                       flash->erase(flash);
>> +               } else {
>> +                       fprintf(stderr, "Error: flashrom has no chip erase function for this flash chip.\n");
>>                        return 1;
>>                }
>> -               flash->erase(flash);
>>                exit(0);
>>        } else if (read_it) {
>>                if ((image = fopen(filename, "w")) == NULL) {
>
> No comment to the logic. But the new code has a different degree of
> detail compared to other 'if (do_it)' blocks(i.e., the for loop).

I do have a comment to the logic now. If we want to erase a whole
chip, we shall try 'flash->erase' first.

yu ning



From fengyuning1984 at gmail.com  Mon Dec  1 09:14:30 2008
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Mon, 1 Dec 2008 16:14:30 +0800
Subject: [coreboot] [PATCH] flashrom: flashchips.c cosmetic change
Message-ID: <a505dc9d0812010014k29c97afxe8c48a4990616242@mail.gmail.com>

Breaks chip info into multiple lines.

Patch excerpt:

 struct flashchip flashchips[] = {
-	/**********************************************************************************************************************************************************************************************************************/
-	/* Vendor	Chip			Vendor ID	Chip ID		Total size (kB)	Page size
(B)	Test status	Probe function		Erase function			Write function		Read
function */
-	/**********************************************************************************************************************************************************************************************************************/
-	{"AMD",		"Am29F002(N)BB",	AMD_ID,		AM_29F002BB,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
+
+	/* Vendor, Chip, Vendor ID, Chip ID,
+	 * Total size (kB), Page size (B),
+	 * Test status,
+	 * Probe function, Erase function, Write function, Read function
+	 */
+
+	{"AMD", "Am29F002(N)BB", AMD_ID, AM_29F002BB,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_en29f002a
+	},
+

Signed-off-by: FENG yu ning <fengyuning1984 at gmail.com>
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From chris at stockwith.co.uk  Mon Dec  1 11:40:09 2008
From: chris at stockwith.co.uk (Chris Lingard)
Date: Mon, 01 Dec 2008 10:40:09 +0000
Subject: [coreboot] Free chips, not required by me, and a question
In-Reply-To: <4931E92C.1020807@gmx.net>
References: <493111FB.9000701@stockwith.co.uk> <4931E92C.1020807@gmx.net>
Message-ID: <4933BF09.7080501@stockwith.co.uk>

Carl-Daniel Hailfinger wrote:
> On 29.11.2008 10:57, Chris Lingard wrote:
>> Now I need help, my machine has Pm49FL004 chips as standard, I have
>> some Pm49FL008 too.
>>
>> I want a 32 M Bit flash chip, if there is such a thing for this type

> Can you tell us more about your mainboard chipset? The Pm49FL004 can do
> LPC and FWH, but a board only needs one of them.
> 
> I thought I had seen some data sheets for 32 Mbit chips, but it seems
> they all were SPI and not FWH/LPC.

Thanks for all the information.  I have done some reading and got the 
data sheets.  My chips are PLCC, (nearly square with pins on all four 
sides).

So am I stuck?  They do not make large capacity {SST,Pm}49LF0??) PLCC 
chips, or is it just an old chip?

Chris Lingard





From svn at coreboot.org  Mon Dec  1 15:18:57 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Dec 2008 15:18:57 +0100
Subject: [coreboot] r3784 - trunk/util/superiotool
Message-ID: <mailman.2528.1355071445.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-12-01 15:18:57 +0100 (Mon, 01 Dec 2008)
New Revision: 3784

Modified:
   trunk/util/superiotool/ali.c
   trunk/util/superiotool/fintek.c
   trunk/util/superiotool/ite.c
   trunk/util/superiotool/nsc.c
   trunk/util/superiotool/smsc.c
   trunk/util/superiotool/superiotool.c
   trunk/util/superiotool/superiotool.h
   trunk/util/superiotool/winbond.c
Log:
The Winbond Super I/O chips have another indirection of registers. The
hwmon has generic registers and banked registers, mostly temperature
handling, and SMI/GPIO stuff.

Not all LDNs are switched via register offset 0x07, make it a parameter.
  
Add support for dumping the hardware monitor of Winbond W83627THF/THG
parts with the -e option.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/superiotool/ali.c
===================================================================
--- trunk/util/superiotool/ali.c	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/ali.c	2008-12-01 14:18:57 UTC (rev 3784)
@@ -95,7 +95,7 @@
 	       get_superio_name(reg_table, id), id, rev, port);
 	chip_found = 1;
 
-	dump_superio("ALi", reg_table, port, id);
+	dump_superio("ALi", reg_table, port, id, LDN_SEL);
 
 	exit_conf_mode_ali(port);
 }

Modified: trunk/util/superiotool/fintek.c
===================================================================
--- trunk/util/superiotool/fintek.c	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/fintek.c	2008-12-01 14:18:57 UTC (rev 3784)
@@ -137,7 +137,7 @@
 	       get_superio_name(reg_table, did), vid, did, port);
 	chip_found = 1;
 
-	dump_superio("Fintek", reg_table, port, did);
+	dump_superio("Fintek", reg_table, port, did, LDN_SEL);
 
 	exit_conf_mode_winbond_fintek_ite_8787(port);
 }

Modified: trunk/util/superiotool/ite.c
===================================================================
--- trunk/util/superiotool/ite.c	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/ite.c	2008-12-01 14:18:57 UTC (rev 3784)
@@ -534,10 +534,10 @@
 	       get_superio_name(reg_table, id), id, chipver, port);
 	chip_found = 1;
 
-	dump_superio("ITE", reg_table, port, id);
+	dump_superio("ITE", reg_table, port, id, LDN_SEL);
 
 	if (extra_dump) {
-		regwrite(port, 0x07, 0x04); /* Select LDN 4 (EC). */
+		regwrite(port, LDN_SEL, 0x04); /* Select LDN 4 (EC). */
 
 		/* Get EC base address (stored in LDN 4, index 0x60/0x61). */
 		ecport = regval(port, 0x60) << 8;
@@ -547,7 +547,7 @@
 		ecport += 5;
 
 		printf("Environment controller (0x%04x)\n", ecport);
-		dump_superio("ITE-EC", ec_table, ecport, id);
+		dump_superio("ITE-EC", ec_table, ecport, id, LDN_SEL);
 	}
 }
 
@@ -583,5 +583,5 @@
 void print_ite_chips(void)
 {
 	print_vendor_chips("ITE", reg_table);
-	print_vendor_chips("ITE EC", ec_table);
+	print_vendor_chips("ITE-EC", ec_table);
 }

Modified: trunk/util/superiotool/nsc.c
===================================================================
--- trunk/util/superiotool/nsc.c	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/nsc.c	2008-12-01 14:18:57 UTC (rev 3784)
@@ -506,7 +506,7 @@
 	       get_superio_name(reg_table, id), id, rev, port);
 	chip_found = 1;
 
-	dump_superio("NSC", reg_table, port, id);
+	dump_superio("NSC", reg_table, port, id, LDN_SEL);
 }
 
 void print_nsc_chips(void)

Modified: trunk/util/superiotool/smsc.c
===================================================================
--- trunk/util/superiotool/smsc.c	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/smsc.c	2008-12-01 14:18:57 UTC (rev 3784)
@@ -643,7 +643,8 @@
 	       id, rev, port);
 	chip_found = 1;
 
-	dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id);
+	dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id,
+		     LDN_SEL);
 
 	exit_conf_mode_smsc(port);
 }

Modified: trunk/util/superiotool/superiotool.c
===================================================================
--- trunk/util/superiotool/superiotool.c	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/superiotool.c	2008-12-01 14:18:57 UTC (rev 3784)
@@ -82,7 +82,7 @@
 }
 
 static void dump_regs(const struct superio_registers reg_table[],
-		      int i, int j, uint16_t port)
+		      int i, int j, uint16_t port, uint8_t ldn_sel)
 {
 	int k;
 	const int16_t *idx;
@@ -91,7 +91,7 @@
 		printf("LDN 0x%02x", reg_table[i].ldn[j].ldn);
 		if (reg_table[i].ldn[j].name != NULL)
 			printf(" (%s)", reg_table[i].ldn[j].name);
-		regwrite(port, 0x07, reg_table[i].ldn[j].ldn);
+		regwrite(port, ldn_sel, reg_table[i].ldn[j].ldn);
 	} else {
 		printf("Register dump:");
 	}
@@ -131,7 +131,7 @@
 
 void dump_superio(const char *vendor,
 		  const struct superio_registers reg_table[],
-		  uint16_t port, uint16_t id)
+		  uint16_t port, uint16_t id, uint8_t ldn_sel)
 {
 	int i, j, no_dump_available = 1;
 
@@ -149,7 +149,7 @@
 			if (reg_table[i].ldn[j].ldn == EOT)
 				break;
 			no_dump_available = 0;
-			dump_regs(reg_table, i, j, port);
+			dump_regs(reg_table, i, j, port, ldn_sel);
 		}
 
 		if (no_dump_available)

Modified: trunk/util/superiotool/superiotool.h
===================================================================
--- trunk/util/superiotool/superiotool.h	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/superiotool.h	2008-12-01 14:18:57 UTC (rev 3784)
@@ -73,10 +73,14 @@
 #define MISC		-5		/* Needs special comment in output */
 #define MAXLDN		0x14		/* Biggest LDN */
 #define LDNSIZE		(MAXLDN + 3)	/* Biggest LDN + 0 + NOLDN + EOT */
-#define MAXNUMIDX	170		/* Maximum number of indexes */
+#define MAXNUMIDX	170		/* Maximum number of indices */
 #define IDXSIZE 	(MAXNUMIDX + 1)
 #define MAXNUMPORTS	(6 + 1)		/* Maximum number of Super I/O ports */
 
+/* Select registers for various components. */
+#define LDN_SEL		0x07		/* LDN select register */
+#define WINBOND_HWM_SEL	0x4e		/* Hardware monitor bank select */
+
 /* Command line parameters. */
 extern int dump, verbose, extra_dump;
 
@@ -102,7 +106,7 @@
 const char *get_superio_name(const struct superio_registers reg_table[],
 			     uint16_t id);
 void dump_superio(const char *name, const struct superio_registers reg_table[],
-		  uint16_t port, uint16_t id);
+		  uint16_t port, uint16_t id, uint8_t ldn_sel);
 void probing_for(const char *vendor, const char *info, uint16_t port);
 void print_vendor_chips(const char *vendor,
 			const struct superio_registers reg_table[]);

Modified: trunk/util/superiotool/winbond.c
===================================================================
--- trunk/util/superiotool/winbond.c	2008-11-30 14:52:46 UTC (rev 3783)
+++ trunk/util/superiotool/winbond.c	2008-12-01 14:18:57 UTC (rev 3784)
@@ -468,6 +468,55 @@
 	{EOT}
 };
 
+static const struct superio_registers hwm_table[] = {
+	{0x828, "W83627THF/THG", {
+		{NOLDN, NULL,
+			{0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,
+			 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,
+			 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,
+			 0x1e,0x1f,
+			 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
+			 0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34,
+			 0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,
+			 0x3f,
+			 0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,
+			 0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT},
+			{RSVD,0xff,RSVD,0xff,0x00,0x00,0x00,0x00,0x01,0x01,
+			 0x01,0x01,0x3c,0x3c,0x0a,0x0a,RSVD,0xff,0x00,0x00,
+			 0x00,0x01,0x01,0x3c,0x43,RSVD,0xff,0xff,RSVD,RSVD,
+			 NANA,NANA,
+			 NANA,NANA,NANA,NANA,NANA,RSVD,RSVD,NANA,NANA,NANA,
+			 NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+			 RSVD,RSVD,RSVD,RSVD,NANA,NANA,NANA,NANA,NANA,RSVD,
+			 RSVD,
+			 0x03,0x00,0x00,0xfe,0xff,RSVD,RSVD,0x5f,NANA,0x03,
+			 RSVD,0x44,0x18,0x15,0x80,0x5c,EOT}},
+		{0x0, "Bank 0",
+			{0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,
+			 0x5d,0x5e,0x5f,EOT},
+			{NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x80,0x90,0x70,
+			 0x00,RSVD,RSVD,EOT}},
+		{0x1, "Bank 1",
+			{0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT},
+			{NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}},
+		{0x2, "Bank 2",
+			{0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT},
+			{NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}},
+		{0x4, "Bank 4",
+			{0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x59,0x5a,
+			 0x5b,EOT},
+			{0x00,0xff,RSVD,0x00,0x00,0x00,0x00,0x00,0x00,
+			 0x00,EOT}},
+		{0x5, "Bank 5",
+			{0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT},
+			{NANA,NANA,RSVD,RSVD,NANA,NANA,NANA,NANA,EOT}},
+		{0x6, "Bank 6",
+			{0x50,EOT},
+			{RSVD,EOT}},
+		{EOT}}},
+	{EOT}
+};
+
 static void enter_conf_mode_winbond_88(uint16_t port)
 {
 	OUTB(0x88, port);
@@ -486,7 +535,7 @@
 
 static void probe_idregs_winbond_helper(const char *init, uint16_t port)
 {
-	uint16_t id;
+	uint16_t id, hwmport;
 	uint8_t devid, rev, olddevid;
 
 	probing_for("Winbond", init, port);
@@ -522,7 +571,27 @@
 		       get_superio_name(reg_table, id), devid, rev, port);
 	chip_found = 1;
 
-	dump_superio("Winbond", reg_table, port, id);
+	dump_superio("Winbond", reg_table, port, id, LDN_SEL);
+
+	if (extra_dump) {
+		regwrite(port, LDN_SEL, 0x0b); /* Select LDN 0xb (HWM). */
+
+		if ((regval(port, 0x30) & (1 << 0)) != (1 << 0)) {
+			printf("Hardware Monitor disabled or does not exist.\n");
+			return;
+		}
+
+		/* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
+		hwmport = regval(port, 0x60) << 8;
+		hwmport |= regval(port, 0x61);
+
+		/* HWM address register = HWM base address + 5. */
+		hwmport += 5;
+
+		printf("Hardware monitor (0x%04x)\n", hwmport);
+		dump_superio("Winbond-HWM", hwm_table, hwmport, id,
+			     WINBOND_HWM_SEL);
+	}
 }
 
 void probe_idregs_winbond(uint16_t port)
@@ -547,4 +616,5 @@
 void print_winbond_chips(void)
 {
 	print_vendor_chips("Winbond", reg_table);
+	print_vendor_chips("Winbond-HWM", hwm_table);
 }




From uwe at hermann-uwe.de  Mon Dec  1 15:28:22 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 1 Dec 2008 15:28:22 +0100
Subject: [coreboot] [PATCH] superiotool: dump winbond hardware
	monitor	registers
In-Reply-To: <493078F1.7020402@coresystems.de>
References: <493078F1.7020402@coresystems.de>
Message-ID: <20081201142822.GA18231@greenwood>

On Sat, Nov 29, 2008 at 12:04:17AM +0100, Stefan Reinauer wrote:
> * Not all LDNs are switched via register offset 0x07, make it a parameter
> * add support for dumping the hardware monitor of Winbond W83627THF/THG 
>   parts with -e
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Nice, thanks! Acked, and committed in r3784 with a few minor changes:

 - Added more RSVD entries (for all registers which are explicitly
   mentioned to be reserved in the datasheet). This includes one
   register in bank 6 (this bank was not in the original patch).

 - Use LDN_SEL in one or two more places, now that we have a #define.

 - Add
     print_vendor_chips("Winbond-HWM", hwm_table);
   to the print_winbond_chips() function to make the new dump appear
   in 'superiotool -l' output.


> +static const struct superio_registers hwm_table[] = {
> +	{0x828, "W83627THF/THG", {
> +		{NOLDN, NULL,
> +			{0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,
> +			 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,
> +			 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,
> +			 0x1e,0x1f,
> +			 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
> +			 0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34,
> +			 0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,
> +			 0x3f,
> +			 0x40,0x41,0x42,0x43,0x44,0x47,0x48,0x49,0x4a,0x4b,
> +			 0x4c,0x4d,0x4e,0x4f,EOT},
> +			{RSVD,0xff,RSVD,0xff,0x00,0x00,0x00,0x00,0x01,0x01,
> +			 0x01,0x01,0x3c,0x3c,0x0a,0x0a,RSVD,0xff,0x00,0x00,
> +			 0x00,0x01,0x01,0x3c,0x43,RSVD,0xff,0xff,RSVD,RSVD,
> +			 NANA,NANA,
> +			 NANA,NANA,NANA,NANA,NANA,RSVD,RSVD,NANA,NANA,NANA,
> +			 NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
> +			 RSVD,RSVD,RSVD,RSVD,NANA,NANA,NANA,NANA,NANA,RSVD,
> +			 RSVD,
> +			 0x03,0x00,0x00,0xfe,0xff,0x5f,NANA,0x03,RSVD,0x44,
> +			 0x18,0x15,0x80,0x5c,EOT}},

Can you post a sample dump of this Super I/O with '-e'? The 0x4f
register here is a bit unclear, the datasheet (page 48) says that it's
16 bit. Seems like the default is 0x5c or 0xa3, depending on 0x4e bit 7?
Maybe we should make the value of 0x4e 'MISC' instead, as 0x5c is not
always correct.


> +	if (extra_dump) {
> +		regwrite(port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
                               ^^^^
                         changed to LDN_SEL


> +		      int i, int j, uint16_t port, uint8_t bank_sel)

Changed bank_sel to ldn_sel, as that's the more common name/use for it
(but both is correct, of course).


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From stepan at coresystems.de  Mon Dec  1 16:12:45 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 01 Dec 2008 16:12:45 +0100
Subject: [coreboot] [PATCH] superiotool: dump winbond hardware monitor
 registers
In-Reply-To: <20081201142822.GA18231@greenwood>
References: <493078F1.7020402@coresystems.de>
	<20081201142822.GA18231@greenwood>
Message-ID: <4933FEED.1080007@coresystems.de>

Uwe Hermann wrote:
> On Sat, Nov 29, 2008 at 12:04:17AM +0100, Stefan Reinauer wrote:
>   
>> * Not all LDNs are switched via register offset 0x07, make it a parameter
>> * add support for dumping the hardware monitor of Winbond W83627THF/THG 
>>   parts with -e
>>
>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>     
>
> Nice, thanks! Acked, and committed in r3784 with a few minor changes:
cool thanks.
> Can you post a sample dump of this Super I/O with '-e'? The 0x4f
> register here is a bit unclear, the datasheet (page 48) says that it's
> 16 bit. Seems like the default is 0x5c or 0xa3, depending on 0x4e bit 7?
> Maybe we should make the value of 0x4e 'MISC' instead, as 0x5c is not
> always correct.
>   
The value of 0x4f depends on the upper bit of the bank select register.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From marcj303 at gmail.com  Mon Dec  1 18:19:04 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 1 Dec 2008 10:19:04 -0700
Subject: [coreboot] [PATCH] Athlon64 K8 fixes
In-Reply-To: <13426df10811241948p5819e6f8ofba85c6e936d2a4f@mail.gmail.com>
References: <20081119230135.GA27038@thorin>
	<13426df10811191532o5f5652bfiad57778de393950@mail.gmail.com>
	<20081120132801.GA14733@thorin>
	<13426df10811241948p5819e6f8ofba85c6e936d2a4f@mail.gmail.com>
Message-ID: <534e5dc20812010919g7d05280wa942b6f7b0e90941@mail.gmail.com>

On Mon, Nov 24, 2008 at 8:48 PM, ron minnich <rminnich at gmail.com> wrote:
> On Thu, Nov 20, 2008 at 5:28 AM, Robert Millan <rmh at aybabtu.com> wrote:
>
>> Okay.  Bit 29 is the easiest, as the spec reads "This bit should be set
>> if the 939 package is used."  This is enough for a single-DIMM setup to
>> work.
>
> I like this patch. I'd like to see marc ack it but:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

I am a little hesitant to change this. Bit 28 and 29 were already
being set for all rev a-e processors. This will affect socket 754 and
940 platforms (which I assume are working) so we would need some
additional test coverage. I think that you will need to implement all
the settings in the bkdg section 4.1.3 Maximum DRAM Speed as a
Function of Loading for 2T settings.

I think that adding CPU_SOCKET_TYPE for the 754, 939 and 940 would be
a good. Maybe number them 0x07, 0x08, and 0x09. Update the
src\config\Options.lb to document the socket  numbers.

Marc

--



From dupontyv at gmail.com  Mon Dec  1 19:03:03 2008
From: dupontyv at gmail.com (Dupont Yves)
Date: Mon, 1 Dec 2008 19:03:03 +0100
Subject: [coreboot] Spi flash
In-Reply-To: <491C7573.9080806@gmx.net>
References: <6ad6bfe40811130011pfd4a11bxfa548bb4a879a420@mail.gmail.com>
	<491C36CE.80206@gmx.net>
	<6ad6bfe40811130951g13e051dfud3b330667c43d5e9@mail.gmail.com>
	<491C7573.9080806@gmx.net>
Message-ID: <6ad6bfe40812011003w5af1bb7asa637f8cb5ac7211b@mail.gmail.com>

2008/11/13 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>:
> Hi Yves,
>
> please keep the list in CC so they know what's going on. Thanks.
>
> On 13.11.2008 18:51, Dupont Yves wrote:
>> here is the corresponding dump :
>>
>> Calibrating delay loop... 326M loops per second, 100 myus = 193 us. OK.
>> No coreboot table found.
>> Found chipset "Intel ICH7M", enabling flash write...
>> BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
>>
>> Root Complex Register Block address = 0xfed1c000
>> GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
>> [...]
>> SPI Read Configuration: prefetching disabled, caching enabled, OK.
>> [...]
>> Probing for Atmel AT25DF321, 4096 KB: Programming OPCODES... done
>> RDID returned ff ff ff.
>>
>
> The flash chip doesn't support RDID.
>
>> RDID byte 0 parity violation.
>> probe_spi_rdid_generic: id1 0xff, id2 0xffff
>> [...]
>> Probing for ST M25P40-old, 512 KB: RDID returned ff ff ff.
>> RES returned 13.
>>
>
> But the chip supports RES.
>
>> probe_spi_res: id 0x13
>> [....]
>> No EEPROM/flash device found.
>>
>
> The big problem is that ~30 chips from different manufacturers with
> different sizes all have the same RES ID. I will try to cook up a patch
> checking REMS (which is more accurate).
>
>> It seems to bea SPI flash device but I don't want to open my laptop.
>> Any idea?
>>
>
> I will create a patch to improve detection, but that may take a week or
> so. If you don't hear anything back from me in the next 7 days, please
> ask me for a status.
>
>
> Regards,
> Carl-Daniel
>
> --
> http://www.hailfinger.org/
>

Hi Carl-Daniel,

I still have troubles with the detection of my SPI flash.
Here is the result of the dump:

Calibrating delay loop... 227M loops per second, 100 myus = 135 us. OK.
No coreboot table found.
Found chipset "Intel ICH7M", enabling flash write...
BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1

Root Complex Register Block address = 0xfed1c000
GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
Top Swap : not enabled
SPIBAR = 0xfed1c000 + 0x3020
0x00: 0x0004     (SPIS)
0x02: 0x4260     (SPIC)
0x04: 0x00000000 (SPIA)
0x08: 0xffffffff (SPID0)
0x0c: 0x00000000 (SPID0+4)
0x10: 0x00000000 (SPID1)
0x14: 0x00000000 (SPID1+4)
0x18: 0x00000000 (SPID2)
0x1c: 0x00000000 (SPID2+4)
0x20: 0x00000000 (SPID3)
0x24: 0x00000000 (SPID3+4)
0x28: 0x00000000 (SPID4)
0x2c: 0x00000000 (SPID4+4)
0x30: 0x00000000 (SPID5)
0x34: 0x00000000 (SPID5+4)
0x38: 0x00000000 (SPID6)
0x3c: 0x00000000 (SPID6+4)
0x40: 0x00000000 (SPID7)
0x44: 0x4a000000 (SPID7+4)
0x50: 0x00000000 (BBAR)
0x54: 0x0006     (PREOP)
0x56: 0x463b     (OPTYPE)
0x58: 0x05d80302 (OPMENU)
0x5c: 0xc79f01ab (OPMENU+4)
0x60: 0x00000000 (PBR0)
0x64: 0x00000000 (PBR1)
0x68: 0x00000000 (PBR2)
0x6c: 0x00000000 (PBR3)

SPI Read Configuration: prefetching disabled, caching enabled, OK.
Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41
Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Atmel AT25DF021, 256 KB: Programming OPCODES... done
RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF041A, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF081, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF161, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF321, 4096 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF321A, 4096 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25DF641, 8192 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25F512B, 64 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25FS010, 128 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT25FS040, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF041, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF081A, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF161, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26DF161A, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT26F004, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for Atmel AT45CS1282, 16896 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB011D, 128 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB021D, 256 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB041D, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB081D, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB161D, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB321C, 4224 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB321D, 4096 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT45DB642D, 8192 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for AMIC A25L40P, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0x46, id2 0xfc
Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0x46, id2 0xfc
Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41
Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0x4e, id2
0x41, id1 parity violation
Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0x4e, id2
0x41, id1 parity violation
Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for Macronix MX25L512, 64 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L1005, 128 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L2005, 256 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L4005, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L8005, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L1605, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L3205, 4096 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX25L6405, 8192 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0x46, id2 0xfc
Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0x46, id2 0xfc
Probing for Numonyx M25PE10, 128 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE20, 256 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE40, 256 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE80, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Numonyx M25PE16, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV010, 128 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV016B, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV020, 256 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV040, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV080B, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm25LV512, 64 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff
Probing for Spansion S25FL016A, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF016B, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF032B, 4096 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF040B, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST25VF080B, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x4e, id2 0x41
Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x0, id2 0x0, id1
parity violation
Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x7e, id2
0x37, id1 parity violation
Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x4e, id2
0x41, id1 parity violation
Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x4e, id2 0x41
Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for ST M25P05-A, 64 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P10-A, 128 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P20, 256 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P40, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P40-old, 512 KB: RDID returned ff ff ff.
RES returned 13.
probe_spi_res: id 0x13
Probing for ST M25P80, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P16, 2048 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P32, 4096 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P64, 8192 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M25P128, 16384 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x4e, id2 0x41
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50
Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1
parity violation
Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x4e, id2 0x41, id1
parity violation
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x4e, id2 0x41
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x4e, id2 0x41
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x46, id2 0xfc
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x4e, id2 0x41
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x4e, id2
0x41, id1 parity violation
Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xff, id2
0xff, id1 parity violation
Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x4e, id2
0x41, id1 parity violation
Probing for Winbond W25x10, 128 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25x20, 256 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25x40, 512 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W25x80, 1024 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xff, id2 0xff,
id1 parity violation
Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for Winbond W29EE011, 128 KB:
===
  Probing disabled for Winbond W29EE011 because the probing sequence puts the
  AMIC A49LF040A in a funky state.
  Use 'flashrom -c W29EE011' if you have a board with this chip.
===
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x4e, id2 0x41,
id1 parity violation
Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x4e, id2
0x41, id1 parity violation
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x4e, id2
0x41, id1 parity violation
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2
0xff, id1 parity violation
Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x46, id2 0xfc
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff
Probing for Winbond W39V080FA (dual mode), 512 KB:
probe_winbond_fwhub: vid 0x4e, did 0x41
Probing for Atmel unknown Atmel SPI chip, 0 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for EON unknown EON SPI chip, 0 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for Macronix unknown Macronix SPI chip, 0 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for PMC unknown PMC SPI chip, 0 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for SST unknown SST SPI chip, 0 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
Probing for ST unknown ST SPI chip, 0 KB: RDID returned ff ff ff.
RDID byte 0 parity violation.
probe_spi_rdid_generic: id1 0xff, id2 0xffff
No EEPROM/flash device found.
If you know which flash chip you have, and if this version of flashrom
supports a similar flash chip, you can try to force read your chip. Run:
flashrom -f -r -c similar_supported_flash_chip filename

Note: flashrom can never write when the flash chip isn't found automatically.

I don't known if you have enough time to create your patch.
Thanks for your help.
Regards,

Yves



From svn at coreboot.org  Mon Dec  1 20:37:22 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Dec 2008 20:37:22 +0100
Subject: [coreboot] r3785 - trunk/coreboot-v2/src/southbridge/amd/sb600
Message-ID: <mailman.2529.1355071446.16123.coreboot@coreboot.org>

Author: mjones
Date: 2008-12-01 20:37:21 +0100 (Mon, 01 Dec 2008)
New Revision: 3785

Modified:
   trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h
Log:
Add AMD sb600 HPET setup and some minor cleanups.

Signed-off-by:  Joe Bao <zheng.bao at amd.com>
Reviewed-by:    Maggie Li <maggie.li at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/chip.h	2008-12-01 19:37:21 UTC (rev 3785)
@@ -20,11 +20,11 @@
 #ifndef SB600_CHIP_H
 #define SB600_CHIP_H
 
-struct southbridge_amd_sb600_config 
+struct southbridge_amd_sb600_config
 {
-	unsigned int ide0_enable : 1;
-	unsigned int sata0_enable : 1;
-	unsigned long hda_viddid;
+	u32 ide0_enable : 1;
+	u32 sata0_enable : 1;
+	u32 hda_viddid;
 };
 struct chip_operations;
 extern struct chip_operations southbridge_amd_sb600_ops;

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -24,6 +24,7 @@
 #define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */
 
+
 static void pmio_write(u8 reg, u8 value)
 {
 	outb(reg, PM_INDEX);
@@ -44,6 +45,7 @@
 
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\r\n");
+		/* NOT REACHED */
 	}
 	return pci_read_config8(dev, 0x08);
 }
@@ -259,6 +261,7 @@
 
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\r\n");
+		/* NOT REACHED */
 	}
 	printk_info("SMBus controller enabled, sb revision is 0x%x\r\n",
 		    get_sb600_revision());
@@ -317,7 +320,7 @@
 	pci_write_config8(dev, 0x62, byte);
 
 	/* Features Enable */
-	pci_write_config32(dev, 0x64, 0x829E79BF);
+	pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
 
 	/* SerialIrq Control */
 	pci_write_config8(dev, 0x69, 0x90);
@@ -373,7 +376,7 @@
 	byte |= ((1 << 1) + (1 << 6));	/*0x42, save the configuraion for port 0x80. */
 	pci_write_config8(dev, 0x4A, byte);
 
-	/* Set LPC ROM size, it has been done in sb600_lpc_init(). 
+	/* Set LPC ROM size, it has been done in sb600_lpc_init().
 	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
 	 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
 	 * pci_write_config16(dev, 0x68, 0x000e)
@@ -382,7 +385,7 @@
 	/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
 	pci_write_config8(dev, 0x7C, 0x05);
 
-	/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, 
+	/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
 	 * TODO: I don't know what are their mean? */
 	printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
@@ -397,7 +400,7 @@
 
 	pci_write_config8(dev, 0x40, 0x26);
 
-	/* I don't know why CIM set reg0x1c as 0x11. 
+	/* I don't know why CIM set reg0x1c as 0x11.
 	 * System will block at sdram_initialize() if I set it before call sdram_initialize().
 	 * If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
 	 * pci_write_config8(dev, 0x1c, 0x11);
@@ -490,8 +493,10 @@
 	pmio_write(0x9e, byte);
 
 	/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
+	/* We have to clear this bit here, otherwise the kernel hangs. */
 	byte = pmio_read(0x55);
 	byte |= 1 << 7;
+	byte |= 1 << 1;
 	pmio_write(0x55, byte);
 
 	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
@@ -550,7 +555,7 @@
 	byte |= (1 << 3);
 	pci_write_config8(dev, 0x41, byte);
 
-	/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) 
+	/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
 	 * generated PCIRST#. */
 	byte = pmio_read(0x65);
 	byte |= (1 << 4);

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -55,7 +55,7 @@
 	return 0;
 }
 
-static int codec_detect(u8 * base)
+static u32 codec_detect(u8 * base)
 {
 	u32 dword;
 
@@ -148,7 +148,7 @@
 	0x01f71ec4,
 	0x01f71f01,
 };
-static unsigned find_verb(u32 viddid, u32 ** verb)
+static u32 find_verb(u32 viddid, u32 ** verb)
 {
 	device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
 	struct southbridge_amd_sb600_config *cfg =

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_ide.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -38,13 +38,10 @@
 	pci_write_config32(dev, 0x70, dword);
 
 	/* Ultra DMA mode */
+	/* enable UDMA */
 	byte = pci_read_config8(dev, 0x54);
 	byte |= 1 << 0;
 	pci_write_config8(dev, 0x54, byte);
-	byte = pci_read_config8(dev, 0x56);
-	byte &= ~(7 << 0);
-	byte |= 5 << 0;		/* mode 5 */
-	pci_write_config8(dev, 0x56, byte);
 
 	/* Enable I/O Access&& Bus Master */
 	dword = pci_read_config16(dev, 0x4);

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -82,14 +82,14 @@
 	compact_resources(dev);
 }
 
-/**     
+/**
  * @brief Enable resources for children devices
- *      
+ *
  * @param dev the device whos children's resources are to be enabled
- *      
+ *
  * This function is call by the global enable_resources() indirectly via the
  * device_operation::enable_resources() method of devices.
- *      
+ *
  * Indirect mutual recursion:
  *      enable_childrens_resources() -> enable_resources()
  *      enable_resources() -> device_operation::enable_resources()
@@ -115,7 +115,7 @@
 			    && (child->path.type == DEVICE_PATH_PNP)) {
 				for (i = 0; i < child->resources; i++) {
 					struct resource *res;
-					unsigned long base, end;	/*  don't need long long */
+					u32 base, end;	/*  don't need long long */
 					res = &child->resource[i];
 					if (!(res->flags & IORESOURCE_IO))
 						continue;

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -24,7 +24,7 @@
 	(((DEV) & 0x1F) << 15) | \
 	(((FN)  & 0x7) << 12))
 
-typedef unsigned device_t;
+typedef u32 device_t;
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -62,12 +62,12 @@
 	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7;
 	sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7;
 
-	printk_debug("sata_bar0=%x\n", sata_bar0);	/* 3030 */
-	printk_debug("sata_bar1=%x\n", sata_bar1);	/* 3070 */
-	printk_debug("sata_bar2=%x\n", sata_bar2);	/* 3040 */
-	printk_debug("sata_bar3=%x\n", sata_bar3);	/* 3080 */
-	printk_debug("sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk_debug("sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+	/* printk_debug("sata_bar0=%x\n", sata_bar0); */	/* 3030 */
+	/* printk_debug("sata_bar1=%x\n", sata_bar1); */	/* 3070 */
+	/* printk_debug("sata_bar2=%x\n", sata_bar2); */	/* 3040 */
+	/* printk_debug("sata_bar3=%x\n", sata_bar3); */	/* 3080 */
+	/* printk_debug("sata_bar4=%x\n", sata_bar4); */	/* 3000 */
+	/* printk_debug("sata_bar5=%x\n", sata_bar5); */	/* e0309000 */
 
 	/* Program the 2C to 0x43801002 */
 	dword = 0x43801002;
@@ -142,15 +142,15 @@
 	/* Use BAR5+0x2A8,BAR0+0x6 for Secondary Slave */
 
 	byte = readb(sata_bar5 + 0x128);
-	printk_debug("byte=%x\n", byte);
+	/* printk_debug("byte=%x\n", byte); */
 	byte &= 0xF;
 	if (byte == 0x3) {
 		outb(0xA0, sata_bar0 + 0x6);
 		while ((inb(sata_bar0 + 0x6) != 0xA0)
 		       || ((inb(sata_bar0 + 0x7) & 0x88) != 0)) {
 			mdelay(10);
-			printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
-				     inb(sata_bar0 + 0x7));
+			/* printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
+			   inb(sata_bar0 + 0x7)); */
 			printk_debug("drive detection fail,trying...\n");
 		}
 		printk_debug("Primary master device is ready\n");

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -41,8 +41,8 @@
 #endif
 
 struct ioapicreg {
-	unsigned int reg;
-	unsigned int value_low, value_high;
+	u32 reg;
+	u32 value_low, value_high;
 };
 
 static struct ioapicreg ioapicregvalues[] = {
@@ -89,18 +89,18 @@
 	/* Be careful and don't write past the end... */
 };
 
-static void setup_ioapic(unsigned long ioapic_base)
+static void setup_ioapic(u32 ioapic_base)
 {
 	int i;
-	unsigned long value_low, value_high;
-	volatile unsigned long *l;
+	u32 value_low, value_high;
+	volatile u32 *l;
 	struct ioapicreg *a = ioapicregvalues;
 
 	ioapicregvalues[0].value_high = lapicid() << (56 - 32);
 
 	printk_debug("lapicid = %016x\n", ioapicregvalues[0].value_high);
 
-	l = (unsigned long *)ioapic_base;
+	l = (u32 *)ioapic_base;
 
 	for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 	     i++, a++) {
@@ -126,9 +126,9 @@
 	u8 byte;
 	u8 byte_old;
 	u32 dword;
-	unsigned long ioapic_base;
-	int on;
-	int nmi_option;
+	u32 ioapic_base;
+	u32 on;
+	u32 nmi_option;
 
 	printk_info("sm_init().\n");
 
@@ -143,6 +143,10 @@
 	dword |= 1 << 9;
 	pci_write_config32(dev, 0x78, dword);	/* enable 0xCD6 0xCD7 */
 
+	/* bit 10: MultiMediaTimerIrqEn */
+	dword = pci_read_config8(dev, 0x64);
+	dword |= 1 << 10;
+	pci_write_config8(dev, 0x64, dword);
 	/* enable serial irq */
 	byte = pci_read_config8(dev, 0x69);
 	byte |= 1 << 7;		/* enable serial irq function */
@@ -191,8 +195,21 @@
 
 	byte = pm_ioread(0x68);
 	byte &= ~(1 << 1);
+	/* 2.6 */
+	byte |= 1 << 2;
 	pm_iowrite(0x68, byte);
 
+	/* 2.6 */
+	byte = pm_ioread(0x65);
+	byte &= ~(1 << 7);
+	pm_iowrite(0x65, byte);
+
+	/* 2.3.4 */
+	byte = pm_ioread(0x52);
+	byte &= ~0x2F;
+	byte |= 0x8;
+	pm_iowrite(0x52, byte);
+
 	byte = pm_ioread(0x8D);
 	byte &= ~(1 << 6);
 	pm_iowrite(0x8D, byte);
@@ -344,10 +361,20 @@
 static void sb600_sm_read_resources(device_t dev)
 {
 	struct resource *res;
+	u8 byte;
 
+	/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
+	byte = pm_ioread(0x55);
+	byte |= 1 << 7;
+	pm_iowrite(0x55, byte);
+
 	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);
+	/* pci_dev_read_resources(dev); */
 
+	byte = pm_ioread(0x55);
+	byte &= ~(1 << 7);
+	pm_iowrite(0x55, byte);
+
 	/* apic */
 	res = new_resource(dev, 0x74);
 	res->base  = 0xfec00000;
@@ -357,19 +384,49 @@
 	res->gran = 8;
 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 0x14); /* hpet */
+	res->base  = 0xfed00000;	/* reset hpet to widely accepted address */
+	res->size = 0x400;
+	res->limit = 0xFFFFFFFFUL;	/* res->base + res->size -1; */
+	res->align = 8;
+	res->gran = 8;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
 	/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
 
+	/* smbus */
+	res = new_resource(dev, 0x10);
+	res->base  = 0xB00;
+	res->size = 0x10;
+	res->limit = 0xFFFFUL;	/* res->base + res->size -1; */
+	res->align = 8;
+	res->gran = 8;
+	res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
+
+
 	compact_resources(dev);
 
 }
 static void sb600_sm_set_resources(struct device *dev)
 {
 	struct resource *res;
+	u8 byte;
 
 	pci_dev_set_resources(dev);
 
+
+	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
+	byte = pm_ioread(0x52);
+	byte |= 1 << 6;
+	pm_iowrite(0x52, byte);
+
 	res = find_resource(dev, 0x74);
 	pci_write_config32(dev, 0x74, res->base | 1 << 3);
+
+	res = find_resource(dev, 0x14);
+	pci_write_config32(dev, 0x14, res->base);
+
+	res = find_resource(dev, 0x10);
+	pci_write_config32(dev, 0x10, res->base | 1);
 }
 
 static struct pci_operations lops_pci = {

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.c	2008-12-01 19:37:21 UTC (rev 3785)
@@ -17,12 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-//#include <arch/io.h>
-//#include <device/device.h>
-//#include <device/pci.h>
-//#include <device/pci_ids.h>
-//#include <device/pci_ops.h>
-//#include <device/smbus_def.h>
 #include "sb600_smbus.h"
 
 static inline void smbus_delay(void)
@@ -32,7 +26,7 @@
 
 static int smbus_wait_until_ready(u32 smbus_io_base)
 {
-	unsigned long loops;
+	u32 loops;
 	loops = SMBUS_TIMEOUT;
 	do {
 		u8 val;
@@ -48,7 +42,7 @@
 
 static int smbus_wait_until_done(u32 smbus_io_base)
 {
-	unsigned long loops;
+	u32 loops;
 	loops = SMBUS_TIMEOUT;
 	do {
 		u8 val;
@@ -121,7 +115,7 @@
 	return 0;
 }
 
-static int do_smbus_read_byte(u32 smbus_io_base, u32 device,
+int do_smbus_read_byte(u32 smbus_io_base, u32 device,
 			      u32 address)
 {
 	u8 byte;
@@ -152,7 +146,7 @@
 	return byte;
 }
 
-static int do_smbus_write_byte(u32 smbus_io_base, u32 device,
+int do_smbus_write_byte(u32 smbus_io_base, u32 device,
 			       u32 address, u8 val)
 {
 	u8 byte;
@@ -183,10 +177,11 @@
 	return 0;
 }
 
-static void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr,
-			  unsigned int mask, unsigned int val)
+static void alink_ab_indx(u32 reg_space, u32 reg_addr,
+			  u32 mask, u32 val)
 {
-	unsigned int tmp;
+	u32 tmp;
+
 	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
 	tmp = inl(AB_DATA);
 
@@ -201,10 +196,10 @@
 /* space = 0: AX_INDXC, AX_DATAC
 *   space = 1: AX_INDXP, AX_DATAP
  */
-static void alink_ax_indx(unsigned int space /*c or p? */ , unsigned int axindc,
-			  unsigned int mask, unsigned int val)
+static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+			  u32 mask, u32 val)
 {
-	unsigned int tmp;
+	u32 tmp;
 
 	/* read axindc to tmp */
 	outl(space << 30 | space << 3 | 0x30, AB_INDX);
@@ -221,6 +216,3 @@
 	outl(space << 30 | space << 3 | 0x34, AB_INDX);
 	outl(tmp, AB_DATA);
 }
-
-
-

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h	2008-12-01 14:18:57 UTC (rev 3784)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_smbus.h	2008-12-01 19:37:21 UTC (rev 3785)
@@ -44,7 +44,7 @@
 #define AB_INDX   0xCD8
 #define AB_DATA   (AB_INDX+4)
 
-/* Between 1-10 seconds, We should never timeout normally 
+/* Between 1-10 seconds, We should never timeout normally
  * Longer than this is just painful when a timeout condition occurs.
  */
 #define SMBUS_TIMEOUT (100*1000*10)




From svn at coreboot.org  Mon Dec  1 20:49:57 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Dec 2008 20:49:57 +0100
Subject: [coreboot] r3786 - trunk/coreboot-v2/src/southbridge/amd/rs690
Message-ID: <mailman.2530.1355071446.16123.coreboot@coreboot.org>

Author: mjones
Date: 2008-12-01 20:49:57 +0100 (Mon, 01 Dec 2008)
New Revision: 3786

Modified:
   trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c
Log:
Add AMD rs690 VID DID reporting and some minor cleanups.

Signed-off-by:  Joe Bao <zheng.bao at amd.com>
Reviewed-by:    Maggie Li <maggie.li at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h	2008-12-01 19:37:21 UTC (rev 3785)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/chip.h	2008-12-01 19:49:57 UTC (rev 3786)
@@ -21,9 +21,9 @@
 #define RS690_CHIP_H
 
 /* Member variables are defined in Config.lb. */
-struct southbridge_amd_rs690_config 
+struct southbridge_amd_rs690_config
 {
-	unsigned long vga_rom_address;		/* The location that the VGA rom has been appened. */
+	u32 vga_rom_address;		/* The location that the VGA rom has been appened. */
 	u8 gpp_configuration;	/* The configuration of General Purpose Port, A/B/C/D/E. */
 	u8 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
 	u8 gfx_dev2_dev3;	/* for GFX Core initialization REFCLK_SEL */

Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c	2008-12-01 19:37:21 UTC (rev 3785)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c	2008-12-01 19:49:57 UTC (rev 3786)
@@ -29,26 +29,7 @@
 #include <cpu/amd/mtrr.h>
 #include "rs690.h"
 
-static device_t find_nb_dev(device_t dev, u32 devfn)
-{
-	device_t nb_dev;
 
-	nb_dev = dev_find_slot(dev->bus->secondary, devfn);
-
-	if (!nb_dev)
-		return nb_dev;
-
-	if ((nb_dev->vendor != PCI_VENDOR_ID_ATI)
-	    || (nb_dev->device != PCI_DEVICE_ID_ATI_RS690_HT)) {
-		u32 id;
-		id = pci_read_config32(nb_dev, PCI_VENDOR_ID);
-		if (id != (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_RS690_HT << 16))) {
-			nb_dev = 0;
-		}
-	}
-	return nb_dev;
-}
-
 /*****************************************
 * Compliant with CIM_33's ATINB_MiscClockCtrl
 *****************************************/
@@ -65,7 +46,7 @@
 
 	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
 	word &= 0xf00;
-	 pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+	pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
 
 	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
 	word &= ~((1 << 12) | (1 << 13) | (1 << 14));
@@ -123,6 +104,12 @@
 	set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
 }
 
+
+u32 get_vid_did(device_t dev)
+{
+	return pci_read_config32(dev, 0);
+}
+
 /***********************************************
 *	0:00.0  NBCFG	:
 *	0:00.1  CLK	: bit 0 of nb_cfg 0x4c : 0 - disable, default
@@ -140,39 +127,25 @@
 void rs690_enable(device_t dev)
 {
 	device_t nb_dev = 0, sb_dev = 0;
-	int index = -1;
-	u32 i;
-	u32 devfn;
-	u32 deviceid, vendorid;
+	int dev_ind;
 
-	vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
-	deviceid = (vendorid >> 16) & 0xffff;
-	vendorid &= 0xffff;
-	printk_info("rs690_enable VID=0x%x, DID=0x%x\n", vendorid, deviceid);
+	printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev));
 
-	/**********************************************************
-	* Work for bus0, internal GFX located on bus1 and will return after find_nb_dev.
-	**********************************************************/
-	i = (dev->path.u.pci.devfn) & ~7;
-	for (devfn = 0; devfn <= i; devfn += (1 << 3)) {
-		nb_dev = find_nb_dev(dev, devfn);
-		if (nb_dev)
-			break;
-	}
+	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
-		printk_info("CAN NOT FIND RS690 DEVICE!\n");
-		return;		/* nb_dev is not dev */
+		die("rs690_enable: CAN NOT FIND RS690 DEVICE, HALT!\n");
+		/* NOT REACHED */
 	}
 
 	/* sb_dev (dev 8) is a bridge that links to southbridge. */
 	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
 	if (!sb_dev) {
-		printk_info("rs690_enable CAN NOT FIND SB bridge, HALT!\n");
-		for (;;) ;
+		die("rs690_enable: CAN NOT FIND SB bridge, HALT!\n");
+		/* NOT REACHED */
 	}
 
-	printk_info("rs690_enable bus0, dev=0x%x\n", (dev->path.u.pci.devfn - devfn) >> 3);
-	switch (dev->path.u.pci.devfn - devfn) {
+	dev_ind = dev->path.u.pci.devfn >> 3;
+	switch (dev_ind) {
 	case 0:		/* bus0, dev0, fun0; */
 		printk_info("Bus-0, Dev-0, Fun-0.\n");
 		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
@@ -185,36 +158,34 @@
 		rs690_config_misc_clk(nb_dev);
 		break;
 
-	case 1 << 3:		/* bus0, dev1 */
+	case 1:		/* bus0, dev1 */
 		printk_info("Bus-0, Dev-1, Fun-0.\n");
 		break;
-	case 2 << 3:		/* bus0, dev2,3, two GFX */
-	case 3 << 3:
+	case 2:		/* bus0, dev2,3, two GFX */
+	case 3:
 		printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
-		index = (dev->path.u.pci.devfn - devfn) >> 3;
-		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
-				       (dev->enabled ? 0 : 1) << index);
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
+				       (dev->enabled ? 0 : 1) << dev_ind);
 		if (dev->enabled)
-			rs690_gfx_init(nb_dev, dev, index);
+			rs690_gfx_init(nb_dev, dev, dev_ind);
 		break;
-	case 4 << 3:		/* bus0, dev4-7, four GPP */
-	case 5 << 3:
-	case 6 << 3:
-	case 7 << 3:
+	case 4:		/* bus0, dev4-7, four GPP */
+	case 5:
+	case 6:
+	case 7:
 		printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
 			    dev->enabled);
-		index = (dev->path.u.pci.devfn - devfn) >> 3;
-		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
-				       (dev->enabled ? 0 : 1) << index);
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
+				       (dev->enabled ? 0 : 1) << dev_ind);
 		if (dev->enabled)
-			rs690_gpp_sb_init(nb_dev, dev, index);
+			rs690_gpp_sb_init(nb_dev, dev, dev_ind);
 		break;
-	case 8 << 3:		/* bus0, dev8, SB */
+	case 8:		/* bus0, dev8, SB */
 		printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
 				       (dev->enabled ? 1 : 0) << 6);
 		if (dev->enabled)
-			rs690_gpp_sb_init(nb_dev, dev, index);
+			rs690_gpp_sb_init(nb_dev, dev, dev_ind);
 		disable_pcie_bar3(nb_dev);
 		break;
 	default:

Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c	2008-12-01 19:37:21 UTC (rev 3785)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c	2008-12-01 19:49:57 UTC (rev 3786)
@@ -63,8 +63,8 @@
 
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c);
-	printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
-		     dev->path.u.pci.devfn);
+	/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.u.pci.devfn);*/
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.u.pci.devfn << 12 | reg_pos;
 

Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c	2008-12-01 19:37:21 UTC (rev 3785)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c	2008-12-01 19:49:57 UTC (rev 3786)
@@ -18,7 +18,6 @@
  */
 
 
- 
 #define NBHTIU_INDEX		0xA8
 #define NBMISC_INDEX		0x60
 #define NBMC_INDEX 		0xE8
@@ -185,7 +184,7 @@
 	* get k8's ht freq, in k8's function 0, offset 0x88
 	* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
 	* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
-	* value to this reg, and that value takes effect on the next warm reset or 
+	* value to this reg, and that value takes effect on the next warm reset or
 	* LDTSTOP_L disconnect sequence.
 	* 0000b = 200Mhz
 	* 0010b = 400Mhz
@@ -300,7 +299,7 @@
 	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
 	 * force this BAR as mem type in rs690_gfx.c */
 	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
-	
+
 }
 
 /*****************************************

Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c	2008-12-01 19:37:21 UTC (rev 3785)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c	2008-12-01 19:49:57 UTC (rev 3786)
@@ -72,7 +72,7 @@
 
 static void internal_gfx_pci_dev_init(struct device *dev)
 {
-	unsigned short deviceid, vendorid;
+	u16 deviceid, vendorid;
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)dev->chip_info;
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
@@ -109,11 +109,6 @@
 	clkind_write(dev, 0x5C, 0x0);
 }
 
-static void rs690_gfx_set_resources(struct device *dev)
-{
-	printk_info("rs690_gfx_set_resources.\n");
-	pci_dev_set_resources(dev);
-}
 
 /*
 * Set registers in RS690 and CPU to enable the internal GFX.
@@ -137,7 +132,7 @@
 
 	/* set TOM */
 	rs690_set_tom(nb_dev);
-	
+
 	/* LPC DMA Deadlock workaround? */
 	k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 	l_dword = pci_read_config32(k8_f0, 0x68);
@@ -206,9 +201,9 @@
 	.set_subsystem = pci_dev_set_subsystem,
 };
 
-static struct device_operations ht_ops = {
+static struct device_operations pcie_ops = {
 	.read_resources = rs690_gfx_read_resources,
-	.set_resources = rs690_gfx_set_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = internal_gfx_pci_dev_init,	/* The option ROM initializes the device. rs690_gfx_init, */
 	.scan_bus = 0,
@@ -216,8 +211,8 @@
 	.ops_pci = &lops_pci,
 };
 
-static struct pci_driver internal_gfx_driver __pci_driver = {
-	.ops = &ht_ops,
+static struct pci_driver pcie_driver __pci_driver = {
+	.ops = &pcie_ops,
 	.vendor = PCI_VENDOR_ID_ATI,
 	.device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX,
 };
@@ -350,7 +345,7 @@
 }
 
 
-/* For single port GFX configuration Only 
+/* For single port GFX configuration Only
 * width:
 * 	000 = x16
 * 	001 = x1
@@ -492,7 +487,7 @@
 	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
 	printk_info("rs690_gfx_init step8.3.\n");
 
-	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still 
+	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
 	 * time out and go back to Detect Idle.*/
 	set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14);
 	printk_info("rs690_gfx_init step8.4.\n");
@@ -510,7 +505,7 @@
 	set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30);
 	printk_info("rs690_gfx_init step8.8.\n");
 
-	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM. 
+	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
 	 * SLOT_IMPLEMENTED at PCIE_CAP */
 	reg16 = pci_read_config16(dev, 0x5a);
 	reg16 |= 0x100;
@@ -563,7 +558,7 @@
 
 	/* step 10.e: LCLK clock gating, done in rs690_config_misc_clk() */
 
-	/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.  
+	/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.
 	 * While details will be added later in the document, for now assue the single-port configuration. */
 	/* skip */
 

Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c	2008-12-01 19:37:21 UTC (rev 3785)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_ht.c	2008-12-01 19:49:57 UTC (rev 3786)
@@ -61,7 +61,7 @@
 	dword |= (1 << 30);	/* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
 
-	/* 
+	/*
 	 * 1 is APIC enable
 	 * 18 is enable nb to accept A4 interrupt request from SB.
 	 */

Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c	2008-12-01 19:37:21 UTC (rev 3785)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c	2008-12-01 19:49:57 UTC (rev 3786)
@@ -116,37 +116,6 @@
 	pci_write_config32(dev, 0x04, dword);
 }
 
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pcie_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pcie_init,
-	.scan_bus = pci_scan_bridge,
-	/*.enable           = rs690_enable, */
-	.ops_pci = &lops_pci,
-};
-
-static struct pci_driver pcie_driver __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE,
-};
-
-static struct pci_driver pcie_driver_dev7 __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7,
-};
-static struct pci_driver pcie_driver_dev8 __pci_driver = {
-	.ops = &pcie_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8,
-};
-
 /**********************************************************************
 **********************************************************************/
 static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)




From svn at coreboot.org  Mon Dec  1 20:52:54 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Dec 2008 20:52:54 +0100
Subject: [coreboot] r3787 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
Message-ID: <mailman.2531.1355071446.16123.coreboot@coreboot.org>

Author: mjones
Date: 2008-12-01 20:52:54 +0100 (Mon, 01 Dec 2008)
New Revision: 3787

Modified:
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
Log:
Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.


Signed-off-by:  Joe Bao <zheng.bao at amd.com>
Reviewed-by:    Maggie Li <maggie.li at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb	2008-12-01 19:52:54 UTC (rev 3787)
@@ -54,7 +54,7 @@
 default XIP_ROM_SIZE=65536
 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
 
-arch i386 end 
+arch i386 end
 
 ##
 ## Build the objects we have code for in this directory.
@@ -65,11 +65,22 @@
 #dir /drivers/si/3114
 
 if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE 
+if HAVE_PIRQ_TABLE
 	object get_bus_conf.o
-	object irq_tables.o 
+	object irq_tables.o
 end
 
+if HAVE_ACPI_TABLES
+	object acpi_tables.o
+	object fadt.o
+	makerule dsdt.c
+		depends "$(MAINBOARD)/acpi/*.asl"
+		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
+		action  "mv dsdt.hex dsdt.c"
+	end
+	object ./dsdt.o
+end
+
 #object reset.o
 
 if USE_DCACHE_RAM
@@ -78,14 +89,14 @@
 
 		makerule ./cache_as_ram_auto.o
 			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" 
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 		end
 
 	else
 
 		makerule ./cache_as_ram_auto.inc
 			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"         
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
@@ -112,7 +123,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -134,7 +145,7 @@
 end
 
 ###
-### This is the early phase of coreboot startup 
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -165,7 +176,7 @@
 end
 
 ##
-## Include the secondary Configuration files 
+## Include the secondary Configuration files
 ##
 if CONFIG_CHIP_NAME
 	config chip.h
@@ -177,7 +188,7 @@
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
 #Define vga_rom_address = 0xfff0000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, 
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 #					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
@@ -193,7 +204,7 @@
 	end
 	device pci_domain 0 on
 		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge 
+			device pci 18.0 on #  southbridge
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
@@ -221,13 +232,13 @@
 					register "gfx_link_width" = "0"
 				end
 				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-				device pci 12.0 on end # SATA  0x4380
-				device pci 13.0 on end # USB   0x4387
-				device pci 13.1 on end # USB   0x4388
-				device pci 13.2 on end # USB   0x4389
-				device pci 13.3 on end # USB   0x438a
-				device pci 13.4 on end # USB   0x438b
-				device pci 13.5 on end # USB 2 0x4386
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
 	 				device pci 14.0 on # SM        0x4385
 						chip drivers/generic/generic #dimm 0-0-0
 							device i2c 50 on end
@@ -242,49 +253,51 @@
 							device i2c 53 on end
 						end
 					end # SM
-				device pci 14.1 on end # IDE    0x438c
-				device pci 14.2 on end # HDA    0x4383
-				device pci 14.3 on # LPC	0x438d
-					chip superio/ite/it8712f
-						device pnp 2e.0 off #  Floppy
-							io 0x60 = 0x3f0
-							irq 0x70 = 6
-							drq 0x74 = 2
-						end
-						device pnp 2e.1 on #  Com1
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp 2e.2 off #  Com2
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp 2e.3 off #  Parallel Port
-							io 0x60 = 0x378
-							irq 0x70 = 7
-						end
-						device pnp 2e.4 off end #  EC
-						device pnp 2e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-						end
-						device pnp 2e.6 on #  Mouse
-							irq 0x70 = 12
-						end
-						device pnp 2e.8 off #  MIDI
-							io 0x60 = 0x300
-							irq 0x70 = 9
-						end
-						device pnp 2e.9 off #  GAME
-							io 0x60 = 0x220
-						end
-						device pnp 2e.a off end #  CIR
-					end	#superio/ite/it8712f
-				end		#LPC
-				device pci 14.4 on end # PCI 0x4384
-				device pci 14.5 on end # ACI 0x4382
-				device pci 14.6 on end # MCI 0x438e
+					device pci 14.1 on end # IDE    0x438c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x438d
+						chip superio/ite/it8712f
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.4 off end #  EC
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.6 on #  Mouse
+								irq 0x70 = 12
+							end
+							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
+							end
+							device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+							device pnp 2e.a off end #  CIR
+						end	#superio/ite/it8712f
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # ACI 0x4382
+					device pci 14.6 on end # MCI 0x438e
 					register "ide0_enable" = "1"
 					register "sata0_enable" = "1"
 					register "hda_viddid" = "0x10ec0882"

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2008-12-01 19:52:54 UTC (rev 3787)
@@ -130,6 +130,9 @@
 ##
 default HAVE_MP_TABLE=1
 
+## ACPI tables will be included
+default HAVE_ACPI_TABLES=1
+
 ##
 ## Build code to export a CMOS option table
 ##
@@ -232,7 +235,7 @@
 
 ###
 ### Defaults of options that you may want to override in the target config file
-### 
+###
 
 ##
 ## The default compiler
@@ -242,7 +245,7 @@
 
 ##
 ## Disable the gdb stub by default
-## 
+##
 default CONFIG_GDB_STUB=0
 
 
@@ -275,15 +278,15 @@
 ##
 ### Select the coreboot loglevel
 ##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
 
 ## Request this level of debugging output
 default  DEFAULT_CONSOLE_LOGLEVEL=8

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2008-12-01 19:52:54 UTC (rev 3787)
@@ -163,6 +163,7 @@
 	msr_t msr;
 	struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 
+
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	}
@@ -203,7 +204,7 @@
 	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 	init_fidvid_bsp(bsp_apicid);
 
-	// show final fid and vid
+	/* show final fid and vid */
 	msr=rdmsr(0xc0010042);
 	printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h	2008-12-01 19:52:54 UTC (rev 3787)
@@ -16,11 +16,11 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
-	 
+
 extern struct chip_operations mainboard_amd_dbm690t_ops;
 
-struct mainboard_amd_dbm690t_config 
+struct mainboard_amd_dbm690t_config
 {
-	unsigned long uma_size;			/* How many UMA should be used in memory for TOP. */
+	u32 uma_size;			/* How many UMA should be used in memory for TOP. */
 };
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c	2008-12-01 19:52:54 UTC (rev 3787)
@@ -1,96 +1,199 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-
-
-
-/**
- * Create the Fixed ACPI Description Tables (FADT) for this board.
- The FADT defines various fixed hardware ACPI information vital to an ACPI-compatible
- OS, such as the base address for the following hardware registers blocks:
- PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK,
- PM2_CNT_BLK, PM_TMR_BLK, GPE0_BLK and GPE1_BLK.
- The FADT also has a pointer to the DSDT that contains the Differentiated Definition Block,
- which in turn provides variable information to an ACPI-compatible OS concerning the base
- system design.
-
- Not all blocks are necessary usualy only PM1a, PMTMR and GPE0 are used.
- */
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
-	acpi_header_t *header=&(fadt->header);
-	
-	printk_debug("pm_base: 0x%04x\n", pm_base);
-	
-	memset((void *)fadt,0,sizeof(acpi_fadt_t));
-
-	/* Prepare the header */
-	memcpy(header->signature,"FACP",4);
-	header->length = 244;
-	header->revision = 1;
-	memcpy(header->oem_id,OEM_ID,6);
-	memcpy(header->oem_table_id,"LXBACPI ",8);
-	memcpy(header->asl_compiler_id,ASLC,4);
-	header->asl_compiler_revision=0;
-
-	
-	fadt->firmware_ctrl=(u32)facs;
-	fadt->dsdt= (u32)dsdt;
-
-	/*
-	0:	unspecified
-	1:	desktop
-	2:	mobile
-	3:	workstation
-	4:	enterprise server
-	*/
-	fadt->preferred_pm_profile=0x01;
-
-	/*
-	System vector the SCI interrupt is wired to in 8259 mode. 
-	On systems that do not contain the 8259, this field contains the Global
-	System interrupt number of the SCI interrupt. OSPM is required to treat
-	the ACPI SCI interrupt as a sharable, level, active low interrupt.
-	SB600 BDG 4.1
-	*/
-	fadt->sci_int=4;
-
-	/*
-	System port address of the SMI Command Port. During ACPI OS initialization,
-	OSPM can determine that the ACPI hardware registers are owned by SMI (by way
-	of the SCI_EN bit), in which case the ACPI OS issues the ACPI_ENABLE command
-	to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the
-	ACPI hardware registers. OSPM issues commands to the SMI_CMD port
-	synchronously from the boot processor.
-	This filed is reserved and must be zero on system that does not support
-	System Management mode.
-	*/
-	fadt->smi_cmd = 0;
-
-	/*Those two fields are reserved and must be zero on systems that do not
-	support Legacy Mode.*/
-	fadt->acpi_enable = 0;
-	fadt->acpi_disable = 0;
-	
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0x0;
-	
-}
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of rs690. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK		(pm_base + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK		(pm_base + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTORL	(pm_base + 0x08) /* 6 bytes */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	pm_base &= 0xFFFF;
+	printk_debug("pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
+	pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
+	pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
+	pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
+	pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
+	pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
+	pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
+	pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
+	pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
+
+	pm_iowrite(0x2A, 0);	/* AcpiSmiCmdLo */
+	pm_iowrite(0x2B, 0);	/* AcpiSmiCmdHi */
+
+	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
+	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
+
+	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+					* the contents of the PM registers at
+					* index 20-2B to decode ACPI I/O address.
+					* AcpiSmiEn & SmiCmdEn*/
+	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+
+	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c	2008-12-01 19:52:54 UTC (rev 3787)
@@ -29,20 +29,20 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-/* Global variables for MB layouts and these will be shared by irqtable mptable 
+/* Global variables for MB layouts and these will be shared by irqtable mptable
 * and acpi_tables busnum is default.
 */
 u8 bus_isa;
 u8 bus_rs690[8];
 u8 bus_sb600[2];
-unsigned long apicid_sb600;
+u32 apicid_sb600;
 
 /*
 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
 * You may need to preset pci1234 for HTIO board,
 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
 */
-unsigned long pci1234x[] = {
+u32 pci1234x[] = {
 	0x0000ff0,
 };
 
@@ -50,22 +50,22 @@
 * HT Chain device num, actually it is unit id base of every ht device in chain,
 * assume every chain only have 4 ht device at most
 */
-unsigned long hcdnx[] = {
+u32 hcdnx[] = {
 	0x20202020,
 };
 
-unsigned long bus_type[256];
+u32 bus_type[256];
 
-unsigned long sbdn_rs690;
-unsigned long sbdn_sb600;
+u32 sbdn_rs690;
+u32 sbdn_sb600;
 
 extern void get_sblk_pci1234(void);
 
-static unsigned long get_bus_conf_done = 0;
+static u32 get_bus_conf_done = 0;
 
 void get_bus_conf(void)
 {
-	unsigned long apicid_base;
+	u32 apicid_base;
 	device_t dev;
 	int i, j;
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c	2008-12-01 19:52:54 UTC (rev 3787)
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This file was generated by getpir.c, do not modify! 
+/* This file was generated by getpir.c, do not modify!
    (but if you do, please run checkpir on it to verify)
    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c	2008-12-01 19:52:54 UTC (rev 3787)
@@ -19,12 +19,25 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <arch/io.h>
 #include <boot/coreboot_tables.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
 #include "chip.h"
 
+#define ADT7461_ADDRESS 0x4C
+#define SMBUS_IO_BASE 0x1000
+
+extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
+			       u8 val);
+#define ADT7461_read_byte(address) \
+	do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
 /********************************************************
 * dbm690t uses a BCM5789 as on-board NIC.
 * It has a pin named LOW_POWER to enable it into LOW POWER state.
@@ -63,6 +76,109 @@
 	outb(byte, 0xC52);
 }
 
+/********************************************************
+* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66()
+{
+	u8 byte;
+	/*u32 sm_dev, ide_dev; */
+	device_t sm_dev, ide_dev;
+	struct bus pbus;
+
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	byte =
+	    pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
+				sm_dev->path.u.pci.devfn, 0xA9);
+	byte |= (1 << 5);	/* Set Gpio9 as input */
+	pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
+			     sm_dev->path.u.pci.devfn, 0xA9, byte);
+
+	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+	byte =
+	    pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
+				ide_dev->path.u.pci.devfn, 0x56);
+	byte &= ~(7 << 0);
+	if ((1 << 5) & pci_cf8_conf1.
+	    read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn,
+		  0xAA))
+		byte |= 2 << 0;	/* mode 2 */
+	else
+		byte |= 5 << 0;	/* mode 5 */
+	pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
+			     ide_dev->path.u.pci.devfn, 0x56, byte);
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config()
+{
+	u8 byte;
+	u16 word;
+	device_t sm_dev;
+	struct bus pbus;
+
+	/* set ADT 7461 */
+	ADT7461_write_byte(0x0B, 0x50);	/* Local Temperature Hight limit */
+	ADT7461_write_byte(0x0C, 0x00);	/* Local Temperature Low limit */
+	ADT7461_write_byte(0x0D, 0x50);	/* External Temperature Hight limit  High Byte */
+	ADT7461_write_byte(0x0E, 0x00);	/* External Temperature Low limit High Byte */
+
+	ADT7461_write_byte(0x19, 0x55);	/* External THERM limit */
+	ADT7461_write_byte(0x20, 0x55);	/* Local THERM limit */
+
+	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
+	printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
+
+	/* sb600 settings for thermal config */
+	/* set SB600 GPIO 64 to GPIO with pull-up */
+	byte = pm2_ioread(0x42);
+	byte &= 0x3f;
+	pm2_iowrite(0x42, byte);
+
+	/* set GPIO 64 to input */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	word =
+	    pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
+				 sm_dev->path.u.pci.devfn, 0x56);
+	word |= 1 << 7;
+	pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
+			      sm_dev->path.u.pci.devfn, 0x56, word);
+
+	/* set GPIO 64 internal pull-up */
+	byte = pm2_ioread(0xf0);
+	byte &= 0xee;
+	pm2_iowrite(0xf0, byte);
+
+	/* set Talert to be active low */
+	byte = pm_ioread(0x67);
+	byte &= ~(1 << 5);
+	pm_iowrite(0x67, byte);
+
+	/* set Talert to generate ACPI event */
+	byte = pm_ioread(0x3c);
+	byte &= 0xf3;
+	pm_iowrite(0x3c, byte);
+
+	/* THERMTRIP pin */
+	/* byte = pm_ioread(0x68);
+	 * byte |= 1 << 3;
+	 * pm_iowrite(0x68, byte);
+	 *
+	 * byte = pm_ioread(0x55);
+	 * byte |= 1 << 0;
+	 * pm_iowrite(0x55, byte);
+	 *
+	 * byte = pm_ioread(0x67);
+	 * byte &= ~( 1 << 6);
+	 * pm_iowrite(0x67, byte);
+	 */
+}
+
 /*************************************************
 * enable the dedicated function in dbm690t board.
 * This function called early than rs690_enable.
@@ -72,47 +188,54 @@
 	struct mainboard_amd_dbm690t_config *mainboard =
 	    (struct mainboard_amd_dbm690t_config *)dev->chip_info;
 
+	printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev);
+
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info("dbm690t_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", msr.lo, msr.hi);
+	printk_info
+	    ("dbm690t_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info("dbm690t_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", msr2.lo, msr2.hi);
+	printk_info
+	    ("dbm690t_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     msr2.lo, msr2.hi);
 
 	switch (msr.lo) {
-		case 0x10000000: /* 256M system memory */
-			uma_memory_size = 0x2000000; /* 32M recommended UMA */
-			break;
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x2000000;	/* 32M recommended UMA */
+		break;
 
-		case 0x18000000: /* 384M system memory */
-			uma_memory_size = 0x4000000; /* 64M recommended UMA */
-			break;
+	case 0x18000000:	/* 384M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
 
-		case 0x20000000: /* 512M system memory */
-			uma_memory_size = 0x4000000; /* 64M recommended UMA */
-			break;
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
 
-		default: /* 1GB and above system memory */
-			uma_memory_size = 0x8000000; /* 128M recommended UMA */
-			break;
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
 	}
 
-	uma_memory_start = msr.lo - uma_memory_size;/* TOP_MEM1 */
-	printk_info("dbm690t_enable: uma size 0x%08x, memory start 0x%08x\n", uma_memory_size, uma_memory_start);
+	uma_memory_start = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk_info("dbm690t_enable: uma size 0x%08x, memory start 0x%08x\n",
+		    uma_memory_size, uma_memory_start);
 
 	/* TODO: TOP_MEM2 */
 #else
-	uma_memory_size = 0x8000000; /* 128M recommended UMA */
-	uma_memory_start = 0x38000000; /* 1GB  system memory supposed */
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_start = 0x38000000;	/* 1GB  system memory supposed */
 #endif
 
-	printk_info("dbm690t_enable. dev=0x%x\n", dev);
-
 	enable_onboard_nic();
+	get_ide_dma66();
+	set_thermal_config();
 }
 
 /*
@@ -122,5 +245,5 @@
 #if CONFIG_CHIP_NAME == 1
 	CHIP_NAME("AMD Dbm690t   Mainboard")
 #endif
-	.enable_dev = dbm690t_enable,
+	    .enable_dev = dbm690t_enable,
 };

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2008-12-01 19:49:57 UTC (rev 3786)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2008-12-01 19:52:54 UTC (rev 3787)
@@ -31,11 +31,11 @@
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
 
-extern unsigned long apicid_sb600;
+extern u32 apicid_sb600;
 
-extern unsigned long bus_type[256];
-extern unsigned long sbdn_rs690;
-extern unsigned long sbdn_sb600;
+extern u32 bus_type[256];
+extern u32 sbdn_rs690;
+extern u32 sbdn_sb600;
 
 extern void get_bus_conf(void);
 
@@ -102,7 +102,7 @@
 			/* dword |= 1<<22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
-			/* 
+			/*
 			 * 00:12.0: PROG SATA : INT F
 			 * 00:13.0: INTA USB_0
 			 * 00:13.1: INTB USB_1
@@ -121,7 +121,7 @@
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
 	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-	
+
 	IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
 
 	/* ISA ints are edge-triggered, and usually originate from the ISA bus,
@@ -143,8 +143,12 @@
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
+#if HAVE_ACPI_TABLES == 0
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
 
 	/* usb */
 	PCI_INT(0x0, 0x13, 0x0, 0x10);




From marcj303 at gmail.com  Mon Dec  1 20:56:40 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 1 Dec 2008 12:56:40 -0700
Subject: [coreboot] Patches for ACPI support on dbm690t (RS600 and SB600)
In-Reply-To: <13426df10811280857x620035e4j9aed3a6cfa08c906@mail.gmail.com>
References: <DD1CC71B621B004FA76856E5129D6B17022F1025@sbjgexmb1.amd.com>
	<13426df10811260746o1c3a4dfeqa5f382e4109c99f3@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B17022F12AA@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17022F165D@sbjgexmb1.amd.com>
	<13426df10811280857x620035e4j9aed3a6cfa08c906@mail.gmail.com>
Message-ID: <534e5dc20812011156m7ae6360apb9692f5efce10110@mail.gmail.com>

On Fri, Nov 28, 2008 at 9:57 AM, ron minnich <rminnich at gmail.com> wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>

Joe,
Thanks for submitting this code. This is a good example of how to use
the pre-processor to make the APCI table more readable.

Acked-by: Marc Jones <marcj303 at gmail.com>

r3785
r3786
r3787

Thanks,
Marc



From mylesgw at gmail.com  Mon Dec  1 21:38:17 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 13:38:17 -0700
Subject: [coreboot] add 2 k8 devs
Message-ID: <2831fecf0812011238n7c95745dpac20fbcbfebb1918@mail.gmail.com>

This patch adds two more devices to k8.  It adds them to the makefile in
northbridge/amd/k8, and removes some multiple definitions in k8.h and
mainboard.h

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Mon Dec  1 21:43:55 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 13:43:55 -0700
Subject: [coreboot] pnp fixes
Message-ID: <2831fecf0812011243pddea7ddq606b3ddc7a6c5296@mail.gmail.com>

This patch mostly fixes breakage that I introduced in a previous commit.  It
also adds the create flag to the pnp_info struct.  I think we need it until
we figure out how to specify which PNP devices should be created.  Some need
to be created even if they're disabled.

It also changes a !! to a ? 1 : 0

It changes my || to | because I meant |.

It puts the table in superio.c back to how it was in v2, so that there will
be less pain in porting.

It doesn't fix up the other superios, but I will if I get an ack.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Mon Dec  1 21:47:30 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 13:47:30 -0700
Subject: [coreboot] qemu dts fixes
Message-ID: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>

This patch updates qemu.  It takes out the bus construct from the dts, adds
the dts for ide, isa, and acpi.  It changes the default for ide to enabled.
It makes it so that only the plugged in cards are dynamic.

Since it's harder in emulation to tell if chips are cards or on the
mainboard, I may be wrong with the VGA card.  Help?

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From rminnich at gmail.com  Mon Dec  1 21:52:11 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 1 Dec 2008 12:52:11 -0800
Subject: [coreboot] add 2 k8 devs
In-Reply-To: <2831fecf0812011238n7c95745dpac20fbcbfebb1918@mail.gmail.com>
References: <2831fecf0812011238n7c95745dpac20fbcbfebb1918@mail.gmail.com>
Message-ID: <13426df10812011252q12537213t90121e60a615cd3e@mail.gmail.com>

did you need to do an svn add for the device code?

ron



From mylesgw at gmail.com  Mon Dec  1 22:15:50 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 14:15:50 -0700
Subject: [coreboot] add 2 k8 devs
In-Reply-To: <13426df10812011252q12537213t90121e60a615cd3e@mail.gmail.com>
References: <2831fecf0812011238n7c95745dpac20fbcbfebb1918@mail.gmail.com>
	<13426df10812011252q12537213t90121e60a615cd3e@mail.gmail.com>
Message-ID: <2831fecf0812011315t79bd3621v1258f50e50025341@mail.gmail.com>

On Mon, Dec 1, 2008 at 1:52 PM, ron minnich <rminnich at gmail.com> wrote:

> did you need to do an svn add for the device code?


I don't think so.  They were already there.

Thanks,
Myles
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From mylesgw at gmail.com  Mon Dec  1 22:18:52 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 14:18:52 -0700
Subject: [coreboot] resource allocation part 1
Message-ID: <2831fecf0812011318k5701924dpc78eba649ea6f482@mail.gmail.com>

This is mostly the same patch as before, but I separated it into two patches
to make the changes easier to follow.

device/device.c:
    Remove references to have_resources.
    Remove read_resources from compute allocate resources.
    Split compute_allocate_resources into two
    1. compute_resource_needs
        A. Traverse the tree depth first
        B. Sum resources
        C. Adjust limits and bases
        D. Update bridge resources sizes
    2. assign_resource_values
        A. Traverse the tree breadth first
        B. Assign resource values

device/device_util.c:
    Remove references to have_resources.

device/pci_device.c:
    Remove saved values stubs (they're not needed now.)
        1. Sizing function restores values
    Fix 64-bit flag masking.
    Add an error message for an invalid value.
    Update pci_record_bridge_resource:
        1. remove compute_allocate_resource call
        2. remove pci_set_resource call
    Update pci_bus_read_resources to read children's too.
    Update pci_set_resource:
        1. change logic for setting zero-size resources
            A. Set range to [limit->limit-2^gran]
                (Could have been any range with base > limit)
        2. remove compute_allocate_resource calls
        3. Change phase4_assign_resources ->phase4_set_resources

device/pci_ops.c:
    Change an error message to be more helpful.

device/root_device.c:
    Remove code for read_resources and set resources.
    Add a .id to the ops.

include/device/device.h:
    Remove have_resources.
    Comment out assign_resources.  I think we could comment out more here.
    Add debugging function prototypes.
    Change phase4_assign_resources to phase4_set_resources.

include/device/resource.h
    Add a IORESOURCE_BRIDGE flag.

device/cardbus_device.c
    Remove compute_allocate_resource call.
    Use probe_resource (doesn't die) instead of find_resource.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Mon Dec  1 22:33:22 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 14:33:22 -0700
Subject: [coreboot] resource allocation part 2
Message-ID: <2831fecf0812011333r45300b4cg5a131e95ac35a20f@mail.gmail.com>

This patch makes specific devices use the updated resource allocation code.

The changes necessary are:
    1. Remove all calls to compute_allocate_resources.
    2. Read children's resources when yours are read.
    3. Don't store resources except in phase4_set_resources.

northbridge/amd/k8/domain.c:
    A comment for later cleanup efforts.
    Change the resource base from 0x400 to 0x1000 to match the granularity.
    Add the IORESOURCE_BRIDGE flag.
    Read the resources of the grandchildren.
        This should disappear when the domain has the children.
    Update k8_pci_domain_set_resources:
        1. remove compute_allocate_resource call
        2. Change phase4_assign_resources to phase4_set_resources

northbridge/amd/k8/pci.c:

    Remove calls to compute_allocate_resource.
    Make the VGA resource remain visible.
    Stop passing around nodeid so much.
    Remove unneeded #defines

southbridge/amd/amd8132/amd8132_bridge.c:
    Remove NPUML and NPUMB.
    Add a warning for bus disabling.
    Remove bridge_{read|set}_resources (they were there for NPUML)

northbridge/intel/i440bxemulation/i440bx.c:
    Change phase4_assign_resources->phase4_set_resources.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Mon Dec  1 22:37:12 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 14:37:12 -0700
Subject: [coreboot] Resource Allocation discussion
Message-ID: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>

The resource patches I submitted work fairly well, but still need a little
help.

I haven't touched subtractively decoded resources, and that's where the
breakage is right now.

Questions:
- Who should have a resource that moves all other IO resources above 0x400
or 0x1000?
- Is one needed if subtractive resources are implemented correctly?
- Who is responsible for setting the top of the address range?
   - From an earlier thread with Carl-Daniel it sounded like there are fixed
locations for APICs that need to be avoided.  Where should these be avoided?

Thanks,
Myles
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From info at coresystems.de  Mon Dec  1 23:01:04 2008
From: info at coresystems.de (coreboot information)
Date: Mon, 01 Dec 2008 23:01:04 +0100
Subject: [coreboot] r3787 build service
Message-ID: <E1L7GpE-0006rF-Eu@ra.coresystems.de>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "mjones" checked in revision 3787 to
the coreboot source repository and caused the following 
changes:

Change Log:
Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.


Signed-off-by:  Joe Bao <zheng.bao at amd.com>
Reviewed-by:    Maggie Li <maggie.li at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Build Log:
Compilation of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3787&device=dbm690t&vendor=amd


If something broke during this checkin please be a pain 
in mjones's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Mon Dec  1 23:57:00 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 01 Dec 2008 23:57:00 +0100
Subject: [coreboot] Free chips, not required by me, and a question
In-Reply-To: <4933BF09.7080501@stockwith.co.uk>
References: <493111FB.9000701@stockwith.co.uk> <4931E92C.1020807@gmx.net>
	<4933BF09.7080501@stockwith.co.uk>
Message-ID: <49346BBC.4050106@gmx.net>

On 01.12.2008 11:40, Chris Lingard wrote:
> Carl-Daniel Hailfinger wrote:
>> On 29.11.2008 10:57, Chris Lingard wrote:
>>> Now I need help, my machine has Pm49FL004 chips as standard, I have
>>> some Pm49FL008 too.
>>>
>>> I want a 32 M Bit flash chip, if there is such a thing for this type
>
>> Can you tell us more about your mainboard chipset? The Pm49FL004 can do
>> LPC and FWH, but a board only needs one of them.
>>
>> I thought I had seen some data sheets for 32 Mbit chips, but it seems
>> they all were SPI and not FWH/LPC.
>
> Thanks for all the information.  I have done some reading and got the
> data sheets.  My chips are PLCC, (nearly square with pins on all four
> sides).

Ah, that's an old trap. Your chips have a PLCC32 housing, but the
housing is unrelated to the protocol used by the chips.
The protocol for recent chips can be LPC, FWH and SPI. To make matters
more complicated, FWH is a special case variant of LPC with one bit set
differently. That means some data sheets mention the chips speak LPC
although they will not respond to regular LPC read/write cycles.

I've tried to create a marketing language -> chip type mapping below:
- FWH -> FWH
- Firmware Hub -> FWH
- LPC Firmware -> FWH
- Firmware Memory -> FWH
- Low Pin Count (if Firmware/FWH is not mentioned) -> LPC
- LPC (if Firmware is not mentioned) -> LPC

SST data sheets have the following conventions:
"LPC Memory Read" -> LPC
"Firmware Memory Read" -> FWH
If both are mentioned, the chip supports both.

> So am I stuck?  They do not make large capacity {SST,Pm}49LF0??) PLCC
> chips, or is it just an old chip?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From jordan at cosmicpenguin.net  Tue Dec  2 00:29:06 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Mon, 01 Dec 2008 16:29:06 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>	
	<49344EA4.9070208@cosmicpenguin.net>
	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
Message-ID: <49347342.6080504@cosmicpenguin.net>

Myles Watson wrote:
> On Mon, Dec 1, 2008 at 1:52 PM, Jordan Crouse <jordan at cosmicpenguin.net>wrote:
> 
>> Myles Watson wrote:
>>
>>> This patch updates qemu.  It takes out the bus construct from the dts,
>>> adds
>>> the dts for ide, isa, and acpi.  It changes the default for ide to
>>> enabled.
>>> It makes it so that only the plugged in cards are dynamic.
>>>
>>> Since it's harder in emulation to tell if chips are cards or on the
>>> mainboard, I may be wrong with the VGA card.  Help?
>>>
>> Excuse my ignorance, but why does it matter?   They are on the PCI bus
>> regardless of where the logic lives, right?
> 
> 
> It matters for the expansion ROM.  If it's onboard, then coreboot has to
> include it in the lar, otherwise it just reads the "card's" ROM.  It also
> changes the logic of whether or not we set subsytem IDs.

So the defining criteria isn't "onboard or cards", its "need a ROM or 
not" - because not all onboard GPUs require an option ROM in the main 
system ROM - some can use an attached EEPROM (as do soldered down NICs 
and other such devices).

Its not a huge deal, since I see where you are doing with it - but it 
might relieve some confusion if we called it "need_optionrom" instead of 
"on_mainboard".

Jordan





From Zheng.Bao at amd.com  Tue Dec  2 02:30:49 2008
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Tue, 2 Dec 2008 09:30:49 +0800
Subject: [coreboot] r3787 build service
In-Reply-To: <E1L7GpE-0006rF-Eu@ra.coresystems.de>
References: <E1L7GpE-0006rF-Eu@ra.coresystems.de>
Message-ID: <DD1CC71B621B004FA76856E5129D6B1702340EF7@sbjgexmb1.amd.com>

Hi, all,
The dbm690t_acpi.patch we sent has a created directory "acpi" in
src/mainboard/amd/dbm690t. It is lost in the most updated revision. That
is why the error comes up. Do we need send a new patch based on current
revision?

Joe

-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of coreboot information
Sent: Tuesday, December 02, 2008 6:01 AM
To: coreboot mailinglist
Subject: [coreboot] r3787 build service

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "mjones" checked in revision 3787 to
the coreboot source repository and caused the following 
changes:

Change Log:
Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.


Signed-off-by:  Joe Bao <zheng.bao at amd.com>
Reviewed-by:    Maggie Li <maggie.li at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Build Log:
Compilation of amd:dbm690t has been broken
See the error log at
http://qa.coreboot.org/log_buildbrd.php?revision=3787&device=dbm690t&ven
dor=amd


If something broke during this checkin please be a pain 
in mjones's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system



--
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot





From svn at coreboot.org  Tue Dec  2 03:56:38 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  2 Dec 2008 03:56:38 +0100
Subject: [coreboot] r3788 - in trunk/coreboot-v2/src/mainboard/amd/dbm690t:
	. acpi
Message-ID: <mailman.2532.1355071446.16123.coreboot@coreboot.org>

Author: mjones
Date: 2008-12-02 03:56:38 +0100 (Tue, 02 Dec 2008)
New Revision: 3788

Added:
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/cpstate.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/debug.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/doit.sh
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/globutil.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/ide.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/routing.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/sata.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/statdef.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/usb.asl
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c
Log:
I missed the svn add on r3787. These are the additional files. 

Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.


Signed-off-by:  Joe Bao <zheng.bao at amd.com>
Reviewed-by:    Maggie Li <maggie.li at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/cpstate.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/cpstate.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/cpstate.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			Include ("cpstate.asl")
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			Include ("cpstate.asl")
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			Include ("cpstate.asl")
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			Include ("cpstate.asl")
+		}
+	}
+*/
+/*
+ * 1. Get the CPUID to know what the version of the CPU is. (or see what powernow
+ *     reports)
+ * 2. Find how many P-states the CPU supports, power and frequecy in each
+ *     P-states in 'Power and Thermal Data Sheet.' (PTDS)
+ * 3. Go to BIOS and Kernel Developer's Guide (BKDG) and find Low FID Frequency
+ *     Table & High FID Frequency Table. Find Fid for each frequency.
+ * 4. In PTDS, got the Voltage for each P-state. In table VID Code Voltages of BKDG,
+ *     find the VID for each Voltage.
+ *  Is that clear?
+ */
+
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	Name(_PSS, Package(){
+		/* The processor core clock PLL lock time is 2 us for AMD NPT Family 0Fh Processors.*/
+		/* vst=100us*/
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x13<<6|0xD, 0x13<<6|0xD */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x14<<6|0xC, 0x14<<6|0xC */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x15<<6|0xA, 0x15<<6|0xA */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x16<<6|0x8, 0x16<<6|0x8 */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x1E<<6|0x0, 0x1E<<6|0x0 */
+		/*
+		* Package() {2100, 35000, 100, 7, 0xE8202CCD, 0x04CD},
+		* Package() {2000, 30100, 100, 7, 0xE8202D0C, 0x050C},
+		* Package() {1800, 26400, 100, 7, 0xE8202D4A, 0x054A},
+		* Package() {1600, 23000, 100, 7, 0xE8202D88, 0x0588},
+		* Package() { 800,  9400, 100, 7, 0xE8202F80, 0x0780},
+		*/
+		/*Use this tricky method to reserve 8 Pstates space*/
+		Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
+		Package() {0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF},
+		Package() {0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF},
+		Package() {0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF},
+		Package() {0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF},
+		Package() {0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF},
+		Package() {0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF},
+		Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/debug.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/debug.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/debug.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+	DefinitionBlock (
+		"DSDT.AML",
+		"DSDT",
+		0x01,
+		"XXXXXX",
+		"XXXXXXXX",
+		0x00010001
+		)
+	{
+		Include ("debug.asl")
+	}
+*/
+
+/*
+* 0x80: POST_BASE
+* 0x3F8: DEBCOM_BASE
+* X80: POST_REGION
+* P80: PORT80
+*
+* CREG: DEBCOM_REGION
+* CUAR: DEBCOM_UART
+* CDAT: DEBCOM_DATA
+* CDLM: DEBCOM_DLM
+* DLCR: DEBCOM_LCR
+* CMCR: DEBCOM_MCR
+* CLSR: DEBCOM_LSR
+*
+* DEBUG_INIT	DINI
+*/
+
+OperationRegion(X80, SystemIO, 0x80, 1)
+	Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+	Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
+}
+
+/*
+* DINI
+* Initialize the COM port to 115,200 8-N-1
+*/
+Method(DINI)
+{
+	store(0x83, DLCR)
+	store(0x01, CDAT)	/* 115200 baud (low) */
+	store(0x00, CDLM)	/* 115200 baud (high) */
+	store(0x03, DLCR)	/* word=8 stop=1 parity=none */
+	store(0x03, CMCR)	/* DTR=1 RTS=1 Out2=Off Loop=Off */
+	store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/*
+* THRE
+* Wait for COM port transmitter holding register to go empty
+*/
+Method(THRE)
+{
+	and(CLSR, 0x20, local0)
+	while (Lequal(local0, Zero)) {
+		and(CLSR, 0x20, local0)
+	}
+}
+
+/*
+* OUTX
+* Send a single raw character
+*/
+Method(OUTX, 1)
+{
+	THRE()
+	store(Arg0, CDAT)
+}
+
+/*
+* OUTC
+* Send a single character, expanding LF into CR/LF
+*/
+Method(OUTC, 1)
+{
+	if (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/*
+* DBGN
+* Send a single hex nibble
+*/
+Method(DBGN, 1)
+{
+	and(Arg0, 0x0f, Local0)
+	if (LLess(Local0, 10)) {
+		add(Local0, 0x30, Local0)
+	} else {
+		add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/*
+* DBGB
+* Send a hex byte
+*/
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/*
+* DBGW
+* Send a hex word
+*/
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/*
+* DBGD
+* Send a hex Dword
+*/
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/*
+* DBGO
+* Send either a string or an integer
+*/
+Method(DBGO, 1)
+{
+	/* DINI() */
+	if (LEqual(ObjectType(Arg0), 1)) {
+		if (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} else {
+			if (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} else {
+				DBGB(Arg0)
+			}
+		}
+	} else {
+		Name(BDBG, Buffer(80) {})
+		store(Arg0, BDBG)
+		store(0, Local1)
+		while (One) {
+			store(GETC(BDBG, Local1), Local0)
+			if (LEqual(Local0, 0)) {
+				return (0)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+	return (0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	return (DBGC)
+}

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/doit.sh
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/doit.sh	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/doit.sh	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,3 @@
+#!/bin/bash
+#cpp -P dsdt.asl > dsdt.i
+iasl dsdt.asl

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,1832 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x01,               	 /* DSDT Revision */
+	"AMD   ",               /* OEMID */
+	"DBM690T ",          /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* Include ("debug.asl") */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* Memory related values */
+	Name(TOM, 0x40000000)/* Top of RAM memory below 4GB */
+	Name(TOM2, 0x0)	/* Top of RAM memory above 4GB (>> 16) */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+	} /* End _PR scope */
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/* PIC IRQ mapping registers, C00h-C01h */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PINA, 0x00000008,	/* Index 0  */
+		PINB, 0x00000008,	/* Index 1 */
+		PINC, 0x00000008,	/* Index 2 */
+		PIND, 0x00000008,	/* Index 3 */
+		AINT, 0x00000008,	/* Index 4 */
+		SINT, 0x00000008,	/*  Index 5 */
+		, 0x00000008,	             /* Index 6 */
+		AAUD, 0x00000008,	/* Index 7 */
+		AMOD, 0x00000008,	/* Index 8 */
+		PINE, 0x00000008,	/* Index 9 */
+		PINF, 0x00000008,	/* Index A */
+		PING, 0x00000008,	/* Index B */
+		PINH, 0x00000008,	/* Index C */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			   * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			   * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00090024),	/* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve)
+			{
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+	Include ("routing.asl")
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+
+		Method(CIRQ, 0x00, NotSerialized)
+		{
+			Store(0, PINA)
+			Store(0, PINB)
+			Store(0, PINC)
+			Store(0, PIND)
+			Store(0, PINE)
+			Store(0, PINF)
+			Store(0, PING)
+			Store(0, PINH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PINA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PINA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PINB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PINB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PINC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PINC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIND) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIND)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIND, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIND)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PINE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PINE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PINF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PINF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PING) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PING)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PING, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PING)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PINH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PINH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+		\_SB.PCI0.SIOS (Arg0)
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		\_SB.PCI0.SIOW (Arg0)
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			Notify (\_TZ.TZ00, 0x80)
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	Include ("usb.asl")
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		Include ("globutil.asl") /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00120000)
+				Include ("sata.asl")
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00130001)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130003)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00130004)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00130005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				Include ("ide.asl")
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			/* ITE87427 Support */
+			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
+				Field (IOID, ByteAcc, NoLock, Preserve)
+				{
+					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
+				}
+
+			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+			{
+					Offset (0x07),
+				LDN,	8,	/* Logical Device Number */
+					Offset (0x20),
+				CID1,	8,	/* Chip ID Byte 1, 0x87 */
+				CID2,	8,	/* Chip ID Byte 2, 0x12 */
+					Offset (0x30),
+				ACTR,	8,	/* Function activate */
+					Offset (0xF0),
+				APC0,	8,	/* APC/PME Event Enable Register */
+				APC1,	8,	/* APC/PME Status Register */
+				APC2,	8,      /* APC/PME Control Register 1 */
+				APC3,	8,	/* Environment Controller Special Configuration Register */
+				APC4,	8	/* APC/PME Control Register 2 */
+			}
+
+			/* Enter the 87427 MB PnP Mode */
+			Method (EPNP)
+			{
+				Store(0x87, SIOI)
+				Store(0x01, SIOI)
+				Store(0x55, SIOI)
+				Store(0x55, SIOI) /* 87427 magic number */
+			}
+			/* Exit the 87427 MB PnP Mode */
+			Method (XPNP)
+			{
+				Store (0x02, SIOI)
+				Store (0x02, SIOD)
+			}
+
+			/*
+			 * Keyboard PME is routed to SB600 Gevent3. We can wake
+			 * up the system by pressing the key.
+			 */
+		        Method (SIOS, 1)
+			{
+				/* We only enable KBD PME for S5. */
+				If (LLess (Arg0, 0x05))
+				{
+					EPNP()
+					/* DBGO("87427F\n") */
+
+					Store (0x4, LDN)
+					Store (One, ACTR)  /* Enable EC */
+					/*
+					Store (0x4, LDN)
+					Store (0x04, APC4)
+					*/  /* falling edge. which mode? Not sure. */
+
+					Store (0x4, LDN)
+					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+					Store (0x4, LDN)
+					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+					XPNP()
+				}
+			}
+			Method (SIOW, 1)
+			{
+				EPNP()
+				Store (0x4, LDN)
+				Store (Zero, APC0) /* disable keyboard PME */
+				Store (0x4, LDN)
+				Store (0xFF, APC1) /* clear keyboard PME status */
+				XPNP()
+			}
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* Resource source index */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/*  Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/*  Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+}
+/* End of ASL file */

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/globutil.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/globutil.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/globutil.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope(\_SB) {
+	Include ("globutil.asl")
+}
+*/
+
+/* string compare functions */
+Method(MIN, 2)
+{
+	if (LLess(Arg0, Arg1)) {
+		Return(Arg0)
+	} else {
+		Return(Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return(Sizeof(Local0))
+}
+
+Method(S2BF, 1)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return(BUFF)
+}
+
+/* Strong string compare.  Checks both length and content */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While(LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		if (LGreater(Local2, Local3)) {
+			Return(One)
+		} else {
+			if (LLess(Local2, Local3)) {
+				Return(Ones)
+			}
+		}
+		Increment(Local4)
+	}
+	if (LLess(Local4, Local5)) {
+		Return(One)
+	} else {
+		if (LLess(Local4, Local6)) {
+			Return(Ones)
+		} else {
+			Return(Zero)
+		}
+	}
+}
+
+/* Weak string compare.  Checks to find Arg1 at beginning of Arg0.
+* Fails if length(Arg0) < length(Arg1).  Returns 0 on Fail, 1 on
+* Pass.
+*/
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	if (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return(0)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While(LLess(Local2, Local3)) {
+		if (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return(0)
+		}
+		Increment(Local2)
+	}
+	Return(One)
+}
+
+/* ARG0 = IRQ Number(0-15)
+* Returns Bit Map
+*/
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	if (LNotEqual(ARG0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, ARG0, Local0)
+	}
+	Return(Local0)
+}

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/ide.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/ide.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/ide.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			Include ("ide.asl")
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/routing.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/routing.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/routing.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		Include ("routing.asl")
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS690 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0012FFFF, 1, INTA, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0013FFFF, 0, INTA, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+		Package(){0x0013FFFF, 2, INTC, 0 },
+		Package(){0x0013FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS690 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Package(){0x0001FFFF, 0, 0, 18 }, */
+		/* package(){0x0001FFFF, 1, 0, 19 }, */
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0012FFFF, 0, 0, 22 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0013FFFF, 0, 0, 16 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		Package(){0x0013FFFF, 2, 0, 18 },
+		Package(){0x0013FFFF, 3, 0, 19 },
+		/* Package(){0x00130004, 2, 0, 18 }, */
+		/* Package(){0x00130005, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS690 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR1, Package(){
+		/* Internal graphics - RS690 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/sata.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/sata.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/sata.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00120000)
+			Include ("sata.asl")
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/statdef.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/statdef.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/statdef.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/* Status and notification definitions */
+
+#define STA_MISSING			    0x00
+#define STA_PRESENT			    0x01
+#define	STA_ENABLED			    0x03
+#define STA_DISABLED		    0x09
+#define	STA_INVISIBLE		    0x0B
+#define	STA_UNAVAILABLE		    0x0D
+#define	STA_VISIBLE			    0x0F
+
+/* SMBus status codes */
+#define SMB_OK                  0x00
+#define SMB_UnknownFail         0x07
+#define SMB_DevAddrNAK          0x10
+#define SMB_DeviceError         0x11
+#define SMB_DevCmdDenied        0x12
+#define SMB_UnknownErr          0x13
+#define SMB_DevAccDenied        0x17
+#define SMB_Timeout             0x18
+#define SMB_HstUnsuppProtocol   0x19
+#define SMB_Busy                0x1A
+#define SMB_PktChkError         0x1F
+
+/* Device Object Notification Values */
+#define	NOTIFY_BUS_CHECK		0x00
+#define	NOTIFY_DEVICE_CHECK		0x01
+#define	NOTIFY_DEVICE_WAKE		0x02
+#define	NOTIFY_EJECT_REQUEST	0x03
+#define	NOTIFY_DEVICE_CHECK_JR	0x04
+#define	NOTIFY_FREQUENCY_ERROR	0x05
+#define	NOTIFY_BUS_MODE			0x06
+#define	NOTIFY_POWER_FAULT		0x07
+#define	NOTIFY_CAPABILITIES		0x08
+#define	NOTIFY_PLD_CHECK		0x09
+#define	NOTIFY_SLIT_UPDATE		0x0B
+
+/* Battery Device Notification Values */
+#define	NOTIFY_BAT_STATUSCHG	0x80
+#define	NOTIFY_BAT_INFOCHG  	0x81
+#define	NOTIFY_BAT_MAINTDATA    0x82
+
+/* Power Source Object Notification Values */
+#define	NOTIFY_PWR_STATUSCHG	0x80
+
+/* Thermal Zone Object Notification Values */
+#define	NOTIFY_TZ_STATUSCHG	    0x80
+#define	NOTIFY_TZ_TRIPPTCHG	    0x81
+#define	NOTIFY_TZ_DEVLISTCHG	0x82
+#define	NOTIFY_TZ_RELTBLCHG 	0x83
+
+/* Power Button Notification Values */
+#define	NOTIFY_POWER_BUTTON		0x80
+
+/* Sleep Button Notification Values */
+#define	NOTIFY_SLEEP_BUTTON		0x80
+
+/* Lid Notification Values */
+#define	NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define	NOTIFY_CPU_PPCCHG   	0x80
+#define	NOTIFY_CPU_CSTATECHG  	0x81
+#define	NOTIFY_CPU_THROTLCHG    0x82
+
+/* User Presence Device Notification Values */
+#define	NOTIFY_USR_PRESNCECHG	0x80
+
+/* Battery Device Notification Values */
+#define	NOTIFY_ALS_ILLUMCHG 	0x80
+#define	NOTIFY_ALS_COLORTMPCHG 	0x81
+#define	NOTIFY_ALS_RESPCHG      0x82
+
+

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/usb.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/usb.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/usb.asl	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		Include ("usb.asl")
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c	2008-12-02 02:56:38 UTC (rev 3788)
@@ -0,0 +1,755 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include <arch/cpu.h>
+
+#define DUMP_ACPI_TABLES 0
+
+/*
+* Assume the max pstate number is 8
+* 0x21(33 bytes) is one package length of _PSS package
+*/
+
+#define Maxpstate 8
+#define Defpkglength 0x21
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk_debug("\n%08x:", i);
+		}
+		printk_debug(" %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern u8 AmlCode[];
+extern u8 AmlCode_ssdt[];
+
+#if ACPI_SSDTX_NUM >= 1
+extern u8 AmlCode_ssdt2[];
+extern u8 AmlCode_ssdt3[];
+extern u8 AmlCode_ssdt4[];
+extern u8 AmlCode_ssdt5[];
+#endif
+
+#define IO_APIC_ADDR	0xfec00000UL
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB600 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+extern void get_bus_conf(void);
+
+extern void update_ssdt(void *ssdt);
+
+void update_ssdtx(void *ssdtx, int i)
+{
+	uint8_t *PCI;
+	uint8_t *HCIN;
+	uint8_t *UID;
+
+	PCI = ssdtx + 0x32;
+	HCIN = ssdtx + 0x39;
+	UID = ssdtx + 0x40;
+
+	if (i < 7) {
+		*PCI = (uint8_t) ('4' + i - 1);
+	} else {
+		*PCI = (uint8_t) ('A' + i - 1 - 6);
+	}
+	*HCIN = (uint8_t) i;
+	*UID = (uint8_t) (i + 3);
+
+	/* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
+/*
+* Details about this algorithm , refert to BDKG 10.5.1
+* Two parts are included, the another is the DSDT reconstruction process
+*/
+u32 pstates_algorithm(acpi_header_t * dsdt)
+{
+	u8 processor_brand[49];
+	u32 *v;
+	struct cpuid_result cpuid1;
+
+	typedef struct power_limit_encoding {
+		u8 socket_type;
+		u8 cmp_cap;
+		u8 pwr_lmt;
+		u32 power_limit;
+	};
+	u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
+	u16 Max_feq;
+	u8 Pstate_fid[10];
+	u16 Pstate_feq[10];
+	u8 Pstate_vid[10];
+	u32 Pstate_power[10];
+	u32 Pstate_volt[10];
+	u8 PstateStep, PstateStep_coef;
+	u8 IntPstateSup;
+	u8 Pstate_num;
+	u16 Cur_feq;
+	u8 Cur_fid;
+	u8 cmp_cap, pwr_lmt;
+	u32 power_limit = 0;
+	u8 index;
+	u32 i, j;
+	u32 processor_length, scope_length;
+	msr_t msr;
+	u8 *dsdt_pointer;
+	u8 *pointer1;
+	u8 *pointer2;
+	u8 byte_index;
+	u32 old_dsdt_length, new_dsdt_length;
+	u32 corefeq, power, transitionlatency, busmasterlatency, control,
+	    status;
+	u32 new_package_length;
+	u8 sum, checksum;
+	u32 fid_multiplier;
+	static struct power_limit_encoding TDP[20] = {
+		{0x11, 0x0, 0x8, 62},
+		{0x11, 0x1, 0x8, 89},
+		{0x11, 0x1, 0xa, 103},
+		{0x11, 0x1, 0xc, 125},
+		{0x11, 0x0, 0x2, 15},
+		{0x11, 0x0, 0x4, 35},
+		{0x11, 0x1, 0x2, 35},
+		{0x11, 0x0, 0x5, 45},
+		{0x11, 0x1, 0x7, 76},
+		{0x11, 0x1, 0x6, 65},
+		{0x11, 0x1, 0x8, 89},
+		{0x11, 0x0, 0x1, 8},
+		{0x11, 0x1, 0x1, 22},
+		{0x12, 0x0, 0x6, 25},
+		{0x12, 0x0, 0x1, 8},
+		{0x12, 0x0, 0x2, 9},
+		{0x12, 0x0, 0x4, 15},
+		{0x12, 0x0, 0xc, 35},
+		{0x12, 0x1, 0xc, 35},
+		{0x12, 0x1, 0x4, 20}
+	};
+
+	/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
+	cpuid1 = cpuid(0x80000002);
+	v = (u32 *) processor_brand;
+	v[0] = cpuid1.eax;
+	v[1] = cpuid1.ebx;
+	v[2] = cpuid1.ecx;
+	v[3] = cpuid1.edx;
+	cpuid1 = cpuid(0x80000003);
+	v[4] = cpuid1.eax;
+	v[5] = cpuid1.ebx;
+	v[6] = cpuid1.ecx;
+	v[7] = cpuid1.edx;
+	cpuid1 = cpuid(0x80000004);
+	v[8] = cpuid1.eax;
+	v[9] = cpuid1.ebx;
+	v[10] = cpuid1.ecx;
+	v[11] = cpuid1.edx;
+	processor_brand[48] = 0;
+	printk_info("processor_brand=%s\n", processor_brand);
+
+	/*
+	 * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
+	 * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
+	 * cmp_cap : 0x0 SingleCore ; 0x1 DualCore
+	 */
+	printk_info("Pstates Algorithm ...\n");
+	cmp_cap =
+	    (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
+	     0x3000) >> 12;
+	cpuid1 = cpuid(0x80000001);
+	pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
+	for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
+		if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
+		    TDP[index].cmp_cap == cmp_cap &&
+		    TDP[index].pwr_lmt == pwr_lmt) {
+			power_limit = TDP[index].power_limit;
+		}
+
+	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
+	cpuid1 = cpuid(0x80000007);
+	if ((cpuid1.edx & 0x6) != 0x6) {
+		printk_info("No valid set of P-states\n");
+		return 0;
+	}
+
+	msr = rdmsr(0xc0010042);
+	Max_fid = (msr.lo & 0x3F0000) >> 16;
+	Start_fid = (msr.lo & 0x3F00) >> 8;
+	Max_vid = (msr.hi & 0x3F0000) >> 16;
+	Start_vid = (msr.hi & 0x3F00) >> 8;
+	PstateStep = (msr.hi & 0x1000000) >> 24;
+	IntPstateSup = (msr.hi & 0x20000000) >> 29;
+
+	/*
+	 * The P1...P[Min+1] VID need PstateStep to calculate
+	 * P[N] = P[N-1]VID + 2^PstateStep
+	 * PstateStep_coef = 2^PstateStep
+	 */
+	if (PstateStep == 0)
+		PstateStep_coef = 1;
+	else
+		PstateStep_coef = 2;
+
+	if (IntPstateSup == 0) {
+		printk_info("No intermediate P-states are supported\n");
+		return 0;
+	}
+
+	/*get the multipier of the fid frequency */
+	/*
+	 * In RevG, 100MHz step is added
+	 */
+	cpuid1 = cpuid(0x80000007);
+	fid_multiplier = ((cpuid1.edx & 0x40) >> 6) * 100;
+
+	/*
+	 * Formula1:    CPUFreq = FID * fid_multiplier + 800
+	 * Formula2:       CPUVolt = 1550 - VID * 25 (mv)
+	 * Formula3:       Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
+	 */
+
+	/* Construct P0(P[Max]) state */
+	Pstate_num = 0;
+	Max_feq = Max_fid * fid_multiplier + 800;
+	if (Max_fid == 0x2A && Max_vid != 0x0) {
+		Min_fid = 0x2;
+		Pstate_fid[0] = Start_fid + 0xA;	/* Start Frequency + 1GHz */
+		Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
+		Min_vid = Start_vid;
+		Pstate_vid[0] = Max_vid + 0x2;	/* Maximum Voltage - 50mV */
+		Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
+		Pstate_power[0] = power_limit * 1000;	/* mw */
+		Pstate_num++;
+	} else {
+		Min_fid = Start_fid;
+		Pstate_fid[0] = Max_fid;
+		Pstate_feq[0] = Max_feq;
+		Min_vid = Start_vid;
+		Pstate_vid[0] = Max_vid + 0x2;
+		Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
+		Pstate_power[0] = power_limit * 1000;	/* mw */
+		Pstate_num++;
+	}
+
+	Cur_feq = Max_feq;
+	Cur_fid = Max_fid;
+	/* Construct P1 state */
+	if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) {	/* odd value */
+		Pstate_fid[1] = Max_fid - 0x1;
+		Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
+		Cur_fid = Pstate_fid[1];
+		Cur_feq = Pstate_feq[1];
+		if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* odd value */
+			Pstate_vid[1] = Pstate_vid[0] + 0x1;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+		if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* even value */
+			Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+		Pstate_num++;
+	}
+
+	if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) {	/* even value */
+		Pstate_fid[1] = Max_fid - 0x2;
+		Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
+		Cur_fid = Pstate_fid[1];
+		Cur_feq = Pstate_feq[1];
+		if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* odd value */
+			Pstate_vid[1] = Pstate_vid[0] + 0x1;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+		if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* even value */
+			Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+
+		Pstate_num++;
+	}
+
+	/* Construct P2...P[Min-1] state */
+	Cur_fid = Cur_fid - 0x2;
+	Cur_feq = Cur_fid * fid_multiplier + 800;
+	while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
+		Pstate_fid[Pstate_num] = Cur_fid;
+		Pstate_feq[Pstate_num] =
+		    Pstate_fid[Pstate_num] * fid_multiplier + 800;
+		Cur_fid = Cur_fid - 0x2;
+		Cur_feq = Cur_fid * fid_multiplier + 800;
+		if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
+			Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
+			Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
+			Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
+		} else {
+			Pstate_vid[Pstate_num] =
+			    Pstate_vid[Pstate_num - 1] + PstateStep_coef;
+			Pstate_volt[Pstate_num] =
+			    1550 - Pstate_vid[Pstate_num] * 25;
+			Pstate_power[Pstate_num] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
+			    Pstate_volt[Pstate_num] / (Pstate_feq[0] *
+						       Pstate_volt[0] *
+						       Pstate_volt[0]);
+		}
+		Pstate_num++;
+	}
+
+	/* Constuct P[Min] State */
+	if (Max_fid == 0x2A && Max_vid != 0x0) {
+		Pstate_fid[Pstate_num] = 0x2;
+		Pstate_feq[Pstate_num] =
+		    Pstate_fid[Pstate_num] * fid_multiplier + 800;
+		Pstate_vid[Pstate_num] = Min_vid;
+		Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
+		Pstate_power[Pstate_num] =
+		    (unsigned long long)Pstate_power[0] *
+		    Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
+		    Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
+					       Pstate_volt[0]);
+		Pstate_num++;
+	} else {
+		Pstate_fid[Pstate_num] = Start_fid;
+		Pstate_feq[Pstate_num] =
+		    Pstate_fid[Pstate_num] * fid_multiplier + 800;
+		Pstate_vid[Pstate_num] = Min_vid;
+		Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
+		Pstate_power[Pstate_num] =
+		    (unsigned long long)Pstate_power[0] *
+		    Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
+		    Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
+					       Pstate_volt[0]);
+		Pstate_num++;
+	}
+
+	/* Print Pstate feq,vid,volt,power */
+
+	for (index = 0; index < Pstate_num; index++) {
+		printk_info("Pstate_feq[%d] = %dMHz\t", index,
+			    Pstate_feq[index]);
+		printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
+		printk_info("Pstate_volt[%d] = %dmv\t", index,
+			    Pstate_volt[index]);
+		printk_info("Pstate_power[%d] = %dmw\n", index,
+			    Pstate_power[index]);
+	}
+
+	/*
+	 * Modify the DSDT Table to put the actural _PSS package
+	 * corefeq-->Pstate_feq[index] power-->Pstate_power[index] transitionlatency-->0x64 busmasterlatency-->0x7,
+	 * control-->0xE8202C00| Pstate_vid[index]<<6 | Pstate_fid[index]
+	 * status --> Pstate_vid[index]<<6 | Pstate_fid[index]
+	 * Get the _PSS control method Sig.
+	 */
+
+	dsdt_pointer = (u8 *) dsdt;
+	old_dsdt_length = dsdt->length;
+	new_dsdt_length = old_dsdt_length;
+	printk_info("DSDT reconstruction...\n");
+	for (i = 0x20; i < new_dsdt_length; i++)
+		if ((*(dsdt_pointer + i) == '_')
+		    && (*(dsdt_pointer + i + 1) == 'P')
+		    && (*(dsdt_pointer + i + 2) == 'S')
+		    && (*(dsdt_pointer + i + 3) == 'S')) {
+
+			if ((*(dsdt_pointer + i + 4) !=
+			     0x12) | (*(dsdt_pointer + i + 5) !=
+				      0x4B) | (*(dsdt_pointer + i + 6) !=
+					       0x10)) {
+				printk_info
+				    ("Error:No _PSS package leader byte!\n");
+			} else {
+				new_package_length =
+				    0x10B - Defpkglength * (Maxpstate -
+							    Pstate_num);
+				/* two Pstates length will larger than 63, so we need not worry about the length */
+				if (new_package_length > 63) {
+					*(dsdt_pointer + i + 5) =
+					    0x40 | (new_package_length & 0xf);
+					*(dsdt_pointer + i + 6) =
+					    (new_package_length & 0xff0) >> 4;
+				}
+				*(dsdt_pointer + i + 7) = Pstate_num;
+			}
+
+			if ((*(dsdt_pointer + i + 8) !=
+			     0x12) | (*(dsdt_pointer + i + 9) !=
+				      0x20) | (*(dsdt_pointer + i + 10) != 0x6))
+				printk_info
+				    ("Error:No package leader for the first Pstate!\n");
+			for (index = 0; index < Pstate_num; index++) {
+				corefeq = Pstate_feq[index];
+				power = Pstate_power[index];
+				transitionlatency = 0x64;
+				busmasterlatency = 0x7;
+				control =
+				    0xE8202C00 | (Pstate_vid[index] << 6) |
+				    Pstate_fid[index];
+				status =
+				    (Pstate_vid[index] << 6) |
+				    Pstate_fid[index];
+				for (byte_index = 0; byte_index < 4;
+				     byte_index++) {
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + byte_index) =
+		   corefeq >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 +
+					  byte_index) =
+		   power >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 2 +
+					  byte_index) =
+		   transitionlatency >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 3 +
+					  byte_index) =
+		   busmasterlatency >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 4 +
+					  byte_index) =
+		   control >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 5 +
+					  byte_index) =
+		   status >> (8 * byte_index);
+				}
+			}
+			pointer1 =
+			    dsdt_pointer + i + 8 + Pstate_num * Defpkglength;
+			pointer2 =
+			    dsdt_pointer + i + 8 + Maxpstate * Defpkglength;
+			while (pointer2 < dsdt_pointer + new_dsdt_length) {
+				*pointer1 = *pointer2;
+				pointer1++;
+				pointer2++;
+			}
+			/* Recalcute the DSDT length */
+			new_dsdt_length =
+			    new_dsdt_length - Defpkglength * (Maxpstate -
+							      Pstate_num);
+
+			/* Search the first processor(CPUx) item and recalculate the processor length */
+			for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
+				if ((*(dsdt_pointer + i - j) == 'C')
+				    && (*(dsdt_pointer + i - j + 1) == 'P')
+				    && (*(dsdt_pointer + i - j + 2) == 'U')) {
+					processor_length =
+					    ((*(dsdt_pointer + i - j - 1) << 4)
+					     | (*(dsdt_pointer + i - j - 2) &
+						0xf));
+					processor_length =
+					    processor_length -
+					    Defpkglength * (Maxpstate -
+							    Pstate_num);
+					*(dsdt_pointer + i - j - 2) =
+					    (processor_length & 0xf) | 0x40;
+					*(dsdt_pointer + i - j - 1) =
+					    (processor_length & 0xff0) >> 4;
+					break;
+				}
+			}
+
+			/* Search the first scope(_PR_) item and recalculate the scope length */
+			for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
+				if ((*(dsdt_pointer + i - j) == '_')
+				    && (*(dsdt_pointer + i - j + 1) == 'P')
+				    && (*(dsdt_pointer + i - j + 2) == 'R')
+				    && (*(dsdt_pointer + i - j + 3) == '_')) {
+					scope_length =
+					    ((*(dsdt_pointer + i - j - 1) << 4)
+					     | (*(dsdt_pointer + i - j - 2) &
+						0xf));
+					scope_length =
+					    scope_length -
+					    Defpkglength * (Maxpstate -
+							    Pstate_num);
+					*(dsdt_pointer + i - j - 2) =
+					    (scope_length & 0xf) | 0x40;
+					*(dsdt_pointer + i - j - 1) =
+					    (scope_length & 0xff0) >> 4;
+					break;
+				}
+			}
+
+		}
+
+	/* Recalculate the DSDT length and fill back to the table */
+	*(dsdt_pointer + 0x4) = new_dsdt_length;
+	*(dsdt_pointer + 0x5) = new_dsdt_length >> 8;
+
+	/*
+	 * Recalculate the DSDT checksum and fill back to the table
+	 * We must make sure the sum of the whole table is 0
+	 */
+	sum = 0;
+	for (i = 0; i < new_dsdt_length; i++)
+		if (i != 9)
+			sum = sum + *(dsdt_pointer + i);
+	checksum = 0x100 - sum;
+	*(dsdt_pointer + 0x9) = checksum;
+
+	/*Check the DSDT Table */
+	/*
+	 * printk_info("The new DSDT table length is %x\n", new_dsdt_length);
+	 * printk_info("Details is as below:\n");
+	 * for(i=0; i< new_dsdt_length; i++){
+	 *      printk_info("%x\t",(unsigned char)*(dsdt_pointer+i));
+	 *      if( ((i+1)&0x7) == 0x0)
+	 *              printk_info("**0x%x**\n",i-7);
+	 *}
+	 */
+
+	return 1;
+
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf();		/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16byte */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk_debug("ACPI:    * HPET\n");
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdt, hpet);
+
+	printk_debug("ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdt, madt);
+
+#if 0
+	/* SRAT */
+	printk_debug("ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdt, srat);
+
+	/* SLIT */
+	printk_debug("ACPI:    * SLIT\n");
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdt, slit);
+#endif
+
+	/* SSDT */
+	printk_debug("ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *) current;
+	current += ((acpi_header_t *) AmlCode_ssdt)->length;
+	memcpy((void *)ssdt, (void *)AmlCode_ssdt,
+	       ((acpi_header_t *) AmlCode_ssdt)->length);
+	/* Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c */
+	update_ssdt((void *)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((u8 *)ssdt, ssdt->length);
+	acpi_add_table(rsdt, ssdt);
+
+#if ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
+
+	for (i = 1; i < sysconf.hc_possible_num; i++) {	/* 0: is hc sblink */
+		if ((sysconf.pci1234[i] & 1) != 1)
+			continue;
+		uint8_t c;
+		if (i < 7) {
+			c = (uint8_t) ('4' + i - 1);
+		} else {
+			c = (uint8_t) ('A' + i - 1 - 6);
+		}
+		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		current = (current + 0x07) & -0x08;
+		ssdtx = (acpi_header_t *) current;
+		switch (sysconf.hcid[i]) {
+		case 1:	/* 8132 */
+			p = AmlCode_ssdt2;
+			break;
+		case 2:	/* 8151 */
+			p = AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = AmlCode_ssdt5;
+			break;
+		}
+		current += ((acpi_header_t *) p)->length;
+		memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *) p)->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum =
+		    acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdt, ssdtx);
+	}
+#endif
+
+	/* FACS */
+	printk_debug("ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* DSDT */
+	printk_debug("ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy((void *)dsdt, (void *)AmlCode,
+	       ((acpi_header_t *) AmlCode)->length);
+	if (!pstates_algorithm(dsdt))
+		printk_debug("pstates_algorithm error!\n");
+	else
+		printk_debug("pstates_algorithm success.\n");
+
+	current += dsdt->length;
+	printk_debug("ACPI:    * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
+	/* FDAT */
+	printk_debug("ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdt, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+	printk_debug("rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk_debug("rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk_debug("madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk_debug("srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk_debug("slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk_debug("ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk_debug("fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk_info("ACPI: done.\n");
+	return current;
+}




From marcj303 at gmail.com  Tue Dec  2 03:57:22 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 1 Dec 2008 19:57:22 -0700
Subject: [coreboot] Patches for ACPI support on dbm690t (RS600 and SB600)
In-Reply-To: <534e5dc20812011156m7ae6360apb9692f5efce10110@mail.gmail.com>
References: <DD1CC71B621B004FA76856E5129D6B17022F1025@sbjgexmb1.amd.com>
	<13426df10811260746o1c3a4dfeqa5f382e4109c99f3@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B17022F12AA@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17022F165D@sbjgexmb1.amd.com>
	<13426df10811280857x620035e4j9aed3a6cfa08c906@mail.gmail.com>
	<534e5dc20812011156m7ae6360apb9692f5efce10110@mail.gmail.com>
Message-ID: <534e5dc20812011857j227518can83ec9ab969e98e83@mail.gmail.com>

On Mon, Dec 1, 2008 at 12:56 PM, Marc Jones <marcj303 at gmail.com> wrote:
> On Fri, Nov 28, 2008 at 9:57 AM, ron minnich <rminnich at gmail.com> wrote:
>> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>>
>
> Joe,
> Thanks for submitting this code. This is a good example of how to use
> the pre-processor to make the APCI table more readable.
>
> Acked-by: Marc Jones <marcj303 at gmail.com>
>
> r3785
> r3786
> r3787

Sorry, I missed the svn add on this.
r3788



From info at coresystems.de  Tue Dec  2 04:14:50 2008
From: info at coresystems.de (coreboot information)
Date: Tue, 02 Dec 2008 04:14:50 +0100
Subject: [coreboot] r3788 build service
Message-ID: <E1L7Lis-0007Vl-GX@ra.coresystems.de>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "mjones" checked in revision 3788 to
the coreboot source repository and caused the following 
changes:

Change Log:
I missed the svn add on r3787. These are the additional files.

Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.


Signed-off-by:  Joe Bao <zheng.bao at amd.com>
Reviewed-by:    Maggie Li <maggie.li at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Build Log:
Compilation of amd:dbm690t has been fixed


If something broke during this checkin please be a pain 
in mjones's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From pyro at linuxlabs.com  Tue Dec  2 04:17:10 2008
From: pyro at linuxlabs.com (Steven James)
Date: Mon, 1 Dec 2008 22:17:10 -0500 (EST)
Subject: [coreboot] Baremetal bootloader project
In-Reply-To: <18d205ed0811301633s18a34cb7r3f16090f87774c9c@mail.gmail.com>
References: <18d205ed0811301633s18a34cb7r3f16090f87774c9c@mail.gmail.com>
Message-ID: <Pine.LNX.4.58.0812012213380.30609@www>

Greetings,

I'm still lurking about, just very quiet lately.

I think the best part of it that would still be relevant got absorbed into
FILO for USB support.

Since the library itself pulled in includes from the main tree, it's
unlikely to even compile anymore without a fair bit of work.

G'day,
sjames

On Sun, 30 Nov 2008, Gregg Levine wrote:

> Hello!
> During the ramp up that brought us to the coreboot project, one Steven
> James contributed a project he called Baremetal, and described it as a
> bootloader of sorts. During that time period I actually did get it to
> build, but sadly never did get around to test it.
>
> Was this project imported along with everything else to the coreboot
> storage point that we access using subversion? (As it happens I have
> now gotten one of the currently available loaders to work using Qemu.)
>
> -----
> Gregg C Levine gregg.drwho8 at gmail.com
> "This signature was once found posting rude
>  messages in English in the Moscow subway."
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

||||| |||| |||||||||||||  |||
by Linux Labs International, Inc.
   Steven James, CTO

866 824 9737 support




From rminnich at gmail.com  Tue Dec  2 04:37:36 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 1 Dec 2008 19:37:36 -0800
Subject: [coreboot] Baremetal bootloader project
In-Reply-To: <Pine.LNX.4.58.0812012213380.30609@www>
References: <18d205ed0811301633s18a34cb7r3f16090f87774c9c@mail.gmail.com>
	<Pine.LNX.4.58.0812012213380.30609@www>
Message-ID: <13426df10812011937o392c1ed4o7e6f6e9ea39b3147@mail.gmail.com>

In a sense baremetal was a first cut at what we have now in libpayload.

ron



From mylesgw at gmail.com  Tue Dec  2 04:45:09 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 1 Dec 2008 20:45:09 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <49347342.6080504@cosmicpenguin.net>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>	
	<49344EA4.9070208@cosmicpenguin.net>
	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
	<49347342.6080504@cosmicpenguin.net>
Message-ID: <0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>



> -----Original Message-----
> From: Jordan Crouse [mailto:jordan at cosmicpenguin.net]
> Sent: Monday, December 01, 2008 4:29 PM
> To: Myles Watson
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] qemu dts fixes
> 
> Myles Watson wrote:
> > On Mon, Dec 1, 2008 at 1:52 PM, Jordan Crouse
> <jordan at cosmicpenguin.net>wrote:
> >
> >> Myles Watson wrote:
> >>
> >>> This patch updates qemu.  It takes out the bus construct from the dts,
> >>> adds
> >>> the dts for ide, isa, and acpi.  It changes the default for ide to
> >>> enabled.
> >>> It makes it so that only the plugged in cards are dynamic.
> >>>
> >>> Since it's harder in emulation to tell if chips are cards or on the
> >>> mainboard, I may be wrong with the VGA card.  Help?
> >>>
> >> Excuse my ignorance, but why does it matter?   They are on the PCI bus
> >> regardless of where the logic lives, right?
> >
> >
> > It matters for the expansion ROM.  If it's onboard, then coreboot has to
> > include it in the lar, otherwise it just reads the "card's" ROM.  It
> also
> > changes the logic of whether or not we set subsytem IDs.
> 
> So the defining criteria isn't "onboard or cards", its "need a ROM or
> not" - because not all onboard GPUs require an option ROM in the main
> system ROM - some can use an attached EEPROM (as do soldered down NICs
> and other such devices).

I guess the other thing is that you might want to throw an error if
something that's soldered on doesn't respond (and it won't change
addresses), but you won't even know if someone moves a card from slot to
slot or plugs in a new one.

> Its not a huge deal, since I see where you are doing with it - but it
> might relieve some confusion if we called it "need_optionrom" instead of
> "on_mainboard".

It's carried over from v2, but now is the time to change things that don't
make sense.

Thanks,
Myles





From marcj303 at gmail.com  Tue Dec  2 06:42:15 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 1 Dec 2008 22:42:15 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
Message-ID: <534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>

Hi Myles,
I will try to help..... :)

On Mon, Dec 1, 2008 at 2:37 PM, Myles Watson <mylesgw at gmail.com> wrote:
> The resource patches I submitted work fairly well, but still need a little
> help.
>
> I haven't touched subtractively decoded resources, and that's where the
> breakage is right now.
>
> Questions:
> - Who should have a resource that moves all other IO resources above 0x400
> or 0x1000?

What do you mean? By definition the subtractive port takes all
unclaimed cycles. There should be a LPC or ISA bridge in the
southbridge that forwards cycles that the legacy southbridge devices
don't claim.

> - Is one needed if subtractive resources are implemented correctly?

I don't think so. You might need to track the the subtractive bit in
the bridges so you don't try to add those resources to the bridge BAR.

> - Who is responsible for setting the top of the address range?

This should be set per mainboard but the chipset will probably have
them most influence on the value.
#define DEVICE_MEM_HIGH 0xFEBFFFFFUL is probably ok for most systems
but an easy way to override it would be good.

>    - From an earlier thread with Carl-Daniel it sounded like there are fixed
> locations for APICs that need to be avoided.  Where should these be avoided?

Yes, APICs are generally at FEC00000(IO) and FEE00000(local).

Marc



From dfhall at tearosegroup.net  Tue Dec  2 02:56:00 2008
From: dfhall at tearosegroup.net (Darren F. Hall)
Date: Mon, 1 Dec 2008 20:56:00 -0500
Subject: [coreboot] tyan s2875 processor issues
In-Reply-To: <20081122202958.GA3876@darkstar.oz.net>
References: <20081122202958.GA3876@darkstar.oz.net>
Message-ID: <20081202015600.GA3767@darkstar.oz.net>

So far I'm still unsuccessful at getting this board's second processor
to start, so now I'm looking for some direction.

At the moment it is unclear whether the problem is something exclusive
to my end or its a more general problem. To find that out I would like
to ask anyone who is running or attempting to run coreboot on a Tyan
s2875 the following things:

Does it work fully or at least does the second physical processor
initialize? 

In the event that it is functioning correctly what revision, patches,
special configuration files, or deep, black magic are you using?

What kind of processors are you using?

Again thank you for any help you can provide.

DFH




From joe at settoplinux.org  Tue Dec  2 12:03:33 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 02 Dec 2008 06:03:33 -0500
Subject: [coreboot] Free chips, not required by me, and a question
In-Reply-To: <49346BBC.4050106@gmx.net>
References: <493111FB.9000701@stockwith.co.uk> <4931E92C.1020807@gmx.net>
	<4933BF09.7080501@stockwith.co.uk> <49346BBC.4050106@gmx.net>
Message-ID: <0dd02fb1fc3e3d78af4628baeb3ffc4f@imap.1and1.com>


> I've tried to create a marketing language -> chip type mapping below:
> - FWH -> FWH
> - Firmware Hub -> FWH
> - LPC Firmware -> FWH
> - Firmware Memory -> FWH
> - Low Pin Count (if Firmware/FWH is not mentioned) -> LPC
> - LPC (if Firmware is not mentioned) -> LPC
> 
> SST data sheets have the following conventions:
> "LPC Memory Read" -> LPC
> "Firmware Memory Read" -> FWH
> If both are mentioned, the chip supports both.
> 
This is great info Carl-Daniel. Is it listed on the Wiki somewhere? If not
it should be. I always thought we should have a little bit of technical
info in our flashrom "Supported devices" table. A column with the chips
package size (PLCC32, DIP24, etc) and a column with what type the chip is
(ex. FWH, LPC, SPI, etc). This would make it a great reference point for
people looking for a replacement chip, or larger compatable chip. Do you
agree?


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From aaron.lwe at gmail.com  Tue Dec  2 08:58:15 2008
From: aaron.lwe at gmail.com (aaron lwe)
Date: Tue, 2 Dec 2008 15:58:15 +0800
Subject: [coreboot] r3783 - in trunk/coreboot-v2: src/config util/options
Message-ID: <ff277c2e0812012358g3539ce98nbc93d7a7fcad9890@mail.gmail.com>

>>ok, another attempt to the build_opt_tbl problem:
>>- create temp files and move them afterwards

A small problem here, I have a seperate home partition that caused an error:
./build_opt_tbl --config
/home/aaron/src/coreboot-v2/src/mainboard/emulation/qemu-x86/cmos.layout
--header option_table.h --option option_table.c
Error - Could not write option_table.c: Invalid cross-device link

Should the temp file name template be changed or other way?

-Aaron



From stepan at coresystems.de  Tue Dec  2 12:36:28 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 02 Dec 2008 12:36:28 +0100
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
Message-ID: <49351DBC.5050107@coresystems.de>

Myles Watson wrote:
>    - From an earlier thread with Carl-Daniel it sounded like there are
> fixed locations for APICs that need to be avoided.  Where should these
> be avoided?
The right way to do this is create devices for them that hold fixed
address resources.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  2 12:42:08 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Dec 2008 12:42:08 +0100
Subject: [coreboot] r3783 - in trunk/coreboot-v2: src/config util/options
In-Reply-To: <ff277c2e0812012358g3539ce98nbc93d7a7fcad9890@mail.gmail.com>
References: <ff277c2e0812012358g3539ce98nbc93d7a7fcad9890@mail.gmail.com>
Message-ID: <49351F10.8000604@gmx.net>

On 02.12.2008 08:58, aaron lwe wrote:
>>> ok, another attempt to the build_opt_tbl problem:
>>> - create temp files and move them afterwards
>>>       
>
> A small problem here, I have a seperate home partition that caused an error:
> ./build_opt_tbl --config
> /home/aaron/src/coreboot-v2/src/mainboard/emulation/qemu-x86/cmos.layout
> --header option_table.h --option option_table.c
> Error - Could not write option_table.c: Invalid cross-device link
>
> Should the temp file name template be changed or other way?
>   

Thanks for spotting this bug! I'll send a fix soon.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  2 12:44:36 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Dec 2008 12:44:36 +0100
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <49351DBC.5050107@coresystems.de>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<49351DBC.5050107@coresystems.de>
Message-ID: <49351FA4.4000902@gmx.net>

On 02.12.2008 12:36, Stefan Reinauer wrote:
> Myles Watson wrote:
>   
>>    - From an earlier thread with Carl-Daniel it sounded like there are
>> fixed locations for APICs that need to be avoided.  Where should these
>> be avoided?
>>     
> The right way to do this is create devices for them that hold fixed
> address resources.
>   

Sounds good to me. We just have to make sure that fixed address
resources are allowed even if they are between DEVICE_MEM_HIGH and
0xFFFFFFFF.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Tue Dec  2 13:00:58 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 2 Dec 2008 13:00:58 +0100
Subject: [coreboot] Free chips, not required by me, and a question
In-Reply-To: <4933BF09.7080501@stockwith.co.uk>
	<493111FB.9000701@stockwith.co.uk>
References: <493111FB.9000701@stockwith.co.uk> <4931E92C.1020807@gmx.net>
	<4933BF09.7080501@stockwith.co.uk>
	<493111FB.9000701@stockwith.co.uk>
Message-ID: <20081202120058.12204.qmail@stuge.se>

Hi Chris,

Chris Lingard wrote:
> Now I need help, my machine has Pm49FL004 chips as standard, I have
> some Pm49FL008 too.
> 
> I want a 32 M Bit flash chip, if there is such a thing for this
> type of chip, please let me know the part number.  (I would much
> appreciate the exact detail, as the supplier asks incomprehensible
> questions)

Sadly the largest I think you can find that will fit your board is 16
Mbit. Look for the part number SST49LF160C-33-4C-NHE.


Chris Lingard wrote:
> So am I stuck?  They do not make large capacity {SST,Pm}49LF0??)
> PLCC chips, or is it just an old chip?

I'm afraid SST have the largest PLCC package chips at 16 Mbit. The
market demands smaller package chips, so while it's technically
trivial none of the flash manufacturers make larger PLCC package
chips.

If you have a budget you could buy an Artec dongle (150EUR+VAT) and a
PLCC adapter from me (80EUR+VAT) to get 4x32Mbit which is rewritable
through a USB port, but it is a bit costly.


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  2 13:05:45 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Dec 2008 13:05:45 +0100
Subject: [coreboot] [PATCH] Avoid cross-device renames in build_opt_tbl
Message-ID: <49352499.6040302@gmx.net>

Aaron Lwe reported that v2 build fails if /tmp and the build directory
are on different file systems.

That's due to the rename being performed in build_opt_tbl. Renames can't
be done across filesystems. I saw that problem in the original patch,
but I didn't want to ruin the mood by complaining.

Anyway, here is a patch to fix it.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c
===================================================================
--- LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c	(Revision 3788)
+++ LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #define INPUT_LINE_MAX 256
 #define MAX_VALUE_BYTE_LENGTH 64
 
-#define TMPFILE_TEMPLATE "/tmp/build_opt_tbl_XXXXXX"
+#define TMPFILE_TEMPLATE ".XXXXXX"
 
 static unsigned char cmos_table[4096];
 
@@ -215,7 +215,7 @@
 	char *header=0;
 	FILE *fp;
 	int tmpfile;
-	char tmpfilename[32];
+	char *tmpfilename;
 	struct cmos_option_table *ct;
 	struct cmos_entries *ce;
 	struct cmos_enums *c_enums, *c_enums_start;
@@ -485,7 +485,9 @@
 
 	/* See if we want to output a C source file */
 	if(option) {
-	        strcpy(tmpfilename, TMPFILE_TEMPLATE);
+		tmpfilename = malloc(strlen(option) + strlen(TMPFILE_TEMPLATE) + 1);
+	        strcpy(tmpfilename, option);
+	        strcat(tmpfilename, TMPFILE_TEMPLATE);
 		tmpfile = mkstemp(tmpfilename);
 		if(tmpfile == -1) {
                         perror("Error - Could not create temporary file");
@@ -535,7 +537,9 @@
 		struct cmos_option_table *hdr;
 		struct lb_record *ptr, *end;
 
-		strcpy(tmpfilename, TMPFILE_TEMPLATE);
+		tmpfilename = malloc(strlen(header) + strlen(TMPFILE_TEMPLATE) + 1);
+	        strcpy(tmpfilename, header);
+	        strcat(tmpfilename, TMPFILE_TEMPLATE);
 		tmpfile = mkstemp(tmpfilename);
 		if(tmpfile == -1) {
 			perror("Error - Could not create temporary file");


-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  2 13:17:58 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Dec 2008 13:17:58 +0100
Subject: [coreboot] Free chips, not required by me, and a question
In-Reply-To: <20081202120058.12204.qmail@stuge.se>
References: <493111FB.9000701@stockwith.co.uk>
	<4931E92C.1020807@gmx.net>	<4933BF09.7080501@stockwith.co.uk>	<493111FB.9000701@stockwith.co.uk>
	<20081202120058.12204.qmail@stuge.se>
Message-ID: <49352776.3090909@gmx.net>

On 02.12.2008 13:00, Peter Stuge wrote:
> Hi Chris,
>
> Chris Lingard wrote:
>   
>> Now I need help, my machine has Pm49FL004 chips as standard, I have
>> some Pm49FL008 too.
>>
>> I want a 32 M Bit flash chip, if there is such a thing for this
>> type of chip, please let me know the part number.  (I would much
>> appreciate the exact detail, as the supplier asks incomprehensible
>> questions)
>>     
>
> Sadly the largest I think you can find that will fit your board is 16
> Mbit. Look for the part number SST49LF160C-33-4C-NHE.
>
>
> Chris Lingard wrote:
>   
>> So am I stuck?  They do not make large capacity {SST,Pm}49LF0??)
>> PLCC chips, or is it just an old chip?
>>     
>
> I'm afraid SST have the largest PLCC package chips at 16 Mbit. The
> market demands smaller package chips, so while it's technically
> trivial none of the flash manufacturers make larger PLCC package
> chips.
>
> If you have a budget you could buy an Artec dongle (150EUR+VAT) and a
> PLCC adapter from me (80EUR+VAT) to get 4x32Mbit which is rewritable
> through a USB port, but it is a bit costly.
>   

You can also stack up to 16 of the 16 Mbit chips on top of each other,
switching betwee them with the ID[0..3] lines. Depending on how your
mainboard is wired up, you won't even need additional circuitry. And 256
Mbit should be enough for you.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Tue Dec  2 13:26:17 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  2 Dec 2008 13:26:17 +0100
Subject: [coreboot] r3789 - trunk/coreboot-v2/util/options
Message-ID: <mailman.2533.1355071446.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-12-02 13:26:17 +0100 (Tue, 02 Dec 2008)
New Revision: 3789

Modified:
   trunk/coreboot-v2/util/options/build_opt_tbl.c
Log:
build_opt_tbl:
make sure the temporary files are created in the same directory as the
target files so they can be rename()d. This fixes a compilation issue on
machines with the build directory living on another partition than /tmp.
Pretty trivial.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c
===================================================================
--- trunk/coreboot-v2/util/options/build_opt_tbl.c	2008-12-02 02:56:38 UTC (rev 3788)
+++ trunk/coreboot-v2/util/options/build_opt_tbl.c	2008-12-02 12:26:17 UTC (rev 3789)
@@ -4,6 +4,7 @@
 #include <unistd.h>
 #include <ctype.h>
 #include <errno.h>
+#include <libgen.h>
 #include "../../src/include/pc80/mc146818rtc.h"
 #include "../../src/include/boot/coreboot_tables.h"
 
@@ -11,7 +12,8 @@
 #define INPUT_LINE_MAX 256
 #define MAX_VALUE_BYTE_LENGTH 64
 
-#define TMPFILE_TEMPLATE "/tmp/build_opt_tbl_XXXXXX"
+#define TMPFILE_LEN 256
+#define TMPFILE_TEMPLATE "/build_opt_tbl_XXXXXX"
 
 static unsigned char cmos_table[4096];
 
@@ -215,7 +217,7 @@
 	char *header=0;
 	FILE *fp;
 	int tmpfile;
-	char tmpfilename[32];
+	char tmpfilename[TMPFILE_LEN];
 	struct cmos_option_table *ct;
 	struct cmos_entries *ce;
 	struct cmos_enums *c_enums, *c_enums_start;
@@ -485,7 +487,8 @@
 
 	/* See if we want to output a C source file */
 	if(option) {
-	        strcpy(tmpfilename, TMPFILE_TEMPLATE);
+		strncpy(tmpfilename, dirname(option), TMPFILE_LEN);
+	        strncat(tmpfilename, TMPFILE_TEMPLATE, TMPFILE_LEN);
 		tmpfile = mkstemp(tmpfilename);
 		if(tmpfile == -1) {
                         perror("Error - Could not create temporary file");
@@ -535,7 +538,8 @@
 		struct cmos_option_table *hdr;
 		struct lb_record *ptr, *end;
 
-		strcpy(tmpfilename, TMPFILE_TEMPLATE);
+		strncpy(tmpfilename, dirname(option), TMPFILE_LEN);
+	        strncat(tmpfilename, TMPFILE_TEMPLATE, TMPFILE_LEN);
 		tmpfile = mkstemp(tmpfilename);
 		if(tmpfile == -1) {
 			perror("Error - Could not create temporary file");




From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  2 13:37:30 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Dec 2008 13:37:30 +0100
Subject: [coreboot] r3789 - trunk/coreboot-v2/util/options
In-Reply-To: <20081202122816.21393gmx1@mx017.gmx.net>
References: <20081202122816.21393gmx1@mx017.gmx.net>
Message-ID: <49352C0A.5080105@gmx.net>

On 02.12.2008 13:26, svn at coreboot.org wrote:
> Author: stepan
> Date: 2008-12-02 13:26:17 +0100 (Tue, 02 Dec 2008)
> New Revision: 3789
>
> Modified:
>    trunk/coreboot-v2/util/options/build_opt_tbl.c
> Log:
> build_opt_tbl:
> make sure the temporary files are created in the same directory as the
> target files so they can be rename()d. This fixes a compilation issue on
> machines with the build directory living on another partition than /tmp.
> Pretty trivial.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
>   

This will break if the path is longer than 234 bytes, whereas PATH_MAX
on my Linux system is 4096.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Tue Dec  2 14:02:04 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 2 Dec 2008 14:02:04 +0100
Subject: [coreboot] r3789 - trunk/coreboot-v2/util/options
In-Reply-To: <49352C0A.5080105@gmx.net>
References: <20081202122816.21393gmx1@mx017.gmx.net> <49352C0A.5080105@gmx.net>
Message-ID: <20081202130204.28666.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> This will break if the path is longer than 234 bytes, whereas
> PATH_MAX on my Linux system is 4096.

Would obviously rock if you sent a patch too. :)


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  2 14:28:30 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Dec 2008 14:28:30 +0100
Subject: [coreboot] r3789 - trunk/coreboot-v2/util/options
In-Reply-To: <20081202130204.28666.qmail@stuge.se>
References: <20081202122816.21393gmx1@mx017.gmx.net> <49352C0A.5080105@gmx.net>
	<20081202130204.28666.qmail@stuge.se>
Message-ID: <493537FE.6070102@gmx.net>

On 02.12.2008 14:02, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> This will break if the path is longer than 234 bytes, whereas
>> PATH_MAX on my Linux system is 4096.
>>     
>
> Would obviously rock if you sent a patch too. :)
>   

Sure, I already did that. See "[coreboot] [PATCH] Avoid cross-device
renames in build_opt_tbl".

Should I revert r3789 and apply my patch instead? Or is a fusion of both
patches preferred?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mylesgw at gmail.com  Tue Dec  2 14:57:40 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 06:57:40 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
Message-ID: <BE6EF501005248F69CAB0169816A73D0@chimp>



> -----Original Message-----
> From: Marc Jones [mailto:marcj303 at gmail.com]
> Sent: Monday, December 01, 2008 10:42 PM
> To: Myles Watson
> Cc: Coreboot
> Subject: Re: [coreboot] Resource Allocation discussion
> 
> Hi Myles,
> I will try to help..... :)
> 
> On Mon, Dec 1, 2008 at 2:37 PM, Myles Watson <mylesgw at gmail.com> wrote:
> > The resource patches I submitted work fairly well, but still need a
> little
> > help.
> >
> > I haven't touched subtractively decoded resources, and that's where the
> > breakage is right now.
> >
> > Questions:
> > - Who should have a resource that moves all other IO resources above
> 0x400
> > or 0x1000?
> 
> What do you mean? By definition the subtractive port takes all
> unclaimed cycles. There should be a LPC or ISA bridge in the
> southbridge that forwards cycles that the legacy southbridge devices
> don't claim.

Sorry.  I wasn't clear enough again.  What I meant was something more like:

Since the resource allocation algorithm can't avoid resources that it
doesn't know about, who decides if the subtractive area to avoid is
0x0-0x400, 0x0-0x1000, or some other range?  If I declare some device to
hold these addresses so that no other resource ends up there, should it be
subtractive?  I'm inclined to put it in the domain or in the SuperIO.

> > - Is one needed if subtractive resources are implemented correctly?
> 
> I don't think so. You might need to track the the subtractive bit in
> the bridges so you don't try to add those resources to the bridge BAR.

Right now subtractive resources are just skipped altogether.

> > - Who is responsible for setting the top of the address range?
> 
> This should be set per mainboard but the chipset will probably have
> them most influence on the value.

Are you aware of mainboards with the same chipset that have different
DEVICE_MEM_HIGH?

> #define DEVICE_MEM_HIGH 0xFEBFFFFFUL is probably ok for most systems
> but an easy way to override it would be good.

I'd like this to be in the domain as well.  If we set the domain's resource
range to 0x0-0xFEBFFFFF, then nothing will get allocated outside of that.

> >    - From an earlier thread with Carl-Daniel it sounded like there are
> fixed
> > locations for APICs that need to be avoided.  Where should these be
> avoided?
> 
> Yes, APICs are generally at FEC00000(IO) and FEE00000(local).

So these should be created in the domain?

Thanks,
Myles




From mylesgw at gmail.com  Tue Dec  2 14:58:10 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 06:58:10 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <49351DBC.5050107@coresystems.de>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<49351DBC.5050107@coresystems.de>
Message-ID: <9E76CB8D1BC84DE887934AE173302607@chimp>



> -----Original Message-----
> From: Stefan Reinauer [mailto:stepan at coresystems.de]
> Sent: Tuesday, December 02, 2008 4:36 AM
> To: Myles Watson
> Cc: Coreboot
> Subject: Re: [coreboot] Resource Allocation discussion
> 
> Myles Watson wrote:
> >    - From an earlier thread with Carl-Daniel it sounded like there are
> > fixed locations for APICs that need to be avoided.  Where should these
> > be avoided?
> The right way to do this is create devices for them that hold fixed
> address resources.

In the domain, or wherever they're implemented?

Thanks,
Myles




From mylesgw at gmail.com  Tue Dec  2 14:59:11 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 06:59:11 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <49351FA4.4000902@gmx.net>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<49351DBC.5050107@coresystems.de> <49351FA4.4000902@gmx.net>
Message-ID: <727D3946F4F648FC80F3F7104839A1DB@chimp>



> -----Original Message-----
> From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net]
> Sent: Tuesday, December 02, 2008 4:45 AM
> To: Stefan Reinauer
> Cc: Myles Watson; Coreboot
> Subject: Re: [coreboot] Resource Allocation discussion
> 
> On 02.12.2008 12:36, Stefan Reinauer wrote:
> > Myles Watson wrote:
> >
> >>    - From an earlier thread with Carl-Daniel it sounded like there are
> >> fixed locations for APICs that need to be avoided.  Where should these
> >> be avoided?
> >>
> > The right way to do this is create devices for them that hold fixed
> > address resources.
> >
> 
> Sounds good to me. We just have to make sure that fixed address
> resources are allowed even if they are between DEVICE_MEM_HIGH and
> 0xFFFFFFFF.

Fixed resources right now just get skipped.  They're not even considered by
the allocator.  I think it might be nice to do some sort of sanity check,
but ...

Thanks,
Myles





From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  2 15:00:56 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Dec 2008 15:00:56 +0100
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <727D3946F4F648FC80F3F7104839A1DB@chimp>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<49351DBC.5050107@coresystems.de> <49351FA4.4000902@gmx.net>
	<727D3946F4F648FC80F3F7104839A1DB@chimp>
Message-ID: <49353F98.7050607@gmx.net>

On 02.12.2008 14:59, Myles Watson wrote:
>   
>> -----Original Message-----
>> From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net]
>> Sent: Tuesday, December 02, 2008 4:45 AM
>> To: Stefan Reinauer
>> Cc: Myles Watson; Coreboot
>> Subject: Re: [coreboot] Resource Allocation discussion
>>
>> On 02.12.2008 12:36, Stefan Reinauer wrote:
>>     
>>> Myles Watson wrote:
>>>
>>>       
>>>>    - From an earlier thread with Carl-Daniel it sounded like there are
>>>> fixed locations for APICs that need to be avoided.  Where should these
>>>> be avoided?
>>>>
>>>>         
>>> The right way to do this is create devices for them that hold fixed
>>> address resources.
>>>
>>>       
>> Sounds good to me. We just have to make sure that fixed address
>> resources are allowed even if they are between DEVICE_MEM_HIGH and
>> 0xFFFFFFFF.
>>     
>
> Fixed resources right now just get skipped.  They're not even considered by
> the allocator.  I think it might be nice to do some sort of sanity check,
> but ...
>   

A nice warning message for overlapping resources would be helpful.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From r.marek at assembler.cz  Tue Dec  2 15:10:43 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Dec 2008 15:10:43 +0100
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <BE6EF501005248F69CAB0169816A73D0@chimp>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
Message-ID: <493541E3.2090507@assembler.cz>

>> Yes, APICs are generally at FEC00000(IO) and FEE00000(local).
> 
> So these should be created in the domain?

Yes and no? Check this:

http://www.coreboot.org/Memory_map

Also MMCONFIG region should be somewhere. For VIAs, the static resources are in 
.h files in V2
http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h
http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h

Problem is that some resources (APICs can be only on arbitrary range, typically 
0xfec0 0000 - 0xfecf ffff

So DEVICE_MEM_HIGH should be lower then those .h files?? And IO_LOW would be 
nice too...

Rudolf



From mylesgw at gmail.com  Tue Dec  2 15:13:01 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 07:13:01 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>
	<49344EA4.9070208@cosmicpenguin.net>
	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
	<49347342.6080504@cosmicpenguin.net>
	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
Message-ID: <2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>

Jordan,

Sorry I obviously missed the point of your questions.  I'd forgotten that
the fix went in to make all devices found in the dts be "on the mainboard."
Here's a new patch that updates the dts with that in mind.  It also fixes
the subsystem_vendor, which was broken in the last patch.

I appreciate the sanity check.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From r.marek at assembler.cz  Tue Dec  2 15:20:27 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Dec 2008 15:20:27 +0100
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <493541E3.2090507@assembler.cz>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<493541E3.2090507@assembler.cz>
Message-ID: <4935442B.60700@assembler.cz>

Sorry I forgot to ask if the DEVICE_MEM_HIGH is in fact the HIGH limit for MMIO 
or not. Of course CPU must be instructed to decode the addresses as MMIO too. 
But in some range we need static allocation.

For MMIO decode:

DEVICE_MEM_LOW =< DEVICE_MEM_LOW_STATIC < DEVICE_MEM_HIGH_STATIC =< DEVICE_MEM_HIGH

And similar for IO decode.

Like here K8 resources:

MMIO map: #7 0x0040000000 - 0x00ff70ffff Access: R/W     Dstnode:0 DstLink 0
   IO map: #0  0x000000 - 0x000fff Access: /    Dstnode:0 DstLink 0
   IO map: #1  0x001000 - 0x0fffff Access: R/W   VGA Dstnode:0 DstLink 0
   IO map: #2  0x000000 - 0x000fff Access: /    Dstnode:0 DstLink 0
   IO map: #3  0x000000 - 0x000fff Access: /    Dstnode:0 DstLink 0

Rudolf



From mylesgw at gmail.com  Tue Dec  2 15:32:37 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 07:32:37 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <493541E3.2090507@assembler.cz>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<493541E3.2090507@assembler.cz>
Message-ID: <5C2C19EAB23942C399DBD0EE9B793104@chimp>



> -----Original Message-----
> From: Rudolf Marek [mailto:r.marek at assembler.cz]
> Sent: Tuesday, December 02, 2008 7:11 AM
> To: Myles Watson
> Cc: 'Marc Jones'; 'Coreboot'
> Subject: Re: [coreboot] Resource Allocation discussion
> 
> >> Yes, APICs are generally at FEC00000(IO) and FEE00000(local).
> >
> > So these should be created in the domain?
> 
> Yes and no? Check this:
> 
> http://www.coreboot.org/Memory_map

Thanks for the pointers!
 
> Also MMCONFIG region should be somewhere. For VIAs, the static resources
> are in
> .h files in V2
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-
> v2/src/southbridge/via/k8t890/k8t890.h
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-
> v2/src/southbridge/via/vt8237r/vt8237r.h
> 
> Problem is that some resources (APICs can be only on arbitrary range,
> typically
> 0xfec0 0000 - 0xfecf ffff
> 
> So DEVICE_MEM_HIGH should be lower then those .h files?? And IO_LOW would
> be
> nice too...

I'm hoping that these defines can go away.  I'd like each board or each
domain to define their areas explicitly.  So, for example, the k8t890 has:

------- From k8t890_traf_ctrl.c ------

	pci_dev_read_resources(dev);

	res = new_resource(dev, 0x40);
	/* NB APIC fixed to this address. */
	res->base = K8T890_APIC_BASE;
	res->size = 256;
	res->limit = res->base + res->size - 1;
	res->align = 8;
	res->gran = 8;
	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;

	/* Add an MMCONFIG resource. */
	res = new_resource(dev, K8T890_MMCONFIG_MBAR);
	res->size = 256 * 1024 * 1024;
	res->align = log2(res->size);
	res->gran = log2(res->size);
	res->limit = 0xffffffff;	/* 4G */
	res->flags = IORESOURCE_MEM;

------- end ----------

So it seems like we could add bridge resources that contain all the space
that can be used for allocations to the domain below this.

> -----Original Message-----
> 
> Sorry I forgot to ask if the DEVICE_MEM_HIGH is in fact the HIGH limit for
> MMIO
> or not.
I don't know for sure.

> Of course CPU must be instructed to decode the addresses as MMIO
> too.
Yes.

> But in some range we need static allocation.
> 
> For MMIO decode:
> 
> DEVICE_MEM_LOW =< DEVICE_MEM_LOW_STATIC < DEVICE_MEM_HIGH_STATIC =<
> DEVICE_MEM_HIGH
> 
> And similar for IO decode.
> 
> Like here K8 resources:
> 
> MMIO map: #7 0x0040000000 - 0x00ff70ffff Access: R/W     Dstnode:0 DstLink
> 0
>    IO map: #0  0x000000 - 0x000fff Access: /    Dstnode:0 DstLink 0
>    IO map: #1  0x001000 - 0x0fffff Access: R/W   VGA Dstnode:0 DstLink 0
>    IO map: #2  0x000000 - 0x000fff Access: /    Dstnode:0 DstLink 0
>    IO map: #3  0x000000 - 0x000fff Access: /    Dstnode:0 DstLink 0

If we explicitly declare the resources we use, I'm hoping that the
device-specific code can do the right thing.

Thanks,
Myles




From r.marek at assembler.cz  Tue Dec  2 15:56:06 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Dec 2008 15:56:06 +0100
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <5C2C19EAB23942C399DBD0EE9B793104@chimp>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>	<BE6EF501005248F69CAB0169816A73D0@chimp>	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
Message-ID: <49354C86.9000805@assembler.cz>

> ------- From k8t890_traf_ctrl.c ------
> 
> 	pci_dev_read_resources(dev);
> 
> 	res = new_resource(dev, 0x40);
> 	/* NB APIC fixed to this address. */
> 	res->base = K8T890_APIC_BASE;
> 	res->size = 256;
> 	res->limit = res->base + res->size - 1;
> 	res->align = 8;
> 	res->gran = 8;
> 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
> 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
> 
> 	/* Add an MMCONFIG resource. */
> 	res = new_resource(dev, K8T890_MMCONFIG_MBAR);
> 	res->size = 256 * 1024 * 1024;
> 	res->align = log2(res->size);
> 	res->gran = log2(res->size);
> 	res->limit = 0xffffffff;	/* 4G */
> 	res->flags = IORESOURCE_MEM;
> 
> ------- end ----------

Yes now I remember that I wrote the code ;) so please disregard mine previous 
mail about _LOW and _STATIC_HIGH.

Problem is that some resources needs to go to ACPI. And it is needed to

1) store them in some ACPI table during table construction, read resource should 
work.

2) worse case - store in AML code. This can be done by some SSDT hacks which is 
ugly or write AML code which re-reads the resources from hardware.


Ad 1)
http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/fadt.c
http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/acpi_tables.c

Ad 2)

http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/northbridge/amd/amdk8/ssdt.dsl
http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/agami/aruma/acpi_tables.c

In fact #2 as in ARUMA and proper DSDT code which handles _CSR (CRS?) resources 
is neccessary for Windows to boot properly. Check the Aruma DSDT:

http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/agami/aruma/dx/dsdt_lb.dsl

(In particular Method (_CRS, 0, NotSerialized) for PCI0).

Rudolf






From mylesgw at gmail.com  Tue Dec  2 17:17:29 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 09:17:29 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <49354C86.9000805@assembler.cz>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>	<BE6EF501005248F69CAB0169816A73D0@chimp>	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
Message-ID: <FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>



> -----Original Message-----
> From: Rudolf Marek [mailto:r.marek at assembler.cz]
> Sent: Tuesday, December 02, 2008 7:56 AM
> To: Myles Watson
> Cc: 'Marc Jones'; 'Coreboot'
> Subject: Re: [coreboot] Resource Allocation discussion
> 
> > ------- From k8t890_traf_ctrl.c ------
> >
> > 	pci_dev_read_resources(dev);
> >
> > 	res = new_resource(dev, 0x40);
> > 	/* NB APIC fixed to this address. */
> > 	res->base = K8T890_APIC_BASE;
> > 	res->size = 256;
> > 	res->limit = res->base + res->size - 1;
> > 	res->align = 8;
> > 	res->gran = 8;
> > 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
> > 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
> >
> > 	/* Add an MMCONFIG resource. */
> > 	res = new_resource(dev, K8T890_MMCONFIG_MBAR);
> > 	res->size = 256 * 1024 * 1024;
> > 	res->align = log2(res->size);
> > 	res->gran = log2(res->size);
> > 	res->limit = 0xffffffff;	/* 4G */
> > 	res->flags = IORESOURCE_MEM;
> >
> > ------- end ----------
> 
> Yes now I remember that I wrote the code ;) so please disregard mine
> previous
> mail about _LOW and _STATIC_HIGH.

:)

I'm wondering why the size of the APIC region here is 256.  That's smaller
than any reference from the resource map link you sent.

> Problem is that some resources needs to go to ACPI. And it is needed to
> 
> 1) store them in some ACPI table during table construction, read resource
> should
> work.
> 
> 2) worse case - store in AML code. This can be done by some SSDT hacks
> which is
> ugly or write AML code which re-reads the resources from hardware.

Which device should logically own the ACPI resources?  We can just allocate
them there.  I vote for the domain or the mainboard (root device) to own
them. 

> 
> Ad 1)
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-
> v2/src/mainboard/asus/a8v-e_se/fadt.c
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-
> v2/src/mainboard/asus/a8v-e_se/acpi_tables.c
> 
> Ad 2)
> 
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-
> v2/src/northbridge/amd/amdk8/ssdt.dsl
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-
> v2/src/mainboard/agami/aruma/acpi_tables.c
> 
> In fact #2 as in ARUMA and proper DSDT code which handles _CSR (CRS?)
> resources
> is neccessary for Windows to boot properly. Check the Aruma DSDT:
> 
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-
> v2/src/mainboard/agami/aruma/dx/dsdt_lb.dsl
> 
> (In particular Method (_CRS, 0, NotSerialized) for PCI0).

I'm in too deep here.  I'm hoping that we can figure out resource allocation
a little better before we move on to ACPI tables.

Thanks,
Myles




From jordan at cosmicpenguin.net  Tue Dec  2 17:24:37 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Tue, 02 Dec 2008 09:24:37 -0700
Subject: [coreboot] [PATCH] buildrom:  add 'source' target
Message-ID: <49356145.2060306@cosmicpenguin.net>

Per request - a target to only download the source code packages in 
buildrom.

Jordan
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From r.marek at assembler.cz  Tue Dec  2 17:30:17 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 02 Dec 2008 17:30:17 +0100
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>	<BE6EF501005248F69CAB0169816A73D0@chimp>	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
Message-ID: <49356299.2040408@assembler.cz>

Myles Watson wrote:
> 
>> -----Original Message-----
>> From: Rudolf Marek [mailto:r.marek at assembler.cz]
> I'm wondering why the size of the APIC region here is 256.  That's smaller
> than any reference from the resource map link you sent.

The K8M890 APIC decodes only 256 bytes. Some APICs can decode more.


> 
> Which device should logically own the ACPI resources?  We can just allocate
> them there.  I vote for the domain or the mainboard (root device) to own
> them. 

Here is something how the other resources from host bus and PCI bus are handled:

http://www.acpi.info/acpi_faq.htm

How do I report a CPU-to-PCI bridge (root PCI Bus) in the ACPI NameSpace?

And also some more about the ACPI representation in:
http://www.google.cz/search?hl=cs&q=%22PCI+Firmware+Specification%22+filetype%3Apdf&btnG=Hledat&lr=
http://www.pcisig.com/specifications/conventional/pci_firmware/PCI_FW_Slot_Power_ECN_website.pdf

> I'm in too deep here.  I'm hoping that we can figure out resource allocation
> a little better before we move on to ACPI tables.

Yes ;)

Rudolf



From jordan at cosmicpenguin.net  Tue Dec  2 17:45:19 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Tue, 02 Dec 2008 09:45:19 -0700
Subject: [coreboot] [PATCH] coreboot-v3: Default to qemu
Message-ID: <4935661F.7030801@cosmicpenguin.net>

If no .config exists, then default to qemu for defconfig targets.  As a 
further extension, I think we should consider allowing the user to pass 
the desired mainboard via an environment variable:

make MAINBOARD=amd/db800 defconfig

Jordan
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From mylesgw at gmail.com  Tue Dec  2 18:57:29 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 10:57:29 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>
	<49344EA4.9070208@cosmicpenguin.net>
	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
	<49347342.6080504@cosmicpenguin.net>
	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>
Message-ID: <2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>

On Tue, Dec 2, 2008 at 7:13 AM, Myles Watson <mylesgw at gmail.com> wrote:

> Jordan,
>
> Sorry I obviously missed the point of your questions.  I'd forgotten that
> the fix went in to make all devices found in the dts be "on the mainboard."
> Here's a new patch that updates the dts with that in mind.  It also fixes
> the subsystem_vendor, which was broken in the last patch.
>
> I appreciate the sanity check.

This patch is updated so that qemu works with resource allocation in phases.
Here are the changes:

1. Add a dts for the northbridge so it can have its own ops.
2. Separates the domain from the device resource code.
3. Add new resources for the APIC and VGA area.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
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From mylesgw at gmail.com  Tue Dec  2 19:02:24 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 11:02:24 -0700
Subject: [coreboot] resource allocation part 1
In-Reply-To: <2831fecf0812011318k5701924dpc78eba649ea6f482@mail.gmail.com>
References: <2831fecf0812011318k5701924dpc78eba649ea6f482@mail.gmail.com>
Message-ID: <2831fecf0812021002u28dc49e3o522c7051cc5ed711@mail.gmail.com>

I had an error in the type_mask logic with PREF_64.

This fixes it so that it works with qemu.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Tue Dec  2 19:06:41 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 11:06:41 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <49356299.2040408@assembler.cz>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
Message-ID: <2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>

Here's the read_resources code from qemu after my latest patch.  Is this
what people are thinking?  Notice that I explicitly allocate VGA space and
APIC.  At the end of the code I'm pasting in a snippet of the log that shows
the resources after they are assigned values.

Thanks,
Myles

static void i440bx_read_resources(struct device *dev)
{
    struct resource *res;
    u32 tolmk;        /* Top of low mem, Kbytes. */
    int idx;

    /* I/O resource. */
    res = new_resource(dev, 0);
    res->base = 0x1000UL;
    res->limit = 0xFFFFUL;
    res->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;

    /* read large mem memory descriptor
       for <16 MB read the more detailed small mem descriptor
       all values in kbytes */
    tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64;
    if (tolmk <= 16 * 1024) {
        tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30);
    }

    printk(BIOS_WARNING, "Using CMOS settings of %d kB RAM.\n", tolmk);
    idx = 10;

    /* 0 .. 640 kB */
    ram_resource(dev, idx++, 0, 640);

    /* Hole for VGA (0xA0000-0xAFFFF) graphics and text mode
     * graphics (0xB8000-0xBFFFF) */
    res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
    res->base = 0xA0000UL;
    res->size = 0x20000UL;
    res->limit = 0xBFFFUL;
    res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
             IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

    /* 768 kB .. Systop (in KB) */
    ram_resource(dev, idx++, 768, tolmk - 768);
}

static void i440bx_domain_read_resources(struct device *dev)
{
    struct resource *res;

    /* Initialize the domain's I/O space constraints. */
    res = new_resource(dev, 0);
    res->base = 0x1000UL;
    res->limit = 0xffffUL;
    res->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;

    /* Initialize the system-wide memory resources constraints. */
    res = new_resource(dev, 1);
    res->limit = 0xffffffffULL;
    res->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;

    /* Reserve space for the APIC. */
    res = new_resource(dev, 2);
    res->base = 0xfec00000UL;
    res->size = 0x100000UL;
    res->limit = 0xffffffffULL;
    res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED;

    /* Reserve space for the APIC. */
    res = new_resource(dev, 2);
    res->base = 0xfee00000UL;
    res->size = 0x10000UL;
    res->limit = 0xffffffffULL;
    res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED;
}

Show resources in subtree (root)...After assigning values.
 Root Device links 1 child on link 0 cpus
 Root Device resource base 1000 size 410 align 8 gran 0 limit ffff flags
80100 index 0
 Root Device resource base fc000000 size 2001000 align 25 gran 0 limit
ffffffff flags 40080200 index 1
 Root Device resource base 0 size 0 align 0 gran 0 limit ffffffffffffffff
flags 81200 index 2
  CPU: 00 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0
  PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit ffff
flags 40080100 index 0
  PCI_DOMAIN: 0000 resource base fc000000 size 2001000 align 25 gran 0 limit
ffffffff flags 40080200 index 1
  PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit
ffffffff flags a0000200 index 2
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:00.0 resource base 1000 size 0 align 0 gran 0 limit ffff flags
80100 index 0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index a
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff
flags c0040200 index 10000000
   PCI: 00:00.0 resource base c0000 size 6f40000 align 0 gran 0 limit 0
flags e0004200 index b
   PCI: 00:01.0 links 0 child on link 0 NULL
   PCI: 00:01.1 links 0 child on link 0 NULL
   PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit ffff flags
40000100 index 20
   PCI: 00:01.3 links 0 child on link 0 NULL
   PCI: 00:02.0 links 0 child on link 0 NULL
   PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit
ffffffff flags 40001200 index 10
   PCI: 00:02.0 resource base fe000000 size 1000 align 12 gran 12 limit
ffffffff flags 40000200 index 14
   PCI: 00:03.0 links 0 child on link 0 NULL
   PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags
40000100 index 10
Phase 4: Setting resources...
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From mylesgw at gmail.com  Tue Dec  2 19:23:59 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 11:23:59 -0700
Subject: [coreboot] [PATCH] buildrom: add 'source' target
In-Reply-To: <49356145.2060306@cosmicpenguin.net>
References: <49356145.2060306@cosmicpenguin.net>
Message-ID: <2831fecf0812021023t647f0238s9d1fd72b58e920ca@mail.gmail.com>

On Tue, Dec 2, 2008 at 9:24 AM, Jordan Crouse <jordan at cosmicpenguin.net>wrote:

> Per request - a target to only download the source code packages in
> buildrom. <http://www.coreboot.org/mailman/listinfo/coreboot>


packages/kernel
packages/kexec-boot-loader
packages/roms
packages/unifdef
packages/wireless-tools

These didn't get the source target.  I'm not sure it makes sense for all of
them, but at least kernel needs it, I think.

Thanks,
Myles
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From jordan at cosmicpenguin.net  Tue Dec  2 19:26:52 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Tue, 02 Dec 2008 11:26:52 -0700
Subject: [coreboot] [PATCH] buildrom: add 'source' target
In-Reply-To: <2831fecf0812021023t647f0238s9d1fd72b58e920ca@mail.gmail.com>
References: <49356145.2060306@cosmicpenguin.net>
	<2831fecf0812021023t647f0238s9d1fd72b58e920ca@mail.gmail.com>
Message-ID: <49357DEC.8090608@cosmicpenguin.net>

Myles Watson wrote:
> On Tue, Dec 2, 2008 at 9:24 AM, Jordan Crouse <jordan at cosmicpenguin.net>wrote:
> 
>> Per request - a target to only download the source code packages in
>> buildrom. <http://www.coreboot.org/mailman/listinfo/coreboot>
> 
> 
> packages/kernel
> packages/kexec-boot-loader
> packages/roms
> packages/unifdef
> packages/wireless-tools
> 
> These didn't get the source target.  I'm not sure it makes sense for all of
> them, but at least kernel needs it, I think.

Grumble - unifdef, wireless-tools and kexec-boot-loader didn't make it 
into the patch (stupid quilt - be less smart!).   I'm not sure why I 
didn't do kernel -probably because it was more extensive then I wanted 
to do at the time.  Thanks for the check, and the patch is withdrawn 
until I do a better job of it.

Jordan




From mylesgw at gmail.com  Tue Dec  2 19:30:59 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 11:30:59 -0700
Subject: [coreboot] [PATCH] coreboot-v3: Default to qemu
In-Reply-To: <4935661F.7030801@cosmicpenguin.net>
References: <4935661F.7030801@cosmicpenguin.net>
Message-ID: <2831fecf0812021030i60338cadjdc45b21a8ab2cc2c@mail.gmail.com>

On Tue, Dec 2, 2008 at 9:45 AM, Jordan Crouse <jordan at cosmicpenguin.net>wrote:

> If no .config exists, then default to qemu for defconfig targets.  As a
> further extension, I think we should consider allowing the user to pass the
> desired mainboard via an environment variable:
>
> make MAINBOARD=amd/db800 defconfig


I think we already do that.  Here's the snippet from  buildrom's
packages/coreboot-v3/coreboot-v3.mk.

    @ make -C $(CBV3_SRC_DIR) defconfig \
        MAINBOARDDIR="$(COREBOOT_VENDOR)/$(CBV3_BOARD)" \
        > $(CBV3_CONFIG_LOG) 2>&1

Am I misunderstanding what you want to do?  Did we used to allow that and
it's broken since then?

Thanks,
Myles
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From jordan at cosmicpenguin.net  Tue Dec  2 19:34:49 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Tue, 02 Dec 2008 11:34:49 -0700
Subject: [coreboot] [PATCH] coreboot-v3: Default to qemu
In-Reply-To: <2831fecf0812021030i60338cadjdc45b21a8ab2cc2c@mail.gmail.com>
References: <4935661F.7030801@cosmicpenguin.net>
	<2831fecf0812021030i60338cadjdc45b21a8ab2cc2c@mail.gmail.com>
Message-ID: <49357FC9.5010908@cosmicpenguin.net>

Myles Watson wrote:
> On Tue, Dec 2, 2008 at 9:45 AM, Jordan Crouse <jordan at cosmicpenguin.net>wrote:
> 
>> If no .config exists, then default to qemu for defconfig targets.  As a
>> further extension, I think we should consider allowing the user to pass the
>> desired mainboard via an environment variable:
>>
>> make MAINBOARD=amd/db800 defconfig
> 
> 
> I think we already do that.  Here's the snippet from  buildrom's
> packages/coreboot-v3/coreboot-v3.mk.
> 
>     @ make -C $(CBV3_SRC_DIR) defconfig \
>         MAINBOARDDIR="$(COREBOOT_VENDOR)/$(CBV3_BOARD)" \
>         > $(CBV3_CONFIG_LOG) 2>&1
> 
> Am I misunderstanding what you want to do?  Did we used to allow that and
> it's broken since then?

No, it still works.  I guess thats fine - MAINBOARDDIR is slightly 
unintuitive but we can deal.

Jordan



From marcj303 at gmail.com  Tue Dec  2 19:44:13 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 2 Dec 2008 11:44:13 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <BE6EF501005248F69CAB0169816A73D0@chimp>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
Message-ID: <534e5dc20812021044m3ba6985bj6fbc5ae1a44bf751@mail.gmail.com>

On Tue, Dec 2, 2008 at 6:57 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
>
>> -----Original Message-----
>> From: Marc Jones [mailto:marcj303 at gmail.com]
>> Sent: Monday, December 01, 2008 10:42 PM
>> To: Myles Watson
>> Cc: Coreboot
>> Subject: Re: [coreboot] Resource Allocation discussion
>>
>> Hi Myles,
>> I will try to help..... :)
>>
>> On Mon, Dec 1, 2008 at 2:37 PM, Myles Watson <mylesgw at gmail.com> wrote:
>> > The resource patches I submitted work fairly well, but still need a
>> little
>> > help.
>> >
>> > I haven't touched subtractively decoded resources, and that's where the
>> > breakage is right now.
>> >
>> > Questions:
>> > - Who should have a resource that moves all other IO resources above
>> 0x400
>> > or 0x1000?
>>
>> What do you mean? By definition the subtractive port takes all
>> unclaimed cycles. There should be a LPC or ISA bridge in the
>> southbridge that forwards cycles that the legacy southbridge devices
>> don't claim.
>
> Sorry.  I wasn't clear enough again.  What I meant was something more like:
>
> Since the resource allocation algorithm can't avoid resources that it
> doesn't know about, who decides if the subtractive area to avoid is
> 0x0-0x400, 0x0-0x1000, or some other range?  If I declare some device to
> hold these addresses so that no other resource ends up there, should it be
> subtractive?  I'm inclined to put it in the domain or in the SuperIO.

I think it belongs in the southbridge lpc/isa device which is in the
domain. It should be 0x0-0x1000.

Marc



From mylesgw at gmail.com  Tue Dec  2 19:48:17 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 11:48:17 -0700
Subject: [coreboot] [PATCH] coreboot-v3: Default to qemu
In-Reply-To: <49357FC9.5010908@cosmicpenguin.net>
References: <4935661F.7030801@cosmicpenguin.net>
	<2831fecf0812021030i60338cadjdc45b21a8ab2cc2c@mail.gmail.com>
	<49357FC9.5010908@cosmicpenguin.net>
Message-ID: <2831fecf0812021048p7aabd02bpde6a0f9510548ff9@mail.gmail.com>

On Tue, Dec 2, 2008 at 11:34 AM, Jordan Crouse <jordan at cosmicpenguin.net>wrote:

> Myles Watson wrote:
>
>> On Tue, Dec 2, 2008 at 9:45 AM, Jordan Crouse <jordan at cosmicpenguin.net
>> >wrote:
>>
>>  If no .config exists, then default to qemu for defconfig targets.  As a
>>> further extension, I think we should consider allowing the user to pass
>>> the
>>> desired mainboard via an environment variable:
>>>
>>> make MAINBOARD=amd/db800 defconfig
>>>
>>
>>
>> I think we already do that.  Here's the snippet from  buildrom's
>> packages/coreboot-v3/coreboot-v3.mk.
>>
>>    @ make -C $(CBV3_SRC_DIR) defconfig \
>>        MAINBOARDDIR="$(COREBOOT_VENDOR)/$(CBV3_BOARD)" \
>>        > $(CBV3_CONFIG_LOG) 2>&1
>>
>> Am I misunderstanding what you want to do?  Did we used to allow that and
>> it's broken since then?
>>
>
> No, it still works.  I guess thats fine - MAINBOARDDIR is slightly
> unintuitive but we can deal.


I guess we could add a MAINBOARD that gets copied into MAINBOARDDIR, or
change all MAINBOARDDIR to MAINBOARD.  I think that's a pretty trivial
change if it only has to change in the Makefile.

Your patch:
Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From marcj303 at gmail.com  Tue Dec  2 19:59:39 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 2 Dec 2008 11:59:39 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
Message-ID: <534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>

On Tue, Dec 2, 2008 at 11:06 AM, Myles Watson <mylesgw at gmail.com> wrote:
> Here's the read_resources code from qemu after my latest patch.  Is this
> what people are thinking?  Notice that I explicitly allocate VGA space and
> APIC.  At the end of the code I'm pasting in a snippet of the log that shows
> the resources after they are assigned values.

I think I like this. It makes sense to me. The legacy VGA space nadd
the legacy IO space should be reserved in the southbridge as you have
done. The IOAPIC address should be held by the southbridge since that
is where it is a located. The LAPIC should probably be in the
CPU/northbridge device.

It would be handy to show the fixed resources in the output.

>
> Show resources in subtree (root)...After assigning values.
>  Root Device links 1 child on link 0 cpus
>  Root Device resource base 1000 size 410 align 8 gran 0 limit ffff flags
> 80100 index 0

Coreboot allocates IO from the bottom (0x1000) up? I think it should
allocate top down as it does with memory. I think that the rule is
that the BIOS allocates top down and the OS allocates bottom up.

Marc



-- 
http://marcjstuff.blogspot.com/



From jordan at cosmicpenguin.net  Tue Dec  2 20:00:28 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Tue, 02 Dec 2008 12:00:28 -0700
Subject: [coreboot] Request for comments: v3 config script
Message-ID: <493585CC.9090305@cosmicpenguin.net>

We have had a configuration problem smoldering for some time in 
buildrom.  Basically, the problem is that we sometimes want buildrom to 
have some sort of control over the configuration of coreboot v2 and v3. 
The classic example is compression - buildrom allows the user to choose 
if they want to compress with LZMA or not - the problem is that this 
then needs to be communicated to coreboot v2 or v3, which is difficult 
to do with static configuration files.  So we need a way to massage the 
v2 and v3 configuration files based on information from buildrom.

Attached is a quick script that I wrote this morning that starts to go 
down that path for v3.  Given a trigger item in the buildrom config (in 
this case CONFIG_USE_LZMA), it adds the appropriate config options to 
the v3 config which is piped in through stdin. The result is a fully 
operational config file that can be run through oldconfig in the v3 build.

I'm sending this out for comments - clearly this is an early hack, and 
there will be refinements made.  And v3 is the easy case - v2 is going 
to be a bear, and unfortunately v2 is the system that needs this the most.

So comments welcome, and please excuse my lack of perl fu.

Jordan

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From mylesgw at gmail.com  Tue Dec  2 20:03:52 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 12:03:52 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <534e5dc20812021044m3ba6985bj6fbc5ae1a44bf751@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<534e5dc20812021044m3ba6985bj6fbc5ae1a44bf751@mail.gmail.com>
Message-ID: <2831fecf0812021103s530a0c97v1015536c467880e1@mail.gmail.com>

On Tue, Dec 2, 2008 at 11:44 AM, Marc Jones <marcj303 at gmail.com> wrote:

> On Tue, Dec 2, 2008 at 6:57 AM, Myles Watson <mylesgw at gmail.com> wrote:
> >
> >
> >> -----Original Message-----
> >> From: Marc Jones [mailto:marcj303 at gmail.com]
> >> Sent: Monday, December 01, 2008 10:42 PM
> >> To: Myles Watson
> >> Cc: Coreboot
> >> Subject: Re: [coreboot] Resource Allocation discussion
> >>
> >> Hi Myles,
> >> I will try to help..... :)
> >>
> >> On Mon, Dec 1, 2008 at 2:37 PM, Myles Watson <mylesgw at gmail.com> wrote:
> >> > The resource patches I submitted work fairly well, but still need a
> >> little
> >> > help.
> >> >
> >> > I haven't touched subtractively decoded resources, and that's where
> the
> >> > breakage is right now.
> >> >
> >> > Questions:
> >> > - Who should have a resource that moves all other IO resources above
> >> 0x400
> >> > or 0x1000?
> >>
> >> What do you mean? By definition the subtractive port takes all
> >> unclaimed cycles. There should be a LPC or ISA bridge in the
> >> southbridge that forwards cycles that the legacy southbridge devices
> >> don't claim.
> >
> > Sorry.  I wasn't clear enough again.  What I meant was something more
> like:
> >
> > Since the resource allocation algorithm can't avoid resources that it
> > doesn't know about, who decides if the subtractive area to avoid is
> > 0x0-0x400, 0x0-0x1000, or some other range?  If I declare some device to
> > hold these addresses so that no other resource ends up there, should it
> be
> > subtractive?  I'm inclined to put it in the domain or in the SuperIO.
>
> I think it belongs in the southbridge lpc/isa device which is in the
> domain. It should be 0x0-0x1000.


So like this? For qemu:

static void i82371eb_isa_read_resources(struct device *dev)
{
    struct resource *res;
    res = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
    res->base = 0x0UL;
    res->size = 0x1000UL;
    res->limit = 0xFFFUL;
    res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
             IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}

static void i82371eb_isa_set_resources(struct device *dev)
{
    struct resource *res;
    res = probe_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
    res->flags |= IORESOURCE_STORED;
    pci_set_resources(dev);
}

Thanks for the help.

Myles
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From mylesgw at gmail.com  Tue Dec  2 20:09:09 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 12:09:09 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<534e5dc20812012142q3c11dfbcr61ad71feaa772074@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
Message-ID: <2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>

On Tue, Dec 2, 2008 at 11:59 AM, Marc Jones <marcj303 at gmail.com> wrote:

> On Tue, Dec 2, 2008 at 11:06 AM, Myles Watson <mylesgw at gmail.com> wrote:
> > Here's the read_resources code from qemu after my latest patch.  Is this
> > what people are thinking?  Notice that I explicitly allocate VGA space
> and
> > APIC.  At the end of the code I'm pasting in a snippet of the log that
> shows
> > the resources after they are assigned values.
>
> I think I like this. It makes sense to me. The legacy VGA space nadd
> the legacy IO space should be reserved in the southbridge as you have
> done.

I actually think I just bumped up the base in the northbridge this time
around.


> The IOAPIC address should be held by the southbridge since that
> is where it is a located.

OK.

The LAPIC should probably be in the
> CPU/northbridge device.

So I got this one right?  No I put it in the domain.


>
> It would be handy to show the fixed resources in the output.


Because of a typo the two APIC reservations clobbered each other, so only
one is there.  The rest of the fixed allocations should be there.

>
> > Show resources in subtree (root)...After assigning values.
> >  Root Device links 1 child on link 0 cpus
> >  Root Device resource base 1000 size 410 align 8 gran 0 limit ffff flags
> > 80100 index 0
>
> Coreboot allocates IO from the bottom (0x1000) up?

Yes.


> I think it should
> allocate top down as it does with memory. I think that the rule is
> that the BIOS allocates top down and the OS allocates bottom up.


I don't think that would match v2 or the factory BIOS for serengeti or
qemu.  Is there a packing reason?

Thanks,
Myles
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From mylesgw at gmail.com  Tue Dec  2 20:33:50 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 12:33:50 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
Message-ID: <2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>

On Tue, Dec 2, 2008 at 12:09 PM, Myles Watson <mylesgw at gmail.com> wrote:

>
>
> On Tue, Dec 2, 2008 at 11:59 AM, Marc Jones <marcj303 at gmail.com> wrote:
>
>> On Tue, Dec 2, 2008 at 11:06 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> > Here's the read_resources code from qemu after my latest patch.  Is this
>> > what people are thinking?  Notice that I explicitly allocate VGA space
>> and
>> > APIC.  At the end of the code I'm pasting in a snippet of the log that
>> shows
>> > the resources after they are assigned values.
>>
>> I think I like this. It makes sense to me. The legacy VGA space nadd
>> the legacy IO space should be reserved in the southbridge as you have
>> done.
>
> I actually think I just bumped up the base in the northbridge this time
> around.
>

All right.  If I do this then I can't ignore fixed resources in the
allocation algorithm anymore.  It still works right now because 0-0xfff is
the largest resource, so it gets allocated first.  I think it would break if
you tried to allocate an IO resource larger than that.

Do we want to take fixed resources into account in the allocator?

Thanks,
Myles
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From mylesgw at gmail.com  Tue Dec  2 20:45:03 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 12:45:03 -0700
Subject: [coreboot] Request for comments: v3 config script
In-Reply-To: <493585CC.9090305@cosmicpenguin.net>
References: <493585CC.9090305@cosmicpenguin.net>
Message-ID: <551A71DFAEA047CFBEE7481529F8301E@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Jordan Crouse
> Sent: Tuesday, December 02, 2008 12:00 PM
> To: coreboot at coreboot.org
> Subject: [coreboot] Request for comments: v3 config script
> 
> We have had a configuration problem smoldering for some time in
> buildrom.  Basically, the problem is that we sometimes want buildrom to
> have some sort of control over the configuration of coreboot v2 and v3.
> The classic example is compression - buildrom allows the user to choose
> if they want to compress with LZMA or not - the problem is that this
> then needs to be communicated to coreboot v2 or v3, which is difficult
> to do with static configuration files.  So we need a way to massage the
> v2 and v3 configuration files based on information from buildrom.

The last time we looked at this, I thought we decided that we would just
have a "reasonable" default for v3, and not let the user configure it any
more than that.  So in defconfig we always enable LZMA.  This allows the
user to compress the payload or not.  The other thing we allowed the user to
change was ROM size.  Anything else they need to do a make
coreboot-v3-config.

I think that's still reasonable for v3.  What other things do we want
configurable directly from buildrom?
 
> Attached is a quick script that I wrote this morning that starts to go
> down that path for v3.  Given a trigger item in the buildrom config (in
> this case CONFIG_USE_LZMA), it adds the appropriate config options to
> the v3 config which is piped in through stdin. The result is a fully
> operational config file that can be run through oldconfig in the v3 build.
> 
> I'm sending this out for comments - clearly this is an early hack, and
> there will be refinements made.  And v3 is the easy case - v2 is going
> to be a bear, and unfortunately v2 is the system that needs this the most.

I agree that v2 is the real needy one here.  I think this might be overkill
for v3.

Thanks,
Myles




From mylesgw at gmail.com  Tue Dec  2 21:40:36 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 13:40:36 -0700
Subject: [coreboot] add 2 k8 devs
In-Reply-To: <2831fecf0812011315t79bd3621v1258f50e50025341@mail.gmail.com>
References: <2831fecf0812011238n7c95745dpac20fbcbfebb1918@mail.gmail.com>
	<13426df10812011252q12537213t90121e60a615cd3e@mail.gmail.com>
	<2831fecf0812011315t79bd3621v1258f50e50025341@mail.gmail.com>
Message-ID: <2831fecf0812021240j25caf7d7q6bb93a0ea3e0f54d@mail.gmail.com>

On Mon, Dec 1, 2008 at 2:15 PM, Myles Watson <mylesgw at gmail.com> wrote:

>
>
> On Mon, Dec 1, 2008 at 1:52 PM, ron minnich <rminnich at gmail.com> wrote:
>
>> did you need to do an svn add for the device code?
>
>
> I don't think so.  They were already there.
>
I guess they were only there in my tree :)

Sorry about that.  New patch attached.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From chris at stockwith.co.uk  Tue Dec  2 21:58:22 2008
From: chris at stockwith.co.uk (Chris Lingard)
Date: Tue, 02 Dec 2008 20:58:22 +0000
Subject: [coreboot] Free chips, not required by me, and a question
In-Reply-To: <49352776.3090909@gmx.net>
References: <493111FB.9000701@stockwith.co.uk>	<4931E92C.1020807@gmx.net>	<4933BF09.7080501@stockwith.co.uk>	<493111FB.9000701@stockwith.co.uk>	<20081202120058.12204.qmail@stuge.se>
	<49352776.3090909@gmx.net>
Message-ID: <4935A16E.8030409@stockwith.co.uk>

Carl-Daniel Hailfinger wrote:
> On 02.12.2008 13:00, Peter Stuge wrote:
>> Hi Chris,

> 
> You can also stack up to 16 of the 16 Mbit chips on top of each other,
> switching betwee them with the ID[0..3] lines. Depending on how your
> mainboard is wired up, you won't even need additional circuitry. And 256
> Mbit should be enough for you.
> 
> 
> Regards,
> Carl-Daniel
> 

LOL, yes that would be great.

I have ordered some SST49LF160 chips, so will settle for 16Mbit. I 
should be able to get a kernel into it.  Many thanks for all your help.

Chris





From rminnich at gmail.com  Tue Dec  2 22:37:36 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 2 Dec 2008 13:37:36 -0800
Subject: [coreboot] add 2 k8 devs
In-Reply-To: <2831fecf0812021240j25caf7d7q6bb93a0ea3e0f54d@mail.gmail.com>
References: <2831fecf0812011238n7c95745dpac20fbcbfebb1918@mail.gmail.com>
	<13426df10812011252q12537213t90121e60a615cd3e@mail.gmail.com>
	<2831fecf0812011315t79bd3621v1258f50e50025341@mail.gmail.com>
	<2831fecf0812021240j25caf7d7q6bb93a0ea3e0f54d@mail.gmail.com>
Message-ID: <13426df10812021337r3653eef9xdf8089ff1fd9e2e@mail.gmail.com>

I think you can remove all the stuff in the #if 0, we don't care about
pre-c0 and pre-d0 on v3.

apeture -> aperture
reousce or some such -> resource

There are a few mispellings which we can fix later.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

ron



From rminnich at gmail.com  Tue Dec  2 22:51:21 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 2 Dec 2008 13:51:21 -0800
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
	<2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
Message-ID: <13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>

On Tue, Dec 2, 2008 at 11:33 AM, Myles Watson <mylesgw at gmail.com> wrote:

> Do we want to take fixed resources into account in the allocator?

I would think so.

ron



From mylesgw at gmail.com  Tue Dec  2 23:23:17 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 2 Dec 2008 15:23:17 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
	<2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
	<13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>
Message-ID: <7872596BBD834D33A5FAF4A70E79BE0F@chimp>



> -----Original Message-----
> From: ron minnich [mailto:rminnich at gmail.com]
> Sent: Tuesday, December 02, 2008 2:51 PM
> To: Myles Watson
> Cc: Marc Jones; Rudolf Marek; Coreboot
> Subject: Re: [coreboot] Resource Allocation discussion
> 
> On Tue, Dec 2, 2008 at 11:33 AM, Myles Watson <mylesgw at gmail.com> wrote:
> 
> > Do we want to take fixed resources into account in the allocator?
> 
> I would think so.

I would too, but v2 didn't and did pretty well.  I'm interested to see an
idea for the resource allocation algorithm that allocates from largest to
smallest resource, except when it's skipping fixed resources.

I think it's doable, but nothing like what we have.

Thanks,
Myles




From svn at coreboot.org  Wed Dec  3 00:59:14 2008
From: svn at coreboot.org (coreboot)
Date: Tue, 02 Dec 2008 23:59:14 -0000
Subject: [coreboot] #104: flashrom: Change flash drivers to never erase
 data before writing
In-Reply-To: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
References: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
Message-ID: <050.b3fea22b7e01ab245d1cd2ad7e4010f5@coreboot.org>

#104: flashrom: Change flash drivers to never erase data before writing
---------------------------------+------------------------------------------
   Reporter:  stuge              |          Owner:  somebody     
       Type:  defect             |         Status:  new          
   Priority:  major              |      Milestone:  flashrom v1.0
  Component:  flashrom           |        Version:               
   Keywords:  erase write        |   Dependencies:  #103         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------

Comment(by stuge):

 Maybe the original comment was overzealous, and the decision to erase
 should not be moved all the way out to the user - but I think it should at
 least be moved out of the write functions in drivers, and instead be
 handled by flashrom common code.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:5>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Wed Dec  3 01:36:53 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 03 Dec 2008 00:36:53 -0000
Subject: [coreboot] #104: flashrom: Change flash drivers to never erase
 data before writing
In-Reply-To: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
References: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
Message-ID: <050.6c6e32ee1a21388693912e957e24ac14@coreboot.org>

#104: flashrom: Change flash drivers to never erase data before writing
---------------------------------+------------------------------------------
   Reporter:  stuge              |          Owner:  somebody     
       Type:  defect             |         Status:  new          
   Priority:  major              |      Milestone:  flashrom v1.0
  Component:  flashrom           |        Version:               
   Keywords:  erase write        |   Dependencies:  #103         
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------

Comment(by hailfinger):

 Stefan's comments about printing a warning if to-be-written areas are not
 0xff is valid. Same about erroring out if any bit being 0 would be set to
 1 by the write (which is impossible).

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:6>
coreboot <http://www.coreboot.org/>


From stephan.guilloux at free.fr  Wed Dec  3 02:04:27 2008
From: stephan.guilloux at free.fr (Stephan GUILLOUX)
Date: Wed, 03 Dec 2008 02:04:27 +0100
Subject: [coreboot] [PATCH] flashrom patch for partial flash read #2
Message-ID: <4935DB1B.6070803@free.fr>

Second try for this patch, after some review/comments on #coreboot channel.
- renamed generic_read() to read_flash()
- renamed options chunk_start/size to offset/length
- fixed some indentation spaces
- fixed some error messages
- replaces chk_start/size by offset/length
- added a description in the usage()

The goal for this patch is to allow flashrom to read some part of the flash,
described by a pair offset/length.
Added flashrom arguments --offset (-S) and --length (-N).
The result is stored in a <length>-size file.

The design intends to provide offset and length arguments to the 
xxx_read functions,
so that each can read only <length> bytes from <offset>.
Actually, for the READ part, there are still 2 or 3 functions to modify.
If this design is agreed, I'll modify the others too.

The same kind of design could be used for the VERIFY (easy), ERASE and 
WRITE (more
difficult) parts too.

Also in attachment for GMail users.

Any comment is welcome.

   Stephan.

Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux at free.fr>

Index: flashrom/flash.h
===================================================================
--- flashrom/flash.h    (r?vision 3789)
+++ flashrom/flash.h    (copie de travail)
@@ -74,7 +74,7 @@
     int (*probe) (struct flashchip *flash);
     int (*erase) (struct flashchip *flash);
     int (*write) (struct flashchip *flash, uint8_t *buf);
-    int (*read) (struct flashchip *flash, uint8_t *buf);
+    int (*read) (struct flashchip *flash, uint8_t *buf, uint32_t start, 
uint32_t size);
 
     /* Some flash devices have an additional register space. */
     volatile uint8_t *virtual_memory;
@@ -464,7 +464,7 @@
 int spi_block_erase_52(const struct flashchip *flash, unsigned long addr);
 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr);
 int spi_chip_write(struct flashchip *flash, uint8_t *buf);
-int spi_chip_read(struct flashchip *flash, uint8_t *buf);
+int spi_chip_read(struct flashchip *flash, uint8_t *buf, uint32_t 
start, uint32_t size);
 uint8_t spi_read_status_register();
 int spi_disable_blockprotect(void);
 void spi_byte_program(int address, uint8_t byte);
@@ -488,7 +488,7 @@
 /* ichspi.c */
 int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
             const unsigned char *writearr, unsigned char *readarr);
-int ich_spi_read(struct flashchip *flash, uint8_t * buf);
+int ich_spi_read(struct flashchip *flash, uint8_t * buf, uint32_t 
start, uint32_t size);
 int ich_spi_write(struct flashchip *flash, uint8_t * buf);
 
 /* it87spi.c */
Index: flashrom/spi.c
===================================================================
--- flashrom/spi.c    (r?vision 3789)
+++ flashrom/spi.c    (copie de travail)
@@ -544,21 +544,29 @@
     return spi_command(sizeof(cmd), len, cmd, bytes);
 }
 
-int spi_chip_read(struct flashchip *flash, uint8_t *buf)
+int spi_chip_read(struct flashchip *flash, uint8_t *buf, uint32_t 
offset, uint32_t length)
 {
+    unsigned int total_size = flash->total_size * 1024;
+
     switch (flashbus) {
     case BUS_TYPE_IT87XX_SPI:
+        if ((offset != 0) || (length != total_size)) {
+            printf ("Error: offset/lenght options not supported on ITE 
87xx SPI bus masters.\n");
+            return (1);
+        }
         return it8716f_spi_chip_read(flash, buf);
     case BUS_TYPE_SB600_SPI:
+        if ((offset != 0) || (length != total_size)) {
+            printf ("Error: offset/lenght options not supported on SB 
600 SPI bus masters.\n");
+            return (1);
+        }
         return sb600_spi_read(flash, buf);
     case BUS_TYPE_ICH7_SPI:
     case BUS_TYPE_ICH9_SPI:
     case BUS_TYPE_VIA_SPI:
-        return ich_spi_read(flash, buf);
+        return ich_spi_read(flash, buf, offset, length);
     default:
-        printf_debug
-            ("%s called, but no SPI chipset/strapping detected\n",
-             __FUNCTION__);
+        printf_debug ("%s called, but no SPI chipset/strapping 
detected\n", __FUNCTION__);
     }
 
     return 1;
Index: flashrom/flashrom.c
===================================================================
--- flashrom/flashrom.c    (r?vision 3789)
+++ flashrom/flashrom.c    (copie de travail)
@@ -46,6 +46,8 @@
 int verbose = 0;
 int fd_mem;
 
+#define UNKNOWN_LENGTH    0xffffffff
+
 struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device)
 {
     struct pci_dev *temp;
@@ -171,15 +173,41 @@
     return flash;
 }
 
+static int read_flash(struct flashchip *flash, uint8_t *buf, uint32_t 
offset, uint32_t length)
+{
+    int total_size = flash->total_size * 1024;
+
+    if (offset >= total_size) {
+        printf ("Error: Invalid start address.\n");
+        return (1);
+    }
+
+    if ((length == 0) || (offset + length > total_size)) {
+        printf ("Error: Invalid size.\n");
+        return (1);
+    }
+
+    if (flash->read == NULL) {
+        memcpy(buf, (const char *)flash->virtual_memory + offset, length);
+    } else {
+        if (flash->read(flash, buf, offset, length)) {
+            printf ("ERROR : flash read failed\n");
+            return (1);
+        }
+    }
+    return (0);
+}
+
 int verify_flash(struct flashchip *flash, uint8_t *buf)
 {
     int idx;
     int total_size = flash->total_size * 1024;
     uint8_t *buf2 = (uint8_t *) calloc(total_size, sizeof(char));
-    if (flash->read == NULL)
-        memcpy(buf2, (const char *)flash->virtual_memory, total_size);
-    else
-        flash->read(flash, buf2);
+   
+    if (read_flash(flash, buf2, 0, total_size)) {
+        printf ("ERROR : verification aborted.\n");
+        return (1);
+    }
 
     printf("Verifying flash... ");
 
@@ -224,7 +252,8 @@
 {
     printf("usage: %s [-rwvEVfLhR] [-c chipname] [-s exclude_start]\n",
            name);
-    printf("       [-e exclude_end] [-m [vendor:]part] [-l file.layout] 
[-i imagename] [file]\n");
+    printf("       [-e exclude_end] [-m [vendor:]part] [-l file.layout] 
[-i imagename]\n");
+    printf("       [-S offs] [-N length] [file]\n");
     printf
         ("   -r | --read:                      read flash and save into 
file\n"
          "   -w | --write:                     write file into flash\n"
@@ -241,6 +270,8 @@
          "   -L | --list-supported:            print supported devices\n"
          "   -h | --help:                      print this help text\n"
          "   -R | --version:                   print the version 
(release)\n"
+         "   -S | --offset <offs>:             start address\n"
+         "   -N | --length <length>:           number of bytes to 
process (READ)\n"
          "\n" " If no file is specified, then all that happens"
          " is that flash info is dumped.\n\n");
     exit(1);
@@ -280,6 +311,8 @@
         {"force", 0, 0, 'f'},
         {"layout", 1, 0, 'l'},
         {"image", 1, 0, 'i'},
+        {"offset", 1, 0, 'S'},
+        {"length", 1, 0, 'N'},
         {"list-supported", 0, 0, 'L'},
         {"help", 0, 0, 'h'},
         {"version", 0, 0, 'R'},
@@ -288,6 +321,8 @@
 
     char *filename = NULL;
 
+    unsigned int offset = 0;
+    unsigned int length = UNKNOWN_LENGTH;
     unsigned int exclude_start_position = 0, exclude_end_position = 
0;    // [x,y)
     char *tempstr = NULL, *tempstr2 = NULL;
 
@@ -329,6 +364,12 @@
             tempstr = strdup(optarg);
             sscanf(tempstr, "%x", &exclude_end_position);
             break;
+        case 'S':
+            sscanf(optarg, "%x", &offset);
+            break;
+        case 'N':
+            sscanf(optarg, "%x", &length);
+            break;
         case 'm':
             tempstr = strdup(optarg);
             strtok(tempstr, ":");
@@ -463,18 +504,22 @@
                 perror(filename);
                 exit(1);
             }
+
+            if (length == UNKNOWN_LENGTH)
+                length = size - offset;
+
             printf("Force reading flash... ");
-            if (!flashes[0]->read)
-                memcpy(buf, (const char *)flashes[0]->virtual_memory, 
size);
-            else
-                flashes[0]->read(flashes[0], buf);
+            if (read_flash(flashes[0], buf + offset, offset, length)) {
+                fclose(image);
+                exit (1);
+            }
 
             if (exclude_end_position - exclude_start_position > 0)
                 memset(buf + exclude_start_position, 0,
                        exclude_end_position -
                        exclude_start_position);
 
-            fwrite(buf, sizeof(char), size, image);
+            fwrite(buf + offset, sizeof(char), length, image);
             fclose(image);
             printf("done.\n");
             free(buf);
@@ -546,21 +591,25 @@
         printf("done.\n");
         exit(0);
     } else if (read_it) {
+        printf("Reading flash... ");
         if ((image = fopen(filename, "w")) == NULL) {
             perror(filename);
             exit(1);
         }
-        printf("Reading flash... ");
-        if (flash->read == NULL)
-            memcpy(buf, (const char *)flash->virtual_memory, size);
-        else
-            flash->read(flash, buf);
 
+        if (length == UNKNOWN_LENGTH)
+            length = size - offset;
+
+        if (read_flash(flash, buf + offset, offset, length)) {
+            fclose(image);
+            exit(1);
+        }
+
         if (exclude_end_position - exclude_start_position > 0)
             memset(buf + exclude_start_position, 0,
                    exclude_end_position - exclude_start_position);
 
-        fwrite(buf, sizeof(char), size, image);
+        fwrite(buf + offset, sizeof(char), length, image);
         fclose(image);
         printf("done.\n");
     } else {
Index: flashrom/ichspi.c
===================================================================
--- flashrom/ichspi.c    (r?vision 3789)
+++ flashrom/ichspi.c    (copie de travail)
@@ -545,18 +545,26 @@
     return 0;
 }
 
-int ich_spi_read(struct flashchip *flash, uint8_t * buf)
+int ich_spi_read(struct flashchip *flash, uint8_t * buf, uint32_t 
offset, uint32_t length)
 {
     int i, rc = 0;
-    int total_size = flash->total_size * 1024;
     int page_size = flash->page_size;
     int maxdata = 64;
+    int page_start;
+    int page_nbr;
 
+    if ((offset % page_size) || (length % page_size)) {
+        printf ("Error: offset/length must be page aligned (page=%d 
bytes).\n", page_size);
+        return (1);
+    }
+    page_start = offset / page_size;
+    page_nbr = length / page_size;
+
     if (flashbus == BUS_TYPE_VIA_SPI) {
         maxdata = 16;
     }
 
-    for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
+    for (i = page_start; (i < page_start + page_nbr) && (rc == 0); i++) {
         rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
                        i * page_size, maxdata);
     }

-------------- next part --------------
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From c-d.hailfinger.devel.2006 at gmx.net  Wed Dec  3 02:40:54 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Dec 2008 02:40:54 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
Message-ID: <4935E3A6.5060200@gmx.net>

LAR currently overwrites the top 13 bytes (0xfffff3-0xffffff) of the
bootblock with zeros, then it stores the ROM size in 0xfffff4-0xfffff7.
The top 8 bytes are unused in that scheme.
Leave the top 8 bytes as they are and allow us to store something in
there during the bootblock build process. The byte at 0xfffff3 is 0xff
by default on x86 and setting it to 0 is not needed.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: corebootv3-lar_dont_erase_top_8_bytes/util/lar/stream.c
===================================================================
--- corebootv3-lar_dont_erase_top_8_bytes/util/lar/stream.c	(Revision 1061)
+++ corebootv3-lar_dont_erase_top_8_bytes/util/lar/stream.c	(Arbeitskopie)
@@ -245,8 +245,9 @@
 }
 
 /**
- * Add the LAR archive size to the bootblock, and clean up some other params
- * in what we're loosely calling the "bootblockh header"
+ * Add the LAR archive size to the bootblock at 0xfffffff4
+ * in what we're loosely calling the "bootblock header".
+ * Leave anything else alone.
  * @param ptr Pointer to the start of the bootblock
  * @param size The size value to write to the bootblock header
  */
@@ -255,7 +256,6 @@
 	int i;
 	u32 *p;
 
-	memset(ptr + (BOOTBLOCK_SIZE - 13), 0, 13);
 	p = (u32 *) (ptr + BOOTBLOCK_SIZE - 12);
 	p[0] = size;
 }


-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Wed Dec  3 02:52:18 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Dec 2008 02:52:18 +0100
Subject: [coreboot] [PATCH] flashrom patch for partial flash read #2
In-Reply-To: <4935DB1B.6070803@free.fr>
References: <4935DB1B.6070803@free.fr>
Message-ID: <4935E652.4000107@gmx.net>

On 03.12.2008 02:04, Stephan GUILLOUX wrote:
> Second try for this patch, after some review/comments on #coreboot
> channel.
> - renamed generic_read() to read_flash()
> - renamed options chunk_start/size to offset/length
> - fixed some indentation spaces
> - fixed some error messages
> - replaces chk_start/size by offset/length
> - added a description in the usage()
>
> The goal for this patch is to allow flashrom to read some part of the
> flash,
> described by a pair offset/length.
> Added flashrom arguments --offset (-S) and --length (-N).
> The result is stored in a <length>-size file.
>
> The design intends to provide offset and length arguments to the
> xxx_read functions,
> so that each can read only <length> bytes from <offset>.
> Actually, for the READ part, there are still 2 or 3 functions to modify.
> If this design is agreed, I'll modify the others too.
>
> The same kind of design could be used for the VERIFY (easy), ERASE and
> WRITE (more
> difficult) parts too.
>
> Also in attachment for GMail users.
>
> Any comment is welcome.
>
>   Stephan.
>
> Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux at free.fr>

Partial review follows.

> +static int read_flash(struct flashchip *flash, uint8_t *buf, uint32_t offset, uint32_t length)
> +{
> +	int total_size = flash->total_size * 1024;
>   

total_size should be unsigned.

> +
> +	if (offset >= total_size) {
> +		printf ("Error: Invalid start address.\n");
> +		return (1);
> +	}
>   

You have to check for length>= total_size as well.

> +
> +	if ((length == 0) || (offset + length > total_size)) {
>   

(offset + length > total_size) can overflow. This is not a
problem as long as flash chips are smaller than 2 GB and the
checks mentioned above are in place.


> +		printf ("Error: Invalid size.\n");
> +		return (1);
> +	}
> +
> +	if (flash->read == NULL) {
> +		memcpy(buf, (const char *)flash->virtual_memory + offset, length);
> +	} else {
> +		if (flash->read(flash, buf, offset, length)) {
> +			printf ("ERROR : flash read failed\n");
> +			return (1);
> +		}
> +	}
> +	return (0);
> +}
> +
>  int verify_flash(struct flashchip *flash, uint8_t *buf)
>  {
>  	int idx;
>  	int total_size = flash->total_size * 1024;
>  	uint8_t *buf2 = (uint8_t *) calloc(total_size, sizeof(char));
> -	if (flash->read == NULL)
> -		memcpy(buf2, (const char *)flash->virtual_memory, total_size);
> -	else
> -		flash->read(flash, buf2);
> +	
> +	if (read_flash(flash, buf2, 0, total_size)) {
> +		printf ("ERROR : verification aborted.\n");
>   

"ERROR : verification aborted because flash could not be read.\n"


> +		return (1);
> +	}
>  
>  	printf("Verifying flash... ");
>  
>   

I noticed you are using parentheses around return values. That's rather
uncommon in flashrom. Please avoid them if possible.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Wed Dec  3 03:14:30 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  3 Dec 2008 03:14:30 +0100
Subject: [coreboot] r1062 - coreboot-v3/arch/x86
Message-ID: <mailman.2534.1355071447.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-12-03 03:14:30 +0100 (Wed, 03 Dec 2008)
New Revision: 1062

Modified:
   coreboot-v3/arch/x86/Makefile
Log:
Fix a missing dependency on arch/x86/stage0_common.S (that's an included
file from all arch/x86/*/stage0.S).

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-11-27 01:01:16 UTC (rev 1061)
+++ coreboot-v3/arch/x86/Makefile	2008-12-03 02:14:30 UTC (rev 1062)
@@ -259,7 +259,7 @@
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 	
 # Building asm stub.
-$(obj)/arch/x86/%/stage0.o: $(src)/arch/x86/%/stage0.S
+$(obj)/arch/x86/%/stage0.o: $(src)/arch/x86/%/stage0.S $(src)/arch/x86/stage0_common.S
 	$(Q)mkdir -p $(dir $@)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \




From c-d.hailfinger.devel.2006 at gmx.net  Wed Dec  3 03:33:27 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Dec 2008 03:33:27 +0100
Subject: [coreboot] v3: VPD handling bogosity
Message-ID: <4935EFF7.2040708@gmx.net>

We have the following nice rule in arch/x86/Makefile

$(obj)/arch/x86/%/stage0.o: $(src)/arch/x86/%/stage0.S
$(src)/arch/x86/stage0_common.S
        $(Q)mkdir -p $(dir $@)
        $(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
        $(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
                -o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
                -DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
        $(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
        $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@

RESRVED is never used although arch/x86/stage0_common.S says it refers
to the area reserved for VPD.
However, we prepend the VPD to stage0.init without any linker magic. Are
there two different meanings of VPD?

Can someone please explain this?

Regards.
Carl-Daniel

-- 
http://www.hailfinger.org/




From marcj303 at gmail.com  Wed Dec  3 03:44:53 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 2 Dec 2008 19:44:53 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<BE6EF501005248F69CAB0169816A73D0@chimp>
	<493541E3.2090507@assembler.cz>
	<5C2C19EAB23942C399DBD0EE9B793104@chimp>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
Message-ID: <534e5dc20812021844w62f8874mb66b75c5df19f95c@mail.gmail.com>

On Tue, Dec 2, 2008 at 12:09 PM, Myles Watson <mylesgw at gmail.com> wrote:


>> Coreboot allocates IO from the bottom (0x1000) up?
>
> Yes.
>
>>
>> I think it should
>> allocate top down as it does with memory. I think that the rule is
>> that the BIOS allocates top down and the OS allocates bottom up.
>
> I don't think that would match v2 or the factory BIOS for serengeti or
> qemu.  Is there a packing reason?


No, It was a rule to stop device allocation from colliding between the
BIOS and OS The firmware is only required to setup boot devices and
the OS was expected to do the rest. I guess you can leave it since it
is working.

Marc



From marcj303 at gmail.com  Wed Dec  3 03:51:58 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 2 Dec 2008 19:51:58 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <7872596BBD834D33A5FAF4A70E79BE0F@chimp>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
	<2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
	<13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>
	<7872596BBD834D33A5FAF4A70E79BE0F@chimp>
Message-ID: <534e5dc20812021851n4fc902bdk1f6b342dad9c0086@mail.gmail.com>

On Tue, Dec 2, 2008 at 3:23 PM, Myles Watson <mylesgw at gmail.com> wrote:
>
>
>> -----Original Message-----
>> From: ron minnich [mailto:rminnich at gmail.com]
>> Sent: Tuesday, December 02, 2008 2:51 PM
>> To: Myles Watson
>> Cc: Marc Jones; Rudolf Marek; Coreboot
>> Subject: Re: [coreboot] Resource Allocation discussion
>>
>> On Tue, Dec 2, 2008 at 11:33 AM, Myles Watson <mylesgw at gmail.com> wrote:
>>
>> > Do we want to take fixed resources into account in the allocator?
>>
>> I would think so.
>
> I would too, but v2 didn't and did pretty well.  I'm interested to see an
> idea for the resource allocation algorithm that allocates from largest to
> smallest resource, except when it's skipping fixed resources.
>
> I think it's doable, but nothing like what we have.

That surprises me. I thought it does, which is how/why you can get rid
of DEVICE_MEM_HIGH. Otherwise you would clobber the ROM and the APIC.

And that brings up where to reserve the ROM space. In the southbridge
subtractive device code I guess?



Marc



From marcj303 at gmail.com  Wed Dec  3 04:05:55 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 2 Dec 2008 20:05:55 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>
	<49344EA4.9070208@cosmicpenguin.net>
	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
	<49347342.6080504@cosmicpenguin.net>
	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>
	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>
Message-ID: <534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>

On Tue, Dec 2, 2008 at 10:57 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
>
> On Tue, Dec 2, 2008 at 7:13 AM, Myles Watson <mylesgw at gmail.com> wrote:
>>
>> Jordan,
>>
>> Sorry I obviously missed the point of your questions.  I'd forgotten that
>> the fix went in to make all devices found in the dts be "on the mainboard."
>> Here's a new patch that updates the dts with that in mind.  It also fixes
>> the subsystem_vendor, which was broken in the last patch.
>>
>> I appreciate the sanity check.
>
> This patch is updated so that qemu works with resource allocation in phases.
> Here are the changes:
>
> 1. Add a dts for the northbridge so it can have its own ops.
> 2. Separates the domain from the device resource code.
> 3. Add new resources for the APIC and VGA area.

Move the IOAPIC to the the 82371? I'm not sure if the LAPIC belongs in
the northbridge on since every core needs one it might belong in the
CPU but I think you only need to reserve the range once.

On another note, Do you find the res-> size and res->limit redundant?
I can't think of how they could be different.

Marc



From peter at stuge.se  Wed Dec  3 04:19:18 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 3 Dec 2008 04:19:18 +0100
Subject: [coreboot] Request for comments: v3 config script
In-Reply-To: <551A71DFAEA047CFBEE7481529F8301E@chimp>
References: <493585CC.9090305@cosmicpenguin.net>
	<551A71DFAEA047CFBEE7481529F8301E@chimp>
Message-ID: <20081203031918.32139.qmail@stuge.se>

Myles Watson wrote:
> Anything else they need to do a make coreboot-v3-config.

Could a submenu in buildrom menuconfig bring up the v3 menuconfig?
Maybe with some Kconfig glue?

For v2, well, we're stuck using homemade config things but maybe a
very simple sh script is enough?


//Peter



From jordan at cosmicpenguin.net  Wed Dec  3 04:51:50 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Tue, 02 Dec 2008 20:51:50 -0700
Subject: [coreboot] Request for comments: v3 config script
In-Reply-To: <20081203031918.32139.qmail@stuge.se>
References: <493585CC.9090305@cosmicpenguin.net>	<551A71DFAEA047CFBEE7481529F8301E@chimp>
	<20081203031918.32139.qmail@stuge.se>
Message-ID: <49360256.90607@cosmicpenguin.net>

Peter Stuge wrote:
> Myles Watson wrote:
>> Anything else they need to do a make coreboot-v3-config.
> 
> Could a submenu in buildrom menuconfig bring up the v3 menuconfig?
> Maybe with some Kconfig glue?

Possibly - the interesting thing would be "sharing" config options 
between buildrom and coreboot-v3.

> For v2, well, we're stuck using homemade config things but maybe a
> very simple sh script is enough?

I think simple is a bit optimistic  - here is the diff between the 
standard Config.lb and the LZMA enabled one for one of the tyan boards. 
  If you think we could recreate this magic in a shell script, then lets 
go for it.

--- Config.lb	2008-11-06 11:47:54.000000000 -0700
+++ Config-lab.lb	2008-11-06 11:47:54.000000000 -0700
@@ -5,59 +5,19 @@
  target s2891
  mainboard tyan/s2891

-# Tyan s2891
-romimage "normal"
-#       36K for ATI ROM in 1M
-	option ROM_SIZE = 1024*1024-36*1024
-#       48K for SCSI FW
-#        option ROM_SIZE = 512*1024-48*1024
-#       48K for SCSI FW and 36K for ATI ROM
-#       option ROM_SIZE = 512*1024-48*1024-36*1024
-#       64K for Etherboot
-#        option ROM_SIZE = 512*1024-64*1024
-	option USE_FALLBACK_IMAGE=0
-#        option ROM_IMAGE_SIZE=0x11800
-#	option ROM_IMAGE_SIZE=0x13000
-#	option ROM_IMAGE_SIZE=0x16000
-	option ROM_IMAGE_SIZE=0x20000
-        option XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_com2.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_3.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
-end
+option ROM_SIZE=0x100000
+# 36K for ATI ROM in 1M
+option FALLBACK_SIZE=(ROM_SIZE-0x9000)

+# Tyan s2891
  romimage "fallback"
  	option USE_FALLBACK_IMAGE=1
-#        option ROM_IMAGE_SIZE=0x11800
-#	option ROM_IMAGE_SIZE=0x13000
-#	option ROM_IMAGE_SIZE=0x16000
-	option ROM_IMAGE_SIZE=0x20000
-        option XIP_ROM_SIZE=0x20000
+	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
+	option CONFIG_PRECOMPRESSED_PAYLOAD=1
+	option ROM_IMAGE_SIZE=0x17000
+	option XIP_ROM_SIZE=0x40000
  	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#       payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_com2.zelf
-#	payload ../../../payloads/tg3--filo_hda2_vga_5_3.zelf
-#       payload ../../../payloads/e1000--filo.zelf
-#	payload ../../../payloads/tg3--filo_btext_hda2.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-	payload ../payload.elf
+	payload ../payload.elf.lzma
  end

-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"



> 
> //Peter
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 




From ward at gnu.org  Wed Dec  3 05:22:42 2008
From: ward at gnu.org (Ward Vandewege)
Date: Tue, 2 Dec 2008 23:22:42 -0500
Subject: [coreboot] Request for comments: v3 config script
In-Reply-To: <49360256.90607@cosmicpenguin.net>
References: <493585CC.9090305@cosmicpenguin.net>
	<551A71DFAEA047CFBEE7481529F8301E@chimp>
	<20081203031918.32139.qmail@stuge.se>
	<49360256.90607@cosmicpenguin.net>
Message-ID: <20081203042242.GA2223@localdomain>

On Tue, Dec 02, 2008 at 08:51:50PM -0700, Jordan Crouse wrote:
> I think simple is a bit optimistic  - here is the diff between the  
> standard Config.lb and the LZMA enabled one for one of the tyan boards.  
> If you think we could recreate this magic in a shell script, then lets  
> go for it.

Let's start by simplyfying that diff by throwing out all the cruft from the
Config.lb file:

--- Config-lab.lb	2008-11-26 14:29:06.000000000 -0500
+++ Config.lb	2008-12-02 23:18:42.000000000 -0500
@@ -5,19 +5,23 @@
 target s2891
 mainboard tyan/s2891
 
-option ROM_SIZE=0x100000
-# 36K for ATI ROM in 1M
-option FALLBACK_SIZE=(ROM_SIZE-0x9000)
-
 # Tyan s2891
+romimage "normal"
+#       36K for ATI ROM in 1M
+	option ROM_SIZE = 1024*1024-36*1024
+	option USE_FALLBACK_IMAGE=0
+	option ROM_IMAGE_SIZE=0x20000
+	option XIP_ROM_SIZE=0x20000
+	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+	payload ../payload.elf
+end
+
 romimage "fallback" 
 	option USE_FALLBACK_IMAGE=1
-	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option ROM_IMAGE_SIZE=0x17000
-	option XIP_ROM_SIZE=0x40000
+	option ROM_IMAGE_SIZE=0x20000
+	option XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf.lzma
+	payload ../payload.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

So basically these are the differences:

1) no normal image in the lzma case, only fallback
2) some size parameter differences
3) payload filename is different

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From fengyuning1984 at gmail.com  Wed Dec  3 05:38:13 2008
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Wed, 3 Dec 2008 12:38:13 +0800
Subject: [coreboot] #104: flashrom: Change flash drivers to never erase
	data before writing
In-Reply-To: <050.6c6e32ee1a21388693912e957e24ac14@coreboot.org>
References: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
	<050.6c6e32ee1a21388693912e957e24ac14@coreboot.org>
Message-ID: <a505dc9d0812022038g59f8154du4437045618e1e1fe@mail.gmail.com>

We are talking about choosing some options from the full list:

* chip read
* chip erase
  chip write (0xff to other)
* chip erase-and-write (option 'write')

  partial read
  partial erase
1 partial write
2 partial erase-and-write

* = Options we have
1 = Carl-Daniel suggests
2 = Other people suggest

Every option in the list is useful in some case. My opinion on -

the choice	- Support the full list;
1		- Warning and ask for continuation. No checking for 0xff;
2		- We need this convenience for partial modification.

My two cents.

yu ning



From stepan at coresystems.de  Wed Dec  3 12:48:14 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 03 Dec 2008 12:48:14 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <4935E3A6.5060200@gmx.net>
References: <4935E3A6.5060200@gmx.net>
Message-ID: <493671FE.10407@coresystems.de>

Carl-Daniel Hailfinger wrote:
> LAR currently overwrites the top 13 bytes (0xfffff3-0xffffff) of the
> bootblock with zeros, then it stores the ROM size in 0xfffff4-0xfffff7.
> The top 8 bytes are unused in that scheme.
> Leave the top 8 bytes as they are and allow us to store something in
> there during the bootblock build process. The byte at 0xfffff3 is 0xff
> by default on x86 and setting it to 0 is not needed.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Nack.

They're unused, and until they are used, they should be cleared to a
consistent state.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866





From r.marek at assembler.cz  Wed Dec  3 14:47:27 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 03 Dec 2008 14:47:27 +0100
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and AMD
 690 Chipset source code for Coreboot]
Message-ID: <49368DEF.9020409@assembler.cz>

Just FYI:

AMD helps lower barriers for Open Source Development of AMD based 
embedded systems

Continuing its efforts to support the Open Source Community AMD has 
announced the release of the public versions of its SB600 documents. 
With the availability of the SB600 documentation, along with the already 
available AMD 690 Series chipset and processor documents, Open Source 
developers are now enabled to develop firmware and drivers for AMD based 
embedded systems.

AMD has also contributed the AMD 690 Series chipset, SB600, and DBM690E 
platform source code to the coreboot project (formerly know as 
LinuxBIOS). In the upcoming months, AMD plans to work with the coreboot 
community to enable AMD 690 chipset based systems to help provide the 
best possible coreboot experience.

"Since our earliest days in the LinuxBIOS project at Los Alamos National 
Labs, and continuing to its evolution to coreboot, AMD has been 
unequalled in their support of open source BIOS software; not just in 
documents, but in code and support." said Dr. Ronald G. Minnich, founder 
and developer of the coreboot project, and Principle Member of Technical 
Staff, Sandia National Labs, California. "We are looking forward to our 
continued work with AMD on the new chipsets."

The coreboot project is an Open Source firmware replacement focused on 
loading the Linux? operating system. Coreboot is an alternative firmware 
solution for AMD customers and technology partners that require an open 
and customizable embedded bootloader. AMD and the coreboot community 
have worked closely together for a number of years to develop coreboot 
for the AMD Athlon? processor, AMD Opteron? processor, AMD Phenom? 
processor, and AMD Geode? processor and the AMD-8000? Series, AMD 690 
Series and AMD CS5536 chipsets. AMD plans to continue supporting 
coreboot on future embedded silicon and platform releases.

In addition to this documentation, AMD embedded has also expanded its 
AMD 64 processors and chipset Linux support documentation. This includes 
BIOS, drivers and open processor information which can now be downloaded 
from AMD.com. AMD continues to collaborate with its customers in 
providing the resources and support to help enable their customers to 
market low-power, high-performance solutions.

For more information regarding SB600 documentation, AMD 64 processor and 
chipset Linux support and AMD embedded solutions please see:
http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_15872,00.html 
<http://links.mkt426.com/ctt?kn=5&m=2295441&r=MTUxNjMzMDc4MTES1&b=0&j=NjI1NTQzNjES1&mt=1&rt=0> 


For more information on coreboot please see:
http://www.coreboot.org/Welcome_to_coreboot 
<http://links.mkt426.com/ctt?kn=2&m=2295441&r=MTUxNjMzMDc4MTES1&b=0&j=NjI1NTQzNjES1&mt=1&rt=0>





From mylesgw at gmail.com  Wed Dec  3 15:34:31 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 3 Dec 2008 07:34:31 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>
	<49344EA4.9070208@cosmicpenguin.net>
	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
	<49347342.6080504@cosmicpenguin.net>
	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>
	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>
	<534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
Message-ID: <9C6D9FB140074309BBF88C861E99CA3A@chimp>



> -----Original Message-----
> From: Marc Jones [mailto:marcj303 at gmail.com]
> Sent: Tuesday, December 02, 2008 8:06 PM
> To: Myles Watson
> Cc: jordan at cosmicpenguin.net; coreboot at coreboot.org
> Subject: Re: [coreboot] qemu dts fixes
> 
> On Tue, Dec 2, 2008 at 10:57 AM, Myles Watson <mylesgw at gmail.com> wrote:
> >
> >
> > On Tue, Dec 2, 2008 at 7:13 AM, Myles Watson <mylesgw at gmail.com> wrote:
> >>
> >> Jordan,
> >>
> >> Sorry I obviously missed the point of your questions.  I'd forgotten
> that
> >> the fix went in to make all devices found in the dts be "on the
> mainboard."
> >> Here's a new patch that updates the dts with that in mind.  It also
> fixes
> >> the subsystem_vendor, which was broken in the last patch.
> >>
> >> I appreciate the sanity check.
> >
> > This patch is updated so that qemu works with resource allocation in
> phases.
> > Here are the changes:
> >
> > 1. Add a dts for the northbridge so it can have its own ops.
> > 2. Separates the domain from the device resource code.
> > 3. Add new resources for the APIC and VGA area.
> 
> Move the IOAPIC to the the 82371? I'm not sure if the LAPIC belongs in
> the northbridge on since every core needs one it might belong in the
> CPU but I think you only need to reserve the range once.

I'm happy to put them wherever makes the most sense.  APICs are a black box
to me at this point.  I've never had to do much with them.

> On another note, Do you find the res-> size and res->limit redundant?
> I can't think of how they could be different.

I just set them both here for completeness.  In other resources they aren't
redundant, because the limit says how high it could go (usually 0xffff for
IO), but the base+size-1 is the end of the resource.

Thanks,
Myles




From mylesgw at gmail.com  Wed Dec  3 15:46:25 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 3 Dec 2008 07:46:25 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <534e5dc20812021851n4fc902bdk1f6b342dad9c0086@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<49354C86.9000805@assembler.cz>
	<FC3FD2E4DC4C4AA085A52AE3294B8569@chimp>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
	<2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
	<13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>
	<7872596BBD834D33A5FAF4A70E79BE0F@chimp>
	<534e5dc20812021851n4fc902bdk1f6b342dad9c0086@mail.gmail.com>
Message-ID: <D0438496826F46CF9F3998C8AB663B61@chimp>



> -----Original Message-----
> From: Marc Jones [mailto:marcj303 at gmail.com]
> Sent: Tuesday, December 02, 2008 7:52 PM
> To: Myles Watson
> Cc: ron minnich; Rudolf Marek; Coreboot
> Subject: Re: [coreboot] Resource Allocation discussion
> 
> On Tue, Dec 2, 2008 at 3:23 PM, Myles Watson <mylesgw at gmail.com> wrote:
> >
> >
> >> -----Original Message-----
> >> From: ron minnich [mailto:rminnich at gmail.com]
> >> Sent: Tuesday, December 02, 2008 2:51 PM
> >> To: Myles Watson
> >> Cc: Marc Jones; Rudolf Marek; Coreboot
> >> Subject: Re: [coreboot] Resource Allocation discussion
> >>
> >> On Tue, Dec 2, 2008 at 11:33 AM, Myles Watson <mylesgw at gmail.com>
> wrote:
> >>
> >> > Do we want to take fixed resources into account in the allocator?
> >>
> >> I would think so.
> >
> > I would too, but v2 didn't and did pretty well.  I'm interested to see
> an
> > idea for the resource allocation algorithm that allocates from largest
> to
> > smallest resource, except when it's skipping fixed resources.
> >
> > I think it's doable, but nothing like what we have.
> 
> That surprises me. I thought it does, which is how/why you can get rid
> of DEVICE_MEM_HIGH. Otherwise you would clobber the ROM and the APIC.

You're right.  I think it's broken.  That's why right now I'm setting the
base to 0xfc000000 manually.  Thanks for pointing it out. 

I'd assumed that resource_max took fixed resources into account, but it
doesn't.  All resource_max does is align the resource based on its limit.

So maybe we need to traverse the tree looking for fixed spaces, and
constrain the domain's resource limit and base.  That wouldn't be too hard.
What I was saying would be hard is interleaving fixed resources with movable
resources.  In other words, if we put the VGA ROM between the two APIC
allocations to save space.  I think that's too ugly.

I'll add a traversal to the tree that doesn't ignore fixed resources.

> And that brings up where to reserve the ROM space. In the southbridge
> subtractive device code I guess?

Sure.  How much do we reserve?  Is it southbridge dependent?

Thanks,
Myles




From svn at coreboot.org  Wed Dec  3 16:38:43 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  3 Dec 2008 16:38:43 +0100
Subject: [coreboot] r1063 - in coreboot-v3: include/arch/x86/amd/k8
	mainboard/amd/serengeti northbridge/amd/k8
Message-ID: <mailman.2535.1355071447.16123.coreboot@coreboot.org>

Author: myles
Date: 2008-12-03 16:38:42 +0100 (Wed, 03 Dec 2008)
New Revision: 1063

Added:
   coreboot-v3/northbridge/amd/k8/apic
   coreboot-v3/northbridge/amd/k8/apic.c
   coreboot-v3/northbridge/amd/k8/mcf3
   coreboot-v3/northbridge/amd/k8/mcf3.c
Modified:
   coreboot-v3/include/arch/x86/amd/k8/k8.h
   coreboot-v3/mainboard/amd/serengeti/mainboard.h
   coreboot-v3/northbridge/amd/k8/Makefile
Log:
This patch adds two k8 devices from v2 to v3 (apic and mcf3.)

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-12-03 02:14:30 UTC (rev 1062)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h	2008-12-03 15:38:42 UTC (rev 1063)
@@ -580,7 +580,7 @@
 /* note: we'd like to have this sysinfo common to all K8, there's no need to
  * have one different kind per different kind of k8 at this point. 
  */
-//#include "raminit.h"
+#include "raminit.h"
 
 struct dimm_size {
         u8 per_rank; // it is rows + col + bank_lines + data lines */
@@ -608,14 +608,6 @@
 	u8 rsv[3];
 } __attribute__((packed));
 
-struct mem_controller {
-	unsigned node_id;
-	/* NOTE: these are in "BDF" format -- i.e. bus in upper 16, devfn in upper 8 of lower 16 */
-	u32 f0, f1, f2, f3;
-	u32 channel0[DIMM_SOCKETS];
-	u32 channel1[DIMM_SOCKETS];
-};
-
 struct link_pair_st {
 	u32 udev;
 	u32	upos;
@@ -685,8 +677,9 @@
 void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, 
 		const u16 *spd_addr);
 int lapic_remote_read(int apicid, int reg, unsigned int *pvalue);
-void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
+/*void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
 				const char *str);
+*/
 unsigned int wait_cpu_state(unsigned apicid, unsigned state);
 void set_apicid_cpuid_lo(void);
 /* fidvid.c */

Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/mainboard.h	2008-12-03 02:14:30 UTC (rev 1062)
+++ coreboot-v3/mainboard/amd/serengeti/mainboard.h	2008-12-03 15:38:42 UTC (rev 1063)
@@ -21,8 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define DIMM_SOCKETS 4
-#define NODE_NUMS 16
 #define CPU_SOCKET_TYPE SOCKET_AM2
 #define MEM_TRAIN_SEQ 0 /* for now */
 #define HW_MEM_HOLE_SIZE_AUTO_INC 0

Modified: coreboot-v3/northbridge/amd/k8/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/k8/Makefile	2008-12-03 02:14:30 UTC (rev 1062)
+++ coreboot-v3/northbridge/amd/k8/Makefile	2008-12-03 15:38:42 UTC (rev 1063)
@@ -27,6 +27,8 @@
 					$(src)/northbridge/amd/k8/cpu.c \
 					$(src)/northbridge/amd/k8/domain.c \
 					$(src)/northbridge/amd/k8/pci.c \
+					$(src)/northbridge/amd/k8/mcf3.c \
+					$(src)/northbridge/amd/k8/apic.c \
 					$(src)/northbridge/amd/k8/util.c
 
 endif

Added: coreboot-v3/northbridge/amd/k8/apic
===================================================================
--- coreboot-v3/northbridge/amd/k8/apic	                        (rev 0)
+++ coreboot-v3/northbridge/amd/k8/apic	2008-12-03 15:38:42 UTC (rev 1063)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	/* Miscellaneous Control Function 3 for Athlon/Opteron. */
+	device_operations = "k8_apic_ops";
+};

Added: coreboot-v3/northbridge/amd/k8/apic.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/apic.c	                        (rev 0)
+++ coreboot-v3/northbridge/amd/k8/apic.c	2008-12-03 15:38:42 UTC (rev 1063)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct device_operations k8_apic_ops = {
+	.id = {.type = DEVICE_ID_APIC},
+	.ops_pci = 0,
+};

Added: coreboot-v3/northbridge/amd/k8/mcf3
===================================================================
--- coreboot-v3/northbridge/amd/k8/mcf3	                        (rev 0)
+++ coreboot-v3/northbridge/amd/k8/mcf3	2008-12-03 15:38:42 UTC (rev 1063)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	/* Miscellaneous Control Function 3 for Athlon/Opteron. */
+	device_operations = "mcf3_ops";
+};

Added: coreboot-v3/northbridge/amd/k8/mcf3.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/mcf3.c	                        (rev 0)
+++ coreboot-v3/northbridge/amd/k8/mcf3.c	2008-12-03 15:38:42 UTC (rev 1063)
@@ -0,0 +1,182 @@
+/* Turn off machine check triggers when reading
+ * pci space where there are no devices.
+ * This is necessary when scaning the bus for
+ * devices which is done by the kernel
+ *
+ * written in 2003 by Eric Biederman
+ *
+ *  - Athlon64 workarounds by Stefan Reinauer
+ *  - "reset once" logic by Yinghai Lu
+ */
+
+#include <console.h>
+#include <lib.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#warning Broken hard_reset
+//#include <part/hard_reset.h>
+#include <mc146818rtc.h>
+#include <amd/k8/k8.h>
+
+#warning Make AGP_APERTURE_SIZE a CONFIG variable
+#define AGP_APERTURE_SIZE 0x4000000	//64M
+
+/**
+ * @brief Read resources for AGP aperture
+ *
+ * @param
+ *
+ * There is only one AGP aperture resource needed. The resoruce is added to
+ * the northbridge of BSP.
+ *
+ * The same trick can be used to augment legacy VGA resources which can
+ * be detected by the generic pci resource allocator for VGA devices.
+ * BAD: it is more tricky than I think, the resource allocation code is
+ * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * purpose :-(.
+ */
+static void mcf3_read_resources(struct device *dev)
+{
+	struct resource *resource;
+	unsigned char iommu;
+	/* Read the generic PCI resources */
+	pci_dev_read_resources(dev);
+
+	/* If we are not the first processor don't allocate the GART aperture */
+	if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
+		return;
+	}
+
+	iommu = 1;
+	get_option(&iommu, "iommu");
+
+	if (iommu) {
+		/* Add a GART aperture resource */
+		resource = new_resource(dev, 0x94);
+		resource->size = iommu ? AGP_APERTURE_SIZE : 1;
+		resource->align = log2f(resource->size);
+		resource->gran = log2f(resource->size);
+		resource->limit = 0xffffffff;	/* 4G */
+		resource->flags = IORESOURCE_MEM;
+	}
+}
+
+static void set_agp_aperture(struct device *dev)
+{
+	struct resource *resource;
+
+	resource = probe_resource(dev, 0x94);
+	if (resource) {
+		struct device *pdev;
+		struct device_id id;
+		u32 gart_base, gart_acr;
+
+		/* Remember this resource has been stored */
+		resource->flags |= IORESOURCE_STORED;
+
+		/* Find the size of the GART aperture */
+		gart_acr = (0 << 6) | (0 << 5) | (0 << 4) |
+		           ((resource->gran - 25) << 1) | (0 << 0);
+
+		/* Get the base address */
+		gart_base = ((resource->base) >> 25) & 0x00007fff;
+
+		/* Update the other northbriges */
+		pdev = NULL;
+		id.type = DEVICE_ID_PCI;
+		id.pci.vendor = PCI_VENDOR_ID_AMD;
+		id.pci.device = 0x1103;
+		while ((pdev = dev_find_device(&id, pdev))) {
+			/* Store the GART size but don't enable it */
+			pci_write_config32(pdev, 0x90, gart_acr);
+
+			/* Store the GART base address */
+			pci_write_config32(pdev, 0x94, gart_base);
+
+			/* Don't set the GART Table base address */
+			pci_write_config32(pdev, 0x98, 0);
+
+			/* Report the resource has been stored... */
+			report_resource_stored(pdev, resource, " <gart>");
+		}
+	}
+}
+
+static void mcf3_set_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s...\n", __func__);
+	/* Set the GART aperture */
+	set_agp_aperture(dev);
+
+	/* Set the generic PCI resources */
+	pci_set_resources(dev);
+}
+
+static void misc_control_init(struct device *dev)
+{
+	u32 cmd, cmd_ref;
+	int needs_reset;
+	struct device *f0_dev;
+
+	printk(BIOS_DEBUG, "NB: Function 3 Misc Control..\n");
+	needs_reset = 0;
+
+	/* Disable Machine checks from Invalid Locations.
+	 * This is needed for PC backwards compatibility.
+	 */
+	cmd = pci_read_config32(dev, 0x44);
+	cmd |= (1 << 6) | (1 << 25);
+	pci_write_config32(dev, 0x44, cmd);
+
+	/* Optimize the Link read pointers */
+	f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
+	if (f0_dev) {
+		int link;
+		cmd_ref = cmd = pci_read_config32(dev, 0xdc);
+		for (link = 0; link < 3; link++) {
+			u32 link_type;
+			unsigned reg;
+			/* This works on an Athlon64 because unimplemented
+			 * links return 0.
+			 */
+			reg = 0x98 + (link * 0x20);
+			link_type = pci_read_config32(f0_dev, reg);
+			/* Only handle coherent links here please. */
+			if ((link_type &
+			     (LinkConnected | InitComplete | NonCoherent))
+			    == (LinkConnected | InitComplete)) {
+				cmd &= ~(0xff << (link * 8));
+				/* FIXME this assumes the device on the other
+				 * side is an AMD device.
+				 */
+				cmd |= 0x25 << (link * 8);
+			}
+		}
+		if (cmd != cmd_ref) {
+			pci_write_config32(dev, 0xdc, cmd);
+			needs_reset = 1;
+		}
+	} else {
+		printk(BIOS_ERR, "Missing f0 device!\n");
+	}
+	if (needs_reset) {
+		printk(BIOS_DEBUG, "Not resetting cpu, but it's needed.\n");
+		//hard_reset();
+	}
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+struct device_operations mcf3_ops = {
+	.id = {.type = DEVICE_ID_PCI,
+	       {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+			.device = 0x1103}}},
+	.phase3_scan		 = 0,
+	.phase4_read_resources	 = mcf3_read_resources,
+	.phase4_set_resources	 = mcf3_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
+	.phase6_init		 = misc_control_init,
+	.ops_pci		 = 0,
+};
+




From mylesgw at gmail.com  Wed Dec  3 16:39:45 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 3 Dec 2008 08:39:45 -0700
Subject: [coreboot] add 2 k8 devs
In-Reply-To: <13426df10812021337r3653eef9xdf8089ff1fd9e2e@mail.gmail.com>
References: <2831fecf0812011238n7c95745dpac20fbcbfebb1918@mail.gmail.com>
	<13426df10812011252q12537213t90121e60a615cd3e@mail.gmail.com>
	<2831fecf0812011315t79bd3621v1258f50e50025341@mail.gmail.com>
	<2831fecf0812021240j25caf7d7q6bb93a0ea3e0f54d@mail.gmail.com>
	<13426df10812021337r3653eef9xdf8089ff1fd9e2e@mail.gmail.com>
Message-ID: <2831fecf0812030739l603c7410ha8e1a3ade53e4f47@mail.gmail.com>

On Tue, Dec 2, 2008 at 2:37 PM, ron minnich <rminnich at gmail.com> wrote:

> I think you can remove all the stuff in the #if 0, we don't care about
> pre-c0 and pre-d0 on v3.

fixed.

> apeture -> aperture
> reousce or some such -> resource

fixed.


> There are a few mispellings which we can fix later.
>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
Rev 1063.

Thanks,
Myles
-------------- next part --------------
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From rminnich at gmail.com  Wed Dec  3 17:41:09 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 3 Dec 2008 08:41:09 -0800
Subject: [coreboot] Fwd: Merging Qi with coreboot?
In-Reply-To: <4936AF10.3020103@openmoko.com>
References: <20081203155123.GA2896@excalibur.hozed.org>
	<4936AF10.3020103@openmoko.com>
Message-ID: <13426df10812030841w181102c8nad6113ed802edb5@mail.gmail.com>

This is an interesting writeup (see link). I think they think coreboot
does lots of BIOS stuff.

ron


---------- Forwarded message ----------
From: Andy Green <andy at openmoko.com>
Date: Wed, Dec 3, 2008 at 8:08 AM
Subject: Re: Merging Qi with coreboot?
To: Troy Benjegerdes <hozer at hozed.org>
Cc: devel at lists.openmoko.org, rminnich at gmail.com


-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Somebody in the thread at some point said:

| I'd like to understand the motivation for Qi.. it really seems like it's
| just a "YABL" (yet another boot loader). Why can't U-boot be made to

There's some explanation of why we moved off U-Boot here

http://git.openmoko.org/?p=qi.git;a=blob;f=README;h=198507c717cc8b5f8f72250f2caa28ffef1ac537;hb=HEAD

| boot "really fast", or if speed is the primary motivation, wouldn't it
| make more sense to leverage the work begin done on Coreboot for x86?
| (cold boot to linux console in 3 seconds on x86 hardware)

x86 and s3c device boot are very different, and we don't need to take
care about a lot of PC-centric BIOS business.

- -Andy
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From c-d.hailfinger.devel.2006 at gmx.net  Wed Dec  3 18:49:10 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Dec 2008 18:49:10 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <493671FE.10407@coresystems.de>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>
Message-ID: <4936C696.8090404@gmx.net>

On 03.12.2008 12:48, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> LAR currently overwrites the top 13 bytes (0xfffff3-0xffffff) of the
>> bootblock with zeros, then it stores the ROM size in 0xfffff4-0xfffff7.
>> The top 8 bytes are unused in that scheme.
>> Leave the top 8 bytes as they are and allow us to store something in
>> there during the bootblock build process. The byte at 0xfffff3 is 0xff
>> by default on x86 and setting it to 0 is not needed.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> Nack.
>
> They're unused, and until they are used, they should be cleared to a
> consistent state.
>   

They are already cleared by arch/x86/stage0_common.S. Having to clear
them in the LAR would mean the code in stage0_common.S is crap and needs
to be fixed.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Wed Dec  3 18:52:18 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Dec 2008 18:52:18 +0100
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and
 AMD 690 Chipset source code for Coreboot]
In-Reply-To: <49368DEF.9020409@assembler.cz>
References: <49368DEF.9020409@assembler.cz>
Message-ID: <4936C752.1000900@gmx.net>

Hi Rudolf,

the links in the forwarded mail look a lot like phishing related stuff.
Where did you find that press release?

Regards,
Carl-Daniel

On 03.12.2008 14:47, Rudolf Marek wrote:
> For more information regarding SB600 documentation, AMD 64 processor
> and chipset Linux support and AMD embedded solutions please see:
> http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_15872,00.html
> <http://links.mkt426.com/ctt?kn=5&m=2295441&r=MTUxNjMzMDc4MTES1&b=0&j=NjI1NTQzNjES1&mt=1&rt=0>
>
>
> For more information on coreboot please see:
> http://www.coreboot.org/Welcome_to_coreboot
> <http://links.mkt426.com/ctt?kn=2&m=2295441&r=MTUxNjMzMDc4MTES1&b=0&j=NjI1NTQzNjES1&mt=1&rt=0>
>

-- 
http://www.hailfinger.org/




From jordan at cosmicpenguin.net  Wed Dec  3 19:00:10 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Wed, 03 Dec 2008 11:00:10 -0700
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <4936C696.8090404@gmx.net>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>
	<4936C696.8090404@gmx.net>
Message-ID: <4936C92A.4060106@cosmicpenguin.net>

Carl-Daniel Hailfinger wrote:
> On 03.12.2008 12:48, Stefan Reinauer wrote:
>> Carl-Daniel Hailfinger wrote:
>>   
>>> LAR currently overwrites the top 13 bytes (0xfffff3-0xffffff) of the
>>> bootblock with zeros, then it stores the ROM size in 0xfffff4-0xfffff7.
>>> The top 8 bytes are unused in that scheme.
>>> Leave the top 8 bytes as they are and allow us to store something in
>>> there during the bootblock build process. The byte at 0xfffff3 is 0xff
>>> by default on x86 and setting it to 0 is not needed.
>>>
>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>     
>> Nack.
>>
>> They're unused, and until they are used, they should be cleared to a
>> consistent state.
>>   
> 
> They are already cleared by arch/x86/stage0_common.S. Having to clear
> them in the LAR would mean the code in stage0_common.S is crap and needs
> to be fixed.

Not necessarily.  This is a userland utility, so there is no real 
penalty for making extra sure that the area is in a valid state.  LAR 
shouldn't depend on the v3 code to do the right thing, nor should the v3 
code depend on LAR to do the right thing.

Jordan





From joe at settoplinux.org  Wed Dec  3 19:06:44 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 03 Dec 2008 13:06:44 -0500
Subject: [coreboot] =?utf-8?q?Fwd=3A_Merging_Qi_with_coreboot=3F?=
In-Reply-To: <13426df10812030841w181102c8nad6113ed802edb5@mail.gmail.com>
References: <20081203155123.GA2896@excalibur.hozed.org>
	<4936AF10.3020103@openmoko.com>
	<13426df10812030841w181102c8nad6113ed802edb5@mail.gmail.com>
Message-ID: <837a8bea190ee07fc8f2078a5dd48e6a@imap.1and1.com>




On Wed, 3 Dec 2008 08:41:09 -0800, "ron minnich" <rminnich at gmail.com>
wrote:
> This is an interesting writeup (see link). I think they think coreboot
> does lots of BIOS stuff.
> 
That's funny. If we had ARM support in coreboot there wouldn't be a need
for all the sillyness :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Wed Dec  3 19:10:18 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 03 Dec 2008 13:10:18 -0500
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and
 AMD 690 Chipset source code for Coreboot]
In-Reply-To: <4936C752.1000900@gmx.net>
References: <49368DEF.9020409@assembler.cz> <4936C752.1000900@gmx.net>
Message-ID: <a5a4264b1edae71b943de65be3d14871@imap.1and1.com>




On Wed, 03 Dec 2008 18:52:18 +0100, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi Rudolf,
> 
> the links in the forwarded mail look a lot like phishing related stuff.
> Where did you find that press release?
> 
It was an email. I got, because I am on the AMD embedded developers mailing
list. I will forward the html version to you.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mylesgw at gmail.com  Wed Dec  3 19:43:47 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 3 Dec 2008 11:43:47 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <D0438496826F46CF9F3998C8AB663B61@chimp>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<49356299.2040408@assembler.cz>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
	<2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
	<13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>
	<7872596BBD834D33A5FAF4A70E79BE0F@chimp>
	<534e5dc20812021851n4fc902bdk1f6b342dad9c0086@mail.gmail.com>
	<D0438496826F46CF9F3998C8AB663B61@chimp>
Message-ID: <2831fecf0812031043i31aa57edp157d64b1a51f3565@mail.gmail.com>

On Wed, Dec 3, 2008 at 7:46 AM, Myles Watson <mylesgw at gmail.com> wrote:

>
>
> > -----Original Message-----
> > From: Marc Jones [mailto:marcj303 at gmail.com]
> > Sent: Tuesday, December 02, 2008 7:52 PM
> > To: Myles Watson
> > Cc: ron minnich; Rudolf Marek; Coreboot
> > Subject: Re: [coreboot] Resource Allocation discussion
> >
> > On Tue, Dec 2, 2008 at 3:23 PM, Myles Watson <mylesgw at gmail.com> wrote:
> > >
> > >
> > >> -----Original Message-----
> > >> From: ron minnich [mailto:rminnich at gmail.com]
> > >> Sent: Tuesday, December 02, 2008 2:51 PM
> > >> To: Myles Watson
> > >> Cc: Marc Jones; Rudolf Marek; Coreboot
> > >> Subject: Re: [coreboot] Resource Allocation discussion
> > >>
> > >> On Tue, Dec 2, 2008 at 11:33 AM, Myles Watson <mylesgw at gmail.com>
> > wrote:
> > >>
> > >> > Do we want to take fixed resources into account in the allocator?
> > >>
> > >> I would think so.
> > >
> > > I would too, but v2 didn't and did pretty well.  I'm interested to see
> > an
> > > idea for the resource allocation algorithm that allocates from largest
> > to
> > > smallest resource, except when it's skipping fixed resources.
> > >
> > > I think it's doable, but nothing like what we have.
> >
> > That surprises me. I thought it does, which is how/why you can get rid
> > of DEVICE_MEM_HIGH. Otherwise you would clobber the ROM and the APIC.
>
> You're right.  I think it's broken.  That's why right now I'm setting the
> base to 0xfc000000 manually.  Thanks for pointing it out.
>
> I'd assumed that resource_max took fixed resources into account, but it
> doesn't.  All resource_max does is align the resource based on its limit.
>
> So maybe we need to traverse the tree looking for fixed spaces, and
> constrain the domain's resource limit and base.  That wouldn't be too hard.
> What I was saying would be hard is interleaving fixed resources with
> movable
> resources.  In other words, if we put the VGA ROM between the two APIC
> allocations to save space.  I think that's too ugly.
>
> I'll add a traversal to the tree that doesn't ignore fixed resources.
>

A question before the code:
1. Can anyone enumerate all the fixed resources that should be included in
QEMU?
Currently I have:
- DRAM (first 640K and 0xc0000-TOP-768K) Is this necessary?
- I/O first 0x400 in southbridge
- VGA 0xa0000-0xc0000
- APIC at 0xfec00000 and 0xfee00000
- ROM at 0xfff80000

Side note: Only the lowest and highest fixed addresses matter in my code.
The others get ignored.  I think it's too much pain to try to interleave
them to use the space between 0xfee00000 and 0xfff80000, for example.

All right.  I've added code that traverses each domain looking for fixed
resources.  Here's the pseudo code:

For each domain:
    call avoid_fixed_resources(domain_dev)

avoid_fixed_resources(dev)
     initialize limits to maximum size
     initialize the limits to dev's resources limits
     call constrain_resources(dev, limits)
     update dev's resources

constrain_resources(dev, limits)
     for each child
         call constrain_resources(child, limits)
         for each fixed resource
            if limits contain resource
               update limits to exclude resource (largest space possible)

And here's the code.  It's not a diff because it's all new.
struct constraints {
    struct resource pref, io, mem;
};

static void constrain_resources(struct device *dev, struct constraints*
limits)
{
    struct device *child;
    struct resource *res;
    struct resource *lim;
    int i;

#ifdef CONFIG_PCI_64BIT_PREF_MEM
    #define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#else
    #define MEM_MASK (IORESOURCE_MEM)
#endif
#define IO_MASK (IORESOURCE_IO)
#define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#define MEM_TYPE (IORESOURCE_MEM)
#define IO_TYPE (IORESOURCE_IO)

    /* Descend into every child and look for fixed resources. */
    for (child=dev->link[0].children; child; child = child->sibling) {
        constrain_resources(child, limits);
        for (i = 0; i<child->resources; i++) {
            res = &child->resource[i];
            if (!(res->flags & IORESOURCE_FIXED))
                continue;
            /* Choose larger space: above or below fixed resources. */

            /* PREFETCH */
            if ((res->flags & MEM_MASK) == PREF_TYPE) {
                lim = &limits->pref;
                /* Is it already outside the limits? */
                if ((res->base + res->size -1) < lim->base ||
                    res->base > lim->limit)
                    continue;
                /* Is the space above larger? */
                if ((lim->limit - (res->base + res->size -1)) >
                    (res->base - lim->base))
                    lim->base = res->base + res->size;
                else
                    lim->limit = res->base -1;
            }

            /* MEM */
            if ((res->flags & MEM_MASK) == MEM_TYPE) {
                lim = &limits->mem;
                /* Is it already outside the limits? */
                if ((res->base + res->size -1) < lim->base ||
                    res->base > lim->limit)
                    continue;
                /* Is the space above larger? */
                if ((lim->limit - (res->base + res->size -1)) >
                    (res->base - lim->base))
                    lim->base = res->base + res->size;
                else
                    lim->limit = res->base -1;
            }

            /* I/O */
            if ((res->flags & IO_MASK) == IO_TYPE) {
                lim = &limits->io;
                /* Is it already outside the limits? */
                if ((res->base + res->size -1) < lim->base ||
                    res->base > lim->limit)
                    continue;
                /* Is the space above larger? */
                if ((lim->limit - (res->base + res->size -1)) >
                    (res->base - lim->base))
                    lim->base = res->base + res->size;
                else
                    lim->limit = res->base -1;
            }
        }
    }
}

static void avoid_fixed_resources(struct device *dev)
{
    struct constraints limits;
    struct resource *res;
    int i;

    /* Initialize constraints to maximum size. */

    limits.pref.base = 0;
    limits.pref.limit = 0xfffffffffffffffULL;
    limits.io.base = 0;
    limits.io.limit = 0xfffffffffffffffULL;
    limits.mem.base = 0;
    limits.mem.limit = 0xfffffffffffffffULL;

    /* Initialize the limits from the device's resources. */
    for (i = 0; i<dev->resources; i++) {
        res = &dev->resource[i];

        /* PREFETCH */
        if ((res->flags & MEM_MASK) == PREF_TYPE &&
            res->limit < limits.pref.limit )
            limits.pref.limit = res->limit;
        /* MEM */
        if ((res->flags & MEM_MASK) == MEM_TYPE &&
            res->limit < limits.mem.limit )
            limits.mem.limit = res->limit;
        /* I/O */
        if ((res->flags & IO_MASK) == IO_TYPE &&
            res->limit < limits.io.limit )
            limits.io.limit = res->limit;
    }

    constrain_resources(dev, &limits);

    for (i = 0; i<dev->resources; i++) {
        res = &dev->resource[i];
        /* Update the device's resources with new limits. */

        /* PREFETCH */
        if ((res->flags & MEM_MASK) == PREF_TYPE) {
            /* Is the resource outside the limits? */
            if ( limits.pref.base > res->base )
                res->base = limits.pref.base;
            if ( res->limit > limits.pref.limit )
                res->limit = limits.pref.limit;
        }

        /* MEM */
        if ((res->flags & MEM_MASK) == MEM_TYPE) {
            /* Is the resource outside the limits? */
            if ( limits.mem.base > res->base )
                res->base = limits.mem.base;
            if ( res->limit > limits.mem.limit )
                res->limit = limits.mem.limit;
        }

        /* I/O */
        if ((res->flags & IO_MASK) == IO_TYPE) {
            /* Is the resource outside the limits? */
            if ( limits.io.base > res->base )
                res->base = limits.io.base;
            if ( res->limit > limits.io.limit )
                res->limit = limits.io.limit;
        }
    }
}

Thanks,
Myles
-------------- next part --------------
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From uwe at hermann-uwe.de  Wed Dec  3 19:46:29 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 3 Dec 2008 19:46:29 +0100
Subject: [coreboot] [PATCH] inteltool: i965, i975,
	ICH8M and Darwin	support.
In-Reply-To: <493300AB.2000201@coresystems.de>
References: <493300AB.2000201@coresystems.de>
Message-ID: <20081203184629.GA29474@greenwood>

I was about to ack this, but it fails to build, see below. I also added
a few smaller comments to the review, but the build issue is the only
really important one.


On Sun, Nov 30, 2008 at 10:07:55PM +0100, Stefan Reinauer wrote:
> +#ifndef DARWIN
> +#include <sys/io.h>
> +#else
> +#include <DirectIO/darwinio.h>
> +#endif

Maybe a small paragraph with build instructions and URL for DirectIO
etc. in the README/manpage would be good (that's for another patch though).


>  #define PCI_DEVICE_ID_INTEL_82845	0x1a30
>  #define PCI_DEVICE_ID_INTEL_82945P	0x2770
>  #define PCI_DEVICE_ID_INTEL_82945GM	0x27a0
> +#define PCI_DEVICE_ID_INTEL_PM965       0x2a00
> +#define PCI_DEVICE_ID_INTEL_82975X      0x277c

These two use spaces, not TABs, and are thus not properly aligned,
please change to TABs in the commit.


>  	for (i = 0; i < size; i += 4) {
> +#ifdef DARWIN
> +		if (i==0x14) {
                     ^ ^ 
           add spaces here, please.


> +			/* Reading this register will hang a macbook pro */
> +			printf("pmbase+0x%04x: 0xXXXXXXXX\n", i);

Any idea why? Hardware problem or OS problem? Does Linux on Apple
hardware have the same issue? If yes, the "#ifdef DARWIN" check may
not be correct/complete.


> +void unmap_physical(void *virt_addr, int len)
> +{
> +       munmap((void *)rcba, size);
> +}

This part fails to build, as 'rcba' is never defined. I guess 'virt_addr' is
the correct thing to use here (?) If yes, the (void *) cast is not
needed, too, I think.

Also, s/size/len/, otherwise it won't build.


> Index: Makefile
> ===================================================================
> --- Makefile	(revision 3783)
> +++ Makefile	(working copy)
> @@ -29,6 +29,13 @@
>  
>  OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o
>  
> +OS_ARCH	= $(shell uname)
> +ifeq ($(OS_ARCH), Darwin)
> +CFLAGS += -DDARWIN -I/usr/local/include 
> +LDFLAGS = -framework IOKit -framework DirectIO -L/usr/local/lib -lpci -lz

Maybe /usr/local should be easily configurable (adding it as variable,
or reusing PREFIX or so)?


> +# OBJS += darwinio.o
> +endif
> +
>  all: pciutils dep $(PROGRAM)
>  
>  $(PROGRAM): $(OBJS)
> @@ -41,10 +48,10 @@
>  	rm -f .dependencies
>  
>  dep:
> -	@$(CC) -MM *.c > .dependencies
> +	@$(CC) $(CFLAGS) -MM *.c > .dependencies
>  
>  pciutils:
> -	@echo; echo -n "Checking for pciutils and zlib... "
> +	@echo; /bin/echo -n "Checking for pciutils and zlib... "

Why this change? If it's needed, the "@echo" should also have the
full path then?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From peter at stuge.se  Wed Dec  3 19:53:06 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 3 Dec 2008 19:53:06 +0100
Subject: [coreboot] Fwd: Merging Qi with coreboot?
In-Reply-To: <13426df10812030841w181102c8nad6113ed802edb5@mail.gmail.com>
References: <20081203155123.GA2896@excalibur.hozed.org>
	<4936AF10.3020103@openmoko.com>
	<13426df10812030841w181102c8nad6113ed802edb5@mail.gmail.com>
Message-ID: <20081203185306.9329.qmail@stuge.se>

Sorry about the crossposting. Please let me know if you should be
excluded.


ron minnich wrote:
> This is an interesting writeup (see link). I think they think
> coreboot does lots of BIOS stuff.

Andy Green wrote:
> | wouldn't it make more sense to leverage the work begin done on
> | Coreboot for x86?
> 
> x86 and s3c device boot are very different, and we don't need to
> take care about a lot of PC-centric BIOS business.

Note that coreboot is not about being a BIOS, by design. The idea
with coreboot since day 1 was to get Linux running as soon as
possible and to let Linux handle as much as it could. This design
goal seems to be shared by coreboot and Qi.

coreboot does not implement BIOS services, coreboot only does
hardware initialization and then it hands over to another program,
called the payload, which never returns.

Linux can be used as payload, if you really do want a BIOS you can
use the SeaBIOS payload, there are several lightweight bootloaders
that can be payloads (FILO, GRUB 2, gPXE, 9load..) and simple
applications can be built into payloads using libpayload.

While coreboot worked mostly for x86 small and large in the past, it
has supported both alpha and power. In coreboot v3 we make an effort
to keep everything arch clean to make support also for non-x86 easy.

What steps does Qi need to take before it can hand over to Linux?


//Peter



From peter at stuge.se  Wed Dec  3 19:54:15 2008
From: peter at stuge.se (Peter Stuge)
Date: Wed, 3 Dec 2008 19:54:15 +0100
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and
	AMD 690 Chipset source code for Coreboot]
In-Reply-To: <4936C752.1000900@gmx.net>
References: <49368DEF.9020409@assembler.cz> <4936C752.1000900@gmx.net>
Message-ID: <20081203185415.9608.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> the links in the forwarded mail look a lot like phishing related
> stuff.

They are used for click tracking. Not uncommon in newsletters.


//Peter



From chris at stockwith.co.uk  Wed Dec  3 20:10:24 2008
From: chris at stockwith.co.uk (Chris Lingard)
Date: Wed, 03 Dec 2008 19:10:24 +0000
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and
 AMD 690 Chipset source code for Coreboot]
In-Reply-To: <a5a4264b1edae71b943de65be3d14871@imap.1and1.com>
References: <49368DEF.9020409@assembler.cz> <4936C752.1000900@gmx.net>
	<a5a4264b1edae71b943de65be3d14871@imap.1and1.com>
Message-ID: <4936D9A0.3080808@stockwith.co.uk>

Joseph Smith wrote:
> 
> 
> On Wed, 03 Dec 2008 18:52:18 +0100, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> Hi Rudolf,
>>
>> the links in the forwarded mail look a lot like phishing related stuff.
>> Where did you find that press release?
>>
> It was an email. I got, because I am on the AMD embedded developers mailing
> list. I will forward the html version to you.
> 

If that is a press release, for general release; can I have a copy and 
publish it on www.groklaw.net

Chris Lingard




From klt29 at freemail.hu  Wed Dec  3 20:07:10 2008
From: klt29 at freemail.hu (Tamas Szabo)
Date: Wed, 03 Dec 2008 20:07:10 +0100
Subject: [coreboot] EPIA MII Tutorial for recent coreboot-v2
Message-ID: <4936D8DE.8040400@freemail.hu>

Hi,

Is there an up-to-date version of EPIA MII tutorial?

The one I found at http://www.coreboot.org/VIA_EPIA-MII seems to be 
outdated - even the referenced filenames are differ. Based on it I was 
not able to create the right ROM file.

If I just simply run buildtarget and make (assume that filo is already 
compiled and sits at the right place) the coreboot.rom is created. 
However it start with the ELF signature - is it right?

If I use filo from the svn it is compiles, however coreboot 'make' 
complains about the size.

The VGA bios extraction method say skip=12 but the doc in coreboot svn 
use skip=790528. Which one should I use?

Also, the description of the usage of VGA bios to create the 
coreboot.rom is quite unclear.

Can anyone help me, how can I build a usable bios for a few of my 
good-old EPIA MIIs?

Thanks in advance,

/sza2




From stephan.guilloux at free.fr  Wed Dec  3 22:23:10 2008
From: stephan.guilloux at free.fr (Stephan GUILLOUX)
Date: Wed, 03 Dec 2008 22:23:10 +0100
Subject: [coreboot] [PATCH] flashrom patch for partial flash read #2
In-Reply-To: <4935E652.4000107@gmx.net>
References: <4935DB1B.6070803@free.fr> <4935E652.4000107@gmx.net>
Message-ID: <4936F8BE.1010405@free.fr>


After partial review, the following fixes are included :
- return used without parentheses.
    I prefer parentheses, as it allows macros around. For instance, I 
oftenly use macros like FUNCTION_RETURN(xx)
    do dump the return code at debug time. Not the case here, so, () 
removed.
- unsigned int total_size.
    errr. yes ;-)
- verification error message changed to
    Error: verification aborted because of flash read failure.
- length > total_size
    length == total_size is allowed !.

Anything else ?

    Stephan.





From svn at coreboot.org  Wed Dec  3 22:24:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  3 Dec 2008 22:24:40 +0100
Subject: [coreboot] r3790 - trunk/util/flashrom
Message-ID: <mailman.2536.1355071447.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-12-03 22:24:40 +0100 (Wed, 03 Dec 2008)
New Revision: 3790

Modified:
   trunk/util/flashrom/Makefile
   trunk/util/flashrom/chipset_enable.c
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashrom.c
Log:
Replace #ifdefs for sc520 systems by run time probing.

fixes #109

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/util/flashrom/Makefile
===================================================================
--- trunk/util/flashrom/Makefile	2008-12-02 12:26:17 UTC (rev 3789)
+++ trunk/util/flashrom/Makefile	2008-12-03 21:24:40 UTC (rev 3790)
@@ -11,7 +11,7 @@
 INSTALL = /usr/bin/install
 PREFIX  = /usr/local
 #CFLAGS  = -O2 -g -Wall -Werror
-CFLAGS  = -Os -Wall -Werror # -DTS5300
+CFLAGS  = -Os -Wall -Werror
 OS_ARCH	= $(shell uname)
 ifeq ($(OS_ARCH), SunOS)
 LDFLAGS = -lpci -lz

Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c	2008-12-02 12:26:17 UTC (rev 3789)
+++ trunk/util/flashrom/chipset_enable.c	2008-12-03 21:24:40 UTC (rev 3790)
@@ -35,6 +35,8 @@
 #include <unistd.h>
 #include "flash.h"
 
+unsigned long flashbase = 0;
+
 /**
  * flashrom defaults to LPC flash devices. If a known SPI controller is found
  * and the SPI strappings are set, this will be overwritten by the probing code.
@@ -797,6 +799,59 @@
 	return 0;
 }
 
+/**
+ * Usually on the x86 architectures (and on other PC-like platforms like some
+ * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
+ * Elan SC520 only a small piece of the system flash is mapped there, but the
+ * complete flash is mapped somewhere below 1G. The position can be determined
+ * by the BOOTCS PAR register.
+ */
+static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
+{
+	int i, bootcs_found = 0;
+	uint32_t parx = 0;
+	void *mmcr;
+
+	/* 1. Map MMCR */
+	mmcr = mmap(0, getpagesize(), PROT_WRITE | PROT_READ,
+			MAP_SHARED, fd_mem, (off_t)0xFFFEF000);
+
+	if (mmcr == MAP_FAILED) {
+		perror("Can't mmap Elan SC520 specific registers using " MEM_DEV);
+		exit(1);
+	}
+
+	/* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
+	 *    BOOTCS region (PARx[31:29] = 100b)e
+	 */
+	for (i = 0x88; i <= 0xc4; i += 4) {
+		parx = *(volatile uint32_t *)(mmcr + i);
+		if ((parx >> 29) == 4) {
+			bootcs_found = 1;
+			break; /* BOOTCS found */
+		}
+	}
+
+	/* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
+	 *    PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
+	 */
+	if (bootcs_found) {
+		if (parx & (1 << 25)) {
+			parx &= (1 << 14) - 1; /* Mask [13:0] */
+			flashbase = parx << 16;
+		} else {
+			parx &= (1 << 18) - 1; /* Mask [17:0] */
+			flashbase = parx << 12;
+		}
+	} else {
+		printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
+	}
+
+	/* 4. Clean up */
+	munmap (mmcr, getpagesize());
+	return 0;
+}
+
 typedef struct penable {
 	uint16_t vendor, device;
 	const char *name;
@@ -875,6 +930,7 @@
 	{0x10de, 0x0548, "NVIDIA MCP67",	enable_flash_mcp55},
 	{0x1002, 0x4377, "ATI SB400",		enable_flash_sb400},
 	{0x1166, 0x0205, "Broadcom HT-1000",	enable_flash_ht1000},
+	{0x1022, 0x3000, "AMD Elan SC520",	get_flashbase_sc520},
 };
 
 void print_supported_chipsets(void)

Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h	2008-12-02 12:26:17 UTC (rev 3789)
+++ trunk/util/flashrom/flash.h	2008-12-03 21:24:40 UTC (rev 3790)
@@ -410,6 +410,8 @@
 int chipset_flash_enable(void);
 void print_supported_chipsets(void);
 
+extern unsigned long flashbase;
+
 typedef enum {
 	BUS_TYPE_LPC,
 	BUS_TYPE_ICH7_SPI,

Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-12-02 12:26:17 UTC (rev 3789)
+++ trunk/util/flashrom/flashrom.c	2008-12-03 21:24:40 UTC (rev 3790)
@@ -105,7 +105,7 @@
 {
 	volatile uint8_t *bios;
 	struct flashchip *flash;
-	unsigned long flash_baseaddr = 0, size;
+	unsigned long size;
 
 	for (flash = first_flash; flash && flash->name; flash++) {
 		if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0)
@@ -133,16 +133,11 @@
 			 */
 			size = getpagesize();
 		}
-#ifdef TS5300
-		// FIXME: Wrong place for this decision
-		// FIXME: This should be autodetected. It is trivial.
-		flash_baseaddr = 0x9400000;
-#else
-		flash_baseaddr = (0xffffffff - size + 1);
-#endif
+		if (!flashbase)
+			flashbase = (0xffffffff - size + 1);
 
 		bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
-			    fd_mem, (off_t) flash_baseaddr);
+			    fd_mem, (off_t) flashbase);
 		if (bios == MAP_FAILED) {
 			perror("Can't mmap memory using " MEM_DEV);
 			exit(1);
@@ -167,7 +162,7 @@
 		return NULL;
 
 	printf("Found chip \"%s %s\" (%d KB) at physical address 0x%lx.\n",
-	       flash->vendor, flash->name, flash->total_size, flash_baseaddr);
+	       flash->vendor, flash->name, flash->total_size, flashbase);
 	return flash;
 }
 




From svn at coreboot.org  Wed Dec  3 22:25:44 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 03 Dec 2008 21:25:44 -0000
Subject: [coreboot] #109: flash base autodetection on AMD SC520
In-Reply-To: <042.dd2a4ac52c99eda42cddbbfeec557d3f@coreboot.org>
References: <042.dd2a4ac52c99eda42cddbbfeec557d3f@coreboot.org>
Message-ID: <051.ea49ce5c907217defcfd9eb51162d481@coreboot.org>

#109: flash base autodetection on AMD SC520
-------------------------+--------------------------------------------------
    Reporter:  stepan    |         Owner:  stepan                  
        Type:  defect    |        Status:  closed                  
    Priority:  major     |     Milestone:  flashrom v1.0           
   Component:  flashrom  |       Version:                          
  Resolution:  fixed     |      Keywords:                          
Dependencies:            |   Patchstatus:  patch has been committed
-------------------------+--------------------------------------------------
Changes (by stuge):

  * status:  new => closed
  * patchstatus:  patch needs work => patch has been committed
  * resolution:  => fixed


Comment:

 r3790

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/109#comment:4>
coreboot <http://www.coreboot.org/>


From stephan.guilloux at free.fr  Wed Dec  3 22:33:43 2008
From: stephan.guilloux at free.fr (Stephan GUILLOUX)
Date: Wed, 03 Dec 2008 22:33:43 +0100
Subject: [coreboot] [PATCH] flashrom patch for partial flash read #2
In-Reply-To: <4935E652.4000107@gmx.net>
References: <4935DB1B.6070803@free.fr> <4935E652.4000107@gmx.net>
Message-ID: <4936FB37.8030503@free.fr>


>> +static int read_flash(struct flashchip *flash, uint8_t *buf, uint32_t offset, uint32_t length)
>> +{
>> +	int total_size = flash->total_size * 1024;
>>   
>>     
>
> total_size should be unsigned.
>   
Agreed, but found some inconsistencies for total_size :
- "size_t" is used, like in map_flash_registers()
- "int" is used, like in verify_flash()
Anyway, the best would be to use "size_t", not "unsigned int" or 
"unsigned long".

    Stephan.




From svn at coreboot.org  Wed Dec  3 22:39:56 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  3 Dec 2008 22:39:56 +0100
Subject: [coreboot] r3791 - trunk/util/flashrom
Message-ID: <mailman.2537.1355071447.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-12-03 22:39:56 +0100 (Wed, 03 Dec 2008)
New Revision: 3791

Modified:
   trunk/util/flashrom/flashrom.c
Log:
flashrom: Fix bug in r3790

If flashbase was set before probe_flash() it would only ever be used once, for
the very first flash chip probe.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-12-03 21:24:40 UTC (rev 3790)
+++ trunk/util/flashrom/flashrom.c	2008-12-03 21:39:56 UTC (rev 3791)
@@ -105,7 +105,7 @@
 {
 	volatile uint8_t *bios;
 	struct flashchip *flash;
-	unsigned long size;
+	unsigned long base, size;
 
 	for (flash = first_flash; flash && flash->name; flash++) {
 		if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0)
@@ -133,11 +133,10 @@
 			 */
 			size = getpagesize();
 		}
-		if (!flashbase)
-			flashbase = (0xffffffff - size + 1);
 
+		base = flashbase ? flashbase : (0xffffffff - size + 1);
 		bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
-			    fd_mem, (off_t) flashbase);
+			    fd_mem, (off_t) base);
 		if (bios == MAP_FAILED) {
 			perror("Can't mmap memory using " MEM_DEV);
 			exit(1);
@@ -162,7 +161,8 @@
 		return NULL;
 
 	printf("Found chip \"%s %s\" (%d KB) at physical address 0x%lx.\n",
-	       flash->vendor, flash->name, flash->total_size, flashbase);
+	       flash->vendor, flash->name, flash->total_size, base);
+	flashbase = base;
 	return flash;
 }
 




From joe at settoplinux.org  Wed Dec  3 23:00:04 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 03 Dec 2008 17:00:04 -0500
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and
 AMD 690 Chipset source code for Coreboot]
In-Reply-To: <4936D9A0.3080808@stockwith.co.uk>
References: <49368DEF.9020409@assembler.cz> <4936C752.1000900@gmx.net>
	<a5a4264b1edae71b943de65be3d14871@imap.1and1.com>
	<4936D9A0.3080808@stockwith.co.uk>
Message-ID: <f6bab6776bc55c5741488569cb6bf7c6@imap.1and1.com>




On Wed, 03 Dec 2008 19:10:24 +0000, Chris Lingard <chris at stockwith.co.uk>
wrote:
> Joseph Smith wrote:
>>
>>
>> On Wed, 03 Dec 2008 18:52:18 +0100, Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>>> Hi Rudolf,
>>>
>>> the links in the forwarded mail look a lot like phishing related stuff.
>>> Where did you find that press release?
>>>
>> It was an email. I got, because I am on the AMD embedded developers
> mailing
>> list. I will forward the html version to you.
>>
> 
> If that is a press release, for general release; can I have a copy and
> publish it on www.groklaw.net
> 
Here is the html link:
http://links.mkt426.com/servlet/MailView?ms=MjI5NTQ0MQS2&r=MTUxNjMzMTU4NDgS1

But your going to have to ask AMD about publishing it. 

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From stepan at coresystems.de  Wed Dec  3 23:02:42 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 3 Dec 2008 23:02:42 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <4936C92A.4060106@cosmicpenguin.net>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>
	<4936C696.8090404@gmx.net> <4936C92A.4060106@cosmicpenguin.net>
Message-ID: <17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>



On 03.12.2008, at 19:00, Jordan Crouse <jordan at cosmicpenguin.net> wrote:

> Carl-Daniel Hailfinger wrote:
>> On 03.12.2008 12:48, Stefan Reinauer wrote:
>>> Carl-Daniel Hailfinger wrote:
>>>
>>>> LAR currently overwrites the top 13 bytes (0xfffff3-0xffffff) of  
>>>> the
>>>> bootblock with zeros, then it stores the ROM size in  
>>>> 0xfffff4-0xfffff7.
>>>> The top 8 bytes are unused in that scheme.
>>>> Leave the top 8 bytes as they are and allow us to store something  
>>>> in
>>>> there during the bootblock build process. The byte at 0xfffff3 is  
>>>> 0xff
>>>> by default on x86 and setting it to 0 is not needed.
>>>>
>>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net 
>>>> >
>>>>
>>> Nack.
>>>
>>> They're unused, and until they are used, they should be cleared to a
>>> consistent state.
>>>
>> They are already cleared by arch/x86/stage0_common.S. Having to clear
>> them in the LAR would mean the code in stage0_common.S is crap and  
>> needs
>> to be fixed.
>
> Not necessarily.  This is a userland utility, so there is no real  
> penalty for making extra sure that the area is in a valid state.   
> LAR shouldn't depend on the v3 code to do the right thing, nor  
> should the v3 code depend on LAR to do the right thing.

In fact the area is not completely clean due to the binutils  
workaround. We had "nicer" code there, and it broke on Ron's binutils,  
so we went to the current version. It works, so don't waste time  
fixing it.

Stefan



From phueper at hueper.net  Wed Dec  3 23:22:29 2008
From: phueper at hueper.net (Pattrick Hueper)
Date: Wed, 3 Dec 2008 23:22:29 +0100
Subject: [coreboot] [RFC] Here we go... the SLOF biosemu for coreboot-v3
Message-ID: <b5765cdf0812031422v5185d06ew3a676188ae5a7567@mail.gmail.com>

Hi,

as mailed earlier, i took the IBM SLOF biosemu code that i wrote for
IBM and included it into coreboot-v3.
The SLOF code is opensourced under a BSD license at
http://www.ibm.com/developerworks/power/pa-slof/

Here is my git repository containing the code:
git://patty-server2.hueper.net/coreboot-v3_biosemu

This repository is actually a git svn clone of the coreboot svn, with
the plain unmodified biosemu copied from SLOF and my integration
patches for coreboot-v3 on top of it. (starting with a commit "add
.gitignore")

I know that the current state is neither very clean nor very nice from
a patch point of view... i wanted to create a state where i could stay
as close as possible to the original sources while showing the steps
needed for coreboot-v3 integration.

If i compile this coreboot-v3 code for qemu it initialises a plain
unmodified cirrus card in qemu, which was my primary goal. I verified
this with a buildrom build with coreinfo as payload, which can use the
textmode to display its info.

There are some changes to the original x86emu code (adding bswap
opcodes, some debugging output, ...) which i needed for other PCI
cards initializations (IDE/Ethernet) but i still think they make sense
to be added to x86emu.

I am not quite sure where i would like to go from here, the code
obviously needs some cleanups, and as i said earlier i would love to
try to get it working in qemu-ppc since the code is designed to be
pretty much architecture independent (some basic functions are needed
but should be easy to port...  i already ported them to x86/coreboot
from ppc/OF)

If you would rather see a patch series, i can try to come up with a
git format-patch created patch series.

Comments very much welcome!

Cheers, Patty



From rminnich at gmail.com  Wed Dec  3 23:27:01 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 3 Dec 2008 14:27:01 -0800
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>
	<4936C696.8090404@gmx.net> <4936C92A.4060106@cosmicpenguin.net>
	<17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>
Message-ID: <13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>

On Wed, Dec 3, 2008 at 2:02 PM, Stefan Reinauer <stepan at coresystems.de> wrote:

> In fact the area is not completely clean due to the binutils workaround. We
> had "nicer" code there, and it broke on Ron's binutils, so we went to the
> current version. It works, so don't waste time fixing it.

In fact, if anything, can we please fix the cn700?

these cosmetic patches are not really helping anything.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Wed Dec  3 23:59:01 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Dec 2008 23:59:01 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>	
	<4936C696.8090404@gmx.net> <4936C92A.4060106@cosmicpenguin.net>	
	<17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>
	<13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>
Message-ID: <49370F35.9020602@gmx.net>

On 03.12.2008 23:27, ron minnich wrote:
> On Wed, Dec 3, 2008 at 2:02 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
>
>   
>> In fact the area is not completely clean due to the binutils workaround. We
>> had "nicer" code there, and it broke on Ron's binutils, so we went to the
>> current version. It works, so don't waste time fixing it.
>>     

Since the code works, it is pointless to overwrite the result of the
working code in LAR.


> In fact, if anything, can we please fix the cn700?
>   

I don't have the hardware, so I can't fix it. I did fix the C7 CAR code,
but beyond that I can't help.


> these cosmetic patches are not really helping anything.
>   

This patch is not cosmetic and it is needed to fix the broken heuristic
in flashrom for coreboot image detection.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Thu Dec  4 00:15:09 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Dec 2008 00:15:09 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <49370F35.9020602@gmx.net>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>
	<4936C696.8090404@gmx.net> <4936C92A.4060106@cosmicpenguin.net>
	<17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>
	<13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>
	<49370F35.9020602@gmx.net>
Message-ID: <20081203231509.576.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> This patch is not cosmetic and it is needed to fix the broken
> heuristic in flashrom for coreboot image detection.

Not at all.


//Peter



From sza2king at freemail.hu  Wed Dec  3 20:04:48 2008
From: sza2king at freemail.hu (Tamas Szabo)
Date: Wed, 03 Dec 2008 20:04:48 +0100
Subject: [coreboot] EPIA MII Tutorial for recent coreboot-v2
Message-ID: <4936D850.3030602@freemail.hu>

Hi,

Is there an up-to-date version of EPIA MII tutorial?

The one I found at http://www.coreboot.org/VIA_EPIA-MII seems to be 
outdated - even the referenced filenames are differ. Based on it I was 
not able to create the right ROM file.

If I just simply run buildtarget and make (assume that filo is already 
compiled and sits at the right place) the coreboot.rom is created. 
However it start with the ELF signature - is it right?

If I use filo from the svn it is compiles, however coreboot 'make' 
complains about the size.

The VGA bios extraction method say skip=12 but the doc in coreboot svn 
use skip=790528. Which one should I use?

Also, the description of the usage of VGA bios to create the 
coreboot.rom is quite unclear.

Can anyone help me, how can I build a usable bios for a few of my 
good-old EPIA MIIs?

Thanks in advance,

/sza2



From andy at openmoko.com  Wed Dec  3 23:37:34 2008
From: andy at openmoko.com (Andy Green)
Date: Wed, 03 Dec 2008 22:37:34 +0000
Subject: [coreboot] Fwd: Merging Qi with coreboot?
In-Reply-To: <20081203185306.9329.qmail@stuge.se>
References: <20081203155123.GA2896@excalibur.hozed.org>
	<4936AF10.3020103@openmoko.com>
	<13426df10812030841w181102c8nad6113ed802edb5@mail.gmail.com>
	<20081203185306.9329.qmail@stuge.se>
Message-ID: <49370A2E.5030701@openmoko.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Somebody in the thread at some point said:
| Sorry about the crossposting. Please let me know if you should be
| excluded.
|
|
| ron minnich wrote:
|> This is an interesting writeup (see link). I think they think
|> coreboot does lots of BIOS stuff.
|
| Andy Green wrote:
|> | wouldn't it make more sense to leverage the work begin done on
|> | Coreboot for x86?
|>
|> x86 and s3c device boot are very different, and we don't need to
|> take care about a lot of PC-centric BIOS business.
|
| Note that coreboot is not about being a BIOS, by design. The idea
| with coreboot since day 1 was to get Linux running as soon as
| possible and to let Linux handle as much as it could. This design
| goal seems to be shared by coreboot and Qi.

That sounds like it is the case.

| coreboot does not implement BIOS services, coreboot only does
| hardware initialization and then it hands over to another program,
| called the payload, which never returns.
|
| Linux can be used as payload, if you really do want a BIOS you can
| use the SeaBIOS payload, there are several lightweight bootloaders
| that can be payloads (FILO, GRUB 2, gPXE, 9load..) and simple
| applications can be built into payloads using libpayload.

The philosophy I plan to follow is the OS is the only payload we are
interested in.  Any applications would then be normal Linux apps in a
normal Linux rootfs.  We saw plenty of U-Boot specific code rot whereas
there are nice living libs for UI or applications in Linux, many users
can imagine to contribute normal Python apps, etc.

| While coreboot worked mostly for x86 small and large in the past, it
| has supported both alpha and power. In coreboot v3 we make an effort
| to keep everything arch clean to make support also for non-x86 easy.
|
| What steps does Qi need to take before it can hand over to Linux?

s3c processors from Samsung have a piece of magic SRAM, either 4K or 8K
bytes which gets filled from NAND or SD Card by magic at reset, then
jumped into.  This chunk of SRAM is called "steppingstone" by Samsung.
The task of the code in there is to init the SDRAM and pull the rest of
the bootloader (Qi binary is around 24KBytes currently), then jump into
that.  imx31 from Freescale is also using a similar scheme.

The mandates a specific architecture for the bootloader that you have to
cram a highly capable "first phase" code into the 4 or 8 K, for 6410
ours not only has SD driver but memory test and other bringup in there.
~ Then in the second phase, situation is more relaxed and we have ext2/3
filesystem support and other goodies in the rest of it.

If you want to extend coreboot to work with ARM go for it by all
means... Qi code is all GPL'd and in git

http://git.openmoko.org/?p=qi.git;a=summary

Take a look at src/phase2.c to see the flow into Linux.  I think you'll
find it's not only lean in the sources but quite tight as a binary.

- -Andy
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Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org

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From svn at coreboot.org  Thu Dec  4 00:36:48 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Dec 2008 00:36:48 +0100
Subject: [coreboot] r3792 - trunk/util/flashrom
Message-ID: <mailman.2538.1355071447.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-12-04 00:36:48 +0100 (Thu, 04 Dec 2008)
New Revision: 3792

Modified:
   trunk/util/flashrom/flashrom.c
Log:
flashrom: gcc thinks base could be used uninitialized, so shut it up.

Bug from r3791.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-12-03 21:39:56 UTC (rev 3791)
+++ trunk/util/flashrom/flashrom.c	2008-12-03 23:36:48 UTC (rev 3792)
@@ -105,7 +105,7 @@
 {
 	volatile uint8_t *bios;
 	struct flashchip *flash;
-	unsigned long base, size;
+	unsigned long base = 0, size;
 
 	for (flash = first_flash; flash && flash->name; flash++) {
 		if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0)




From svn at coreboot.org  Thu Dec  4 00:39:49 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Dec 2008 00:39:49 +0100
Subject: [coreboot] r1064 - coreboot-v3/arch/x86
Message-ID: <mailman.2539.1355071447.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-12-04 00:39:49 +0100 (Thu, 04 Dec 2008)
New Revision: 1064

Modified:
   coreboot-v3/arch/x86/stage0_common.S
Log:
Document unexpected clobbering of stage0 code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/arch/x86/stage0_common.S
===================================================================
--- coreboot-v3/arch/x86/stage0_common.S	2008-12-03 15:38:42 UTC (rev 1063)
+++ coreboot-v3/arch/x86/stage0_common.S	2008-12-03 23:39:49 UTC (rev 1064)
@@ -149,6 +149,7 @@
 	.byte	0xe9
 	.int	_stage0 - ( . + 2 )
 
+#warning Everything below this line and two bytes above this line is being clobbered by LAR. For the discussion about this, see the thread at www.coreboot.org/pipermail/coreboot/2008-December/042771.html
 	/* Note: The above jump is hand coded to work around bugs in binutils.
 	 * 5 bytes are used for a 3 byte instruction. This works because x86
 	 * is little endian and allows us to use supported 32 bit relocations




From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 00:40:57 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 00:40:57 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <20081203231509.576.qmail@stuge.se>
References: <4935E3A6.5060200@gmx.net>
	<493671FE.10407@coresystems.de>	<4936C696.8090404@gmx.net>
	<4936C92A.4060106@cosmicpenguin.net>	<17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>	<13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>	<49370F35.9020602@gmx.net>
	<20081203231509.576.qmail@stuge.se>
Message-ID: <49371909.9080806@gmx.net>

On 04.12.2008 00:15, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> This patch is not cosmetic and it is needed to fix the broken
>> heuristic in flashrom for coreboot image detection.
>>     
>
> Not at all.
>   

OK, I give up.

I documented this bug in r1064 if someone else ever stumbles on it.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Thu Dec  4 00:56:56 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 04 Dec 2008 00:56:56 +0100
Subject: [coreboot] [PATCH] inteltool: i965, i975,
	ICH8M and Darwin	support.
In-Reply-To: <20081203184629.GA29474@greenwood>
References: <493300AB.2000201@coresystems.de>
	<20081203184629.GA29474@greenwood>
Message-ID: <49371CC8.6000603@coresystems.de>

Uwe Hermann wrote:
> I was about to ack this, but it fails to build, see below. I also added
> a few smaller comments to the review, but the build issue is the only
> really important one.
>
>
> On Sun, Nov 30, 2008 at 10:07:55PM +0100, Stefan Reinauer wrote:
>   
>> +#ifndef DARWIN
>> +#include <sys/io.h>
>> +#else
>> +#include <DirectIO/darwinio.h>
>> +#endif
>>     
>
> Maybe a small paragraph with build instructions and URL for DirectIO
> etc. in the README/manpage would be good (that's for another patch though).
>   
Inteltool has no README yet. It seems it should have one.

The DirectIO code can be downloaded here:

http://www.coresystems.de/en/directio


>>  #define PCI_DEVICE_ID_INTEL_82845	0x1a30
>>  #define PCI_DEVICE_ID_INTEL_82945P	0x2770
>>  #define PCI_DEVICE_ID_INTEL_82945GM	0x27a0
>> +#define PCI_DEVICE_ID_INTEL_PM965       0x2a00
>> +#define PCI_DEVICE_ID_INTEL_82975X      0x277c
>>     
>
> These two use spaces, not TABs, and are thus not properly aligned,
> please change to TABs in the commit.
>   

fixed.

>>  	for (i = 0; i < size; i += 4) {
>> +#ifdef DARWIN
>> +		if (i==0x14) {
>>     
>                      ^ ^ 
>            add spaces here, please.
>
>
>   
fixed.
>> +			/* Reading this register will hang a macbook pro */
>> +			printf("pmbase+0x%04x: 0xXXXXXXXX\n", i);
>>     
>
> Any idea why? Hardware problem or OS problem? Does Linux on Apple
> hardware have the same issue? If yes, the "#ifdef DARWIN" check may
> not be correct/complete.
>   
I am not sure yet. There is no Linux on that box. It might even be a
generic ICH8 thing. Time will show and bring a patch when we find out.

>> +void unmap_physical(void *virt_addr, int len)
>> +{
>> +       munmap((void *)rcba, size);
>> +}
>>     
>
> This part fails to build, as 'rcba' is never defined. I guess 'virt_addr' is
> the correct thing to use here (?) If yes, the (void *) cast is not
> needed, too, I think.
>
> Also, s/size/len/, otherwise it won't build.
>   
awkward and fixed.

>> Index: Makefile
>> ===================================================================
>> --- Makefile	(revision 3783)
>> +++ Makefile	(working copy)
>> @@ -29,6 +29,13 @@
>>  
>>  OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o
>>  
>> +OS_ARCH	= $(shell uname)
>> +ifeq ($(OS_ARCH), Darwin)
>> +CFLAGS += -DDARWIN -I/usr/local/include 
>> +LDFLAGS = -framework IOKit -framework DirectIO -L/usr/local/lib -lpci -lz
>>     
>
> Maybe /usr/local should be easily configurable (adding it as variable,
> or reusing PREFIX or so)?
>   
The default installation of pciutils is /usr/local/, and usually on OSX
it would be installed as a .pkg.
Using PREFIX is wrong, because that's the install prefix of inteltool,
not of pciutils.

While the above always works in the default case and in the case that
pciutils' PREFIX was just /usr, one might say the right way to do this
is by looking for pciutils on the system, ie with autoconf. But that's
outside of the scope of this patch.
>> +# OBJS += darwinio.o
>> +endif
>> +
>>  all: pciutils dep $(PROGRAM)
>>  
>>  $(PROGRAM): $(OBJS)
>> @@ -41,10 +48,10 @@
>>  	rm -f .dependencies
>>  
>>  dep:
>> -	@$(CC) -MM *.c > .dependencies
>> +	@$(CC) $(CFLAGS) -MM *.c > .dependencies
>>  
>>  pciutils:
>> -	@echo; echo -n "Checking for pciutils and zlib... "
>> +	@echo; /bin/echo -n "Checking for pciutils and zlib... "
>>     
>
> Why this change? If it's needed, the "@echo" should also have the
> full path then?
>   
The builtin echo does not do -n. Not sure why. This is GNU Make 3.81
from OSX 10.5.5/Xcode 3.1

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From rminnich at gmail.com  Thu Dec  4 01:28:07 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 3 Dec 2008 16:28:07 -0800
Subject: [coreboot] Fwd: Merging Qi with coreboot?
In-Reply-To: <49370A2E.5030701@openmoko.com>
References: <20081203155123.GA2896@excalibur.hozed.org>
	<4936AF10.3020103@openmoko.com>
	<13426df10812030841w181102c8nad6113ed802edb5@mail.gmail.com>
	<20081203185306.9329.qmail@stuge.se> <49370A2E.5030701@openmoko.com>
Message-ID: <13426df10812031628u6f9466d9y9d81cfaa1f15e68f@mail.gmail.com>

On Wed, Dec 3, 2008 at 2:37 PM, Andy Green <andy at openmoko.com> wrote:

> The philosophy I plan to follow is the OS is the only payload we are
> interested in.  Any applications would then be normal Linux apps in a
> normal Linux rootfs.  We saw plenty of U-Boot specific code rot whereas
> there are nice living libs for UI or applications in Linux, many users
> can imagine to contribute normal Python apps, etc.

yep, that is pretty much what the original plan with linuxbios was in
1999, so I love the plan :-)

It makes sense to do this as opposed to make the boot loader
complicated. Every boot loader that tries anything fancy inevitably
turns into its own little OS, as witness OFW, U-boot, EFI, Alpha boot
loader, and so on.

I have to get an open moko now!


> s3c processors from Samsung have a piece of magic SRAM, either 4K or 8K
> bytes which gets filled from NAND or SD Card by magic at reset, then
> jumped into.  This chunk of SRAM is called "steppingstone" by Samsung.
> The task of the code in there is to init the SDRAM and pull the rest of
> the bootloader (Qi binary is around 24KBytes currently), then jump into
> that.  imx31 from Freescale is also using a similar scheme.

neat.

> If you want to extend coreboot to work with ARM go for it by all
> means... Qi code is all GPL'd and in git
>
> http://git.openmoko.org/?p=qi.git;a=summary
>
> Take a look at src/phase2.c to see the flow into Linux.  I think you'll
> find it's not only lean in the sources but quite tight as a binary.

we'll see if anyone jumps on this. Thanks for the link troy.

Somehow this thread has gotten dropped across two lists, so we should
probably close it down before people not on each list get annoyed.

Thanks again

ron



From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 01:55:35 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 01:55:35 +0100
Subject: [coreboot] [PATCH] v3: make inline asm declarations consistent
In-Reply-To: <48C2F4A0.5060109@gmx.net>
References: <48C2D067.4010309@gmx.net> <48C2E941.1020506@coresystems.de>
	<48C2F4A0.5060109@gmx.net>
Message-ID: <49372A87.8080202@gmx.net>

On 06.09.2008 23:22, Carl-Daniel Hailfinger wrote:
> On 06.09.2008 22:34, Stefan Reinauer wrote:
>   
>> Carl-Daniel Hailfinger wrote:
>>   
>>     
>>> v3 uses all combinations of __asm__, asm, __volatile__, volatile and
>>> single variations to declare inline asm statements. "asm" is a GNU C
>>> extension, while volatile is ANSI C. That means:
>>> - __volatile__ can be replaced by volatile unless you use a pure K&R
>>> compiler.
>>> - asm is not a reserved keyword and should be replaced by __asm__.
>>> As a bonus, grepping for __asm__ returns less hits than asm because asm
>>> is also used as a normal word in comments.
>>>
>>>     
>>>       
>> What are the implications of this? I think we should either go __asm__
>> __volatile__ or asm volatile for the sake of looking at the code without
>> eye cancer, but not mix it.
>>
>> We're absolutely gcc specific, so discussing about asm not being
>> reserved sounds a bit vain. Also, is __asm__ reserved? Reserved by whom?
>> I know more compilers that know about asm than __asm__ if we're really
>> trying to become non-GNU-centric.
>>
>> What's the goal of your patch?
>>   
>>     
>
> Two goals:
> 1. __volatile__ is pointless since 1983 (ANSI-C). No idea why anyone
> uses it.
> 2. Neither __asm__ nor asm are reserved. Grepping for asm turns up lots
> of stuff that is not inline asm, so using __asm__ eases grepping.
>
> If you prefer asm volatile, tell me. I'll prepare an updated patch.
>   

Stefan, do you prefer "asm volatile" or "__asm__ __volatile__"? From
your mail, it seems you prefer "asm volatile", but I want to make sure I
get it right.
This patch has been pending for quite a while and it would be great if I
could get rid of it.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Thu Dec  4 01:58:11 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Dec 2008 01:58:11 +0100
Subject: [coreboot] r3793 - trunk/util/flashrom
Message-ID: <mailman.2540.1355071447.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-12-04 01:58:10 +0100 (Thu, 04 Dec 2008)
New Revision: 3793

Modified:
   trunk/util/flashrom/flash.h
Log:
Add RDID/REMS IDs for the following flash chips:

SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64

Straight from the data sheets.

The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.

Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h	2008-12-03 23:36:48 UTC (rev 3792)
+++ trunk/util/flashrom/flash.h	2008-12-04 00:58:10 UTC (rev 3793)
@@ -290,10 +290,20 @@
 #define SST_25WF010		0x2502
 #define SST_25WF020		0x2503
 #define SST_25WF040		0x2504
+#define SST_25VF512A_REMS	0x48	/* REMS or RES opcode */
+#define SST_25VF010_REMS	0x49	/* REMS or RES opcode */
+#define SST_25VF020_REMS	0x43	/* REMS or RES opcode */
+#define SST_25VF040_REMS	0x44	/* REMS or RES opcode */
+#define SST_25VF040B		0x258D
+#define SST_25VF040B_REMS	0x8D	/* REMS or RES opcode */
+#define SST_25VF080_REMS	0x80	/* REMS or RES opcode */
+#define SST_25VF080B		0x258E
+#define SST_25VF080B_REMS	0x8E	/* REMS or RES opcode */
 #define SST_25VF016B		0x2541
 #define SST_25VF032B		0x254A
-#define SST_25VF040B		0x258D
-#define SST_25VF080B		0x258E
+#define SST_25VF032B_REMS	0x4A	/* REMS or RES opcode */
+#define SST_26VF016		0x2601
+#define SST_26VF032		0x2602
 #define SST_27SF512		0xA4
 #define SST_27SF010		0xA5
 #define SST_27SF020		0xA6
@@ -378,6 +388,9 @@
 #define W_25X20			0x3012
 #define W_25X40			0x3013
 #define W_25X80			0x3014
+#define W_25X16			0x3015
+#define W_25X32			0x3016
+#define W_25X64			0x3017
 #define W_29C011		0xC1
 #define W_29C020C		0x45
 #define W_29C040P		0x46




From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 01:58:39 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 01:58:39 +0100
Subject: [coreboot] [PATCH] flashrom: Add a bunch of new IDs
In-Reply-To: <492F581F.7080003@gmx.net>
References: <492F581F.7080003@gmx.net>
Message-ID: <49372B3F.5040404@gmx.net>

On 28.11.2008 03:31, Carl-Daniel Hailfinger wrote:
> Add RDID/REMS IDs for the following flash chips:
>
> SST_25VF512A_REMS
> SST_25VF010_REMS
> SST_25VF020_REMS
> SST_25VF040_REMS
> SST_25VF040B_REMS
> SST_25VF080_REMS
> SST_25VF080B_REMS
> SST_25VF032B_REMS
> SST_26VF016
> SST_26VF032
> W_25X16
> W_25X32
> W_25X64
>
> Straight from the data sheets.
>
> The REMS IDs help in case the RDID opcode is unavailable (due to opcode
> lockdown) or unsupported by the chip.
>
> Some day, we need to pair probe functions together with IDs. Multiple
> pairs can exist per chip and duplicating chip definitions does not
> really make sense.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

Committed in r3793.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From coreboot at zl2tod.net  Thu Dec  4 02:49:00 2008
From: coreboot at zl2tod.net (Mark Robinson)
Date: Thu, 04 Dec 2008 14:49:00 +1300
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and
 AMD 690 Chipset source code for Coreboot]
In-Reply-To: <f6bab6776bc55c5741488569cb6bf7c6@imap.1and1.com>
References: <49368DEF.9020409@assembler.cz> <4936C752.1000900@gmx.net>
	<a5a4264b1edae71b943de65be3d14871@imap.1and1.com>
	<4936D9A0.3080808@stockwith.co.uk>
	<f6bab6776bc55c5741488569cb6bf7c6@imap.1and1.com>
Message-ID: <4937370C.8060403@zl2tod.net>

Joseph Smith wrote:
 > On Wed, 03 Dec 2008 19:10:24 +0000, Chris Lingard <chris at stockwith.co.uk>
 > wrote:
 >> Joseph Smith wrote:
 >>> On Wed, 03 Dec 2008 18:52:18 +0100, Carl-Daniel Hailfinger
 >>> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
 >>>> Hi Rudolf,
 >>>> the links in the forwarded mail look a lot like phishing related stuff.
 >>>> Where did you find that press release?
 >>> It was an email. I got, because I am on the AMD embedded developers
 >> mailing
 >>> list. I will forward the html version to you.
 >> If that is a press release, for general release; can I have a copy and
 >> publish it on www.groklaw.net
 > Here is the html link:
 > <snippage>
 > But your going to have to ask AMD about publishing it.

Here's a much better link:

http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_15872,00.html

Rudolf: a number of viruses cause this kind of thing.





From aaron.lwe at gmail.com  Thu Dec  4 04:02:30 2008
From: aaron.lwe at gmail.com (aaron lwe)
Date: Thu, 4 Dec 2008 11:02:30 +0800
Subject: [coreboot] [PATCH] fix qemu no screen problem when with -std-vga
	switch
Message-ID: <ff277c2e0812031902o7ec8122ase0df1b4d9f1bc2a3@mail.gmail.com>

When running qemu with -std-vga switch using coreboot, qemu's screen
window will disappear. It's caused by no vga initialization for
std-vga card. The patch below adds a driver structure to make std-vga
card work.

Index: src/mainboard/emulation/qemu-x86/mainboard.c
===================================================================
--- src/mainboard/emulation/qemu-x86/mainboard.c	(revision 3789)
+++ src/mainboard/emulation/qemu-x86/mainboard.c	(working copy)
@@ -35,6 +35,12 @@
 	.device = 0x00b8,
 };

+static const struct pci_driver vga_driver_stdvga __pci_driver = {
+	.ops = &vga_operations,
+	.vendor = 0x1234,
+	.device = 0x1111,
+};
+
 struct chip_operations mainboard_emulation_qemu_x86_ops = {
 	CHIP_NAME("QEMU Mainboard")
 };

Signed-off-by: Aaron Lwe <aaron.lwe at gmail.com>

-Aaron



From jordan at cosmicpenguin.net  Thu Dec  4 04:29:39 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Wed, 03 Dec 2008 20:29:39 -0700
Subject: [coreboot] [RFC] Here we go... the SLOF biosemu for coreboot-v3
In-Reply-To: <b5765cdf0812031422v5185d06ew3a676188ae5a7567@mail.gmail.com>
References: <b5765cdf0812031422v5185d06ew3a676188ae5a7567@mail.gmail.com>
Message-ID: <49374EA3.1030301@cosmicpenguin.net>

Pattrick Hueper wrote:
> Hi,
> 
> as mailed earlier, i took the IBM SLOF biosemu code that i wrote for
> IBM and included it into coreboot-v3.
> The SLOF code is opensourced under a BSD license at
> http://www.ibm.com/developerworks/power/pa-slof/
> 
> Here is my git repository containing the code:
> git://patty-server2.hueper.net/coreboot-v3_biosemu
> 
> This repository is actually a git svn clone of the coreboot svn, with
> the plain unmodified biosemu copied from SLOF and my integration
> patches for coreboot-v3 on top of it. (starting with a commit "add
> .gitignore")

For the git impared in the group (which is most everybody), I am 
attaching a patch between svn HEAD and Pattrick's tree.  Enjoy.

Jordan

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From aaron.lwe at gmail.com  Thu Dec  4 04:41:35 2008
From: aaron.lwe at gmail.com (aaron lwe)
Date: Thu, 4 Dec 2008 11:41:35 +0800
Subject: [coreboot] [PATCH] Avoid cross-device renames in build_opt_tbl
In-Reply-To: <49352499.6040302@gmx.net>
References: <49352499.6040302@gmx.net>
Message-ID: <ff277c2e0812031941p90f55d8t3946da8e7e49818a@mail.gmail.com>

> That's due to the rename being performed in build_opt_tbl. Renames can't
> be done across filesystems. I saw that problem in the original patch,
> but I didn't want to ruin the mood by complaining.

I see compiling errors more important than the mood.

>
> Anyway, here is a patch to fix it.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
> Index: LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c
> ===================================================================
> --- LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c      (Revision 3788)
> +++ LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c      (Arbeitskopie)
> @@ -11,7 +11,7 @@
>  #define INPUT_LINE_MAX 256
>  #define MAX_VALUE_BYTE_LENGTH 64
>
> -#define TMPFILE_TEMPLATE "/tmp/build_opt_tbl_XXXXXX"
> +#define TMPFILE_TEMPLATE ".XXXXXX"
>
>  static unsigned char cmos_table[4096];
>
> @@ -215,7 +215,7 @@
>        char *header=0;
>        FILE *fp;
>        int tmpfile;
> -       char tmpfilename[32];
> +       char *tmpfilename;
>        struct cmos_option_table *ct;
>        struct cmos_entries *ce;
>        struct cmos_enums *c_enums, *c_enums_start;
> @@ -485,7 +485,9 @@
>
>        /* See if we want to output a C source file */
>        if(option) {
> -               strcpy(tmpfilename, TMPFILE_TEMPLATE);
> +               tmpfilename = malloc(strlen(option) + strlen(TMPFILE_TEMPLATE) + 1);
> +               strcpy(tmpfilename, option);
> +               strcat(tmpfilename, TMPFILE_TEMPLATE);
>                tmpfile = mkstemp(tmpfilename);
>                if(tmpfile == -1) {
>                         perror("Error - Could not create temporary file");
> @@ -535,7 +537,9 @@
>                struct cmos_option_table *hdr;
>                struct lb_record *ptr, *end;
>
> -               strcpy(tmpfilename, TMPFILE_TEMPLATE);
> +               tmpfilename = malloc(strlen(header) + strlen(TMPFILE_TEMPLATE) + 1);
> +               strcpy(tmpfilename, header);
> +               strcat(tmpfilename, TMPFILE_TEMPLATE);
>                tmpfile = mkstemp(tmpfilename);
>                if(tmpfile == -1) {
>                        perror("Error - Could not create temporary file");
>
>

The patch works well for me and is much better than the statically
allocated method which will probablly cause other people complain due
to their very long path name.

Acked-by: Aaron Lwe <aaron.lwe at gmail.com>



From peter at stuge.se  Thu Dec  4 05:06:43 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Dec 2008 05:06:43 +0100
Subject: [coreboot] [PATCH] Avoid cross-device renames in build_opt_tbl
In-Reply-To: <49352499.6040302@gmx.net>
References: <49352499.6040302@gmx.net>
Message-ID: <20081204040643.30361.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> +		tmpfilename = malloc(strlen(option) + strlen(TMPFILE_TEMPLATE) + 1);
..
> +		tmpfilename = malloc(strlen(header) + strlen(TMPFILE_TEMPLATE) + 1);

Watch out for those exploits.


//Peter



From peter at stuge.se  Thu Dec  4 05:13:02 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Dec 2008 05:13:02 +0100
Subject: [coreboot] Darwin support
In-Reply-To: <49371CC8.6000603@coresystems.de>
References: <493300AB.2000201@coresystems.de>
	<20081203184629.GA29474@greenwood>
	<49371CC8.6000603@coresystems.de>
Message-ID: <20081204041302.31948.qmail@stuge.se>

Stefan Reinauer wrote:
> While the above always works in the default case and in the case that
> pciutils' PREFIX was just /usr, one might say the right way to do this
> is by looking for pciutils on the system, ie with autoconf. But that's
> outside of the scope of this patch.

Does the msrtool configure script run well on Darwin?


//Peter



From peter at stuge.se  Thu Dec  4 05:39:39 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Dec 2008 05:39:39 +0100
Subject: [coreboot] [PATCH] flashrom patch for partial flash read #2
In-Reply-To: <4936FB37.8030503@free.fr>
References: <4935DB1B.6070803@free.fr> <4935E652.4000107@gmx.net>
	<4936FB37.8030503@free.fr>
Message-ID: <20081204043939.6411.qmail@stuge.se>

Stephan GUILLOUX wrote:
> >>+static int read_flash(struct flashchip *flash, uint8_t *buf, uint32_t 
> >>offset, uint32_t length)
> >>+{
> >>+	int total_size = flash->total_size * 1024;
> >
> >total_size should be unsigned.
> 
> Agreed, but found some inconsistencies for total_size :

I disagree, this does not matter at all right now, and will not for
some time to come. Worry about it later.


//Peter



From Zheng.Bao at amd.com  Thu Dec  4 06:25:51 2008
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Thu, 4 Dec 2008 13:25:51 +0800
Subject: [coreboot] Patches for ACPI support on dbm690t (reset TALERT of
	ADT7461)
Message-ID: <DD1CC71B621B004FA76856E5129D6B170234160A@sbjgexmb1.amd.com>

The TALERT of ADT7461 should be pull back high if the temperature is within the limit. It is done by reading the register whose device address is 0xC. It is not trivial as it looks.



Signed-off-by:? Maggie Li <maggie.li at amd.com>
Reviewed-by:    Joe Bao <zheng.bao at amd.com>

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From rminnich at gmail.com  Thu Dec  4 07:24:11 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 3 Dec 2008 22:24:11 -0800
Subject: [coreboot] Patches for ACPI support on dbm690t (reset TALERT of
	ADT7461)
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B170234160A@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B170234160A@sbjgexmb1.amd.com>
Message-ID: <13426df10812032224l7a79eceet18bb74dded6800d8@mail.gmail.com>

One spelling change: hareware -> hardware.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Thank you

ron



From r.marek at assembler.cz  Thu Dec  4 08:44:08 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 04 Dec 2008 08:44:08 +0100
Subject: [coreboot] [Fwd: AMD Releases Documentation for AMD SB600 and
 AMD 690 Chipset source code for Coreboot]
In-Reply-To: <4937370C.8060403@zl2tod.net>
References: <49368DEF.9020409@assembler.cz>
	<4936C752.1000900@gmx.net>	<a5a4264b1edae71b943de65be3d14871@imap.1and1.com>	<4936D9A0.3080808@stockwith.co.uk>	<f6bab6776bc55c5741488569cb6bf7c6@imap.1and1.com>
	<4937370C.8060403@zl2tod.net>
Message-ID: <49378A48.90002@assembler.cz>

> Rudolf: a number of viruses cause this kind of thing.

Yes but this is a customer tracking ;)

Rudolf



From Zheng.Bao at amd.com  Thu Dec  4 09:48:27 2008
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Thu, 4 Dec 2008 16:48:27 +0800
Subject: [coreboot] BarCamp Beijing
Message-ID: <DD1CC71B621B004FA76856E5129D6B1702341710@sbjgexmb1.amd.com>

http://us.apachecon.com/c/accn2008/about

I am going to do a brief presentation on BarCamp Beijing. Hopefully more
people in China will know this project.





From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 10:02:20 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 10:02:20 +0100
Subject: [coreboot] BarCamp Beijing
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1702341710@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1702341710@sbjgexmb1.amd.com>
Message-ID: <49379C9C.4080408@gmx.net>

On 04.12.2008 09:48, Bao, Zheng wrote:
> http://us.apachecon.com/c/accn2008/about
>
> I am going to do a brief presentation on BarCamp Beijing. Hopefully more
> people in China will know this project.
>   

Great, thank you! If you need any help or pointers to other coreboot
presentations, please tell us.

(And I think it is cool that this coreboot presentation happens at the
Intel China Research Center.)

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From Zheng.Bao at amd.com  Thu Dec  4 10:23:13 2008
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Thu, 4 Dec 2008 17:23:13 +0800
Subject: [coreboot] BarCamp Beijing
In-Reply-To: <49379C9C.4080408@gmx.net>
References: <DD1CC71B621B004FA76856E5129D6B1702341710@sbjgexmb1.amd.com>
	<49379C9C.4080408@gmx.net>
Message-ID: <DD1CC71B621B004FA76856E5129D6B170234174A@sbjgexmb1.amd.com>

The presentation is what I want. Do you have a presentation for new
people,  focusing on the advantage of coreboot.

Joe

-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] 
Sent: Thursday, December 04, 2008 5:02 PM
To: Bao, Zheng
Cc: coreboot mailinglist
Subject: Re: [coreboot] BarCamp Beijing

On 04.12.2008 09:48, Bao, Zheng wrote:
> http://us.apachecon.com/c/accn2008/about
>
> I am going to do a brief presentation on BarCamp Beijing. Hopefully
more
> people in China will know this project.
>   

Great, thank you! If you need any help or pointers to other coreboot
presentations, please tell us.

(And I think it is cool that this coreboot presentation happens at the
Intel China Research Center.)

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/






From Qingpei.Wang at amd.com  Thu Dec  4 10:24:40 2008
From: Qingpei.Wang at amd.com (Wang, Qingpei)
Date: Thu, 4 Dec 2008 17:24:40 +0800
Subject: [coreboot] BarCamp Beijing
In-Reply-To: <49379C9C.4080408@gmx.net>
References: <DD1CC71B621B004FA76856E5129D6B1702341710@sbjgexmb1.amd.com>
	<49379C9C.4080408@gmx.net>
Message-ID: <DD1CC71B621B004FA76856E5129D6B1701D7E8D6@sbjgexmb1.amd.com>


Hi all,
  I am going together with Joe
Jason Wang
BeiJing Technology Development Center
Advanced Micro Devices (AMD)


-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Carl-Daniel
Hailfinger
Sent: Thursday, December 04, 2008 5:02 PM
To: Bao, Zheng
Cc: coreboot mailinglist
Subject: Re: [coreboot] BarCamp Beijing

On 04.12.2008 09:48, Bao, Zheng wrote:
> http://us.apachecon.com/c/accn2008/about
>
> I am going to do a brief presentation on BarCamp Beijing. Hopefully
more
> people in China will know this project.
>   

Great, thank you! If you need any help or pointers to other coreboot
presentations, please tell us.

(And I think it is cool that this coreboot presentation happens at the
Intel China Research Center.)

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/


--
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot





From stepan at coresystems.de  Thu Dec  4 10:59:09 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 04 Dec 2008 10:59:09 +0100
Subject: [coreboot] Darwin support
In-Reply-To: <20081204041302.31948.qmail@stuge.se>
References: <493300AB.2000201@coresystems.de>	<20081203184629.GA29474@greenwood>	<49371CC8.6000603@coresystems.de>
	<20081204041302.31948.qmail@stuge.se>
Message-ID: <4937A9ED.1000402@coresystems.de>

Peter Stuge wrote:
> Stefan Reinauer wrote:
>   
>> While the above always works in the default case and in the case that
>> pciutils' PREFIX was just /usr, one might say the right way to do this
>> is by looking for pciutils on the system, ie with autoconf. But that's
>> outside of the scope of this patch.
>>     
>
> Does the msrtool configure script run well on Darwin?
>   

Only a very quick test:

./configure
-n searching for compiler (gcc cc icc)...
./configure: line 28: seq: command not found
  using  in PATH
-n searching for install (install ginstall)...
./configure: line 28: seq: command not found
  using  in PATH

configured using the following settings:

VERSION=3766
CC=
CFLAGS= -Os -Wall -Werror
LDFLAGS=
INSTALL=
PREFIX=/usr/local

-n creating Makefile...
  done




-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866





From avg at icyb.net.ua  Thu Dec  4 11:11:09 2008
From: avg at icyb.net.ua (Andriy Gapon)
Date: Thu, 04 Dec 2008 12:11:09 +0200
Subject: [coreboot] [PATCH] inteltool: i965, i975,
	ICH8M and Darwin support.
In-Reply-To: <49371CC8.6000603@coresystems.de>
References: <493300AB.2000201@coresystems.de>	<20081203184629.GA29474@greenwood>
	<49371CC8.6000603@coresystems.de>
Message-ID: <4937ACBD.7020905@icyb.net.ua>

on 04/12/2008 01:56 Stefan Reinauer said the following:
> Uwe Hermann wrote:
...
>> On Sun, Nov 30, 2008 at 10:07:55PM +0100, Stefan Reinauer wrote:
...
>>> +			/* Reading this register will hang a macbook pro */
>>> +			printf("pmbase+0x%04x: 0xXXXXXXXX\n", i);
>>>     
>> Any idea why? Hardware problem or OS problem? Does Linux on Apple
>> hardware have the same issue? If yes, the "#ifdef DARWIN" check may
>> not be correct/complete.
>>   
> I am not sure yet. There is no Linux on that box. It might even be a
> generic ICH8 thing. Time will show and bring a patch when we find out.
> 


From avg at icyb.net.ua  Thu Dec  4 11:21:01 2008
From: avg at icyb.net.ua (Andriy Gapon)
Date: Thu, 04 Dec 2008 12:21:01 +0200
Subject: [coreboot] Darwin support
In-Reply-To: <4937A9ED.1000402@coresystems.de>
References: <493300AB.2000201@coresystems.de>	<20081203184629.GA29474@greenwood>	<49371CC8.6000603@coresystems.de>	<20081204041302.31948.qmail@stuge.se>
	<4937A9ED.1000402@coresystems.de>
Message-ID: <4937AF0D.3090901@icyb.net.ua>

on 04/12/2008 11:59 Stefan Reinauer said the following:
> Peter Stuge wrote:
>> Stefan Reinauer wrote:
>>   
>>> While the above always works in the default case and in the case that
>>> pciutils' PREFIX was just /usr, one might say the right way to do this
>>> is by looking for pciutils on the system, ie with autoconf. But that's
>>> outside of the scope of this patch.
>>>     
>> Does the msrtool configure script run well on Darwin?
>>   
> 
> Only a very quick test:
> 
> ./configure
> -n searching for compiler (gcc cc icc)...
> ./configure: line 28: seq: command not found
>   using  in PATH
> -n searching for install (install ginstall)...
> ./configure: line 28: seq: command not found
>   using  in PATH
> 
> configured using the following settings:
> 
> VERSION=3766
> CC=
> CFLAGS= -Os -Wall -Werror
> LDFLAGS=
> INSTALL=
> PREFIX=/usr/local
> 
> -n creating Makefile...
>   done

I tried it on FreeBSD with the following tweaks: replace seq with gseq
and explicitly use /usr/local/bin/bash to execute configure (it's not in
POSIX shell syntax):

$ bash ./configure
searching for compiler (gcc cc icc)...  using /usr/bin/gcc in PATH
searching for install (install ginstall)...  using /usr/bin/install in PATH
finding CFLAGS for libpci (from pciutils)...  using:  -Os -Wall -Werror
-I/usr/local/include
finding LDFLAGS for libpci (from pciutils)...  using:  -L/usr/local/lib
-lpci -lz

configured using the following settings:

VERSION=3770M
CC=gcc
CFLAGS= -Os -Wall -Werror -I/usr/local/include
LDFLAGS= -L/usr/local/lib -lpci -lz
INSTALL=install
PREFIX=/usr/local

creating Makefile...  done



-- 
Andriy Gapon



From patrick at georgi-clan.de  Thu Dec  4 11:48:01 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 04 Dec 2008 11:48:01 +0100
Subject: [coreboot] Darwin support
In-Reply-To: <4937A9ED.1000402@coresystems.de>
References: <493300AB.2000201@coresystems.de>
	<20081203184629.GA29474@greenwood>	<49371CC8.6000603@coresystems.de>
	<20081204041302.31948.qmail@stuge.se> <4937A9ED.1000402@coresystems.de>
Message-ID: <1228387681.3826.3.camel@linux-fikf.site>

Am Donnerstag, den 04.12.2008, 10:59 +0100 schrieb Stefan Reinauer:
> ./configure
> -n searching for compiler (gcc cc icc)...
> ./configure: line 28: seq: command not found
>   using  in PATH
> -n searching for install (install ginstall)...
That looks like "echo -n" - printf would be better

> ./configure: line 28: seq: command not found
>   using  in PATH
For this,
if [ `uname -s` = "Darwin" ]; then
?seq() {
if [ $# -eq 3 ]; then
  jot $(( ($3 - $1 + $2)/$2 )) $1 $3
else
  jot $2 $1 $2
fi
}
fi

should work. I'm not sure about the uname -s, and it should also cover
the BSDs (which also have jot, but not seq).
Also, the $(( )) syntax might or might not be supported, and probably
should be replaced by `echo ... | bc` or something like that.


Regards,
Patrick




From stepan at coresystems.de  Thu Dec  4 14:44:45 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 04 Dec 2008 14:44:45 +0100
Subject: [coreboot] [PATCH] inteltool: i965, i975,
	ICH8M and Darwin support.
In-Reply-To: <4937ACBD.7020905@icyb.net.ua>
References: <493300AB.2000201@coresystems.de>	<20081203184629.GA29474@greenwood>
	<49371CC8.6000603@coresystems.de> <4937ACBD.7020905@icyb.net.ua>
Message-ID: <4937DECD.70100@coresystems.de>

Hi Andriy,

excellent! This made me add the long overdue register descriptions for
the PMBASE area to the patch, which I can use very well for the project
I'm working on.

Attached is a new patch that should solve the issues the right way.



Andriy Gapon wrote:
> From publicly available ICH9 spec (I guess ICH8 is the same here):
>
> <quote>
> LV2 ? Level 2 Register
> I/O Address: PMBASE + 14h
> ...
> Reads to this register return all 0s, writes to this register have no
> effect. Reads to this
> register generate a ?enter a level 2 power state? (C2) to the clock
> control logic. This will
> cause the STPCLK# signal to go active, and stay active until a break
> event occurs.
> Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
> ...
> NOTE: This register should not be used by IA-64 processors or systems
> with more than 1 logical
>       processor, unless appropriate semaphoring software has been put in
> place to ensure that
>       all threads/processors are ready for the C2 state when the read to
> this register occurs.
> </quote>
>
> The subsequent byte registers are LV3, LV4, LV5 and for mobile version
> LV6 intended for entering C3, C4, C5 and C6 states.
>
>   


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From mylesgw at gmail.com  Thu Dec  4 15:00:32 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 4 Dec 2008 07:00:32 -0700
Subject: [coreboot] Resources and links
Message-ID: <6994AEB29D4D42908E54F1C8AA7E11CF@chimp>

I've been thinking about getting rid of the links in v3, or changing their
meaning.  I can't see anywhere that they're being used right now.

The problem is how to deal with k8.  It has "multiple links", but not in the
same sense as v3.  In v3, multiple links means logical connections to
multiple devices.  K8 has multiple physical connections, but only one
logical connection.

This is a problem for resource allocation (the current implementation as
well as my patch.)  The idea is that for every bridge resource gets all
matching resources from the sub-tree packed into it.  The problem is that
for k8 there can be multiple bridge resources of the same type, and to know
which resources to pack into it, you have to know which physical link they
are connected to.  At the same time, all the children are logically
connected to the same PCI.

This could be solved in several ways, but I'm hoping that there's an elegant
way that I haven't thought of yet.  Here are a couple I was thinking of:

1. Let links have resources, and make all bridge resources live there.
	I don't like this one because links aren't needed anywhere else, and
this just makes links larger.

2. Give bridges a function which returns the children under a resource.
	It's an extra function for all bridges, but most would just return
all children.

I'm sure there are myriad other ways.  I'm looking for one that will be easy
to explain and implement correctly.

Thanks,
Myles




From mylesgw at gmail.com  Thu Dec  4 15:38:37 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 4 Dec 2008 07:38:37 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>
	<49344EA4.9070208@cosmicpenguin.net>
	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>
	<49347342.6080504@cosmicpenguin.net>
	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>
	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>
	<534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
Message-ID: <2831fecf0812040638o6b740b83v33507aa9c30a623f@mail.gmail.com>

On Tue, Dec 2, 2008 at 8:05 PM, Marc Jones <marcj303 at gmail.com> wrote:

> On Tue, Dec 2, 2008 at 10:57 AM, Myles Watson <mylesgw at gmail.com> wrote:
> >
> >
> > On Tue, Dec 2, 2008 at 7:13 AM, Myles Watson <mylesgw at gmail.com> wrote:
> >>
> >> Jordan,
> >>
> >> Sorry I obviously missed the point of your questions.  I'd forgotten
> that
> >> the fix went in to make all devices found in the dts be "on the
> mainboard."
> >> Here's a new patch that updates the dts with that in mind.  It also
> fixes
> >> the subsystem_vendor, which was broken in the last patch.
> >>
> >> I appreciate the sanity check.
> >
> > This patch is updated so that qemu works with resource allocation in
> phases.
> > Here are the changes:
> >
> > 1. Add a dts for the northbridge so it can have its own ops.
> > 2. Separates the domain from the device resource code.
> > 3. Add new resources for the APIC and VGA area.
>
> Move the IOAPIC to the the 82371? I'm not sure if the LAPIC belongs in
> the northbridge on since every core needs one it might belong in the
> CPU but I think you only need to reserve the range once.
>

Can we put the LAPIC in the NB domain?  Hopefully we can reserve an area
that would cover any CPU connected to that NB.  Here's my current resource
list for qemu.  This is after resource assignment.

  PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit ffff
flags 80100 index 0
  PCI_DOMAIN: 0000 resource base fc000000 size 2001000 align 25 gran 0 limit
ffffffff flags 80200 index 1
  PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit
ffffffff flags e0000200 index 2
  PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit
ffffffff flags e0000200 index 3
   PCI: 00:00.0 resource base 0 size 0 align 0 gran 12 limit ffff flags
80100 index 0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index a
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff
flags c0040200 index 1
   PCI: 00:00.0 resource base c0000 size 6f40000 align 0 gran 0 limit 0
flags e0004200 index b
   PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags
e0000100 index 0
   PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit ffff flags
40000100 index 20
   PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit
ffffffff flags 40001200 index 10
   PCI: 00:02.0 resource base fe000000 size 1000 align 12 gran 12 limit
ffffffff flags 40000200 index 14
   PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags
40000100 index 10

Which APIC resource did you want to move into the 82371?

Thanks,
Myles
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From r.marek at assembler.cz  Thu Dec  4 15:51:36 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 04 Dec 2008 15:51:36 +0100
Subject: [coreboot] qemu dts fixes
In-Reply-To: <2831fecf0812040638o6b740b83v33507aa9c30a623f@mail.gmail.com>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>	<49344EA4.9070208@cosmicpenguin.net>	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>	<49347342.6080504@cosmicpenguin.net>	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>	<534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
	<2831fecf0812040638o6b740b83v33507aa9c30a623f@mail.gmail.com>
Message-ID: <4937EE78.3070809@assembler.cz>

> Can we put the LAPIC in the NB domain?  Hopefully we can reserve an area 
> that would cover any CPU connected to that NB.  Here's my current 
> resource list for qemu.  This is after resource assignment.

Random note: LAPIC is in each CPU. It has always same address in each CPU.

Rudolf



From uwe at hermann-uwe.de  Thu Dec  4 15:54:11 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 4 Dec 2008 15:54:11 +0100
Subject: [coreboot] [PATCH] inteltool: i965, i975,
	ICH8M and Darwin	support.
In-Reply-To: <49371CC8.6000603@coresystems.de>
References: <493300AB.2000201@coresystems.de>
	<20081203184629.GA29474@greenwood>
	<49371CC8.6000603@coresystems.de>
Message-ID: <20081204145411.GA19805@greenwood>

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Buids fine now.

Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Thu Dec  4 15:58:02 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 4 Dec 2008 15:58:02 +0100
Subject: [coreboot] [PATCH] inteltool: i965, i975,
	ICH8M and Darwin support.
In-Reply-To: <4937DECD.70100@coresystems.de>
References: <493300AB.2000201@coresystems.de>
	<20081203184629.GA29474@greenwood>
	<49371CC8.6000603@coresystems.de>
	<4937ACBD.7020905@icyb.net.ua> <4937DECD.70100@coresystems.de>
Message-ID: <20081204145802.GB19805@greenwood>

On Thu, Dec 04, 2008 at 02:44:45PM +0100, Stefan Reinauer wrote:
> Hi Andriy,
> 
> excellent! This made me add the long overdue register descriptions for
> the PMBASE area to the patch, which I can use very well for the project
> I'm working on.
> 
> Attached is a new patch that should solve the issues the right way.

Oops, didn't notice the new patch earlier, please ignore my other ACK
and commit this one.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From mylesgw at gmail.com  Thu Dec  4 15:59:44 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 4 Dec 2008 07:59:44 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <4937EE78.3070809@assembler.cz>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>	<49344EA4.9070208@cosmicpenguin.net>	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>	<49347342.6080504@cosmicpenguin.net>	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>	<534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
	<2831fecf0812040638o6b740b83v33507aa9c30a623f@mail.gmail.com>
	<4937EE78.3070809@assembler.cz>
Message-ID: <42F619BBB3D04CD6B4C3263CF32B8413@chimp>



> -----Original Message-----
> From: Rudolf Marek [mailto:r.marek at assembler.cz]
> Sent: Thursday, December 04, 2008 7:52 AM
> To: Myles Watson
> Cc: Marc Jones; coreboot at coreboot.org; jordan at cosmicpenguin.net
> Subject: Re: [coreboot] qemu dts fixes
> 
> > Can we put the LAPIC in the NB domain?  Hopefully we can reserve an area
> > that would cover any CPU connected to that NB.  Here's my current
> > resource list for qemu.  This is after resource assignment.
> 
> Random note: LAPIC is in each CPU. It has always same address in each CPU.

So would it be reasonable to have the domain reserve it, since having a
resource for each CPU at the same place could get confusing?  Do we have
LAPIC devices on any platforms in Coreboot, so that it could be reserved
there?

Thanks,
Myles




From svn at coreboot.org  Thu Dec  4 16:18:21 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Dec 2008 16:18:21 +0100
Subject: [coreboot] r3794 - trunk/util/inteltool
Message-ID: <mailman.2542.1355071448.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-12-04 16:18:20 +0100 (Thu, 04 Dec 2008)
New Revision: 3794

Modified:
   trunk/util/inteltool/Makefile
   trunk/util/inteltool/cpu.c
   trunk/util/inteltool/gpio.c
   trunk/util/inteltool/inteltool.c
   trunk/util/inteltool/inteltool.h
   trunk/util/inteltool/memory.c
   trunk/util/inteltool/pcie.c
   trunk/util/inteltool/powermgt.c
   trunk/util/inteltool/rootcmplx.c
Log:
Patch to util/inteltool:
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Modified: trunk/util/inteltool/Makefile
===================================================================
--- trunk/util/inteltool/Makefile	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/Makefile	2008-12-04 15:18:20 UTC (rev 3794)
@@ -29,6 +29,13 @@
 
 OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o
 
+OS_ARCH	= $(shell uname)
+ifeq ($(OS_ARCH), Darwin)
+CFLAGS += -DDARWIN -I/usr/local/include 
+LDFLAGS = -framework IOKit -framework DirectIO -L/usr/local/lib -lpci -lz
+# OBJS += darwinio.o
+endif
+
 all: pciutils dep $(PROGRAM)
 
 $(PROGRAM): $(OBJS)
@@ -41,25 +48,25 @@
 	rm -f .dependencies
 
 dep:
-	@$(CC) -MM *.c > .dependencies
+	@$(CC) $(CFLAGS) -MM *.c > .dependencies
 
 pciutils:
-	@echo; echo -n "Checking for pciutils and zlib... "
-	@$(shell ( echo "#include <pci/pci.h>";		   \
-		   echo "struct pci_access *pacc;";	   \
-		   echo "int main(int argc, char **argv)"; \
-		   echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c )
-	@$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null &&	\
-		echo "found." || ( echo "not found."; echo;		\
-		echo "Please install pciutils-devel and zlib-devel.";	\
-		echo "See README for more information."; echo;		\
+	@printf "\nChecking for pciutils and zlib... "
+	@$(shell ( printf "#include <pci/pci.h>\n";		\
+		   printf "struct pci_access *pacc;\n";		\
+		   printf "int main(int argc, char **argv)\n";	\
+		   printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c )
+	@$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null &&	  \
+		printf "found.\n" || ( printf "not found.\n\n"; 	  \
+		printf "Please install pciutils-devel and zlib-devel.\n"; \
+		printf "See README for more information.\n\n";		  \
 		rm -f .test.c .test; exit 1)
-	@rm -f .test.c .test
+	@rm -rf .test.c .test .test.dSYM
 
 install: $(PROGRAM)
-	$(INSTALL) $(PROGRAM) $(PREFIX)/sbin
-	mkdir -p $(PREFIX)/share/man/man8
-	$(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8
+	$(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin
+	mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8
+	$(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8
 
 .PHONY: all clean distclean dep pciutils
 

Modified: trunk/util/inteltool/cpu.c
===================================================================
--- trunk/util/inteltool/cpu.c	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/cpu.c	2008-12-04 15:18:20 UTC (rev 3794)
@@ -33,13 +33,18 @@
 	unsigned int ret;
 	unsigned int dummy2, dummy3, dummy4;
 	asm volatile ( 
-		"cpuid" 
-		: "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4)
+		"pushl %%ebx	\n"
+		"cpuid		\n"
+		"movl %%ebx, %1	\n"
+		"popl %%ebx	\n"
+		: "=a" (ret), "=r" (dummy2), "=c" (dummy3), "=d" (dummy4)
 		: "a" (op)
+		: "cc"
 	);
 	return ret;
 }
 
+#ifndef DARWIN
 int msr_readerror = 0;
 
 msr_t rdmsr(int addr)
@@ -72,6 +77,7 @@
 
 	return msr;
 }
+#endif
 
 int print_intel_core_msrs(void)
 {
@@ -273,12 +279,14 @@
 		return -1;
 	}
 
+#ifndef DARWIN
 	fd_msr = open("/dev/cpu/0/msr", O_RDWR);
 	if (fd_msr < 0) {
 		perror("Error while opening /dev/cpu/0/msr");
 		printf("Did you run 'modprobe msr'?\n");
 		return -1;
 	}
+#endif
 
 	printf("\n===================== SHARED MSRs (All Cores) =====================\n");
 
@@ -292,6 +300,7 @@
 	close(fd_msr);
 
 	for (core = 0; core < 8; core++) {
+#ifndef DARWIN
 		char msrfilename[64];
 		memset(msrfilename, 0, 64);
 		sprintf(msrfilename, "/dev/cpu/%d/msr", core);
@@ -303,7 +312,7 @@
 		 */
 		if (fd_msr < 0)
 			break;
-
+#endif
 		printf("\n====================== UNIQUE MSRs  (core %d) ======================\n", core);
 
 		for (i = 0; i < cpu->num_per_core_msrs; i++) {
@@ -312,13 +321,15 @@
 			       cpu->per_core_msrs[i].number, msr.hi, msr.lo,
 			       cpu->per_core_msrs[i].name);
 		}
-
+#ifndef DARWIN
 		close(fd_msr);
+#endif
 	}
 
+#ifndef DARWIN
 	if (msr_readerror)
 		printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
-
+#endif
 	return 0;
 }
 

Modified: trunk/util/inteltool/gpio.c
===================================================================
--- trunk/util/inteltool/gpio.c	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/gpio.c	2008-12-04 15:18:20 UTC (rev 3794)
@@ -18,7 +18,6 @@
  */
 
 #include <stdio.h>
-#include <sys/io.h>
 #include "inteltool.h"
 
 static const io_register_t ich0_gpio_registers[] = {
@@ -78,6 +77,26 @@
 	{ 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich8_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "GPIO_USE_SEL Override (LOW)" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "GP_SER_BLINK" },
+	{ 0x20, 4, "GP_SB_CMDSTS" },
+	{ 0x24, 4, "GP_SB_DATA" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
+};
+
+
 int print_gpios(struct pci_dev *sb)
 {
 	int i, size;
@@ -87,6 +106,11 @@
 	printf("\n============= GPIOS =============\n\n");
 
 	switch (sb->device_id) {
+	case PCI_DEVICE_ID_INTEL_ICH8M:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich8_gpio_registers;
+		size = ARRAY_SIZE(ich8_gpio_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH7:
 	case PCI_DEVICE_ID_INTEL_ICH7M:
 	case PCI_DEVICE_ID_INTEL_ICH7DH:

Modified: trunk/util/inteltool/inteltool.c
===================================================================
--- trunk/util/inteltool/inteltool.c	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/inteltool.c	2008-12-04 15:18:20 UTC (rev 3794)
@@ -21,9 +21,8 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <getopt.h>
-#include <sys/io.h>
 #include <fcntl.h>
-
+#include <sys/mman.h>
 #include "inteltool.h"
 
 static const struct {
@@ -33,6 +32,9 @@
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
@@ -44,8 +46,30 @@
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
 };
 
-int fd_mem;
+#ifndef DARWIN
+static int fd_mem;
 
+void *map_physical(unsigned long phys_addr, int len)
+{
+	void *virt_addr;
+
+	virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
+		    fd_mem, (off_t) phys_addr);
+	
+	if (virt_addr == MAP_FAILED) {
+		printf("Error mapping physical memory 0x%08x[0x%x]\n", phys_addr, len);
+		return NULL;
+	}
+
+	return virt_addr;
+}
+
+void unmap_physical(void *virt_addr, int len)
+{
+	munmap(virt_addr, len);
+}
+#endif
+
 void print_version(void)
 {
 	printf("inteltool v%s -- ", INTELTOOL_VERSION);
@@ -164,10 +188,12 @@
 		exit(1);
 	}
 
+#ifndef DARWIN
 	if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
 		perror("Can not open /dev/mem");
 		exit(1);
 	}
+#endif
 
 	pacc = pci_alloc();
 	pci_init(pacc);

Modified: trunk/util/inteltool/inteltool.h
===================================================================
--- trunk/util/inteltool/inteltool.h	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/inteltool.h	2008-12-04 15:18:20 UTC (rev 3794)
@@ -18,6 +18,14 @@
  */
 
 #include <stdint.h>
+#ifndef DARWIN
+#include <sys/io.h>
+#else
+/* DirectIO is available here:
+ * http://www.coresystems.de/en/directio
+ */
+#include <DirectIO/darwinio.h>
+#endif
 #include <pci/pci.h>
 
 #define INTELTOOL_VERSION "1.0"
@@ -33,17 +41,23 @@
 #define PCI_DEVICE_ID_INTEL_ICH7	0x27b8
 #define PCI_DEVICE_ID_INTEL_ICH7M	0x27b9
 #define PCI_DEVICE_ID_INTEL_ICH7MDH	0x27bd
+#define PCI_DEVICE_ID_INTEL_ICH8M	0x2815
 
 #define PCI_DEVICE_ID_INTEL_82845	0x1a30
 #define PCI_DEVICE_ID_INTEL_82945P	0x2770
 #define PCI_DEVICE_ID_INTEL_82945GM	0x27a0
+#define PCI_DEVICE_ID_INTEL_PM965	0x2a00
+#define PCI_DEVICE_ID_INTEL_82975X	0x277c
 
 #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
 
+#ifndef DARWIN
 typedef struct { uint32_t hi, lo; } msr_t;
+#endif
 typedef struct { uint16_t addr; int size; char *name; } io_register_t;
 
-extern int fd_mem;
+void *map_physical(unsigned long phys_addr, int len);
+void unmap_physical(void *virt_addr, int len);
 
 unsigned int cpuid(unsigned int op);
 int print_intel_core_msrs(void);

Modified: trunk/util/inteltool/memory.c
===================================================================
--- trunk/util/inteltool/memory.c	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/memory.c	2008-12-04 15:18:20 UTC (rev 3794)
@@ -20,8 +20,6 @@
 
 #include <stdio.h>
 #include <stdlib.h>
-#include <sys/mman.h>
-
 #include "inteltool.h"
 
 /*
@@ -31,15 +29,20 @@
 {
 	int i, size = (16 * 1024);
 	volatile uint8_t *mchbar;
-	uint32_t mchbar_phys;
+ 	uint64_t mchbar_phys;
 
 	printf("\n============= MCHBAR ============\n\n");
 
 	switch (nb->device_id) {
 	case PCI_DEVICE_ID_INTEL_82945GM:
 	case PCI_DEVICE_ID_INTEL_82945P:
+ 	case PCI_DEVICE_ID_INTEL_82975X:
 		mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
 		break;
+ 	case PCI_DEVICE_ID_INTEL_PM965:
+ 		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
+ 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+ 		break;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This northbrigde does not have MCHBAR.\n");
 		return 1;
@@ -48,22 +51,21 @@
 		return 1;
 	}
 
-	mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
-		      fd_mem, (off_t) mchbar_phys);
+	mchbar = map_physical(mchbar_phys, size);
 	
-	if (mchbar == MAP_FAILED) {
+	if (mchbar == NULL) {
 		perror("Error mapping MCHBAR");
 		exit(1);
 	}
 
-	printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys);
+	printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys);
 
 	for (i = 0; i < size; i += 4) {
 		if (*(uint32_t *)(mchbar + i))
 			printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
 	}
 
-	munmap((void *)mchbar, size);
+	unmap_physical((void *)mchbar, size);
 	return 0;
 }
 

Modified: trunk/util/inteltool/pcie.c
===================================================================
--- trunk/util/inteltool/pcie.c	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/pcie.c	2008-12-04 15:18:20 UTC (rev 3794)
@@ -19,8 +19,6 @@
 
 #include <stdio.h>
 #include <stdlib.h>
-#include <sys/mman.h>
-
 #include "inteltool.h"
 
 /*
@@ -30,15 +28,20 @@
 {
 	int i, size = (4 * 1024);
 	volatile uint8_t *epbar;
-	uint32_t epbar_phys;
+	uint64_t epbar_phys;
 
 	printf("\n============= EPBAR =============\n\n");
 
 	switch (nb->device_id) {
 	case PCI_DEVICE_ID_INTEL_82945GM:
 	case PCI_DEVICE_ID_INTEL_82945P:
+	case PCI_DEVICE_ID_INTEL_82975X:
 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
 		break;
+ 	case PCI_DEVICE_ID_INTEL_PM965:
+ 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
+ 		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
+ 		break;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This northbrigde does not have EPBAR.\n");
 		return 1;
@@ -47,21 +50,20 @@
 		return 1;
 	}
 
-	epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
-		     fd_mem, (off_t) epbar_phys);
+	epbar = map_physical(epbar_phys, size);
 	
-	if (epbar == MAP_FAILED) {
+	if (epbar == NULL) {
 		perror("Error mapping EPBAR");
 		exit(1);
 	}
 
-	printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys);
+	printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
 	for (i = 0; i < size; i += 4) {
 		if (*(uint32_t *)(epbar + i))
 			printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
 	}
 
-	munmap((void *)epbar, size);
+	unmap_physical((void *)epbar, size);
 	return 0;
 }
 
@@ -72,15 +74,20 @@
 {
 	int i, size = (4 * 1024);
 	volatile uint8_t *dmibar;
-	uint32_t dmibar_phys;
+	uint64_t dmibar_phys;
 
 	printf("\n============= DMIBAR ============\n\n");
 
 	switch (nb->device_id) {
 	case PCI_DEVICE_ID_INTEL_82945GM:
 	case PCI_DEVICE_ID_INTEL_82945P:
+	case PCI_DEVICE_ID_INTEL_82975X:
 		dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
 		break;
+ 	case PCI_DEVICE_ID_INTEL_PM965:
+ 		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
+ 		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
+ 		break;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This northbrigde does not have DMIBAR.\n");
 		return 1;
@@ -89,21 +96,20 @@
 		return 1;
 	}
 
-	dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
-		      fd_mem, (off_t) dmibar_phys);
+	dmibar = map_physical(dmibar_phys, size);
 	
-	if (dmibar == MAP_FAILED) {
+	if (dmibar == NULL) {
 		perror("Error mapping DMIBAR");
 		exit(1);
 	}
 
-	printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys);
+	printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
 	for (i = 0; i < size; i += 4) {
 		if (*(uint32_t *)(dmibar + i))
 			printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
 	}
 
-	munmap((void *)dmibar, size);
+	unmap_physical((void *)dmibar, size);
 	return 0;
 }
 
@@ -112,8 +118,8 @@
  */
 int print_pciexbar(struct pci_dev *nb)
 {
-	uint32_t pciexbar_reg;
-	uint32_t pciexbar_phys;
+	uint64_t pciexbar_reg;
+	uint64_t pciexbar_phys;
 	volatile uint8_t *pciexbar;
 	int max_busses, devbase, i;
 	int bus, dev, fn;
@@ -123,8 +129,13 @@
 	switch (nb->device_id) {
 	case PCI_DEVICE_ID_INTEL_82945GM:
 	case PCI_DEVICE_ID_INTEL_82945P:
+	case PCI_DEVICE_ID_INTEL_82975X:
 		pciexbar_reg = pci_read_long(nb, 0x48);
 		break;
+ 	case PCI_DEVICE_ID_INTEL_PM965:
+ 		pciexbar_reg = pci_read_long(nb, 0x60);
+ 		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
+ 		break;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("Error: This northbrigde does not have PCIEXBAR.\n");
 		return 1;
@@ -140,15 +151,15 @@
 
 	switch ((pciexbar_reg >> 1) & 3) {
 	case 0: // 256MB
-		pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		pciexbar_phys = pciexbar_reg & (0xff << 28);
 		max_busses = 256;
 		break;
 	case 1: // 128M
-		pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		pciexbar_phys = pciexbar_reg & (0x1ff << 27);
 		max_busses = 128;
 		break;
 	case 2: // 64M
-		pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		pciexbar_phys = pciexbar_reg & (0x3ff << 26);
 		max_busses = 64;
 		break;
 	default: // RSVD
@@ -156,12 +167,11 @@
 		return 1;
 	}	
 
-	printf("PCIEXBAR: 0x%08x\n", pciexbar_phys);
+	printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
 
-	pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ,
-		        MAP_SHARED, fd_mem, (off_t) pciexbar_phys);
+	pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
 	
-	if (pciexbar == MAP_FAILED) {
+	if (pciexbar == NULL) {
 		perror("Error mapping PCIEXBAR");
 		exit(1);
 	}
@@ -194,7 +204,7 @@
 		}
 	}
 
-	munmap((void *)pciexbar, (max_busses * 1024 * 1024));
+	unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));
 
 	return 0;
 }

Modified: trunk/util/inteltool/powermgt.c
===================================================================
--- trunk/util/inteltool/powermgt.c	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/powermgt.c	2008-12-04 15:18:20 UTC (rev 3794)
@@ -19,14 +19,137 @@
  */
 
 #include <stdio.h>
-#include <sys/io.h>
-
 #include "inteltool.h"
 
+static const io_register_t ich7_pm_registers[] = {
+	{ 0x00, 2, "PM1_STS" },
+	{ 0x02, 2, "PM1_EN" },
+	{ 0x04, 4, "PM1_CNT" },
+	{ 0x08, 4, "PM1_TMR" },
+	{ 0x0c, 4, "RESERVED" },
+	{ 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+	/* These registers return 0 on read, but reading them may cause
+	 * the system to enter C2/C3/C4 state, which might hang the system.
+	 */
+	{ 0x14, 1, "LV2 (Mobile/Ultra Mobile)" },
+	{ 0x15, 1, "LV3 (Mobile/Ultra Mobile)" },
+	{ 0x16, 1, "LV4 (Mobile/Ultra Mobile)" },
+#endif
+	{ 0x17, 1, "RESERVED" },
+	{ 0x18, 4, "RESERVED" },
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" },
+	{ 0x21, 1, "RESERVED" },
+	{ 0x22, 2, "RESERVED" },
+	{ 0x24, 4, "RESERVED" },
+	{ 0x28, 4, "GPE0_STS" },
+	{ 0x2C, 4, "GPE0_EN" },
+	{ 0x30, 4, "SMI_EN" },
+	{ 0x34, 4, "SMI_STS" },
+	{ 0x38, 2, "ALT_GP_SMI_EN" },
+	{ 0x3a, 2, "ALT_GP_SMI_STS" },
+	{ 0x3c, 4, "RESERVED" },
+	{ 0x40, 2, "RESERVED" },
+	{ 0x42, 1, "GPE_CNTL" },
+	{ 0x43, 1, "RESERVED" },
+	{ 0x44, 2, "DEVACT_STS" },
+	{ 0x46, 2, "RESERVED" },
+	{ 0x48, 4, "RESERVED" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
+	{ 0x51, 1, "RESERVED" },
+	{ 0x52, 2, "RESERVED" },
+	{ 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" },
+	{ 0x58, 4, "RESERVED" },
+	{ 0x5c, 4, "RESERVED" },
+	/* Here start the TCO registers */
+	{ 0x60, 2, "TCO_RLD" },
+	{ 0x62, 1, "TCO_DAT_IN" },
+	{ 0x63, 1, "TCO_DAT_OUT" },
+	{ 0x64, 2, "TCO1_STS" },
+	{ 0x66, 2, "TCO2_STS" },
+	{ 0x68, 2, "TCO1_CNT" },
+	{ 0x6a, 2, "TCO2_CNT" },
+	{ 0x6c, 2, "TCO_MESSAGE" },
+	{ 0x6e, 1, "TCO_WDCNT" },
+	{ 0x6f, 1, "RESERVED" },
+	{ 0x70, 1, "SW_IRQ_GEN" },
+	{ 0x71, 1, "RESERVED" },
+	{ 0x72, 2, "TCO_TMR" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
+static const io_register_t ich8_pm_registers[] = {
+	{ 0x00, 2, "PM1_STS" },
+	{ 0x02, 2, "PM1_EN" },
+	{ 0x04, 4, "PM1_CNT" },
+	{ 0x08, 4, "PM1_TMR" },
+	{ 0x0c, 4, "RESERVED" },
+	{ 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+	/* These registers return 0 on read, but reading them may cause
+	 * the system to enter Cx states, which might hang the system.
+	 */
+	{ 0x14, 1, "LV2 (Mobile)" },
+	{ 0x15, 1, "LV3 (Mobile)" },
+	{ 0x16, 1, "LV4 (Mobile)" },
+	{ 0x17, 1, "LV5 (Mobile)" },
+	{ 0x18, 1, "LV6 (Mobile)" },
+#endif
+	{ 0x19, 1, "RESERVED" },
+	{ 0x1a, 2, "RESERVED" },
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 1, "PM2_CNT (Mobile)" },
+	{ 0x21, 1, "RESERVED" },
+	{ 0x22, 2, "RESERVED" },
+	{ 0x24, 4, "RESERVED" },
+	{ 0x28, 4, "GPE0_STS" },
+	{ 0x2C, 4, "GPE0_EN" },
+	{ 0x30, 4, "SMI_EN" },
+	{ 0x34, 4, "SMI_STS" },
+	{ 0x38, 2, "ALT_GP_SMI_EN" },
+	{ 0x3a, 2, "ALT_GP_SMI_STS" },
+	{ 0x3c, 4, "RESERVED" },
+	{ 0x40, 2, "RESERVED" },
+	{ 0x42, 1, "GPE_CNTL" },
+	{ 0x43, 1, "RESERVED" },
+	{ 0x44, 2, "DEVACT_STS" },
+	{ 0x46, 2, "RESERVED" },
+	{ 0x48, 4, "RESERVED" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 1, "SS_CNT (Mobile)" },
+	{ 0x51, 1, "RESERVED" },
+	{ 0x52, 2, "RESERVED" },
+	{ 0x54, 4, "C3_RES (Mobile)" },
+	{ 0x58, 4, "C5_RES (Mobile)" },
+	{ 0x5c, 4, "RESERVED" },
+	/* Here start the TCO registers */
+	{ 0x60, 2, "TCO_RLD" },
+	{ 0x62, 1, "TCO_DAT_IN" },
+	{ 0x63, 1, "TCO_DAT_OUT" },
+	{ 0x64, 2, "TCO1_STS" },
+	{ 0x66, 2, "TCO2_STS" },
+	{ 0x68, 2, "TCO1_CNT" },
+	{ 0x6a, 2, "TCO2_CNT" },
+	{ 0x6c, 2, "TCO_MESSAGE" },
+	{ 0x6e, 1, "TCO_WDCNT" },
+	{ 0x6f, 1, "RESERVED" },
+	{ 0x70, 1, "SW_IRQ_GEN" },
+	{ 0x71, 1, "RESERVED" },
+	{ 0x72, 2, "TCO_TMR" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
 int print_pmbase(struct pci_dev *sb)
 {
-	int i, size = 0x80;
+	int i, size;
 	uint16_t pmbase;
+	const io_register_t *pm_registers;
 
 	printf("\n============= PMBASE ============\n\n");
 
@@ -36,7 +159,14 @@
 	case PCI_DEVICE_ID_INTEL_ICH7DH:
 	case PCI_DEVICE_ID_INTEL_ICH7MDH:
 		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+		pm_registers = ich7_pm_registers;
+		size = ARRAY_SIZE(ich7_pm_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_ICH8M:
+		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+		pm_registers = ich8_pm_registers;
+		size = ARRAY_SIZE(ich8_pm_registers);
+		break;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This southbridge does not have PMBASE.\n");
 		return 1;
@@ -47,8 +177,27 @@
 
 	printf("PMBASE = 0x%04x (IO)\n\n", pmbase);
 
-	for (i = 0; i < size; i += 4) {
-		printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i));
+	for (i = 0; i < size; i++) {
+		switch (pm_registers[i].size) {
+		case 4:
+			printf("pmbase+0x%04x: 0x%08x (%s)\n",
+				pm_registers[i].addr,
+				inl(pmbase+pm_registers[i].addr),
+				pm_registers[i].name);
+			break;
+		case 2:
+			printf("pmbase+0x%04x: 0x%04x     (%s)\n",
+				pm_registers[i].addr,
+				inw(pmbase+pm_registers[i].addr),
+				pm_registers[i].name);
+			break;
+		case 1:
+			printf("pmbase+0x%04x: 0x%02x       (%s)\n",
+				pm_registers[i].addr,
+				inb(pmbase+pm_registers[i].addr),
+				pm_registers[i].name);
+			break;
+		}
 	}
 
 	return 0;

Modified: trunk/util/inteltool/rootcmplx.c
===================================================================
--- trunk/util/inteltool/rootcmplx.c	2008-12-04 00:58:10 UTC (rev 3793)
+++ trunk/util/inteltool/rootcmplx.c	2008-12-04 15:18:20 UTC (rev 3794)
@@ -18,18 +18,8 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <errno.h>
-#include <fcntl.h>
-#include <unistd.h>
 #include <stdio.h>
-#include <string.h>
 #include <stdlib.h>
-#include <stdint.h>
-#include <getopt.h>
-#include <sys/mman.h>
-#include <sys/io.h>
-#include <pci/pci.h>
-
 #include "inteltool.h"
 
 int print_rcba(struct pci_dev *sb)
@@ -45,6 +35,7 @@
 	case PCI_DEVICE_ID_INTEL_ICH7M:
 	case PCI_DEVICE_ID_INTEL_ICH7DH:
 	case PCI_DEVICE_ID_INTEL_ICH7MDH:
+	case PCI_DEVICE_ID_INTEL_ICH8M:
 		rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 		break;
 	case PCI_DEVICE_ID_INTEL_ICH:
@@ -58,10 +49,9 @@
 		return 1;
 	}
 
-	rcba = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
-		    fd_mem, (off_t) rcba_phys);
+	rcba = map_physical(rcba_phys, size);
 	
-	if (rcba == MAP_FAILED) {
+	if (rcba == NULL) {
 		perror("Error mapping RCBA");
 		exit(1);
 	}
@@ -73,7 +63,7 @@
 			printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i));
 	}
 
-	munmap((void *)rcba, size);
+	unmap_physical((void *)rcba, size);
 	return 0;
 }
 




From stepan at coresystems.de  Thu Dec  4 16:18:41 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 04 Dec 2008 16:18:41 +0100
Subject: [coreboot] [PATCH] inteltool: i965, i975,
	ICH8M and Darwin support.
In-Reply-To: <20081204145802.GB19805@greenwood>
References: <493300AB.2000201@coresystems.de>
	<20081203184629.GA29474@greenwood>
	<49371CC8.6000603@coresystems.de>
	<4937ACBD.7020905@icyb.net.ua> <4937DECD.70100@coresystems.de>
	<20081204145802.GB19805@greenwood>
Message-ID: <4937F4D1.7090406@coresystems.de>

Uwe Hermann wrote:
> On Thu, Dec 04, 2008 at 02:44:45PM +0100, Stefan Reinauer wrote:
>   
>> Hi Andriy,
>>
>> excellent! This made me add the long overdue register descriptions for
>> the PMBASE area to the patch, which I can use very well for the project
>> I'm working on.
>>
>> Attached is a new patch that should solve the issues the right way.
>>     
>
> Oops, didn't notice the new patch earlier, please ignore my other ACK
> and commit this one.
>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
>
>
> Uwe.
>   
Thanks, r3794

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From r.marek at assembler.cz  Thu Dec  4 16:21:40 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 04 Dec 2008 16:21:40 +0100
Subject: [coreboot] qemu dts fixes
In-Reply-To: <42F619BBB3D04CD6B4C3263CF32B8413@chimp>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>	<49344EA4.9070208@cosmicpenguin.net>	<2831fecf0812011317k51f2e86es54da17927375b0cb@mail.gmail.com>	<49347342.6080504@cosmicpenguin.net>	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>	<534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
	<2831fecf0812040638o6b740b83v33507aa9c30a623f@mail.gmail.com>
	<4937EE78.3070809@assembler.cz>
	<42F619BBB3D04CD6B4C3263CF32B8413@chimp>
Message-ID: <4937F584.8060701@assembler.cz>

> So would it be reasonable to have the domain reserve it, since having a
> resource for each CPU at the same place could get confusing?  Do we have
> LAPIC devices on any platforms in Coreboot, so that it could be reserved
> there?

LAPIC is in any CPU post Pentium.

R.



From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 16:42:44 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 16:42:44 +0100
Subject: [coreboot] [PATCH] Avoid cross-device renames in build_opt_tbl
In-Reply-To: <20081204040643.30361.qmail@stuge.se>
References: <49352499.6040302@gmx.net> <20081204040643.30361.qmail@stuge.se>
Message-ID: <4937FA74.6060605@gmx.net>

On 04.12.2008 05:06, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> +		tmpfilename = malloc(strlen(option) + strlen(TMPFILE_TEMPLATE) + 1);
>>     
> ..
>   
>> +		tmpfilename = malloc(strlen(header) + strlen(TMPFILE_TEMPLATE) + 1);
>>     
>
> Watch out for those exploits.
>   

;-)

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mylesgw at gmail.com  Thu Dec  4 17:39:36 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 4 Dec 2008 09:39:36 -0700
Subject: [coreboot] [RFC] Here we go... the SLOF biosemu for coreboot-v3
In-Reply-To: <49374EA3.1030301@cosmicpenguin.net>
References: <b5765cdf0812031422v5185d06ew3a676188ae5a7567@mail.gmail.com>
	<49374EA3.1030301@cosmicpenguin.net>
Message-ID: <2831fecf0812040839r4033ea4au8a5fcab5923fcc1e@mail.gmail.com>

On Wed, Dec 3, 2008 at 8:29 PM, Jordan Crouse <jordan at cosmicpenguin.net>wrote:

> Pattrick Hueper wrote:
>
>> Hi,
>>
>> as mailed earlier, i took the IBM SLOF biosemu code that i wrote for
>> IBM and included it into coreboot-v3.
>> The SLOF code is opensourced under a BSD license at
>> http://www.ibm.com/developerworks/power/pa-slof/
>>
>> Here is my git repository containing the code:
>> git://patty-server2.hueper.net/coreboot-v3_biosemu
>>
>> This repository is actually a git svn clone of the coreboot svn, with
>> the plain unmodified biosemu copied from SLOF and my integration
>> patches for coreboot-v3 on top of it. (starting with a commit "add
>> .gitignore")
>>
>
> For the git impared in the group (which is most everybody), I am attaching
> a patch between svn HEAD and Pattrick's tree.  Enjoy.<http://www.coreboot.org/mailman/listinfo/coreboot>

This is the same patch minus:
- The typedefs in types.h and multiboot.h ( s/uintXX_t/uXX/g)
- The -g in the Makefile
- An unrelated comment in stage0.s

It applies and works the same as x86emu for me on SimNOW and qemu.

Thanks,
Myles
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From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 18:00:40 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 18:00:40 +0100
Subject: [coreboot] r3789 - trunk/coreboot-v2/util/options
In-Reply-To: <493537FE.6070102@gmx.net>
References: <20081202122816.21393gmx1@mx017.gmx.net>
	<49352C0A.5080105@gmx.net>	<20081202130204.28666.qmail@stuge.se>
	<493537FE.6070102@gmx.net>
Message-ID: <49380CB8.3050206@gmx.net>

On 02.12.2008 14:28, Carl-Daniel Hailfinger wrote:
> On 02.12.2008 14:02, Peter Stuge wrote:
>   
>> Carl-Daniel Hailfinger wrote:
>>   
>>     
>>> This will break if the path is longer than 234 bytes, whereas
>>> PATH_MAX on my Linux system is 4096.
>>>     
>>>       
>> Would obviously rock if you sent a patch too. :)
>>   
>>     
>
> Sure, I already did that. See "[coreboot] [PATCH] Avoid cross-device
> renames in build_opt_tbl".
>
> Should I revert r3789 and apply my patch instead? Or is a fusion of both
> patches preferred?
>   

I sent a followup patch.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 18:00:50 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 18:00:50 +0100
Subject: [coreboot] [PATCH] Avoid cross-device renames in build_opt_tbl
In-Reply-To: <ff277c2e0812031941p90f55d8t3946da8e7e49818a@mail.gmail.com>
References: <49352499.6040302@gmx.net>
	<ff277c2e0812031941p90f55d8t3946da8e7e49818a@mail.gmail.com>
Message-ID: <49380CC2.9080100@gmx.net>

Hi Aaron,

could you retest with latest svn and the patch below? Thanks!

On 04.12.2008 04:41, aaron lwe wrote:
>> That's due to the rename being performed in build_opt_tbl. Renames can't
>> be done across filesystems. I saw that problem in the original patch,
>> but I didn't want to ruin the mood by complaining.
>>     
>
> I see compiling errors more important than the mood.
>
>   
>> Anyway, here is a patch to fix it.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> The patch works well for me and is much better than the statically
> allocated method which will probablly cause other people complain due
> to their very long path name.
>
> Acked-by: Aaron Lwe <aaron.lwe at gmail.com>
>   

Fix a few bugs introduced in r3789.
- Possible NULL pointer dereference in the header code because the
header code incorrectly used the option filename instead of the header
filename.
- Breakage if the path is longer than 234 bytes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c
===================================================================
--- LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c	(Revision 3794)
+++ LinuxBIOSv2-build_opt_tbl/util/options/build_opt_tbl.c	(Arbeitskopie)
@@ -12,7 +12,6 @@
 #define INPUT_LINE_MAX 256
 #define MAX_VALUE_BYTE_LENGTH 64
 
-#define TMPFILE_LEN 256
 #define TMPFILE_TEMPLATE "/build_opt_tbl_XXXXXX"
 
 static unsigned char cmos_table[4096];
@@ -217,7 +216,7 @@
 	char *header=0;
 	FILE *fp;
 	int tmpfile;
-	char tmpfilename[TMPFILE_LEN];
+	char *tmpfilename;
 	struct cmos_option_table *ct;
 	struct cmos_entries *ce;
 	struct cmos_enums *c_enums, *c_enums_start;
@@ -487,8 +486,9 @@
 
 	/* See if we want to output a C source file */
 	if(option) {
-		strncpy(tmpfilename, dirname(option), TMPFILE_LEN);
-	        strncat(tmpfilename, TMPFILE_TEMPLATE, TMPFILE_LEN);
+		tmpfilename = malloc(strlen(dirname(option)) + strlen(TMPFILE_TEMPLATE) + 1);
+	        strcpy(tmpfilename, dirname(option));
+	        strcat(tmpfilename, TMPFILE_TEMPLATE);
 		tmpfile = mkstemp(tmpfilename);
 		if(tmpfile == -1) {
                         perror("Error - Could not create temporary file");
@@ -531,6 +531,7 @@
 			unlink(tmpfilename);
 			exit(1);
 		}
+		free(tmpfilename);
 	}
 
 	/* See if we also want to output a C header file */
@@ -538,8 +539,9 @@
 		struct cmos_option_table *hdr;
 		struct lb_record *ptr, *end;
 
-		strncpy(tmpfilename, dirname(option), TMPFILE_LEN);
-	        strncat(tmpfilename, TMPFILE_TEMPLATE, TMPFILE_LEN);
+		tmpfilename = malloc(strlen(dirname(header)) + strlen(TMPFILE_TEMPLATE) + 1);
+	        strcpy(tmpfilename, dirname(header));
+	        strcat(tmpfilename, TMPFILE_TEMPLATE);
 		tmpfile = mkstemp(tmpfilename);
 		if(tmpfile == -1) {
 			perror("Error - Could not create temporary file");
@@ -586,6 +588,7 @@
 			unlink(tmpfilename);
 			exit(1);
 		}
+		free(tmpfilename);
 	}
 	return(0);
 }


-- 
http://www.hailfinger.org/

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From marcj303 at gmail.com  Thu Dec  4 18:52:00 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 4 Dec 2008 10:52:00 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <4937F584.8060701@assembler.cz>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>
	<49347342.6080504@cosmicpenguin.net>
	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>
	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>
	<534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
	<2831fecf0812040638o6b740b83v33507aa9c30a623f@mail.gmail.com>
	<4937EE78.3070809@assembler.cz>
	<42F619BBB3D04CD6B4C3263CF32B8413@chimp>
	<4937F584.8060701@assembler.cz>
Message-ID: <534e5dc20812040952x79985c3fw68914f720d7bde39@mail.gmail.com>

On Thu, Dec 4, 2008 at 8:21 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
>> So would it be reasonable to have the domain reserve it, since having a
>> resource for each CPU at the same place could get confusing?  Do we have
>> LAPIC devices on any platforms in Coreboot, so that it could be reserved
>> there?
>
> LAPIC is in any CPU post Pentium.

I was trying to say what Rudolf clarified. There is a local APIC in
each CPU core at the addess 0xFEE00000 so we only need to reserve it
once. Logically it doesn't make sense to have it in the northbridge.
That gets back to just putting it in the domain. I thought that the
IOAPIC 0xFEC00000 should in the southbridge but if the LAPIC is in
the domain then maybe the IOAPIC shoud be with it.

I think that the only CPU coreboot supports that doesn't have a LAPIC
is the Geode. It has no multicore capability and sitll uses the legacy
PIC.

Marc



From lookicanfly at gmail.com  Thu Dec  4 19:11:59 2008
From: lookicanfly at gmail.com (=?BIG5?B?vEKlv7Fq?=)
Date: Fri, 5 Dec 2008 02:11:59 +0800
Subject: [coreboot] Flashrom problems on VIA EPIA CN13000G
Message-ID: <e087b27e0812041011v5d348a09ge26958c845d47f19@mail.gmail.com>

Hi all !

I have an VIA EPIA CN13000G board , and bought five SST49LF008A chips
from internet.
Now Trying to flash these chips, but i got this result:

# ./flashrom
  Calibrating delay loop... ok
  No LinuxBIOS table found.
  Found chipset "VT8237": Enabling flash write... OK.
  Found board "VIA EPIA-CN": Enabling flash write... OK.
  No EEPROM/flash device found.

Also i tried to flash original BIOS rom (SST49LF004B), it work fine
(read/write).
So what did i miss? Could someone tell me what to do ?



From mylesgw at gmail.com  Thu Dec  4 19:25:05 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 4 Dec 2008 11:25:05 -0700
Subject: [coreboot] qemu dts fixes
In-Reply-To: <534e5dc20812040952x79985c3fw68914f720d7bde39@mail.gmail.com>
References: <2831fecf0812011247k565ccc8et35420f91b6587c90@mail.gmail.com>
	<0C7EFA1EAFC64ED2B95E9D8ECFC307CF@chimp>
	<2831fecf0812020613s8d5d916taf80e0b27d7ed7ec@mail.gmail.com>
	<2831fecf0812020957h1085ad84hec6340da76bcf504@mail.gmail.com>
	<534e5dc20812021905p6fc61663k9da7bc88b2a6d5b@mail.gmail.com>
	<2831fecf0812040638o6b740b83v33507aa9c30a623f@mail.gmail.com>
	<4937EE78.3070809@assembler.cz>
	<42F619BBB3D04CD6B4C3263CF32B8413@chimp>
	<4937F584.8060701@assembler.cz>
	<534e5dc20812040952x79985c3fw68914f720d7bde39@mail.gmail.com>
Message-ID: <2831fecf0812041025t57d58bfct5df2234bcae40ca5@mail.gmail.com>

On Thu, Dec 4, 2008 at 10:52 AM, Marc Jones <marcj303 at gmail.com> wrote:

> On Thu, Dec 4, 2008 at 8:21 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
> >> So would it be reasonable to have the domain reserve it, since having a
> >> resource for each CPU at the same place could get confusing?  Do we have
> >> LAPIC devices on any platforms in Coreboot, so that it could be reserved
> >> there?
> >
> > LAPIC is in any CPU post Pentium.
>
> I was trying to say what Rudolf clarified. There is a local APIC in
> each CPU core at the addess 0xFEE00000 so we only need to reserve it
> once. Logically it doesn't make sense to have it in the northbridge.
> That gets back to just putting it in the domain.

That makes sense to me.  I didn't want to put it in the CPU because it only
needs to be reserved once.  This doesn't really matter for resource
allocation because the IOAPIC is at a lower address and so resource
allocation will never come this high.  I'd like it to be logical and
complete in case something else needs to know, though.


> I thought that the
> IOAPIC 0xFEC00000 should in the southbridge but if the LAPIC is in
> the domain then maybe the IOAPIC shoud be with it.

It makes sense to me to put it in the southbridge.  Rudolf has said that
different southbridges reserve different amounts of space for these, and
domains are independent of southbridges.

I think that the only CPU coreboot supports that doesn't have a LAPIC
> is the Geode. It has no multicore capability and sitll uses the legacy
> PIC.

I should have clarified here.  I was asking if any of the platforms would
create a device in the dts for the LAPIC.  I'm assuming that the answer is
no.

Thanks,
Myles
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From dlev89 at gmail.com  Thu Dec  4 21:17:38 2008
From: dlev89 at gmail.com (Daniel Levine)
Date: Thu, 4 Dec 2008 15:17:38 -0500
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
Message-ID: <a16fb16b0812041217q2a6a8c58mbcac39717771e88d@mail.gmail.com>

My Aspire 3680 has a bad BIOS, is no longer under warranty, and is
already leaning towards obsolescence a year and a half after its
purchase;  I'm wondering if Coreboot might work on it.

The output of lspci follows:
00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML
and 945GT Express Memory Controller Hub (rev 03)
00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS,
943/940GML Express Integrated Graphics Controller (rev 03)
00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME,
943/940GML Express Integrated Graphics Controller (rev 03)
00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High
Definition Audio Controller (rev 02)
00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
Port 1 (rev 02)
00:1c.1 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
Port 2 (rev 02)
00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
Port 3 (rev 02)
00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #3 (rev 02)
00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #4 (rev 02)
00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2
EHCI Controller (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2)
00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface
Bridge (rev 02)
00:1f.2 IDE interface: Intel Corporation 82801GBM/GHM (ICH7 Family)
SATA IDE Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 02)
02:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8038
PCI-E Fast Ethernet Controller (rev 14)
03:00.0 Ethernet controller: Atheros Communications Inc. AR242x
802.11abg Wireless PCI Express Adapter (rev 01)
0a:09.0 CardBus bridge: Texas Instruments PCIxx12 Cardbus Controller
0a:09.2 Mass storage controller: Texas Instruments 5-in-1 Multimedia
Card Reader (SD/MMC/MS/MS PRO/xD)

How well are 945GM and 82801G supported? Could I actually have
Coreboot working on this machine, or would I only succeed in bricking
it? Would I need custom code for the laptop?

Also, for whatever it's worth - can Coreboot load GNU GRUB (or
FreeBSD's BTX bootloader) instead of a Linux kernel?



From c-d.hailfinger.devel.2006 at gmx.net  Thu Dec  4 21:37:12 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Dec 2008 21:37:12 +0100
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
In-Reply-To: <a16fb16b0812041217q2a6a8c58mbcac39717771e88d@mail.gmail.com>
References: <a16fb16b0812041217q2a6a8c58mbcac39717771e88d@mail.gmail.com>
Message-ID: <49383F78.1080304@gmx.net>

Hi Daniel,

On 04.12.2008 21:17, Daniel Levine wrote:
> My Aspire 3680 has a bad BIOS, is no longer under warranty, and is
> already leaning towards obsolescence a year and a half after its
> purchase;  I'm wondering if Coreboot might work on it.
>
> The output of lspci follows:
> [...]
> How well are 945GM and 82801G supported? Could I actually have
> Coreboot working on this machine, or would I only succeed in bricking
> it? Would I need custom code for the laptop?
>   

That depends a lot on the embedded controller in your laptop.
Unfortunately, finding the embedded controller chip by software is next
to impossible because almost all embedded controller data sheets are
under NDA or totally unavailable. That's also the biggest reason why
coreboot focuses on desktop, server and embedded boards. Usually none of
those boards need or have an embedded controller, so we can circumvent
the associated headache.


> Also, for whatever it's worth - can Coreboot load GNU GRUB (or
> FreeBSD's BTX bootloader) instead of a Linux kernel?
>   

It can work with GRUB2, but I have no idea about BTX loading. Most
bootloaders try to use BIOS interrupt services and for that you need to
load SeaBIOS.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Thu Dec  4 21:37:37 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Dec 2008 12:37:37 -0800
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
In-Reply-To: <a16fb16b0812041217q2a6a8c58mbcac39717771e88d@mail.gmail.com>
References: <a16fb16b0812041217q2a6a8c58mbcac39717771e88d@mail.gmail.com>
Message-ID: <13426df10812041237s705660c3gf740c3e212ac7074@mail.gmail.com>

On Thu, Dec 4, 2008 at 12:17 PM, Daniel Levine <dlev89 at gmail.com> wrote:
> My Aspire 3680 has a bad BIOS, is no longer under warranty, and is
> already leaning towards obsolescence a year and a half after its
> purchase;  I'm wondering if Coreboot might work on it.
>
> The output of lspci follows:
> 00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML
> and 945GT Express Memory Controller Hub (rev 03)
> 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS,
> 943/940GML Express Integrated Graphics Controller (rev 03)
> 00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME,
> 943/940GML Express Integrated Graphics Controller (rev 03)
> 00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High
> Definition Audio Controller (rev 02)
> 00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
> Port 1 (rev 02)
> 00:1c.1 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
> Port 2 (rev 02)
> 00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
> Port 3 (rev 02)
> 00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
> UHCI Controller #1 (rev 02)
> 00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
> UHCI Controller #2 (rev 02)
> 00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
> UHCI Controller #3 (rev 02)
> 00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
> UHCI Controller #4 (rev 02)
> 00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2
> EHCI Controller (rev 02)
> 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2)
> 00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface
> Bridge (rev 02)
> 00:1f.2 IDE interface: Intel Corporation 82801GBM/GHM (ICH7 Family)
> SATA IDE Controller (rev 02)
> 00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 02)
> 02:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8038
> PCI-E Fast Ethernet Controller (rev 14)
> 03:00.0 Ethernet controller: Atheros Communications Inc. AR242x
> 802.11abg Wireless PCI Express Adapter (rev 01)
> 0a:09.0 CardBus bridge: Texas Instruments PCIxx12 Cardbus Controller
> 0a:09.2 Mass storage controller: Texas Instruments 5-in-1 Multimedia
> Card Reader (SD/MMC/MS/MS PRO/xD)
>
> How well are 945GM and 82801G supported? Could I actually have
> Coreboot working on this machine, or would I only succeed in bricking
> it? Would I need custom code for the laptop?

they're quite well supported. But there is so much custom hardware in
these laptops -- the embedded controller is the big one -- that you
would have to commit to significant reverse engineering. This will be
a bit of work absent help from Acer.

>
> Also, for whatever it's worth - can Coreboot load GNU GRUB (or
> FreeBSD's BTX bootloader) instead of a Linux kernel?

Does BTX make BIOS calls? In any event there are lots of bootloaders
you can use, I believe (but have not tried) GRUB+seabios+coreboot
ought to work.

ron



From peter at stuge.se  Thu Dec  4 21:41:33 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Dec 2008 21:41:33 +0100
Subject: [coreboot] Flashrom problems on VIA EPIA CN13000G
In-Reply-To: <e087b27e0812041011v5d348a09ge26958c845d47f19@mail.gmail.com>
References: <e087b27e0812041011v5d348a09ge26958c845d47f19@mail.gmail.com>
Message-ID: <20081204204133.1963.qmail@stuge.se>

Hi,

?B???j wrote:
> I have an VIA EPIA CN13000G board , and bought five SST49LF008A
> chips from internet.

I'm afraid those chips can not work on that board.


>   No EEPROM/flash device found.
> 
> Also i tried to flash original BIOS rom (SST49LF004B), it work fine
> (read/write).
> So what did i miss? Could someone tell me what to do ?

I believe your original chip is SST49LF040B, not 004B. 004B and 008A
understand only Firmware commands (they are FWH-compatible) while
040B and 080A respond to "LPC Memory Read" commands and are called
LPC chips.

I suggest trying to find SST49LF080A-33-4C-NHE chips instead.


//Peter



From phueper at hueper.net  Fri Dec  5 00:14:21 2008
From: phueper at hueper.net (Pattrick Hueper)
Date: Fri, 5 Dec 2008 00:14:21 +0100
Subject: [coreboot] [RFC] Here we go... the SLOF biosemu for coreboot-v3
In-Reply-To: <b5765cdf0812041510ja073a98o633394e51fdc6400@mail.gmail.com>
References: <b5765cdf0812031422v5185d06ew3a676188ae5a7567@mail.gmail.com>
	<49374EA3.1030301@cosmicpenguin.net>
	<2831fecf0812040839r4033ea4au8a5fcab5923fcc1e@mail.gmail.com>
	<b5765cdf0812041314v7133e92o377b851a59f7bb3c@mail.gmail.com>
	<b5765cdf0812041510ja073a98o633394e51fdc6400@mail.gmail.com>
Message-ID: <b5765cdf0812041514l56080ddcg2158e25ebc057a62@mail.gmail.com>

On Thu, Dec 4, 2008 at 10:14 PM, Pattrick Hueper <phueper at hueper.net> wrote:
> On Thu, Dec 4, 2008 at 5:39 PM, Myles Watson <mylesgw at gmail.com> wrote:
>> This is the same patch minus:
>> - The typedefs in types.h and multiboot.h ( s/uintXX_t/uXX/g)
>> - The -g in the Makefile
>> - An unrelated comment in stage0.s

Hi,

here is an updated patch series, no changes in types.h / multiboot.h anymore.
You can ignore 0011-enable-debug-g.patch.
The change in stage0_common.S was not part of my changes, it seem that
it was introduced by a svn update Jordan did? ( it was commited by
Carl-Daniel, i think).

Patty
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From r.marek at assembler.cz  Fri Dec  5 00:21:36 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 05 Dec 2008 00:21:36 +0100
Subject: [coreboot] fix VT8237S/K8M890 powernow
Message-ID: <49386600.5080300@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello all,

I finally got the powernow working after countless hours. And CPU runs fullspeed
after power up!

The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.

Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.


Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Thanks,
Rudolf

-----BEGIN PGP SIGNATURE-----
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From peter at stuge.se  Fri Dec  5 00:29:22 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 5 Dec 2008 00:29:22 +0100
Subject: [coreboot] fix VT8237S/K8M890 powernow
In-Reply-To: <49386600.5080300@assembler.cz>
References: <49386600.5080300@assembler.cz>
Message-ID: <20081204232922.8525.qmail@stuge.se>

Hi,

Rudolf Marek wrote:
> I finally got the powernow working after countless hours. And CPU
> runs fullspeed after power up!

Awesome.


> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Fri Dec  5 00:37:13 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 00:37:13 +0100
Subject: [coreboot] r3795 - in trunk/coreboot-v2/src:
	mainboard/asus/m2v-mx_se southbridge/via/vt8237r
Message-ID: <mailman.2543.1355071448.16123.coreboot@coreboot.org>

Author: ruik
Date: 2008-12-05 00:37:12 +0100 (Fri, 05 Dec 2008)
New Revision: 3795

Modified:
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
Log:
The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.

Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.


Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2008-12-04 15:18:20 UTC (rev 3794)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2008-12-04 23:37:12 UTC (rev 3795)
@@ -282,7 +282,7 @@
 	print_debug("after enable_fid_change\r\n");
 
 	/* FIXME does not work yet */
-//	init_fidvid_bsp(bsp_apicid);
+	init_fidvid_bsp(bsp_apicid);
 
 	/* Stop the APs so we can start them later in init. */
 	allow_all_aps_stop(bsp_apicid);

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-12-04 15:18:20 UTC (rev 3794)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-12-04 23:37:12 UTC (rev 3795)
@@ -236,20 +236,10 @@
 
 		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
+
 		if (devctl == PCI_DEV_INVALID)
 			return;
 
-		/* TODO: Why is this an extra block? */
-		{
-			u8 tmp;
-			tmp = pci_read_config8(devctl, 0xec);
-			print_debug("EC is ");
-			print_debug_hex8(tmp);
-			print_debug(" E5 is ");
-			tmp = pci_read_config8(dev, 0xe5);
-			print_debug_hex8(tmp);
-		}
-
 		/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
 		pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
 
@@ -261,47 +251,15 @@
 		 * Will work for C3 and for FID/VID change.
 		 */
 
-		/* FIXME */
-		outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
-//              outb(0x4, VT8237R_ACPI_IO_BASE + 0x50);  /* Maybe unneeded? */
+		outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
 
-		/* It seems for AMD LDTSTP is connected not to SLP anymore. */
-		/* Enable 0: DPSLP# / DPRSTP# / VRDSLP */
-
-		/*
-		 * Enable SATA LED, VR timer = 100us.
-		 * Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs
-		 * to some of those pins! (and not to SLP as on R ver).
-		 */
-		pci_write_config8(dev, 0xe5, 0x69);	/* FIXME */
-
-		/*
-		 * REQ5 as PCI request input - should be together with
-		 * INTE-INTH. Fast VR timer disable - need for LDTSTP signal.
-		 */
-		pci_write_config8(dev, 0xe4, 0xa5);
-
 		/* Reduce further the STPCLK/LDTSTP signal to 5us. */
 		pci_write_config8(dev, 0xec, 0x4);
 
-		/* Host Bus Power Management Control, maybe not needed. */
-		pci_write_config8(dev, 0x8c, 0x5);
-
 		/* So the chip knows we are on AMD. */
-		pci_write_config8(devctl, 0x7c, 0x77);
+		pci_write_config8(devctl, 0x7c, 0x7f);
 
-		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-						  0x2336), 0);
-		if (devctl == PCI_DEV_INVALID)
-			return;
-
-		/*
-		 * Enable C2NOW delay to PSTATECTL VID / FID Change Delay
-		 * to P-State Control.
-		 */
-		pci_write_config8(devctl, 0xa6, 0x83);
-
-		// return; // FIXME: Fall through some revs have it old way.
+		return;
 	}
 
 	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2008-12-04 15:18:20 UTC (rev 3794)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2008-12-04 23:37:12 UTC (rev 3795)
@@ -264,14 +264,10 @@
 	pci_write_config32(dev, 0xbc,
 			   (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
 
-	/* Enable SATA LED, VR timer = 100us, VR timer should be fixed. */
-	pci_write_config8(dev, 0xe5, 0x69);
-
 	/*
 	 * REQ5 as PCI request input - should be together with INTE-INTH. 
-	 * Fast VR timer disable - need for LDTSTOP_L signal.
 	 */
-	pci_write_config8(dev, 0xe4, 0xa5);
+	pci_write_config8(dev, 0xe4, 0x04);
 
 	/* Reduce further the STPCLK/LDTSTP signal to 5us. */
 	pci_write_config8(dev, 0xec, 0x4);




From svn at coreboot.org  Fri Dec  5 00:42:36 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 00:42:36 +0100
Subject: [coreboot] r3796 - trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
Message-ID: <mailman.2544.1355071448.16123.coreboot@coreboot.org>

Author: ruik
Date: 2008-12-05 00:42:36 +0100 (Fri, 05 Dec 2008)
New Revision: 3796

Modified:
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
Log:
This belongs to changeset 3795.

The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.

Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2008-12-04 23:37:12 UTC (rev 3795)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2008-12-04 23:42:36 UTC (rev 3796)
@@ -92,6 +92,8 @@
 
 #define K8_4RANK_DIMM_SUPPORT 1
 
+
+
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -102,6 +104,21 @@
 #include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
+
+#define SB_VFSMAF 0
+
+/* this function might fail on some K8 CPUs with errata #181 */
+static void ldtstop_sb(void)
+{
+	print_debug("toggle LDTSTP#\r\n");
+	u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
+	reg = reg ^ (1 << 0);
+	outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
+	reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
+	print_debug("done\r\n");
+}
+
+
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 




From quentin.rameau at gmail.com  Fri Dec  5 00:50:47 2008
From: quentin.rameau at gmail.com (Quentin RAMEAU)
Date: Fri, 5 Dec 2008 00:50:47 +0100
Subject: [coreboot] NEC PowerMate2000(Celeron) info
Message-ID: <5b8804ae0812041550m11e1cdabmdb976f391d57f1aa@mail.gmail.com>

lspci -tvnn
-------------------------------------------------------------------------------------------------------------------------------------------------------
-[0000:00]-+-00.0  Intel Corporation 82810 GMCH (Graphics Memory
Controller Hub) [8086:7120]
           +-01.0  Intel Corporation 82810 (CGC) Chipset Graphics
Controller [8086:7121]
           +-1e.0-[0000:01-09]--+-03.0  Texas Instruments PCI1420 PC
card Cardbus Controller [104c:ac51]
           |                    +-03.1  Texas Instruments PCI1420 PC
card Cardbus Controller [104c:ac51]
           |                    \-04.0  Intel Corporation
82557/8/9/0/1 Ethernet Pro 100 [8086:1229]
           +-1f.0  Intel Corporation 82801AB ISA Bridge (LPC) [8086:2420]
           +-1f.1  Intel Corporation 82801AB IDE Controller [8086:2421]
           +-1f.2  Intel Corporation 82801AB USB Controller [8086:2422]
           +-1f.3  Intel Corporation 82801AB SMBus Controller [8086:2423]
           \-1f.5  Intel Corporation 82801AB AC'97 Audio Controller [8086:2425]

superiotool -dV
-------------------------------------------------------------------------------------------------------------------------------------------------------
superiotool r3784
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0x0000, rev=0x00
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0x5101, rev=0x9
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0x5101, rev=0x9
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0x5101, rev=0x9
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0x5101, rev=0x9
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
Found SMSC LPC47B27x (id=0x51, rev=0x01) at 0x2e
Register dump:
idx 03 20 21 22 23 24 26 27  28 2a 2b 2c 2d 2e 2f
val 00 51 01 19 19 44 2e 00  00 00 00 00 00 00 00
def RR 51 NA 00 00 04 MM MM  RR NA NA NA NA NA NA
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 01 03 f0 06 02 0e 00 ff  08 08
def 00 03 f0 06 02 0e 00 ff  00 00
LDN 0x03 (Parallel port)
idx 30 60 61 70 74 f0 f1
val 01 03 78 07 04 38 00
def 00 00 00 00 04 3c 00
LDN 0x04 (COM1)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 00 00 00 00 00
LDN 0x05 (COM2)
idx 30 60 61 62 63 70 74 f0  f1 f2
val 00 00 00 00 00 00 04 00  02 03
def NA 00 00 00 00 00 04 00  02 03
LDN 0x07 (Keyboard)
idx 30 70 72 f0
val 01 01 00 04
def 00 00 00 00
LDN 0x09 (Game port)
idx 30 60 61
val 00 00 00
def 00 00 00
LDN 0x0a (Power-management events (PME))
idx 30 60 61 f0 f1
val 01 08 00 00 00
def 00 00 00 NA NA
LDN 0x0b (MIDI port (MPU-401))
idx 30 60 61 70
val 00 03 30 05
def 00 03 30 05
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff

irq_tables.c
-------------------------------------------------------------------------------------------------------------------------------------------------------
/* This file was generated by getpir.c, do not modify!
 * (but if you do, please run checkpir on it to verify)
 *
 * Contains the IRQ Routing Table dumped directly from your
 * memory, which BIOS sets up.
 *
 * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
 */

#ifdef GETPIR
#include "pirq_routing.h"
#else
#include <arch/pirq_routing.h>
#endif

const struct irq_routing_table intel_irq_routing_table = {
        PIRQ_SIGNATURE,  /* u32 signature */
        PIRQ_VERSION,    /* u16 version   */
        32+16*5,         /* There can be total 5 devices on the bus */
        0x00,            /* Where the interrupt router lies (bus) */
        (0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
        0,               /* IRQs devoted exclusively to PCI usage */
        0x8086,          /* Vendor */
        0x122e,          /* Device */
        0,               /* Miniport */
        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
        0x6e,            /* u8 checksum. This has to be set to some
                            value that would give 0 after the sum of all
                            bytes for this structure (including checksum) */
        {
                /* bus,     dev|fn,   {link, bitmap}, {link, bitmap},
{link, bitmap}, {link, bitmap},  slot, rfu */
                {0x00,(0x1e<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8},
{0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
                {0x01,(0x03<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8},
{0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
                {0x01,(0x04<<3)|0x0, {{0x62, 0xdef8}, {0x00, 0xdef8},
{0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
                {0x00,(0x1f<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8},
{0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
                {0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8},
{0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
        }
};

unsigned long write_pirq_routing_table(unsigned long addr)
{
        return copy_pirq_routing_table(addr);
}

mptable -grope
-------------------------------------------------------------------------------------------------------------------------------------------------------
/* generated by MPTable, version 2.0.15*/
/* as modified by RGM for coreboot */
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>

void *smp_write_config_table(void *v)
{
        static const char sig[4] = "PCMP";
        static const char oem[8] = "LNXI    ";
        static const char productid[12] = "P4DPE       ";
        struct mp_config_table *mc;

        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
        memset(mc, 0, sizeof(*mc));

        memcpy(mc->mpc_signature, sig, sizeof(sig));
        mc->mpc_length = sizeof(*mc); /* initially just the header */
        mc->mpc_spec = 0x04;
        mc->mpc_checksum = 0; /* not yet computed */
        memcpy(mc->mpc_oem, oem, sizeof(oem));
        memcpy(mc->mpc_productid, productid, sizeof(productid));
        mc->mpc_oemptr = 0;
        mc->mpc_oemsize = 0;
        mc->mpc_entry_count = 0; /* No entries yet... */
        mc->mpc_lapic = LAPIC_ADDR;
        mc->mpe_length = 0;
        mc->mpe_checksum = 0;
        mc->reserved = 0;

        smp_write_processors(mc);


  MP default config type: 115

   future type
   future type
        /* There is no extension information... */

        /* Compute the checksums */
        mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
        mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
        printk_debug("Wrote the mp table end at: %p - %p\n",
                mc, smp_next_mpe_entry(mc));
        return smp_next_mpe_entry(mc);
}

unsigned long write_smp_table(unsigned long addr)
{
        void *v;
        v = smp_write_floating_table(addr);
        return (unsigned long)smp_write_config_table(v);
}



From quentin.rameau at gmail.com  Fri Dec  5 00:53:02 2008
From: quentin.rameau at gmail.com (Quentin RAMEAU)
Date: Fri, 5 Dec 2008 00:53:02 +0100
Subject: [coreboot] NEC PowerMate2000(Celeron) info
In-Reply-To: <5b8804ae0812041550m11e1cdabmdb976f391d57f1aa@mail.gmail.com>
References: <5b8804ae0812041550m11e1cdabmdb976f391d57f1aa@mail.gmail.com>
Message-ID: <5b8804ae0812041553kdc880fdrd99252a811687103@mail.gmail.com>

lspci -xxx
-------------------------------------------------------------------------------------------------------------------------------------------------------
00:00.0 Host bridge: Intel Corporation 82810 GMCH (Graphics Memory
Controller Hub) (rev 02)
00: 86 80 20 71 06 01 80 20 02 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:01.0 VGA compatible controller: Intel Corporation 82810 (CGC)
Chipset Graphics Controller (rev 02)
00: 86 80 21 71 07 00 b0 02 02 00 00 03 00 00 00 00
10: 08 00 00 f8 00 00 00 e4 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 33 10 aa 80
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 00 00

00:1e.0 PCI bridge: Intel Corporation 82801AB PCI Bridge (rev 01)
00: 86 80 28 24 07 01 80 00 01 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 09 40 20 40 80 02
20: 10 e4 20 f4 00 10 f0 17 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00

00:1f.0 ISA bridge: Intel Corporation 82801AB ISA Bridge (LPC) (rev 01)
00: 86 80 20 24 0f 00 80 02 01 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:1f.1 IDE interface: Intel Corporation 82801AB IDE Controller (rev 01)
00: 86 80 21 24 05 00 80 02 01 80 01 01 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: e1 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:1f.2 USB Controller: Intel Corporation 82801AB USB Controller (rev 01)
00: 86 80 22 24 05 00 80 02 01 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: c1 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 00

00:1f.3 SMBus: Intel Corporation 82801AB SMBus Controller (rev 01)
00: 86 80 23 24 01 00 80 02 01 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: f1 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 09 02 00 00

00:1f.5 Multimedia audio controller: Intel Corporation 82801AB AC'97
Audio Controller (rev 01)
00: 86 80 25 24 05 00 80 02 01 00 01 04 00 00 00 00
10: 01 14 00 00 81 10 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 33 10 ab 80
30: 00 00 00 00 00 00 00 00 00 00 00 00 09 02 00 00

01:03.0 CardBus bridge: Texas Instruments PCI1420 PC card Cardbus Controller
00: 4c 10 51 ac 07 00 10 02 00 00 07 06 20 a8 82 00
10: 00 10 20 e4 a0 00 00 02 01 02 05 b0 00 00 00 10
20: 00 f0 ff 13 00 00 00 e8 00 f0 ff eb 00 24 00 00
30: fc 24 00 00 00 28 00 00 fc 28 00 00 ff 01 c0 05
40: 33 10 b8 80 01 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:03.1 CardBus bridge: Texas Instruments PCI1420 PC card Cardbus Controller
00: 4c 10 51 ac 07 00 10 02 00 00 07 06 20 a8 82 00
10: 00 20 20 e4 a0 00 00 02 01 06 09 b0 00 00 00 14
20: 00 f0 ff 17 00 00 00 ec 00 f0 ff ef 00 2c 00 00
30: fc 2c 00 00 00 30 00 00 fc 30 00 00 ff 02 c0 05
40: 33 10 b8 80 01 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:04.0 Ethernet controller: Intel Corporation 82557/8/9/0/1 Ethernet
Pro 100 (rev 08)
00: 86 80 29 12 17 01 90 02 08 00 00 02 08 42 00 00
10: 00 00 20 e4 01 20 00 00 00 00 10 e4 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 33 10 64 80
30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 08 38



From uwe at hermann-uwe.de  Fri Dec  5 01:16:45 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 5 Dec 2008 01:16:45 +0100
Subject: [coreboot] [PATCH] v2: Support for the NEC PowerMate 2000 board
Message-ID: <20081205001645.GA26513@greenwood>

See patch.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From stepan at coresystems.de  Fri Dec  5 02:29:41 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Dec 2008 02:29:41 +0100
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
In-Reply-To: <49383F78.1080304@gmx.net>
References: <a16fb16b0812041217q2a6a8c58mbcac39717771e88d@mail.gmail.com>
	<49383F78.1080304@gmx.net>
Message-ID: <49388405.3030507@coresystems.de>

Carl-Daniel Hailfinger wrote:
> That depends a lot on the embedded controller in your laptop.
> Unfortunately, finding the embedded controller chip by software is next
> to impossible because almost all embedded controller data sheets are
> under NDA or totally unavailable. 
I've been having a hit rate of 100% on free data sheets for the ECs used
in 945 based systems so far.
Doesn't significantly help though, as the protocol for communication
between "the bios" and the EC firmware is usually not documented, and
schematics for the systems are hard to find.

Daniel, you might want to start with reading out your flash chip with
flashrom, finding out what chip it is, open the laptop, check if it's
socketed... Find out what superios are in there (superiotool),
investigate the system with inteltool, ...


Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Fri Dec  5 03:20:32 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 02:20:32 -0000
Subject: [coreboot] #117: flashrom: Check if erase succeeds and exit with
 error on failure
Message-ID: <041.33261a5b842d6b0b1436137ef9bad262@coreboot.org>

#117: flashrom: Check if erase succeeds and exit with error on failure
----------------------------------------------+-----------------------------
   Reporter:  stuge                           |          Owner:  stuge        
       Type:  defect                          |         Status:  new          
   Priority:  blocker                         |      Milestone:  flashrom v1.0
  Component:  flashrom                        |        Version:               
   Keywords:  erase error                     |   Dependencies:               
Patchstatus:  patch is ready to be committed  |  
----------------------------------------------+-----------------------------


-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/117>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Dec  5 03:22:30 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 03:22:30 +0100
Subject: [coreboot] r3797 - trunk/util/flashrom
Message-ID: <mailman.2545.1355071449.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-12-05 03:22:30 +0100 (Fri, 05 Dec 2008)
New Revision: 3797

Modified:
   trunk/util/flashrom/flashrom.c
Log:
flashrom: Check if erase succeeds and exit with error on failure.

flashrom used to exit 0 even if erase failed. Not anymore.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-12-04 23:42:36 UTC (rev 3796)
+++ trunk/util/flashrom/flashrom.c	2008-12-05 02:22:30 UTC (rev 3797)
@@ -250,6 +250,7 @@
 {
 	uint8_t *buf;
 	unsigned long size;
+	size_t erasedbytes;
 	FILE *image;
 	/* Probe for up to three flash chips. */
 	struct flashchip *flash, *flashes[3];
@@ -533,13 +534,25 @@
 
 	if (erase_it) {
 		printf("Erasing flash chip... ");
-		if (!flash->erase) {
-			fprintf(stderr, "Error: flashrom has no erase function for this flash chip.\n");
+		if (NULL == flash->erase) {
+			printf("FAILED!\n");
+			fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n");
 			return 1;
 		}
 		flash->erase(flash);
-		printf("done.\n");
-		exit(0);
+		if (NULL == flash->read)
+			memcpy(buf, (const char *)flash->virtual_memory, size);
+		else
+			flash->read(flash, buf);
+		for (erasedbytes = 0; erasedbytes <= size; erasedbytes++)
+			if (0xff != buf[erasedbytes]) {
+				printf("FAILED!\n");
+				fprintf(stderr, "ERROR at 0x%08x: Expected=0xff, Read=0x%02x\n",
+					erasedbytes, buf[erasedbytes]);
+				return 1;
+			}
+		printf("SUCCESS.\n");
+		return 0;
 	} else if (read_it) {
 		if ((image = fopen(filename, "w")) == NULL) {
 			perror(filename);




From svn at coreboot.org  Fri Dec  5 03:23:05 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 02:23:05 -0000
Subject: [coreboot] #117: flashrom: Check if erase succeeds and exit
 with error on failure
In-Reply-To: <041.33261a5b842d6b0b1436137ef9bad262@coreboot.org>
References: <041.33261a5b842d6b0b1436137ef9bad262@coreboot.org>
Message-ID: <050.c87463dce3e14fe1ae625ec998040f88@coreboot.org>

#117: flashrom: Check if erase succeeds and exit with error on failure
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge                   
        Type:  defect    |        Status:  closed                  
    Priority:  blocker   |     Milestone:  flashrom v1.0           
   Component:  flashrom  |       Version:                          
  Resolution:  fixed     |      Keywords:  erase error             
Dependencies:            |   Patchstatus:  patch has been committed
-------------------------+--------------------------------------------------
Changes (by stuge):

  * status:  new => closed
  * patchstatus:  patch is ready to be committed => patch has been
                  committed
  * resolution:  => fixed


Comment:

 r3797

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/117#comment:1>
coreboot <http://www.coreboot.org/>


From joe at settoplinux.org  Fri Dec  5 03:29:22 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 04 Dec 2008 21:29:22 -0500
Subject: [coreboot] LPCflasher rename to Paraflasher
Message-ID: <662f8558de20ab17a6b9ce23822477b1@imap.1and1.com>


Hello,
I was thinking of renaming the LPCflasher Project to the Paraflasher
Project. It will have the ability to flash more than just LPC chips so I
think it should have a more generalized name hence the Paraflasher
(Parallel Port Flasher) Project. What does everyone think? If no one
strongly disagrees I will go ahead and change it.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Fri Dec  5 03:36:35 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 02:36:35 -0000
Subject: [coreboot] #104: flashrom: Change flash drivers to never erase
 data before writing
In-Reply-To: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
References: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
Message-ID: <050.29e7bb833e6daf61ecdb19bebd3f1429@coreboot.org>

#104: flashrom: Change flash drivers to never erase data before writing
---------------------------------+------------------------------------------
   Reporter:  stuge              |          Owner:  stuge        
       Type:  defect             |         Status:  new          
   Priority:  major              |      Milestone:  flashrom v1.1
  Component:  flashrom           |        Version:               
   Keywords:  erase write        |   Dependencies:               
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
Changes (by stuge):

  * owner:  somebody => stuge
  * dependencies:  #103 =>
  * milestone:  flashrom v1.0 => flashrom v1.1


-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:7>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Dec  5 03:49:04 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 02:49:04 -0000
Subject: [coreboot] #100: flashrom: Change start/end -s and -e to -S and
 -E, and change erase -E to -e.
In-Reply-To: <041.8aa562bc051ad7561e8886785fe385eb@coreboot.org>
References: <041.8aa562bc051ad7561e8886785fe385eb@coreboot.org>
Message-ID: <050.8d4787e1bb66d2b69dae77a368edb08e@coreboot.org>

#100: flashrom: Change start/end -s and -e to -S and -E, and change erase -E to
-e.
----------------------------+-----------------------------------------------
    Reporter:  stuge        |         Owner:  somebody             
        Type:  enhancement  |        Status:  closed               
    Priority:  major        |     Milestone:  flashrom v1.1        
   Component:  flashrom     |       Version:                       
  Resolution:  duplicate    |      Keywords:  usability cli options
Dependencies:               |   Patchstatus:  there is no patch    
----------------------------+-----------------------------------------------
Changes (by stuge):

  * status:  new => closed
  * patchstatus:  patch needs review => there is no patch
  * resolution:  => duplicate
  * milestone:  flashrom v1.0 => flashrom v1.1


Comment:

 Moving to 1.1 where -s -e should be replaced anyway, with something like
 -s -n which would specify an inclusive byte range to operate on, AKA
 partial operation. Depends/duplicate #104.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/100#comment:2>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Dec  5 03:58:14 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 02:58:14 -0000
Subject: [coreboot] #103: flashrom: Don't exit() after successful erase;
 enable testing all operations in one invocation (was: flashrom:
 Don't exit() after successful erase)
In-Reply-To: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
References: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
Message-ID: <050.16bfc8a6d7981ebe042f00b36e6008f1@coreboot.org>

#103: flashrom: Don't exit() after successful erase; enable testing all
operations in one invocation
----------------------------------+-----------------------------------------
   Reporter:  stuge               |          Owner:  stuge        
       Type:  enhancement         |         Status:  assigned     
   Priority:  major               |      Milestone:  flashrom v1.0
  Component:  flashrom            |        Version:               
   Keywords:  erase exit testing  |   Dependencies:  #117         
Patchstatus:  patch needs review  |  
----------------------------------+-----------------------------------------
Changes (by stuge):

  * keywords:  erase exit => erase exit testing
  * dependencies:  => #117
  * type:  defect => enhancement


Comment:

 This allows -Er -Ew and -Ev but they are pretty useless. The point is that
 this allows -Ewv which will test erase, write and read (both during erase
 and verify) operations on the probed flash chip, so it's an easy way to
 exercise flash chip drivers.

 Currently the order of commands (-E -r -w -v) on the command line is not
 significant, if multiple commands are specified flashrom will always
 execute them in order ERASE READ WRITE VERIFY.

 This can be bad for users running -rE expecting to get a backup before the
 erase is done. A simple solution would be to change the order in main()
 into READ ERASE WRITE VERIFY, in which case the invocation:

 flashrom -rEwv org.bin

 will save the original contents, erase the chip and write back the
 original, verifying each step.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:5>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Dec  5 04:00:55 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 03:00:55 -0000
Subject: [coreboot] #106: flashrom: Add -T to automatically test all
 flash chip operations
In-Reply-To: <041.16204f2bdbfde4e3eac5ffa09962d8e9@coreboot.org>
References: <041.16204f2bdbfde4e3eac5ffa09962d8e9@coreboot.org>
Message-ID: <050.de225b2ce6483738afaa998b4d04df71@coreboot.org>

#106: flashrom: Add -T to automatically test all flash chip operations
----------------------------+-----------------------------------------------
    Reporter:  stuge        |         Owner:  somebody         
        Type:  enhancement  |        Status:  closed           
    Priority:  major        |     Milestone:  flashrom v1.0    
   Component:  flashrom     |       Version:                   
  Resolution:  duplicate    |      Keywords:  testing          
Dependencies:  #103         |   Patchstatus:  there is no patch
----------------------------+-----------------------------------------------
Changes (by stuge):

  * status:  new => closed
  * dependencies:  => #103
  * resolution:  => duplicate
  * milestone:  flashrom v1.1 => flashrom v1.0


Comment:

 dup #103

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/106#comment:4>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Dec  5 04:17:34 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 03:17:34 -0000
Subject: [coreboot] #104: flashrom: Change flash drivers to not erase in
 the write function (was: flashrom: Change flash drivers to never erase data
 before writing)
In-Reply-To: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
References: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
Message-ID: <050.6862c3121ab3d1c1f8868b1847e64d4d@coreboot.org>

#104: flashrom: Change flash drivers to not erase in the write function
-----------------------------------+----------------------------------------
   Reporter:  stuge                |          Owner:  stuge        
       Type:  enhancement          |         Status:  new          
   Priority:  major                |      Milestone:  flashrom v1.1
  Component:  flashrom             |        Version:               
   Keywords:  partial erase write  |   Dependencies:               
Patchstatus:  there is no patch    |  
-----------------------------------+----------------------------------------
Changes (by stuge):

  * keywords:  erase write => partial erase write
  * type:  defect => enhancement


Comment:

 --8<--
 [http://www.coreboot.org/pipermail/coreboot/2008-December/042781.html
 email from Yu Ning FENG]
 {{{
 We are talking about choosing some options from the full list:

 * chip read
 * chip erase
   chip write (0xff to other)
 * chip erase-and-write (option 'write')

   partial read
   partial erase
 1 partial write
 2 partial erase-and-write

 * = Options we have
 1 = Carl-Daniel suggests
 2 = Other people suggest

 Every option in the list is useful in some case. My opinion on -

 the choice  - Support the full list;
 1           - Warning and ask for continuation. No checking for 0xff;
 2           - We need this convenience for partial modification.

 My two cents.

 yu ning
 }}}
 -->8--

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:8>
coreboot <http://www.coreboot.org/>


From dlev89 at gmail.com  Fri Dec  5 04:23:59 2008
From: dlev89 at gmail.com (Daniel Levine)
Date: Thu, 4 Dec 2008 22:23:59 -0500
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
Message-ID: <a16fb16b0812041923p2c25af92h996576ba4c97bcd0@mail.gmail.com>

Stefan: flashrom -r gives me this:


Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH7M", enabling flash write... OK.
No EEPROM/flash device found.
If you know which flash chip you have, and if this version of flashrom
supports a similar flash chip, you can try to force read your chip. Run:
flashrom -f -r -c similar_supported_flash_chip filename

Note: flashrom can never write when the flash chip isn't found automatically.



From corey.osgood at gmail.com  Fri Dec  5 04:39:52 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 4 Dec 2008 22:39:52 -0500
Subject: [coreboot] [PATCH] v2: Support for the NEC PowerMate 2000 board
In-Reply-To: <20081205001645.GA26513@greenwood>
References: <20081205001645.GA26513@greenwood>
Message-ID: <dd3c80060812041939m13dbc082pc1d41fb9823ed3a9@mail.gmail.com>

2008/12/4 Uwe Hermann <uwe at hermann-uwe.de>

> See patch.
>
>
> Uwe.
> --
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Acked-by: Corey Osgood <corey.osgood at gmail.com>
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Dec  5 04:40:20 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Dec 2008 04:40:20 +0100
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
In-Reply-To: <a16fb16b0812041923p2c25af92h996576ba4c97bcd0@mail.gmail.com>
References: <a16fb16b0812041923p2c25af92h996576ba4c97bcd0@mail.gmail.com>
Message-ID: <4938A2A4.3030009@gmx.net>

On 05.12.2008 04:23, Daniel Levine wrote:
> Stefan: flashrom -r gives me this:
>
>
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel ICH7M", enabling flash write... OK.
> No EEPROM/flash device found.
>   

Please try
flashrom -V
The full output of that command hat should give us a chance to debug
your problem.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From dlev89 at gmail.com  Fri Dec  5 04:50:36 2008
From: dlev89 at gmail.com (Daniel Levine)
Date: Thu, 4 Dec 2008 22:50:36 -0500
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
In-Reply-To: <4938A2A4.3030009@gmx.net>
References: <a16fb16b0812041923p2c25af92h996576ba4c97bcd0@mail.gmail.com>
	<4938A2A4.3030009@gmx.net>
Message-ID: <a16fb16b0812041950j33415895meba0ef92ce47232d@mail.gmail.com>

Thanks, output is attached.

Also, for whatever it's worth, superiotool says I have an NSC PC87591x
SuperIO chip (dump not available).

On Thu, Dec 4, 2008 at 10:40 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 05.12.2008 04:23, Daniel Levine wrote:
>> Stefan: flashrom -r gives me this:
>>
>>
>> Calibrating delay loop... OK.
>> No coreboot table found.
>> Found chipset "Intel ICH7M", enabling flash write... OK.
>> No EEPROM/flash device found.
>>
>
> Please try
> flashrom -V
> The full output of that command hat should give us a chance to debug
> your problem.
>
> Regards,
> Carl-Daniel
>
> --
> http://www.hailfinger.org/
>
>
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From svn at coreboot.org  Fri Dec  5 05:19:49 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 04:19:49 -0000
Subject: [coreboot] #107: flashrom: Display test status in -L chip
 listing
In-Reply-To: <041.eea91e31685039e0026d8afdaa925b4c@coreboot.org>
References: <041.eea91e31685039e0026d8afdaa925b4c@coreboot.org>
Message-ID: <050.35943a3a40d985b6cdf4d594156e163f@coreboot.org>

#107: flashrom: Display test status in -L chip listing
----------------------------------+-----------------------------------------
   Reporter:  stuge               |          Owner:  stuge        
       Type:  enhancement         |         Status:  assigned     
   Priority:  minor               |      Milestone:  flashrom v1.0
  Component:  flashrom            |        Version:               
   Keywords:  testing             |   Dependencies:               
Patchstatus:  patch needs review  |  
----------------------------------+-----------------------------------------
Changes (by stuge):

  * owner:  somebody => stuge
  * status:  new => assigned
  * patchstatus:  there is no patch => patch needs review


-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/107#comment:3>
coreboot <http://www.coreboot.org/>


From peter at stuge.se  Fri Dec  5 05:28:58 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 5 Dec 2008 05:28:58 +0100
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
In-Reply-To: <a16fb16b0812041950j33415895meba0ef92ce47232d@mail.gmail.com>
References: <a16fb16b0812041923p2c25af92h996576ba4c97bcd0@mail.gmail.com>
	<4938A2A4.3030009@gmx.net>
	<a16fb16b0812041950j33415895meba0ef92ce47232d@mail.gmail.com>
Message-ID: <20081205042858.11312.qmail@stuge.se>

Daniel Levine wrote:
> Thanks, output is attached.

No help I'm afraid.

There may be a hardware signal disabling writes to the flash chip, in
which case I think you'll have to bring out the soldering iron.

Could you take the system apart and identify the flash chip visually?


//Peter



From svn at coreboot.org  Fri Dec  5 05:31:24 2008
From: svn at coreboot.org (coreboot)
Date: Fri, 05 Dec 2008 04:31:24 -0000
Subject: [coreboot] #104: flashrom: Partial operations;
 change flash drivers to not erase in the write function (was:
 flashrom: Change flash drivers to not erase in the write function)
In-Reply-To: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
References: <041.613243c7ca7145feb67f1cb5420bf35c@coreboot.org>
Message-ID: <050.617b605388f78d3d5ba3957467f14e4e@coreboot.org>

#104: flashrom: Partial operations; change flash drivers to not erase in the
write function
-----------------------------------+----------------------------------------
   Reporter:  stuge                |          Owner:  stuge        
       Type:  enhancement          |         Status:  new          
   Priority:  major                |      Milestone:  flashrom v1.1
  Component:  flashrom             |        Version:               
   Keywords:  partial erase write  |   Dependencies:               
Patchstatus:  there is no patch    |  
-----------------------------------+----------------------------------------

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:9>
coreboot <http://www.coreboot.org/>


From mylesgw at gmail.com  Fri Dec  5 05:55:50 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 4 Dec 2008 21:55:50 -0700
Subject: [coreboot] Coreboot on Tyan S2892
In-Reply-To: <1DDD70DC220D454CB0F9711D4BD08A3C02194F4F@emss04m21.us.lmco.com>
References: <A3017FB5D181440FB505C2B939B92EC0@chimp>
	<1DDD70DC220D454CB0F9711D4BD08A3C01EDB8AF@emss04m21.us.lmco.com>
	<20081114005619.GA5949@localdomain>
	<1DDD70DC220D454CB0F9711D4BD08A3C01FB9E7A@emss04m21.us.lmco.com>
	<2831fecf0811190919x412e2f23lb98a91b76c165e4f@mail.gmail.com>
	<1DDD70DC220D454CB0F9711D4BD08A3C01FBA3CC@emss04m21.us.lmco.com>
	<2831fecf0811191323l3f5b9979g5ab5e597bc150fc0@mail.gmail.com>
	<1DDD70DC220D454CB0F9711D4BD08A3C01FFD41B@emss04m21.us.lmco.com>
	<2831fecf0811200946m1d31cac2u165978017296eeb@mail.gmail.com>
	<1DDD70DC220D454CB0F9711D4BD08A3C02194F4F@emss04m21.us.lmco.com>
Message-ID: <2831fecf0812042055r5039e714o4b229ce602c5ef22@mail.gmail.com>

On Thu, Dec 4, 2008 at 3:25 PM, Anose, Bijoy K (N-Aerotek) <
bijoy.k.anose at lmco.com> wrote:

>  That seemed to be the case, but it is not exactly correct.  The LAB
> kernel (and kernels I've built) consistently are only seeing
> part of the drives.  The two drives in my setup each have 1 partition that
> is outside any swraid, and several partitions that are
> in a raid1 between the two drives.
>

I wish I knew more about swraid.  Hopefully someone else on the list will
know more.


> Each time I boot and kexec my target kernel from LAB, creation of the
> swraid is failing.  It complains that it can't find /dev/sda2
> (part of the swraid).  However, I can manually mount /dev/sda1 without
> issues.
>
> The whole boot process (including the swraid assembly, etc) has always been
> successful when booting with legacy BIOS.
> To be clear, we do not use the onboard RAID controller at all.
>
> It appears to me that coreboot is maybe not fully/correctly initializing
> the SATA controller as the BIOS is.
>
This is very possible.  Are there any illuminating error messages when the
drive fails to mount?  Have you compared a very verbose lspci of the SATA
controller? lspci -vvxxx


> Also, I'm curious what other cards, if any, you had in your machine when
> you were able to boot successfully?  Eventually, I
> need to be able to boot with some multi-port serial cards and a multi-port
> NIC (a Broadcom card that Stepan and others have
> seen issues with).  Right now, with coreboot I get no VGA or serial console
> output whatsoever when those are present, so I've
> been doing all my experimenting with those cards removed.
>

I've never used any cards in the machine.  Just a HyperTransport module.

Thanks,
Myles




 ------------------------------
*From:* Myles Watson [mailto:mylesgw at gmail.com]
*Sent:* Thursday, November 20, 2008 11:47 AM
*To:* Anose, Bijoy K (N-Aerotek)
*Cc:* Ward Vandewege; Coreboot
*Subject:* Re: [coreboot] Coreboot on Tyan S2892



On Thu, Nov 20, 2008 at 10:24 AM, Anose, Bijoy K (N-Aerotek) <
bijoy.k.anose at lmco.com> wrote:

>  Yes, it is busybox-based, and yes, the final kernel is definitely getting
> run, as evidenced by 'uname -a' output at the busybox
> prompt.  The file '/dev/sda' does exist.. I don't remember the major/minor
> numbers, etc.
>
> My .config file is attached.  I am not modifying the skeleton/* files.
>
>   -Bijoy
>

All right.  The only differences I see are that you are building on a 32-bit
machine and you're building a 32-bit LAB image.
CONFIG_TARGET_64BIT
CONFIG_CHOOSE_64BIT

Since your kernel gets loaded, I don't see why either of those should
matter.  It seems like there's a difference between the way your LAB kernel
and your regular kernel are handling the SATA drive.  Since the LAB kernel
finds and reads it, but yours doesn't...

I hope that helps.

Thanks,
Myles






>  ------------------------------
>  *From:* Myles Watson [mailto:mylesgw at gmail.com]
> *Sent:* Wednesday, November 19, 2008 3:24 PM
> *To:* Anose, Bijoy K (N-Aerotek)
>  *Cc:* Ward Vandewege; Coreboot
> *Subject:* Re: [coreboot] Coreboot on Tyan S2892
>
>
>
> On Wed, Nov 19, 2008 at 2:12 PM, Anose, Bijoy K (N-Aerotek) <
> bijoy.k.anose at lmco.com> wrote:
>
>>  I enabled the busybox option and used the default value of "5 second
>> pause to allow access to busybox" but it doesn't
>> pause anywhere, as far as I can tell.  Coreboot starts, LAB starts, LAB
>> kexecs the kernel/initrd on the SATA disk, and
>> then at that busybox prompt, I get no output when I issue "fdisk -l
>> /dev/sda".
>>
>
> So your kernel/initrd is busybox-based as well?  Is the new kernel really
> getting run?
>
> I'd start with ls -l /dev/sda or something simple like that.
>
>
>>  Could you send me a tarball of your buildrom-devel?
>>
> Since it's old I don't think that would be really helpful.  Are you
> changing the .config files?  Are you changing the skeleton/ files?
>
>
>>    Something must be different in our config.  Also your lab.conf and
>> the kernel/initrd that is on your SATA disk, if that would ok.
>>
> I don't have that machine up right now, so it would take a while.  I think
> there's a shorter path to the answer than that.
>
>
>>  I built my own static kexec and xfer'd it to the SATA drive.
>>
> Great.
>
>
>>  Multiple drives shouldn't make any difference -- if the controller can
>> see one drive, it can see them all (if it is actually
>> working properly).
>>
>
> You're right.  If they don't all work it's a bug.  Maybe it's been fixed.
> If you're only using two drives, though, it's probably not that.
>
>
>>  My system may have 2 drives or 8, depending on its function.  The one
>> I'm currently experimenting
>>
>  with has only 2 installed.
>>
>
>> -Bijoy
>>
>> (sorry again for top-posting, Outlook is acting differently over
>> VPN/rdesktop for some reason)
>>
>>  ------------------------------
>> *From:* Myles Watson [mailto:mylesgw at gmail.com]
>> *Sent:* Wednesday, November 19, 2008 11:19 AM
>> *To:* Anose, Bijoy K (N-Aerotek)
>> *Cc:* Ward Vandewege; Coreboot
>> *Subject:* Re: [coreboot] Coreboot on Tyan S2892
>>
>>
>>
>> On Wed, Nov 19, 2008 at 9:40 AM, Anose, Bijoy K (N-Aerotek) <
>> bijoy.k.anose at lmco.com> wrote:
>>
>>> > From: Ward Vandewege [mailto:ward at gnu.org]
>>> > Sent: Thursday, November 13, 2008 6:56 PM
>>> > To: Anose, Bijoy K (N-Aerotek)
>>> > Cc: Myles Watson; Marc Jones; Coreboot
>>> > Subject: Re: [coreboot] Coreboot on Tyan S2892
>>> >
>>> > On Thu, Nov 13, 2008 at 07:04:49PM -0500, Anose, Bijoy K
>>> > (N-Aerotek) wrote:
>>> > > > So far it's just me seeing that, on one specific board
>>> > (s2891). So
>>> > > > don't worry about that too much just yet.
>>> > >
>>> > > True, I'll cross that bridge when I get there.
>>> > >
>>> > > First I'll need to be able to boot, period.  So far, what
>>> > I've done is
>>>   > > this:
>>> > >
>>> > > 1.  Subversion checkout of latest buildrom 2.  make menuconfig,
>>> > > specifying Tyan S2892, 32-bit LAB 3.  make
>>> > >
>>> > > Do I need to do further configuration (Config.lb etc)?  I
>>> > thought that
>>> > > the menuconfig took care of everything.  Maybe that was wishful
>>> > > thinking..
>>> >
>>> > It's not. The only other thing you need to do is *pre*pend
>>> > the vga image to the generated image, which will generate an
>>> > image that is exactly 1024KB large, and which you can flash,
>>> > and which *should* just boot your system.
>>> >
>>>
>>> I finally got coreboot+LAB to boot my target kernel/initrd on the SATA
>>> disks (many thanks to Ward)!
>>>
>>> However, once the init script in the initrd attempts to assembly the
>>> software
>>> RAID, it fails because it can't see the SATA disks.
>>
>> How many do you have?  Ward has seen a problem with some disk controllers
>> not functioning on the ck804.  I've never used more than one.
>>
>>
>>> My guess is that coreboot is originally doing some low level block reads
>>> from
>>> the disk to load the kernel/initrd but when the final kernel attempts to
>>> do a
>>> SATA read from the disk, the controller has not been fully/properly
>>> initialized,
>>> and it fails.
>>
>>
>> Have you tried configure the busybox shell to not load automatically, and
>> looked at the SATA drives from there?
>>
>> I assume that whatever modifications that Myles made to successfully
>>> boot from
>>> SATA devices with coreboot+LAB on S2892 have trickled down to buildrom..
>>
>> I used buildrom.  I think the multiple drives may be getting you, though.
>>
>> Thanks,
>> Myles
>>
>>
>
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From lookicanfly at gmail.com  Fri Dec  5 08:30:57 2008
From: lookicanfly at gmail.com (sunggekun)
Date: Fri, 5 Dec 2008 15:30:57 +0800
Subject: [coreboot] Flashrom problems on VIA EPIA CN13000G
In-Reply-To: <e087b27e0812041011v5d348a09ge26958c845d47f19@mail.gmail.com>
References: <e087b27e0812041011v5d348a09ge26958c845d47f19@mail.gmail.com>
Message-ID: <e087b27e0812042330h5e9b5581pbf65a88c3f23a2c0@mail.gmail.com>

>> I have an VIA EPIA CN13000G board , and bought five SST49LF008A
>> chips from internet.
>
> I'm afraid those chips can not work on that board.
>
>>   No EEPROM/flash device found.
>>
>> Also i tried to flash original BIOS rom (SST49LF004B), it work fine
>> (read/write).
>> So what did i miss? Could someone tell me what to do ?
>
> I believe your original chip is SST49LF040B, not 004B. 004B and 008A
> understand only Firmware commands (they are FWH-compatible) while
> 040B and 080A respond to "LPC Memory Read" commands and are called
> LPC chips.
>
> I suggest trying to find SST49LF080A-33-4C-NHE chips instead.
>
> //Peter

Hi Peter ,
I had checked the original BIOS chip again, it's SST49LF004B,
and the flashrom output:

# ./flashrom
 Calibrating delay loop... ok
 No LinuxBIOS table found.
 Found chipset "VT8237": Enabling flash write... OK.
 Found board "VIA EPIA-CN": Enabling flash write... OK.
 Found chip "SST SST49LF004A/B" (512KB) at physical address 0xfff80000

any ideal? Is it possible all the SST49LF008A chips are broken ?



From corey.osgood at gmail.com  Fri Dec  5 09:41:33 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 5 Dec 2008 03:41:33 -0500
Subject: [coreboot] Flashrom problems on VIA EPIA CN13000G
In-Reply-To: <e087b27e0812042330h5e9b5581pbf65a88c3f23a2c0@mail.gmail.com>
References: <e087b27e0812041011v5d348a09ge26958c845d47f19@mail.gmail.com>
	<e087b27e0812042330h5e9b5581pbf65a88c3f23a2c0@mail.gmail.com>
Message-ID: <dd3c80060812050041q383c0a02n54246d7d04a16152@mail.gmail.com>

On Fri, Dec 5, 2008 at 2:30 AM, sunggekun <lookicanfly at gmail.com> wrote:

> >> I have an VIA EPIA CN13000G board , and bought five SST49LF008A
> >> chips from internet.
> >
> > I'm afraid those chips can not work on that board.
> >
> >>   No EEPROM/flash device found.
> >>
> >> Also i tried to flash original BIOS rom (SST49LF004B), it work fine
> >> (read/write).
> >> So what did i miss? Could someone tell me what to do ?
> >
> > I believe your original chip is SST49LF040B, not 004B. 004B and 008A
> > understand only Firmware commands (they are FWH-compatible) while
> > 040B and 080A respond to "LPC Memory Read" commands and are called
> > LPC chips.
> >
> > I suggest trying to find SST49LF080A-33-4C-NHE chips instead.
> >
> > //Peter
>
> Hi Peter ,
> I had checked the original BIOS chip again, it's SST49LF004B,
> and the flashrom output:
>
> # ./flashrom
>  Calibrating delay loop... ok
>  No LinuxBIOS table found.
>  Found chipset "VT8237": Enabling flash write... OK.
>  Found board "VIA EPIA-CN": Enabling flash write... OK.
>  Found chip "SST SST49LF004A/B" (512KB) at physical address 0xfff80000
>
> any ideal? Is it possible all the SST49LF008A chips are broken ?


SST49LF004B is LPC/FWH, but SST49LF008A is only FWH [1], the former was the
stock chip on my board as well. I'm currently using a Winbond W39V080A with
my board, a Jetway J7F2, or the SST chip Peter mentioned should work too.

-Corey

[1] http://www.sst.com/products.xhtml/serial_flash/49/SST49LF004B
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From corey.osgood at gmail.com  Fri Dec  5 09:53:58 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 5 Dec 2008 03:53:58 -0500
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>
	<4936C696.8090404@gmx.net> <4936C92A.4060106@cosmicpenguin.net>
	<17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>
	<13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>
Message-ID: <dd3c80060812050053o4f16922x948b79d07743d63b@mail.gmail.com>

On Wed, Dec 3, 2008 at 5:27 PM, ron minnich <rminnich at gmail.com> wrote:

> On Wed, Dec 3, 2008 at 2:02 PM, Stefan Reinauer <stepan at coresystems.de>
> wrote:
>
> > In fact the area is not completely clean due to the binutils workaround.
> We
> > had "nicer" code there, and it broke on Ron's binutils, so we went to the
> > current version. It works, so don't waste time fixing it.
>
> In fact, if anything, can we please fix the cn700?


Working on it!

Current status: a GPIO line isn't getting disabled for some reason (even
though it's disabled several times), and the damn chipset reboots when the
timer it controls expires. Once the board reboots, something isn't working
correctly, presumably CAR, and the LAR can't be read from. I'm working from
revision 1010, but I think it's the same status in current svn. I'll be
spending more time with it this weekend, from the sound of the weather
report I won't be able to do much else anyways :p

-Corey



>
>
> these cosmetic patches are not really helping anything.
>
> ron
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From niels_ole at salscheider-online.de  Fri Dec  5 12:17:46 2008
From: niels_ole at salscheider-online.de (Niels Ole Salscheider)
Date: Fri, 5 Dec 2008 12:17:46 +0100
Subject: [coreboot] [PATCH] flashrom: Add SB700 support
Message-ID: <200812051217.54008.niels_ole@salscheider-online.de>

This patch adds SB700 support to flashrom and fixes a small compilation error 
for GCC 4.3.2. The code for enabling the flash rom is the same as for SB600. 
It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a 
Macronix MX25L8005.

Signed-off-by: Niels Ole Salscheider <niels_ole at salscheider-online.de>
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From svn at coreboot.org  Fri Dec  5 12:56:58 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 12:56:58 +0100
Subject: [coreboot] r3798 - trunk/util/flashrom
Message-ID: <mailman.2546.1355071449.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-12-05 12:56:57 +0100 (Fri, 05 Dec 2008)
New Revision: 3798

Modified:
   trunk/util/flashrom/flashrom.c
Log:
flashrom: Fix compilation of r3797 with gcc-4.3.2

Thanks to Niels Ole Salscheider for the problem report.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-12-05 02:22:30 UTC (rev 3797)
+++ trunk/util/flashrom/flashrom.c	2008-12-05 11:56:57 UTC (rev 3798)
@@ -250,7 +250,7 @@
 {
 	uint8_t *buf;
 	unsigned long size;
-	size_t erasedbytes;
+	uint32_t erasedbytes;
 	FILE *image;
 	/* Probe for up to three flash chips. */
 	struct flashchip *flash, *flashes[3];




From svn at coreboot.org  Fri Dec  5 12:58:43 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 12:58:43 +0100
Subject: [coreboot] r3799 - trunk/util/flashrom
Message-ID: <mailman.2547.1355071449.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-12-05 12:58:43 +0100 (Fri, 05 Dec 2008)
New Revision: 3799

Modified:
   trunk/util/flashrom/chipset_enable.c
Log:
flashrom: Add AMD SB700 flash enable

This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.

Signed-off-by: Niels Ole Salscheider <niels_ole at salscheider-online.de>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c	2008-12-05 11:56:57 UTC (rev 3798)
+++ trunk/util/flashrom/chipset_enable.c	2008-12-05 11:58:43 UTC (rev 3799)
@@ -910,6 +910,7 @@
 	{0x1022, 0x2080, "AMD CS5536",		enable_flash_cs5536},
 	{0x1022, 0x7468, "AMD8111",		enable_flash_amd8111},
 	{0x1002, 0x438D, "ATI(AMD) SB600",	enable_flash_sb600},
+	{0x1002, 0x439d, "ATI(AMD) SB700",	enable_flash_sb600},
 	{0x10B9, 0x1533, "ALi M1533",		enable_flash_ali_m1533},
 	{0x10de, 0x0050, "NVIDIA CK804",	enable_flash_ck804}, /* LPC */
 	{0x10de, 0x0051, "NVIDIA CK804",	enable_flash_ck804}, /* Pro */




From peter at stuge.se  Fri Dec  5 12:59:22 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 5 Dec 2008 12:59:22 +0100
Subject: [coreboot] [PATCH] flashrom: Add SB700 support
In-Reply-To: <200812051217.54008.niels_ole@salscheider-online.de>
References: <200812051217.54008.niels_ole@salscheider-online.de>
Message-ID: <20081205115922.15126.qmail@stuge.se>

Niels Ole Salscheider wrote:
> This patch adds SB700 support to flashrom and fixes a small compilation error 
> for GCC 4.3.2. The code for enabling the flash rom is the same as for SB600. 
> It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a 
> Macronix MX25L8005.

Thanks, I split it up and applied in r3798 and r3799.


//Peter
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From svn at coreboot.org  Fri Dec  5 15:15:17 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 15:15:17 +0100
Subject: [coreboot] r3800 - in trunk/coreboot-v2: src/mainboard
	src/mainboard/nec src/mainboard/nec/powermate2000 targets
	targets/nec targets/nec/powermate2000
Message-ID: <mailman.2548.1355071449.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-12-05 15:15:17 +0100 (Fri, 05 Dec 2008)
New Revision: 3800

Added:
   trunk/coreboot-v2/src/mainboard/nec/
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c
   trunk/coreboot-v2/targets/nec/
   trunk/coreboot-v2/targets/nec/powermate2000/
   trunk/coreboot-v2/targets/nec/powermate2000/Config.lb
Log:
Add initial support for the NEC PowerMate 2000 board.

See details at:
http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/

Thanks to Quentin RAMEAU <quentin.rameau at gmail.com> for providing the
required information and for testing the patch.

This boots into a Linux console just fine.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood at gmail.com>



Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb	2008-12-05 14:15:17 UTC (rev 3800)
@@ -0,0 +1,135 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+	default ROM_SECTION_SIZE   = (ROM_SIZE - FALLBACK_SIZE)
+	default ROM_SECTION_OFFSET = 0
+end
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
+# object reset.o
+makerule ./failover.E
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i82810			# Northbridge
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/intel/socket_PGA370		# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on
+    device pci 0.0 on end			# Host bridge
+    device pci 1.0 off				# Onboard video
+      # chip drivers/pci/onboard
+      #   device pci 1.0 on end
+      #   register "rom_address" = "0xfff80000"
+      # end
+    end
+    chip southbridge/intel/i82801xx		# Southbridge
+      device pci 1e.0 on end			# PCI bridge
+      device pci 1f.0 on			# ISA/LPC bridge
+        chip superio/smsc/smscsuperio		# Super I/O (SMSC LPC47B27x)
+          device pnp 2e.0 on			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.3 on			# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.4 on			# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.5 off end		# Com2 (N/A)
+          device pnp 2e.7 on			# PS/2 keyboard
+            irq 0x70 = 1
+            irq 0x72 = 0
+          end
+          device pnp 2e.9 off end		# Game port (N/A)
+          device pnp 2e.a on			# Power-management events (PME)
+            io 0x60 = 0x800
+          end
+          device pnp 2e.b on			# MIDI port
+            io 0x60 = 0x330
+            irq 0x70 = 5
+          end
+        end
+      end
+      device pci 1f.1 on end			# IDE
+      device pci 1f.2 on end			# USB
+      device pci 1f.3 on end			# SMBus
+      device pci 1f.5 on end			# AC'97 audio
+      device pci 1f.6 off end			# AC'97 modem (N/A)
+    end
+  end
+end
+

Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb	2008-12-05 14:15:17 UTC (rev 3800)
@@ -0,0 +1,98 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+
+default ROM_SIZE = 512 * 1024
+default HAVE_FALLBACK_BOOT = 1
+default HAVE_MP_TABLE = 0
+default HAVE_HARD_RESET = 0
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 16 * 1024
+default HAVE_OPTION_TABLE = 0
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+default _RAMBASE = 0x00004000
+default CONFIG_ROM_PAYLOAD = 1
+default CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default TTYS0_BAUD = 115200
+default TTYS0_BASE = 0x3f8
+default TTYS0_LCS = 0x3			# 8n1
+default DEFAULT_CONSOLE_LOGLEVEL = 9
+default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default CONFIG_CONSOLE_VGA = 1
+default CONFIG_PCI_ROM_RUN = 1
+
+end

Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/auto.c	2008-12-05 14:15:17 UTC (rev 3800)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "northbridge/intel/i82810/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "pc80/udelay_io.c"
+#include "northbridge/intel/i82810/raminit.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
+static void main(unsigned long bist)
+{
+	if (bist == 0)
+		early_mtrr_init();
+
+	smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	enable_smbus();
+
+	report_bist_failure(bist);
+
+	/* dump_spd_registers(); */
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+	/* ram_check(0, 640 * 1024); */
+}

Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/chip.h	2008-12-05 14:15:17 UTC (rev 3800)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_nec_powermate2000_ops;
+
+struct mainboard_nec_powermate2000_config {
+};

Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/irq_tables.c	2008-12-05 14:15:17 UTC (rev 3800)
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router device */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x6e,			/* Checksum */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
+		{0x01, (0x03 << 3) | 0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x01, (0x04 << 3) | 0x0, {{0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+		{0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/mainboard.c	2008-12-05 14:15:17 UTC (rev 3800)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_nec_powermate2000_ops = {
+	CHIP_NAME("NEC PowerMate 2000 Mainboard")
+};

Added: trunk/coreboot-v2/targets/nec/powermate2000/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/nec/powermate2000/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/targets/nec/powermate2000/Config.lb	2008-12-05 14:15:17 UTC (rev 3800)
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target powermate2000
+mainboard nec/powermate2000
+
+option ROM_SIZE = 512 * 1024
+
+option MAINBOARD_VENDOR = "NEC"
+option MAINBOARD_PART_NUMBER = "PowerMate 2000"
+
+option IRQ_SLOT_COUNT = 5
+
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+option CONFIG_CONSOLE_VGA = 1
+option CONFIG_PCI_ROM_RUN = 1
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE = 0
+	option COREBOOT_EXTRA_VERSION = ".0Normal"
+	payload ../payload.elf
+end
+
+romimage "fallback"
+	option USE_FALLBACK_IMAGE = 1
+	option COREBOOT_EXTRA_VERSION = ".0Fallback"
+	payload ../payload.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"




From uwe at hermann-uwe.de  Fri Dec  5 15:16:06 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 5 Dec 2008 15:16:06 +0100
Subject: [coreboot] [PATCH] v2: Support for the NEC PowerMate 2000 board
In-Reply-To: <dd3c80060812041939m13dbc082pc1d41fb9823ed3a9@mail.gmail.com>
References: <20081205001645.GA26513@greenwood>
	<dd3c80060812041939m13dbc082pc1d41fb9823ed3a9@mail.gmail.com>
Message-ID: <20081205141606.GA8679@greenwood>

On Thu, Dec 04, 2008 at 10:39:52PM -0500, Corey Osgood wrote:
> Acked-by: Corey Osgood <corey.osgood at gmail.com>

Thanks, r3800.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From klt29 at freemail.hu  Fri Dec  5 15:38:03 2008
From: klt29 at freemail.hu (Tamas Szabo)
Date: Fri, 05 Dec 2008 15:38:03 +0100
Subject: [coreboot] EPIA MII
Message-ID: <49393CCB.1070306@freemail.hu>

Hello,

Can someone point to a guide which helps me how to make my EPIA working 
with the latest coreboot and filo?

Thx,

/sza2



From bari at onelabs.com  Fri Dec  5 15:49:08 2008
From: bari at onelabs.com (bari)
Date: Fri, 05 Dec 2008 08:49:08 -0600
Subject: [coreboot] Flashrom problem on VIA EPIA CN13000G
In-Reply-To: <e087b27e0812050040g780649b6p9154927f83c1b7da@mail.gmail.com>
References: <e087b27e0812050040g780649b6p9154927f83c1b7da@mail.gmail.com>
Message-ID: <49393F64.9050805@onelabs.com>

Sunggekun wrote:
> Hi Bari,
>
> i have Flashrom problem on VIA EPIA CN13000G,
> and saw this tutorial http://www.coreboot.org/VIA_EPIA-CN ,
> it says:
> Flashrom 	 OK 	 SST 512KB, 1MB, 2MB, PMC 512KB
>
> while trying to flash SST49LF0008A (1MB),i got this result:
> # ./flashrom
>  Calibrating delay loop... ok
>  No LinuxBIOS table found.
>  Found chipset "VT8237": Enabling flash write... OK.
>  Found board "VIA EPIA-CN": Enabling flash write... OK.
>  No EEPROM/flash device found
>
> Can SST49LF0008A work on VIA EPIA CN13000G? i missed to setup something?
> and how did you flash SST 1MB roms?
>
>
>
> Sunggekun
>
>   
SST49LF080A-33-4C-NHE works great!

We also use the 49LF016C-33-4C-NH in the same VIA Epia boards without 
any problems.

-Bari



From dlev89 at gmail.com  Fri Dec  5 15:55:01 2008
From: dlev89 at gmail.com (Daniel Levine)
Date: Fri, 5 Dec 2008 09:55:01 -0500
Subject: [coreboot] Coreboot on an Acer Aspire 3680?
Message-ID: <a16fb16b0812050655s27bc72d6he639bf1dcb01d423@mail.gmail.com>

Peter Stuge wrote:
>No help I'm afraid.
>
>There may be a hardware signal disabling writes to the flash chip, in
>which case I think you'll have to bring out the soldering iron.
>
>Could you take the system apart and identify the flash chip visually?

Unfortunately no... Thanks for the help anyway.



From corey.osgood at gmail.com  Fri Dec  5 18:04:28 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 5 Dec 2008 12:04:28 -0500
Subject: [coreboot] EPIA MII
In-Reply-To: <49393CCB.1070306@freemail.hu>
References: <49393CCB.1070306@freemail.hu>
Message-ID: <dd3c80060812050904x6954dbd2v121ada5ac3d09708@mail.gmail.com>

On Fri, Dec 5, 2008 at 9:38 AM, Tamas Szabo <klt29 at freemail.hu> wrote:

> Hello,
>
> Can someone point to a guide which helps me how to make my EPIA working
> with the latest coreboot and filo?
>
> Thx,
>
> /sza2


Hi,

I'll try to update the wiki page tonight or this weekend.

-Corey
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From svn at coreboot.org  Fri Dec  5 19:38:57 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 19:38:57 +0100
Subject: [coreboot] r3801 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
Message-ID: <mailman.2549.1355071449.16123.coreboot@coreboot.org>

Author: mjones
Date: 2008-12-05 19:38:57 +0100 (Fri, 05 Dec 2008)
New Revision: 3801

Modified:
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c
Log:
The TALERT of ADT7461 should be pull back high if the temperature is within the limit. It is done by reading the register whose device address is 0xC. It is not trivial as it looks.



Signed-off-by:  Maggie Li <maggie.li at amd.com>
Reviewed-by:    Joe Bao <zheng.bao at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c	2008-12-05 14:15:17 UTC (rev 3800)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c	2008-12-05 18:38:57 UTC (rev 3801)
@@ -28,6 +28,7 @@
 #include "chip.h"
 
 #define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS     0x0C /* Alert Response Address */
 #define SMBUS_IO_BASE 0x1000
 
 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
@@ -35,6 +36,8 @@
 			       u8 val);
 #define ADT7461_read_byte(address) \
 	do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+	do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
@@ -132,6 +135,7 @@
 	ADT7461_write_byte(0x20, 0x55);	/* Local THERM limit */
 
 	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
+	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
 	printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
 
 	/* sb600 settings for thermal config */




From marcj303 at gmail.com  Fri Dec  5 19:39:23 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 5 Dec 2008 11:39:23 -0700
Subject: [coreboot] Patches for ACPI support on dbm690t (reset TALERT of
	ADT7461)
In-Reply-To: <13426df10812032224l7a79eceet18bb74dded6800d8@mail.gmail.com>
References: <DD1CC71B621B004FA76856E5129D6B170234160A@sbjgexmb1.amd.com>
	<13426df10812032224l7a79eceet18bb74dded6800d8@mail.gmail.com>
Message-ID: <534e5dc20812051039u35e90cc2s107afda5970c5f69@mail.gmail.com>

On Wed, Dec 3, 2008 at 11:24 PM, ron minnich <rminnich at gmail.com> wrote:
> One spelling change: hareware -> hardware.
>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
r3801

Marc



From rminnich at gmail.com  Fri Dec  5 19:53:51 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Dec 2008 10:53:51 -0800
Subject: [coreboot] qemu floppy filo or ...
Message-ID: <13426df10812051053x1d8b96ffnb053d35a140fdd09@mail.gmail.com>

So, has anybody tried to boot a floppy i qemu lately? Just had a
request. I'm not even sure how to proceed.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Fri Dec  5 19:59:37 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Dec 2008 19:59:37 +0100
Subject: [coreboot] [Qemu-devel] IRQ problems under qemu
In-Reply-To: <4938E7C9.8090107@dbservice.com>
References: <4938E7C9.8090107@dbservice.com>
Message-ID: <49397A19.3080301@gmx.net>

On 05.12.2008 09:35, Tomas Carnecky wrote:
> When I tried to run coreboot under qemu, I was at first positively
> surprised how well the things worked. The BIOS + linux kernel payload
> booted in no time! But when I then tried to set up networking, I
> couldn't get that to work. Somehow the linux kernel couldn't locate
> the interrupts of the NIC. After some digging I found out that
> coreboot doesn't provide ACPI tables and instead uses PCI IRQ table (I
> had to extract this table from a running qemu system using the getpir
> utility and then copy it to coreboot, if you want that patch, I can
> send that too). Coreboot copies this table at runtime into memory at
> 0xf0000. Apparently 0xf0000-0xfffff is part of the ISA BIOS, and qemu
> marks this range as read-only.
> The attached patch for qemu fixes that and also cleans up some of the
> memory initialization. Instead of marking the ISA BIOS as read-only,
> it copies that part from the BIOS image into the appropriate place (at
> 0xf0000-0xfffff) and leaves the memory as read-write.

I believe that works around the problem you're seeing, but in theory the
BIOS/firmware should be able to tell Qemu when it wants to enable RAM or
ROM mapping in that area.
Qemu early adress map (RAM vs. ROM) for x86 is unrealistic anyway
because it assumes RAM is available from the start and RAM/ROM
designation of a given area will not change. The quirk you're hitting is
just another aspect of that problem.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From jordan at cosmicpenguin.net  Fri Dec  5 20:01:22 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Fri, 05 Dec 2008 12:01:22 -0700
Subject: [coreboot] qemu floppy filo or ...
In-Reply-To: <13426df10812051053x1d8b96ffnb053d35a140fdd09@mail.gmail.com>
References: <13426df10812051053x1d8b96ffnb053d35a140fdd09@mail.gmail.com>
Message-ID: <49397A82.4@cosmicpenguin.net>

ron minnich wrote:
> So, has anybody tried to boot a floppy i qemu lately? Just had a
> request. I'm not even sure how to proceed.

qemu -boot a -fda <image>

Jordan



From peter at stuge.se  Fri Dec  5 20:01:28 2008
From: peter at stuge.se (Peter Stuge)
Date: Fri, 5 Dec 2008 20:01:28 +0100
Subject: [coreboot] qemu floppy filo or ...
In-Reply-To: <13426df10812051053x1d8b96ffnb053d35a140fdd09@mail.gmail.com>
References: <13426df10812051053x1d8b96ffnb053d35a140fdd09@mail.gmail.com>
Message-ID: <20081205190128.27809.qmail@stuge.se>

ron minnich wrote:
> So, has anybody tried to boot a floppy i qemu lately? Just had a
> request. I'm not even sure how to proceed.

Try SeaBIOS? I don't think FILO has a floppy driver.


//Peter



From marcj303 at gmail.com  Fri Dec  5 20:04:33 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 5 Dec 2008 12:04:33 -0700
Subject: [coreboot] Resources and links
In-Reply-To: <6994AEB29D4D42908E54F1C8AA7E11CF@chimp>
References: <6994AEB29D4D42908E54F1C8AA7E11CF@chimp>
Message-ID: <534e5dc20812051104p4d5e1a78yac97abddc426ed1a@mail.gmail.com>

On Thu, Dec 4, 2008 at 7:00 AM, Myles Watson <mylesgw at gmail.com> wrote:
> I've been thinking about getting rid of the links in v3, or changing their
> meaning.  I can't see anywhere that they're being used right now.
>
> The problem is how to deal with k8.  It has "multiple links", but not in the
> same sense as v3.  In v3, multiple links means logical connections to
> multiple devices.  K8 has multiple physical connections, but only one
> logical connection.
>
> This is a problem for resource allocation (the current implementation as
> well as my patch.)  The idea is that for every bridge resource gets all
> matching resources from the sub-tree packed into it.  The problem is that
> for k8 there can be multiple bridge resources of the same type, and to know
> which resources to pack into it, you have to know which physical link they
> are connected to.  At the same time, all the children are logically
> connected to the same PCI.
>
> This could be solved in several ways, but I'm hoping that there's an elegant
> way that I haven't thought of yet.  Here are a couple I was thinking of:
>
> 1. Let links have resources, and make all bridge resources live there.
>        I don't like this one because links aren't needed anywhere else, and
> this just makes links larger.
>
> 2. Give bridges a function which returns the children under a resource.
>        It's an extra function for all bridges, but most would just return
> all children.

Myles,

#2 seems like it would be useful. Would it be useful to have the link
hold pointes to the child bridge(s) or is that already handled?

Marc



From rminnich at gmail.com  Fri Dec  5 20:21:40 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Dec 2008 11:21:40 -0800
Subject: [coreboot] qemu floppy filo or ...
In-Reply-To: <20081205190128.27809.qmail@stuge.se>
References: <13426df10812051053x1d8b96ffnb053d35a140fdd09@mail.gmail.com>
	<20081205190128.27809.qmail@stuge.se>
Message-ID: <13426df10812051121n5078f3a3y744c46f9aaebd2eb@mail.gmail.com>

On Fri, Dec 5, 2008 at 11:01 AM, Peter Stuge <peter at stuge.se> wrote:
> ron minnich wrote:
>> So, has anybody tried to boot a floppy i qemu lately? Just had a
>> request. I'm not even sure how to proceed.
>
> Try SeaBIOS? I don't think FILO has a floppy driver.
>

yeah, I guess that's the only option.

Has anyone tried it however.

ron



From tom at dbservice.com  Fri Dec  5 09:35:21 2008
From: tom at dbservice.com (Tomas Carnecky)
Date: Fri, 05 Dec 2008 09:35:21 +0100
Subject: [coreboot] IRQ problems under qemu
Message-ID: <4938E7C9.8090107@dbservice.com>

When I tried to run coreboot under qemu, I was at first positively 
surprised how well the things worked. The BIOS + linux kernel payload 
booted in no time! But when I then tried to set up networking, I 
couldn't get that to work. Somehow the linux kernel couldn't locate the 
interrupts of the NIC. After some digging I found out that coreboot 
doesn't provide ACPI tables and instead uses PCI IRQ table (I had to 
extract this table from a running qemu system using the getpir utility 
and then copy it to coreboot, if you want that patch, I can send that 
too). Coreboot copies this table at runtime into memory at 0xf0000. 
Apparently 0xf0000-0xfffff is part of the ISA BIOS, and qemu marks this 
range as read-only.
The attached patch for qemu fixes that and also cleans up some of the 
memory initialization. Instead of marking the ISA BIOS as read-only, it 
copies that part from the BIOS image into the appropriate place (at 
0xf0000-0xfffff) and leaves the memory as read-write.

tom
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From svn at coreboot.org  Fri Dec  5 20:45:09 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 20:45:09 +0100
Subject: [coreboot] r255 - in buildrom-devel/packages: coreboot-v2
	coreboot-v3 coreinfo filo geodevsa grub2 libpayload nrv2b ofw
	openbios
Message-ID: <mailman.2550.1355071449.16123.coreboot@coreboot.org>

Author: ward
Date: 2008-12-05 20:45:09 +0100 (Fri, 05 Dec 2008)
New Revision: 255

Modified:
   buildrom-devel/packages/coreboot-v2/coreboot.inc
   buildrom-devel/packages/coreboot-v3/coreboot-v3.mk
   buildrom-devel/packages/coreinfo/coreinfo.mk
   buildrom-devel/packages/filo/filo.mk
   buildrom-devel/packages/geodevsa/openvsa.inc
   buildrom-devel/packages/grub2/grub2.mk
   buildrom-devel/packages/libpayload/libpayload.mk
   buildrom-devel/packages/nrv2b/nrv2b.mk
   buildrom-devel/packages/ofw/ofw.mk
   buildrom-devel/packages/openbios/openbios.mk
Log:

Small makefile fixes:

1. filo's extract target depended on $(FILO_STAMP_DIR)/.patched, which we don't
have anymore. Replaced with a dependency on $(FILO_STAMP_DIR)/.unpacked

2. add dependency on the relevant LOG_DIR in the TARBALL target for a lot of
packages, to avoid errors when that log directory has not been created yet.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: buildrom-devel/packages/coreboot-v2/coreboot.inc
===================================================================
--- buildrom-devel/packages/coreboot-v2/coreboot.inc	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/coreboot-v2/coreboot.inc	2008-12-05 19:45:09 UTC (rev 255)
@@ -144,7 +144,7 @@
 	@ svn status > $(OUTPUT_DIR)/config/svn/svn.status
 endif
 
-$(SOURCE_DIR)/$(CBV2_TARBALL):
+$(SOURCE_DIR)/$(CBV2_TARBALL): | $(CBV2_LOG_DIR)
 	@ echo "Fetching the coreboot rev $(CBV2_TAG) code..."
 	@ mkdir -p $(SOURCE_DIR)/coreboot
 	@ $(BIN_DIR)/fetchsvn.sh $(CBV2_URL) $(SOURCE_DIR)/coreboot \

Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk
===================================================================
--- buildrom-devel/packages/coreboot-v3/coreboot-v3.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/coreboot-v3/coreboot-v3.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -48,7 +48,7 @@
 
 CBV3_PATCHES ?=
 
-$(SOURCE_DIR)/$(CBV3_TARBALL):
+$(SOURCE_DIR)/$(CBV3_TARBALL): | $(CBV3_LOG_DIR)
 	@ mkdir -p $(SOURCE_DIR)/coreboot-v3
 	@ $(BIN_DIR)/fetchsvn.sh $(CBV3_URL) \
 	$(SOURCE_DIR)/coreboot-v3 $(CBV3_TAG) \

Modified: buildrom-devel/packages/coreinfo/coreinfo.mk
===================================================================
--- buildrom-devel/packages/coreinfo/coreinfo.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/coreinfo/coreinfo.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -22,7 +22,7 @@
 
 COREINFO_TARBALL=coreinfo-svn-$(COREINFO_TAG).tar.gz
 
-$(SOURCE_DIR)/$(COREINFO_TARBALL):
+$(SOURCE_DIR)/$(COREINFO_TARBALL): | $(COREINFO_LOG_DIR)
 	@ mkdir -p $(SOURCE_DIR)/coreinfo
 	@ $(BIN_DIR)/fetchsvn.sh $(COREINFO_URL) $(SOURCE_DIR)/coreinfo \
 	$(COREINFO_TAG) $(SOURCE_DIR)/$(COREINFO_TARBALL) \

Modified: buildrom-devel/packages/filo/filo.mk
===================================================================
--- buildrom-devel/packages/filo/filo.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/filo/filo.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -24,7 +24,7 @@
 	FILO_CONFIG = $(FILO_SRC_DIR)/configs/defconfig
 endif
 
-$(SOURCE_DIR)/$(FILO_TARBALL): 
+$(SOURCE_DIR)/$(FILO_TARBALL): | $(FILO_LOG_DIR)
 	@ mkdir -p $(SOURCE_DIR)/filo
 	@ $(BIN_DIR)/fetchsvn.sh $(FILO_URL) $(SOURCE_DIR)/filo \
 	$(FILO_TAG) $(SOURCE_DIR)/$(FILO_TARBALL) \
@@ -75,7 +75,7 @@
 filo-distclean:
 	@ rm -rf $(FILO_DIR)/*
 
-filo-extract: $(FILO_STAMP_DIR)/.patched
+filo-extract: | $(FILO_STAMP_DIR)/.unpacked
 
 filo-config: | $(FILO_STAMP_DIR)/.configured
 ifeq ($(shell if [ -f $(PACKAGE_DIR)/filo/conf/customconfig--$(PAYLOAD)--$(COREBOOT_VENDOR)-$(COREBOOT_BOARD) ]; then echo 1; fi),1)

Modified: buildrom-devel/packages/geodevsa/openvsa.inc
===================================================================
--- buildrom-devel/packages/geodevsa/openvsa.inc	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/geodevsa/openvsa.inc	2008-12-05 19:45:09 UTC (rev 255)
@@ -17,7 +17,7 @@
 OPENVSA_FETCH_LOG=$(OPENVSA_LOG_DIR)/fetch.log
 endif
 
-$(SOURCE_DIR)/$(OPENVSA_TARBALL):
+$(SOURCE_DIR)/$(OPENVSA_TARBALL): | $(OPENVSA_LOG_DIR)
 	@ mkdir -p $(SOURCE_DIR)/openvsa
 	@ mkdir -p $(OPENVSA_LOG_DIR)
 	@ echo "Fetching openvsa..."

Modified: buildrom-devel/packages/grub2/grub2.mk
===================================================================
--- buildrom-devel/packages/grub2/grub2.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/grub2/grub2.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -29,7 +29,7 @@
 	GRUB2_CONFIG = $(GRUB2_SRC_DIR)/configs/defconfig
 endif
 
-$(SOURCE_DIR)/$(GRUB2_TARBALL): 
+$(SOURCE_DIR)/$(GRUB2_TARBALL): | $(GRUB2_LOG_DIR)
 	@ mkdir -p $(SOURCE_DIR)/grub2
 	@ $(BIN_DIR)/fetchsvn.sh $(GRUB2_URL) $(SOURCE_DIR)/grub2 \
 	$(GRUB2_TAG) $(SOURCE_DIR)/$(GRUB2_TARBALL) \

Modified: buildrom-devel/packages/libpayload/libpayload.mk
===================================================================
--- buildrom-devel/packages/libpayload/libpayload.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/libpayload/libpayload.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -28,7 +28,7 @@
 
 LIBPAYLOAD_TARBALL=libpayload-svn-$(LIBPAYLOAD_TAG).tar.gz
 
-$(SOURCE_DIR)/$(LIBPAYLOAD_TARBALL):
+$(SOURCE_DIR)/$(LIBPAYLOAD_TARBALL): | $(LIBPAYLOAD_LOG_DIR)
 	@ mkdir -p $(SOURCE_DIR)/libpayload
 	@ $(BIN_DIR)/fetchsvn.sh $(LIBPAYLOAD_URL) $(SOURCE_DIR)/libpayload \
 	$(LIBPAYLOAD_TAG) $(SOURCE_DIR)/$(LIBPAYLOAD_TARBALL) \

Modified: buildrom-devel/packages/nrv2b/nrv2b.mk
===================================================================
--- buildrom-devel/packages/nrv2b/nrv2b.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/nrv2b/nrv2b.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -15,7 +15,7 @@
 NRV2B_FETCH_LOG=$(NRV2B_LOG_DIR)/fetch.log
 endif
 
-$(SOURCE_DIR)/$(NRV2B_TARBALL):
+$(SOURCE_DIR)/$(NRV2B_TARBALL): | $(NRV2B_LOG_DIR)
 	@ mkdir -p $(SOURCE_DIR)/nrv2b
 	@ $(BIN_DIR)/fetchsvn.sh $(NRV2B_URL) $(SOURCE_DIR)/nrv2b \
 	$(NRV2B_TAG) $@ > $(NRV2B_FETCH_LOG) 2>&1

Modified: buildrom-devel/packages/ofw/ofw.mk
===================================================================
--- buildrom-devel/packages/ofw/ofw.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/ofw/ofw.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -26,7 +26,7 @@
 # NOTE - this should be replaced by the GIT fetch or tarball fetch
 # as appropriate
 
-$(SOURCE_DIR)/$(OFW_TARBALL):
+$(SOURCE_DIR)/$(OFW_TARBALL): | $(OFW_LOG_DIR)
 	@ echo "Fetching OpenFirmware..."
 	@ echo "SVN Checkout rev $(OFW_SVN_TAG)"
 	@ $(BIN_DIR)/fetchsvn.sh $(OFW_SVN_URL) $(SOURCE_DIR)/ofw \

Modified: buildrom-devel/packages/openbios/openbios.mk
===================================================================
--- buildrom-devel/packages/openbios/openbios.mk	2008-11-26 21:21:30 UTC (rev 254)
+++ buildrom-devel/packages/openbios/openbios.mk	2008-12-05 19:45:09 UTC (rev 255)
@@ -31,7 +31,7 @@
 $(error To build OpenBIOS, you need to install 'fcode-utils')
 endif
 
-$(SOURCE_DIR)/$(OPENBIOS_TARBALL):
+$(SOURCE_DIR)/$(OPENBIOS_TARBALL): | $(OPENBIOS_LOG_DIR)
 	@ echo "Fetching OpenBIOS..."
 	@ echo "SVN Checkout rev $(OPENBIOS_SVN_TAG)"
 	@ $(BIN_DIR)/fetchsvn.sh $(OPENBIOS_SVN_URL) $(SOURCE_DIR)/openbios \




From stepan at coresystems.de  Fri Dec  5 21:54:26 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Dec 2008 21:54:26 +0100
Subject: [coreboot] AMD MCT fixes
Message-ID: <49399502.4060003@coresystems.de>

See patch

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From rminnich at gmail.com  Fri Dec  5 22:17:38 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Dec 2008 13:17:38 -0800
Subject: [coreboot] patch: smm support
Message-ID: <13426df10812051317s151ed268q49a3089ef98f46f9@mail.gmail.com>

attached.

ron
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From marcj303 at gmail.com  Fri Dec  5 22:42:50 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 5 Dec 2008 14:42:50 -0700
Subject: [coreboot] AMD MCT fixes
In-Reply-To: <49399502.4060003@coresystems.de>
References: <49399502.4060003@coresystems.de>
Message-ID: <534e5dc20812051342h24a215e6j3f94b82d5f946702@mail.gmail.com>

On Fri, Dec 5, 2008 at 1:54 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
> See patch
>
> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
>
>
> Fixes to AMD MCT code, found by Marco Schmidt <mschmidt at dspace.de>
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>


Acked-by: Marc Jones <marcj303 at gmail.com>



From marcj303 at gmail.com  Fri Dec  5 23:08:19 2008
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 5 Dec 2008 15:08:19 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <2831fecf0812031043i31aa57edp157d64b1a51f3565@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<2831fecf0812021006x5933204fna6a219e3d55161f7@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
	<2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
	<13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>
	<7872596BBD834D33A5FAF4A70E79BE0F@chimp>
	<534e5dc20812021851n4fc902bdk1f6b342dad9c0086@mail.gmail.com>
	<D0438496826F46CF9F3998C8AB663B61@chimp>
	<2831fecf0812031043i31aa57edp157d64b1a51f3565@mail.gmail.com>
Message-ID: <534e5dc20812051408m3636491aw9c373b7ca8906a66@mail.gmail.com>

On Wed, Dec 3, 2008 at 11:43 AM, Myles Watson <mylesgw at gmail.com> wrote:

> A question before the code:
> 1. Can anyone enumerate all the fixed resources that should be included in
> QEMU?
> Currently I have:
> - DRAM (first 640K and 0xc0000-TOP-768K) Is this necessary?
> - I/O first 0x400 in southbridge
> - VGA 0xa0000-0xc0000
> - APIC at 0xfec00000 and 0xfee00000
> - ROM at 0xfff80000

This looks normal. You could put the first 0x1000 in the SB IMO.

>
> Side note: Only the lowest and highest fixed addresses matter in my code.
> The others get ignored.  I think it's too much pain to try to interleave
> them to use the space between 0xfee00000 and 0xfff80000, for example.

This is probably ok for a normal system. There is a problem with this
if a device is already setup and should be treated as fixed but if
that is the case it should be seup in the dts....

>     /* Initialize constraints to maximum size. */
>
>     limits.pref.base = 0;
>     limits.pref.limit = 0xfffffffffffffffULL;
>     limits.io.base = 0;
>     limits.io.limit = 0xfffffffffffffffULL;
>     limits.mem.base = 0;
>     limits.mem.limit = 0xfffffffffffffffULL;

The limit for memory and prefetch should be the same since they are in
the same address space. For mem.base I assume it gets set from TOM
(for K8) somehow?

Marc



From c-d.hailfinger.devel.2006 at gmx.net  Fri Dec  5 23:11:21 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Dec 2008 23:11:21 +0100
Subject: [coreboot] patch: smm support
In-Reply-To: <13426df10812051317s151ed268q49a3089ef98f46f9@mail.gmail.com>
References: <13426df10812051317s151ed268q49a3089ef98f46f9@mail.gmail.com>
Message-ID: <4939A709.30506@gmx.net>

On 05.12.2008 22:17, ron minnich wrote:
> Add support for creating an smm top-level object. 
>
> Whether SMM is added or not depends on the mainboard. To enable SMM, 
> the Kconfig variable SMM should be set, and the SMM variable should be 
> defined in the mainbard. 
>
> Also correct a type CONFIG_HPET should be HPET. 
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>
> Index: mainboard/kontron/Kconfig
> ===================================================================
> --- mainboard/kontron/Kconfig	(revision 1064)
> +++ mainboard/kontron/Kconfig	(working copy)
> @@ -32,6 +32,7 @@
>  	select SOUTHBRIDGE_INTEL_I82801GX
>  	select SUPERIO_WINBOND_W83627THG
>  	select PIRQ_TABLE
> +	select SMM
>  	help
>  	  Kontron 986LCD-M Series mainboards
>  
> Index: mainboard/kontron/986lcd-m/mainboard.h
> ===================================================================
> --- mainboard/kontron/986lcd-m/mainboard.h	(revision 1064)
> +++ mainboard/kontron/986lcd-m/mainboard.h	(working copy)
> @@ -31,3 +31,5 @@
>  /* nowhere else to go yet */
>  #define TEST_SMM_FLASH_LOCKDOWN 0
>  
> +#define TTYS0_BASE 0x3f8
> +
> Index: mainboard/kontron/986lcd-m/Makefile
> ===================================================================
> --- mainboard/kontron/986lcd-m/Makefile	(revision 1064)
> +++ mainboard/kontron/986lcd-m/Makefile	(working copy)
> @@ -35,3 +35,4 @@
>  	$(Q)printf "  BUILD   DUMMY VPD\n"
>  	$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
>  
> +SMM=$(obj)/southbridge/intel/i82801gx/smm.elf

Hm. Here you use the = operator.

> Index: arch/x86/Kconfig
> ===================================================================
> --- arch/x86/Kconfig	(revision 1064)
> +++ arch/x86/Kconfig	(working copy)
> @@ -72,13 +72,21 @@
>  	  arch/x86/Makefile for more hints on possible values.
>  	  It is usually set in mainboard/*/Kconfig.
>  
> -config CONFIG_HPET
> +config HPET
>  	boolean
>  	depends CPU_AMD_K8
>  	help
>  	  Whether to configure a High Precision Event Timer (HPET). Note that
>  	  HPETs are known to be bug-prone.
>  
> +config SMM
> +	boolean
> +	help
> +	  Whether to configure System Management Mode support. 
> +	  This is mainboard-enabled. This is a tricky option that 
> +	  should not be enabled/disabled casually, as some chipsets
> +	  will not work without some form of SMM enabled.
> +
>  config K8_REV_F_SUPPORT
>  	hex
>  	default 0 if CPU_AMD_K8
> Index: arch/x86/Makefile
> ===================================================================
> --- arch/x86/Makefile	(revision 1064)
> +++ arch/x86/Makefile	(working copy)
> @@ -48,7 +48,7 @@
>  COMPRESSFLAG := -C nrv2b
>  endif
>  
> -$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table
> +$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table $(SMM)
>  	$(Q)printf "  LAR     $(subst $(shell pwd)/,,$(@))\n"
>  	$(Q)rm -f $(obj)/coreboot.rom
>  	$(Q)cd $(obj) && \
> @@ -74,6 +74,10 @@
>  	$(Q)printf "  ZEROING lar -z ./coreboot.rom\n"
>  	$(Q)cd $(obj) && ./util/lar/lar -z ./coreboot.rom
>  endif
> +ifeq ($(CONFIG_SMM),y)
> +	$(Q)printf "  Adding smm.elf\n"
> +	$(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a $(obj)/coreboot.rom $(SMM):normal/smm;
> +endif
>  	$(Q)# QEMU wants bios.bin:
>  	$(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero".
>  	$(Q)printf "  CP      $(subst $(shell pwd)/,,$(obj)/bios.bin)\n"
> Index: Makefile
> ===================================================================
> --- Makefile	(revision 1064)
> +++ Makefile	(working copy)
> @@ -109,6 +109,9 @@
>  # the compiler actually used for the build (e.g. on cross compiler setups).
>  CFLAGS += -nostdinc -isystem `$(CC) -print-file-name=include`
>  
> +# Optional SMM
> +SMM=

Same here.

> +
>  include lib/Makefile
>  include device/Makefile
>  include mainboard/$(MAINBOARDDIR)/Makefile
>
>

If you explain or change the makefile hunks I commented on, the patch is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Fri Dec  5 23:11:54 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Dec 2008 23:11:54 +0100
Subject: [coreboot] patch: smm support
In-Reply-To: <13426df10812051317s151ed268q49a3089ef98f46f9@mail.gmail.com>
References: <13426df10812051317s151ed268q49a3089ef98f46f9@mail.gmail.com>
Message-ID: <4939A72A.1060006@coresystems.de>

ron minnich wrote:
> attached.
>
> ron
>   
> Add support for creating an smm top-level object. 
>
> Whether SMM is added or not depends on the mainboard. 
Actually, now that I read it, it kind of "depends" on the CPU,
northbridge and southbridge. But for us, having it tied to a mainboard
probably makes most sense, for now.

> To enable SMM, 
> the Kconfig variable SMM should be set, and the SMM variable should be 
> defined in the mainbard. 
>
> Also correct a type CONFIG_HPET should be HPET. 
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   
Acked-by: Stefan Reinauer <stepan at coresystems.de>


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From mylesgw at gmail.com  Fri Dec  5 23:13:05 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 5 Dec 2008 15:13:05 -0700
Subject: [coreboot] Resource Allocation discussion
In-Reply-To: <534e5dc20812051408m3636491aw9c373b7ca8906a66@mail.gmail.com>
References: <2831fecf0812011337k623ffa94m18d5f111a731ed80@mail.gmail.com>
	<534e5dc20812021059q3b9b2564h31d97820e5a077b@mail.gmail.com>
	<2831fecf0812021109g24553101kc6ad30f9df4384cc@mail.gmail.com>
	<2831fecf0812021133q383563e7pd1ab14e6420afa73@mail.gmail.com>
	<13426df10812021351tc2b12a0w53e169edc31352e2@mail.gmail.com>
	<7872596BBD834D33A5FAF4A70E79BE0F@chimp>
	<534e5dc20812021851n4fc902bdk1f6b342dad9c0086@mail.gmail.com>
	<D0438496826F46CF9F3998C8AB663B61@chimp>
	<2831fecf0812031043i31aa57edp157d64b1a51f3565@mail.gmail.com>
	<534e5dc20812051408m3636491aw9c373b7ca8906a66@mail.gmail.com>
Message-ID: <2831fecf0812051413t3ad07f1fr46fe7f579a417d78@mail.gmail.com>

On Fri, Dec 5, 2008 at 3:08 PM, Marc Jones <marcj303 at gmail.com> wrote:

> On Wed, Dec 3, 2008 at 11:43 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
> > A question before the code:
> > 1. Can anyone enumerate all the fixed resources that should be included
> in
> > QEMU?
> > Currently I have:
> > - DRAM (first 640K and 0xc0000-TOP-768K) Is this necessary?
> > - I/O first 0x400 in southbridge
> > - VGA 0xa0000-0xc0000
> > - APIC at 0xfec00000 and 0xfee00000
> > - ROM at 0xfff80000
>
> This looks normal. You could put the first 0x1000 in the SB IMO.

I changed it, thanks.


> >
> > Side note: Only the lowest and highest fixed addresses matter in my code.
> > The others get ignored.  I think it's too much pain to try to interleave
> > them to use the space between 0xfee00000 and 0xfff80000, for example.
>
> This is probably ok for a normal system. There is a problem with this
> if a device is already setup and should be treated as fixed but if
> that is the case it should be seup in the dts....
>
> >     /* Initialize constraints to maximum size. */
> >
> >     limits.pref.base = 0;
> >     limits.pref.limit = 0xfffffffffffffffULL;
> >     limits.io.base = 0;
> >     limits.io.limit = 0xfffffffffffffffULL;
> >     limits.mem.base = 0;
> >     limits.mem.limit = 0xfffffffffffffffULL;
>
> The limit for memory and prefetch should be the same since they are in
> the same address space. For mem.base I assume it gets set from TOM
> (for K8) somehow?

The problem comes when they are not in the same address space.  I need to be
able to allocate prefetchable memory above 4G.  The way the code works now,
you only get separate address spaces if the domain asks for it.  Otherwise
they end up in the same space.

Thanks,
Myles
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From svn at coreboot.org  Fri Dec  5 23:38:18 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Dec 2008 23:38:18 +0100
Subject: [coreboot] r3802 - in trunk/coreboot-v2/src/northbridge/amd/amdmct:
	mct wrappers
Message-ID: <mailman.2551.1355071449.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-12-05 23:38:18 +0100 (Fri, 05 Dec 2008)
New Revision: 3802

Modified:
   trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
   trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
Log:
Fixes to AMD MCT code, found by Marco Schmidt <mschmidt at dspace.de>

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Marc Jones <marcj303 at gmail.com>



Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c	2008-12-05 18:38:57 UTC (rev 3801)
+++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c	2008-12-05 22:38:18 UTC (rev 3802)
@@ -3400,6 +3400,8 @@
 	u8 max_dimms;
 
 	// FIXME: skip for Ax
+	
+	dev = pDCTstat->dev_dct;
 
 	/* Tri-state unused ODTs when motherboard termination is available */
 	max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);

Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c	2008-12-05 18:38:57 UTC (rev 3801)
+++ trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c	2008-12-05 22:38:18 UTC (rev 3802)
@@ -197,13 +197,16 @@
 	case NV_CS_SpareCTL:
 		val = 0;	/* Disabled */
 		//val = 1;	/* Enabled */
+		break;
 	case NV_SyncOnUnEccEn:
 		val = 0;	/* Disabled */
 		//val = 1;	/* Enabled */
+		break;
 	case NV_Unganged:
 		/* channel interleave is better performance than ganged mode at this time */
 		val = 1;		/* Enabled */
 		//val = 0;	/* Disabled */
+		break;
 	case NV_ChannelIntlv:
 		val = 5;	/* Not currently checked in mctchi_d.c */
 	/* Bit 0 =     0 - Disable
@@ -213,7 +216,7 @@
 	 *             10b - Hash*, XOR of address bits [20:16, 6]
 	 *             11b - Hash*, XOR of address bits [20:16, 9]
 	 */
-
+		break;
 	}
 
 	return val;




From stepan at coresystems.de  Fri Dec  5 23:39:45 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Dec 2008 23:39:45 +0100
Subject: [coreboot] AMD MCT fixes
In-Reply-To: <534e5dc20812051342h24a215e6j3f94b82d5f946702@mail.gmail.com>
References: <49399502.4060003@coresystems.de>
	<534e5dc20812051342h24a215e6j3f94b82d5f946702@mail.gmail.com>
Message-ID: <4939ADB1.1080507@coresystems.de>

Marc Jones wrote:
> On Fri, Dec 5, 2008 at 1:54 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
>   
>> Fixes to AMD MCT code, found by Marco Schmidt <mschmidt at dspace.de>
>>
>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>     
>
>
> Acked-by: Marc Jones <marcj303 at gmail.com>
>   
Thanks Marc! r3802



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From uwe at hermann-uwe.de  Sat Dec  6 00:02:38 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 6 Dec 2008 00:02:38 +0100
Subject: [coreboot] #107: flashrom: Display test status in -L
	chip	listing
In-Reply-To: <050.35943a3a40d985b6cdf4d594156e163f@coreboot.org>
References: <041.eea91e31685039e0026d8afdaa925b4c@coreboot.org>
	<050.35943a3a40d985b6cdf4d594156e163f@coreboot.org>
Message-ID: <20081205230238.GC26513@greenwood>

On Fri, Dec 05, 2008 at 04:19:49AM -0000, coreboot wrote:
> #107: flashrom: Display test status in -L chip listing
> ----------------------------------+-----------------------------------------
>    Reporter:  stuge               |          Owner:  stuge        
>        Type:  enhancement         |         Status:  assigned     
>    Priority:  minor               |      Milestone:  flashrom v1.0
>   Component:  flashrom            |        Version:               
>    Keywords:  testing             |   Dependencies:               
> Patchstatus:  patch needs review  |  
> ----------------------------------+-----------------------------------------
> Changes (by stuge):
> 
>   * owner:  somebody => stuge
>   * status:  new => assigned
>   * patchstatus:  there is no patch => patch needs review



> flashrom: Display test status in -L chip listing
> 
> Looks like this:
> 
> Supported flash chips:          Tested OK operations:   Known BAD operations:
> 
> AMD Am29F002(N)BB                                       
> AMD Am29F002(N)BT               PROBE READ ERASE WRITE  
> AMD Am29F016D                                           
> AMD Am29F040B                   PROBE READ ERASE WRITE  
> AMD Am29LV040B                                          
> Atmel AT45CS1282                                        READ 
> 
> 
> Signed-off-by: Peter Stuge <peter at stuge.se>

With the small change below this is

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


The output looks nice, patch compiles and works fine.

Please post patches to the list though, trac doesn't automatically
forward them to the list -> harder and more annoying to review, IMO.

 
> Index: flashrom.c
> ===================================================================
> --- flashrom.c	(revision 3797)
> +++ flashrom.c	(working copy)
> @@ -205,14 +205,61 @@
>  	return 0;
>  }
>  
> +#define MAX(a,b) ((a)>(b)?(a):(b))
                ^       ^^  ^^  ^^
             lots of missing spaces here


> +#define POS_PRINT(x) do { pos += strlen(x); printf(x); } while (0)
> +
>  void print_supported_chips(void)
>  {
> -	int i;
> +	int okcol = 0, pos = 0;
> +	struct flashchip *f;
>  
> -	printf("Supported ROM chips:\n\n");
> +	for (f = flashchips; f->name != NULL; f++) {
> +		if (GENERIC_DEVICE_ID == f->model_id)
> +			continue;
> +		okcol = MAX(okcol, strlen(f->vendor) + 1 + strlen(f->name));
> +	}
> +	okcol = (okcol + 7) & ~7;
>  
> -	for (i = 0; flashchips[i].name != NULL; i++)
> -		printf("%s %s\n", flashchips[i].vendor, flashchips[i].name);
> +	POS_PRINT("Supported flash chips:");
> +	while (pos < okcol) {
> +		printf("\t");
> +		pos += 8 - (pos % 8);
> +	}
> +	printf("Tested OK operations:\tKnown BAD operations:\n\n");
> +
> +	for (f = flashchips; f->name != NULL; f++) {
> +		printf("%s %s", f->vendor, f->name);
> +		pos = strlen(f->vendor) + 1 + strlen(f->name);
> +		while (pos < okcol) {
> +			printf("\t");
> +			pos += 8 - (pos % 8);
> +		}
> +		if ((f->tested & TEST_OK_MASK)) {
> +			if ((f->tested & TEST_OK_PROBE))
> +				POS_PRINT("PROBE ");
> +			if ((f->tested & TEST_OK_READ))
> +				POS_PRINT("READ ");
> +			if ((f->tested & TEST_OK_ERASE))
> +				POS_PRINT("ERASE ");
> +			if ((f->tested & TEST_OK_WRITE))
> +				POS_PRINT("WRITE");
> +		}
> +		while (pos < okcol + 24) {
> +			printf("\t");
> +			pos += 8 - (pos % 8);
> +		}
> +		if ((f->tested & TEST_BAD_MASK)) {
> +			if ((f->tested & TEST_BAD_PROBE))
> +				POS_PRINT("PROBE ");
> +			if ((f->tested & TEST_BAD_READ))
> +				POS_PRINT("READ ");
> +			if ((f->tested & TEST_BAD_ERASE))
> +				POS_PRINT("ERASE ");
> +			if ((f->tested & TEST_BAD_WRITE))
> +				POS_PRINT("WRITE");
> +		}
> +		printf("\n");
> +	}
>  }
>  
>  void usage(const char *name)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From svn at coreboot.org  Sat Dec  6 02:37:09 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  6 Dec 2008 02:37:09 +0100
Subject: [coreboot] r3803 - trunk/util/flashrom
Message-ID: <mailman.2552.1355071449.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-12-06 02:37:09 +0100 (Sat, 06 Dec 2008)
New Revision: 3803

Modified:
   trunk/util/flashrom/flashrom.c
Log:
flashrom: Display test status in -L chip listing

Looks like this:

Supported flash chips:          Tested OK operations:   Known BAD operations:

AMD Am29F002(N)BB                                       
AMD Am29F002(N)BT               PROBE READ ERASE WRITE  
AMD Am29F016D                                           
AMD Am29F040B                   PROBE READ ERASE WRITE  
AMD Am29LV040B                                          
Atmel AT45CS1282                                        READ 

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-12-05 22:38:18 UTC (rev 3802)
+++ trunk/util/flashrom/flashrom.c	2008-12-06 01:37:09 UTC (rev 3803)
@@ -205,14 +205,61 @@
 	return 0;
 }
 
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define POS_PRINT(x) do { pos += strlen(x); printf(x); } while (0)
+
 void print_supported_chips(void)
 {
-	int i;
+	int okcol = 0, pos = 0;
+	struct flashchip *f;
 
-	printf("Supported ROM chips:\n\n");
+	for (f = flashchips; f->name != NULL; f++) {
+		if (GENERIC_DEVICE_ID == f->model_id)
+			continue;
+		okcol = MAX(okcol, strlen(f->vendor) + 1 + strlen(f->name));
+	}
+	okcol = (okcol + 7) & ~7;
 
-	for (i = 0; flashchips[i].name != NULL; i++)
-		printf("%s %s\n", flashchips[i].vendor, flashchips[i].name);
+	POS_PRINT("Supported flash chips:");
+	while (pos < okcol) {
+		printf("\t");
+		pos += 8 - (pos % 8);
+	}
+	printf("Tested OK operations:\tKnown BAD operations:\n\n");
+
+	for (f = flashchips; f->name != NULL; f++) {
+		printf("%s %s", f->vendor, f->name);
+		pos = strlen(f->vendor) + 1 + strlen(f->name);
+		while (pos < okcol) {
+			printf("\t");
+			pos += 8 - (pos % 8);
+		}
+		if ((f->tested & TEST_OK_MASK)) {
+			if ((f->tested & TEST_OK_PROBE))
+				POS_PRINT("PROBE ");
+			if ((f->tested & TEST_OK_READ))
+				POS_PRINT("READ ");
+			if ((f->tested & TEST_OK_ERASE))
+				POS_PRINT("ERASE ");
+			if ((f->tested & TEST_OK_WRITE))
+				POS_PRINT("WRITE");
+		}
+		while (pos < okcol + 24) {
+			printf("\t");
+			pos += 8 - (pos % 8);
+		}
+		if ((f->tested & TEST_BAD_MASK)) {
+			if ((f->tested & TEST_BAD_PROBE))
+				printf("PROBE ");
+			if ((f->tested & TEST_BAD_READ))
+				printf("READ ");
+			if ((f->tested & TEST_BAD_ERASE))
+				printf("ERASE ");
+			if ((f->tested & TEST_BAD_WRITE))
+				printf("WRITE");
+		}
+		printf("\n");
+	}
 }
 
 void usage(const char *name)




From peter at stuge.se  Sat Dec  6 02:37:48 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 6 Dec 2008 02:37:48 +0100
Subject: [coreboot] #107: flashrom: Display test status in -L
	chip	listing
In-Reply-To: <20081205230238.GC26513@greenwood>
References: <041.eea91e31685039e0026d8afdaa925b4c@coreboot.org>
	<050.35943a3a40d985b6cdf4d594156e163f@coreboot.org>
	<20081205230238.GC26513@greenwood>
Message-ID: <20081206013748.18591.qmail@stuge.se>

Uwe Hermann wrote:
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Thanks, r3803.


> Please post patches to the list though, trac doesn't automatically
> forward them to the list -> harder and more annoying to review, IMO.

Hm yea understand.


//Peter



From svn at coreboot.org  Sat Dec  6 02:38:51 2008
From: svn at coreboot.org (coreboot)
Date: Sat, 06 Dec 2008 01:38:51 -0000
Subject: [coreboot] #107: flashrom: Display test status in -L chip
 listing
In-Reply-To: <041.eea91e31685039e0026d8afdaa925b4c@coreboot.org>
References: <041.eea91e31685039e0026d8afdaa925b4c@coreboot.org>
Message-ID: <050.dca80649a409c0162323657f69e18c5f@coreboot.org>

#107: flashrom: Display test status in -L chip listing
----------------------------+-----------------------------------------------
    Reporter:  stuge        |         Owner:  stuge                   
        Type:  enhancement  |        Status:  closed                  
    Priority:  minor        |     Milestone:  flashrom v1.0           
   Component:  flashrom     |       Version:                          
  Resolution:  fixed        |      Keywords:  testing                 
Dependencies:               |   Patchstatus:  patch has been committed
----------------------------+-----------------------------------------------
Changes (by stuge):

  * status:  assigned => closed
  * patchstatus:  patch needs review => patch has been committed
  * resolution:  => fixed


Comment:

 r3803

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/107#comment:4>
coreboot <http://www.coreboot.org/>


From kevin at koconnor.net  Sat Dec  6 03:16:18 2008
From: kevin at koconnor.net (Kevin O'Connor)
Date: Fri, 5 Dec 2008 21:16:18 -0500
Subject: [coreboot] qemu floppy filo or ...
In-Reply-To: <13426df10812051121n5078f3a3y744c46f9aaebd2eb@mail.gmail.com>
References: <13426df10812051053x1d8b96ffnb053d35a140fdd09@mail.gmail.com>
	<20081205190128.27809.qmail@stuge.se>
	<13426df10812051121n5078f3a3y744c46f9aaebd2eb@mail.gmail.com>
Message-ID: <20081206021618.GA18622@morn.localdomain>

On Fri, Dec 05, 2008 at 11:21:40AM -0800, ron minnich wrote:
> On Fri, Dec 5, 2008 at 11:01 AM, Peter Stuge <peter at stuge.se> wrote:
> > ron minnich wrote:
> >> So, has anybody tried to boot a floppy i qemu lately? Just had a
> >> request. I'm not even sure how to proceed.
> >
> > Try SeaBIOS? I don't think FILO has a floppy driver.
> >
> 
> yeah, I guess that's the only option.
> 
> Has anyone tried it however.

I've tested qemu+SeaBIOS with floppies.  I'm sure
qemu+coreboot+SeaBIOS would work with floppies, but it's currently
disabled.  (If you look in src/floppy.c you'll see a specific test
that turns off floppy support when coreboot support is enabled.)  I
disabled the support because I wasn't sure if it would work on real
hardware and I didn't want to complicate testing of other things.

-Kevin



From svn at coreboot.org  Sat Dec  6 04:59:24 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  6 Dec 2008 04:59:24 +0100
Subject: [coreboot] r1065 - in coreboot-v3: arch/x86 mainboard/kontron
	mainboard/kontron/986lcd-m
Message-ID: <mailman.2553.1355071449.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-12-06 04:59:24 +0100 (Sat, 06 Dec 2008)
New Revision: 1065

Modified:
   coreboot-v3/arch/x86/Kconfig
   coreboot-v3/arch/x86/Makefile
   coreboot-v3/mainboard/kontron/986lcd-m/Makefile
   coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h
   coreboot-v3/mainboard/kontron/Kconfig
Log:
Add support for creating an smm top-level object. 

Whether SMM is added or not depends on the mainboard. To enable SMM, 
the Kconfig variable SMM should be set, and the SMM variable should be 
defined in the mainbard. 

Also correct a type CONFIG_HPET should be HPET. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig	2008-12-03 23:39:49 UTC (rev 1064)
+++ coreboot-v3/arch/x86/Kconfig	2008-12-06 03:59:24 UTC (rev 1065)
@@ -72,13 +72,21 @@
 	  arch/x86/Makefile for more hints on possible values.
 	  It is usually set in mainboard/*/Kconfig.
 
-config CONFIG_HPET
+config HPET
 	boolean
 	depends CPU_AMD_K8
 	help
 	  Whether to configure a High Precision Event Timer (HPET). Note that
 	  HPETs are known to be bug-prone.
 
+config SMM
+	boolean
+	help
+	  Whether to configure System Management Mode support. 
+	  This is mainboard-enabled. This is a tricky option that 
+	  should not be enabled/disabled casually, as some chipsets
+	  will not work without some form of SMM enabled.
+
 config K8_REV_F_SUPPORT
 	hex
 	default 0 if CPU_AMD_K8

Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-12-03 23:39:49 UTC (rev 1064)
+++ coreboot-v3/arch/x86/Makefile	2008-12-06 03:59:24 UTC (rev 1065)
@@ -48,7 +48,7 @@
 COMPRESSFLAG := -C nrv2b
 endif
 
-$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table
+$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table $(SMM)
 	$(Q)printf "  LAR     $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)rm -f $(obj)/coreboot.rom
 	$(Q)cd $(obj) && \
@@ -74,6 +74,10 @@
 	$(Q)printf "  ZEROING lar -z ./coreboot.rom\n"
 	$(Q)cd $(obj) && ./util/lar/lar -z ./coreboot.rom
 endif
+ifeq ($(CONFIG_SMM),y)
+	$(Q)printf "  Adding smm.elf\n"
+	$(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a $(obj)/coreboot.rom $(SMM):normal/smm;
+endif
 	$(Q)# QEMU wants bios.bin:
 	$(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero".
 	$(Q)printf "  CP      $(subst $(shell pwd)/,,$(obj)/bios.bin)\n"

Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/Makefile	2008-12-03 23:39:49 UTC (rev 1064)
+++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile	2008-12-06 03:59:24 UTC (rev 1065)
@@ -35,3 +35,4 @@
 	$(Q)printf "  BUILD   DUMMY VPD\n"
 	$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
 
+SMM := $(obj)/southbridge/intel/i82801gx/smm.elf

Modified: coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h	2008-12-03 23:39:49 UTC (rev 1064)
+++ coreboot-v3/mainboard/kontron/986lcd-m/mainboard.h	2008-12-06 03:59:24 UTC (rev 1065)
@@ -31,3 +31,5 @@
 /* nowhere else to go yet */
 #define TEST_SMM_FLASH_LOCKDOWN 0
 
+#define TTYS0_BASE 0x3f8
+

Modified: coreboot-v3/mainboard/kontron/Kconfig
===================================================================
--- coreboot-v3/mainboard/kontron/Kconfig	2008-12-03 23:39:49 UTC (rev 1064)
+++ coreboot-v3/mainboard/kontron/Kconfig	2008-12-06 03:59:24 UTC (rev 1065)
@@ -32,6 +32,7 @@
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_WINBOND_W83627THG
 	select PIRQ_TABLE
+	select SMM
 	help
 	  Kontron 986LCD-M Series mainboards
 




From rminnich at gmail.com  Sat Dec  6 05:00:24 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Dec 2008 20:00:24 -0800
Subject: [coreboot] patch: smm support
In-Reply-To: <4939A72A.1060006@coresystems.de>
References: <13426df10812051317s151ed268q49a3089ef98f46f9@mail.gmail.com>
	<4939A72A.1060006@coresystems.de>
Message-ID: <13426df10812052000g77b3a72esf4fe099c2533fdc2@mail.gmail.com>

On Fri, Dec 5, 2008 at 2:11 PM, Stefan Reinauer <stepan at coresystems.de> wrote:

> Acked-by: Stefan Reinauer <stepan at coresystems.de>

Committed revision 1065.
with changes requested by carl-daniel.

ron



From joe at settoplinux.org  Sat Dec  6 12:29:48 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 06 Dec 2008 06:29:48 -0500
Subject: [coreboot] LPCflasher rename to Paraflasher
In-Reply-To: <662f8558de20ab17a6b9ce23822477b1@imap.1and1.com>
References: <662f8558de20ab17a6b9ce23822477b1@imap.1and1.com>
Message-ID: <d4d42ebbfc6b375b6eebef70c3f42dcb@imap.1and1.com>




On Thu, 04 Dec 2008 21:29:22 -0500, Joseph Smith <joe at settoplinux.org>
wrote:
> 
> Hello,
> I was thinking of renaming the LPCflasher Project to the Paraflasher
> Project. It will have the ability to flash more than just LPC chips so I
> think it should have a more generalized name hence the Paraflasher
> (Parallel Port Flasher) Project. What does everyone think? If no one
> strongly disagrees I will go ahead and change it.
> 
Rename complete.

http://www.coreboot.org/Paraflasher

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Sat Dec  6 13:52:56 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Dec 2008 13:52:56 +0100
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <dd3c80060812050053o4f16922x948b79d07743d63b@mail.gmail.com>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>	
	<4936C696.8090404@gmx.net> <4936C92A.4060106@cosmicpenguin.net>	
	<17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>	
	<13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>
	<dd3c80060812050053o4f16922x948b79d07743d63b@mail.gmail.com>
Message-ID: <493A75A8.3050800@gmx.net>

On 05.12.2008 09:53, Corey Osgood wrote:
> On Wed, Dec 3, 2008 at 5:27 PM, ron minnich <rminnich at gmail.com> wrote:
>   
>> In fact, if anything, can we please fix the cn700?
>>     
>
> Working on it!
>
> Current status: a GPIO line isn't getting disabled for some reason (even
> though it's disabled several times), and the damn chipset reboots when the
> timer it controls expires. Once the board reboots, something isn't working
> correctly, presumably CAR, and the LAR can't be read from. I'm working from
> revision 1010, but I think it's the same status in current svn. I'll be
> spending more time with it this weekend, from the sound of the weather
> report I won't be able to do much else anyways :p
>   

Could you give me a little more verbose info? If CAR is not working,
printk should not work (or at least crash directly after the first
call). Having the ROM not mapped also looks weird.
I don't doubt your description, I'm just trying to understand it.
In theory, the different cache behaviour of the C7 on poweron could be
related... can you try issuing a reset from inside coreboot and check if
the same problem appears after your deliberate reset? Oh, and please
check how the processor behaves if you press the reset button. I hope to
find a pattern here.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From joe at settoplinux.org  Sat Dec  6 16:22:44 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 06 Dec 2008 10:22:44 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
Message-ID: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>


Hello,
For the Paraflasher project I would like to setup a function to
automatically detect the presence of the PC's parallel ports and their base
addresses. This way it doesn't need to be hard-coded into the program. I
was thinking of using /proc/ioports to do this but I am not really sure how
to do this in C. Here is what I am thinking:

1. First use grep -c paraport /proc/ioports to check if we have multiple
parallel ports and maybe setup loop for it.
2. Then grep paraport /proc/ioports again to get the base address of each
parallel port detected. This is where I am stuck. I just need to turn the
first 4 characters (base address) into a variable. Can anyone help???

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From corey.osgood at gmail.com  Sat Dec  6 17:29:16 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 6 Dec 2008 11:29:16 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
Message-ID: <dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>

On Sat, Dec 6, 2008 at 10:22 AM, Joseph Smith <joe at settoplinux.org> wrote:

>
> Hello,
> For the Paraflasher project I would like to setup a function to
> automatically detect the presence of the PC's parallel ports and their base
> addresses. This way it doesn't need to be hard-coded into the program. I
> was thinking of using /proc/ioports to do this but I am not really sure how
> to do this in C. Here is what I am thinking:
>
> 1. First use grep -c paraport /proc/ioports to check if we have multiple
> parallel ports and maybe setup loop for it.
> 2. Then grep paraport /proc/ioports again to get the base address of each
> parallel port detected. This is where I am stuck. I just need to turn the
> first 4 characters (base address) into a variable. Can anyone help???


There must be a way to do this in C. Maybe do some digging around in the
kernel's include files?

-Corey
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From ward at gnu.org  Sat Dec  6 17:45:33 2008
From: ward at gnu.org (Ward Vandewege)
Date: Sat, 6 Dec 2008 11:45:33 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
Message-ID: <20081206164533.GA16025@localdomain>

On Sat, Dec 06, 2008 at 10:22:44AM -0500, Joseph Smith wrote:
> 
> Hello,
> For the Paraflasher project I would like to setup a function to
> automatically detect the presence of the PC's parallel ports and their base
> addresses. This way it doesn't need to be hard-coded into the program. I
> was thinking of using /proc/ioports to do this but I am not really sure how
> to do this in C. Here is what I am thinking:
> 
> 1. First use grep -c paraport /proc/ioports to check if we have multiple
> parallel ports and maybe setup loop for it.
> 2. Then grep paraport /proc/ioports again to get the base address of each
> parallel port detected. This is where I am stuck. I just need to turn the
> first 4 characters (base address) into a variable. Can anyone help???

Would an environment variable be ok? Sed/awk should be able to do that for
you.

Thanks,
Ward.
 
-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From rminnich at gmail.com  Sat Dec  6 18:35:25 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Dec 2008 09:35:25 -0800
Subject: [coreboot] [PATCH] LAR: Don't clobber top 8 bytes
In-Reply-To: <dd3c80060812050053o4f16922x948b79d07743d63b@mail.gmail.com>
References: <4935E3A6.5060200@gmx.net> <493671FE.10407@coresystems.de>
	<4936C696.8090404@gmx.net> <4936C92A.4060106@cosmicpenguin.net>
	<17E1BFD1-D424-4D22-ACDE-FA17AD45525D@coresystems.de>
	<13426df10812031427g7f609785pf76b7de762aaf88@mail.gmail.com>
	<dd3c80060812050053o4f16922x948b79d07743d63b@mail.gmail.com>
Message-ID: <13426df10812060935p5cf4adf7oa2241b8ea5ee5291@mail.gmail.com>

were you able to get a working rev tested?

Just want to make sure your hardware has not gone bad on you.

ron



From rminnich at gmail.com  Sat Dec  6 18:49:32 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Dec 2008 09:49:32 -0800
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
Message-ID: <13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>

you're making it too hard. :-)

If you do this:
 awk '/rtc/{print $1}'

you get a line like this:
cat /proc/ioports | awk '/rtc/{print $1}'
0070-0071

OK, but you just want the first four digits, right? Well, strtoul will
do this for you, so:
port = strtoul(string, 0, 16);

it will stop at the '-', which is not hex. Problem solved.

But how do I get this into a program?

paraflash `awk '/rtc/{print $1}'`

First arg will be the port addresses.

Instead of 'rtc', use whatever your parallel port name is.

Did you want more than one? Here's another example:
[rminnich at xcpu2 coreboot-v3]$ echo `cat /proc/ioports | awk '/ahci/{print $1}' `
1c20-1c3f 1c40-1c43 1c44-1c47 1c48-1c4f 1c50-1c57
[rminnich at xcpu2 coreboot-v3]$

So your program will see a sequence of arguments, one for each parallel port.

You don't have to do it exactly this way, but this is why we have all
these fiddly little tools, so you can put things together without
having to write lots of code.

If you don't want users to see this commnand, use popen(3).

thanks

ron



From joe at settoplinux.org  Sat Dec  6 19:07:06 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 06 Dec 2008 13:07:06 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
	<13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>
Message-ID: <5c941ebbecea6751ead0cbfd289874a1@imap.1and1.com>




On Sat, 6 Dec 2008 09:49:32 -0800, "ron minnich" <rminnich at gmail.com>
wrote:
> you're making it too hard. :-)
> 
> If you do this:
>  awk '/rtc/{print $1}'
> 
> you get a line like this:
> cat /proc/ioports | awk '/rtc/{print $1}'
> 0070-0071
> 
> OK, but you just want the first four digits, right? Well, strtoul will
> do this for you, so:
> port = strtoul(string, 0, 16);
> 
> it will stop at the '-', which is not hex. Problem solved.
> 
> But how do I get this into a program?
> 
> paraflash `awk '/rtc/{print $1}'`
> 
> First arg will be the port addresses.
> 
> Instead of 'rtc', use whatever your parallel port name is.
> 
> Did you want more than one? Here's another example:
> [rminnich at xcpu2 coreboot-v3]$ echo `cat /proc/ioports | awk '/ahci/{print
> $1}' `
> 1c20-1c3f 1c40-1c43 1c44-1c47 1c48-1c4f 1c50-1c57
> [rminnich at xcpu2 coreboot-v3]$
> 
> So your program will see a sequence of arguments, one for each parallel
> port.
> 
> You don't have to do it exactly this way, but this is why we have all
> these fiddly little tools, so you can put things together without
> having to write lots of code.
> 
> If you don't want users to see this commnand, use popen(3).
> 
Awsome, that is exacly what I was looking for, thanks Ron.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Sat Dec  6 19:51:28 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 06 Dec 2008 13:51:28 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <5c941ebbecea6751ead0cbfd289874a1@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
	<13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>
	<5c941ebbecea6751ead0cbfd289874a1@imap.1and1.com>
Message-ID: <18a995282ba1543bfddd21154c254536@imap.1and1.com>




On Sat, 06 Dec 2008 13:07:06 -0500, Joseph Smith <joe at settoplinux.org>
wrote:
> 
> 
> 
> On Sat, 6 Dec 2008 09:49:32 -0800, "ron minnich" <rminnich at gmail.com>
> wrote:
>> you're making it too hard. :-)
>>
>> If you do this:
>>  awk '/rtc/{print $1}'
>>
>> you get a line like this:
>> cat /proc/ioports | awk '/rtc/{print $1}'
>> 0070-0071
>>
>> OK, but you just want the first four digits, right? Well, strtoul will
>> do this for you, so:
>> port = strtoul(string, 0, 16);
>>
>> it will stop at the '-', which is not hex. Problem solved.
>>
>> But how do I get this into a program?
>>
>> paraflash `awk '/rtc/{print $1}'`
>>
>> First arg will be the port addresses.
>>
>> Instead of 'rtc', use whatever your parallel port name is.
>>
>> Did you want more than one? Here's another example:
>> [rminnich at xcpu2 coreboot-v3]$ echo `cat /proc/ioports | awk
> '/ahci/{print
>> $1}' `
>> 1c20-1c3f 1c40-1c43 1c44-1c47 1c48-1c4f 1c50-1c57
>> [rminnich at xcpu2 coreboot-v3]$
>>
>> So your program will see a sequence of arguments, one for each parallel
>> port.
>>
>> You don't have to do it exactly this way, but this is why we have all
>> these fiddly little tools, so you can put things together without
>> having to write lots of code.
>>
>> If you don't want users to see this commnand, use popen(3).
>>
So, to get the command into the program wouldn't I use system() ?

Something like:
base_addrs = system("cat /proc/ioports | awk '/paraport*{print $1}'");

para1_base_addr = strtoul(base_addrs, 0, 16);

This should get the firsts parallel ports base address, right? What if I
want to get the base address of the second parallel port, can I use
strtoul() to skip to the next string after the whitespace?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Sat Dec  6 20:35:28 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 06 Dec 2008 14:35:28 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <18a995282ba1543bfddd21154c254536@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
	<13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>
	<5c941ebbecea6751ead0cbfd289874a1@imap.1and1.com>
	<18a995282ba1543bfddd21154c254536@imap.1and1.com>
Message-ID: <5d63973ed0ee1250139e436acdd8e42a@imap.1and1.com>




On Sat, 06 Dec 2008 13:51:28 -0500, Joseph Smith <joe at settoplinux.org>
wrote:
> 
> 
> 
> On Sat, 06 Dec 2008 13:07:06 -0500, Joseph Smith <joe at settoplinux.org>
> wrote:
>>
>>
>>
>> On Sat, 6 Dec 2008 09:49:32 -0800, "ron minnich" <rminnich at gmail.com>
>> wrote:
>>> you're making it too hard. :-)
>>>
>>> If you do this:
>>>  awk '/rtc/{print $1}'
>>>
>>> you get a line like this:
>>> cat /proc/ioports | awk '/rtc/{print $1}'
>>> 0070-0071
>>>
>>> OK, but you just want the first four digits, right? Well, strtoul will
>>> do this for you, so:
>>> port = strtoul(string, 0, 16);
>>>
>>> it will stop at the '-', which is not hex. Problem solved.
>>>
>>> But how do I get this into a program?
>>>
>>> paraflash `awk '/rtc/{print $1}'`
>>>
>>> First arg will be the port addresses.
>>>
>>> Instead of 'rtc', use whatever your parallel port name is.
>>>
>>> Did you want more than one? Here's another example:
>>> [rminnich at xcpu2 coreboot-v3]$ echo `cat /proc/ioports | awk
>> '/ahci/{print
>>> $1}' `
>>> 1c20-1c3f 1c40-1c43 1c44-1c47 1c48-1c4f 1c50-1c57
>>> [rminnich at xcpu2 coreboot-v3]$
>>>
>>> So your program will see a sequence of arguments, one for each parallel
>>> port.
>>>
>>> You don't have to do it exactly this way, but this is why we have all
>>> these fiddly little tools, so you can put things together without
>>> having to write lots of code.
>>>
>>> If you don't want users to see this commnand, use popen(3).
>>>
> So, to get the command into the program wouldn't I use system() ?
> 
> Something like:
> base_addrs = system("cat /proc/ioports | awk '/paraport*{print $1}'");
> 
> para1_base_addr = strtoul(base_addrs, 0, 16);
> 
> This should get the firsts parallel ports base address, right? What if I
> want to get the base address of the second parallel port, can I use
> strtoul() to skip to the next set of char after the whitespace?

I think I got it:

unsigned long * next;
para1_base_addr = strtoul(base_addrs, &next, 16);
para2_base_addr = strtoul(next, &next, 16);
para3_base_addr = strtoul(next, 0, 16);

right?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From rminnich at gmail.com  Sat Dec  6 20:51:10 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Dec 2008 11:51:10 -0800
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <18a995282ba1543bfddd21154c254536@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
	<13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>
	<5c941ebbecea6751ead0cbfd289874a1@imap.1and1.com>
	<18a995282ba1543bfddd21154c254536@imap.1and1.com>
Message-ID: <13426df10812061151v42ebc4faye44e6a24a19993f8@mail.gmail.com>

system() doesn't give you a pipe to read from.

ron



From peter at stuge.se  Sat Dec  6 22:54:46 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 6 Dec 2008 22:54:46 +0100
Subject: [coreboot] r1065 - in coreboot-v3: arch/x86 mainboard/kontron
	mainboard/kontron/986lcd-m
Message-ID: <20081206215446.30572.qmail@stuge.se>

svn at coreboot.org wrote:
> +	$(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a $(obj)/coreboot.rom $(SMM):normal/smm;

normal/smm vs. blob/vsa - should one of them be changed?


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Sat Dec  6 23:00:29 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Dec 2008 23:00:29 +0100
Subject: [coreboot] r1065 - in coreboot-v3: arch/x86 mainboard/kontron
 mainboard/kontron/986lcd-m
In-Reply-To: <20081206215446.30572.qmail@stuge.se>
References: <20081206215446.30572.qmail@stuge.se>
Message-ID: <493AF5FD.2030603@gmx.net>

On 06.12.2008 22:54, Peter Stuge wrote:
> svn at coreboot.org wrote:
>   
>> +	$(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a $(obj)/coreboot.rom $(SMM):normal/smm;
>>     
>
> normal/smm vs. blob/vsa - should one of them be changed?
>   

Good question. What about normal/vsa?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Sat Dec  6 23:01:02 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Dec 2008 14:01:02 -0800
Subject: [coreboot] r1065 - in coreboot-v3: arch/x86 mainboard/kontron
	mainboard/kontron/986lcd-m
In-Reply-To: <20081206215446.30572.qmail@stuge.se>
References: <20081206215446.30572.qmail@stuge.se>
Message-ID: <13426df10812061401p367f7d72j1318d47b29921196@mail.gmail.com>

On Sat, Dec 6, 2008 at 1:54 PM, Peter Stuge <peter at stuge.se> wrote:
> svn at coreboot.org wrote:
>> +     $(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a $(obj)/coreboot.rom $(SMM):normal/smm;
>
> normal/smm vs. blob/vsa - should one of them be changed?
>

Well my propoosal for blob/smm was rejected :-)

and normal/smm seems pretty safe.

one thing about blob/vsa -- there is unlikely to be a normal/vsa and
fallback/vsa. vsa is unlikely to have a normal and fallback version --
it's a blob.

I think I'm ok with this for now.

ron



From joe at settoplinux.org  Sat Dec  6 23:07:21 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 06 Dec 2008 17:07:21 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <13426df10812061151v42ebc4faye44e6a24a19993f8@mail.gmail.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
	<13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>
	<5c941ebbecea6751ead0cbfd289874a1@imap.1and1.com>
	<18a995282ba1543bfddd21154c254536@imap.1and1.com>
	<13426df10812061151v42ebc4faye44e6a24a19993f8@mail.gmail.com>
Message-ID: <24d2daee9963e8f493115f058854a9c4@imap.1and1.com>




On Sat, 6 Dec 2008 11:51:10 -0800, "ron minnich" <rminnich at gmail.com>
wrote:
>>> But how do I get this into a program?
>>>
>>> paraflash `awk '/rtc/{print $1}'`
>> 
>> base_addrs = system("cat /proc/ioports | awk '/paraport*{print $1}'");
>> 
> 
> system() doesn't give you a pipe to read from.
> 
Hmm. I guess I am a little confused then how I am supposed to call the bash
one-liner from with in the program?

Sorry, I am just trying to understand.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Sat Dec  6 23:08:22 2008
From: svn at coreboot.org (coreboot)
Date: Sat, 06 Dec 2008 22:08:22 -0000
Subject: [coreboot] #105: flashrom: add documentation files (ChangeLog
 etc) that need to be in the release
In-Reply-To: <041.43c89429f4bc2b157cdb53f0a41b38c3@coreboot.org>
References: <041.43c89429f4bc2b157cdb53f0a41b38c3@coreboot.org>
Message-ID: <050.4696d94c33e6dec1425ac0c0a16275c9@coreboot.org>

#105: flashrom: add documentation files (ChangeLog etc) that need to be in the
release
----------------------------+-----------------------------------------------
    Reporter:  stuge        |         Owner:  somebody         
        Type:  enhancement  |        Status:  closed           
    Priority:  blocker      |     Milestone:  flashrom v1.0    
   Component:  flashrom     |       Version:                   
  Resolution:  fixed        |      Keywords:  documentation    
Dependencies:               |   Patchstatus:  there is no patch
----------------------------+-----------------------------------------------
Changes (by stepan):

  * status:  new => closed
  * resolution:  => fixed


Comment:

 Thanks, Uwe. It seems svn log provides a sufficient changelog
 functionality.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/105#comment:4>
coreboot <http://www.coreboot.org/>


From rminnich at gmail.com  Sat Dec  6 23:11:07 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Dec 2008 14:11:07 -0800
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <24d2daee9963e8f493115f058854a9c4@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<dd3c80060812060829o1efcf8f3sf2e20a9cc53361e2@mail.gmail.com>
	<13426df10812060949q7654ae3arf9bc855c6d6cea35@mail.gmail.com>
	<5c941ebbecea6751ead0cbfd289874a1@imap.1and1.com>
	<18a995282ba1543bfddd21154c254536@imap.1and1.com>
	<13426df10812061151v42ebc4faye44e6a24a19993f8@mail.gmail.com>
	<24d2daee9963e8f493115f058854a9c4@imap.1and1.com>
Message-ID: <13426df10812061411h5b1c5eaah2c9fe86e178956d6@mail.gmail.com>

hey, have some fun!

FILE *f;
f = popen("date", "r");

fgets(f, data, sizeof(data));
printf(data);

Any sh command in place of "date" will do.

ron



From svn at coreboot.org  Sat Dec  6 23:16:37 2008
From: svn at coreboot.org (coreboot)
Date: Sat, 06 Dec 2008 22:16:37 -0000
Subject: [coreboot] #102: flashrom: coreboot ROM image file
 identification heuristic is broken
In-Reply-To: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
Message-ID: <050.525eaf579af6c77e9fb028ea140fadec@coreboot.org>

#102: flashrom: coreboot ROM image file identification heuristic is broken
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge              
        Type:  defect    |        Status:  new                
    Priority:  major     |     Milestone:  flashrom v1.0      
   Component:  flashrom  |       Version:                     
  Resolution:            |      Keywords:  rom image heuristic
Dependencies:            |   Patchstatus:  there is no patch  
-------------------------+--------------------------------------------------

Comment(by stepan):

 Let's get this out of the door.

 Carl-Daniel: Is the code tested on a couple of coreboot and non-coreboot
 images?
 Especially it should be tested with ck804 or mcp55 coreboot images.

 If so, this is
 Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102#comment:13>
coreboot <http://www.coreboot.org/>


From peter at stuge.se  Sat Dec  6 23:17:57 2008
From: peter at stuge.se (Peter Stuge)
Date: Sat, 6 Dec 2008 23:17:57 +0100
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
Message-ID: <20081206221757.5445.qmail@stuge.se>

Joseph Smith wrote:
> For the Paraflasher project I would like to setup a function to
> automatically detect the presence of the PC's parallel ports and
> their base addresses.
..
> I was thinking of using /proc/ioports to do this

I'm afraid you can't win this one.

If the kernel knows about the ports (ie. if they are listed in
/proc/ioports) then it's because there is already a driver in the
kernel which is responsible for driving the hardware - and your
/userspace program should not interfere.

If there is no driver loaded, there will be no entry in /proc/ioports
so you won't know which ports to use.

There are two ways to do this while still playing nicely;

1. Interface with the kernel parport driver. This may not work, I'm
not sure if parport offers a userspace API, and if it does I don't
know if it offers functionality suitable for bitbanging the port.

2. Make the user specify an IO port (you can give suggestions, 0x3bc
0x378 and 0x278 are the common ones) and check that this port is NOT
listed in /proc/ioports.


> but I am not really sure how to do this in C.

If you know another language better then just use that. :) It doesn't
matter for flashrom, I want potential future plugin stuff to use IPC
so that hardware drivers can be written in any language.

In C, I would suggest fopen("/proc/ioports","r"), while(fgets()),
then using strstr() to find lines with "parport" and finally sscanf()
to convert the string into an uint16_t variable.

Don't forget error checking and corner cases, make sure that you have
actually read a full line before letting the loop start over.


//Peter



From svn at coreboot.org  Sat Dec  6 23:21:30 2008
From: svn at coreboot.org (coreboot)
Date: Sat, 06 Dec 2008 22:21:30 -0000
Subject: [coreboot] #103: flashrom: Don't exit() after successful erase;
 enable testing all operations in one invocation
In-Reply-To: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
References: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
Message-ID: <050.da9f1fb030afbb49a24ef53da7e5ae5b@coreboot.org>

#103: flashrom: Don't exit() after successful erase; enable testing all
operations in one invocation
----------------------------------+-----------------------------------------
   Reporter:  stuge               |          Owner:  stuge        
       Type:  enhancement         |         Status:  assigned     
   Priority:  minor               |      Milestone:  flashrom v1.0
  Component:  flashrom            |        Version:               
   Keywords:  erase exit testing  |   Dependencies:  #117         
Patchstatus:  patch needs review  |  
----------------------------------+-----------------------------------------
Changes (by stepan):

  * priority:  major => minor


Comment:

 As you said, the new "features" introduced by the patch are rather
 useless.

 If this is about making testing easier, what about explicitly creating a "
 --test" option that does things in a defined order. Then we don't have to
 worry about doing implicit things.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:6>
coreboot <http://www.coreboot.org/>


From stepan at coresystems.de  Sat Dec  6 23:32:26 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 06 Dec 2008 23:32:26 +0100
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
Message-ID: <493AFD7A.4070007@coresystems.de>

Joseph Smith wrote:
> Hello,
> For the Paraflasher project I would like to setup a function to
> automatically detect the presence of the PC's parallel ports and their base
> addresses. This way it doesn't need to be hard-coded into the program. I
> was thinking of using /proc/ioports to do this but I am not really sure how
> to do this in C. Here is what I am thinking:
>
> 1. First use grep -c paraport /proc/ioports to check if we have multiple
> parallel ports and maybe setup loop for it.
> 2. Then grep paraport /proc/ioports again to get the base address of each
> parallel port detected. This is where I am stuck. I just need to turn the
> first 4 characters (base address) into a variable. Can anyone help???
>   

Check out http://people.redhat.com/twaugh/parport/html/parportguide.html

It has some information on how to use /dev/partportX for your purposes.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866





From svn at coreboot.org  Sat Dec  6 23:37:32 2008
From: svn at coreboot.org (coreboot)
Date: Sat, 06 Dec 2008 22:37:32 -0000
Subject: [coreboot] #102: flashrom: coreboot ROM image file
 identification heuristic is broken
In-Reply-To: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
Message-ID: <050.0d546168b3580a8f9da02d9aca0b123a@coreboot.org>

#102: flashrom: coreboot ROM image file identification heuristic is broken
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge              
        Type:  defect    |        Status:  new                
    Priority:  major     |     Milestone:  flashrom v1.0      
   Component:  flashrom  |       Version:                     
  Resolution:            |      Keywords:  rom image heuristic
Dependencies:            |   Patchstatus:  there is no patch  
-------------------------+--------------------------------------------------

Comment(by stuge):

 Hold on, this is a bit tricky.

 This is about flashrom trying to identify the image it is about to flash.
 After identification it checks the vendor/board information in the image
 against that in a coreboot table, and will warn the user if the image
 seems unsuitable for the board flashrom is running on, and require -f to
 override a mismatch.

 The fact is that we are having a very hard time coming up with a test
 which determines whether an image is coreboot or not to begin with, and
 we're also having some difficulties with the technical details of how to
 store image metadata in the image itself.

 I suggest that we completely remove the image detection for 1.0 and add
 the feature back in at a later time when we actually have something close
 to a good solution. We have already spent far too much effort on this
 problem, and it's sole purpose is to warn users when they are
 crossflashing on a board which is running coreboot. I don't think we need
 this.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102#comment:14>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Sat Dec  6 23:48:48 2008
From: svn at coreboot.org (coreboot)
Date: Sat, 06 Dec 2008 22:48:48 -0000
Subject: [coreboot] #103: flashrom: Don't exit() after successful erase;
 enable testing all operations in one invocation
In-Reply-To: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
References: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
Message-ID: <050.ab2a3d1fc4e8420c87b0c519e4ec7fec@coreboot.org>

#103: flashrom: Don't exit() after successful erase; enable testing all
operations in one invocation
----------------------------------+-----------------------------------------
   Reporter:  stuge               |          Owner:  stuge        
       Type:  enhancement         |         Status:  assigned     
   Priority:  major               |      Milestone:  flashrom v1.0
  Component:  flashrom            |        Version:               
   Keywords:  erase exit testing  |   Dependencies:  #117         
Patchstatus:  patch needs review  |  
----------------------------------+-----------------------------------------
Changes (by stuge):

  * priority:  minor => major


Comment:

 I suggested adding -T in #106 (dup of this) and I closed it because the
 patch suggested here achieves the same thing but with the user interface
 -Ewv (already familiar options) instead of -T (which would be new).

 But if everyone is really serious about restricting what flashrom lets the
 user do - unless it is invoked a special way - I guess that's what we have
 to do, but I think it's silly. Let user shoot foot if they try - that's
 why I fell in love with UNIX anyway.

 (And I don't think simplifying the test procedure from many
 flashrom+hexdump commands into a single flashrom command is minor, so
 changing prio back.)

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:7>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Sun Dec  7 00:52:05 2008
From: svn at coreboot.org (coreboot)
Date: Sat, 06 Dec 2008 23:52:05 -0000
Subject: [coreboot] #102: flashrom: coreboot ROM image file
 identification heuristic is broken
In-Reply-To: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
Message-ID: <050.959b23e03aabccadc21010c570317290@coreboot.org>

#102: flashrom: coreboot ROM image file identification heuristic is broken
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge              
        Type:  defect    |        Status:  closed             
    Priority:  major     |     Milestone:  flashrom v1.0      
   Component:  flashrom  |       Version:                     
  Resolution:  fixed     |      Keywords:  rom image heuristic
Dependencies:            |   Patchstatus:  there is no patch  
-------------------------+--------------------------------------------------
Changes (by hailfinger):

  * status:  new => closed
  * resolution:  => fixed


Comment:

 An alternative patch was committed in r3420 which fixes this bug.

 To be honest, having a better signature in coreboot images would help.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102#comment:15>
coreboot <http://www.coreboot.org/>


From rminnich at gmail.com  Sun Dec  7 01:30:40 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Dec 2008 16:30:40 -0800
Subject: [coreboot] fix VT8237S/K8M890 powernow
In-Reply-To: <20081204232922.8525.qmail@stuge.se>
References: <49386600.5080300@assembler.cz>
	<20081204232922.8525.qmail@stuge.se>
Message-ID: <13426df10812061630j72f0f067g5e1f4e6ae8fced4b@mail.gmail.com>

did we get a commit yet?

ron

On Thu, Dec 4, 2008 at 3:29 PM, Peter Stuge <peter at stuge.se> wrote:
> Hi,
>
> Rudolf Marek wrote:
>> I finally got the powernow working after countless hours. And CPU
>> runs fullspeed after power up!
>
> Awesome.
>
>
>> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
>
> Acked-by: Peter Stuge <peter at stuge.se>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From c-d.hailfinger.devel.2006 at gmx.net  Sun Dec  7 01:56:18 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Dec 2008 01:56:18 +0100
Subject: [coreboot] [RFC] coreboot image marker
Message-ID: <493B1F32.3080208@gmx.net>

I'd like to introduce a reasonably safe way to detect whether an image
is a coreboot image.

Goals:
- Easy to implement
- Good for visual inspection of a image file with hexdump
- Fixed location to make detection easy
- Independence of the format of the image data
- Reusable even if we decide to change the image data format completely

The existing solutions and approached do not fulfill all (or even any)
of the goals above.

Proposal:
Use the top 8 bytes of an image to store a short signature and a pointer
to the real data. If the signature is 4 bytes and the pointer is 4
bytes, they fit exactly into the range 0xfffffff8-0xffffffff.
The reset vector lives at 0xfffffff0 and it is a jump instruction with
immediate operand. The instruction is 1 byte, the operand is 2 bytes
(well, 4 bytes in reality due to binutils workarounds, but as the code
is 16bit, only the first two bytes are evaluated). The space after the
reset vector is not usable for code because you could only fit ~2-3
instructions there before needing another jump and that would complicate
things a lot. So anything from 0xfffffff3 onwards (0xfffffff5 onwards if
you consider the binutils workaround) is fair game for a signature or
any other helpful construct.
The LAR utility stores the 32-bit length of the archive at 0xfffffff4.
That means the space 0xfffffff8-0xffffffff is up for grabs.

We could use the top 8 bytes for the following signature:
0xfffffff8-0xfffffffb: String (not NULL terminated) 'cb30'
0xfffffffc-0xffffffff: Relative location/pointer to a to-be-designed struct

This has the advantage of separating the information storage format from
locating the information. If the string is 'cb30', follow the pointer
and try to understand the storage format. If you can't decipher the
storage format, you know that it is a coreboot image with an
unsupported/unknown information storage format and you can tell the user
to upgrade flashrom or whatever tool he/she is using to work on that image.
We could even use the pointer to point to existing image information in
v2 (which is currently searched for with exceessively ugly heuristics)
and point to a LAR entry in v3 as needed.

Thoughts? Comments?
The v3 patch below illustrates the idea, but it does not yet fill in the
pointer.

Index: arch/x86/stage0_common.S
===================================================================
--- arch/x86/stage0_common.S	(Revision 1065)
+++ arch/x86/stage0_common.S	(Arbeitskopie)
@@ -156,10 +156,12 @@
 	 * instead of the weird 16 bit relocations that binutils does not
 	 * handle consistenly between versions because they are used so rarely.
 	 */
-.byte	0
+	/* 3 filler bytes to have the signature at 0xfffff8. */
+.byte	0,0,0
 
-/* Date? ID string? We might want to put something else in here. */
-.ascii DATE
+/* Signature together with a pointer to a struct with more information. */
+.ascii "cb30"
+.long 0
 
 /* Checksum. */
 /* .word 0 */


Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/




From jordan at cosmicpenguin.net  Sun Dec  7 02:20:23 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Sat, 06 Dec 2008 18:20:23 -0700
Subject: [coreboot] [RFC] coreboot image marker
In-Reply-To: <493B1F32.3080208@gmx.net>
References: <493B1F32.3080208@gmx.net>
Message-ID: <493B24D7.8000700@cosmicpenguin.net>

Carl-Daniel Hailfinger wrote:
> I'd like to introduce a reasonably safe way to detect whether an image
> is a coreboot image.
> 
> Goals:
> - Easy to implement
> - Good for visual inspection of a image file with hexdump
> - Fixed location to make detection easy
> - Independence of the format of the image data
> - Reusable even if we decide to change the image data format completely
> 
> The existing solutions and approached do not fulfill all (or even any)
> of the goals above.
> 
> Proposal:
> Use the top 8 bytes of an image to store a short signature and a pointer
> to the real data. If the signature is 4 bytes and the pointer is 4
> bytes, they fit exactly into the range 0xfffffff8-0xffffffff.
> The reset vector lives at 0xfffffff0 and it is a jump instruction with
> immediate operand. The instruction is 1 byte, the operand is 2 bytes
> (well, 4 bytes in reality due to binutils workarounds, but as the code
> is 16bit, only the first two bytes are evaluated). The space after the
> reset vector is not usable for code because you could only fit ~2-3
> instructions there before needing another jump and that would complicate
> things a lot. So anything from 0xfffffff3 onwards (0xfffffff5 onwards if
> you consider the binutils workaround) is fair game for a signature or
> any other helpful construct.
> The LAR utility stores the 32-bit length of the archive at 0xfffffff4.
> That means the space 0xfffffff8-0xffffffff is up for grabs.
> 
> We could use the top 8 bytes for the following signature:
> 0xfffffff8-0xfffffffb: String (not NULL terminated) 'cb30'
> 0xfffffffc-0xffffffff: Relative location/pointer to a to-be-designed struct
> 
> This has the advantage of separating the information storage format from
> locating the information. If the string is 'cb30', follow the pointer
> and try to understand the storage format. If you can't decipher the
> storage format, you know that it is a coreboot image with an
> unsupported/unknown information storage format and you can tell the user
> to upgrade flashrom or whatever tool he/she is using to work on that image.
> We could even use the pointer to point to existing image information in
> v2 (which is currently searched for with exceessively ugly heuristics)
> and point to a LAR entry in v3 as needed.
> 
> Thoughts? Comments?

If you do this, then you can get rid of the length at 0xfffffff4 and put 
the pointer there.  All the ROM information should be contained in one 
place.  The pointer should point to a master information header, 
including, but not limited to:

Magic
ROM size
block alignment
start of the LAR data in the ROM (it might not always be at 0)

In addition, the structure could contain things like:

Date/time the ROM was created
Description (e.g. "CBV3+coreinfo")
Target architecture information
Flashrom identifiers, etc, etc.

I think its fine to have one header to rule them all - LAR information 
can probably coexist with the other stuff, even if it is unused in v2. 
if it is a concern, you can probably turn the master header into a list 
of lists (e.g - magic, pointer to coreboot header, pointer to LAR 
header) but I think thats probably needs more real estate then we want 
to spend.

LAR desperately needs this - a master header would solve problems in 
multiple fields at once.

Jordan



From peter at stuge.se  Sun Dec  7 03:42:00 2008
From: peter at stuge.se (Peter Stuge)
Date: Sun, 7 Dec 2008 03:42:00 +0100
Subject: [coreboot] [RFC] coreboot image marker
In-Reply-To: <493B24D7.8000700@cosmicpenguin.net>
References: <493B1F32.3080208@gmx.net> <493B24D7.8000700@cosmicpenguin.net>
Message-ID: <20081207024200.21130.qmail@stuge.se>

Jordan Crouse wrote:
> LAR desperately needs this - a master header would solve problems
> in multiple fields at once.

It goes directly against one original design goal of lar that I
consider to be essential (the larball is a series of independent
files) and I do not understand all the benefits.

This lar feature comes from the desire to support the use case of
replacing single files in the lar in flash without any modifications
being needed in any other part of the flash chip.

One way to preserve that goal while still providing the information
you desire would be to store any master header in a separate file in
the lar.

I think it is important to keep the non-structure of larballs.


//Peter



From joe at settoplinux.org  Sun Dec  7 06:52:06 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sun, 07 Dec 2008 00:52:06 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <493AFD7A.4070007@coresystems.de>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<493AFD7A.4070007@coresystems.de>
Message-ID: <3a19b80eb0f70ee6c39f7073d1347515@imap.1and1.com>




On Sat, 06 Dec 2008 23:32:26 +0100, Stefan Reinauer <stepan at coresystems.de>
wrote:
> Joseph Smith wrote:
>> Hello,
>> For the Paraflasher project I would like to setup a function to
>> automatically detect the presence of the PC's parallel ports and their
> base
>> addresses. This way it doesn't need to be hard-coded into the program. I
>> was thinking of using /proc/ioports to do this but I am not really sure
> how
>> to do this in C. Here is what I am thinking:
>>
>> 1. First use grep -c paraport /proc/ioports to check if we have multiple
>> parallel ports and maybe setup loop for it.
>> 2. Then grep paraport /proc/ioports again to get the base address of
> each
>> parallel port detected. This is where I am stuck. I just need to turn
> the
>> first 4 characters (base address) into a variable. Can anyone help???
>>   
Hmm after some research it looks like for every parallel port Linux (kernel
2.4 and up) detects it creates /proc/sys/dev/parport/parport* (0,1,2,3, and
so on) directory. Within this directory there is a base-addr file.

cat /proc/sys/dev/parport/parport0/base-addr 
888 1912
Then turn the first number into hex (888 => 0x378) 

Wala, we have our base address :-)

So, For multi ports I think I just need a shell command that will count how
many parport* directories found in /proc/sys/dev/parport/, any ideas?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From rminnich at gmail.com  Sun Dec  7 07:53:04 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Dec 2008 22:53:04 -0800
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <3a19b80eb0f70ee6c39f7073d1347515@imap.1and1.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<493AFD7A.4070007@coresystems.de>
	<3a19b80eb0f70ee6c39f7073d1347515@imap.1and1.com>
Message-ID: <13426df10812062253r6ef08ecdxe19923fce0137d7d@mail.gmail.com>

On Sat, Dec 6, 2008 at 9:52 PM, Joseph Smith <joe at settoplinux.org> wrote:

> cat /proc/sys/dev/parport/parport0/base-addr
> 888 1912
> Then turn the first number into hex (888 => 0x378)

boy do I feel dumb! I forgot entirely about that.

But why not use Stefan's idea of /dev/parportX?

Why do all this other work?

ron



From r.marek at assembler.cz  Sun Dec  7 09:33:07 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Dec 2008 09:33:07 +0100
Subject: [coreboot] [RFC] coreboot image marker
In-Reply-To: <493B1F32.3080208@gmx.net>
References: <493B1F32.3080208@gmx.net>
Message-ID: <493B8A43.30900@assembler.cz>

Hi,

Just a note. At the end of the flash, there is info for ROM bootstraps. VIA has 
it as a pointer on 0xffffffd0 (IIRC). nVidia & SiS has something too.

Rudolf



From c-d.hailfinger.devel.2006 at gmx.net  Sun Dec  7 12:24:20 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Dec 2008 12:24:20 +0100
Subject: [coreboot] [RFC] coreboot image marker
In-Reply-To: <493B8A43.30900@assembler.cz>
References: <493B1F32.3080208@gmx.net> <493B8A43.30900@assembler.cz>
Message-ID: <493BB264.7000602@gmx.net>

On 07.12.2008 09:33, Rudolf Marek wrote:
> Hi,
>
> Just a note. At the end of the flash, there is info for ROM
> bootstraps. VIA has it as a pointer on 0xffffffd0 (IIRC). nVidia & SiS
> has something too.

Yes, and that ROM bootstrap info location varies. It is always in the
top 256 bytes, but never in the top 16 bytes. That's why I explicitly
chose the top 8 bytes.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sun Dec  7 12:38:57 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Dec 2008 12:38:57 +0100
Subject: [coreboot] [RFC] coreboot image marker
In-Reply-To: <20081207024200.21130.qmail@stuge.se>
References: <493B1F32.3080208@gmx.net> <493B24D7.8000700@cosmicpenguin.net>
	<20081207024200.21130.qmail@stuge.se>
Message-ID: <493BB5D1.4010303@gmx.net>

On 07.12.2008 03:42, Peter Stuge wrote:
> Jordan Crouse wrote:
>   
>> LAR desperately needs this - a master header would solve problems
>> in multiple fields at once.
>>     
>
> It goes directly against one original design goal of lar that I
> consider to be essential (the larball is a series of independent
> files) and I do not understand all the benefits.
>
> This lar feature comes from the desire to support the use case of
> replacing single files in the lar in flash without any modifications
> being needed in any other part of the flash chip.
>
> One way to preserve that goal while still providing the information
> you desire would be to store any master header in a separate file in
> the lar.
>   

Storing the LAR size in the boot block is irrelevant for the LAR
utility, but absolutely essential for booting. There's no other way to
find out where to start scanning for LAR members. (In theory, we could
start scanning at 4G-16M, but I doubt anybody wants to wait for up to 16
million accesses before the first LAR member is found.
By the way, for future boards (especially GA-M57SLI) in v3 we will need
another header field: Mappable size. It is pointless to scan memory
where a chip is not mapped even if the chip would theoretically occupy
that area.


> I think it is important to keep the non-structure of larballs.
>   

As long as the boot process can easily determine all the info it needs,
that is OK with me.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From r.marek at assembler.cz  Sun Dec  7 15:53:45 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Dec 2008 15:53:45 +0100
Subject: [coreboot] fix VT8237S/K8M890 powernow
In-Reply-To: <13426df10812061630j72f0f067g5e1f4e6ae8fced4b@mail.gmail.com>
References: <49386600.5080300@assembler.cz>	<20081204232922.8525.qmail@stuge.se>
	<13426df10812061630j72f0f067g5e1f4e6ae8fced4b@mail.gmail.com>
Message-ID: <493BE379.2000503@assembler.cz>

Hi,

Sorry I forgot to write it here.  Changeset 3795 and 3796.

Thanks,
Rudolf



From joe at settoplinux.org  Sun Dec  7 16:10:02 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sun, 07 Dec 2008 10:10:02 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <13426df10812062253r6ef08ecdxe19923fce0137d7d@mail.gmail.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<493AFD7A.4070007@coresystems.de>
	<3a19b80eb0f70ee6c39f7073d1347515@imap.1and1.com>
	<13426df10812062253r6ef08ecdxe19923fce0137d7d@mail.gmail.com>
Message-ID: <3f6646be718a8bd846af40a91c3831e5@imap.1and1.com>




On Sat, 6 Dec 2008 22:53:04 -0800, "ron minnich" <rminnich at gmail.com>
wrote:
> On Sat, Dec 6, 2008 at 9:52 PM, Joseph Smith <joe at settoplinux.org> wrote:
> 
>> cat /proc/sys/dev/parport/parport0/base-addr
>> 888 1912
>> Then turn the first number into hex (888 => 0x378)
> 
> boy do I feel dumb! I forgot entirely about that.
> 
> But why not use Stefan's idea of /dev/parportX?
> 
> Why do all this other work?
> 

From jordan at cosmicpenguin.net  Sun Dec  7 17:11:29 2008
From: jordan at cosmicpenguin.net (Jordan Crouse)
Date: Sun, 07 Dec 2008 09:11:29 -0700
Subject: [coreboot] [RFC] coreboot image marker
In-Reply-To: <20081207024200.21130.qmail@stuge.se>
References: <493B1F32.3080208@gmx.net> <493B24D7.8000700@cosmicpenguin.net>
	<20081207024200.21130.qmail@stuge.se>
Message-ID: <493BF5B1.7050807@cosmicpenguin.net>

Peter Stuge wrote:
> Jordan Crouse wrote:
>> LAR desperately needs this - a master header would solve problems 
>> in multiple fields at once.
> 
> It goes directly against one original design goal of lar that I 
> consider to be essential (the larball is a series of independent 
> files) and I do not understand all the benefits.

That might have been the original goal, but its just simply not the case
in reality. Having to put the bootblock in a fixed position completely
destroys the theory of a pure archive. And Ron has requested that we be
able to support LAR components in fixed locations within the ROM, which
will further emphasis the need for a fully formed ROM from the word go.

And really, this isn't a bad thing - the logical output of the coreboot
build is a valid ROM (i.e - properly organized bits that can be directly
written to the hardware without further modification). LAR still plays
an important part here because both coreboot and the userland utilities
desperately need a filesystem like organization within the ROM.

> One way to preserve that goal while still providing the information 
> you desire would be to store any master header in a separate file in 
> the lar.

There are a number of problems with that approach - one, it doesn't work
with v2, which was an important feature of Carl-Daniel's design. Two, it
ends up wasting (eraseblock - sizeof(lar header file)) bytes on every ROM.
Thirdly, coreboot and the LAR utilities would still have to know the
size of the ROM and the location of the first LAR entry, so information
has to be written to the bootblock regardless. The bootblock is valuable
here because it is in a known fixed location, and both coreboot and the
LAR utility can easily communicate with one another through it.

> I think it is important to keep the non-structure of larballs.

Can you explain why in more detail? Do you have some examples?

Jordan



From klt29 at freemail.hu  Sun Dec  7 17:21:52 2008
From: klt29 at freemail.hu (Tamas Szabo)
Date: Sun, 07 Dec 2008 17:21:52 +0100
Subject: [coreboot] EPIA MII
In-Reply-To: <dd3c80060812050904x6954dbd2v121ada5ac3d09708@mail.gmail.com>
References: <49393CCB.1070306@freemail.hu>
	<dd3c80060812050904x6954dbd2v121ada5ac3d09708@mail.gmail.com>
Message-ID: <493BF820.4050502@freemail.hu>

Corey Osgood wrote:
> On Fri, Dec 5, 2008 at 9:38 AM, Tamas Szabo <klt29 at freemail.hu 
> <mailto:klt29 at freemail.hu>> wrote:
> 
>     Hello,
> 
>     Can someone point to a guide which helps me how to make my EPIA
>     working with the latest coreboot and filo?
> 
>     Thx,
> 
>     /sza2
> 
> 
> Hi,
> 
> I'll try to update the wiki page tonight or this weekend.
> 
> -Corey
> 

It would be great!
Thanks in advance,

/sza2



From joe at settoplinux.org  Sun Dec  7 18:40:09 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sun, 07 Dec 2008 12:40:09 -0500
Subject: [coreboot] Dynamic detection of Parallel Port
In-Reply-To: <13426df10812062253r6ef08ecdxe19923fce0137d7d@mail.gmail.com>
References: <4cabae301989f7b168cdc7fcff36fdf1@imap.1and1.com>
	<493AFD7A.4070007@coresystems.de>
	<3a19b80eb0f70ee6c39f7073d1347515@imap.1and1.com>
	<13426df10812062253r6ef08ecdxe19923fce0137d7d@mail.gmail.com>
Message-ID: <16b9478695e745259a4f7c514c3fca24@imap.1and1.com>




On Sat, 6 Dec 2008 22:53:04 -0800, "ron minnich" <rminnich at gmail.com>
wrote:
> On Sat, Dec 6, 2008 at 9:52 PM, Joseph Smith <joe at settoplinux.org> wrote:
> 
>> cat /proc/sys/dev/parport/parport0/base-addr
>> 888 1912
>> Then turn the first number into hex (888 => 0x378)
> 
> boy do I feel dumb! I forgot entirely about that.
> 
> But why not use Stefan's idea of /dev/parportX?
> 
> Why do all this other work?
> 

From fengyuning1984 at gmail.com  Sun Dec  7 19:03:41 2008
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Mon, 8 Dec 2008 02:03:41 +0800
Subject: [coreboot] [PATCH] flashrom: generates OPCODES from the locked
	chipset
Message-ID: <a505dc9d0812071003q401f3c0cn7f15288988c67d87@mail.gmail.com>

Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI
configuration is locked down.

Signed-off-by: FENG yu ning <fengyuning1984 at gmail.com>

Index: flashrom/flash.h
===================================================================
--- flashrom/flash.h	(revision 3803)
+++ flashrom/flash.h	(working copy)
@@ -51,6 +51,12 @@

 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

+/* for pairing opcodes with their required preop */
+struct preop_opcode_pair {
+	uint8_t preop;
+	uint8_t opcode;
+};
+
 struct flashchip {
 	const char *vendor;
 	const char *name;
@@ -76,6 +82,8 @@
 	int (*write) (struct flashchip *flash, uint8_t *buf);
 	int (*read) (struct flashchip *flash, uint8_t *buf);

+	struct preop_opcode_pair *preop_opcode_pairs;
+
 	/* Some flash devices have an additional register space. */
 	volatile uint8_t *virtual_memory;
 	volatile uint8_t *virtual_registers;
Index: flashrom/chipset_enable.c
===================================================================
--- flashrom/chipset_enable.c	(revision 3803)
+++ flashrom/chipset_enable.c	(working copy)
@@ -47,6 +47,8 @@
 flashbus_t flashbus = BUS_TYPE_LPC;
 void *spibar = NULL;

+extern int ichspi_lock;
+
 static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
@@ -335,6 +337,7 @@
 		printf_debug("\n");
 		if ((*(uint16_t *) spibar) & (1 << 15)) {
 			printf("WARNING: SPI Configuration Lockdown activated.\n");
+			ichspi_lock = 1;
 		}
 		break;
 	case BUS_TYPE_ICH9_SPI:
Index: flashrom/ichspi.c
===================================================================
--- flashrom/ichspi.c	(revision 3803)
+++ flashrom/ichspi.c	(working copy)
@@ -101,6 +101,9 @@
 #define ICH7_REG_OPTYPE                0x56	/* 16 Bits */
 #define ICH7_REG_OPMENU                0x58	/* 64 Bits */

+/* ICH SPI configuration lock-down. May be set during chipset enabling. */
+int ichspi_lock = 0;
+
 typedef struct _OPCODE {
 	uint8_t opcode;		//This commands spi opcode
 	uint8_t spi_type;	//This commands spi type
@@ -147,7 +150,11 @@
 #define REGWRITE8(X,Y)  (*(uint8_t *)((uint8_t *)spibar+X)=Y)

 /* Common SPI functions */
+static inline int find_opcode(OPCODES *op, uint8_t opcode);
+static inline int find_preop(OPCODES *op, uint8_t preop);
+static int generate_opcodes(struct flashchip * flash, OPCODES * op);
 static int program_opcodes(OPCODES * op);
+int ich_check_opcodes(struct flashchip * flash);
 static int run_opcode(OPCODE op, uint32_t offset,
 		      uint8_t datalength, uint8_t * data);
 static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
@@ -171,6 +178,98 @@
 	 }
 };

+OPCODES O_EXISTING = {};
+
+static inline int find_opcode(OPCODES *op, uint8_t opcode)
+{
+	int a;
+
+	for (a = 0; a < 8; a++) {
+		if (op->opcode[a].opcode == opcode)
+			return a;
+	}
+
+	return -1;
+}
+
+static inline int find_preop(OPCODES *op, uint8_t preop)
+{
+	int a;
+
+	for (a = 0; a < 2; a++) {
+		if (op->preop[a] == preop)
+			return a;
+	}
+
+	return -1;
+}
+
+static int generate_opcodes(struct flashchip * flash, OPCODES * op)
+{
+  int a, b, i;
+	uint16_t preop, optype;
+	uint32_t opmenu[2];
+	struct preop_opcode_pair *pair;
+
+	if (op == NULL) {
+		printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__);
+		return -1;
+	}
+
+	switch (flashbus) {
+	case BUS_TYPE_ICH7_SPI:
+	case BUS_TYPE_VIA_SPI:
+		preop = REGREAD16(ICH7_REG_PREOP);
+		optype = REGREAD16(ICH7_REG_OPTYPE);
+		opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
+		opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
+		break;
+	case BUS_TYPE_ICH9_SPI:
+		preop = REGREAD16(ICH9_REG_PREOP);
+		optype = REGREAD16(ICH9_REG_OPTYPE);
+		opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
+		opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
+		break;
+	default:
+		printf_debug("%s: unsupported chipset\n", __FUNCTION__);
+		return -1;
+	}
+
+	op->preop[0] = (uint8_t) preop;
+	op->preop[1] = (uint8_t) (preop >> 8);
+
+	for (a = 0; a < 8; a++) {
+		op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
+		optype >>= 2;
+	}
+
+	for (a = 0; a < 4; a++) {
+		op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
+		opmenu[0] >>= 8;
+	}
+
+	for (a = 4; a < 8; a++) {
+		op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
+		opmenu[1] >>= 8;
+	}
+
+	/* atomic (link opcode with required pre-op) */
+	for (a = 4; a < 8; a++)
+		op->opcode[a].atomic = 0;
+
+	pair = flash->preop_opcode_pairs;
+	if (pair) {
+		for (i = 0; pair[i].opcode; i++) {
+			a = find_opcode(op, pair[i].opcode);
+			b = find_preop(op, pair[i].preop);
+			if ((a != -1) && (b != -1))
+				op->opcode[a].atomic = (uint8_t) ++b;
+		}
+	}
+
+	return 0;
+}
+
 int program_opcodes(OPCODES * op)
 {
 	uint8_t a;
@@ -224,6 +323,41 @@
 	return 0;
 }

+/* This function generates OPCODES from or programs OPCODES to the chipset
+ * according to its SPI configuration lock.
+ *
+ * It should be called in the ICH7/ICH9/VIA part of each operation driver(i.e.
+ * probe, read, erase, write, etc.) before any command is sent.
+ */
+int ich_check_opcodes(struct flashchip * flash)
+{
+	int rc = 0;
+	OPCODES *curopcodes_done;
+
+	if (curopcodes)
+		return 0;
+
+	if (ichspi_lock) {
+		printf_debug("Generating OPCODES... ");
+		curopcodes_done = &O_EXISTING;
+		rc = generate_opcodes(flash, curopcodes_done);
+	} else {
+		printf_debug("Programming OPCODES... ");
+		curopcodes_done = &O_ST_M25P;
+		rc = program_opcodes(curopcodes_done);
+	}
+
+	if (rc) {
+		curopcodes = NULL;
+		printf_debug("failed\n");
+		return 1;
+	} else {
+		curopcodes = curopcodes_done;
+		printf_debug("done\n");
+		return 0;
+	}
+}
+
 static int ich7_run_opcode(OPCODE op, uint32_t offset,
 			   uint8_t datalength, uint8_t * data, int maxdata)
 {
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From fengyuning1984 at gmail.com  Sun Dec  7 19:29:57 2008
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Mon, 8 Dec 2008 02:29:57 +0800
Subject: [coreboot] testing patch and output
Message-ID: <a505dc9d0812071029u7770b1cucb80407e623998c1@mail.gmail.com>

Testing Output:

Calibrating delay loop... 686M loops per second, 100 myus = 184 us. OK.
No coreboot table found.
Found chipset "Intel ICH7/ICH7R", enabling flash write...
BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
tried to set 0xdc to 0x3 on Intel ICH7/ICH7R failed (WARNING ONLY)

Root Complex Register Block address = 0xfed1c000
GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
Top Swap : not enabled
SPIBAR = 0xfed1c000 + 0x3020
0x00: 0x8004     (SPIS)
0x02: 0x4030     (SPIC)
0x04: 0x00000000 (SPIA)
0x08: 0x0000000e (SPID0)
0x0c: 0x00000000 (SPID0+4)
0x10: 0x00000000 (SPID1)
0x14: 0x00000000 (SPID1+4)
0x18: 0x00000000 (SPID2)
0x1c: 0x00000000 (SPID2+4)
0x20: 0x00000000 (SPID3)
0x24: 0x00000000 (SPID3+4)
0x28: 0x00000000 (SPID4)
0x2c: 0x00000000 (SPID4+4)
0x30: 0x00000000 (SPID5)
0x34: 0x00000000 (SPID5+4)
0x38: 0x00000000 (SPID6)
0x3c: 0x00000000 (SPID6+4)
0x40: 0x00000000 (SPID7)
0x44: 0x00000000 (SPID7+4)
0x50: 0x00f80000 (BBAR)
0x54: 0x5006     (PREOP)
0x56: 0x123b     (OPTYPE)
0x58: 0x05200302 (OPMENU)
0x5c: 0x000100ab (OPMENU+4)
0x60: 0x00000000 (PBR0)
0x64: 0x00000000 (PBR1)
0x68: 0x00000000 (PBR2)
0x6c: 0x00000000 (PBR3)

WARNING: SPI Configuration Lockdown activated.
SPI Read Configuration: prefetching disabled, caching enabled, FAILED!
Probing for SST SST25LF040A, 512 KB: Generating OPCODES... done
SPIC before going: 0x4140
test_sst25lf040a: id1 0xbf, id2 0x44.
SPIC before going: 0x4030
SPIC before going: 0x406c
Transaction error!
run OPCODE 0x01 failed
SPIC before going: 0x4030
status register: old value = 0x0e, new value = 0x0e.
test_sst25lf040a: *** TEST FAILED! ***
Found chip "SST SST25LF040A" (512 KB) at physical address 0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom at coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
No operations were specified.


--------------------------------------------------------------------------------

Comment on the above output:

  Despite the "TEST FAILED!" warning, the testing is actually successful, for -

  1. The command '0x01'(WRSR) is executed. It is in the existing
     opmenu(see 0x5c in the well formatted ICH SPI registers) but not
     in the hardcoded O_ST_M25P.

  2. The control register for the ready-to-go WRSR command is
     assembled correctly with the atomic bit and the index of its
     required preop EWSR set. See the 2nd "SPIC before going".

  The flash chip is probed at 0xfff80000, because the vendor BIOS has
  put the flash chip at the top of the 24-bit address space.

--------------------------------------------------------------------------------

diff -uN flashrom/flashchips.c flashrom_test/flashchips.c
--- flashrom/flashchips.c	2008-12-08 01:30:19.000000000 +0800
+++ flashrom_test/flashchips.c	2008-12-08 01:24:20.000000000 +0800
@@ -21,6 +21,9 @@
  */

 #include "flash.h"
+#include "spi.h"
+
+struct preop_opcode_pair pop_sst25lf040a[];

 /**
  * List of supported flash ROM chips.
@@ -107,6 +110,7 @@
 	{"PMC",		"Pm49FL004",		PMC_ID_NOPREFIX,PMC_49FL004,		512,	64 *
1024,	TEST_OK_PREW,	probe_49fl00x,		erase_49fl00x,		write_49fl00x},
 	{"Sharp",	"LHF00L04",		SHARP_ID,	SHARP_LHF00L04,		1024,	64 *
1024,	TEST_UNTESTED,	probe_lhf00l04,		erase_lhf00l04,			write_lhf00l04},
 	{"Spansion",	"S25FL016A",		SPANSION_ID,	SPANSION_S25FL016A,	2048,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
+	{"SST",		"SST25LF040A",		SST_ID,		SST_25LF040A_REMS,	512,	256,		TEST_UNTESTED,	test_sst25lf040a,	NULL,			NULL,		NULL,		pop_sst25lf040a},
 	{"SST",		"SST25VF016B",		SST_ID,		SST_25VF016B,		2048,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
 	{"SST",		"SST25VF032B",		SST_ID,		SST_25VF032B,		4096,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
 	{"SST",		"SST25VF040B",		SST_ID,		SST_25VF040B,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
@@ -193,3 +197,13 @@

 	{NULL,}
 };
+
+struct preop_opcode_pair pop_sst25lf040a[] = {
+	{JEDEC_WREN, JEDEC_BYTE_PROGRAM},
+	{JEDEC_WREN, 0xaf}, /* AAI */
+	{JEDEC_WREN, 0x20}, /* sector erase */
+	{JEDEC_WREN, 0x52}, /* block erase */
+	{JEDEC_WREN, 0x60}, /* chip erase */
+	{JEDEC_EWSR, JEDEC_WRSR},
+	{0,}
+};
diff -uN flashrom/flash.h flashrom_test/flash.h
--- flashrom/flash.h	2008-12-08 01:45:24.000000000 +0800
+++ flashrom_test/flash.h	2008-12-08 01:24:20.000000000 +0800
@@ -294,6 +294,7 @@
  * byte of device ID is related to log(bitsize) at least for some chips.
  */
 #define SST_ID			0xBF	/* SST */
+#define SST_25LF040A_REMS	0x44	/* REMS or RES opcode */
 #define SST_25WF512		0x2501
 #define SST_25WF010		0x2502
 #define SST_25WF020		0x2503
@@ -577,6 +578,9 @@
 void data_polling_lhf00l04(volatile uint8_t *dst, uint8_t data);
 void protect_lhf00l04(volatile uint8_t *bios);

+/* sst25lf040a.c */
+int test_sst25lf040a(struct flashchip *flash);
+
 /* sst28sf040.c */
 int probe_28sf040(struct flashchip *flash);
 int erase_28sf040(struct flashchip *flash);
diff -uN flashrom/ichspi.c flashrom_test/ichspi.c
--- flashrom/ichspi.c	2008-12-08 01:24:48.000000000 +0800
+++ flashrom_test/ichspi.c	2008-12-08 01:24:20.000000000 +0800
@@ -441,6 +441,9 @@
 		}
 	}

+	/* DELETE ME! */
+	printf_debug("SPIC before going: 0x%04x\n", temp16);
+
 	/* Start */
 	temp16 |= SPIC_SCGO;

diff -uN flashrom/Makefile flashrom_test/Makefile
--- flashrom/Makefile	2008-12-08 01:30:19.000000000 +0800
+++ flashrom_test/Makefile	2008-12-08 01:24:20.000000000 +0800
@@ -29,7 +29,7 @@
 	w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \
 	sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \
 	flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \
-	ichspi.o w39v040c.o sb600spi.o
+	ichspi.o w39v040c.o sb600spi.o sst25lf040a.o

 all: pciutils dep $(PROGRAM)

diff -uN flashrom/sst25lf040a.c flashrom_test/sst25lf040a.c
--- flashrom/sst25lf040a.c	1970-01-01 08:00:00.000000000 +0800
+++ flashrom_test/sst25lf040a.c	2008-12-08 01:12:47.000000000 +0800
@@ -0,0 +1,56 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "flash.h"
+#include "spi.h"
+
+int ich_check_opcodes(struct flashchip *flash);
+
+int test_sst25lf040a(struct flashchip *flash)
+{
+	uint8_t readarr[2];
+	const uint8_t cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0xf8, 0, 0 };
+	const uint8_t cmd_rdsr[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR};
+	const uint8_t cmd_wrsr[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR};
+
+	switch (flashbus) {
+	case BUS_TYPE_ICH7_SPI:
+	case BUS_TYPE_ICH9_SPI:
+	case BUS_TYPE_VIA_SPI:
+
+		ich_check_opcodes(flash); /* example usage of ich_check_opcodes */
+
+		if (spi_command(sizeof(cmd), 2, cmd, readarr))
+			return 0;
+
+		printf_debug("%s: id1 0x%x, id2 0x%x.\n", __FUNCTION__, readarr[0],
+			     readarr[1]);
+
+		if (readarr[0] != flash->manufacture_id
+		    || readarr[1] != flash->model_id)
+			return 0;
+
+		/* read current status register */
+		spi_command(sizeof(cmd_rdsr), 1, cmd_rdsr, readarr);
+
+		/* try to change the status register */
+		readarr[1] = readarr[0] ^ 0x80; /* BPL - block protection lock-down */
+		spi_command(sizeof(cmd_wrsr), 1, cmd_wrsr, readarr + 1);
+
+		/* read again */
+		spi_command(sizeof(cmd_rdsr), 1, cmd_rdsr, readarr + 1);
+
+		printf_debug("status register: old value = 0x%02x, new value =
0x%02x.\n", readarr[0], readarr[1]);
+
+		printf_debug("%s: *** TEST ", __FUNCTION__);
+		if (readarr[0] == readarr[1])
+			printf_debug("FAILED! ")
+		else
+			printf_debug("PASSED! ");
+		printf_debug("***\n");
+
+		return 1;
+
+	default:
+		return 0;
+	}
+}
Common subdirectories: flashrom/.svn and flashrom_test/.svn
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From fengyuning1984 at gmail.com  Sun Dec  7 19:34:09 2008
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Mon, 8 Dec 2008 02:34:09 +0800
Subject: [coreboot] testing patch and output
In-Reply-To: <a505dc9d0812071029u7770b1cucb80407e623998c1@mail.gmail.com>
References: <a505dc9d0812071029u7770b1cucb80407e623998c1@mail.gmail.com>
Message-ID: <a505dc9d0812071034k793a1571r95e72e5876c46c1@mail.gmail.com>

On Mon, Dec 8, 2008 at 2:29 AM, FENG Yu Ning <fengyuning1984 at gmail.com> wrote:
> Comment on the above output:
>
>  Despite the "TEST FAILED!" warning, the testing is actually successful, for -
>
>  1. The command '0x01'(WRSR) is executed. It is in the existing
>     opmenu(see 0x5c in the well formatted ICH SPI registers) but not
>     in the hardcoded O_ST_M25P.
>
>  2. The control register for the ready-to-go WRSR command is
>     assembled correctly with the atomic bit and the index of its
>     required preop EWSR set. See the 2nd "SPIC before going".

Should be the 3rd one(0x406c).



From peka at min-epost.net  Sun Dec  7 20:23:39 2008
From: peka at min-epost.net (pk)
Date: Sun, 07 Dec 2008 20:23:39 +0100
Subject: [coreboot] Interesting (part of) article.
Message-ID: <493C22BB.7040402@min-epost.net>

Hi,

Don't know if this is of any interest but I think the first part ("BIOS
Ridiculousness...") relates somewhat of what you are trying to
accomplish here. There really should be more interest from motherboard
manufacturers in coreboot than there are...

http://anandtech.com/mb/showdoc.aspx?i=3471

Best regards

Peter Karlsson



From c-d.hailfinger.devel.2006 at gmx.net  Sun Dec  7 23:02:03 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Dec 2008 23:02:03 +0100
Subject: [coreboot] Interesting (part of) article.
In-Reply-To: <493C22BB.7040402@min-epost.net>
References: <493C22BB.7040402@min-epost.net>
Message-ID: <493C47DB.2060808@gmx.net>

Hi Peter,

thanks for the heads-up.

Ron, do you want to write to Anandtech to tell them about coreboot?

Regards,
Carl-Daniel

On 07.12.2008 20:23, pk wrote:
> Hi,
>
> Don't know if this is of any interest but I think the first part ("BIOS
> Ridiculousness...") relates somewhat of what you are trying to
> accomplish here. There really should be more interest from motherboard
> manufacturers in coreboot than there are...
>
> http://anandtech.com/mb/showdoc.aspx?i=3471
>
> Best regards
>
> Peter Karlsson
>   



From svn at coreboot.org  Mon Dec  8 00:41:16 2008
From: svn at coreboot.org (coreboot)
Date: Sun, 07 Dec 2008 23:41:16 -0000
Subject: [coreboot] #103: flashrom: Don't exit() after successful erase;
 enable testing all operations in one invocation
In-Reply-To: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
References: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
Message-ID: <050.42b77ebaff9b81f1c9744cfe6b29357c@coreboot.org>

#103: flashrom: Don't exit() after successful erase; enable testing all
operations in one invocation
----------------------------------+-----------------------------------------
   Reporter:  stuge               |          Owner:  stuge        
       Type:  enhancement         |         Status:  assigned     
   Priority:  major               |      Milestone:  flashrom v1.0
  Component:  flashrom            |        Version:               
   Keywords:  erase exit testing  |   Dependencies:  #117         
Patchstatus:  patch needs review  |  
----------------------------------+-----------------------------------------

Comment(by hailfinger):

 Moving read before erase as a single simple patch is

 Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

 That leaves us with another question: Should -Erwv or any other read/write
 combinations be allowed? I think the semantics of read+write are totally
 unclear. If you perform read, erase, write, verify (in that order) it
 means that you just rewrite ROM contents. That may or may not be desired,
 but it sure would work for testing read/write/erase operations.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:8>
coreboot <http://www.coreboot.org/>


From c-d.hailfinger.devel.2006 at gmx.net  Mon Dec  8 00:44:47 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 08 Dec 2008 00:44:47 +0100
Subject: [coreboot] Spi flash
In-Reply-To: <6ad6bfe40812011003w5af1bb7asa637f8cb5ac7211b@mail.gmail.com>
References: <6ad6bfe40811130011pfd4a11bxfa548bb4a879a420@mail.gmail.com>	
	<491C36CE.80206@gmx.net>	
	<6ad6bfe40811130951g13e051dfud3b330667c43d5e9@mail.gmail.com>	
	<491C7573.9080806@gmx.net>
	<6ad6bfe40812011003w5af1bb7asa637f8cb5ac7211b@mail.gmail.com>
Message-ID: <493C5FEF.5040500@gmx.net>

Hi Yves,

sorry for not getting back to you earlier. We are still working out the
best infrastructure to handle chips such as yours.

I hope to have something testable at the end of this week.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Mon Dec  8 03:18:20 2008
From: svn at coreboot.org (coreboot)
Date: Mon, 08 Dec 2008 02:18:20 -0000
Subject: [coreboot] #102: flashrom: coreboot ROM image file
 identification heuristic is broken
In-Reply-To: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
Message-ID: <050.222e3e32d367511c0423becd6153a967@coreboot.org>

#102: flashrom: coreboot ROM image file identification heuristic is broken
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge              
        Type:  defect    |        Status:  reopened           
    Priority:  major     |     Milestone:  flashrom v1.0      
   Component:  flashrom  |       Version:                     
  Resolution:            |      Keywords:  rom image heuristic
Dependencies:            |   Patchstatus:  there is no patch  
-------------------------+--------------------------------------------------
Changes (by stuge):

  * status:  closed => reopened
  * resolution:  fixed =>


Comment:

 I still think we should remove this check.

 One benefit of flashrom is that it permits hassle free crossflashing. I
 guess the crossflashing will often be factory BIOS images, in which case
 this check does not run. Only when the user booted coreboot and wants to
 flash another coreboot image will flashrom suddenly require -f to perform
 the requested operation.

 Please comment.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102#comment:16>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Mon Dec  8 03:23:33 2008
From: svn at coreboot.org (coreboot)
Date: Mon, 08 Dec 2008 02:23:33 -0000
Subject: [coreboot] #102: flashrom: coreboot ROM image file
 identification heuristic is broken
In-Reply-To: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
Message-ID: <050.af3924420ab15a3d2de5e9b479130da2@coreboot.org>

#102: flashrom: coreboot ROM image file identification heuristic is broken
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge              
        Type:  defect    |        Status:  new                
    Priority:  major     |     Milestone:  flashrom v1.0      
   Component:  flashrom  |       Version:                     
  Resolution:            |      Keywords:  rom image heuristic
Dependencies:            |   Patchstatus:  patch needs review 
-------------------------+--------------------------------------------------
Changes (by stuge):

  * status:  reopened => new
  * patchstatus:  there is no patch => patch needs review


-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102#comment:17>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Mon Dec  8 03:28:23 2008
From: svn at coreboot.org (coreboot)
Date: Mon, 08 Dec 2008 02:28:23 -0000
Subject: [coreboot] #102: flashrom: coreboot ROM image file
 identification heuristic is broken
In-Reply-To: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
Message-ID: <050.9ef6ad7602ce2dba362265a53d8dce23@coreboot.org>

#102: flashrom: coreboot ROM image file identification heuristic is broken
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge              
        Type:  defect    |        Status:  assigned           
    Priority:  major     |     Milestone:  flashrom v1.0      
   Component:  flashrom  |       Version:                     
  Resolution:            |      Keywords:  rom image heuristic
Dependencies:            |   Patchstatus:  patch needs review 
-------------------------+--------------------------------------------------
Changes (by stuge):

  * status:  new => assigned


-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102#comment:18>
coreboot <http://www.coreboot.org/>


From peter at stuge.se  Mon Dec  8 03:31:06 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 8 Dec 2008 03:31:06 +0100
Subject: [coreboot] #102: flashrom: coreboot ROM image file
	identification heuristic is broken
In-Reply-To: <050.af3924420ab15a3d2de5e9b479130da2@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
	<050.af3924420ab15a3d2de5e9b479130da2@coreboot.org>
Message-ID: <20081208023106.24049.qmail@stuge.se>

coreboot wrote:
>   * patchstatus:  there is no patch => patch needs review

Attached.


//Peter
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From svn at coreboot.org  Mon Dec  8 14:31:30 2008
From: svn at coreboot.org (coreboot)
Date: Mon, 08 Dec 2008 13:31:30 -0000
Subject: [coreboot] #103: flashrom: Don't exit() after successful erase;
 enable testing all operations in one invocation
In-Reply-To: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
References: <041.d6f003223df3afe9c38d44f78d70243d@coreboot.org>
Message-ID: <050.76604174b836ca8ee1fb578c83135792@coreboot.org>

#103: flashrom: Don't exit() after successful erase; enable testing all
operations in one invocation
----------------------------------+-----------------------------------------
   Reporter:  stuge               |          Owner:  stuge        
       Type:  enhancement         |         Status:  assigned     
   Priority:  major               |      Milestone:  flashrom v1.0
  Component:  flashrom            |        Version:               
   Keywords:  erase exit testing  |   Dependencies:  #117         
Patchstatus:  patch needs work    |  
----------------------------------+-----------------------------------------
Changes (by stepan):

  * patchstatus:  patch needs review => patch needs work


Comment:

 It also does not necessarily do the same thing with the hardware as
 calling the single functions. Strictly, a reboot between any of the tests
 would be the most reliable way of testing flashrom.

 Answering Peter's concerns, if we're going to add a method of "simplifying
 flashrom tests" that is a new feature, and it should get a new option.
 Using -Erwv for that ignores that fact by adding a lot of implicit
 assumptions. Implicit assumptions are fatal for any user interface.

 Strictly speaking, -wv should be disallowed, too. Instead, write should
 guarantee that the write succeeded, or print an error otherwise. As should
 an erase make sure that the chip is erased, if the program exists without
 error.

 Other than that, we should stick with the small utility approach, and have
 the tool do one thing at a time.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:9>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Mon Dec  8 14:35:47 2008
From: svn at coreboot.org (coreboot)
Date: Mon, 08 Dec 2008 13:35:47 -0000
Subject: [coreboot] #102: flashrom: coreboot ROM image file
 identification heuristic is broken
In-Reply-To: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
References: <041.d02ed69d3d641142e64c5b79feb8cb4e@coreboot.org>
Message-ID: <050.5906ef47133de08b2c8a4e946c3c27fb@coreboot.org>

#102: flashrom: coreboot ROM image file identification heuristic is broken
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge                   
        Type:  defect    |        Status:  closed                  
    Priority:  major     |     Milestone:  flashrom v1.0           
   Component:  flashrom  |       Version:                          
  Resolution:  fixed     |      Keywords:  rom image heuristic     
Dependencies:            |   Patchstatus:  patch has been committed
-------------------------+--------------------------------------------------
Changes (by stepan):

  * status:  assigned => closed
  * patchstatus:  patch needs review => patch has been committed
  * resolution:  => fixed


Comment:

 The check is fine. It should not be removed.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102#comment:19>
coreboot <http://www.coreboot.org/>


From c-d.hailfinger.devel.2006 at gmx.net  Mon Dec  8 18:15:36 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 08 Dec 2008 18:15:36 +0100
Subject: [coreboot] SB600 flashrom hang
Message-ID: <493D5638.70608@gmx.net>

Hi,

on my Asus M2A-VM, latest flashrom hangs while trying to access SB600 SPI.

flashrom -V
Calibrating delay loop... 365M loops per second, 100 myus = 83 us. OK.
No coreboot table found.
Found chipset "ATI(AMD) SB600", enabling flash write... SPI base address
is at 0x0
OK.
Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x0, id2 0x0,
id1 parity violation
Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x0, id2 0x0,
id1 parity violation
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x0, id2 0x0
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x0, id2 0x0
Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x0, id2 0x0, id1
parity violation
Probing for Atmel AT25DF021, 256 KB: sb600_spi_command, cmd=9f,
writecnt=0, readcnt=3

--------it hangs here---------------
The mainboard does not have a SPI chip.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Mon Dec  8 18:16:37 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 08 Dec 2008 18:16:37 +0100
Subject: [coreboot] superiotool on Asus M2A-VM
Message-ID: <493D5675.5040908@gmx.net>

# superiotool -de
superiotool r3784
Found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e
Register dump:
idx 20 21 22 23 24 2b
val 87 16 01 00 00 00
def 87 16 01 00 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1
val 00 00 00 00 04 00 80
def 00 03 f0 06 02 00 00
LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1 f2 f3
val 01 03 f8 04 00 50 00 7f
def 00 03 f8 04 00 50 00 7f
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1 f2 f3
val 00 00 00 00 00 50 00 7f
def 00 02 f8 03 00 50 00 7f
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 01 03 78 00 00 07 04 09
def 00 03 78 07 78 07 03 03
LDN 0x04 (Environment controller)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6
val 01 02 28 00 00 00 00 00  0a 00 8a 00 ff
def 00 02 90 02 30 09 00 00  00 00 00 NA NA
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 71 f0
val 01 00 60 00 64 01 02 68
def 01 00 60 00 64 01 02 00
LDN 0x06 (Mouse)
idx 30 70 71 f0
val 01 0c 02 00
def 00 0c 02 00
LDN 0x07 (GPIO)
idx 25 26 27 28 29 2a 2c 60  61 62 63 64 65 70 71 72  73 74 b0 b1 b2 b3
b4 b5  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c8 c9 ca cb cc  e0 e1 e2 e3 e4
f0 f1 f2  f3 f4 f5 f6 f7 f8 f9 fa  fb fc fd
val 40 0e 00 42 82 00 1f 00  00 02 20 00 00 00 01 00  38 00 40 0e 00 42
02 80  00 02 00 00 00 00 50 0e  00 42 02 50 0e 00 42 02  00 00 00 00 00
00 00 00  00 00 00 00 00 00 00 00  00 32 00
def 01 00 00 40 00 00 00 00  00 00 00 00 00 00 00 20  38 00 00 00 00 00
00 00  00 00 00 00 00 00 01 00  00 40 00 01 00 00 40 00  00 00 00 00 00
00 00 00  00 00 00 00 00 00 00 00  00 NA 00
LDN 0x08 (MIDI port)
idx 30 60 61 70 f0
val 00 03 00 0a 00
def 00 03 00 0a 00
LDN 0x09 (Game port)
idx 30 60 61
val 00 02 01
def 00 02 01
LDN 0x0a (Consumer IR)
idx 30 60 61 70 f0
val 00 03 10 0b 06
def 00 03 10 0b 00
Environment controller (0x022d)
Register dump:
idx 00 04 05 06 07 08 09 0b  0c 10 11 12 13 14 15 16  17 1b 1c 1d 30 31
32 33  34 35 36 37 38 39 3a 3b  3c 3d 3e 3f 40 41 42 43  44 45 48 50 51
52 53 54  56 57 59 5c 5d 5e 5f 60  61 62 63 64 65 68 69 6a  6b 6c 6d 70
71 72 73 74  75 84 85 86 87 88 89 8c  8d 8e 8f 90 91 92 93 94  95 98 99
9a 9b 9c 9d
val 11 00 00 00 00 00 80 09  17 d0 d0 ff 33 d7 80 81  82 00 00 ff ff ff
ff ff  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  ff ff 2d ff 31
7f 7f 7f  f3 00 00 00 00 00 00 00  32 7f 3c a0 00 00 32 7f  3c a0 00 7f
7f 7f 00 00  00 ff ff ff ff 00 00 02  00 99 99 7f 7f 7f 00 00  7f 7f 7f
7f 00 00 7f
def 18 00 00 00 00 00 80 09  00 NA NA NA 07 50 NA NA  NA NA NA NA NA NA
NA NA  NA NA NA NA NA NA NA NA  NA NA NA NA NA NA NA NA  NA NA RR 00 00
7f 7f 7f  00 00 00 00 00 00 00 7f  7f 7f 00 00 7f 7f 7f 7f  00 00 7f 7f
7f 7f 00 00  7f NA NA NA NA 00 00 02  00 99 99 7f 7f 7f 00 00  7f 7f 7f
7f 00 00 7f

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Mon Dec  8 19:00:17 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 08 Dec 2008 19:00:17 +0100
Subject: [coreboot] [PATCH] flashrom: flashchips.c cosmetic change
In-Reply-To: <a505dc9d0812010014k29c97afxe8c48a4990616242@mail.gmail.com>
References: <a505dc9d0812010014k29c97afxe8c48a4990616242@mail.gmail.com>
Message-ID: <493D60B1.6030707@coresystems.de>

FENG Yu Ning wrote:
> Breaks chip info into multiple lines.
>
> Patch excerpt:
>
>  struct flashchip flashchips[] = {
> -	/**********************************************************************************************************************************************************************************************************************/
> -	/* Vendor	Chip			Vendor ID	Chip ID		Total size (kB)	Page size
> (B)	Test status	Probe function		Erase function			Write function		Read
> function */
> -	/**********************************************************************************************************************************************************************************************************************/
> -	{"AMD",		"Am29F002(N)BB",	AMD_ID,		AM_29F002BB,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
> +
> +	/* Vendor, Chip, Vendor ID, Chip ID,
> +	 * Total size (kB), Page size (B),
> +	 * Test status,
> +	 * Probe function, Erase function, Write function, Read function
> +	 */
> +
> +	{"AMD", "Am29F002(N)BB", AMD_ID, AM_29F002BB,
> +	 256, 256,
> +	 TEST_UNTESTED,
> +	 probe_jedec, erase_chip_jedec, write_en29f002a
> +	},
> +
>
> Signed-off-by: FENG yu ning <fengyuning1984 at gmail.com>
>   

Wonderful!

Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From svn at coreboot.org  Mon Dec  8 19:15:10 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  8 Dec 2008 19:15:10 +0100
Subject: [coreboot] r3804 - trunk/util/flashrom
Message-ID: <mailman.2556.1355071450.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-12-08 19:15:10 +0100 (Mon, 08 Dec 2008)
New Revision: 3804

Modified:
   trunk/util/flashrom/flashchips.c
Log:
Breaks chip info into multiple lines.

Signed-off-by: FENG yu ning <fengyuning1984 at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/util/flashrom/flashchips.c
===================================================================
--- trunk/util/flashrom/flashchips.c	2008-12-06 01:37:09 UTC (rev 3803)
+++ trunk/util/flashrom/flashchips.c	2008-12-08 18:15:10 UTC (rev 3804)
@@ -29,167 +29,944 @@
  * the output of 'flashrom -L' is alphabetically sorted.
  */
 struct flashchip flashchips[] = {
-	/**********************************************************************************************************************************************************************************************************************/
-	/* Vendor	Chip			Vendor ID	Chip ID		Total size (kB)	Page size (B)	Test status	Probe function		Erase function			Write function		Read function */
-	/**********************************************************************************************************************************************************************************************************************/
-	{"AMD",		"Am29F002(N)BB",	AMD_ID,		AM_29F002BB,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
-	{"AMD",		"Am29F002(N)BT",	AMD_ID,		AM_29F002BT,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
-	{"AMD",		"Am29F016D",		AMD_ID,		AM_29F016D,		2048,	64 * 1024,	TEST_UNTESTED,	probe_29f040b,		erase_29f040b,			write_29f040b},
-	{"AMD",		"Am29F040B",		AMD_ID,		AM_29F040B,		512,	64 * 1024,	TEST_OK_PREW,	probe_29f040b,		erase_29f040b,			write_29f040b},
-	{"AMD",		"Am29LV040B",		AMD_ID,		AM_29LV040B,		512,	64 * 1024,	TEST_UNTESTED,	probe_29f040b,		erase_29f040b,			write_29f040b},
-	{"ASD",		"AE49F2008",		ASD_ID,		ASD_AE49F2008,		256,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Atmel",	"AT25DF021",		ATMEL_ID,	AT_25DF021,		256,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25DF041A",		ATMEL_ID,	AT_25DF041A,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25DF081",		ATMEL_ID,	AT_25DF081,		1024,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25DF161",		ATMEL_ID,	AT_25DF161,		2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25DF321",		ATMEL_ID,	AT_25DF321,		4096,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Atmel",	"AT25DF321A",		ATMEL_ID,	AT_25DF321A,		4096,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25DF641",		ATMEL_ID,	AT_25DF641,		8192,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25F512B",		ATMEL_ID,	AT_25F512B,		64,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25FS010",		ATMEL_ID,	AT_25FS010,		128,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT25FS040",		ATMEL_ID,	AT_25FS040,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT26DF041",		ATMEL_ID,	AT_26DF041,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,	NULL /* Incompatible Page write */,spi_chip_read},
-	{"Atmel",	"AT26DF081A",		ATMEL_ID,	AT_26DF081A,		1024,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT26DF161",		ATMEL_ID,	AT_26DF161,		2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
-	{"Atmel",	"AT26DF161A",		ATMEL_ID,	AT_26DF161A,		2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},
+
+	/* Vendor, Chip, Vendor ID, Chip ID,
+	 * Total size (kB), Page size (B),
+	 * Test status,
+	 * Probe function, Erase function, Write function, Read function
+	 */
+
+	{"AMD", "Am29F002(N)BB", AMD_ID, AM_29F002BB,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_en29f002a
+	},
+
+	{"AMD", "Am29F002(N)BT", AMD_ID, AM_29F002BT,
+	 256, 256,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_en29f002a
+	},
+
+	{"AMD", "Am29F016D", AMD_ID, AM_29F016D,
+	 2048, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_29f040b, erase_29f040b, write_29f040b
+	},
+
+	{"AMD", "Am29F040B", AMD_ID, AM_29F040B,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_29f040b, erase_29f040b, write_29f040b
+	},
+
+	{"AMD", "Am29LV040B", AMD_ID, AM_29LV040B,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_29f040b, erase_29f040b, write_29f040b
+	},
+
+	{"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008,
+	 256, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081,
+	 1024, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161,
+	 2048, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321,
+	 4096, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A,
+	 4096, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641,
+	 8192, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B,
+	 64, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010,
+	 128, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read
+	},
+
+	{"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A,
+	 1024, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161,
+	 2048, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
+	{"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A,
+	 2048, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	},
+
 	/*The AT26DF321 has the same ID as the AT25DF321. */
-	/*{"Atmel",	"AT26DF321",		ATMEL_ID,	AT_26DF321,		4096,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,			NULL,		spi_chip_read},*/
-	{"Atmel",	"AT26F004",		ATMEL_ID,	AT_26F004,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,	NULL /* Incompatible Page write */,spi_chip_read},
-	{"Atmel",	"AT29C020",		ATMEL_ID,	AT_29C020,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Atmel",	"AT29C040A",		ATMEL_ID,	AT_29C040A,		512,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Atmel",	"AT45CS1282",		ATMEL_ID,	AT_45CS1282,		16896/*!*/,1056/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL /* Incompatible Page write */,	NULL /* Incompatible read */}, /* No power of two sizes */
-	{"Atmel",	"AT45DB011D",		ATMEL_ID,	AT_45DB011D,		128/*!*/,256/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL}, /* Size can only be determined from status register */
-	{"Atmel",	"AT45DB021D",		ATMEL_ID,	AT_45DB021D,		256/*!*/,256/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL}, /* Size can only be determined from status register */
-	{"Atmel",	"AT45DB041D",		ATMEL_ID,	AT_45DB041D,		512/*!*/,256/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL}, /* Size can only be determined from status register */
-	{"Atmel",	"AT45DB081D",		ATMEL_ID,	AT_45DB081D,		1024/*!*/,256/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL}, /* Size can only be determined from status register */
-	{"Atmel",	"AT45DB161D",		ATMEL_ID,	AT_45DB161D,		2048/*!*/,512/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL}, /* Size can only be determined from status register */
-	{"Atmel",	"AT45DB321C",		ATMEL_ID,	AT_45DB321C,		4224/*!*/,528/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL /* Incompatible read */}, /* No power of two sizes */
-	{"Atmel",	"AT45DB321D",		ATMEL_ID,	AT_45DB321D,		4096/*!*/,512/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL}, /* Size can only be determined from status register */
-	{"Atmel",	"AT45DB642D",		ATMEL_ID,	AT_45DB642D,		8192/*!*/,1024/*!*/,	TEST_BAD_READ,	probe_spi_rdid,		NULL,	NULL,	NULL}, /* Size can only be determined from status register */
-	{"Atmel",	"AT49F002(N)",		ATMEL_ID,	AT_49F002N,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"Atmel",	"AT49F002(N)T",		ATMEL_ID,	AT_49F002NT,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"AMIC",	"A25L40P",		AMIC_ID,	AMIC_A25L40P,		512,	256,		TEST_OK_PREW,	probe_spi_rdid4,	spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"AMIC",	"A29002B",		AMIC_ID_NOPREFIX, AMIC_A29002B,		256,	64 * 1024,	TEST_UNTESTED,	probe_29f002,		erase_29f002,			write_29f002},
-	{"AMIC",	"A29002T",		AMIC_ID_NOPREFIX, AMIC_A29002T,		256,	64 * 1024,	TEST_OK_PREW,	probe_29f002,		erase_29f002,			write_29f002},
-	{"AMIC",	"A29040B",		AMIC_ID_NOPREFIX, AMIC_A29040B,		512,	64 * 1024,	TEST_OK_PR,	probe_29f040b,		erase_29f040b,			write_29f040b},
-	{"AMIC",	"A49LF040A",		AMIC_ID_NOPREFIX, AMIC_A49LF040A,	512,	64 * 1024,	TEST_OK_PREW,	probe_49fl00x,		erase_49fl00x,			write_49fl00x},
-	{"EMST",	"F49B002UA",		EMST_ID,	EMST_F49B002UA,		256,	4096,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"EON",		"EN29F002(A)(N)B",	EON_ID,		EN_29F002B,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
-	{"EON",		"EN29F002(A)(N)T",	EON_ID,		EN_29F002T,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
-	{"Fujitsu",	"MBM29F004BC",		FUJITSU_ID,	MBM29F004BC,		512,	64 * 1024,	TEST_UNTESTED,	probe_jedec,		NULL,			NULL},
-	{"Fujitsu",	"MBM29F004TC",		FUJITSU_ID,	MBM29F004TC,		512,	64 * 1024,	TEST_UNTESTED,	probe_jedec,		NULL,			NULL},
-	{"Fujitsu",	"MBM29F400BC",		FUJITSU_ID,	MBM29F400BC,		512,	64 * 1024,	TEST_UNTESTED,	probe_m29f400bt,	erase_m29f400bt,		write_coreboot_m29f400bt},
-	{"Fujitsu",	"MBM29F400TC",		FUJITSU_ID,	MBM29F400TC,		512,	64 * 1024,	TEST_UNTESTED,	probe_m29f400bt,	erase_m29f400bt,		write_coreboot_m29f400bt},
-	{"Intel",	"82802AB",		INTEL_ID,	173,			512,	64 * 1024,	TEST_OK_PREW,	probe_82802ab,		erase_82802ab,			write_82802ab},
-	{"Intel",	"82802AC",		INTEL_ID,	172,			1024,	64 * 1024,	TEST_OK_PREW,	probe_82802ab,		erase_82802ab,			write_82802ab},
-	{"Macronix",	"MX25L512",		MX_ID,		MX_25L512,		64,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX25L1005",		MX_ID,		MX_25L1005,		128,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX25L2005",		MX_ID,		MX_25L2005,		256,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX25L4005",		MX_ID,		MX_25L4005,		512,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX25L8005",		MX_ID,		MX_25L8005,		1024,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX25L1605",		MX_ID,		MX_25L1605,		2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX25L3205",		MX_ID,		MX_25L3205,		4096,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX25L6405",		MX_ID,		MX_25L6405,		8192,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"Macronix",	"MX29F002B",		MX_ID,		MX_29F002B,		256,	64 * 1024,	TEST_UNTESTED,	probe_29f002,		erase_29f002,			write_29f002},
-	{"Macronix",	"MX29F002T",		MX_ID,		MX_29F002T,		256,	64 * 1024,	TEST_UNTESTED,	probe_29f002,		erase_29f002,			write_29f002},
-	{"Numonyx",	"M25PE10",		ST_ID,		0x8011,			128,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_d8,	spi_chip_write, spi_chip_read},
-	{"Numonyx",	"M25PE20",		ST_ID,		0x8012,			256,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_d8,	spi_chip_write, spi_chip_read},
-	{"Numonyx",	"M25PE40",		ST_ID,		0x8013,			256,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_d8,	spi_chip_write, spi_chip_read},
-	{"Numonyx",	"M25PE80",		ST_ID,		0x8014,			1024,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_d8,	spi_chip_write, spi_chip_read},
-	{"Numonyx",	"M25PE16",		ST_ID,		0x8015,			2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_d8,	spi_chip_write, spi_chip_read},
-	{"PMC",		"Pm25LV010",		PMC_ID,		PMC_25LV010,		128,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"PMC",		"Pm25LV016B",		PMC_ID,		PMC_25LV016B,		2048,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"PMC",		"Pm25LV020",		PMC_ID,		PMC_25LV020,		256,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"PMC",		"Pm25LV040",		PMC_ID,		PMC_25LV040,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"PMC",		"Pm25LV080B",		PMC_ID,		PMC_25LV080B,		1024,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"PMC",		"Pm25LV512",		PMC_ID,		PMC_25LV512,		64,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"PMC",		"Pm49FL002",		PMC_ID_NOPREFIX,PMC_49FL002,		256,	16 * 1024,	TEST_OK_PREW,	probe_49fl00x,		erase_49fl00x,		write_49fl00x},
-	{"PMC",		"Pm49FL004",		PMC_ID_NOPREFIX,PMC_49FL004,		512,	64 * 1024,	TEST_OK_PREW,	probe_49fl00x,		erase_49fl00x,		write_49fl00x},
-	{"Sharp",	"LHF00L04",		SHARP_ID,	SHARP_LHF00L04,		1024,	64 * 1024,	TEST_UNTESTED,	probe_lhf00l04,		erase_lhf00l04,			write_lhf00l04},
-	{"Spansion",	"S25FL016A",		SPANSION_ID,	SPANSION_S25FL016A,	2048,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"SST",		"SST25VF016B",		SST_ID,		SST_25VF016B,		2048,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"SST",		"SST25VF032B",		SST_ID,		SST_25VF032B,		4096,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"SST",		"SST25VF040B",		SST_ID,		SST_25VF040B,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
-	{"SST",		"SST25VF080B",		SST_ID,		SST_25VF080B,		1024,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_60_c7,	spi_chip_write,	spi_chip_read},
-	{"SST",		"SST28SF040A",		SST_ID,		SST_28SF040,		512,	256,		TEST_UNTESTED,	probe_28sf040,		erase_28sf040,			write_28sf040},
-	{"SST",		"SST29EE010",		SST_ID,		SST_29EE010,		128,	128,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"SST",		"SST29LE010",		SST_ID,		SST_29LE010,		128,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec, 		write_jedec},
-	{"SST",		"SST29EE020A",		SST_ID,		SST_29EE020A,		256,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"SST",		"SST29LE020",		SST_ID,		SST_29LE020,		256,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"SST",		"SST39SF010A",		SST_ID,		SST_39SF010,		128,	4096,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"SST",		"SST39SF020A",		SST_ID,		SST_39SF020,		256,	4096,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"SST",		"SST39SF040",		SST_ID,		SST_39SF040,		512,	4096,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"SST",		"SST39VF512",		SST_ID,		SST_39VF512,		64,	4096,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"SST",		"SST39VF010",		SST_ID,		SST_39VF010,		128,	4096,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"SST",		"SST39VF020",		SST_ID,		SST_39VF020,		256,	4096,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"SST",		"SST39VF040",		SST_ID,		SST_39VF040,		512,	4096,		TEST_OK_PROBE,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-// assume similar to 004B, ignoring data sheet
-	{"SST",		"SST49LF002A/B",	SST_ID,		SST_49LF002A,		256,	16 * 1024,	TEST_OK_PREW,	probe_sst_fwhub,	erase_sst_fwhub,		write_sst_fwhub},
-	{"SST",		"SST49LF003A/B",	SST_ID,		SST_49LF003A,		384,	64 * 1024,	TEST_UNTESTED,	probe_sst_fwhub,	erase_sst_fwhub,		write_sst_fwhub},
-	{"SST",		"SST49LF004A/B",	SST_ID,		SST_49LF004A,		512,	64 * 1024,	TEST_OK_PREW,	probe_sst_fwhub,	erase_sst_fwhub,		write_sst_fwhub},
-	{"SST",		"SST49LF004C",		SST_ID,		SST_49LF004C,		512,	4 * 1024,	TEST_UNTESTED,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
-	{"SST",		"SST49LF008A",		SST_ID,		SST_49LF008A,		1024,	64 * 1024,	TEST_OK_PREW,	probe_sst_fwhub,	erase_sst_fwhub,		write_sst_fwhub},
-	{"SST",		"SST49LF008C",		SST_ID,		SST_49LF008C,		1024,	4 * 1024,	TEST_UNTESTED,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
-	{"SST",		"SST49LF016C",		SST_ID,		SST_49LF016C,		2048,	4 * 1024,	TEST_OK_PREW,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
-	{"SST",		"SST49LF020A",		SST_ID,		SST_49LF020A,		256,	16 * 1024,	TEST_UNTESTED,	probe_jedec,		erase_49lf040,			write_49lf040},
-	{"SST",		"SST49LF040",		SST_ID,		SST_49LF040,		512,	4096,		TEST_OK_PREW,	probe_jedec,		erase_49lf040,			write_49lf040},
-	{"SST",		"SST49LF040B",		SST_ID,		SST_49LF040B,		512,	64 * 1024,	TEST_OK_PREW,	probe_sst_fwhub,	erase_sst_fwhub,		write_sst_fwhub},
-	{"SST",		"SST49LF080A",		SST_ID,		SST_49LF080A,		1024,	4096,		TEST_OK_PREW,	probe_jedec,		erase_49lf040,			write_49lf040},
-	{"SST",		"SST49LF160C",		SST_ID,		SST_49LF160C,		2048,	4 * 1024,	TEST_OK_PREW,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
-	{"ST",		"M25P05-A",		ST_ID,		ST_M25P05A,		64,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P10-A",		ST_ID,		ST_M25P10A,		128,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P20",		ST_ID,		ST_M25P20,		256,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P40",		ST_ID,		ST_M25P40,		512,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P40-old",		ST_ID,		ST_M25P40_RES,		512,	256,		TEST_UNTESTED,	probe_spi_res,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P80",		ST_ID,		ST_M25P80,		1024,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P16",		ST_ID,		ST_M25P16,		2048,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P32",		ST_ID,		ST_M25P32,		4096,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P64",		ST_ID,		ST_M25P64,		8192,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M25P128",		ST_ID,		ST_M25P128,		16384,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"ST",		"M29F002B",		ST_ID,		ST_M29F002B,		256,	64 * 1024,	TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"ST",		"M29F002T/NT",		ST_ID,		ST_M29F002T,		256,	64 * 1024,	TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"ST",		"M29F040B",		ST_ID,		ST_M29F040B,		512,	64 * 1024,	TEST_OK_PREW,	probe_29f040b,		erase_29f040b,			write_29f040b},
-	{"ST",		"M29F400BT",		ST_ID,		ST_M29F400BT,		512,	64 * 1024,	TEST_UNTESTED,	probe_m29f400bt,	erase_m29f400bt,		write_coreboot_m29f400bt},
-	{"ST",		"M29W010B",		ST_ID,		ST_M29W010B,		128,	16 * 1024,	TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"ST",		"M29W040B",		ST_ID,		ST_M29W040B,		512,	64 * 1024,	TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"ST",		"M50FLW040A",		ST_ID,		ST_M50FLW040A,		512,	64 * 1024,	TEST_UNTESTED,	probe_stm50flw0x0x,	erase_stm50flw0x0x,		write_stm50flw0x0x},
-	{"ST",		"M50FLW040B",		ST_ID,		ST_M50FLW040B,		512,	64 * 1024,	TEST_UNTESTED,	probe_stm50flw0x0x,	erase_stm50flw0x0x,		write_stm50flw0x0x},
-	{"ST",		"M50FLW080A",		ST_ID,		ST_M50FLW080A,		1024,	64 * 1024,	TEST_OK_PREW,	probe_stm50flw0x0x,	erase_stm50flw0x0x,		write_stm50flw0x0x},
-	{"ST",		"M50FLW080B",		ST_ID,		ST_M50FLW080B,		1024,	64 * 1024,	TEST_UNTESTED,	probe_stm50flw0x0x,	erase_stm50flw0x0x,		write_stm50flw0x0x},
-	{"ST",		"M50FW002",		ST_ID,		ST_M50FW002,		256,	64 * 1024,	TEST_UNTESTED,	probe_49lfxxxc,		NULL,			NULL},
-	{"ST",		"M50FW016",		ST_ID,		ST_M50FW016,		2048,	64 * 1024,	TEST_UNTESTED,	probe_82802ab,		erase_82802ab,			write_82802ab},
-	{"ST",		"M50FW040",		ST_ID,		ST_M50FW040,		512,	64 * 1024,	TEST_OK_PREW,	probe_82802ab,		erase_82802ab,			write_82802ab},
-	{"ST",		"M50FW080",		ST_ID,		ST_M50FW080,		1024,	64 * 1024,	TEST_UNTESTED,	probe_82802ab,		erase_82802ab,			write_82802ab},
-	{"ST",		"M50LPW116",		ST_ID,		ST_M50LPW116,		2048,	64 * 1024,	TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"SyncMOS",	"S29C31004T",		SYNCMOS_ID,	S29C31004T,		512,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"SyncMOS",	"S29C51001T",		SYNCMOS_ID,	S29C51001T,		128,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"SyncMOS",	"S29C51002T",		SYNCMOS_ID,	S29C51002T,		256,	128,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"SyncMOS",	"S29C51004T",		SYNCMOS_ID,	S29C51004T,		512,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"Winbond",	"W25x10",		WINBOND_NEX_ID,	W_25X10,		128,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"Winbond",	"W25x20",		WINBOND_NEX_ID,	W_25X20,		256,	256,		TEST_UNTESTED,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"Winbond",	"W25x40",		WINBOND_NEX_ID,	W_25X40,		512,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"Winbond",	"W25x80",		WINBOND_NEX_ID,	W_25X80,		1024,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
-	{"Winbond",	"W29C011",		WINBOND_ID,	W_29C011,		128,	128,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Winbond",	"W29C020C",		WINBOND_ID,	W_29C020C,		256,	128,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Winbond",	"W29C040P",		WINBOND_ID,	W_29C040P,		512,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Winbond",	"W29EE011",		WINBOND_ID,	W_29C011,		128,	128,		TEST_OK_PREW,	probe_w29ee011,		erase_chip_jedec,		write_jedec},
-	{"Winbond",	"W39V040A",		WINBOND_ID,	W_39V040A,		512,	64*1024,	TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"Winbond",	"W39V040B",		WINBOND_ID,	W_39V040B,		512,	64*1024,	TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"Winbond",	"W39V040C",		WINBOND_ID,	0x50,			512,	64*1024,	TEST_OK_PREW,	probe_w39v040c,		erase_w39v040c,			write_w39v040c},
-	{"Winbond",	"W39V040FA",		WINBOND_ID,	W_39V040FA,		512,	64*1024,	TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"Winbond",	"W39V080A",		WINBOND_ID,	W_39V080A,		1024,	64*1024,	TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_39sf020},
-	{"Winbond",	"W49F002U",		WINBOND_ID,	W_49F002U,		256,	128,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"Winbond",	"W49V002A",		WINBOND_ID,	W_49V002A,		256,	128,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"Winbond",	"W49V002FA",		WINBOND_ID,	W_49V002FA,		256,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_49f002},
-	{"Winbond",	"W39V080FA",		WINBOND_ID,	W_39V080FA,		1024,	64*1024,	TEST_OK_PREW,	probe_winbond_fwhub,	erase_winbond_fwhub,		write_winbond_fwhub},
-	{"Winbond",	"W39V080FA (dual mode)",WINBOND_ID,	W_39V080FA_DM,		512,	64*1024,	TEST_UNTESTED,	probe_winbond_fwhub,	erase_winbond_fwhub,		write_winbond_fwhub},
+	/*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321,
+	  4096, 256,
+	  TEST_UNTESTED,
+	  probe_spi_rdid, NULL, NULL, spi_chip_read
+	  },
+	*/
 
-	{"Atmel",	"unknown Atmel SPI chip",ATMEL_ID,	GENERIC_DEVICE_ID,	0,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,				NULL},
-	{"EON",		"unknown EON SPI chip",	EON_ID_NOPREFIX,GENERIC_DEVICE_ID,	0,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,				NULL},
-	{"Macronix",	"unknown Macronix SPI chip",	MX_ID,	GENERIC_DEVICE_ID,	0,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,				NULL},
-	{"PMC",		"unknown PMC SPI chip",	PMC_ID,		GENERIC_DEVICE_ID,	0,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,				NULL},
-	{"SST",		"unknown SST SPI chip",	SST_ID,		GENERIC_DEVICE_ID,	0,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,				NULL},
-	{"ST",		"unknown ST SPI chip",	ST_ID,		GENERIC_DEVICE_ID,	0,	256,		TEST_UNTESTED,	probe_spi_rdid,		NULL,				NULL},
+	{"Atmel", "AT26F004", ATMEL_ID, AT_26F004,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read
+	},
 
+	{"Atmel", "AT29C020", ATMEL_ID, AT_29C020,
+	 256, 256,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282,
+	 16896/*!*/, 1056/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */
+	}, /* No power of two sizes */
+
+	{"Atmel", "AT45DB011D", ATMEL_ID, AT_45DB011D,
+	 128/*!*/, 256/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL
+	}, /* Size can only be determined from status register */
+
+	{"Atmel", "AT45DB021D", ATMEL_ID, AT_45DB021D,
+	 256/*!*/, 256/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL
+	}, /* Size can only be determined from status register */
+
+	{"Atmel", "AT45DB041D", ATMEL_ID, AT_45DB041D,
+	 512/*!*/, 256/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL
+	}, /* Size can only be determined from status register */
+
+	{"Atmel", "AT45DB081D", ATMEL_ID, AT_45DB081D,
+	 1024/*!*/, 256/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL
+	}, /* Size can only be determined from status register */
+
+	{"Atmel", "AT45DB161D", ATMEL_ID, AT_45DB161D,
+	 2048/*!*/, 512/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL
+	}, /* Size can only be determined from status register */
+
+	{"Atmel", "AT45DB321C", ATMEL_ID, AT_45DB321C,
+	 4224/*!*/, 528/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL /* Incompatible read */
+	}, /* No power of two sizes */
+
+	{"Atmel", "AT45DB321D", ATMEL_ID, AT_45DB321D,
+	 4096/*!*/, 512/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL
+	}, /* Size can only be determined from status register */
+
+	{"Atmel", "AT45DB642D", ATMEL_ID, AT_45DB642D,
+	 8192/*!*/, 1024/*!*/,
+	 TEST_BAD_READ,
+	 probe_spi_rdid, NULL, NULL, NULL
+	}, /* Size can only be determined from status register */
+
+	{"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT,
+	 256, 256,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P,
+	 512, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B,
+	 256, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_29f002, erase_29f002, write_29f002
+	},
+
+	{"AMIC", "A29002T", AMIC_ID_NOPREFIX, AMIC_A29002T,
+	 256, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_29f002, erase_29f002, write_29f002
+	},
+
+	{"AMIC", "A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B,
+	 512, 64 * 1024,
+	 TEST_OK_PR,
+	 probe_29f040b, erase_29f040b, write_29f040b
+	},
+
+	{"AMIC", "A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_49fl00x, erase_49fl00x, write_49fl00x
+	},
+
+	{"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA,
+	 256, 4096,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_en29f002a
+	},
+
+	{"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T,
+	 256, 256,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_en29f002a
+	},
+
+	{"Fujitsu", "MBM29F004BC", FUJITSU_ID, MBM29F004BC,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, NULL, NULL
+	},
+
+	{"Fujitsu", "MBM29F004TC", FUJITSU_ID, MBM29F004TC,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, NULL, NULL
+	},
+
+	{"Fujitsu", "MBM29F400BC", FUJITSU_ID, MBM29F400BC,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt
+	},
+
+	{"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt
+	},
+
+	{"Intel", "82802AB", INTEL_ID, 173,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_82802ab, erase_82802ab, write_82802ab
+	},
+
+	{"Intel", "82802AC", INTEL_ID, 172,
+	 1024, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_82802ab, erase_82802ab, write_82802ab
+	},
+
+	{"Macronix", "MX25L512", MX_ID, MX_25L512,
+	 64, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX25L1005", MX_ID, MX_25L1005,
+	 128, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX25L2005", MX_ID, MX_25L2005,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX25L4005", MX_ID, MX_25L4005,
+	 512, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX25L8005", MX_ID, MX_25L8005,
+	 1024, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX25L1605", MX_ID, MX_25L1605,
+	 2048, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX25L3205", MX_ID, MX_25L3205,
+	 4096, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX25L6405", MX_ID, MX_25L6405,
+	 8192, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Macronix", "MX29F002B", MX_ID, MX_29F002B,
+	 256, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_29f002, erase_29f002, write_29f002
+	},
+
+	{"Macronix", "MX29F002T", MX_ID, MX_29F002T,
+	 256, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_29f002, erase_29f002, write_29f002
+	},
+
+	{"Numonyx", "M25PE10", ST_ID, 0x8011,
+	 128, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	},
+
+	{"Numonyx", "M25PE20", ST_ID, 0x8012,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	},
+
+	{"Numonyx", "M25PE40", ST_ID, 0x8013,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	},
+
+	{"Numonyx", "M25PE80", ST_ID, 0x8014,
+	 1024, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	},
+
+	{"Numonyx", "M25PE16", ST_ID, 0x8015,
+	 2048, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	},
+
+	{"PMC", "Pm25LV010", PMC_ID, PMC_25LV010,
+	 128, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B,
+	 2048, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"PMC", "Pm25LV020", PMC_ID, PMC_25LV020,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"PMC", "Pm25LV040", PMC_ID, PMC_25LV040,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B,
+	 1024, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"PMC", "Pm25LV512", PMC_ID, PMC_25LV512,
+	 64, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"PMC", "Pm49FL002", PMC_ID_NOPREFIX, PMC_49FL002,
+	 256, 16 * 1024,
+	 TEST_OK_PREW,
+	 probe_49fl00x, erase_49fl00x, write_49fl00x
+	},
+
+	{"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_49fl00x, erase_49fl00x, write_49fl00x
+	},
+
+	{"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04,
+	 1024, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_lhf00l04, erase_lhf00l04, write_lhf00l04
+	},
+
+	{"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A,
+	 2048, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"SST", "SST25VF016B", SST_ID, SST_25VF016B,
+	 2048, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"SST", "SST25VF032B", SST_ID, SST_25VF032B,
+	 4096, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"SST", "SST25VF040B", SST_ID, SST_25VF040B,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"SST", "SST25VF080B", SST_ID, SST_25VF080B,
+	 1024, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_60_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"SST", "SST28SF040A", SST_ID, SST_28SF040,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_28sf040, erase_28sf040, write_28sf040
+	},
+
+	{"SST", "SST29EE010", SST_ID, SST_29EE010,
+	 128, 128,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"SST", "SST29LE010", SST_ID, SST_29LE010,
+	 128, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"SST", "SST29EE020A", SST_ID, SST_29EE020A,
+	 256, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"SST", "SST29LE020", SST_ID, SST_29LE020,
+	 256, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"SST", "SST39SF010A", SST_ID, SST_39SF010,
+	 128, 4096,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"SST", "SST39SF020A", SST_ID, SST_39SF020,
+	 256, 4096,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"SST", "SST39SF040", SST_ID, SST_39SF040,
+	 512, 4096,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"SST", "SST39VF512", SST_ID, SST_39VF512,
+	 64, 4096,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"SST", "SST39VF010", SST_ID, SST_39VF010,
+	 128, 4096,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"SST", "SST39VF020", SST_ID, SST_39VF020,
+	 256, 4096,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"SST", "SST39VF040", SST_ID, SST_39VF040,
+	 512, 4096,
+	 TEST_OK_PROBE,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	}, /* assume similar to 004B, ignoring data sheet */
+
+	{"SST", "SST49LF002A/B", SST_ID, SST_49LF002A,
+	 256, 16 * 1024,
+	 TEST_OK_PREW,
+	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	},
+
+	{"SST", "SST49LF003A/B", SST_ID, SST_49LF003A,
+	 384, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	},
+
+	{"SST", "SST49LF004A/B", SST_ID, SST_49LF004A,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	},
+
+	{"SST", "SST49LF004C", SST_ID, SST_49LF004C,
+	 512, 4 * 1024,
+	 TEST_UNTESTED,
+	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	},
+
+	{"SST", "SST49LF008A", SST_ID, SST_49LF008A,
+	 1024, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	},
+
+	{"SST", "SST49LF008C", SST_ID, SST_49LF008C,
+	 1024, 4 * 1024,
+	 TEST_UNTESTED,
+	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	},
+
+	{"SST", "SST49LF016C", SST_ID, SST_49LF016C,
+	 2048, 4 * 1024,
+	 TEST_OK_PREW,
+	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	},
+
+	{"SST", "SST49LF020A", SST_ID, SST_49LF020A,
+	 256, 16 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_49lf040, write_49lf040
+	},
+
+	{"SST", "SST49LF040", SST_ID, SST_49LF040,
+	 512, 4096,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_49lf040, write_49lf040
+	},
+
+	{"SST", "SST49LF040B", SST_ID, SST_49LF040B,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	},
+
+	{"SST", "SST49LF080A", SST_ID, SST_49LF080A,
+	 1024, 4096,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_49lf040, write_49lf040
+	},
+
+	{"SST", "SST49LF160C", SST_ID, SST_49LF160C,
+	 2048, 4 * 1024,
+	 TEST_OK_PREW,
+	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	},
+
+	{"ST", "M25P05-A", ST_ID, ST_M25P05A,
+	 64, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P10-A", ST_ID, ST_M25P10A,
+	 128, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P20", ST_ID, ST_M25P20,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P40", ST_ID, ST_M25P40,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P40-old", ST_ID, ST_M25P40_RES,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_spi_res, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P80", ST_ID, ST_M25P80,
+	 1024, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P16", ST_ID, ST_M25P16,
+	 2048, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P32", ST_ID, ST_M25P32,
+	 4096, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P64", ST_ID, ST_M25P64,
+	 8192, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M25P128", ST_ID, ST_M25P128,
+	 16384, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"ST", "M29F002B", ST_ID, ST_M29F002B,
+	 256, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"ST", "M29F002T/NT", ST_ID, ST_M29F002T,
+	 256, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"ST", "M29F040B", ST_ID, ST_M29F040B,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_29f040b, erase_29f040b, write_29f040b
+	},
+
+	{"ST", "M29F400BT", ST_ID, ST_M29F400BT,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt
+	},
+
+	{"ST", "M29W010B", ST_ID, ST_M29W010B,
+	 128, 16 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"ST", "M29W040B", ST_ID, ST_M29W040B,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"ST", "M50FLW040A", ST_ID, ST_M50FLW040A,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	},
+
+	{"ST", "M50FLW040B", ST_ID, ST_M50FLW040B,
+	 512, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	},
+
+	{"ST", "M50FLW080A", ST_ID, ST_M50FLW080A,
+	 1024, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	},
+
+	{"ST", "M50FLW080B", ST_ID, ST_M50FLW080B,
+	 1024, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	},
+
+	{"ST", "M50FW002", ST_ID, ST_M50FW002,
+	 256, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_49lfxxxc, NULL, NULL
+	},
+
+	{"ST", "M50FW016", ST_ID, ST_M50FW016,
+	 2048, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_82802ab, erase_82802ab, write_82802ab
+	},
+
+	{"ST", "M50FW040", ST_ID, ST_M50FW040,
+	 512, 64 * 1024,
+	 TEST_OK_PREW,
+	 probe_82802ab, erase_82802ab, write_82802ab
+	},
+
+	{"ST", "M50FW080", ST_ID, ST_M50FW080,
+	 1024, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_82802ab, erase_82802ab, write_82802ab
+	},
+
+	{"ST", "M50LPW116", ST_ID, ST_M50LPW116,
+	 2048, 64 * 1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T,
+	 512, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T,
+	 128, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T,
+	 256, 128,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T,
+	 512, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10,
+	 128, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20,
+	 256, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40,
+	 512, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80,
+	 1024, 256,
+	 TEST_OK_PREW,
+	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	},
+
+	{"Winbond", "W29C011", WINBOND_ID, W_29C011,
+	 128, 128,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"Winbond", "W29C020C", WINBOND_ID, W_29C020C,
+	 256, 128,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"Winbond", "W29C040P", WINBOND_ID, W_29C040P,
+	 512, 256,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_jedec
+	},
+
+	{"Winbond", "W29EE011", WINBOND_ID, W_29C011,
+	 128, 128,
+	 TEST_OK_PREW,
+	 probe_w29ee011, erase_chip_jedec, write_jedec
+	},
+
+	{"Winbond", "W39V040A", WINBOND_ID, W_39V040A,
+	 512, 64*1024,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"Winbond", "W39V040B", WINBOND_ID, W_39V040B,
+	 512, 64*1024,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"Winbond", "W39V040C", WINBOND_ID, 0x50,
+	 512, 64*1024,
+	 TEST_OK_PREW,
+	 probe_w39v040c, erase_w39v040c, write_w39v040c
+	},
+
+	{"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA,
+	 512, 64*1024,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"Winbond", "W39V080A", WINBOND_ID, W_39V080A,
+	 1024, 64*1024,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_39sf020
+	},
+
+	{"Winbond", "W49F002U", WINBOND_ID, W_49F002U,
+	 256, 128,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"Winbond", "W49V002A", WINBOND_ID, W_49V002A,
+	 256, 128,
+	 TEST_OK_PREW,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"Winbond", "W49V002FA", WINBOND_ID, W_49V002FA,
+	 256, 128,
+	 TEST_UNTESTED,
+	 probe_jedec, erase_chip_jedec, write_49f002
+	},
+
+	{"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA,
+	 1024, 64*1024,
+	 TEST_OK_PREW,
+	 probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub
+	},
+
+	{"Winbond", "W39V080FA (dual mode)", WINBOND_ID, W_39V080FA_DM,
+	 512, 64*1024,
+	 TEST_UNTESTED,
+	 probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub
+	},
+
+	{"Atmel", "unknown Atmel SPI chip", ATMEL_ID, GENERIC_DEVICE_ID,
+	 0, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL
+	},
+
+	{"EON", "unknown EON SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID,
+	 0, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL
+	},
+
+	{"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID,
+	 0, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL
+	},
+
+	{"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID,
+	 0, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL
+	},
+
+	{"SST", "unknown SST SPI chip", SST_ID, GENERIC_DEVICE_ID,
+	 0, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL
+	},
+
+	{"ST", "unknown ST SPI chip", ST_ID, GENERIC_DEVICE_ID,
+	 0, 256,
+	 TEST_UNTESTED,
+	 probe_spi_rdid, NULL, NULL
+	},
+
 	{NULL,}
 };




From svn at coreboot.org  Mon Dec  8 19:16:58 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  8 Dec 2008 19:16:58 +0100
Subject: [coreboot] r3805 - trunk/util/flashrom
Message-ID: <mailman.2557.1355071450.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-12-08 19:16:58 +0100 (Mon, 08 Dec 2008)
New Revision: 3805

Modified:
   trunk/util/flashrom/chipset_enable.c
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/ichspi.c
Log:
Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI
configuration is locked down.

Signed-off-by: FENG yu ning <fengyuning1984 at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c	2008-12-08 18:15:10 UTC (rev 3804)
+++ trunk/util/flashrom/chipset_enable.c	2008-12-08 18:16:58 UTC (rev 3805)
@@ -47,6 +47,8 @@
 flashbus_t flashbus = BUS_TYPE_LPC;
 void *spibar = NULL;
 
+extern int ichspi_lock;
+
 static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
@@ -335,6 +337,7 @@
 		printf_debug("\n");
 		if ((*(uint16_t *) spibar) & (1 << 15)) {
 			printf("WARNING: SPI Configuration Lockdown activated.\n");
+			ichspi_lock = 1;
 		}
 		break;
 	case BUS_TYPE_ICH9_SPI:

Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h	2008-12-08 18:15:10 UTC (rev 3804)
+++ trunk/util/flashrom/flash.h	2008-12-08 18:16:58 UTC (rev 3805)
@@ -51,6 +51,12 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
+/* for pairing opcodes with their required preop */
+struct preop_opcode_pair {
+	uint8_t preop;
+	uint8_t opcode;
+};
+
 struct flashchip {
 	const char *vendor;
 	const char *name;
@@ -76,6 +82,8 @@
 	int (*write) (struct flashchip *flash, uint8_t *buf);
 	int (*read) (struct flashchip *flash, uint8_t *buf);
 
+	struct preop_opcode_pair *preop_opcode_pairs;
+
 	/* Some flash devices have an additional register space. */
 	volatile uint8_t *virtual_memory;
 	volatile uint8_t *virtual_registers;

Modified: trunk/util/flashrom/ichspi.c
===================================================================
--- trunk/util/flashrom/ichspi.c	2008-12-08 18:15:10 UTC (rev 3804)
+++ trunk/util/flashrom/ichspi.c	2008-12-08 18:16:58 UTC (rev 3805)
@@ -101,6 +101,9 @@
 #define ICH7_REG_OPTYPE                0x56	/* 16 Bits */
 #define ICH7_REG_OPMENU                0x58	/* 64 Bits */
 
+/* ICH SPI configuration lock-down. May be set during chipset enabling. */
+int ichspi_lock = 0;
+
 typedef struct _OPCODE {
 	uint8_t opcode;		//This commands spi opcode
 	uint8_t spi_type;	//This commands spi type
@@ -147,7 +150,11 @@
 #define REGWRITE8(X,Y)  (*(uint8_t *)((uint8_t *)spibar+X)=Y)
 
 /* Common SPI functions */
+static inline int find_opcode(OPCODES *op, uint8_t opcode);
+static inline int find_preop(OPCODES *op, uint8_t preop);
+static int generate_opcodes(struct flashchip * flash, OPCODES * op);
 static int program_opcodes(OPCODES * op);
+int ich_check_opcodes(struct flashchip * flash);
 static int run_opcode(OPCODE op, uint32_t offset,
 		      uint8_t datalength, uint8_t * data);
 static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
@@ -171,6 +178,98 @@
 	 }
 };
 
+OPCODES O_EXISTING = {};
+
+static inline int find_opcode(OPCODES *op, uint8_t opcode)
+{
+	int a;
+
+	for (a = 0; a < 8; a++) {
+		if (op->opcode[a].opcode == opcode)
+			return a;
+	}
+
+	return -1;
+}
+
+static inline int find_preop(OPCODES *op, uint8_t preop)
+{
+	int a;
+
+	for (a = 0; a < 2; a++) {
+		if (op->preop[a] == preop)
+			return a;
+	}
+
+	return -1;
+}
+
+static int generate_opcodes(struct flashchip * flash, OPCODES * op)
+{
+  int a, b, i;
+	uint16_t preop, optype;
+	uint32_t opmenu[2];
+	struct preop_opcode_pair *pair;
+
+	if (op == NULL) {
+		printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__);
+		return -1;
+	}
+
+	switch (flashbus) {
+	case BUS_TYPE_ICH7_SPI:
+	case BUS_TYPE_VIA_SPI:
+		preop = REGREAD16(ICH7_REG_PREOP);
+		optype = REGREAD16(ICH7_REG_OPTYPE);
+		opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
+		opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
+		break;
+	case BUS_TYPE_ICH9_SPI:
+		preop = REGREAD16(ICH9_REG_PREOP);
+		optype = REGREAD16(ICH9_REG_OPTYPE);
+		opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
+		opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
+		break;
+	default:
+		printf_debug("%s: unsupported chipset\n", __FUNCTION__);
+		return -1;
+	}
+
+	op->preop[0] = (uint8_t) preop;
+	op->preop[1] = (uint8_t) (preop >> 8);
+
+	for (a = 0; a < 8; a++) {
+		op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
+		optype >>= 2;
+	}
+
+	for (a = 0; a < 4; a++) {
+		op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
+		opmenu[0] >>= 8;
+	}
+
+	for (a = 4; a < 8; a++) {
+		op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
+		opmenu[1] >>= 8;
+	}
+
+	/* atomic (link opcode with required pre-op) */
+	for (a = 4; a < 8; a++)
+		op->opcode[a].atomic = 0;
+
+	pair = flash->preop_opcode_pairs;
+	if (pair) {
+		for (i = 0; pair[i].opcode; i++) {
+			a = find_opcode(op, pair[i].opcode);
+			b = find_preop(op, pair[i].preop);
+			if ((a != -1) && (b != -1))
+				op->opcode[a].atomic = (uint8_t) ++b;
+		}
+	}
+
+	return 0;
+}
+
 int program_opcodes(OPCODES * op)
 {
 	uint8_t a;
@@ -224,6 +323,41 @@
 	return 0;
 }
 
+/* This function generates OPCODES from or programs OPCODES to the chipset
+ * according to its SPI configuration lock.
+ *
+ * It should be called in the ICH7/ICH9/VIA part of each operation driver(i.e.
+ * probe, read, erase, write, etc.) before any command is sent.
+ */
+int ich_check_opcodes(struct flashchip * flash)
+{
+	int rc = 0;
+	OPCODES *curopcodes_done;
+
+	if (curopcodes)
+		return 0;
+
+	if (ichspi_lock) {
+		printf_debug("Generating OPCODES... ");
+		curopcodes_done = &O_EXISTING;
+		rc = generate_opcodes(flash, curopcodes_done);
+	} else {
+		printf_debug("Programming OPCODES... ");
+		curopcodes_done = &O_ST_M25P;
+		rc = program_opcodes(curopcodes_done);
+	}
+
+	if (rc) {
+		curopcodes = NULL;
+		printf_debug("failed\n");
+		return 1;
+	} else {
+		curopcodes = curopcodes_done;
+		printf_debug("done\n");
+		return 0;
+	}
+}
+
 static int ich7_run_opcode(OPCODE op, uint32_t offset,
 			   uint8_t datalength, uint8_t * data, int maxdata)
 {




From mylesgw at gmail.com  Mon Dec  8 19:20:11 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 8 Dec 2008 11:20:11 -0700
Subject: [coreboot] PNP fixes
Message-ID: <2831fecf0812081020t62bd54ddl6471cec89493647@mail.gmail.com>

This fixes the fintek superIO by adding a placeholder so that array indexing
works.

Besides that it
- Changes the struct definition in include/device/pnp.h so that it is more
like v2 for porting ease.
- Fixes some bugs I introduced in device/pnp_device.c
- Sets up the default values of the superios based on v2 boards.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Mon Dec  8 20:13:57 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 8 Dec 2008 12:13:57 -0700
Subject: [coreboot] PNP fixes
In-Reply-To: <2831fecf0812081020t62bd54ddl6471cec89493647@mail.gmail.com>
References: <2831fecf0812081020t62bd54ddl6471cec89493647@mail.gmail.com>
Message-ID: <2831fecf0812081113r52a04650w9717772d2778aa43@mail.gmail.com>

On Mon, Dec 8, 2008 at 11:20 AM, Myles Watson <mylesgw at gmail.com> wrote:

> This fixes the fintek superIO by adding a placeholder so that array
> indexing works.
>
> Besides that it
> - Changes the struct definition in include/device/pnp.h so that it is more
> like v2 for porting ease.
> - Fixes some bugs I introduced in device/pnp_device.c
> - Sets up the default values of the superios based on v2 boards.
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>
> Thanks,
> Myles


This patch is simpler.  It just fixes the struct definition  and fixes the
|| when it should be | bugs.  It makes it so that all of the SuperIOs build
again.

build tested on:
serengeti, m57sli, kontron, jetway

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Mon Dec  8 20:15:04 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 8 Dec 2008 12:15:04 -0700
Subject: [coreboot] PNP fixes
In-Reply-To: <2831fecf0812081113r52a04650w9717772d2778aa43@mail.gmail.com>
References: <2831fecf0812081020t62bd54ddl6471cec89493647@mail.gmail.com>
	<2831fecf0812081113r52a04650w9717772d2778aa43@mail.gmail.com>
Message-ID: <2831fecf0812081115tddc9f42o24b9a78955357fbe@mail.gmail.com>

On Mon, Dec 8, 2008 at 12:13 PM, Myles Watson <mylesgw at gmail.com> wrote:

>
>
> On Mon, Dec 8, 2008 at 11:20 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
>> This fixes the fintek superIO by adding a placeholder so that array
>> indexing works.
>>
>> Besides that it
>> - Changes the struct definition in include/device/pnp.h so that it is more
>> like v2 for porting ease.
>> - Fixes some bugs I introduced in device/pnp_device.c
>> - Sets up the default values of the superios based on v2 boards.
>>
>> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>>
>> Thanks,
>> Myles
>
>
> This patch is simpler.  It just fixes the struct definition  and fixes the
> || when it should be | bugs.  It makes it so that all of the SuperIOs build
> again.
>
> build tested on:
> serengeti, m57sli, kontron, jetway
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>
> Thanks,
> Myles


How much simpler can you get than no patch?

Thanks,
Myles
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From rminnich at gmail.com  Mon Dec  8 21:26:25 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 8 Dec 2008 12:26:25 -0800
Subject: [coreboot] PNP fixes
In-Reply-To: <2831fecf0812081115tddc9f42o24b9a78955357fbe@mail.gmail.com>
References: <2831fecf0812081020t62bd54ddl6471cec89493647@mail.gmail.com>
	<2831fecf0812081113r52a04650w9717772d2778aa43@mail.gmail.com>
	<2831fecf0812081115tddc9f42o24b9a78955357fbe@mail.gmail.com>
Message-ID: <13426df10812081226s3a7ab628i6d29d0864387faed@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Mon Dec  8 21:40:02 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  8 Dec 2008 21:40:02 +0100
Subject: [coreboot] r1066 - in coreboot-v3: device include/device
	superio/fintek/f71805f superio/ite/it8712f
	superio/ite/it8716f superio/winbond/w83627hf
	superio/winbond/w83627thg
Message-ID: <mailman.2558.1355071450.16123.coreboot@coreboot.org>

Author: myles
Date: 2008-12-08 21:40:02 +0100 (Mon, 08 Dec 2008)
New Revision: 1066

Modified:
   coreboot-v3/device/pnp_device.c
   coreboot-v3/include/device/pnp.h
   coreboot-v3/superio/fintek/f71805f/superio.c
   coreboot-v3/superio/ite/it8712f/superio.c
   coreboot-v3/superio/ite/it8716f/superio.c
   coreboot-v3/superio/winbond/w83627hf/superio.c
   coreboot-v3/superio/winbond/w83627thg/dts
   coreboot-v3/superio/winbond/w83627thg/superio.c
Log:
This patch makes all the SuperIOs build again, and reverts some breakage that
I introduced earlier.

It adds a placeholder in the fintek SuperIO so the array indexing works.
It moves the enable to make the struct more compatible with v2.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/device/pnp_device.c
===================================================================
--- coreboot-v3/device/pnp_device.c	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/device/pnp_device.c	2008-12-08 20:40:02 UTC (rev 1066)
@@ -57,7 +57,7 @@
 
 int pnp_read_enable(struct device *dev)
 {
-	return !!pnp_read_config(dev, 0x30);
+	return (pnp_read_config(dev, 0x30) ? 0x1 : 0x0);
 }
 
 void pnp_set_iobase(struct device *dev, unsigned int index, unsigned int iobase)
@@ -110,7 +110,7 @@
 	}
 	resource->flags |= IORESOURCE_STORED;
 
-	report_resource_stored(dev, resource, "");
+	report_resource_stored(dev, resource, __func__);
 }
 
 void pnp_set_resources(struct device *dev)
@@ -192,7 +192,7 @@
 	resource->limit = info->mask | (step - 1);
 	resource->size = 1 << gran;
 	resource->base = info->val;
-	resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
+	resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 }
 
 static void get_resources(struct device *dev, struct pnp_info *info)
@@ -215,29 +215,29 @@
 		resource = new_resource(dev, PNP_IDX_IRQ0);
 		resource->size = 1;
 		resource->flags |= IORESOURCE_IRQ;
-		resource->base = info->irq0.val;
-		resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
+		resource->base = info->irq0;
+		resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 	}
 	if (info->flags & PNP_IRQ1) {
 		resource = new_resource(dev, PNP_IDX_IRQ1);
 		resource->size = 1;
 		resource->flags |= IORESOURCE_IRQ;
-		resource->base = info->irq1.val;
-		resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
+		resource->base = info->irq1;
+		resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 	}
 	if (info->flags & PNP_DRQ0) {
 		resource = new_resource(dev, PNP_IDX_DRQ0);
 		resource->size = 1;
 		resource->flags |= IORESOURCE_DRQ;
-		resource->base = info->drq0.val;
-		resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
+		resource->base = info->drq0;
+		resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 	}
 	if (info->flags & PNP_DRQ1) {
 		resource = new_resource(dev, PNP_IDX_DRQ1);
 		resource->size = 1;
 		resource->flags |= IORESOURCE_DRQ;
-		resource->base = info->drq0.val;
-		resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
+		resource->base = info->drq0;
+		resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 	}
 }
 
@@ -254,6 +254,7 @@
 
 	/* Setup the ops and resources on the newly allocated devices. */
 	for (i = 0; i < functions; i++) {
+
 		path.pnp.device = info[i].function;
 
 		dev = find_dev_path(&base_dev->link[0], &path);
@@ -263,7 +264,7 @@
 			       __func__, dev->dtsname, dev_path(dev));
 			continue;
 		}
-		
+
 		dev = alloc_dev(&base_dev->link[0], &path, &id);
 
 		if (!dev)
@@ -310,12 +311,12 @@
 {
 	int i, idx;
 	u16 port = dev->path.pnp.port;
-	
+
 	/* Determine Super I/O config port. */
 	idx = (port == 0x3f0) ? 0 : ((port == 0x3bd) ? 1 : 2);
 	for (i = 0; i < 4; i++)
 		outb(init[idx][i], ISA_PNP_ADDR);
-	
+
 	/* Sequentially write the 32 MB PnP init values. */
 	for (i = 0; i < 32; i++)
 		outb(initkey_mbpnp[i], port);

Modified: coreboot-v3/include/device/pnp.h
===================================================================
--- coreboot-v3/include/device/pnp.h	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/include/device/pnp.h	2008-12-08 20:40:02 UTC (rev 1066)
@@ -59,7 +59,6 @@
 struct pnp_info {
 	struct device_operations *ops;
 	unsigned function;
-	unsigned enable;
 	unsigned flags;
 #define PNP_IO0  0x01
 #define PNP_IO1  0x02
@@ -69,11 +68,15 @@
 #define PNP_IRQ1 0x20
 #define PNP_DRQ0 0x40
 #define PNP_DRQ1 0x80
-	struct io_info io0, io1, io2, io3, irq0, irq1, drq0, drq1;
+	struct io_info io0, io1, io2, io3;
+	unsigned irq0, irq1, drq0, drq1;
+	unsigned enable;
 };
+
 struct resource *pnp_get_resource(struct device * dev, unsigned index);
+
 void pnp_enable_devices(struct device *dev, struct device_operations *ops,
-	unsigned functions, struct pnp_info *info);
+			unsigned functions, struct pnp_info *info);
 
 #define PNP_IDX_IO0  0x60
 #define PNP_IDX_IO1  0x62

Modified: coreboot-v3/superio/fintek/f71805f/superio.c
===================================================================
--- coreboot-v3/superio/fintek/f71805f/superio.c	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/superio/fintek/f71805f/superio.c	2008-12-08 20:40:02 UTC (rev 1066)
@@ -93,6 +93,8 @@
 };
 
 static struct pnp_info pnp_dev_info[] = {
+		/* Ops, function #, All resources needed by dev,  io_info */
+	{ NULL, F71805F_FDC, }, /* Place holder. */
 	{ &f71805f_ops, F71805F_COM1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 	{ &f71805f_ops, F71805F_COM2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 	/* TODO: Everything else */
@@ -106,12 +108,12 @@
 	/* COM1 */
 	pnp_dev_info[F71805F_COM1].enable = conf->com1enable;
 	pnp_dev_info[F71805F_COM1].io0.val = conf->com1io;
-	pnp_dev_info[F71805F_COM1].irq0.val = conf->com1irq;
+	pnp_dev_info[F71805F_COM1].irq0 = conf->com1irq;
 
 	/* COM2 */
 	pnp_dev_info[F71805F_COM2].enable = conf->com2enable;
 	pnp_dev_info[F71805F_COM2].io0.val = conf->com2io;
-	pnp_dev_info[F71805F_COM2].irq0.val = conf->com2irq;
+	pnp_dev_info[F71805F_COM2].irq0 = conf->com2irq;
 
 	/* Initialize SuperIO for PNP children. */
 	if (!dev->links) {

Modified: coreboot-v3/superio/ite/it8712f/superio.c
===================================================================
--- coreboot-v3/superio/ite/it8712f/superio.c	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/superio/ite/it8712f/superio.c	2008-12-08 20:40:02 UTC (rev 1066)
@@ -95,18 +95,18 @@
 };
 
 static struct pnp_info pnp_dev_info[] = {
-				/* Enable,  All resources need by dev,  io_info_structs */
-	{&it8712f_ops, IT8712F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},},
-	{&it8712f_ops, IT8712F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
-	{&it8712f_ops, IT8712F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
-	{&it8712f_ops, IT8712F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},},
-	{&it8712f_ops, IT8712F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},},
-	{&it8712f_ops, IT8712F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},},
-	{&it8712f_ops, IT8712F_KBCM, 0, PNP_IRQ0,},
-	{&it8712f_ops, IT8712F_GPIO, 0, },
-	{&it8712f_ops, IT8712F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
-	{&it8712f_ops, IT8712F_GAME, 0, PNP_IO0, {0xfff, 0},},
-	{&it8712f_ops, IT8712F_IR, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
+				/* All resources needed by dev,  io_info_structs */
+	{&it8712f_ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},},
+	{&it8712f_ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
+	{&it8712f_ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
+	{&it8712f_ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},},
+	{&it8712f_ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},},
+	{&it8712f_ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},},
+	{&it8712f_ops, IT8712F_KBCM, PNP_IRQ0,},
+	{&it8712f_ops, IT8712F_GPIO, },
+	{&it8712f_ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
+	{&it8712f_ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},},
+	{&it8712f_ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
 };
 
 static void it8712f_setup_scan_bus(struct device *dev)
@@ -116,38 +116,38 @@
 	/* Floppy */
 	pnp_dev_info[IT8712F_FDC].enable = conf->floppyenable;
 	pnp_dev_info[IT8712F_FDC].io0.val = conf->floppyio;
-	pnp_dev_info[IT8712F_FDC].irq0.val = conf->floppyirq;
-	pnp_dev_info[IT8712F_FDC].drq0.val = conf->floppydrq;
+	pnp_dev_info[IT8712F_FDC].irq0 = conf->floppyirq;
+	pnp_dev_info[IT8712F_FDC].drq0 = conf->floppydrq;
 
 	/* COM1 */
 	pnp_dev_info[IT8712F_SP1].enable = conf->com1enable;
 	pnp_dev_info[IT8712F_SP1].io0.val = conf->com1io;
-	pnp_dev_info[IT8712F_SP1].irq0.val = conf->com1irq;
+	pnp_dev_info[IT8712F_SP1].irq0 = conf->com1irq;
 
 	/* COM2 */
 	pnp_dev_info[IT8712F_SP2].enable = conf->com2enable;
 	pnp_dev_info[IT8712F_SP2].io0.val = conf->com2io;
-	pnp_dev_info[IT8712F_SP2].irq0.val = conf->com2irq;
+	pnp_dev_info[IT8712F_SP2].irq0 = conf->com2irq;
 
 	/* Parallel port */
 	pnp_dev_info[IT8712F_PP].enable = conf->ppenable;
 	pnp_dev_info[IT8712F_PP].io0.val = conf->ppio;
-	pnp_dev_info[IT8712F_PP].irq0.val = conf->ppirq;
+	pnp_dev_info[IT8712F_PP].irq0 = conf->ppirq;
 
 	/* Environment controller */
 	pnp_dev_info[IT8712F_EC].enable = conf->ecenable;
 	pnp_dev_info[IT8712F_EC].io0.val = conf->ecio;
-	pnp_dev_info[IT8712F_EC].irq0.val = conf->ecirq;
+	pnp_dev_info[IT8712F_EC].irq0 = conf->ecirq;
 
 	/* Keyboard */
 	pnp_dev_info[IT8712F_KBCK].enable = conf->kbenable;
 	pnp_dev_info[IT8712F_KBCK].io0.val = conf->kbio;
 	pnp_dev_info[IT8712F_KBCK].io1.val = conf->kbio2;
-	pnp_dev_info[IT8712F_KBCK].irq0.val = conf->kbirq;
+	pnp_dev_info[IT8712F_KBCK].irq0 = conf->kbirq;
 
 	/* PS/2 mouse */
 	pnp_dev_info[IT8712F_KBCM].enable = conf->mouseenable;
-	pnp_dev_info[IT8712F_KBCM].irq0.val = conf->mouseirq;
+	pnp_dev_info[IT8712F_KBCM].irq0 = conf->mouseirq;
 
 	/* GPIO */
 	pnp_dev_info[IT8712F_GPIO].enable = conf->gpioenable;
@@ -155,7 +155,7 @@
 	/* MIDI port */
 	pnp_dev_info[IT8712F_MIDI].enable = conf->midienable;
 	pnp_dev_info[IT8712F_MIDI].io0.val = conf->midiio;
-	pnp_dev_info[IT8712F_MIDI].irq0.val = conf->midiirq;
+	pnp_dev_info[IT8712F_MIDI].irq0 = conf->midiirq;
 
 	/* Game port */
 	pnp_dev_info[IT8712F_GAME].enable = conf->gameenable;
@@ -164,7 +164,7 @@
 	/* Consumer IR */
 	pnp_dev_info[IT8712F_IR].enable = conf->cirenable;
 	pnp_dev_info[IT8712F_IR].io0.val = conf->cirio;
-	pnp_dev_info[IT8712F_IR].irq0.val = conf->cirirq;
+	pnp_dev_info[IT8712F_IR].irq0 = conf->cirirq;
 
 	/* Initialize SuperIO for PNP children. */
 	if (!dev->links) {

Modified: coreboot-v3/superio/ite/it8716f/superio.c
===================================================================
--- coreboot-v3/superio/ite/it8716f/superio.c	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/superio/ite/it8716f/superio.c	2008-12-08 20:40:02 UTC (rev 1066)
@@ -133,20 +133,20 @@
 };
 
 static struct pnp_info pnp_dev_info[] = {
-				/* Enable,  All resources need by dev,  io_info_structs */
-	{&it8716f_ops, IT8716F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
-	{&it8716f_ops, IT8716F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
-	{&it8716f_ops, IT8716F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
-	{&it8716f_ops, IT8716F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
-	{&it8716f_ops, IT8716F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
+				/* All resources needed by dev,  io_info_structs */
+	{&it8716f_ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
+	{&it8716f_ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
+	{&it8716f_ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
+	{&it8716f_ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
+	{&it8716f_ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
 	 {0x7f8, 0x4},},
-	{&it8716f_ops, IT8716F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
+	{&it8716f_ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
 	 {0x7ff, 0x4},},
-	{&it8716f_ops, IT8716F_KBCM, 0, PNP_IRQ0,},
-	{&it8716f_ops, IT8716F_GPIO, 0, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
-	{&it8716f_ops, IT8716F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
-	{&it8716f_ops, IT8716F_GAME, 0, PNP_IO0, {0x7ff, 0},},
-	{&it8716f_ops, IT8716F_IR, 0,},
+	{&it8716f_ops, IT8716F_KBCM, PNP_IRQ0,},
+	{&it8716f_ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
+	{&it8716f_ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
+	{&it8716f_ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
+	{&it8716f_ops, IT8716F_IR, },
 };
 
 static void it8716f_setup_scan_bus(struct device *dev)
@@ -156,38 +156,38 @@
 	/* Floppy */
 	pnp_dev_info[IT8716F_FDC].enable = conf->floppyenable;
 	pnp_dev_info[IT8716F_FDC].io0.val = conf->floppyio;
-	pnp_dev_info[IT8716F_FDC].irq0.val = conf->floppyirq;
-	pnp_dev_info[IT8716F_FDC].drq0.val = conf->floppydrq;
+	pnp_dev_info[IT8716F_FDC].irq0 = conf->floppyirq;
+	pnp_dev_info[IT8716F_FDC].drq0 = conf->floppydrq;
 
 	/* COM1 */
 	pnp_dev_info[IT8716F_SP1].enable = conf->com1enable;
 	pnp_dev_info[IT8716F_SP1].io0.val = conf->com1io;
-	pnp_dev_info[IT8716F_SP1].irq0.val = conf->com1irq;
+	pnp_dev_info[IT8716F_SP1].irq0 = conf->com1irq;
 
 	/* COM2 */
 	pnp_dev_info[IT8716F_SP2].enable = conf->com2enable;
 	pnp_dev_info[IT8716F_SP2].io0.val = conf->com2io;
-	pnp_dev_info[IT8716F_SP2].irq0.val = conf->com2irq;
+	pnp_dev_info[IT8716F_SP2].irq0 = conf->com2irq;
 
 	/* Parallel port */
 	pnp_dev_info[IT8716F_PP].enable = conf->ppenable;
 	pnp_dev_info[IT8716F_PP].io0.val = conf->ppio;
-	pnp_dev_info[IT8716F_PP].irq0.val = conf->ppirq;
+	pnp_dev_info[IT8716F_PP].irq0 = conf->ppirq;
 
 	/* Environment controller */
 	pnp_dev_info[IT8716F_EC].enable = conf->ecenable;
 	pnp_dev_info[IT8716F_EC].io0.val = conf->ecio;
-	pnp_dev_info[IT8716F_EC].irq0.val = conf->ecirq;
+	pnp_dev_info[IT8716F_EC].irq0 = conf->ecirq;
 
 	/* Keyboard */
 	pnp_dev_info[IT8716F_KBCK].enable = conf->kbenable;
 	pnp_dev_info[IT8716F_KBCK].io0.val = conf->kbio;
 	pnp_dev_info[IT8716F_KBCK].io1.val = conf->kbio2;
-	pnp_dev_info[IT8716F_KBCK].irq0.val = conf->kbirq;
+	pnp_dev_info[IT8716F_KBCK].irq0 = conf->kbirq;
 
 	/* PS/2 mouse */
 	pnp_dev_info[IT8716F_KBCM].enable = conf->mouseenable;
-	pnp_dev_info[IT8716F_KBCM].irq0.val = conf->mouseirq;
+	pnp_dev_info[IT8716F_KBCM].irq0 = conf->mouseirq;
 
 	/* GPIO */
 	pnp_dev_info[IT8716F_GPIO].enable = conf->gpioenable;
@@ -195,7 +195,7 @@
 	/* MIDI port */
 	pnp_dev_info[IT8716F_MIDI].enable = conf->midienable;
 	pnp_dev_info[IT8716F_MIDI].io0.val = conf->midiio;
-	pnp_dev_info[IT8716F_MIDI].irq0.val = conf->midiirq;
+	pnp_dev_info[IT8716F_MIDI].irq0 = conf->midiirq;
 
 	/* Game port */
 	pnp_dev_info[IT8716F_GAME].enable = conf->gameenable;
@@ -204,7 +204,7 @@
 	/* Consumer IR */
 	pnp_dev_info[IT8716F_IR].enable = conf->cirenable;
 	pnp_dev_info[IT8716F_IR].io0.val = conf->cirio;
-	pnp_dev_info[IT8716F_IR].irq0.val = conf->cirirq;
+	pnp_dev_info[IT8716F_IR].irq0 = conf->cirirq;
 
 	/* Initialize SuperIO for PNP children. */
 	if (!dev->links) {

Modified: coreboot-v3/superio/winbond/w83627hf/superio.c
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/superio.c	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/superio/winbond/w83627hf/superio.c	2008-12-08 20:40:02 UTC (rev 1066)
@@ -195,22 +195,21 @@
 };
 
 static struct pnp_info pnp_dev_info[] = {
-				/* Enable,  All resources need by dev,  io_info_structs */
-	{ &w83627hf_ops, W83627HF_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &w83627hf_ops, W83627HF_PP, 0,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &w83627hf_ops, W83627HF_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &w83627hf_ops, W83627HF_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ 0,},
-	{ &w83627hf_ops, W83627HF_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
-	{ &w83627hf_ops, W83627HF_CIR, 0,PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, 0,PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
-	{ &w83627hf_ops, W83627HF_GPIO2, 0 },
-	{ &w83627hf_ops, W83627HF_GPIO3, 0 },
-	{ &w83627hf_ops, W83627HF_ACPI, 0 },
-	{ &w83627hf_ops, W83627HF_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+		/* Ops, function #, All resources needed by dev,  io_info_structs */
+	{ &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ 0, }, /* No function 4. */
+	{ &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
+	{ &w83627hf_ops, W83627HF_GPIO2, },
+	{ &w83627hf_ops, W83627HF_GPIO3, },
+	{ &w83627hf_ops, W83627HF_ACPI, },
+	{ &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
 };
 
-
 static void phase3_chip_setup_dev(struct device *dev)
 {
 	/* Get dts values and populate pnp_dev_info. */
@@ -219,30 +218,30 @@
 	/* Floppy */
 	pnp_dev_info[W83627HF_FDC].enable = conf->floppyenable;
 	pnp_dev_info[W83627HF_FDC].io0.val = conf->floppyio;
-	pnp_dev_info[W83627HF_FDC].irq0.val = conf->floppyirq;
-	pnp_dev_info[W83627HF_FDC].drq0.val = conf->floppydrq;
+	pnp_dev_info[W83627HF_FDC].irq0 = conf->floppyirq;
+	pnp_dev_info[W83627HF_FDC].drq0 = conf->floppydrq;
 
 	/* Parallel port */
 	pnp_dev_info[W83627HF_PP].enable = conf->ppenable;
 	pnp_dev_info[W83627HF_PP].io0.val = conf->ppio;
-	pnp_dev_info[W83627HF_PP].irq0.val = conf->ppirq;
+	pnp_dev_info[W83627HF_PP].irq0 = conf->ppirq;
 
 	/* COM1 */
 	pnp_dev_info[W83627HF_SP1].enable = conf->com1enable;
 	pnp_dev_info[W83627HF_SP1].io0.val = conf->com1io;
-	pnp_dev_info[W83627HF_SP1].irq0.val = conf->com1irq;
+	pnp_dev_info[W83627HF_SP1].irq0 = conf->com1irq;
 
 	/* COM2 */
 	pnp_dev_info[W83627HF_SP2].enable = conf->com2enable;
 	pnp_dev_info[W83627HF_SP2].io0.val = conf->com2io;
-	pnp_dev_info[W83627HF_SP2].irq0.val = conf->com2irq;
+	pnp_dev_info[W83627HF_SP2].irq0 = conf->com2irq;
 
 	/* Keyboard */
 	pnp_dev_info[W83627HF_KBC].enable = conf->kbenable;
 	pnp_dev_info[W83627HF_KBC].io0.val = conf->kbio;
 	pnp_dev_info[W83627HF_KBC].io1.val = conf->kbio2;
-	pnp_dev_info[W83627HF_KBC].irq0.val = conf->kbirq;
-	pnp_dev_info[W83627HF_KBC].irq1.val = conf->kbirq2;
+	pnp_dev_info[W83627HF_KBC].irq0 = conf->kbirq;
+	pnp_dev_info[W83627HF_KBC].irq1 = conf->kbirq2;
 
 	/* Consumer IR */
 	pnp_dev_info[W83627HF_CIR].enable = conf->cirenable;
@@ -251,7 +250,7 @@
 	pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].enable = conf->gameenable;
 	pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].io0.val = conf->gameio;
 	pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].io1.val = conf->gameio2;
-	pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].irq0.val = conf->gameirq;
+	pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].irq0 = conf->gameirq;
 
 	/* GPIO2 */
 	pnp_dev_info[W83627HF_GPIO2].enable = conf->gpio2enable;
@@ -265,7 +264,7 @@
 	/* Hardware Monitor */
 	pnp_dev_info[W83627HF_HWM].enable = conf->hwmenable;
 	pnp_dev_info[W83627HF_HWM].io0.val = conf->hwmio;
-	pnp_dev_info[W83627HF_HWM].irq0.val = conf->hwmirq;
+	pnp_dev_info[W83627HF_HWM].irq0 = conf->hwmirq;
 
 	/* Initialize SuperIO for PNP children. */
 	if (!dev->links) {
@@ -275,7 +274,6 @@
 		dev->link[0].link = 0;
 	}
 
-	/* Call init with updated tables to create children. */
+	/* Call init with updated tables to create and enable children. */
 	pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
-

Modified: coreboot-v3/superio/winbond/w83627thg/dts
===================================================================
--- coreboot-v3/superio/winbond/w83627thg/dts	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/superio/winbond/w83627thg/dts	2008-12-08 20:40:02 UTC (rev 1066)
@@ -24,33 +24,28 @@
 	/* To override any of these, put the over-ride in mainboard dts. */
 
 	/* Floppy */
-	floppydev = "0";
 	floppyenable = "0";
 	floppyio = "0x3f0";
 	floppyirq = "6";
 	floppydrq = "2";
 
 	/* Parallel port */
-	ppdev = "1";
 	ppenable = "0";
 	ppio = "0x378";
 	ppirq = "7";
 	ppdrq = "4";
 
 	/* COM1 */
-	com1dev = "2";
 	com1enable = "0";
 	com1io = "0x3f8";
 	com1irq = "4";
 
 	/* COM2 */
-	com2dev = "3";
 	com2enable = "0";
 	com2io = "0x2f8";
 	com2irq = "3";
 
 	/* PS/2 keyboard + PS/2 mouse */
-	kbdev = "5";
 	kbenable = "0";
 	kbio = "0x60";
 	kbio2 = "0x64";
@@ -58,26 +53,21 @@
 	kbirq2 = "12";
 
 	/* Game port, MIDI port, GPIO1, GPIO5 */
-	gamedev = "7";
 	gameenable = "0";
 	gameio = "0x201";
 	gameio2 = "0x330";
 	gameirq = "9";
 
 	/* GPIO2 */
-	gpio2dev = "8";
 	gpio2enable = "0";
 
 	/* GPIO3, GPIO4 */
-	gpio34dev = "9";
 	gpio34enable = "0";
 
 	/* ACPI */
-	acpidev = "10";
 	acpienable = "0";
 
 	/* Hardware Monitor */
-	hwmdev = "11";
 	hwmenable = "0";
 	hwmio = "0x290";
 	hwmirq = "5";

Modified: coreboot-v3/superio/winbond/w83627thg/superio.c
===================================================================
--- coreboot-v3/superio/winbond/w83627thg/superio.c	2008-12-06 03:59:24 UTC (rev 1065)
+++ coreboot-v3/superio/winbond/w83627thg/superio.c	2008-12-08 20:40:02 UTC (rev 1066)
@@ -1,9 +1,9 @@
 /*
  * This file is part of the coreboot project.
  *
- *  Copyright 2000  AG Electronics Ltd.
+ * Copyright 2000 AG Electronics Ltd.
  * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan 
+ * Copyright 2004 Tyan
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -25,10 +25,8 @@
 #include <device/pnp.h>
 #include <console.h>
 #include <string.h>
-//#include <bitops.h>
 #include <uart8250.h>
 #include <keyboard.h>
-// #include <pc80/mc146818rtc.h>
 #include <statictree.h>
 #include "w83627thg.h"
 
@@ -93,17 +91,19 @@
 
 /* TODO: this device is not at all filled out. Just copied from v2. */
 static struct pnp_info pnp_dev_info[] = {
-        { &w83627thg_ops, W83627THG_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &w83627thg_ops, W83627THG_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &w83627thg_ops, W83627THG_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &w83627thg_ops, W83627THG_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        // No 4 { 0,},
-        { &w83627thg_ops, W83627THG_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
-        { &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
-        { &w83627thg_ops, W83627THG_GPIO2,},
-        { &w83627thg_ops, W83627THG_GPIO3,},
-        { &w83627thg_ops, W83627THG_ACPI, 0, PNP_IRQ0,  },
-        { &w83627thg_ops, W83627THG_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
+		/* Ops, function #, All resources needed by dev,  io_info_structs */
+	{ &w83627thg_ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &w83627thg_ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &w83627thg_ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &w83627thg_ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ 0, }, /* No function 4. */
+	{ &w83627thg_ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ 0, }, /* No function 6. */
+	{ &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
+	{ &w83627thg_ops, W83627THG_GPIO2, },
+	{ &w83627thg_ops, W83627THG_GPIO3, },
+	{ &w83627thg_ops, W83627THG_ACPI, },
+	{ &w83627thg_ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
 };
 
 static void phase3_chip_setup_dev(struct device *dev)
@@ -111,33 +111,45 @@
 	/* Get dts values and populate pnp_dev_info. */
 	const struct superio_winbond_w83627thg_dts_config * const conf = dev->device_configuration;
 
-#if 0 
-These are not set up at all v2. Ignore for now. */
 	/* Floppy */
 	pnp_dev_info[W83627THG_FDC].enable = conf->floppyenable;
 	pnp_dev_info[W83627THG_FDC].io0.val = conf->floppyio;
-	pnp_dev_info[W83627THG_FDC].irq0.val = conf->floppyirq;
-	pnp_dev_info[W83627THG_FDC].drq0.val = conf->floppydrq;
+	pnp_dev_info[W83627THG_FDC].irq0 = conf->floppyirq;
+	pnp_dev_info[W83627THG_FDC].drq0 = conf->floppydrq;
 
 	/* Parallel port */
 	pnp_dev_info[W83627THG_PP].enable = conf->ppenable;
 	pnp_dev_info[W83627THG_PP].io0.val = conf->ppio;
-	pnp_dev_info[W83627THG_PP].irq0.val = conf->ppirq;
+	pnp_dev_info[W83627THG_PP].irq0 = conf->ppirq;
 
-	/* Consumer IR */
-	pnp_dev_info[W83627THG_CIR].enable = conf->cirenable;
+	/* COM1 */
+	pnp_dev_info[W83627THG_SP1].enable = conf->com1enable;
+	pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io;
+	pnp_dev_info[W83627THG_SP1].irq0 = conf->com1irq;
 
+	/* COM2 */
+	pnp_dev_info[W83627THG_SP2].enable = conf->com2enable;
+	pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io;
+	pnp_dev_info[W83627THG_SP2].irq0 = conf->com2irq;
+
+	/* Keyboard */
+	pnp_dev_info[W83627THG_KBC].enable = conf->kbenable;
+	pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio;
+	pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2;
+	pnp_dev_info[W83627THG_KBC].irq0 = conf->kbirq;
+	pnp_dev_info[W83627THG_KBC].irq1 = conf->kbirq2;
+
 	/* Game port */
 	pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].enable = conf->gameenable;
 	pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io0.val = conf->gameio;
 	pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io1.val = conf->gameio2;
-	pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0.val = conf->gameirq;
+	pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0 = conf->gameirq;
 
 	/* GPIO2 */
 	pnp_dev_info[W83627THG_GPIO2].enable = conf->gpio2enable;
 
-	/* GPIO3 */
-	pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio3enable;
+	/* GPIO3, GPIO4 */
+	pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio34enable;
 
 	/* ACPI */
 	pnp_dev_info[W83627THG_ACPI].enable = conf->acpienable;
@@ -145,27 +157,8 @@
 	/* Hardware Monitor */
 	pnp_dev_info[W83627THG_HWM].enable = conf->hwmenable;
 	pnp_dev_info[W83627THG_HWM].io0.val = conf->hwmio;
-	pnp_dev_info[W83627THG_HWM].irq0.val = conf->hwmirq;
+	pnp_dev_info[W83627THG_HWM].irq0 = conf->hwmirq;
 
-#endif
-
-	/* COM1 */
-	pnp_dev_info[W83627THG_SP1].enable = conf->com1enable;
-	pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io;
-	pnp_dev_info[W83627THG_SP1].irq0.val = conf->com1irq;
-
-	/* COM2 */
-	pnp_dev_info[W83627THG_SP2].enable = conf->com2enable;
-	pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io;
-	pnp_dev_info[W83627THG_SP2].irq0.val = conf->com2irq;
-
-	/* Keyboard */
-	pnp_dev_info[W83627THG_KBC].enable = conf->kbenable;
-	pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio;
-	pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2;
-	pnp_dev_info[W83627THG_KBC].irq0.val = conf->kbirq;
-	pnp_dev_info[W83627THG_KBC].irq1.val = conf->kbirq2;
-
 	/* Initialize SuperIO for PNP children. */
 	if (!dev->links) {
 		dev->links = 1;
@@ -174,6 +167,6 @@
 		dev->link[0].link = 0;
 	}
 
-	/* Call init with updated tables to create children. */
+	/* Call init with updated tables to create and enable children. */
 	pnp_enable_devices(dev, &w83627thg_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }




From mylesgw at gmail.com  Mon Dec  8 21:43:15 2008
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 8 Dec 2008 13:43:15 -0700
Subject: [coreboot] PNP fixes
In-Reply-To: <13426df10812081226s3a7ab628i6d29d0864387faed@mail.gmail.com>
References: <2831fecf0812081020t62bd54ddl6471cec89493647@mail.gmail.com>
	<2831fecf0812081113r52a04650w9717772d2778aa43@mail.gmail.com>
	<2831fecf0812081115tddc9f42o24b9a78955357fbe@mail.gmail.com>
	<13426df10812081226s3a7ab628i6d29d0864387faed@mail.gmail.com>
Message-ID: <2831fecf0812081243v456e77bp18efd8e2f15e9a47@mail.gmail.com>

On Mon, Dec 8, 2008 at 1:26 PM, ron minnich <rminnich at gmail.com> wrote:

> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>


Rev 1066.
Thanks,
Myles
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From tiagomnm at gmail.com  Tue Dec  9 00:30:16 2008
From: tiagomnm at gmail.com (Tiago Marques)
Date: Mon, 8 Dec 2008 23:30:16 +0000
Subject: [coreboot] Interesting (part of) article.
In-Reply-To: <493C47DB.2060808@gmx.net>
References: <493C22BB.7040402@min-epost.net> <493C47DB.2060808@gmx.net>
Message-ID: <b1335fe90812081530i7fab3261mf74af5c37487fd06@mail.gmail.com>

I've spoken with some people at Anandtech, at least Derek Wilson was a very
helpful person.
If you need any help contacting them, please do say so.
Best regards,
                        Tiago Marques


On Sun, Dec 7, 2008 at 10:02 PM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Hi Peter,
>
> thanks for the heads-up.
>
> Ron, do you want to write to Anandtech to tell them about coreboot?
>
> Regards,
> Carl-Daniel
>
> On 07.12.2008 20:23, pk wrote:
> > Hi,
> >
> > Don't know if this is of any interest but I think the first part ("BIOS
> > Ridiculousness...") relates somewhat of what you are trying to
> > accomplish here. There really should be more interest from motherboard
> > manufacturers in coreboot than there are...
> >
> > http://anandtech.com/mb/showdoc.aspx?i=3471
> >
> > Best regards
> >
> > Peter Karlsson
> >
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From r.marek at assembler.cz  Tue Dec  9 00:35:30 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 09 Dec 2008 00:35:30 +0100
Subject: [coreboot] Windows XP and Coreboot + SeaBIOS
Message-ID: <493DAF42.9000909@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello,

I started to hack to make SeaBIOS boot Windows XP and of course its installer.
The patch attached fixes some stuff already noticed by Kevin (FACP align, wrong
total size). And it adds some dynamic _CRS calculation in AML code. It uses SSDT
table with IO resources. For some reason this does not work, but resource hack
allows to boot Windows ACPI hal installer. I won't have much time to continue
with this week or so (maybe more...).

The idea is to let the PCI CRS resource to be calculated dynamically. The CRS
resource for host bridge is needed for Windows. Some ideas are described here:
http://www.acpi.info/acpi_faq.htm How is it done? Coreboot amd-acpi.c reads all
IO resource registers and put them into SSDT table. The AML code in
amdk8_util.asl should construct the IO resource containers which will be
returned concatenated with BUF0. As I stated above, it ends with 0xA5 STOP.
There is some problem somewhere, but once it is fixed, windows should work ;)

Rudolf
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From rminnich at gmail.com  Tue Dec  9 00:46:09 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 8 Dec 2008 15:46:09 -0800
Subject: [coreboot] Interesting (part of) article.
In-Reply-To: <b1335fe90812081530i7fab3261mf74af5c37487fd06@mail.gmail.com>
References: <493C22BB.7040402@min-epost.net> <493C47DB.2060808@gmx.net>
	<b1335fe90812081530i7fab3261mf74af5c37487fd06@mail.gmail.com>
Message-ID: <13426df10812081546u535769ds2656ca10903a92e5@mail.gmail.com>

Why don't we try to talk about anandtech about the ways coreboot would
help solve the problems they are wasting time on.

ron



From svn at coreboot.org  Tue Dec  9 00:51:46 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  9 Dec 2008 00:51:46 +0100
Subject: [coreboot] r3806 - trunk/util/flashrom
Message-ID: <mailman.2559.1355071450.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-12-09 00:51:45 +0100 (Tue, 09 Dec 2008)
New Revision: 3806

Modified:
   trunk/util/flashrom/flashchips.c
Log:
Kill obsolete and misplaced comment.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/util/flashrom/flashchips.c
===================================================================
--- trunk/util/flashrom/flashchips.c	2008-12-08 18:16:58 UTC (rev 3805)
+++ trunk/util/flashrom/flashchips.c	2008-12-08 23:51:45 UTC (rev 3806)
@@ -576,7 +576,7 @@
 	 512, 4096,
 	 TEST_OK_PROBE,
 	 probe_jedec, erase_chip_jedec, write_39sf020
-	}, /* assume similar to 004B, ignoring data sheet */
+	},
 
 	{"SST", "SST49LF002A/B", SST_ID, SST_49LF002A,
 	 256, 16 * 1024,




From r.marek at assembler.cz  Tue Dec  9 01:04:18 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 09 Dec 2008 01:04:18 +0100
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <20081130014525.GA4886@morn.localdomain>
References: <492B35A4.2010307@assembler.cz>
	<20081130014525.GA4886@morn.localdomain>
Message-ID: <493DB602.4050606@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

> Can you do a "git pull" of SeaBIOS and retry?

Yes  I did. I want to report success with a SAS card. At least now it goes
through it. I can even enter the card setup. This is much better then with
legacy BIOS, it will just HANG ;)

Great work! Thanks. I will test with some real HDD connected in some point in
the future.

Rudolf
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From rminnich at gmail.com  Tue Dec  9 01:12:29 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 8 Dec 2008 16:12:29 -0800
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <493DB602.4050606@assembler.cz>
References: <492B35A4.2010307@assembler.cz>
	<20081130014525.GA4886@morn.localdomain>
	<493DB602.4050606@assembler.cz>
Message-ID: <13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>

can someone start accumulating these "works with seabios/doesn't work
with factory BIOS" examples? I'm working up a talk for SCALE feb. 22
and would love to have some slides on just this issue.

BTW, we have a table at SCALE! I'd love to have as many of you there
as can make it.

thanks

ron



From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  9 01:41:25 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 09 Dec 2008 01:41:25 +0100
Subject: [coreboot] [PATCH] flashrom: Group probe function together with
	associated IDs
Message-ID: <493DBEB5.3070800@gmx.net>

The flash probe function and the IDs for that specific probe function
belong together. Group them together on a single line.
We already have chips with multiple probe functions and multiple IDs.
This patch is the first step in consolidating the present way of
creating a new chip definition for each ID of a given chip into multiple
IDs per chip definition.

Attached for Gmail users.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-reorderfields/flash.h
===================================================================
--- flashrom-reorderfields/flash.h	(Revision 3805)
+++ flashrom-reorderfields/flash.h	(Arbeitskopie)
@@ -60,6 +60,7 @@
 struct flashchip {
 	const char *vendor;
 	const char *name;
+
 	/*
 	 * With 32bit manufacture_id and model_id we can cover IDs up to
 	 * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
@@ -67,6 +68,7 @@
 	 */
 	uint32_t manufacture_id;
 	uint32_t model_id;
+	int (*probe) (struct flashchip *flash);
 
 	int total_size;
 	int page_size;
@@ -77,7 +79,6 @@
 	 */
 	uint32_t tested;
 
-	int (*probe) (struct flashchip *flash);
 	int (*erase) (struct flashchip *flash);
 	int (*write) (struct flashchip *flash, uint8_t *buf);
 	int (*read) (struct flashchip *flash, uint8_t *buf);
Index: flashrom-reorderfields/flashchips.c
===================================================================
--- flashrom-reorderfields/flashchips.c	(Revision 3805)
+++ flashrom-reorderfields/flashchips.c	(Arbeitskopie)
@@ -30,942 +30,1097 @@
  */
 struct flashchip flashchips[] = {
 
-	/* Vendor, Chip, Vendor ID, Chip ID,
+	/* Vendor, Chip,
+	 * Vendor ID, Chip ID, Probe function,
 	 * Total size (kB), Page size (B),
 	 * Test status,
-	 * Probe function, Erase function, Write function, Read function
+	 * Erase function, Write function, Read function
 	 */
 
-	{"AMD", "Am29F002(N)BB", AMD_ID, AM_29F002BB,
+	{"AMD", "Am29F002(N)BB",
+	 AMD_ID, AM_29F002BB, probe_jedec,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_en29f002a
+	 erase_chip_jedec, write_en29f002a 
 	},
 
-	{"AMD", "Am29F002(N)BT", AMD_ID, AM_29F002BT,
+	{"AMD", "Am29F002(N)BT",
+	 AMD_ID, AM_29F002BT, probe_jedec,
 	 256, 256,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_en29f002a
+	 erase_chip_jedec, write_en29f002a 
 	},
 
-	{"AMD", "Am29F016D", AMD_ID, AM_29F016D,
+	{"AMD", "Am29F016D",
+	 AMD_ID, AM_29F016D, probe_29f040b,
 	 2048, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_29f040b, erase_29f040b, write_29f040b
+	 erase_29f040b, write_29f040b 
 	},
 
-	{"AMD", "Am29F040B", AMD_ID, AM_29F040B,
+	{"AMD", "Am29F040B",
+	 AMD_ID, AM_29F040B, probe_29f040b,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_29f040b, erase_29f040b, write_29f040b
+	 erase_29f040b, write_29f040b 
 	},
 
-	{"AMD", "Am29LV040B", AMD_ID, AM_29LV040B,
+	{"AMD", "Am29LV040B",
+	 AMD_ID, AM_29LV040B, probe_29f040b,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_29f040b, erase_29f040b, write_29f040b
+	 erase_29f040b, write_29f040b 
 	},
 
-	{"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008,
+	{"ASD", "AE49F2008",
+	 ASD_ID, ASD_AE49F2008, probe_jedec,
 	 256, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"Atmel", "AT25DF021", ATMEL_ID, AT_25DF021,
+	{"Atmel", "AT25DF021",
+	 ATMEL_ID, AT_25DF021, probe_spi_rdid,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25DF041A", ATMEL_ID, AT_25DF041A,
+	{"Atmel", "AT25DF041A",
+	 ATMEL_ID, AT_25DF041A, probe_spi_rdid,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25DF081", ATMEL_ID, AT_25DF081,
+	{"Atmel", "AT25DF081",
+	 ATMEL_ID, AT_25DF081, probe_spi_rdid,
 	 1024, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25DF161", ATMEL_ID, AT_25DF161,
+	{"Atmel", "AT25DF161",
+	 ATMEL_ID, AT_25DF161, probe_spi_rdid,
 	 2048, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321,
+	{"Atmel", "AT25DF321",
+	 ATMEL_ID, AT_25DF321, probe_spi_rdid,
 	 4096, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Atmel", "AT25DF321A", ATMEL_ID, AT_25DF321A,
+	{"Atmel", "AT25DF321A",
+	 ATMEL_ID, AT_25DF321A, probe_spi_rdid,
 	 4096, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25DF641", ATMEL_ID, AT_25DF641,
+	{"Atmel", "AT25DF641",
+	 ATMEL_ID, AT_25DF641, probe_spi_rdid,
 	 8192, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25F512B", ATMEL_ID, AT_25F512B,
+	{"Atmel", "AT25F512B",
+	 ATMEL_ID, AT_25F512B, probe_spi_rdid,
 	 64, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25FS010", ATMEL_ID, AT_25FS010,
+	{"Atmel", "AT25FS010",
+	 ATMEL_ID, AT_25FS010, probe_spi_rdid,
 	 128, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT25FS040", ATMEL_ID, AT_25FS040,
+	{"Atmel", "AT25FS040",
+	 ATMEL_ID, AT_25FS040, probe_spi_rdid,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT26DF041", ATMEL_ID, AT_26DF041,
+	{"Atmel", "AT26DF041",
+	 ATMEL_ID, AT_26DF041, probe_spi_rdid,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read
+	 NULL, NULL /* Incompatible Page write */,spi_chip_read 
 	},
 
-	{"Atmel", "AT26DF081A", ATMEL_ID, AT_26DF081A,
+	{"Atmel", "AT26DF081A",
+	 ATMEL_ID, AT_26DF081A, probe_spi_rdid,
 	 1024, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT26DF161", ATMEL_ID, AT_26DF161,
+	{"Atmel", "AT26DF161",
+	 ATMEL_ID, AT_26DF161, probe_spi_rdid,
 	 2048, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
-	{"Atmel", "AT26DF161A", ATMEL_ID, AT_26DF161A,
+	{"Atmel", "AT26DF161A",
+	 ATMEL_ID, AT_26DF161A, probe_spi_rdid,
 	 2048, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL, spi_chip_read
+	 NULL, NULL, spi_chip_read 
 	},
 
 	/*The AT26DF321 has the same ID as the AT25DF321. */
-	/*{"Atmel", "AT26DF321", ATMEL_ID, AT_26DF321,
-	  4096, 256,
-	  TEST_UNTESTED,
-	  probe_spi_rdid, NULL, NULL, spi_chip_read
-	  },
-	*/
+	/*{"Atmel", "AT26DF321",
+	 ATMEL_ID, AT_26DF321, probe_spi_rdid,
+	 4096, 256,
+	 TEST_UNTESTED,
+	 NULL, NULL, spi_chip_read 
+	}, */
 
-	{"Atmel", "AT26F004", ATMEL_ID, AT_26F004,
+	{"Atmel", "AT26F004",
+	 ATMEL_ID, AT_26F004, probe_spi_rdid,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL /* Incompatible Page write */,spi_chip_read
+	 NULL, NULL /* Incompatible Page write */,spi_chip_read 
 	},
 
-	{"Atmel", "AT29C020", ATMEL_ID, AT_29C020,
+	{"Atmel", "AT29C020",
+	 ATMEL_ID, AT_29C020, probe_jedec,
 	 256, 256,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A,
+	{"Atmel", "AT29C040A",
+	 ATMEL_ID, AT_29C040A, probe_jedec,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"Atmel", "AT45CS1282", ATMEL_ID, AT_45CS1282,
+	{"Atmel", "AT45CS1282",
+	 ATMEL_ID, AT_45CS1282, probe_spi_rdid,
 	 16896/*!*/, 1056/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */
+	 NULL, NULL /* Incompatible Page write */, NULL /* Incompatible read */ 
 	}, /* No power of two sizes */
 
-	{"Atmel", "AT45DB011D", ATMEL_ID, AT_45DB011D,
+	{"Atmel", "AT45DB011D",
+	 ATMEL_ID, AT_45DB011D, probe_spi_rdid,
 	 128/*!*/, 256/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL
+	 NULL, NULL, NULL 
 	}, /* Size can only be determined from status register */
 
-	{"Atmel", "AT45DB021D", ATMEL_ID, AT_45DB021D,
+	{"Atmel", "AT45DB021D",
+	 ATMEL_ID, AT_45DB021D, probe_spi_rdid,
 	 256/*!*/, 256/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL
+	 NULL, NULL, NULL 
 	}, /* Size can only be determined from status register */
 
-	{"Atmel", "AT45DB041D", ATMEL_ID, AT_45DB041D,
+	{"Atmel", "AT45DB041D",
+	 ATMEL_ID, AT_45DB041D, probe_spi_rdid,
 	 512/*!*/, 256/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL
+	 NULL, NULL, NULL 
 	}, /* Size can only be determined from status register */
 
-	{"Atmel", "AT45DB081D", ATMEL_ID, AT_45DB081D,
+	{"Atmel", "AT45DB081D",
+	 ATMEL_ID, AT_45DB081D, probe_spi_rdid,
 	 1024/*!*/, 256/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL
+	 NULL, NULL, NULL 
 	}, /* Size can only be determined from status register */
 
-	{"Atmel", "AT45DB161D", ATMEL_ID, AT_45DB161D,
+	{"Atmel", "AT45DB161D",
+	 ATMEL_ID, AT_45DB161D, probe_spi_rdid,
 	 2048/*!*/, 512/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL
+	 NULL, NULL, NULL 
 	}, /* Size can only be determined from status register */
 
-	{"Atmel", "AT45DB321C", ATMEL_ID, AT_45DB321C,
+	{"Atmel", "AT45DB321C",
+	 ATMEL_ID, AT_45DB321C, probe_spi_rdid,
 	 4224/*!*/, 528/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL /* Incompatible read */
+	 NULL, NULL, NULL /* Incompatible read */ 
 	}, /* No power of two sizes */
 
-	{"Atmel", "AT45DB321D", ATMEL_ID, AT_45DB321D,
+	{"Atmel", "AT45DB321D",
+	 ATMEL_ID, AT_45DB321D, probe_spi_rdid,
 	 4096/*!*/, 512/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL
+	 NULL, NULL, NULL 
 	}, /* Size can only be determined from status register */
 
-	{"Atmel", "AT45DB642D", ATMEL_ID, AT_45DB642D,
+	{"Atmel", "AT45DB642D",
+	 ATMEL_ID, AT_45DB642D, probe_spi_rdid,
 	 8192/*!*/, 1024/*!*/,
 	 TEST_BAD_READ,
-	 probe_spi_rdid, NULL, NULL, NULL
+	 NULL, NULL, NULL 
 	}, /* Size can only be determined from status register */
 
-	{"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N,
+	{"Atmel", "AT49F002(N)",
+	 ATMEL_ID, AT_49F002N, probe_jedec,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT,
+	{"Atmel", "AT49F002(N)T",
+	 ATMEL_ID, AT_49F002NT, probe_jedec,
 	 256, 256,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P,
+	{"AMIC", "A25L40P",
+	 AMIC_ID, AMIC_A25L40P, probe_spi_rdid4,
 	 512, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B,
+	{"AMIC", "A29002B",
+	 AMIC_ID_NOPREFIX, AMIC_A29002B, probe_29f002,
 	 256, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_29f002, erase_29f002, write_29f002
+	 erase_29f002, write_29f002 
 	},
 
-	{"AMIC", "A29002T", AMIC_ID_NOPREFIX, AMIC_A29002T,
+	{"AMIC", "A29002T",
+	 AMIC_ID_NOPREFIX, AMIC_A29002T, probe_29f002,
 	 256, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_29f002, erase_29f002, write_29f002
+	 erase_29f002, write_29f002 
 	},
 
-	{"AMIC", "A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B,
+	{"AMIC", "A29040B",
+	 AMIC_ID_NOPREFIX, AMIC_A29040B, probe_29f040b,
 	 512, 64 * 1024,
 	 TEST_OK_PR,
-	 probe_29f040b, erase_29f040b, write_29f040b
+	 erase_29f040b, write_29f040b 
 	},
 
-	{"AMIC", "A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A,
+	{"AMIC", "A49LF040A",
+	 AMIC_ID_NOPREFIX, AMIC_A49LF040A, probe_49fl00x,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_49fl00x, erase_49fl00x, write_49fl00x
+	 erase_49fl00x, write_49fl00x 
 	},
 
-	{"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA,
+	{"EMST", "F49B002UA",
+	 EMST_ID, EMST_F49B002UA, probe_jedec,
 	 256, 4096,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B,
+	{"EON", "EN29F002(A)(N)B",
+	 EON_ID, EN_29F002B, probe_jedec,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_en29f002a
+	 erase_chip_jedec, write_en29f002a 
 	},
 
-	{"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T,
+	{"EON", "EN29F002(A)(N)T",
+	 EON_ID, EN_29F002T, probe_jedec,
 	 256, 256,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_en29f002a
+	 erase_chip_jedec, write_en29f002a 
 	},
 
-	{"Fujitsu", "MBM29F004BC", FUJITSU_ID, MBM29F004BC,
+	{"Fujitsu", "MBM29F004BC",
+	 FUJITSU_ID, MBM29F004BC, probe_jedec,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"Fujitsu", "MBM29F004TC", FUJITSU_ID, MBM29F004TC,
+	{"Fujitsu", "MBM29F004TC",
+	 FUJITSU_ID, MBM29F004TC, probe_jedec,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"Fujitsu", "MBM29F400BC", FUJITSU_ID, MBM29F400BC,
+	{"Fujitsu", "MBM29F400BC",
+	 FUJITSU_ID, MBM29F400BC, probe_m29f400bt,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt
+	 erase_m29f400bt, write_coreboot_m29f400bt 
 	},
 
-	{"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC,
+	{"Fujitsu", "MBM29F400TC",
+	 FUJITSU_ID, MBM29F400TC, probe_m29f400bt,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt
+	 erase_m29f400bt, write_coreboot_m29f400bt 
 	},
 
-	{"Intel", "82802AB", INTEL_ID, 173,
+	{"Intel", "82802AB",
+	 INTEL_ID, 173, probe_82802ab,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_82802ab, erase_82802ab, write_82802ab
+	 erase_82802ab, write_82802ab 
 	},
 
-	{"Intel", "82802AC", INTEL_ID, 172,
+	{"Intel", "82802AC",
+	 INTEL_ID, 172, probe_82802ab,
 	 1024, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_82802ab, erase_82802ab, write_82802ab
+	 erase_82802ab, write_82802ab 
 	},
 
-	{"Macronix", "MX25L512", MX_ID, MX_25L512,
+	{"Macronix", "MX25L512",
+	 MX_ID, MX_25L512, probe_spi_rdid,
 	 64, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX25L1005", MX_ID, MX_25L1005,
+	{"Macronix", "MX25L1005",
+	 MX_ID, MX_25L1005, probe_spi_rdid,
 	 128, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX25L2005", MX_ID, MX_25L2005,
+	{"Macronix", "MX25L2005",
+	 MX_ID, MX_25L2005, probe_spi_rdid,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX25L4005", MX_ID, MX_25L4005,
+	{"Macronix", "MX25L4005",
+	 MX_ID, MX_25L4005, probe_spi_rdid,
 	 512, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX25L8005", MX_ID, MX_25L8005,
+	{"Macronix", "MX25L8005",
+	 MX_ID, MX_25L8005, probe_spi_rdid,
 	 1024, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX25L1605", MX_ID, MX_25L1605,
+	{"Macronix", "MX25L1605",
+	 MX_ID, MX_25L1605, probe_spi_rdid,
 	 2048, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX25L3205", MX_ID, MX_25L3205,
+	{"Macronix", "MX25L3205",
+	 MX_ID, MX_25L3205, probe_spi_rdid,
 	 4096, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX25L6405", MX_ID, MX_25L6405,
+	{"Macronix", "MX25L6405",
+	 MX_ID, MX_25L6405, probe_spi_rdid,
 	 8192, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Macronix", "MX29F002B", MX_ID, MX_29F002B,
+	{"Macronix", "MX29F002B",
+	 MX_ID, MX_29F002B, probe_29f002,
 	 256, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_29f002, erase_29f002, write_29f002
+	 erase_29f002, write_29f002 
 	},
 
-	{"Macronix", "MX29F002T", MX_ID, MX_29F002T,
+	{"Macronix", "MX29F002T",
+	 MX_ID, MX_29F002T, probe_29f002,
 	 256, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_29f002, erase_29f002, write_29f002
+	 erase_29f002, write_29f002 
 	},
 
-	{"Numonyx", "M25PE10", ST_ID, 0x8011,
+	{"Numonyx", "M25PE10",
+	 ST_ID, 0x8011, probe_spi_rdid,
 	 128, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	 spi_chip_erase_d8, spi_chip_write, spi_chip_read 
 	},
 
-	{"Numonyx", "M25PE20", ST_ID, 0x8012,
+	{"Numonyx", "M25PE20",
+	 ST_ID, 0x8012, probe_spi_rdid,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	 spi_chip_erase_d8, spi_chip_write, spi_chip_read 
 	},
 
-	{"Numonyx", "M25PE40", ST_ID, 0x8013,
+	{"Numonyx", "M25PE40",
+	 ST_ID, 0x8013, probe_spi_rdid,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	 spi_chip_erase_d8, spi_chip_write, spi_chip_read 
 	},
 
-	{"Numonyx", "M25PE80", ST_ID, 0x8014,
+	{"Numonyx", "M25PE80",
+	 ST_ID, 0x8014, probe_spi_rdid,
 	 1024, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	 spi_chip_erase_d8, spi_chip_write, spi_chip_read 
 	},
 
-	{"Numonyx", "M25PE16", ST_ID, 0x8015,
+	{"Numonyx", "M25PE16",
+	 ST_ID, 0x8015, probe_spi_rdid,
 	 2048, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read
+	 spi_chip_erase_d8, spi_chip_write, spi_chip_read 
 	},
 
-	{"PMC", "Pm25LV010", PMC_ID, PMC_25LV010,
+	{"PMC", "Pm25LV010",
+	 PMC_ID, PMC_25LV010, probe_spi_rdid,
 	 128, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B,
+	{"PMC", "Pm25LV016B",
+	 PMC_ID, PMC_25LV016B, probe_spi_rdid,
 	 2048, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"PMC", "Pm25LV020", PMC_ID, PMC_25LV020,
+	{"PMC", "Pm25LV020",
+	 PMC_ID, PMC_25LV020, probe_spi_rdid,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"PMC", "Pm25LV040", PMC_ID, PMC_25LV040,
+	{"PMC", "Pm25LV040",
+	 PMC_ID, PMC_25LV040, probe_spi_rdid,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B,
+	{"PMC", "Pm25LV080B",
+	 PMC_ID, PMC_25LV080B, probe_spi_rdid,
 	 1024, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"PMC", "Pm25LV512", PMC_ID, PMC_25LV512,
+	{"PMC", "Pm25LV512",
+	 PMC_ID, PMC_25LV512, probe_spi_rdid,
 	 64, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"PMC", "Pm49FL002", PMC_ID_NOPREFIX, PMC_49FL002,
+	{"PMC", "Pm49FL002",
+	 PMC_ID_NOPREFIX, PMC_49FL002, probe_49fl00x,
 	 256, 16 * 1024,
 	 TEST_OK_PREW,
-	 probe_49fl00x, erase_49fl00x, write_49fl00x
+	 erase_49fl00x, write_49fl00x 
 	},
 
-	{"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004,
+	{"PMC", "Pm49FL004",
+	 PMC_ID_NOPREFIX,PMC_49FL004, probe_49fl00x,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_49fl00x, erase_49fl00x, write_49fl00x
+	 erase_49fl00x, write_49fl00x 
 	},
 
-	{"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04,
+	{"Sharp", "LHF00L04",
+	 SHARP_ID, SHARP_LHF00L04, probe_lhf00l04,
 	 1024, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_lhf00l04, erase_lhf00l04, write_lhf00l04
+	 erase_lhf00l04, write_lhf00l04 
 	},
 
-	{"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A,
+	{"Spansion", "S25FL016A",
+	 SPANSION_ID, SPANSION_S25FL016A, probe_spi_rdid,
 	 2048, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"SST", "SST25VF016B", SST_ID, SST_25VF016B,
+	{"SST", "SST25VF016B",
+	 SST_ID, SST_25VF016B, probe_spi_rdid,
 	 2048, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"SST", "SST25VF032B", SST_ID, SST_25VF032B,
+	{"SST", "SST25VF032B",
+	 SST_ID, SST_25VF032B, probe_spi_rdid,
 	 4096, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"SST", "SST25VF040B", SST_ID, SST_25VF040B,
+	{"SST", "SST25VF040B",
+	 SST_ID, SST_25VF040B, probe_spi_rdid,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"SST", "SST25VF080B", SST_ID, SST_25VF080B,
+	{"SST", "SST25VF080B",
+	 SST_ID, SST_25VF080B, probe_spi_rdid,
 	 1024, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_60_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_60_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"SST", "SST28SF040A", SST_ID, SST_28SF040,
+	{"SST", "SST28SF040A",
+	 SST_ID, SST_28SF040, probe_28sf040,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_28sf040, erase_28sf040, write_28sf040
+	 erase_28sf040, write_28sf040 
 	},
 
-	{"SST", "SST29EE010", SST_ID, SST_29EE010,
+	{"SST", "SST29EE010",
+	 SST_ID, SST_29EE010, probe_jedec,
 	 128, 128,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"SST", "SST29LE010", SST_ID, SST_29LE010,
+	{"SST", "SST29LE010",
+	 SST_ID, SST_29LE010, probe_jedec,
 	 128, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"SST", "SST29EE020A", SST_ID, SST_29EE020A,
+	{"SST", "SST29EE020A",
+	 SST_ID, SST_29EE020A, probe_jedec,
 	 256, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"SST", "SST29LE020", SST_ID, SST_29LE020,
+	{"SST", "SST29LE020",
+	 SST_ID, SST_29LE020, probe_jedec,
 	 256, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"SST", "SST39SF010A", SST_ID, SST_39SF010,
+	{"SST", "SST39SF010A",
+	 SST_ID, SST_39SF010, probe_jedec,
 	 128, 4096,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"SST", "SST39SF020A", SST_ID, SST_39SF020,
+	{"SST", "SST39SF020A",
+	 SST_ID, SST_39SF020, probe_jedec,
 	 256, 4096,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"SST", "SST39SF040", SST_ID, SST_39SF040,
+	{"SST", "SST39SF040",
+	 SST_ID, SST_39SF040, probe_jedec,
 	 512, 4096,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"SST", "SST39VF512", SST_ID, SST_39VF512,
+	{"SST", "SST39VF512",
+	 SST_ID, SST_39VF512, probe_jedec,
 	 64, 4096,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"SST", "SST39VF010", SST_ID, SST_39VF010,
+	{"SST", "SST39VF010",
+	 SST_ID, SST_39VF010, probe_jedec,
 	 128, 4096,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"SST", "SST39VF020", SST_ID, SST_39VF020,
+	{"SST", "SST39VF020",
+	 SST_ID, SST_39VF020, probe_jedec,
 	 256, 4096,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"SST", "SST39VF040", SST_ID, SST_39VF040,
+	{"SST", "SST39VF040",
+	 SST_ID, SST_39VF040, probe_jedec,
 	 512, 4096,
 	 TEST_OK_PROBE,
-	 probe_jedec, erase_chip_jedec, write_39sf020
-	}, /* assume similar to 004B, ignoring data sheet */
+	 erase_chip_jedec, write_39sf020 
+	},
 
-	{"SST", "SST49LF002A/B", SST_ID, SST_49LF002A,
+	{"SST", "SST49LF002A/B",
+	 SST_ID, SST_49LF002A, probe_sst_fwhub,
 	 256, 16 * 1024,
 	 TEST_OK_PREW,
-	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	 erase_sst_fwhub, write_sst_fwhub 
 	},
 
-	{"SST", "SST49LF003A/B", SST_ID, SST_49LF003A,
+	{"SST", "SST49LF003A/B",
+	 SST_ID, SST_49LF003A, probe_sst_fwhub,
 	 384, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	 erase_sst_fwhub, write_sst_fwhub 
 	},
 
-	{"SST", "SST49LF004A/B", SST_ID, SST_49LF004A,
+	{"SST", "SST49LF004A/B",
+	 SST_ID, SST_49LF004A, probe_sst_fwhub,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	 erase_sst_fwhub, write_sst_fwhub 
 	},
 
-	{"SST", "SST49LF004C", SST_ID, SST_49LF004C,
+	{"SST", "SST49LF004C",
+	 SST_ID, SST_49LF004C, probe_49lfxxxc,
 	 512, 4 * 1024,
 	 TEST_UNTESTED,
-	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	 erase_49lfxxxc, write_49lfxxxc 
 	},
 
-	{"SST", "SST49LF008A", SST_ID, SST_49LF008A,
+	{"SST", "SST49LF008A",
+	 SST_ID, SST_49LF008A, probe_sst_fwhub,
 	 1024, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	 erase_sst_fwhub, write_sst_fwhub 
 	},
 
-	{"SST", "SST49LF008C", SST_ID, SST_49LF008C,
+	{"SST", "SST49LF008C",
+	 SST_ID, SST_49LF008C, probe_49lfxxxc,
 	 1024, 4 * 1024,
 	 TEST_UNTESTED,
-	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	 erase_49lfxxxc, write_49lfxxxc 
 	},
 
-	{"SST", "SST49LF016C", SST_ID, SST_49LF016C,
+	{"SST", "SST49LF016C",
+	 SST_ID, SST_49LF016C, probe_49lfxxxc,
 	 2048, 4 * 1024,
 	 TEST_OK_PREW,
-	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	 erase_49lfxxxc, write_49lfxxxc 
 	},
 
-	{"SST", "SST49LF020A", SST_ID, SST_49LF020A,
+	{"SST", "SST49LF020A",
+	 SST_ID, SST_49LF020A, probe_jedec,
 	 256, 16 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_49lf040, write_49lf040
+	 erase_49lf040, write_49lf040 
 	},
 
-	{"SST", "SST49LF040", SST_ID, SST_49LF040,
+	{"SST", "SST49LF040",
+	 SST_ID, SST_49LF040, probe_jedec,
 	 512, 4096,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_49lf040, write_49lf040
+	 erase_49lf040, write_49lf040 
 	},
 
-	{"SST", "SST49LF040B", SST_ID, SST_49LF040B,
+	{"SST", "SST49LF040B",
+	 SST_ID, SST_49LF040B, probe_sst_fwhub,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub
+	 erase_sst_fwhub, write_sst_fwhub 
 	},
 
-	{"SST", "SST49LF080A", SST_ID, SST_49LF080A,
+	{"SST", "SST49LF080A",
+	 SST_ID, SST_49LF080A, probe_jedec,
 	 1024, 4096,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_49lf040, write_49lf040
+	 erase_49lf040, write_49lf040 
 	},
 
-	{"SST", "SST49LF160C", SST_ID, SST_49LF160C,
+	{"SST", "SST49LF160C",
+	 SST_ID, SST_49LF160C, probe_49lfxxxc,
 	 2048, 4 * 1024,
 	 TEST_OK_PREW,
-	 probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc
+	 erase_49lfxxxc, write_49lfxxxc 
 	},
 
-	{"ST", "M25P05-A", ST_ID, ST_M25P05A,
+	{"ST", "M25P05-A",
+	 ST_ID, ST_M25P05A, probe_spi_rdid,
 	 64, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P10-A", ST_ID, ST_M25P10A,
+	{"ST", "M25P10-A",
+	 ST_ID, ST_M25P10A, probe_spi_rdid,
 	 128, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P20", ST_ID, ST_M25P20,
+	{"ST", "M25P20",
+	 ST_ID, ST_M25P20, probe_spi_rdid,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P40", ST_ID, ST_M25P40,
+	{"ST", "M25P40",
+	 ST_ID, ST_M25P40, probe_spi_rdid,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P40-old", ST_ID, ST_M25P40_RES,
+	{"ST", "M25P40-old",
+	 ST_ID, ST_M25P40_RES, probe_spi_res,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_spi_res, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P80", ST_ID, ST_M25P80,
+	{"ST", "M25P80",
+	 ST_ID, ST_M25P80, probe_spi_rdid,
 	 1024, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P16", ST_ID, ST_M25P16,
+	{"ST", "M25P16",
+	 ST_ID, ST_M25P16, probe_spi_rdid,
 	 2048, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P32", ST_ID, ST_M25P32,
+	{"ST", "M25P32",
+	 ST_ID, ST_M25P32, probe_spi_rdid,
 	 4096, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P64", ST_ID, ST_M25P64,
+	{"ST", "M25P64",
+	 ST_ID, ST_M25P64, probe_spi_rdid,
 	 8192, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M25P128", ST_ID, ST_M25P128,
+	{"ST", "M25P128",
+	 ST_ID, ST_M25P128, probe_spi_rdid,
 	 16384, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"ST", "M29F002B", ST_ID, ST_M29F002B,
+	{"ST", "M29F002B",
+	 ST_ID, ST_M29F002B, probe_jedec,
 	 256, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"ST", "M29F002T/NT", ST_ID, ST_M29F002T,
+	{"ST", "M29F002T/NT",
+	 ST_ID, ST_M29F002T, probe_jedec,
 	 256, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"ST", "M29F040B", ST_ID, ST_M29F040B,
+	{"ST", "M29F040B",
+	 ST_ID, ST_M29F040B, probe_29f040b,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_29f040b, erase_29f040b, write_29f040b
+	 erase_29f040b, write_29f040b 
 	},
 
-	{"ST", "M29F400BT", ST_ID, ST_M29F400BT,
+	{"ST", "M29F400BT",
+	 ST_ID, ST_M29F400BT, probe_m29f400bt,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt
+	 erase_m29f400bt, write_coreboot_m29f400bt 
 	},
 
-	{"ST", "M29W010B", ST_ID, ST_M29W010B,
+	{"ST", "M29W010B",
+	 ST_ID, ST_M29W010B, probe_jedec,
 	 128, 16 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"ST", "M29W040B", ST_ID, ST_M29W040B,
+	{"ST", "M29W040B",
+	 ST_ID, ST_M29W040B, probe_jedec,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"ST", "M50FLW040A", ST_ID, ST_M50FLW040A,
+	{"ST", "M50FLW040A",
+	 ST_ID, ST_M50FLW040A, probe_stm50flw0x0x,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	 erase_stm50flw0x0x, write_stm50flw0x0x 
 	},
 
-	{"ST", "M50FLW040B", ST_ID, ST_M50FLW040B,
+	{"ST", "M50FLW040B",
+	 ST_ID, ST_M50FLW040B, probe_stm50flw0x0x,
 	 512, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	 erase_stm50flw0x0x, write_stm50flw0x0x 
 	},
 
-	{"ST", "M50FLW080A", ST_ID, ST_M50FLW080A,
+	{"ST", "M50FLW080A",
+	 ST_ID, ST_M50FLW080A, probe_stm50flw0x0x,
 	 1024, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	 erase_stm50flw0x0x, write_stm50flw0x0x 
 	},
 
-	{"ST", "M50FLW080B", ST_ID, ST_M50FLW080B,
+	{"ST", "M50FLW080B",
+	 ST_ID, ST_M50FLW080B, probe_stm50flw0x0x,
 	 1024, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x
+	 erase_stm50flw0x0x, write_stm50flw0x0x 
 	},
 
-	{"ST", "M50FW002", ST_ID, ST_M50FW002,
+	{"ST", "M50FW002",
+	 ST_ID, ST_M50FW002, probe_49lfxxxc,
 	 256, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_49lfxxxc, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"ST", "M50FW016", ST_ID, ST_M50FW016,
+	{"ST", "M50FW016",
+	 ST_ID, ST_M50FW016, probe_82802ab,
 	 2048, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_82802ab, erase_82802ab, write_82802ab
+	 erase_82802ab, write_82802ab 
 	},
 
-	{"ST", "M50FW040", ST_ID, ST_M50FW040,
+	{"ST", "M50FW040",
+	 ST_ID, ST_M50FW040, probe_82802ab,
 	 512, 64 * 1024,
 	 TEST_OK_PREW,
-	 probe_82802ab, erase_82802ab, write_82802ab
+	 erase_82802ab, write_82802ab 
 	},
 
-	{"ST", "M50FW080", ST_ID, ST_M50FW080,
+	{"ST", "M50FW080",
+	 ST_ID, ST_M50FW080, probe_82802ab,
 	 1024, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_82802ab, erase_82802ab, write_82802ab
+	 erase_82802ab, write_82802ab 
 	},
 
-	{"ST", "M50LPW116", ST_ID, ST_M50LPW116,
+	{"ST", "M50LPW116",
+	 ST_ID, ST_M50LPW116, probe_jedec,
 	 2048, 64 * 1024,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T,
+	{"SyncMOS", "S29C31004T",
+	 SYNCMOS_ID, S29C31004T, probe_jedec,
 	 512, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T,
+	{"SyncMOS", "S29C51001T",
+	 SYNCMOS_ID, S29C51001T, probe_jedec,
 	 128, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T,
+	{"SyncMOS", "S29C51002T",
+	 SYNCMOS_ID, S29C51002T, probe_jedec,
 	 256, 128,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T,
+	{"SyncMOS", "S29C51004T",
+	 SYNCMOS_ID, S29C51004T, probe_jedec,
 	 512, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10,
+	{"Winbond", "W25x10",
+	 WINBOND_NEX_ID, W_25X10, probe_spi_rdid,
 	 128, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20,
+	{"Winbond", "W25x20",
+	 WINBOND_NEX_ID, W_25X20, probe_spi_rdid,
 	 256, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40,
+	{"Winbond", "W25x40",
+	 WINBOND_NEX_ID, W_25X40, probe_spi_rdid,
 	 512, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80,
+	{"Winbond", "W25x80",
+	 WINBOND_NEX_ID, W_25X80, probe_spi_rdid,
 	 1024, 256,
 	 TEST_OK_PREW,
-	 probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read
+	 spi_chip_erase_c7, spi_chip_write, spi_chip_read 
 	},
 
-	{"Winbond", "W29C011", WINBOND_ID, W_29C011,
+	{"Winbond", "W29C011",
+	 WINBOND_ID, W_29C011, probe_jedec,
 	 128, 128,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"Winbond", "W29C020C", WINBOND_ID, W_29C020C,
+	{"Winbond", "W29C020C",
+	 WINBOND_ID, W_29C020C, probe_jedec,
 	 256, 128,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"Winbond", "W29C040P", WINBOND_ID, W_29C040P,
+	{"Winbond", "W29C040P",
+	 WINBOND_ID, W_29C040P, probe_jedec,
 	 512, 256,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"Winbond", "W29EE011", WINBOND_ID, W_29C011,
+	{"Winbond", "W29EE011",
+	 WINBOND_ID, W_29C011, probe_w29ee011,
 	 128, 128,
 	 TEST_OK_PREW,
-	 probe_w29ee011, erase_chip_jedec, write_jedec
+	 erase_chip_jedec, write_jedec 
 	},
 
-	{"Winbond", "W39V040A", WINBOND_ID, W_39V040A,
+	{"Winbond", "W39V040A",
+	 WINBOND_ID, W_39V040A, probe_jedec,
 	 512, 64*1024,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"Winbond", "W39V040B", WINBOND_ID, W_39V040B,
+	{"Winbond", "W39V040B",
+	 WINBOND_ID, W_39V040B, probe_jedec,
 	 512, 64*1024,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"Winbond", "W39V040C", WINBOND_ID, 0x50,
+	{"Winbond", "W39V040C",
+	 WINBOND_ID, 0x50, probe_w39v040c,
 	 512, 64*1024,
 	 TEST_OK_PREW,
-	 probe_w39v040c, erase_w39v040c, write_w39v040c
+	 erase_w39v040c, write_w39v040c 
 	},
 
-	{"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA,
+	{"Winbond", "W39V040FA",
+	 WINBOND_ID, W_39V040FA, probe_jedec,
 	 512, 64*1024,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"Winbond", "W39V080A", WINBOND_ID, W_39V080A,
+	{"Winbond", "W39V080A",
+	 WINBOND_ID, W_39V080A, probe_jedec,
 	 1024, 64*1024,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_39sf020
+	 erase_chip_jedec, write_39sf020 
 	},
 
-	{"Winbond", "W49F002U", WINBOND_ID, W_49F002U,
+	{"Winbond", "W49F002U",
+	 WINBOND_ID, W_49F002U, probe_jedec,
 	 256, 128,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"Winbond", "W49V002A", WINBOND_ID, W_49V002A,
+	{"Winbond", "W49V002A",
+	 WINBOND_ID, W_49V002A, probe_jedec,
 	 256, 128,
 	 TEST_OK_PREW,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"Winbond", "W49V002FA", WINBOND_ID, W_49V002FA,
+	{"Winbond", "W49V002FA",
+	 WINBOND_ID, W_49V002FA, probe_jedec,
 	 256, 128,
 	 TEST_UNTESTED,
-	 probe_jedec, erase_chip_jedec, write_49f002
+	 erase_chip_jedec, write_49f002 
 	},
 
-	{"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA,
+	{"Winbond", "W39V080FA",
+	 WINBOND_ID, W_39V080FA, probe_winbond_fwhub,
 	 1024, 64*1024,
 	 TEST_OK_PREW,
-	 probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub
+	 erase_winbond_fwhub, write_winbond_fwhub 
 	},
 
-	{"Winbond", "W39V080FA (dual mode)", WINBOND_ID, W_39V080FA_DM,
+	{"Winbond", "W39V080FA (dual mode)",
+	 WINBOND_ID, W_39V080FA_DM, probe_winbond_fwhub,
 	 512, 64*1024,
 	 TEST_UNTESTED,
-	 probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub
+	 erase_winbond_fwhub, write_winbond_fwhub 
 	},
 
-	{"Atmel", "unknown Atmel SPI chip", ATMEL_ID, GENERIC_DEVICE_ID,
+	{"Atmel", "unknown Atmel SPI chip",
+	 ATMEL_ID, GENERIC_DEVICE_ID, probe_spi_rdid,
 	 0, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"EON", "unknown EON SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID,
+	{"EON", "unknown EON SPI chip",
+	 EON_ID_NOPREFIX, GENERIC_DEVICE_ID, probe_spi_rdid,
 	 0, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID,
+	{"Macronix", "unknown Macronix SPI chip",
+	 MX_ID, GENERIC_DEVICE_ID, probe_spi_rdid,
 	 0, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID,
+	{"PMC", "unknown PMC SPI chip",
+	 PMC_ID, GENERIC_DEVICE_ID, probe_spi_rdid,
 	 0, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"SST", "unknown SST SPI chip", SST_ID, GENERIC_DEVICE_ID,
+	{"SST", "unknown SST SPI chip",
+	 SST_ID, GENERIC_DEVICE_ID, probe_spi_rdid,
 	 0, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL
+	 NULL, NULL 
 	},
 
-	{"ST", "unknown ST SPI chip", ST_ID, GENERIC_DEVICE_ID,
+	{"ST", "unknown ST SPI chip",
+	 ST_ID, GENERIC_DEVICE_ID, probe_spi_rdid,
 	 0, 256,
 	 TEST_UNTESTED,
-	 probe_spi_rdid, NULL, NULL
+	 NULL, NULL 
 	},
 
 	{NULL,}


-- 
http://www.hailfinger.org/

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From peter at stuge.se  Tue Dec  9 01:48:33 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 9 Dec 2008 01:48:33 +0100
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>
References: <492B35A4.2010307@assembler.cz>
	<20081130014525.GA4886@morn.localdomain>
	<493DB602.4050606@assembler.cz>
	<13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>
Message-ID: <20081209004833.30783.qmail@stuge.se>

ron minnich wrote:
> BTW, we have a table at SCALE! I'd love to have as many of you
> there as can make it.

What's the URL for the expo again?


//Peter



From rminnich at gmail.com  Tue Dec  9 01:56:29 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 8 Dec 2008 16:56:29 -0800
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <20081209004833.30783.qmail@stuge.se>
References: <492B35A4.2010307@assembler.cz>
	<20081130014525.GA4886@morn.localdomain>
	<493DB602.4050606@assembler.cz>
	<13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>
	<20081209004833.30783.qmail@stuge.se>
Message-ID: <13426df10812081656h1cd932edk22f4c3209ab1ec00@mail.gmail.com>

On Mon, Dec 8, 2008 at 4:48 PM, Peter Stuge <peter at stuge.se> wrote:
> ron minnich wrote:
>> BTW, we have a table at SCALE! I'd love to have as many of you
>> there as can make it.
>
> What's the URL for the expo again?

http://scale7x.socallinuxexpo.org/
and see this!
http://scale7x.socallinuxexpo.org/conference-info/exhibitors



From ward at gnu.org  Tue Dec  9 02:01:14 2008
From: ward at gnu.org (Ward Vandewege)
Date: Mon, 8 Dec 2008 20:01:14 -0500
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <13426df10812081656h1cd932edk22f4c3209ab1ec00@mail.gmail.com>
References: <492B35A4.2010307@assembler.cz>
	<20081130014525.GA4886@morn.localdomain>
	<493DB602.4050606@assembler.cz>
	<13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>
	<20081209004833.30783.qmail@stuge.se>
	<13426df10812081656h1cd932edk22f4c3209ab1ec00@mail.gmail.com>
Message-ID: <20081209010113.GA12846@localdomain>

On Mon, Dec 08, 2008 at 04:56:29PM -0800, ron minnich wrote:
> On Mon, Dec 8, 2008 at 4:48 PM, Peter Stuge <peter at stuge.se> wrote:
> > ron minnich wrote:
> >> BTW, we have a table at SCALE! I'd love to have as many of you
> >> there as can make it.
> >
> > What's the URL for the expo again?
> 
> http://scale7x.socallinuxexpo.org/
> and see this!
> http://scale7x.socallinuxexpo.org/conference-info/exhibitors

The benefits of having a 'brand' that starts with a letter low in the
alphabet :)

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  9 02:15:04 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 09 Dec 2008 02:15:04 +0100
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <13426df10812081656h1cd932edk22f4c3209ab1ec00@mail.gmail.com>
References: <492B35A4.2010307@assembler.cz>	<20081130014525.GA4886@morn.localdomain>	<493DB602.4050606@assembler.cz>	<13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>	<20081209004833.30783.qmail@stuge.se>
	<13426df10812081656h1cd932edk22f4c3209ab1ec00@mail.gmail.com>
Message-ID: <493DC698.9050504@gmx.net>

On 09.12.2008 01:56, ron minnich wrote:
> On Mon, Dec 8, 2008 at 4:48 PM, Peter Stuge <peter at stuge.se> wrote:
>   
>> ron minnich wrote:
>>     
>>> BTW, we have a table at SCALE! I'd love to have as many of you
>>> there as can make it.
>>>       
>> What's the URL for the expo again?
>>     
>
> http://scale7x.socallinuxexpo.org/
> and see this!
> http://scale7x.socallinuxexpo.org/conference-info/exhibitors
>   

Cool. Which laptop will be running coreboot?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From joe at settoplinux.org  Tue Dec  9 02:25:28 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Mon, 08 Dec 2008 20:25:28 -0500
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <493DC698.9050504@gmx.net>
References: <492B35A4.2010307@assembler.cz>	<20081130014525.GA4886@morn.localdomain>	<493DB602.4050606@assembler.cz>	<13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>	<20081209004833.30783.qmail@stuge.se>
	<13426df10812081656h1cd932edk22f4c3209ab1ec00@mail.gmail.com>
	<493DC698.9050504@gmx.net>
Message-ID: <19111318b54912a1d9d9e3458e8d176b@imap.1and1.com>




On Tue, 09 Dec 2008 02:15:04 +0100, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 09.12.2008 01:56, ron minnich wrote:
>> On Mon, Dec 8, 2008 at 4:48 PM, Peter Stuge <peter at stuge.se> wrote:
>>
>>> ron minnich wrote:
>>>
>>>> BTW, we have a table at SCALE! I'd love to have as many of you
>>>> there as can make it.
>>>>
>>> What's the URL for the expo again?
>>>
>>
>> http://scale7x.socallinuxexpo.org/
>> and see this!
>> http://scale7x.socallinuxexpo.org/conference-info/exhibitors
>>
> 
> Cool. Which laptop will be running coreboot?
> 
We have a laptop that runs coreboot? Where have I been?

Also what is the "Safe Open Laptop project" I have heard anything about
this?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From corey.osgood at gmail.com  Tue Dec  9 03:12:35 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Mon, 8 Dec 2008 21:12:35 -0500
Subject: [coreboot] Interesting (part of) article.
In-Reply-To: <13426df10812081546u535769ds2656ca10903a92e5@mail.gmail.com>
References: <493C22BB.7040402@min-epost.net> <493C47DB.2060808@gmx.net>
	<b1335fe90812081530i7fab3261mf74af5c37487fd06@mail.gmail.com>
	<13426df10812081546u535769ds2656ca10903a92e5@mail.gmail.com>
Message-ID: <dd3c80060812081812n5963b43ct7d9dcc7cd9f1ea04@mail.gmail.com>

On Mon, Dec 8, 2008 at 6:46 PM, ron minnich <rminnich at gmail.com> wrote:

> Why don't we try to talk about anandtech about the ways coreboot would
> help solve the problems they are wasting time on.


I've got to ask this: why? These guys are reviewers, the only thing they
could do would be inform motherboard manufacturers about coreboot, and I'm
fairly sure most manufacturers already know about the project. They could do
a write-up on it I suppose, but aside from creating some public interest,
the net result would probably be minimal. And without support for Vista or
even good support for XP, coreboot isn't a viable option IMO for most users.
Just my 2 cents.

-Corey
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From stepan at coresystems.de  Tue Dec  9 09:14:36 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 09 Dec 2008 09:14:36 +0100
Subject: [coreboot] [PATCH] flashrom: Group probe function together with
 associated IDs
In-Reply-To: <493DBEB5.3070800@gmx.net>
References: <493DBEB5.3070800@gmx.net>
Message-ID: <493E28EC.2080304@coresystems.de>

Carl-Daniel Hailfinger wrote:
> The flash probe function and the IDs for that specific probe function
> belong together. Group them together on a single line.
> We already have chips with multiple probe functions and multiple IDs.
> This patch is the first step in consolidating the present way of
> creating a new chip definition for each ID of a given chip into multiple
> IDs per chip definition.
>
> Attached for Gmail users.
>   
Thunderbird users also love this.

> -	{"AMD", "Am29F002(N)BB", AMD_ID, AM_29F002BB,
> +	{"AMD", "Am29F002(N)BB",
> +	 AMD_ID, AM_29F002BB, probe_jedec,
>   
Please leave the chip name and ID on the same line. Once we fixed
flashrom to use the non-hidden IDs here, that'll be a very convenient
way for associating IDs and chips.
>  	 256, 256,
>  	 TEST_UNTESTED,
> -	 probe_jedec, erase_chip_jedec, write_en29f002a
> +	 erase_chip_jedec, write_en29f002a 
>  	},
>   
I think function pointers should not be intercepted by the sized above.
This patch obfuscates the code.

Stefan


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From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  9 10:51:37 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 09 Dec 2008 10:51:37 +0100
Subject: [coreboot] [PATCH] flashrom: Group probe function together with
 associated IDs
In-Reply-To: <493E28EC.2080304@coresystems.de>
References: <493DBEB5.3070800@gmx.net> <493E28EC.2080304@coresystems.de>
Message-ID: <493E3FA9.4010104@gmx.net>

On 09.12.2008 09:14, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> The flash probe function and the IDs for that specific probe function
>> belong together. Group them together on a single line.
>> We already have chips with multiple probe functions and multiple IDs.
>> This patch is the first step in consolidating the present way of
>> creating a new chip definition for each ID of a given chip into multiple
>> IDs per chip definition.
>>
>> Attached for Gmail users.
>>   
>>     
> Thunderbird users also love this.
>
>   
>> -	{"AMD", "Am29F002(N)BB", AMD_ID, AM_29F002BB,
>> +	{"AMD", "Am29F002(N)BB",
>> +	 AMD_ID, AM_29F002BB, probe_jedec,
>>   
>>     
> Please leave the chip name and ID on the same line. Once we fixed
> flashrom to use the non-hidden IDs here, that'll be a very convenient
> way for associating IDs and chips.
>   
>>  	 256, 256,
>>  	 TEST_UNTESTED,
>> -	 probe_jedec, erase_chip_jedec, write_en29f002a
>> +	 erase_chip_jedec, write_en29f002a 
>>  	},
>>   
>>     
> I think function pointers should not be intercepted by the sized above.
> This patch obfuscates the code.
>   

How do you propose to handle chips which have multiple different IDs and
multiple different probe functions? I hope you're not seriously
suggesting something like this:

{"Vendor", "Chip", 0x01, 0x23, 0x45, 0x56, 0x78, 0x9a,
256, 256,
TEST_UNTESTED,
probe_spi_rdid, probe_spi_rems, probe_spi_res, erase_spi_foo, write_spi,
read_spi
}

If we picked that layout, it would be really difficult to find out which
ID belongs to which probe function.

And having 3 entries for almost all SPI flash chips is definitely not
the way to go. Multiply that with the number of erase functions (up to 5
for some SPI chips) and you have 15 entries per real chip. Sure, I can
generate such entries, but people are going to hate that.

If the problem is not obvious, I'll gladly send a patch to illustrate my
point.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From Maggie.Li at amd.com  Tue Dec  9 11:08:15 2008
From: Maggie.Li at amd.com (Li, Maggie)
Date: Tue, 9 Dec 2008 18:08:15 +0800
Subject: [coreboot] patch for support mainboard pistachio:
Message-ID: <DD1CC71B621B004FA76856E5129D6B170239DAC7@sbjgexmb1.amd.com>

Hi,
Attachment is the patch for mainboard PISTACHIO. The following ACPI features are supported.
1. S1, S4, S5 sleep and wake up (by power button).
2. Thermal configuration based on ADT7475.
3. HPET timer.
4. Interrupt routing based on ACPI table.

Signed-off-by:  Maggie Li <maggie.li at amd.com>
Reviewed-by:    Michael Xie <michael.xie at amd.com <mailto:michael.xie at amd.com> >

Please check it, thanks.

 <<pistachio.patch>> 
Best regards
Maggie li

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From r.marek at assembler.cz  Tue Dec  9 11:39:51 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 09 Dec 2008 11:39:51 +0100
Subject: [coreboot] option roms in SeaBIOS and Coreboot
In-Reply-To: <13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>
References: <492B35A4.2010307@assembler.cz>	
	<20081130014525.GA4886@morn.localdomain>	
	<493DB602.4050606@assembler.cz>
	<13426df10812081612wa93cd80l49d80ba69a94553b@mail.gmail.com>
Message-ID: <493E4AF7.5010500@assembler.cz>

ron minnich wrote:
> can someone start accumulating these "works with seabios/doesn't work
> with factory BIOS" examples? I'm working up a talk for SCALE feb. 22
> and would love to have some slides on just this issue.
>   
Next is SMM issues with Xenomai. It creates unpredictable latencies.

Random link:
http://www.captain.at/xenomai-smi-high-latency.php

Rudolf



From peter at stuge.se  Tue Dec  9 14:11:47 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 9 Dec 2008 14:11:47 +0100
Subject: [coreboot] Interesting (part of) article.
In-Reply-To: <dd3c80060812081812n5963b43ct7d9dcc7cd9f1ea04@mail.gmail.com>
References: <493C22BB.7040402@min-epost.net> <493C47DB.2060808@gmx.net>
	<b1335fe90812081530i7fab3261mf74af5c37487fd06@mail.gmail.com>
	<13426df10812081546u535769ds2656ca10903a92e5@mail.gmail.com>
	<dd3c80060812081812n5963b43ct7d9dcc7cd9f1ea04@mail.gmail.com>
Message-ID: <20081209131148.25066.qmail@stuge.se>

Corey Osgood wrote:
> > Why don't we try to talk about anandtech about the ways coreboot
> > would help solve the problems they are wasting time on.
> 
> I've got to ask this: why? These guys are reviewers, the only thing
> they could do would be inform motherboard manufacturers about
> coreboot, and I'm fairly sure most manufacturers already know about
> the project.

Clearly (from the article) board vendors really listen to these guys,
the example mentioned even shows how that one vendor _depends_ on a
favorable review, because their market listens carefully to the
reviewers' advice. The reviewers even have direct contact with BIOS
developers, and they work through hundreds of issues. (Per the
article.)

Maybe vendors know about coreboot, but if this very important market
voice talks coreboot, merely mentioning it, or even requesting it as
an alternative, there is suddenly quite concrete motivation for
vendors to look closer at supporting and supplying coreboot.


> And without support for Vista or even good support for XP, coreboot
> isn't a viable option IMO for most users.

Well, coreboot itself doesn't really care, and this is an important
point to make when talking to anyone who is new to the project. All
the magic is in the payload.

The major benefit of the payload scheme in this case is that "Windows
support" is mostly decoupled from the hardware initialization in
coreboot. We just have to make sure coreboot has enough knowledge to
export the data structures that Windows needs.

SeaBIOS is already in good shape and getting better. Now is the time
for vendors to start looking into it, and I am certain that those
showing early interest will have a big advantage over their
competition.

And help is available to get them started quickly.


//Peter



From peter at stuge.se  Tue Dec  9 14:17:41 2008
From: peter at stuge.se (Peter Stuge)
Date: Tue, 9 Dec 2008 14:17:41 +0100
Subject: [coreboot] [PATCH] flashrom: Group probe function together with
	associated IDs
In-Reply-To: <493E3FA9.4010104@gmx.net>
References: <493DBEB5.3070800@gmx.net> <493E28EC.2080304@coresystems.de>
	<493E3FA9.4010104@gmx.net>
Message-ID: <20081209131741.27606.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> ... and you have 15 entries per real chip. Sure, I can generate
> such entries, but people are going to hate that.

I'm not hating. KISS.


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  9 14:32:23 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 09 Dec 2008 14:32:23 +0100
Subject: [coreboot] [PATCH] flashrom: Group probe function together with
 associated IDs
In-Reply-To: <20081209131741.27606.qmail@stuge.se>
References: <493DBEB5.3070800@gmx.net>
	<493E28EC.2080304@coresystems.de>	<493E3FA9.4010104@gmx.net>
	<20081209131741.27606.qmail@stuge.se>
Message-ID: <493E7367.2080802@gmx.net>

On 09.12.2008 14:17, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> ... and you have 15 entries per real chip. Sure, I can generate
>> such entries, but people are going to hate that.
>>     
>
> I'm not hating. KISS.
>   

Please elaborate. Will you ack the patch I posted or will you ack the 15
entries per chip variant? If it is the latter, please tell me what
scheme of chip naming for each of the 15 variants you had in mind.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From uwe at hermann-uwe.de  Tue Dec  9 15:28:07 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 9 Dec 2008 15:28:07 +0100
Subject: [coreboot] [PATCH] v2: 440BX: Multiple DIMM support, part 1
Message-ID: <20081209142806.GA17329@greenwood>

See patch.

Works fine on hardware, but some settings are still hardcoded for a
specific setup (will be fixed in an upcoming follow-up patch).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From joe at settoplinux.org  Tue Dec  9 16:43:14 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 09 Dec 2008 10:43:14 -0500
Subject: [coreboot] [PATCH] flashrom: Group probe function together with
 associated IDs
In-Reply-To: <493E7367.2080802@gmx.net>
References: <493DBEB5.3070800@gmx.net>
	<493E28EC.2080304@coresystems.de>	<493E3FA9.4010104@gmx.net>
	<20081209131741.27606.qmail@stuge.se> <493E7367.2080802@gmx.net>
Message-ID: <12e8097712e5d903bea1a1e4c7698ad6@imap.1and1.com>




On Tue, 09 Dec 2008 14:32:23 +0100, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 09.12.2008 14:17, Peter Stuge wrote:
>> Carl-Daniel Hailfinger wrote:
>>
>>> ... and you have 15 entries per real chip. Sure, I can generate
>>> such entries, but people are going to hate that.
>>>
>>
>> I'm not hating. KISS.
>>
> 
> Please elaborate. Will you ack the patch I posted or will you ack the 15
> entries per chip variant? If it is the latter, please tell me what
> scheme of chip naming for each of the 15 variants you had in mind.
> 
Ok, it good to be a lover and not a hater, but calm down on the kissing :-)
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Tue Dec  9 16:50:59 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 09 Dec 2008 10:50:59 -0500
Subject: [coreboot] [PATCH] v2: 440BX: Multiple DIMM support, part 1
In-Reply-To: <20081209142806.GA17329@greenwood>
References: <20081209142806.GA17329@greenwood>
Message-ID: <6dd997cd0fb4a4125129c26b073e20fb@imap.1and1.com>




On Tue, 9 Dec 2008 15:28:07 +0100, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> See patch.
> 
> Works fine on hardware, but some settings are still hardcoded for a
> specific setup (will be fixed in an upcoming follow-up patch).
> 
> 
Great work Uwe!
I like how you adopted the sending the ram command to each row of memory
:-) It works great!
If you have tested it on real hardware and it is working good....
Acked by: Joseph Smith <joe at settoplinux.org>
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Tue Dec  9 17:36:12 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  9 Dec 2008 17:36:12 +0100
Subject: [coreboot] r3807 - trunk/coreboot-v2/src/northbridge/intel/i440bx
Message-ID: <mailman.2560.1355071451.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-12-09 17:36:12 +0100 (Tue, 09 Dec 2008)
New Revision: 3807

Modified:
   trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c
Log:
Add (parts of the) support for multiple DIMMs on the Intel 440BX chipset.

This is tested on hardware with four 128MB DIMMs and works ok, _iff_
you also fix additional registers (e.g. DRB, RPS, ...) for your setup.
This requirement will be eliminated in another upcoming patch (i.e. all
of the required settings will be auto-detected).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Joseph Smith <joe at settoplinux.org>



Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c	2008-12-08 23:51:45 UTC (rev 3806)
+++ trunk/coreboot-v2/src/northbridge/intel/i440bx/raminit.c	2008-12-09 16:36:12 UTC (rev 3807)
@@ -352,34 +352,66 @@
 /**
  * Send the specified RAM command to all DIMMs.
  *
- * @param TODO
- * @param TODO
+ * @param command The RAM command to send to the DIMM(s).
  */
-static void do_ram_command(uint32_t command, uint32_t addr_offset)
+static void do_ram_command(u32 command)
 {
-	int i;
-	uint16_t reg;
+	int i, caslatency;
+	u8 dimm_start, dimm_end;
+	u16 reg16;
+	u32 addr, addr_offset;
 
-	/* TODO: Support for multiple DIMMs. */
-
 	/* Configure the RAM command. */
-	reg = pci_read_config16(NB, SDRAMC);
-	reg &= 0xff1f;		/* Clear bits 7-5. */
-	reg |= (uint16_t) (command << 5);
-	pci_write_config16(NB, SDRAMC, reg);
+	reg16 = pci_read_config16(NB, SDRAMC);
+	reg16 &= 0xff1f;		/* Clear bits 7-5. */
+	reg16 |= (u16) (command << 5);	/* Write command into bits 7-5. */
+	pci_write_config16(NB, SDRAMC, reg16);
 
-	/* RAM_COMMAND_NORMAL affects only the memory controller and
-	   doesn't need to be "sent" to the DIMMs. */
-	/* if (command == RAM_COMMAND_NORMAL) return; */
+	/*
+	 * RAM_COMMAND_NORMAL affects only the memory controller and
+	 * doesn't need to be "sent" to the DIMMs.
+	 */
+	if (command == RAM_COMMAND_NORMAL)
+		return;
 
-	PRINT_DEBUG("    Sending RAM command 0x");
-	PRINT_DEBUG_HEX16(reg);
-	PRINT_DEBUG(" to 0x");
-	PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
-	PRINT_DEBUG("\r\n");
+	/* Send the RAM command to each row of memory. */
+	dimm_start = 0;
+	for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
+                addr_offset = 0;
+                caslatency = 3; /* TODO: Dynamically get CAS latency later. */
+		if (command == RAM_COMMAND_MRS) {
+			/*
+			 * MAA[12:11,9:0] must be inverted when sent to DIMM
+			 * 2 or 3 (no inversion if sent to DIMM 0 or 1).
+			 */
+			if ((i >= 0 && i <= 3) && caslatency == 3)
+				addr_offset = 0x1d0;
+			if ((i >= 4 && i <= 7) && caslatency == 3)
+				addr_offset = 0x1e28;
+			if ((i >= 0 && i <= 3) && caslatency == 2)
+				addr_offset = 0x150;
+			if ((i >= 4 && i <= 7) && caslatency == 2)
+				addr_offset = 0x1ea8;
+		}
 
-	/* Read from (DIMM start address + addr_offset). */
-	read32(0 + addr_offset); // FIXME
+		dimm_end = pci_read_config8(NB, DRB + i);
+
+		addr = (dimm_start * 8 * 1024 * 1024) + addr_offset;
+		if (dimm_end > dimm_start) {
+#if 0
+			PRINT_DEBUG("    Sending RAM command 0x");
+			PRINT_DEBUG_HEX16(reg16);
+			PRINT_DEBUG(" to 0x");
+			PRINT_DEBUG_HEX32(addr);
+			PRINT_DEBUG("\r\n");
+#endif
+
+			read32(addr);
+		}
+
+		/* Set the start of the next DIMM. */
+		dimm_start = dimm_end;
+	}
 }
 
 /*-----------------------------------------------------------------------------
@@ -469,12 +501,11 @@
 	/* TODO: Set DRAMC. Don't enable refresh for now. */
 	pci_write_config8(NB, DRAMC, 0x08);
 
-	/* TODO: Set RPS. */
+	/* TODO: Set RPS. Needs to be fixed for multiple DIMM support. */
 	pci_write_config16(NB, RPS, 0x0001);
 
 	/* TODO: Set SDRAMC. */
-	// pci_write_config16(NB, SDRAMC, 0x010f); // FIXME?
-	pci_write_config16(NB, SDRAMC, 0x0003); // FIXME?
+	pci_write_config16(NB, SDRAMC, 0x0010);	/* SDRAMPWR=1: 4 DIMM config */
 
 	/* TODO: Set PGPOL. */
 	// pci_write_config16(NB, PGPOL, 0x0107);
@@ -504,29 +535,29 @@
 
 	/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
 	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
-	do_ram_command(RAM_COMMAND_NOP, 0);
+	do_ram_command(RAM_COMMAND_NOP);
 	udelay(200);
 
 	/* 2. Precharge all. Wait tRP. */
 	PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
-	do_ram_command(RAM_COMMAND_PRECHARGE, 0);
+	do_ram_command(RAM_COMMAND_PRECHARGE);
 	udelay(1);
 
 	/* 3. Perform 8 refresh cycles. Wait tRC each time. */
 	PRINT_DEBUG("RAM Enable 3: CBR\r\n");
 	for (i = 0; i < 8; i++) {
-		do_ram_command(RAM_COMMAND_CBR, 0);
+		do_ram_command(RAM_COMMAND_CBR);
 		udelay(1);
 	}
 
 	/* 4. Mode register set. Wait two memory cycles. */
 	PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
-	do_ram_command(RAM_COMMAND_MRS, 0x1d0);
+	do_ram_command(RAM_COMMAND_MRS);
 	udelay(2);
 
 	/* 5. Normal operation. */
 	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
-	do_ram_command(RAM_COMMAND_NORMAL, 0);
+	do_ram_command(RAM_COMMAND_NORMAL);
 	udelay(1);
 
 	/* 6. Finally enable refresh. */




From uwe at hermann-uwe.de  Tue Dec  9 17:37:38 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Tue, 9 Dec 2008 17:37:38 +0100
Subject: [coreboot] [PATCH] v2: 440BX: Multiple DIMM support, part 1
In-Reply-To: <6dd997cd0fb4a4125129c26b073e20fb@imap.1and1.com>
References: <20081209142806.GA17329@greenwood>
	<6dd997cd0fb4a4125129c26b073e20fb@imap.1and1.com>
Message-ID: <20081209163738.GA17334@greenwood>

On Tue, Dec 09, 2008 at 10:50:59AM -0500, Joseph Smith wrote:
> On Tue, 9 Dec 2008 15:28:07 +0100, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> > See patch.
> > 
> > Works fine on hardware, but some settings are still hardcoded for a
> > specific setup (will be fixed in an upcoming follow-up patch).
> > 
> > 
> Great work Uwe!
> I like how you adopted the sending the ram command to each row of memory
> :-) It works great!
> If you have tested it on real hardware and it is working good....
> Acked by: Joseph Smith <joe at settoplinux.org>

Thanks, r3807. Will post a patch for the remaining issues soon.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From corey.osgood at gmail.com  Tue Dec  9 18:15:09 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Tue, 9 Dec 2008 12:15:09 -0500
Subject: [coreboot] v3 cn700 patch dump
Message-ID: <dd3c80060812090915m7afcfb21w3d16111402e63a31@mail.gmail.com>

Attached is the net result of what I've done to try to figure out what's
going on with the cn700, right now it reboots part of the way through
initram, probably as a result of the GP3 timer not getting reset like it
should. I'm heading into finals week, so I probably won't be able to get
back to this until late December.

-Corey
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From rminnich at gmail.com  Tue Dec  9 19:38:37 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 9 Dec 2008 10:38:37 -0800
Subject: [coreboot] Interesting (part of) article.
In-Reply-To: <20081209131148.25066.qmail@stuge.se>
References: <493C22BB.7040402@min-epost.net> <493C47DB.2060808@gmx.net>
	<b1335fe90812081530i7fab3261mf74af5c37487fd06@mail.gmail.com>
	<13426df10812081546u535769ds2656ca10903a92e5@mail.gmail.com>
	<dd3c80060812081812n5963b43ct7d9dcc7cd9f1ea04@mail.gmail.com>
	<20081209131148.25066.qmail@stuge.se>
Message-ID: <13426df10812091038q12ec3113mccf5dcffda0f84a2@mail.gmail.com>

On Tue, Dec 9, 2008 at 5:11 AM, Peter Stuge <peter at stuge.se> wrote:

>> And without support for Vista or even good support for XP, coreboot
>> isn't a viable option IMO for most users.
>
> Well, coreboot itself doesn't really care, and this is an important
> point to make when talking to anyone who is new to the project. All
> the magic is in the payload.

and, when peter was visiting a few months ago, I watched XP install and boot.

It works for XP to some extent.

Honestly, it never hurts to inform people. We may think they know;
usually they don't.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  9 19:39:19 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 09 Dec 2008 19:39:19 +0100
Subject: [coreboot] [RFC] Add reviewed-by markers to code sections
Message-ID: <493EBB57.2020802@gmx.net>

Hi,

I'm currently trying to get my Asus M2A-VM board (690G/SB600) board
running in v2. It hangs directly after HT reset. That led me to dig into
the code and compare it to the data sheets.

In the past, reviews were mostly centered on coding style (not only
cosmetics, but also code flow) and general sanity. While that is
definitely needed, I propose another layer on top of this:

Verification of the code and comments against data sheet recommendations
and documentation.

Of course such work is neither really sexy nor does it have always an
immediate effect on the usability of a particular board, but it can find
bugs and hidden assumptions which may come to bite us later. I already
found real bugs by comparing code and data sheets in the past, but I
can't remember all the code I went through that way. The situation is
probably similar for other reviewers.

Adding a "Reviewed-by:" tag to the doxygen comments of each function
would be a nice way to say that the function has been reviewed. Pointing
to the section in the docs against which the code was verified is a ncie
added bonus. Plus, comments are really cheap and don't impact compile
time significantly.

Example patch for a reviewed function:

Review and annotate sb600_lpc_init().

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: src/southbridge/amd/sb600/sb600_early_setup.c
===================================================================
--- src/southbridge/amd/sb600/sb600_early_setup.c	(Revision 3803)
+++ src/southbridge/amd/sb600/sb600_early_setup.c	(Arbeitskopie)
@@ -53,11 +53,15 @@
 
 /***************************************
 * Legacy devices are mapped to LPC space.
-*	serial port 0
+*	Serial port 0
 *	KBC Port
 *	ACPI Micro-controller port
-*	LPC ROM size,
+*	LPC ROM size
+*	This function does not change port 0x80 decoding.
+*	Console output through any port besides 0x3f8 is unsupported.
 * NOTE: Call me ASAP, because I will reset LPC ROM size!
+* Reviewed-by: Carl-Daniel Hailfinger
+* Reviewed against AMD SB600 Register Reference Manual 3.03, section 3.1 (LPC ISA Bridge)
 ***************************************/
 static void sb600_lpc_init(void)
 {
@@ -68,31 +72,38 @@
 	/* Enable lpc controller */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);	/* SMBUS controller */
 	reg32 = pci_read_config32(dev, 0x64);
-	reg32 |= 0x00100000;
+	reg32 |= (1 << 20);
 	pci_write_config32(dev, 0x64, reg32);
 
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);	/* LPC Controller */
-	/* Serial 0 */
+	/* Decode port 0x3f8-0x3ff (Serial 0) */
+#warning Serial port decode on LPC is hardcoded to 0x3f8
 	reg8 = pci_read_config8(dev, 0x44);
 	reg8 |= (1 << 6);
 	pci_write_config8(dev, 0x44, reg8);
 
-	/* PS/2 keyboard, ACPI */
+	/* Decode port 0x60-0x67 (PS/2 keyboard, ACPI) */
 	reg8 = pci_read_config8(dev, 0x47);
 	reg8 |= (1 << 5) | (1 << 6);
 	pci_write_config8(dev, 0x47, reg8);
 
 	/* SuperIO, LPC ROM */
 	reg8 = pci_read_config8(dev, 0x48);
-	reg8 |= (1 << 1) | (1 << 0);	/* enable Super IO config port 2e-2h, 4e-4f */
-	reg8 |= (1 << 3) | (1 << 4);	/* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF  */
-	reg8 |= 1 << 6;		/* enable for RTC I/O range */
+	/* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
+	reg8 |= (1 << 1) | (1 << 0);
+	/* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
+	reg8 |= (1 << 3) | (1 << 4);
+	/* Decode port 0x70-0x73 (RTC) */
+	reg8 |= 1 << 6;
 	pci_write_config8(dev, 0x48, reg8);
 
 	/* hardware should enable LPC ROM by pin strapes */
-	/*  rom access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
+	/* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
 	/* See detail in BDG-215SB600-03.pdf page 15. */
-	pci_write_config16(dev, 0x68, 0x000e);	/* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; */
+#warning If Lpc_Rom strap is enabled, the line below has no effect, and if Lpc_Rom strap is disabled, a write to 0x6a is missing
+	pci_write_config16(dev, 0x68, 0x000e);	/* enable LPC ROM range mirroring below 1 MB */
+#warning Due to FWH_*_IDSEL defaults, any LPC ROM chip larger than 512 kB will not work although we enable a range of 1 MB below
+#warning If Lpc_Rom strap is disabled, a write to 0x6e is missing
 	pci_write_config16(dev, 0x6c, 0xfff0);	/* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB  */
 }
 


-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Tue Dec  9 20:14:59 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 9 Dec 2008 11:14:59 -0800
Subject: [coreboot] add atomic ops
Message-ID: <13426df10812091114vce0b15el4d6ad18f620a8fcd@mail.gmail.com>

copyright header ideas anyone?

ron
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From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  9 21:49:18 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 09 Dec 2008 21:49:18 +0100
Subject: [coreboot] add atomic ops
In-Reply-To: <13426df10812091114vce0b15el4d6ad18f620a8fcd@mail.gmail.com>
References: <13426df10812091114vce0b15el4d6ad18f620a8fcd@mail.gmail.com>
Message-ID: <493ED9CE.4060601@gmx.net>

On 09.12.2008 20:14, ron minnich wrote:
> copyright header ideas anyone?
>   

I'm pretty sure that file is from the Linux kernel. Googling for the
comments gives me an exact hit in the Linux kernel sources.

> ron
>   
> Add atomic operators. 
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Tue Dec  9 22:21:48 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 9 Dec 2008 13:21:48 -0800
Subject: [coreboot] patch for support mainboard pistachio:
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B170239DAC7@sbjgexmb1.amd.com>
References: <AclZ5g0+9ynKk4xOR+ikl77H7Q8hPQ==>
	<DD1CC71B621B004FA76856E5129D6B170239DAC7@sbjgexmb1.amd.com>
Message-ID: <13426df10812091321p1f389123pe156e5b3322005e4@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Tue Dec  9 22:52:43 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  9 Dec 2008 22:52:43 +0100
Subject: [coreboot] r3808 - in trunk/coreboot-v2: src/mainboard/amd
	src/mainboard/amd/pistachio src/mainboard/amd/pistachio/acpi
	targets/amd targets/amd/pistachio
Message-ID: <mailman.2561.1355071451.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-12-09 22:52:42 +0100 (Tue, 09 Dec 2008)
New Revision: 3808

Added:
   trunk/coreboot-v2/src/mainboard/amd/pistachio/
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/cpstate.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/debug.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/doit.sh
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/globutil.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/ide.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/routing.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/sata.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/statdef.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/usb.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/chip.h
   trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout
   trunk/coreboot-v2/src/mainboard/amd/pistachio/fadt.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/irq_tables.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/mptable.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/resourcemap.c
   trunk/coreboot-v2/targets/amd/pistachio/
   trunk/coreboot-v2/targets/amd/pistachio/Config-abuild.lb
   trunk/coreboot-v2/targets/amd/pistachio/Config.lb
Log:
AMD PISTACHIO mainboard support.

The following ACPI features are supported:
 1. S1, S4, S5 sleep and wake up (by power button).
 2. Thermal configuration based on ADT7475.
 3. HPET timer.
 4. Interrupt routing based on ACPI table.

Signed-off-by: Maggie Li <maggie.li at amd.com>
Reviewed-by: Michael Xie <michael.xie at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,274 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+##
+##
+
+
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The coreboot bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreboot will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#dir /drivers/si/3114
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE
+	object get_bus_conf.o
+	object irq_tables.o
+end
+
+if HAVE_ACPI_TABLES
+	object acpi_tables.o
+	object fadt.o
+	makerule dsdt.c
+		depends "$(MAINBOARD)/acpi/*.asl"
+		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
+		action  "mv dsdt.hex dsdt.c"
+	end
+	object ./dsdt.o
+end
+
+#object reset.o
+
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+
+		makerule ./cache_as_ram_auto.o
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+		end
+
+	else
+
+		makerule ./cache_as_ram_auto.inc
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"
+			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+		end
+
+	end
+
+end
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+if USE_DCACHE_RAM
+	if CONFIG_USE_INIT
+		ldscript /cpu/x86/32bit/entry32.lds
+	end
+
+	if CONFIG_USE_INIT
+		ldscript      /cpu/amd/car/cache_as_ram.lds
+	end
+end
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	else
+		ldscript /arch/i386/lib/failover.lds
+		mainboardinit ./failover.inc
+	end
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject cache_as_ram_auto.o
+	else
+		mainboardinit ./cache_as_ram_auto.inc
+	end
+
+end
+
+##
+## Include the secondary Configuration files
+##
+if CONFIG_CHIP_NAME
+	config chip.h
+end
+
+#The variables belong to mainboard are defined here.
+
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+#					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#Define gfx_dual_slot, 0: single slot, 1: dual slot
+#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
+#Define gfx_tmds, 0: didn't support TMDS, 1: support
+#Define gfx_compliance, 0: didn't support compliance, 1: support
+#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
+#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_AM2
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge, K8 HT Configuration
+				chip southbridge/amd/rs690
+					device pci 0.0 on end # HT  	0x7910
+				#	device pci 0.1 off end # CLK
+					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
+						chip drivers/pci/onboard
+							device pci 5.0 on end	# Internal Graphics 0x791F
+							register "rom_address" = "0xfff00000"
+						end
+					end
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x1914
+					device pci 5.0 on end # PCIE P2P bridge 0x7915
+					device pci 6.0 on end # PCIE P2P bridge 0x7916
+					device pci 7.0 on end # PCIE P2P bridge 0x7917
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					register "vga_rom_address" = "0xfff00000"
+					register "gpp_configuration" = "4"
+					register "port_enable" = "0xfc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
+	 				device pci 14.0 on # SM        0x4385
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 off end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 off end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 off end
+						end
+					end # SM
+				device pci 14.1 on end # IDE    0x438c
+				device pci 14.2 on end # HDA    0x4383
+				device pci 14.3 on end # LPC	0x438d
+				device pci 14.4 on end # PCI 0x4384
+				device pci 14.5 on end # ACI 0x4382
+				device pci 14.6 on end # MCI 0x438e
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb600
+			end #  device pci 18.0
+
+			device pci 18.1 on end		# K8 Address Map
+			device pci 18.2 on end		# K8 DRAM Controller and HT Trace Mode
+			device pci 18.3 on end		# K8 Miscellaneous Control
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,304 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+##
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses COREBOOT_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_USE_PRINTK_IN_CAR
+
+uses CONFIG_VIDEO_MB
+uses CONFIG_GFXUMA
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=524288
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from coreboot
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+default HAVE_ACPI_TABLES=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=0
+
+##
+## Move the default coreboot cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+
+default CONFIG_MAX_PHYSICAL_CPUS=1
+default CONFIG_LOGICAL_CPUS=1
+
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#1G memory hole
+default HW_MEM_HOLE_SIZEK=0x100000
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+# BTDC: Only one HT device on Herring.
+#HT Unit ID offset
+#default HT_CHAIN_UNITID_BASE=0x6
+default HT_CHAIN_UNITID_BASE=0x0
+
+
+#real SB Unit ID
+default HT_CHAIN_END_UNITID_BASE=0x1
+
+#make the SB HT chain on bus 0
+default SB_HT_CHAIN_ON_BUS0=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc8000
+default DCACHE_RAM_SIZE=0x8000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="pistachio"
+default MAINBOARD_VENDOR="amd"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
+
+
+###
+### coreboot layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+
+##
+## coreboot C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+default CONFIG_VIDEO_MB=1
+default CONFIG_GFXUMA=1
+
+### End Options.lb
+end

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/cpstate.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/cpstate.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/cpstate.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			Include ("cpstate.asl")
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			Include ("cpstate.asl")
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			Include ("cpstate.asl")
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			Include ("cpstate.asl")
+		}
+	}
+*/
+/*
+ * 1. Get the CPUID to know what the version of the CPU is. (or see what powernow
+ *     reports)
+ * 2. Find how many P-states the CPU supports, power and frequecy in each
+ *     P-states in 'Power and Thermal Data Sheet.' (PTDS)
+ * 3. Go to BIOS and Kernel Developer's Guide (BKDG) and find Low FID Frequency
+ *     Table & High FID Frequency Table. Find Fid for each frequency.
+ * 4. In PTDS, got the Voltage for each P-state. In table VID Code Voltages of BKDG,
+ *     find the VID for each Voltage.
+ *  Is that clear?
+ */
+
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	Name(_PSS, Package(){
+		/* The processor core clock PLL lock time is 2 us for AMD NPT Family 0Fh Processors.*/
+		/* vst=100us*/
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x13<<6|0xD, 0x13<<6|0xD */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x14<<6|0xC, 0x14<<6|0xC */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x15<<6|0xA, 0x15<<6|0xA */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x16<<6|0x8, 0x16<<6|0x8 */
+		/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x1E<<6|0x0, 0x1E<<6|0x0 */
+		/*
+		* Package() {2100, 35000, 100, 7, 0xE8202CCD, 0x04CD},
+		* Package() {2000, 30100, 100, 7, 0xE8202D0C, 0x050C},
+		* Package() {1800, 26400, 100, 7, 0xE8202D4A, 0x054A},
+		* Package() {1600, 23000, 100, 7, 0xE8202D88, 0x0588},
+		* Package() { 800,  9400, 100, 7, 0xE8202F80, 0x0780},
+		*/
+		/*Use this tricky method to reserve 8 Pstates space*/
+		Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
+		Package() {0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF},
+		Package() {0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF},
+		Package() {0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF},
+		Package() {0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF},
+		Package() {0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF},
+		Package() {0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF},
+		Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/debug.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/debug.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/debug.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+	DefinitionBlock (
+		"DSDT.AML",
+		"DSDT",
+		0x01,
+		"XXXXXX",
+		"XXXXXXXX",
+		0x00010001
+		)
+	{
+		Include ("debug.asl")
+	}
+*/
+
+/*
+* 0x80: POST_BASE
+* 0x3F8: DEBCOM_BASE
+* X80: POST_REGION
+* P80: PORT80
+*
+* CREG: DEBCOM_REGION
+* CUAR: DEBCOM_UART
+* CDAT: DEBCOM_DATA
+* CDLM: DEBCOM_DLM
+* DLCR: DEBCOM_LCR
+* CMCR: DEBCOM_MCR
+* CLSR: DEBCOM_LSR
+*
+* DEBUG_INIT	DINI
+*/
+
+OperationRegion(X80, SystemIO, 0x80, 1)
+	Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+	Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
+}
+
+/*
+* DINI
+* Initialize the COM port to 115,200 8-N-1
+*/
+Method(DINI)
+{
+	store(0x83, DLCR)
+	store(0x01, CDAT)	/* 115200 baud (low) */
+	store(0x00, CDLM)	/* 115200 baud (high) */
+	store(0x03, DLCR)	/* word=8 stop=1 parity=none */
+	store(0x03, CMCR)	/* DTR=1 RTS=1 Out2=Off Loop=Off */
+	store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/*
+* THRE
+* Wait for COM port transmitter holding register to go empty
+*/
+Method(THRE)
+{
+	and(CLSR, 0x20, local0)
+	while (Lequal(local0, Zero)) {
+		and(CLSR, 0x20, local0)
+	}
+}
+
+/*
+* OUTX
+* Send a single raw character
+*/
+Method(OUTX, 1)
+{
+	THRE()
+	store(Arg0, CDAT)
+}
+
+/*
+* OUTC
+* Send a single character, expanding LF into CR/LF
+*/
+Method(OUTC, 1)
+{
+	if (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/*
+* DBGN
+* Send a single hex nibble
+*/
+Method(DBGN, 1)
+{
+	and(Arg0, 0x0f, Local0)
+	if (LLess(Local0, 10)) {
+		add(Local0, 0x30, Local0)
+	} else {
+		add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/*
+* DBGB
+* Send a hex byte
+*/
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/*
+* DBGW
+* Send a hex word
+*/
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/*
+* DBGD
+* Send a hex Dword
+*/
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/*
+* DBGO
+* Send either a string or an integer
+*/
+Method(DBGO, 1)
+{
+	/* DINI() */
+	if (LEqual(ObjectType(Arg0), 1)) {
+		if (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} else {
+			if (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} else {
+				DBGB(Arg0)
+			}
+		}
+	} else {
+		Name(BDBG, Buffer(80) {})
+		store(Arg0, BDBG)
+		store(0, Local1)
+		while (One) {
+			store(GETC(BDBG, Local1), Local0)
+			if (LEqual(Local0, 0)) {
+				return (0)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+	return (0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	return (DBGC)
+}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/doit.sh
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/doit.sh	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/doit.sh	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,3 @@
+#!/bin/bash
+#cpp -P dsdt.asl > dsdt.i
+iasl dsdt.asl

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,1762 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x01,               	 /* DSDT Revision */
+	"AMD   ",               /* OEMID */
+	"PISTACHI",          /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* Include ("debug.asl") */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* Memory related values */
+	Name(TOM, 0x40000000)/* Top of RAM memory below 4GB */
+	Name(TOM2, 0x0)	/* Top of RAM memory above 4GB (>> 16) */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			Include ("cpstate.asl")
+		}
+	} /* End _PR scope */
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/* PIC IRQ mapping registers, C00h-C01h */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PINA, 0x00000008,	/* Index 0  */
+		PINB, 0x00000008,	/* Index 1 */
+		PINC, 0x00000008,	/* Index 2 */
+		PIND, 0x00000008,	/* Index 3 */
+		AINT, 0x00000008,	/* Index 4 */
+		SINT, 0x00000008,	/*  Index 5 */
+		, 0x00000008,	             /* Index 6 */
+		AAUD, 0x00000008,	/* Index 7 */
+		AMOD, 0x00000008,	/* Index 8 */
+		PINE, 0x00000008,	/* Index 9 */
+		PINF, 0x00000008,	/* Index A */
+		PING, 0x00000008,	/* Index B */
+		PINH, 0x00000008,	/* Index C */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			   * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			   * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00090024),	/* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve)
+			{
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+	Include ("routing.asl")
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+
+		Method(CIRQ, 0x00, NotSerialized)
+		{
+			Store(0, PINA)
+			Store(0, PINB)
+			Store(0, PINC)
+			Store(0, PIND)
+			Store(0, PINE)
+			Store(0, PINF)
+			Store(0, PING)
+			Store(0, PINH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PINA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PINA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PINB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PINB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PINC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PINC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIND) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIND)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIND, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIND)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PINE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PINE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PINF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PINF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PING) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PING)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PING, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PING)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PINH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PINH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			Notify (\_TZ.TZ00, 0x80)
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event */
+		Method(_L1A) {
+			/* DBGO("\\_GPE\\_L1A\n") */
+			Notify (\_SB.SLPB, 0x80)
+		}
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	Include ("usb.asl")
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		Include ("globutil.asl") /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00120000)
+				Include ("sata.asl")
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00130001)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130003)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00130004)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00130005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				Include ("ide.asl")
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* Resource source index */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/*  Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/*  Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+
+		Device (SLPB) {
+			Name (_HID, EisaId ("PNP0C0E"))
+			Name (_PRW, Package (0x02) {0x0F, 0x04})
+			Name (_STA, 0x0B)
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x18, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+
+		Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+
+		Store (0x1F, HSTS)
+		Store (Or (ShiftLeft (Arg1, One), One), HADD)
+		Store (Arg2, HCMD)
+		If (LEqual (Arg0, 0x07)) {
+			Store (0x48, HCNT) /* read byte */
+		}
+
+		Store (SWTC (0x03E8), Local1) /* 1000 ms */
+		If (LEqual (Local1, Zero)) {
+			If (LEqual (Arg0, 0x07)) {
+				Store (DAT0, Local0)
+			}
+		}
+		Else {
+			Store (Local1, Local0)
+		}
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 0x0AAC)
+		Name (THOT, 0x0384)
+		Name (TCRT, 0x03B6)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x2E,, 0x25), Local0)
+				If (LGreater (Local0, 0x20)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, 0x40, Local0)
+					Add (Local0, TCRT, Local0)
+					Return (Add (550, KELV))
+				}
+
+				/* Store (SMBR (0x07, 0x2E, 0x26), Local0)
+				 * If (LGreater (Local0, 0x20)) {
+				 *	If (LGreater (Local0, Local1)) {
+				 *		Store (Local0, Local1)
+				 *	}
+				 * }
+				 * Else {
+				 *	Add (Local0, 0x40, Local0)
+				 *	Add (Local0, TCRT, Local0)
+				 *	Return (Add (Local0, KELV))
+				 * }
+				 */
+
+				Store (SMBR (0x07, 0x2E, 0x27), Local0)
+				If (LGreater (Local0, 0x20)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Subtract (Local1, 0x40, Local1)
+					Multiply (Local1, 0x0A, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, 0x40, Local0)
+					Add (Local0, TCRT, Local0)
+					Return (Add (550 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+}
+/* End of ASL file */
+

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/globutil.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/globutil.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/globutil.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope(\_SB) {
+	Include ("globutil.asl")
+}
+*/
+
+/* string compare functions */
+Method(MIN, 2)
+{
+	if (LLess(Arg0, Arg1)) {
+		Return(Arg0)
+	} else {
+		Return(Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return(Sizeof(Local0))
+}
+
+Method(S2BF, 1)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return(BUFF)
+}
+
+/* Strong string compare.  Checks both length and content */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While(LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		if (LGreater(Local2, Local3)) {
+			Return(One)
+		} else {
+			if (LLess(Local2, Local3)) {
+				Return(Ones)
+			}
+		}
+		Increment(Local4)
+	}
+	if (LLess(Local4, Local5)) {
+		Return(One)
+	} else {
+		if (LLess(Local4, Local6)) {
+			Return(Ones)
+		} else {
+			Return(Zero)
+		}
+	}
+}
+
+/* Weak string compare.  Checks to find Arg1 at beginning of Arg0.
+* Fails if length(Arg0) < length(Arg1).  Returns 0 on Fail, 1 on
+* Pass.
+*/
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	if (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return(0)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While(LLess(Local2, Local3)) {
+		if (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return(0)
+		}
+		Increment(Local2)
+	}
+	Return(One)
+}
+
+/* ARG0 = IRQ Number(0-15)
+* Returns Bit Map
+*/
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	if (LNotEqual(ARG0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, ARG0, Local0)
+	}
+	Return(Local0)
+}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/ide.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/ide.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/ide.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			Include ("ide.asl")
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/routing.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/routing.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/routing.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		Include ("routing.asl")
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS690 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0012FFFF, 1, INTA, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0013FFFF, 0, INTA, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+		Package(){0x0013FFFF, 2, INTC, 0 },
+		Package(){0x0013FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS690 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Package(){0x0001FFFF, 0, 0, 18 }, */
+		/* package(){0x0001FFFF, 1, 0, 19 }, */
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0012FFFF, 0, 0, 22 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0013FFFF, 0, 0, 16 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		Package(){0x0013FFFF, 2, 0, 18 },
+		Package(){0x0013FFFF, 3, 0, 19 },
+		/* Package(){0x00130004, 2, 0, 18 }, */
+		/* Package(){0x00130005, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS690 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR1, Package(){
+		/* Internal graphics - RS690 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/sata.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/sata.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/sata.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00120000)
+			Include ("sata.asl")
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/statdef.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/statdef.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/statdef.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/* Status and notification definitions */
+
+#define STA_MISSING			    0x00
+#define STA_PRESENT			    0x01
+#define	STA_ENABLED			    0x03
+#define STA_DISABLED		    0x09
+#define	STA_INVISIBLE		    0x0B
+#define	STA_UNAVAILABLE		    0x0D
+#define	STA_VISIBLE			    0x0F
+
+/* SMBus status codes */
+#define SMB_OK                  0x00
+#define SMB_UnknownFail         0x07
+#define SMB_DevAddrNAK          0x10
+#define SMB_DeviceError         0x11
+#define SMB_DevCmdDenied        0x12
+#define SMB_UnknownErr          0x13
+#define SMB_DevAccDenied        0x17
+#define SMB_Timeout             0x18
+#define SMB_HstUnsuppProtocol   0x19
+#define SMB_Busy                0x1A
+#define SMB_PktChkError         0x1F
+
+/* Device Object Notification Values */
+#define	NOTIFY_BUS_CHECK		0x00
+#define	NOTIFY_DEVICE_CHECK		0x01
+#define	NOTIFY_DEVICE_WAKE		0x02
+#define	NOTIFY_EJECT_REQUEST	0x03
+#define	NOTIFY_DEVICE_CHECK_JR	0x04
+#define	NOTIFY_FREQUENCY_ERROR	0x05
+#define	NOTIFY_BUS_MODE			0x06
+#define	NOTIFY_POWER_FAULT		0x07
+#define	NOTIFY_CAPABILITIES		0x08
+#define	NOTIFY_PLD_CHECK		0x09
+#define	NOTIFY_SLIT_UPDATE		0x0B
+
+/* Battery Device Notification Values */
+#define	NOTIFY_BAT_STATUSCHG	0x80
+#define	NOTIFY_BAT_INFOCHG  	0x81
+#define	NOTIFY_BAT_MAINTDATA    0x82
+
+/* Power Source Object Notification Values */
+#define	NOTIFY_PWR_STATUSCHG	0x80
+
+/* Thermal Zone Object Notification Values */
+#define	NOTIFY_TZ_STATUSCHG	    0x80
+#define	NOTIFY_TZ_TRIPPTCHG	    0x81
+#define	NOTIFY_TZ_DEVLISTCHG	0x82
+#define	NOTIFY_TZ_RELTBLCHG 	0x83
+
+/* Power Button Notification Values */
+#define	NOTIFY_POWER_BUTTON		0x80
+
+/* Sleep Button Notification Values */
+#define	NOTIFY_SLEEP_BUTTON		0x80
+
+/* Lid Notification Values */
+#define	NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define	NOTIFY_CPU_PPCCHG   	0x80
+#define	NOTIFY_CPU_CSTATECHG  	0x81
+#define	NOTIFY_CPU_THROTLCHG    0x82
+
+/* User Presence Device Notification Values */
+#define	NOTIFY_USR_PRESNCECHG	0x80
+
+/* Battery Device Notification Values */
+#define	NOTIFY_ALS_ILLUMCHG 	0x80
+#define	NOTIFY_ALS_COLORTMPCHG 	0x81
+#define	NOTIFY_ALS_RESPCHG      0x82
+
+

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/usb.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/usb.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/usb.asl	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		Include ("usb.asl")
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+/*
+ * If (LLessEqual(UOM5,9)) {
+ *	Scope (\_GPE) {
+ *		Method (_L1A) {
+ *			UCOC()
+ *			if (LEqual(GPB5,PLC5)) {
+ *				Not(PLC5,PLC5)
+ *				Store(PLC5, \_SB.PT5D)
+ *			}
+ *		}
+ *	}
+ * }
+ */
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,755 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include <arch/cpu.h>
+
+#define DUMP_ACPI_TABLES 0
+
+/*
+* Assume the max pstate number is 8
+* 0x21(33 bytes) is one package length of _PSS package
+*/
+
+#define Maxpstate 8
+#define Defpkglength 0x21
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk_debug("\n%08x:", i);
+		}
+		printk_debug(" %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern u8 AmlCode[];
+extern u8 AmlCode_ssdt[];
+
+#if ACPI_SSDTX_NUM >= 1
+extern u8 AmlCode_ssdt2[];
+extern u8 AmlCode_ssdt3[];
+extern u8 AmlCode_ssdt4[];
+extern u8 AmlCode_ssdt5[];
+#endif
+
+#define IO_APIC_ADDR	0xfec00000UL
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB600 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+extern void get_bus_conf(void);
+
+extern void update_ssdt(void *ssdt);
+
+void update_ssdtx(void *ssdtx, int i)
+{
+	uint8_t *PCI;
+	uint8_t *HCIN;
+	uint8_t *UID;
+
+	PCI = ssdtx + 0x32;
+	HCIN = ssdtx + 0x39;
+	UID = ssdtx + 0x40;
+
+	if (i < 7) {
+		*PCI = (uint8_t) ('4' + i - 1);
+	} else {
+		*PCI = (uint8_t) ('A' + i - 1 - 6);
+	}
+	*HCIN = (uint8_t) i;
+	*UID = (uint8_t) (i + 3);
+
+	/* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
+/*
+* Details about this algorithm , refert to BDKG 10.5.1
+* Two parts are included, the another is the DSDT reconstruction process
+*/
+u32 pstates_algorithm(acpi_header_t * dsdt)
+{
+	u8 processor_brand[49];
+	u32 *v;
+	struct cpuid_result cpuid1;
+
+	typedef struct power_limit_encoding {
+		u8 socket_type;
+		u8 cmp_cap;
+		u8 pwr_lmt;
+		u32 power_limit;
+	};
+	u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
+	u16 Max_feq;
+	u8 Pstate_fid[10];
+	u16 Pstate_feq[10];
+	u8 Pstate_vid[10];
+	u32 Pstate_power[10];
+	u32 Pstate_volt[10];
+	u8 PstateStep, PstateStep_coef;
+	u8 IntPstateSup;
+	u8 Pstate_num;
+	u16 Cur_feq;
+	u8 Cur_fid;
+	u8 cmp_cap, pwr_lmt;
+	u32 power_limit = 0;
+	u8 index;
+	u32 i, j;
+	u32 processor_length, scope_length;
+	msr_t msr;
+	u8 *dsdt_pointer;
+	u8 *pointer1;
+	u8 *pointer2;
+	u8 byte_index;
+	u32 old_dsdt_length, new_dsdt_length;
+	u32 corefeq, power, transitionlatency, busmasterlatency, control,
+	    status;
+	u32 new_package_length;
+	u8 sum, checksum;
+	u32 fid_multiplier;
+	static struct power_limit_encoding TDP[20] = {
+		{0x11, 0x0, 0x8, 62},
+		{0x11, 0x1, 0x8, 89},
+		{0x11, 0x1, 0xa, 103},
+		{0x11, 0x1, 0xc, 125},
+		{0x11, 0x0, 0x2, 15},
+		{0x11, 0x0, 0x4, 35},
+		{0x11, 0x1, 0x2, 35},
+		{0x11, 0x0, 0x5, 45},
+		{0x11, 0x1, 0x7, 76},
+		{0x11, 0x1, 0x6, 65},
+		{0x11, 0x1, 0x8, 89},
+		{0x11, 0x0, 0x1, 8},
+		{0x11, 0x1, 0x1, 22},
+		{0x12, 0x0, 0x6, 25},
+		{0x12, 0x0, 0x1, 8},
+		{0x12, 0x0, 0x2, 9},
+		{0x12, 0x0, 0x4, 15},
+		{0x12, 0x0, 0xc, 35},
+		{0x12, 0x1, 0xc, 35},
+		{0x12, 0x1, 0x4, 20}
+	};
+
+	/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
+	cpuid1 = cpuid(0x80000002);
+	v = (u32 *) processor_brand;
+	v[0] = cpuid1.eax;
+	v[1] = cpuid1.ebx;
+	v[2] = cpuid1.ecx;
+	v[3] = cpuid1.edx;
+	cpuid1 = cpuid(0x80000003);
+	v[4] = cpuid1.eax;
+	v[5] = cpuid1.ebx;
+	v[6] = cpuid1.ecx;
+	v[7] = cpuid1.edx;
+	cpuid1 = cpuid(0x80000004);
+	v[8] = cpuid1.eax;
+	v[9] = cpuid1.ebx;
+	v[10] = cpuid1.ecx;
+	v[11] = cpuid1.edx;
+	processor_brand[48] = 0;
+	printk_info("processor_brand=%s\n", processor_brand);
+
+	/*
+	 * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
+	 * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
+	 * cmp_cap : 0x0 SingleCore ; 0x1 DualCore
+	 */
+	printk_info("Pstates Algorithm ...\n");
+	cmp_cap =
+	    (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
+	     0x3000) >> 12;
+	cpuid1 = cpuid(0x80000001);
+	pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
+	for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
+		if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
+		    TDP[index].cmp_cap == cmp_cap &&
+		    TDP[index].pwr_lmt == pwr_lmt) {
+			power_limit = TDP[index].power_limit;
+		}
+
+	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
+	cpuid1 = cpuid(0x80000007);
+	if ((cpuid1.edx & 0x6) != 0x6) {
+		printk_info("No valid set of P-states\n");
+		return 0;
+	}
+
+	msr = rdmsr(0xc0010042);
+	Max_fid = (msr.lo & 0x3F0000) >> 16;
+	Start_fid = (msr.lo & 0x3F00) >> 8;
+	Max_vid = (msr.hi & 0x3F0000) >> 16;
+	Start_vid = (msr.hi & 0x3F00) >> 8;
+	PstateStep = (msr.hi & 0x1000000) >> 24;
+	IntPstateSup = (msr.hi & 0x20000000) >> 29;
+
+	/*
+	 * The P1...P[Min+1] VID need PstateStep to calculate
+	 * P[N] = P[N-1]VID + 2^PstateStep
+	 * PstateStep_coef = 2^PstateStep
+	 */
+	if (PstateStep == 0)
+		PstateStep_coef = 1;
+	else
+		PstateStep_coef = 2;
+
+	if (IntPstateSup == 0) {
+		printk_info("No intermediate P-states are supported\n");
+		return 0;
+	}
+
+	/*get the multipier of the fid frequency */
+	/*
+	 * In RevG, 100MHz step is added
+	 */
+	cpuid1 = cpuid(0x80000007);
+	fid_multiplier = ((cpuid1.edx & 0x40) >> 6) * 100;
+
+	/*
+	 * Formula1:    CPUFreq = FID * fid_multiplier + 800
+	 * Formula2:       CPUVolt = 1550 - VID * 25 (mv)
+	 * Formula3:       Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
+	 */
+
+	/* Construct P0(P[Max]) state */
+	Pstate_num = 0;
+	Max_feq = Max_fid * fid_multiplier + 800;
+	if (Max_fid == 0x2A && Max_vid != 0x0) {
+		Min_fid = 0x2;
+		Pstate_fid[0] = Start_fid + 0xA;	/* Start Frequency + 1GHz */
+		Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
+		Min_vid = Start_vid;
+		Pstate_vid[0] = Max_vid + 0x2;	/* Maximum Voltage - 50mV */
+		Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
+		Pstate_power[0] = power_limit * 1000;	/* mw */
+		Pstate_num++;
+	} else {
+		Min_fid = Start_fid;
+		Pstate_fid[0] = Max_fid;
+		Pstate_feq[0] = Max_feq;
+		Min_vid = Start_vid;
+		Pstate_vid[0] = Max_vid + 0x2;
+		Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
+		Pstate_power[0] = power_limit * 1000;	/* mw */
+		Pstate_num++;
+	}
+
+	Cur_feq = Max_feq;
+	Cur_fid = Max_fid;
+	/* Construct P1 state */
+	if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) {	/* odd value */
+		Pstate_fid[1] = Max_fid - 0x1;
+		Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
+		Cur_fid = Pstate_fid[1];
+		Cur_feq = Pstate_feq[1];
+		if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* odd value */
+			Pstate_vid[1] = Pstate_vid[0] + 0x1;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+		if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* even value */
+			Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+		Pstate_num++;
+	}
+
+	if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) {	/* even value */
+		Pstate_fid[1] = Max_fid - 0x2;
+		Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
+		Cur_fid = Pstate_fid[1];
+		Cur_feq = Pstate_feq[1];
+		if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* odd value */
+			Pstate_vid[1] = Pstate_vid[0] + 0x1;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+		if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {	/* even value */
+			Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
+			Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
+			Pstate_power[1] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
+			    (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
+		}
+
+		Pstate_num++;
+	}
+
+	/* Construct P2...P[Min-1] state */
+	Cur_fid = Cur_fid - 0x2;
+	Cur_feq = Cur_fid * fid_multiplier + 800;
+	while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
+		Pstate_fid[Pstate_num] = Cur_fid;
+		Pstate_feq[Pstate_num] =
+		    Pstate_fid[Pstate_num] * fid_multiplier + 800;
+		Cur_fid = Cur_fid - 0x2;
+		Cur_feq = Cur_fid * fid_multiplier + 800;
+		if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
+			Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
+			Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
+			Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
+		} else {
+			Pstate_vid[Pstate_num] =
+			    Pstate_vid[Pstate_num - 1] + PstateStep_coef;
+			Pstate_volt[Pstate_num] =
+			    1550 - Pstate_vid[Pstate_num] * 25;
+			Pstate_power[Pstate_num] =
+			    (unsigned long long)Pstate_power[0] *
+			    Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
+			    Pstate_volt[Pstate_num] / (Pstate_feq[0] *
+						       Pstate_volt[0] *
+						       Pstate_volt[0]);
+		}
+		Pstate_num++;
+	}
+
+	/* Constuct P[Min] State */
+	if (Max_fid == 0x2A && Max_vid != 0x0) {
+		Pstate_fid[Pstate_num] = 0x2;
+		Pstate_feq[Pstate_num] =
+		    Pstate_fid[Pstate_num] * fid_multiplier + 800;
+		Pstate_vid[Pstate_num] = Min_vid;
+		Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
+		Pstate_power[Pstate_num] =
+		    (unsigned long long)Pstate_power[0] *
+		    Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
+		    Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
+					       Pstate_volt[0]);
+		Pstate_num++;
+	} else {
+		Pstate_fid[Pstate_num] = Start_fid;
+		Pstate_feq[Pstate_num] =
+		    Pstate_fid[Pstate_num] * fid_multiplier + 800;
+		Pstate_vid[Pstate_num] = Min_vid;
+		Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
+		Pstate_power[Pstate_num] =
+		    (unsigned long long)Pstate_power[0] *
+		    Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
+		    Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
+					       Pstate_volt[0]);
+		Pstate_num++;
+	}
+
+	/* Print Pstate feq,vid,volt,power */
+
+	for (index = 0; index < Pstate_num; index++) {
+		printk_info("Pstate_feq[%d] = %dMHz\t", index,
+			    Pstate_feq[index]);
+		printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
+		printk_info("Pstate_volt[%d] = %dmv\t", index,
+			    Pstate_volt[index]);
+		printk_info("Pstate_power[%d] = %dmw\n", index,
+			    Pstate_power[index]);
+	}
+
+	/*
+	 * Modify the DSDT Table to put the actural _PSS package
+	 * corefeq-->Pstate_feq[index] power-->Pstate_power[index] transitionlatency-->0x64 busmasterlatency-->0x7,
+	 * control-->0xE8202C00| Pstate_vid[index]<<6 | Pstate_fid[index]
+	 * status --> Pstate_vid[index]<<6 | Pstate_fid[index]
+	 * Get the _PSS control method Sig.
+	 */
+
+	dsdt_pointer = (u8 *) dsdt;
+	old_dsdt_length = dsdt->length;
+	new_dsdt_length = old_dsdt_length;
+	printk_info("DSDT reconstruction...\n");
+	for (i = 0x20; i < new_dsdt_length; i++)
+		if ((*(dsdt_pointer + i) == '_')
+		    && (*(dsdt_pointer + i + 1) == 'P')
+		    && (*(dsdt_pointer + i + 2) == 'S')
+		    && (*(dsdt_pointer + i + 3) == 'S')) {
+
+			if ((*(dsdt_pointer + i + 4) !=
+			     0x12) | (*(dsdt_pointer + i + 5) !=
+				      0x4B) | (*(dsdt_pointer + i + 6) !=
+					       0x10)) {
+				printk_info
+				    ("Error:No _PSS package leader byte!\n");
+			} else {
+				new_package_length =
+				    0x10B - Defpkglength * (Maxpstate -
+							    Pstate_num);
+				/* two Pstates length will larger than 63, so we need not worry about the length */
+				if (new_package_length > 63) {
+					*(dsdt_pointer + i + 5) =
+					    0x40 | (new_package_length & 0xf);
+					*(dsdt_pointer + i + 6) =
+					    (new_package_length & 0xff0) >> 4;
+				}
+				*(dsdt_pointer + i + 7) = Pstate_num;
+			}
+
+			if ((*(dsdt_pointer + i + 8) !=
+			     0x12) | (*(dsdt_pointer + i + 9) !=
+				      0x20) | (*(dsdt_pointer + i + 10) != 0x6))
+				printk_info
+				    ("Error:No package leader for the first Pstate!\n");
+			for (index = 0; index < Pstate_num; index++) {
+				corefeq = Pstate_feq[index];
+				power = Pstate_power[index];
+				transitionlatency = 0x64;
+				busmasterlatency = 0x7;
+				control =
+				    0xE8202C00 | (Pstate_vid[index] << 6) |
+				    Pstate_fid[index];
+				status =
+				    (Pstate_vid[index] << 6) |
+				    Pstate_fid[index];
+				for (byte_index = 0; byte_index < 4;
+				     byte_index++) {
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + byte_index) =
+		   corefeq >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 +
+					  byte_index) =
+		   power >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 2 +
+					  byte_index) =
+		   transitionlatency >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 3 +
+					  byte_index) =
+		   busmasterlatency >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 4 +
+					  byte_index) =
+		   control >> (8 * byte_index);
+					*(dsdt_pointer + i + 0xC +
+					  Defpkglength * index + 0x5 * 5 +
+					  byte_index) =
+		   status >> (8 * byte_index);
+				}
+			}
+			pointer1 =
+			    dsdt_pointer + i + 8 + Pstate_num * Defpkglength;
+			pointer2 =
+			    dsdt_pointer + i + 8 + Maxpstate * Defpkglength;
+			while (pointer2 < dsdt_pointer + new_dsdt_length) {
+				*pointer1 = *pointer2;
+				pointer1++;
+				pointer2++;
+			}
+			/* Recalcute the DSDT length */
+			new_dsdt_length =
+			    new_dsdt_length - Defpkglength * (Maxpstate -
+							      Pstate_num);
+
+			/* Search the first processor(CPUx) item and recalculate the processor length */
+			for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
+				if ((*(dsdt_pointer + i - j) == 'C')
+				    && (*(dsdt_pointer + i - j + 1) == 'P')
+				    && (*(dsdt_pointer + i - j + 2) == 'U')) {
+					processor_length =
+					    ((*(dsdt_pointer + i - j - 1) << 4)
+					     | (*(dsdt_pointer + i - j - 2) &
+						0xf));
+					processor_length =
+					    processor_length -
+					    Defpkglength * (Maxpstate -
+							    Pstate_num);
+					*(dsdt_pointer + i - j - 2) =
+					    (processor_length & 0xf) | 0x40;
+					*(dsdt_pointer + i - j - 1) =
+					    (processor_length & 0xff0) >> 4;
+					break;
+				}
+			}
+
+			/* Search the first scope(_PR_) item and recalculate the scope length */
+			for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
+				if ((*(dsdt_pointer + i - j) == '_')
+				    && (*(dsdt_pointer + i - j + 1) == 'P')
+				    && (*(dsdt_pointer + i - j + 2) == 'R')
+				    && (*(dsdt_pointer + i - j + 3) == '_')) {
+					scope_length =
+					    ((*(dsdt_pointer + i - j - 1) << 4)
+					     | (*(dsdt_pointer + i - j - 2) &
+						0xf));
+					scope_length =
+					    scope_length -
+					    Defpkglength * (Maxpstate -
+							    Pstate_num);
+					*(dsdt_pointer + i - j - 2) =
+					    (scope_length & 0xf) | 0x40;
+					*(dsdt_pointer + i - j - 1) =
+					    (scope_length & 0xff0) >> 4;
+					break;
+				}
+			}
+
+		}
+
+	/* Recalculate the DSDT length and fill back to the table */
+	*(dsdt_pointer + 0x4) = new_dsdt_length;
+	*(dsdt_pointer + 0x5) = new_dsdt_length >> 8;
+
+	/*
+	 * Recalculate the DSDT checksum and fill back to the table
+	 * We must make sure the sum of the whole table is 0
+	 */
+	sum = 0;
+	for (i = 0; i < new_dsdt_length; i++)
+		if (i != 9)
+			sum = sum + *(dsdt_pointer + i);
+	checksum = 0x100 - sum;
+	*(dsdt_pointer + 0x9) = checksum;
+
+	/*Check the DSDT Table */
+	/*
+	 * printk_info("The new DSDT table length is %x\n", new_dsdt_length);
+	 * printk_info("Details is as below:\n");
+	 * for(i=0; i< new_dsdt_length; i++){
+	 *      printk_info("%x\t",(unsigned char)*(dsdt_pointer+i));
+	 *      if( ((i+1)&0x7) == 0x0)
+	 *              printk_info("**0x%x**\n",i-7);
+	 *}
+	 */
+
+	return 1;
+
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf();		/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16byte */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk_debug("ACPI:    * HPET\n");
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdt, hpet);
+
+	printk_debug("ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdt, madt);
+
+#if 0
+	/* SRAT */
+	printk_debug("ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdt, srat);
+
+	/* SLIT */
+	printk_debug("ACPI:    * SLIT\n");
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdt, slit);
+#endif
+
+	/* SSDT */
+	printk_debug("ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *) current;
+	current += ((acpi_header_t *) AmlCode_ssdt)->length;
+	memcpy((void *)ssdt, (void *)AmlCode_ssdt,
+	       ((acpi_header_t *) AmlCode_ssdt)->length);
+	/* Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c */
+	update_ssdt((void *)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((u8 *)ssdt, ssdt->length);
+	acpi_add_table(rsdt, ssdt);
+
+#if ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
+
+	for (i = 1; i < sysconf.hc_possible_num; i++) {	/* 0: is hc sblink */
+		if ((sysconf.pci1234[i] & 1) != 1)
+			continue;
+		uint8_t c;
+		if (i < 7) {
+			c = (uint8_t) ('4' + i - 1);
+		} else {
+			c = (uint8_t) ('A' + i - 1 - 6);
+		}
+		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		current = (current + 0x07) & -0x08;
+		ssdtx = (acpi_header_t *) current;
+		switch (sysconf.hcid[i]) {
+		case 1:	/* 8132 */
+			p = AmlCode_ssdt2;
+			break;
+		case 2:	/* 8151 */
+			p = AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = AmlCode_ssdt5;
+			break;
+		}
+		current += ((acpi_header_t *) p)->length;
+		memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *) p)->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum =
+		    acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdt, ssdtx);
+	}
+#endif
+
+	/* FACS */
+	printk_debug("ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* DSDT */
+	printk_debug("ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy((void *)dsdt, (void *)AmlCode,
+	       ((acpi_header_t *) AmlCode)->length);
+	if (!pstates_algorithm(dsdt))
+		printk_debug("pstates_algorithm error!\n");
+	else
+		printk_debug("pstates_algorithm success.\n");
+
+	current += dsdt->length;
+	printk_debug("ACPI:    * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
+	/* FDAT */
+	printk_debug("ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdt, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+	printk_debug("rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk_debug("rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk_debug("madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk_debug("srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk_debug("slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk_debug("ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk_debug("fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk_info("ACPI: done.\n");
+	return current;
+}

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c	2008-12-09 21:52:42 UTC (rev 3808)
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define K8_SET_FIDVID 1
+#define QRANK_DIMM_SUPPORT 1
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+
+#define post_code(x) outb(x, 0x80)
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/ite/it8712f/it8712f_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#include "southbridge/amd/rs690/rs690_early_setup.c"
+#include "southbridge/amd/sb600/sb600_early_setup.c"
+
+/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+/* called in raminit_f.c */
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+/*called in raminit_f.c */
+static inline int spd_read_byte(u32 device, u32 address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "sdram/generic_sdram.c"
+#include "resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	/* Is this a cpu only reset? Is this a secondary cpu? */
+	if ((cpu_init_detectedx) || (!boot_cpu())) {
+		if (last_boot_normal()) {	/* RTC already inited */
+			goto normal_image;
+		} else {
+			goto fallback_image;
+		}
+	}
+	/* Nothing special needs to be done to find bus 0 */
+	/* Allow the HT devices to be found */
+	enumerate_ht_chain();
+
+	sb600_lpc_port80();
+	/* sb600_pci_port80(); */
+
+	/* Is this a deliberate reset by the bios */
+	if (bios_reset_detected() && last_boot_normal()) {
+		goto normal_image;
+	}
+	/* This is the primary cpu how should I boot? */
+	else if (do_normal_boot()) {
+		goto normal_image;
+	} else {
+		goto fallback_image;
+	}
+      normal_image:
+	post_code(0x01);
+	__asm__ volatile ("jmp __normal_image":	/* outputs */
+			  :"a" (bist), "b"(cpu_init_detectedx));	/* inputs */
+
+      fallback_image:
+	post_code(0x02);
+}
+#endif				/* USE_FALLBACK_IMAGE == 1 */
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);
+#endif
+	real_main(bist, cpu_init_detectedx);
+}
+
+void real_main(unsigned long bist, unsigned long cpu