[coreboot] qemu dts fixes

Myles Watson mylesgw at gmail.com
Wed Dec 3 15:34:31 CET 2008

> -----Original Message-----
> From: Marc Jones [mailto:marcj303 at gmail.com]
> Sent: Tuesday, December 02, 2008 8:06 PM
> To: Myles Watson
> Cc: jordan at cosmicpenguin.net; coreboot at coreboot.org
> Subject: Re: [coreboot] qemu dts fixes
> On Tue, Dec 2, 2008 at 10:57 AM, Myles Watson <mylesgw at gmail.com> wrote:
> >
> >
> > On Tue, Dec 2, 2008 at 7:13 AM, Myles Watson <mylesgw at gmail.com> wrote:
> >>
> >> Jordan,
> >>
> >> Sorry I obviously missed the point of your questions.  I'd forgotten
> that
> >> the fix went in to make all devices found in the dts be "on the
> mainboard."
> >> Here's a new patch that updates the dts with that in mind.  It also
> fixes
> >> the subsystem_vendor, which was broken in the last patch.
> >>
> >> I appreciate the sanity check.
> >
> > This patch is updated so that qemu works with resource allocation in
> phases.
> > Here are the changes:
> >
> > 1. Add a dts for the northbridge so it can have its own ops.
> > 2. Separates the domain from the device resource code.
> > 3. Add new resources for the APIC and VGA area.
> Move the IOAPIC to the the 82371? I'm not sure if the LAPIC belongs in
> the northbridge on since every core needs one it might belong in the
> CPU but I think you only need to reserve the range once.

I'm happy to put them wherever makes the most sense.  APICs are a black box
to me at this point.  I've never had to do much with them.

> On another note, Do you find the res-> size and res->limit redundant?
> I can't think of how they could be different.

I just set them both here for completeness.  In other resources they aren't
redundant, because the limit says how high it could go (usually 0xffff for
IO), but the base+size-1 is the end of the resource.


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