[coreboot] More v3 questions/issues
mylesgw at gmail.com
Mon Dec 15 18:24:56 CET 2008
On Sun, Dec 14, 2008 at 1:30 PM, Corey Osgood <corey.osgood at gmail.com>wrote:
> On Sun, Dec 14, 2008 at 2:23 AM, Corey Osgood <corey.osgood at gmail.com>wrote:
>> Alright, the good is that memtest boots now. The bad:
>> -Memtest thinks there's no memory, because...
>> -None of the cn700 stage2 drivers are running
>> -And any pci read/write operation in phase6 seems to lock up coreboot,
>> maybe because of a lack of memory?
>> I'm thinking the cn700 drivers are probably not running due to them not
>> having their own dts files or entries in the mainboard dts. If that's the
>> case, how do I represent d0f0, which acts as a PCI device, PCI domain, and
>> CPU bus controller, and needs drivers for all 3?
> I think I've figured it out, but it hangs during booting, boot log and
> patch attached. Also, I'm trying to add a driver for the c7 cpu, but I can't
> find the k8/geodelx stage2 make rules. And is the dts entry necessary?
Sorry I don't know that much about the cn700...
I'm looking through your log and diff, and it looks like the phase3_scan is
hanging when it finds the first device. Is there something that needs to be
enabled in the CPU before you can do a PCI config read? If so that needs to
get called first.
I saw that you moved something from phase6_init to phase2. I don't think
that's necessary. My understanding is that only things that are necessary
to enable basic things like bus reading and writing should go there.
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