[coreboot] More v3 questions/issues
corey.osgood at gmail.com
Thu Dec 18 05:04:08 CET 2008
On Wed, Dec 17, 2008 at 8:55 PM, Peter Stuge <peter at stuge.se> wrote:
> Corey Osgood wrote:
> > would there be any problem with calling functions to enable mtrrs
> > and the cache (if it's not already) from the end of disable_car()?
> None whatsoever. Commit at will.
It didn't help, disable_car() already does essentially the same thing;
disable cache, enable mtrrs, re-enable cache. I'm comparing memtest between
the stock bios and coreboot right now, the throughput for the stock bios is
6122MB/s for L1 cache and 574MB/s for memory. With v2, it's 3265 and 191,
respectively (using ROMCC), with v3 it's 15 and 18. So something's not right
somewhere. The other thing is that in v2 and v3, the CPU is only running at
800MHz in memtest, but with the stock BIOS it runs at 1.5GHz, that's
probably the reason for the differing cache throughputs. Anyways, I'm diving
into both v2 and v3 and trying to track down why this is running so slowly.
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