[coreboot] flashrom Asus A6T MCP51 PMC Pm49FL004
peter at stuge.se
Sun Dec 21 18:59:08 CET 2008
> 2008/12/21 Peter Stuge <peter at stuge.se>
> > The problem is quite likely that a GPIO pin of some chip is
> > connected to the two write protect pins on the flash chip.
> > You can run flashrom -V to show their status
As it turns out this doesn't apply for the Pm flash chips. But the
verify output was very helpful in confirming the guess.
> razor1394 at picon:~$ sudo flashrom -V -v backup.bin
> Verifying flash... address: 0x0006e079 FAILED! Expected=0x09, Read=0x94
Failure at that address means that the WP# pin is enabled, but it is
possible that also the TBL# pin is enabled. In order to make flashrom
run on this board you need to reverse engineer either the factory
BIOS board enable routine, or the PCB layout, to find out how to
control those two signals. You can use a continuity tester to find
out what is connected to pins 7 and 8 on the flash chip. (Look at the
data sheet for the chip pinout.) Two pins on the superio could be
used, but there's also a chance that the pins are driven by the
chipset, which can't be measured easily because of the BGA package.
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