[coreboot] Asus M2A-VM
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Tue Dec 23 04:51:28 CET 2008
On 17.12.2008 04:39, Carl-Daniel Hailfinger wrote:
> Hi all,
>
> my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
New status:
Working:
- memtest86 works for 2 GB RAM
- FILO works and loads a Linux kernel
- Linux boots
- SATA disks work under Linux
- Network works under Linux
- Power button works
- Software poweroff works
Untested:
- VGA analog/DVI because I have no monitor available right now
- USB (later)
- SeaBIOS
Probably not working, must retest:
- 4 GB RAM
Not working:
- SATA multicount transfers (detected as unsupported by Linux)
- Powernow ("invalid freq entries 1000000 kHz vs. 800000 kHz")
Patch against AMD DBM690T follows. Most parts of the patch (those for
generic code) have been submitted already.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Arbeitskopie)
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -175,8 +176,9 @@
/*
* About HT, it has been done in enumerate_ht_chain().
*/
- device_t k8_f0;
+ device_t k8_f0, rs690_f0;
u32 reg;
+ u8 reg8;
u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0);
@@ -195,7 +197,22 @@
************************/
reg = pci_read_config32(k8_f0, 0x88);
k8_ht_freq = (reg & 0xf00) >> 8;
- printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq);
+ printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+ rs690_f0 = PCI_DEV(0, 0, 0);
+ reg8 = pci_read_config8(rs690_f0, 0x9c);
+ printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+ /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
+ * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
+ */
+ if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
+ printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+ reg8 |= 0x1;
+ pci_write_config8(rs690_f0, 0x9c, reg8);
+ } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
+ printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+ reg8 &= ~0x1;
+ pci_write_config8(rs690_f0, 0x9c, reg8);
+ }
}
/*******************************************************
@@ -462,7 +479,6 @@
break;
}
- rs690_htinit();
k8_optimization();
rs690_por_init(nb_dev);
}
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c (Arbeitskopie)
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -26,6 +27,28 @@
#include <arch/io.h>
#include "sb600.h"
+int sata_drive_detect(int portnum, u16 iobar)
+{
+ u8 byte, byte2;
+ int i = 0;
+ outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
+ while (byte = inb(iobar + 0x6),
+ byte2 = inb(iobar + 0x7),
+ i++,
+ (byte != (0xA0 + 0x10 * (portnum % 2))) ||
+ ((byte2 & 0x88) != 0)) {
+ printk_spew("0x6=%x, 0x7=%x\n", byte, byte2);
+ if (byte != (0xA0 + 0x10 * (portnum % 2))) {
+ printk_debug("drive no longer selected after %i ms, retrying init\n", i * 10);
+ return 1;
+ } else
+ printk_spew("drive detection not yet completed, waiting...\n");
+ mdelay(10);
+ }
+ printk_spew("drive detection done after %i ms\n", i * 10);
+ return 0;
+}
+
static void sata_init(struct device *dev)
{
u8 byte;
@@ -33,6 +56,7 @@
u32 dword;
u8 *sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
+ int i;
struct southbridge_ati_sb600_config *conf;
conf = dev->chip_info;
@@ -62,12 +86,12 @@
sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7;
sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7;
- /* printk_debug("sata_bar0=%x\n", sata_bar0); */ /* 3030 */
- /* printk_debug("sata_bar1=%x\n", sata_bar1); */ /* 3070 */
- /* printk_debug("sata_bar2=%x\n", sata_bar2); */ /* 3040 */
- /* printk_debug("sata_bar3=%x\n", sata_bar3); */ /* 3080 */
- /* printk_debug("sata_bar4=%x\n", sata_bar4); */ /* 3000 */
- /* printk_debug("sata_bar5=%x\n", sata_bar5); */ /* e0309000 */
+ printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */
+ printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */
+ printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */
+ printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */
+ printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */
+ printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */
/* Program the 2C to 0x43801002 */
dword = 0x43801002;
@@ -136,26 +160,26 @@
byte |= 7 << 0;
pci_write_config8(dev, 0x4, byte);
- /* RPR6.6 SATA drive detection. Currently we detect Primary Master Device only */
- /* Use BAR5+0x1A8,BAR0+0x6 for Primary Slave */
- /* Use BAR5+0x228,BAR0+0x6 for Secondary Master */
- /* Use BAR5+0x2A8,BAR0+0x6 for Secondary Slave */
+ /* RPR6.6 SATA drive detection. */
+ /* Use BAR5+0x128,BAR0 for Primary Slave */
+ /* Use BAR5+0x1A8,BAR0 for Primary Slave */
+ /* Use BAR5+0x228,BAR2 for Secondary Master */
+ /* Use BAR5+0x2A8,BAR2 for Secondary Slave */
- byte = readb(sata_bar5 + 0x128);
- /* printk_debug("byte=%x\n", byte); */
- byte &= 0xF;
- if (byte == 0x3) {
- outb(0xA0, sata_bar0 + 0x6);
- while ((inb(sata_bar0 + 0x6) != 0xA0)
- || ((inb(sata_bar0 + 0x7) & 0x88) != 0)) {
- mdelay(10);
- /* printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
- inb(sata_bar0 + 0x7)); */
- printk_debug("drive detection fail,trying...\n");
+ for (i = 0; i < 4; i++) {
+ byte = readb(sata_bar5 + 0x128 + 0x80 * i);
+ printk_spew("SATA port %i status = %x\n", i, byte);
+ byte &= 0xF;
+ if (byte == 0x3) {
+ while (sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2));
+ printk_debug("%s %s device is ready\n",
+ (i / 2) ? "Secondary" : "Primary",
+ (i % 2 ) ? "Slave" : "Master");
+ } else {
+ printk_debug("No %s %s SATA drive on Slot%i\n",
+ (i / 2) ? "Secondary" : "Primary",
+ (i % 2 ) ? "Slave" : "Master", i);
}
- printk_debug("Primary master device is ready\n");
- } else {
- printk_debug("No Primary master SATA drive on Slot0\n");
}
/* Below is CIM InitSataLateFar */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/acpi_tables.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/acpi_tables.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/acpi_tables.c (Arbeitskopie)
@@ -133,7 +133,7 @@
u32 *v;
struct cpuid_result cpuid1;
- typedef struct power_limit_encoding {
+ struct power_limit_encoding {
u8 socket_type;
u8 cmp_cap;
u8 pwr_lmt;
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/cache_as_ram_auto.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/cache_as_ram_auto.c (Arbeitskopie)
@@ -213,6 +213,7 @@
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ rs690_htinit();
printk_debug("needs_reset=0x%x\n", needs_reset);
post_code(0x06);
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/fadt.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/fadt.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/fadt.c (Arbeitskopie)
@@ -25,6 +25,8 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/device.h>
+#include <../southbridge/amd/sb600/sb600.h>
/*extern*/ u16 pm_base = 0x800;
/* pm_base should be set in sb acpi */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Arbeitskopie)
@@ -198,7 +198,7 @@
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
- chip cpu/amd/socket_S1G1
+ chip cpu/amd/socket_AM2
device apic 0 on end
end
end
@@ -214,8 +214,8 @@
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P bridge 0x791b
- device pci 4.0 on end # PCIE P2P bridge 0x1914
+ #device pci 3.0 off end # PCIE P2P bridge 0x791b
+ device pci 4.0 on end # PCIE P2P bridge 0x7914
device pci 5.0 on end # PCIE P2P bridge 0x7915
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Options.lb (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Options.lb (Arbeitskopie)
@@ -290,9 +290,9 @@
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default DEFAULT_CONSOLE_LOGLEVEL=9
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default MAXIMUM_CONSOLE_LOGLEVEL=9
##
## Select power on after power fail setting
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi_tables.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi_tables.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi_tables.c (Arbeitskopie)
@@ -133,7 +133,7 @@
u32 *v;
struct cpuid_result cpuid1;
- typedef struct power_limit_encoding {
+ struct power_limit_encoding {
u8 socket_type;
u8 cmp_cap;
u8 pwr_lmt;
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie)
@@ -25,6 +25,7 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
+#include <../southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
@@ -34,6 +35,8 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
+extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
+ uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie)
@@ -210,6 +210,7 @@
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ rs690_htinit();
printk_debug("needs_reset=0x%x\n", needs_reset);
Index: LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb (Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb (Arbeitskopie)
@@ -7,6 +7,9 @@
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
__COMPRESSION__
option ROM_SIZE=1024*1024
--
http://www.hailfinger.org/
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