[coreboot] v3 stage2 running from flash

Corey Osgood corey.osgood at gmail.com
Wed Dec 24 12:25:22 CET 2008

On Wed, Dec 24, 2008 at 5:20 AM, Corey Osgood <corey.osgood at gmail.com>wrote:

> On Wed, Dec 24, 2008 at 5:09 AM, ron minnich <rminnich at gmail.com> wrote:
>> On Wed, Dec 24, 2008 at 12:14 AM, Corey Osgood <corey.osgood at gmail.com>
>> wrote:
>> > *phew* I was worried that was how v3 was always going to run. As for
>> those
>> > times Ron, stage0 takes <1 second, initram is ~5 seconds,
>> the initram seems way too long. But that stage 2 tells me you have
>> some real problems with your dram setup.
> It could have been less, timing output from a serial port with a stopwatch
> isn't very exact. I don't think there's anything wrong with the dram setup,
> I ran memtest86 overnight without any errors.
> I know nothing about this part. I wonder if you could dump your mtrr
>> settings and let us see them.
> Sure, what point do you want them from? End of stage1?

Here's a boot log that dumps them right after serial comes up, again just
before disable_car(), and once more before loading stage2. After that mtrrs
aren't touched until stage 2 phase 6 AFAIK. I wish I knew more about this
stuff, I should probably make some time to read those Intel x86 programming

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