[coreboot] [PATCH] Fix flashrom init for VT8237S
FENG Yu Ning
fengyuning1984 at gmail.com
Sat Dec 27 13:31:45 CET 2008
On Sat, Dec 27, 2008 at 1:24 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
> Yes or we can ignore the pre op in ich code. Because then another command
> will be find in the table (assuming that it will always need a pre-op - is
> this true?)
I have only investegated few SPI flash chips. For SST25 series, WREN
is required before every time a write/erase command is to be sent.
There are other people here who is familiar with much more chips than
me. Carl-Daniel, can you help answer Rudolf's question?
> The WREN pre op is defined in JEDEC somewhere to be atomic?
> Any pointers to docs?
There are atomicity issues in ICHx because they can share flash chips
for BIOS and some on-board network controllers. Therefore I don't
think JEDEC document will mention it. (Very appreciated if anyone
familiar with JEDEC standard can help.) I have not read about
atomicity issues in flash chip datasheets, only in ICH specs.
More information about the coreboot