[coreboot] r1091 - coreboot-v3/southbridge/amd/cs5536

svn at coreboot.org svn at coreboot.org
Wed Dec 31 20:56:11 CET 2008


Author: myles
Date: 2008-12-31 20:56:11 +0100 (Wed, 31 Dec 2008)
New Revision: 1091

Modified:
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
Log:
patch: geodelx.diff

	This patch fixes up geode for the new resource allocator.  This is the
bare minimum.  I think the functions of the northbridge should be split based
on whether they are domain-specific or not.

southbridge/amd/cs5536/cs5536.c:
	Change read resources to add a fixed IO resource for legacy decoding.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-12-31 19:46:14 UTC (rev 1090)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c	2008-12-31 19:56:11 UTC (rev 1091)
@@ -676,6 +676,25 @@
 }
 
 /**
+ * A slightly different read resources.  We add fixed resources.
+ *
+ * @param dev The device to use.
+ */
+static void cs5536_read_resources(struct device *dev)
+{
+	/* This is a fixed IO resource for legacy decoding.  Its presence moves
+	 * other allocations out of this location. */
+	struct resource *res;
+	res = new_resource(dev, 0);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		     IORESOURCE_STORED;
+
+	pci_dev_read_resources(dev);
+}
+
+/**
  * A slightly different enable resources than the standard.
  * We grab control here as VSA has played in this chip as well.
  *
@@ -695,7 +714,7 @@
 			 .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
-	.phase4_read_resources	 = pci_dev_read_resources,
+	.phase4_read_resources	 = cs5536_read_resources,
 	.phase4_set_resources	 = pci_set_resources,
 	.phase5_enable_resources = cs5536_pci_dev_enable_resources,
 	.phase6_init		 = southbridge_init,
@@ -706,7 +725,6 @@
 		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
 			 .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}},
 	.constructor		 = default_device_constructor,
-#warning FIXME: what has to go in phase3_scan?
 	.phase3_scan		 = 0,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_set_resources,





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