[coreboot] [PATCH] (resend2) fix the flashrom problem on m57sli boards with SPI flash

Florentin Demetrescu echelon at free.fr
Sat Feb 2 00:38:35 CET 2008


It rocks!..
Now after taking a little break (1-2 weeks), I will begin to tackle the problems
of ACPI and/or the incorrect init of IRQs on lagacy PCI slots on this board..
(which one is most urgent?) This is my roadmap for the short-term..
For the long term, Id like to contribute to the porting of coreboot-v3 on this
board.. (but firstly, I have to familiarize myself with the coreboot-v3
architecture..)

Florentin

Quoting Ward Vandewege <ward at gnu.org>:

> On Thu, Jan 31, 2008 at 03:01:51AM +0100, Florentin Demetrescu wrote:
> >  This patch fixes the decoding of the IO address range 0x0820->0x0827 into
> the
> > LPC device of the MCP55 southbridge, thus enabling flashrom access to the
> SPI
> > interface of the IT8716 SIO chip.
> >  Changes :
> >   1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because
> some
> > functions of a PNP device can have more than 12 resources (ex the GPIO
> function
> > of IT8716f), in which case one could have an "array overflow" inside the
> device
> > structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
> > device init time..)
> >   2) - define resource masks for the GPIO function in
> > src/superio/ite/it8716f/superio.c -> this is needed because otherwise the
> IO
> > ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
> > 0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for
> the
> > GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid
> mismatching
> > by the init code
> >   3) - enable the flash SPI interface into
> > src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding
> resource
> > into the GPIO function). I know that this is problematic because not all
> m57sli
> > boards are SPI, but .. do anyone have a better idea how to handle this?..
>
> I have verified your patch on a v2 of this board (it works!) as well as on a
> v1 (plcc). It does not affect flashing on v1 nor have any averse side effects
> that I noticed, so I think this patch should go in.
>
> >  Signed-off-by: Florentin Demetrescu <echelon at free.fr>
> Acked-by: Ward Vandewege <ward at gnu.org>
>
> If nobody objects I will commit this later tonight or tomorrow.
>
> Thanks a lot!
> Ward.
>
> --
> Ward Vandewege <ward at fsf.org>
> Free Software Foundation - Senior System Administrator
>






More information about the coreboot mailing list