[coreboot] VIA EPIA CN100000 is finally Working all.

[Urbez Santana Roma]

Finally works, my mainboard complete, with the IDE +dma, network, usb,
etc...

I must only add the same that y have commented in my last email, for
working the access of IDE , network, etc.

Mainboard: VIA EPIA CN10000.
Chipsets: VT8237 and CN700
Cpu: C7 
Ram: 512MB DDR2 KVR533D2N4
Linux Kernel: 2.6.22

1. Make a clone of the last posted code for CN700/C7 jetway mainboard of
Corey Osgood, for your mainboard.

2. Set to 1 the 20 bit in the function sdram_enable() to all MRS RAM
Commands. If not, the Kingstom
Memory not initiates correctly.

3. comment the call to the function disable_sata(), if not, your normal
ide not appears in the PCI config space.

4. Add the follow code to the end of the function main() in auto.c: if
not, your normal IDE cannot use DMA and via-rhine, usb's, etc, not
works.
	
        //This enable the access of PCI devices to the PCI bus master?
        pci_write_config8(cn700->d0f7, 0x57, 0x20);//was 0x01

5. If you will that the FILO not confuses scanning PCI, you must add, to
the end of main() in auto.c:

    pci_write_config8(cn700->d1f0,0x19,0x1,CF8);//enable PCI-BRIGDE
SECONDARY BUS
    pci_write_config8(cn700->d1f0,0x1a,0x1,CF8);
 
6. If you want that your BIOS, runs at the maximum CPU speed, in my
case, the CPU starts
with 800MHz, and i needed in the bios that works with 1000MHz. You can
add this if u will:

#define MSR_IA32_PERF_STATUS                    0x00000198
#define MSR_IA32_PERF_CTL                       0x00000199
#define MSR_IA32_MISC_ENABLE                    0x000001a0

        msr_t msr;
        print_debug("Enabling C7 Power Save\r\n");
        msr=rdmsr(MSR_IA32_MISC_ENABLE);
        if (!(msr.lo & 0x10000)) {msr.lo|
0x10000;wrmsr(MSR_IA32_MISC_ENABLE,msr);
        msr=rdmsr(MSR_IA32_PERF_STATUS);
        //TODO: wait CPU not busy bit 16 & 17 off (STATUS)
        wrmsr(MSR_IA32_PERF_CTL, 0,  (hi&0xff00)| ((hi>>16)&0x00ff));
        //Max multi Factor, and minimum voltage
        //TODO: wait CPU transition bit 16 & 17 off (STATUS)

7. If you will, you can generate your fadt.c and dsdt.c with the genfadt
and gendsdt tool, or generate one new.
       
8. Force the ACPI in the kernel if not uses it with acpi=force

9. If you want that your kernel recognises lapic, you must change the
kernel driver, for not ignore
another Vendors differs of AMD and Intel, in the function "static int
__init detect_init_APIC (void)" of the file ./arch/i386/kernel/apic.c

End.