[coreboot] patch: init gx cache earlier.

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Tue Feb 5 13:00:33 CET 2008

On 05.02.2008 07:31, ron minnich wrote:
> I think this is fine but I'd like to fit it into the "stage"
> nomenclature, so the numbering fits.
> So which stage is this? I am not sure, I feel like the stage numbering
> never quite got finished :-)
> possibly stage 3 is load payload, stage 4 is prepare the machine for a
> payload, and stage5 is run the payload?

Remember that we load stage 2 like a payload, so we'd have execution
order stage 0,1,3,4,5,2,3,4,5,realpayload. Stage 2 is also special
because it lives completely in RAM, but it calls a lot of functions in
bootblock ROM. If we shadow the boot block, most problems should disappear.

One thing I didn't understand:
Marc Jones wrote:
> Due to some cache coherency snoop problems across pci we need the ROM
> cache properties to be write-serialize + cache disabled. 

The data in ROM doesn't change nor do we write to it. So where exactly
do we need write snooping and/or write-serialize?



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