[coreboot] r608 - coreboot-v3/northbridge/amd/geodelx

[svn at coreboot.org]

Author: mjones
Date: 2008-02-18 17:37:58 +0100 (Mon, 18 Feb 2008)
New Revision: 608

Modified:
   coreboot-v3/northbridge/amd/geodelx/geodelx.c
Log:
Remove dead Geode defines.

Signed-off-by: Marc Jones <marc.jones at amd.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c	2008-02-18 01:43:50 UTC (rev 607)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c	2008-02-18 16:37:58 UTC (rev 608)
@@ -32,115 +32,7 @@
 extern void northbridge_init_early(void);
 extern void setup_realmode_idt(void);
 
-/* Here is programming for the various MSRs. */
-#define IM_QWAIT 0x100000
 
-/* Set in high nibble. */
-#define DMCF_WRITE_SERIALIZE_REQUEST	(2 << 12)	/* 2 outstanding */
-
-#define DMCF_SERIAL_LOAD_MISSES		2		/* Enabled */
-
-/* These are the 8-bit attributes for controlling RCONF registers.
- *
- * RCONF is Region CONFiguration, and controls caching and other
- * attributes of a region. Just like MTRRs, only different.
- */
-#define CACHE_DISABLE		(1 << 0)
-#define WRITE_ALLOCATE		(1 << 1)
-#define WRITE_PROTECT		(1 << 2)
-#define WRITE_THROUGH		(1 << 3)
-#define WRITE_COMBINE		(1 << 4)
-#define WRITE_SERIALIZE		(1 << 5)
-
-/* RAM has none of this stuff. */
-#define RAM_PROPERTIES		0
-#define DEVICE_PROPERTIES	(WRITE_SERIALIZE|CACHE_DISABLE)
-#define ROM_PROPERTIES		(WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
-#define MSR_WS_CD_DEFAULT	0x21212121
-
-/* RCONF registers 1810-1817 give you 8 registers with which to
- * program protection regions the are region configuration range
- * registers, or RRCF in msr terms, the are a straight base, top
- * address assign, since they are 4k aligned.
- */
-/* So no left-shift needed for top or base. */
-#define RRCF_LOW(base, properties)	(base | (1 << 8) | properties)
-#define RRCF_LOW_CD(base)		RRCF_LOW(base, CACHE_DISABLE)
-
-/* Build initializer for P2D MSR.
- *
- * This is complex enough that you are going to need to RTFM if you
- * really want to understand it.
- */
-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \
-		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pbase >> 24), \
-		       .lo = (pbase << 8) | pmask}}
-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \
-		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \
-			     (poffset << 8) | (pbase >> 24), \
-		       .lo = (pbase << 8) | pmask}}
-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \
-		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (pmax >> 12), \
-		       .lo = (pmax << 20) | pmin}}
-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \
-		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | \
-			     (poffset << 8) | (pmax >> 12), \
-		       .lo = (pmax << 20) | pmin}}
-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \
-		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (wen), \
-		       .lo = (ren << 16) | (pscbase >> 18)}}
-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \
-		{msr, {.hi = (pdid1 << 29) | (bizarro << 28) | (ibase >> 12), \
-		       .lo = (ibase << 20) | imask}}
-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \
-		{msr, {.hi = (pdid1 << 29) | (bizarro << 28), \
-		       .lo = (en << 24) | (wen << 21) | \
-			     (ren << 20) | (ibase << 3)}}
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-/* TODO: Not used!? */
-static const struct msrinit msr_defaults[] = {
-	{ 0x1700, {.hi = 0,.lo = IM_QWAIT}},
-	{ 0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST,
-		   .lo = DMCF_SERIAL_LOAD_MISSES}},
-
-	/* 1808 will be done down below, so we have to do 180a->1817
-	 * (well, 1813 really).
-	 */
-	/* For 180a, for now, we assume VSM will configure it. */
-	/* 180b is left at reset value, a0000-bffff is non-cacheable. */
-	/* 180c, c0000-dffff is set to write serialize and non-cachable. */
-	/* Oops, 180c will be set by CPU bug handling in cpubug.c. */
-	/* TODO: There's no cpubug.c. */
-	// {0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
-	/* 180d is left at default, e0000-fffff is non-cached. */
-	/* We will assume 180e, the ssm region configuration, is left
-	 * at default or set by VSM.
-	 */
-	/* We will not set 0x180f, the DMM, yet. */
-
-	// {0x1810, {.hi = 0xee7ff000,
-	// 	     .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
-	// {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
-	// {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
-	// {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
-
-	/* Now for GLPCI routing. */
-
-	/* GLIU0 */
-	P2D_BM(MSR_GLIU0_BASE1,  0x1, 0x0, 0x0, 0xfff80),
-	P2D_BM(MSR_GLIU0_BASE2,  0x1, 0x0, 0x80000, 0xfffe0),
-	P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
-
-	/* GLIU1 */
-	P2D_BM(MSR_GLIU1_BASE1,  0x1, 0x0, 0x0, 0xfff80),
-	P2D_BM(MSR_GLIU1_BASE2,  0x1, 0x0, 0x80000, 0xfffe0),
-	P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
-
-	{0},
-};
-
 /**
  * Currently not set up.
  *