[coreboot] r3107 - trunk/coreboot-v2/src/mainboard/asus/a8v-e_se
svn at coreboot.org
svn at coreboot.org
Mon Feb 18 21:40:03 CET 2008
Author: ruik
Date: 2008-02-18 21:40:02 +0100 (Mon, 18 Feb 2008)
New Revision: 3107
Modified:
trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
Log:
Attached patch fixes two typos in the sio_setup routine (comment + wrong exitLDN
device) and sets the chipset voltage from 1.6V to 1.5V.
Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2008-02-18 20:37:49 UTC (rev 3106)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2008-02-18 20:40:02 UTC (rev 3107)
@@ -182,16 +182,15 @@
pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
- pnp_exit_ext_func_mode(GPIO_DEV);
-
+
/* set memory voltage to 2.75V, vcore offset + 100mV, 1.5V Chipset voltage */
- pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101110 0=output 1=input */
- pnp_write_config(GPIO_DEV, 0xe1, 0x1); /* set output val */
+ pnp_write_config(GPIO_DEV, 0x30, 0x9); /* Enable GPIO 2 & GPIO 5 */
pnp_write_config(GPIO_DEV, 0xe2, 0x0); /* no inversion */
- pnp_write_config(GPIO_DEV, 0xe3, 0x3); /* 0000 0011 0=output 1=input */
- pnp_write_config(GPIO_DEV, 0xe4, 0xa4); /* set output val 1010 0100 */
pnp_write_config(GPIO_DEV, 0xe5, 0x0); /* no inversion */
- pnp_write_config(GPIO_DEV, 0x30, 0x9); /* Enable GPIO 2 & GPIO 5 */
+ pnp_write_config(GPIO_DEV, 0xe3, 0x3); /* 0000 0011 0=output 1=input */
+ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101110 0=output 1=input */
+ pnp_write_config(GPIO_DEV, 0xe1, 0x1); /* set output val */
+ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* set output val 1011 0100 */
pnp_exit_ext_func_mode(GPIO_DEV);
}
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